1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright (c) Microsoft Corporation.
4	*
5	* Author:
6	* Jake Oshins <jakeo@microsoft.com>
7	*
8	* This driver acts as a paravirtual front-end for PCI Express root buses.
9	* When a PCI Express function (either an entire device or an SR-IOV
10	* Virtual Function) is being passed through to the VM, this driver exposes
11	* a new bus to the guest VM. This is modeled as a root PCI bus because
12	* no bridges are being exposed to the VM. In fact, with a "Generation 2"
13	* VM within Hyper-V, there may seem to be no PCI bus at all in the VM
14	* until a device as been exposed using this driver.
15	*
16	* Each root PCI bus has its own PCI domain, which is called "Segment" in
17	* the PCI Firmware Specifications. Thus while each device passed through
18	* to the VM using this front-end will appear at "device 0", the domain will
19	* be unique. Typically, each bus will have one PCI function on it, though
20	* this driver does support more than one.
21	*
22	* In order to map the interrupts from the device through to the guest VM,
23	* this driver also implements an IRQ Domain, which handles interrupts (either
24	* MSI or MSI-X) associated with the functions on the bus. As interrupts are
25	* set up, torn down, or reaffined, this driver communicates with the
26	* underlying hypervisor to adjust the mappings in the I/O MMU so that each
27	* interrupt will be delivered to the correct virtual processor at the right
28	* vector. This driver does not support level-triggered (line-based)
29	* interrupts, and will report that the Interrupt Line register in the
30	* function's configuration space is zero.
31	*
32	* The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
33	* facilities. For instance, the configuration space of a function exposed
34	* by Hyper-V is mapped into a single page of memory space, and the
35	* read and write handlers for config space must be aware of this mechanism.
36	* Similarly, device setup and teardown involves messages sent to and from
37	* the PCI back-end driver in Hyper-V.
38	*/
39
40	#include <linux/kernel.h>
41	#include <linux/module.h>
42	#include <linux/pci.h>
43	#include <linux/pci-ecam.h>
44	#include <linux/delay.h>
45	#include <linux/semaphore.h>
46	#include <linux/irq.h>
47	#include <linux/msi.h>
48	#include <linux/hyperv.h>
49	#include <linux/refcount.h>
50	#include <linux/irqdomain.h>
51	#include <linux/acpi.h>
52	#include <linux/sizes.h>
53	#include <linux/of_irq.h>
54	#include <asm/mshyperv.h>
55
56	/*
57	* Protocol versions. The low word is the minor version, the high word the
58	* major version.
59	*/
60
61	#define PCI_MAKE_VERSION(major, minor) ((u32)(((major) << 16) | (minor)))
62	#define PCI_MAJOR_VERSION(version) ((u32)(version) >> 16)
63	#define PCI_MINOR_VERSION(version) ((u32)(version) & 0xff)
64
65	enum pci_protocol_version_t {
66	PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1), /* Win10 */
67	PCI_PROTOCOL_VERSION_1_2 = PCI_MAKE_VERSION(1, 2), /* RS1 */
68	PCI_PROTOCOL_VERSION_1_3 = PCI_MAKE_VERSION(1, 3), /* Vibranium */
69	PCI_PROTOCOL_VERSION_1_4 = PCI_MAKE_VERSION(1, 4), /* WS2022 */
70	};
71
72	#define CPU_AFFINITY_ALL -1ULL
73
74	/*
75	* Supported protocol versions in the order of probing - highest go
76	* first.
77	*/
78	static enum pci_protocol_version_t pci_protocol_versions[] = {
79	PCI_PROTOCOL_VERSION_1_4,
80	PCI_PROTOCOL_VERSION_1_3,
81	PCI_PROTOCOL_VERSION_1_2,
82	PCI_PROTOCOL_VERSION_1_1,
83	};
84
85	#define PCI_CONFIG_MMIO_LENGTH 0x2000
86	#define CFG_PAGE_OFFSET 0x1000
87	#define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
88
89	#define MAX_SUPPORTED_MSI_MESSAGES 0x400
90
91	#define STATUS_REVISION_MISMATCH 0xC0000059
92
93	/* space for 32bit serial number as string */
94	#define SLOT_NAME_SIZE 11
95
96	/*
97	* Size of requestor for VMbus; the value is based on the observation
98	* that having more than one request outstanding is 'rare', and so 64
99	* should be generous in ensuring that we don't ever run out.
100	*/
101	#define HV_PCI_RQSTOR_SIZE 64
102
103	/*
104	* Message Types
105	*/
106
107	enum pci_message_type {
108	/*
109	* Version 1.1
110	*/
111	PCI_MESSAGE_BASE = 0x42490000,
112	PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
113	PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
114	PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
115	PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
116	PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
117	PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
118	PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
119	PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
120	PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
121	PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
122	PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
123	PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
124	PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
125	PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
126	PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
127	PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
128	PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
129	PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
130	PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
131	PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
132	PCI_RESOURCES_ASSIGNED2 = PCI_MESSAGE_BASE + 0x16,
133	PCI_CREATE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x17,
134	PCI_DELETE_INTERRUPT_MESSAGE2 = PCI_MESSAGE_BASE + 0x18, /* unused */
135	PCI_BUS_RELATIONS2 = PCI_MESSAGE_BASE + 0x19,
136	PCI_RESOURCES_ASSIGNED3 = PCI_MESSAGE_BASE + 0x1A,
137	PCI_CREATE_INTERRUPT_MESSAGE3 = PCI_MESSAGE_BASE + 0x1B,
138	PCI_MESSAGE_MAXIMUM
139	};
140
141	/*
142	* Structures defining the virtual PCI Express protocol.
143	*/
144
145	union pci_version {
146	struct {
147	u16 minor_version;
148	u16 major_version;
149	} parts;
150	u32 version;
151	} __packed;
152
153	/*
154	* Function numbers are 8-bits wide on Express, as interpreted through ARI,
155	* which is all this driver does. This representation is the one used in
156	* Windows, which is what is expected when sending this back and forth with
157	* the Hyper-V parent partition.
158	*/
159	union win_slot_encoding {
160	struct {
161	u32 dev:5;
162	u32 func:3;
163	u32 reserved:24;
164	} bits;
165	u32 slot;
166	} __packed;
167
168	/*
169	* Pretty much as defined in the PCI Specifications.
170	*/
171	struct pci_function_description {
172	u16 v_id; /* vendor ID */
173	u16 d_id; /* device ID */
174	u8 rev;
175	u8 prog_intf;
176	u8 subclass;
177	u8 base_class;
178	u32 subsystem_id;
179	union win_slot_encoding win_slot;
180	u32 ser; /* serial number */
181	} __packed;
182
183	enum pci_device_description_flags {
184	HV_PCI_DEVICE_FLAG_NONE = 0x0,
185	HV_PCI_DEVICE_FLAG_NUMA_AFFINITY = 0x1,
186	};
187
188	struct pci_function_description2 {
189	u16 v_id; /* vendor ID */
190	u16 d_id; /* device ID */
191	u8 rev;
192	u8 prog_intf;
193	u8 subclass;
194	u8 base_class;
195	u32 subsystem_id;
196	union win_slot_encoding win_slot;
197	u32 ser; /* serial number */
198	u32 flags;
199	u16 virtual_numa_node;
200	u16 reserved;
201	} __packed;
202
203	/**
204	* struct hv_msi_desc
205	* @vector: IDT entry
206	* @delivery_mode: As defined in Intel's Programmer's
207	* Reference Manual, Volume 3, Chapter 8.
208	* @vector_count: Number of contiguous entries in the
209	* Interrupt Descriptor Table that are
210	* occupied by this Message-Signaled
211	* Interrupt. For "MSI", as first defined
212	* in PCI 2.2, this can be between 1 and
213	* 32. For "MSI-X," as first defined in PCI
214	* 3.0, this must be 1, as each MSI-X table
215	* entry would have its own descriptor.
216	* @reserved: Empty space
217	* @cpu_mask: All the target virtual processors.
218	*/
219	struct hv_msi_desc {
220	u8 vector;
221	u8 delivery_mode;
222	u16 vector_count;
223	u32 reserved;
224	u64 cpu_mask;
225	} __packed;
226
227	/**
228	* struct hv_msi_desc2 - 1.2 version of hv_msi_desc
229	* @vector: IDT entry
230	* @delivery_mode: As defined in Intel's Programmer's
231	* Reference Manual, Volume 3, Chapter 8.
232	* @vector_count: Number of contiguous entries in the
233	* Interrupt Descriptor Table that are
234	* occupied by this Message-Signaled
235	* Interrupt. For "MSI", as first defined
236	* in PCI 2.2, this can be between 1 and
237	* 32. For "MSI-X," as first defined in PCI
238	* 3.0, this must be 1, as each MSI-X table
239	* entry would have its own descriptor.
240	* @processor_count: number of bits enabled in array.
241	* @processor_array: All the target virtual processors.
242	*/
243	struct hv_msi_desc2 {
244	u8 vector;
245	u8 delivery_mode;
246	u16 vector_count;
247	u16 processor_count;
248	u16 processor_array[32];
249	} __packed;
250
251	/*
252	* struct hv_msi_desc3 - 1.3 version of hv_msi_desc
253	* Everything is the same as in 'hv_msi_desc2' except that the size of the
254	* 'vector' field is larger to support bigger vector values. For ex: LPI
255	* vectors on ARM.
256	*/
257	struct hv_msi_desc3 {
258	u32 vector;
259	u8 delivery_mode;
260	u8 reserved;
261	u16 vector_count;
262	u16 processor_count;
263	u16 processor_array[32];
264	} __packed;
265
266	/**
267	* struct tran_int_desc
268	* @reserved: unused, padding
269	* @vector_count: same as in hv_msi_desc
270	* @data: This is the "data payload" value that is
271	* written by the device when it generates
272	* a message-signaled interrupt, either MSI
273	* or MSI-X.
274	* @address: This is the address to which the data
275	* payload is written on interrupt
276	* generation.
277	*/
278	struct tran_int_desc {
279	u16 reserved;
280	u16 vector_count;
281	u32 data;
282	u64 address;
283	} __packed;
284
285	/*
286	* A generic message format for virtual PCI.
287	* Specific message formats are defined later in the file.
288	*/
289
290	struct pci_message {
291	u32 type;
292	} __packed;
293
294	struct pci_child_message {
295	struct pci_message message_type;
296	union win_slot_encoding wslot;
297	} __packed;
298
299	struct pci_incoming_message {
300	struct vmpacket_descriptor hdr;
301	struct pci_message message_type;
302	} __packed;
303
304	struct pci_response {
305	struct vmpacket_descriptor hdr;
306	s32 status; /* negative values are failures */
307	} __packed;
308
309	struct pci_packet {
310	void (*completion_func)(void *context, struct pci_response *resp,
311	int resp_packet_size);
312	void *compl_ctxt;
313	};
314
315	/*
316	* Specific message types supporting the PCI protocol.
317	*/
318
319	/*
320	* Version negotiation message. Sent from the guest to the host.
321	* The guest is free to try different versions until the host
322	* accepts the version.
323	*
324	* pci_version: The protocol version requested.
325	* is_last_attempt: If TRUE, this is the last version guest will request.
326	* reservedz: Reserved field, set to zero.
327	*/
328
329	struct pci_version_request {
330	struct pci_message message_type;
331	u32 protocol_version;
332	} __packed;
333
334	/*
335	* Bus D0 Entry. This is sent from the guest to the host when the virtual
336	* bus (PCI Express port) is ready for action.
337	*/
338
339	struct pci_bus_d0_entry {
340	struct pci_message message_type;
341	u32 reserved;
342	u64 mmio_base;
343	} __packed;
344
345	struct pci_bus_relations {
346	struct pci_incoming_message incoming;
347	u32 device_count;
348	struct pci_function_description func[];
349	} __packed;
350
351	struct pci_bus_relations2 {
352	struct pci_incoming_message incoming;
353	u32 device_count;
354	struct pci_function_description2 func[];
355	} __packed;
356
357	struct pci_q_res_req_response {
358	struct vmpacket_descriptor hdr;
359	s32 status; /* negative values are failures */
360	u32 probed_bar[PCI_STD_NUM_BARS];
361	} __packed;
362
363	struct pci_set_power {
364	struct pci_message message_type;
365	union win_slot_encoding wslot;
366	u32 power_state; /* In Windows terms */
367	u32 reserved;
368	} __packed;
369
370	struct pci_set_power_response {
371	struct vmpacket_descriptor hdr;
372	s32 status; /* negative values are failures */
373	union win_slot_encoding wslot;
374	u32 resultant_state; /* In Windows terms */
375	u32 reserved;
376	} __packed;
377
378	struct pci_resources_assigned {
379	struct pci_message message_type;
380	union win_slot_encoding wslot;
381	u8 memory_range[0x14][6]; /* not used here */
382	u32 msi_descriptors;
383	u32 reserved[4];
384	} __packed;
385
386	struct pci_resources_assigned2 {
387	struct pci_message message_type;
388	union win_slot_encoding wslot;
389	u8 memory_range[0x14][6]; /* not used here */
390	u32 msi_descriptor_count;
391	u8 reserved[70];
392	} __packed;
393
394	struct pci_create_interrupt {
395	struct pci_message message_type;
396	union win_slot_encoding wslot;
397	struct hv_msi_desc int_desc;
398	} __packed;
399
400	struct pci_create_int_response {
401	struct pci_response response;
402	u32 reserved;
403	struct tran_int_desc int_desc;
404	} __packed;
405
406	struct pci_create_interrupt2 {
407	struct pci_message message_type;
408	union win_slot_encoding wslot;
409	struct hv_msi_desc2 int_desc;
410	} __packed;
411
412	struct pci_create_interrupt3 {
413	struct pci_message message_type;
414	union win_slot_encoding wslot;
415	struct hv_msi_desc3 int_desc;
416	} __packed;
417
418	struct pci_delete_interrupt {
419	struct pci_message message_type;
420	union win_slot_encoding wslot;
421	struct tran_int_desc int_desc;
422	} __packed;
423
424	/*
425	* Note: the VM must pass a valid block id, wslot and bytes_requested.
426	*/
427	struct pci_read_block {
428	struct pci_message message_type;
429	u32 block_id;
430	union win_slot_encoding wslot;
431	u32 bytes_requested;
432	} __packed;
433
434	struct pci_read_block_response {
435	struct vmpacket_descriptor hdr;
436	u32 status;
437	u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
438	} __packed;
439
440	/*
441	* Note: the VM must pass a valid block id, wslot and byte_count.
442	*/
443	struct pci_write_block {
444	struct pci_message message_type;
445	u32 block_id;
446	union win_slot_encoding wslot;
447	u32 byte_count;
448	u8 bytes[HV_CONFIG_BLOCK_SIZE_MAX];
449	} __packed;
450
451	struct pci_dev_inval_block {
452	struct pci_incoming_message incoming;
453	union win_slot_encoding wslot;
454	u64 block_mask;
455	} __packed;
456
457	struct pci_dev_incoming {
458	struct pci_incoming_message incoming;
459	union win_slot_encoding wslot;
460	} __packed;
461
462	struct pci_eject_response {
463	struct pci_message message_type;
464	union win_slot_encoding wslot;
465	u32 status;
466	} __packed;
467
468	static int pci_ring_size = VMBUS_RING_SIZE(SZ_16K);
469
470	/*
471	* Driver specific state.
472	*/
473
474	enum hv_pcibus_state {
475	hv_pcibus_init = 0,
476	hv_pcibus_probed,
477	hv_pcibus_installed,
478	hv_pcibus_removing,
479	hv_pcibus_maximum
480	};
481
482	struct hv_pcibus_device {
483	#ifdef CONFIG_X86
484	struct pci_sysdata sysdata;
485	#elif defined(CONFIG_ARM64)
486	struct pci_config_window sysdata;
487	#endif
488	struct pci_host_bridge *bridge;
489	struct fwnode_handle *fwnode;
490	/* Protocol version negotiated with the host */
491	enum pci_protocol_version_t protocol_version;
492
493	struct mutex state_lock;
494	enum hv_pcibus_state state;
495
496	struct hv_device *hdev;
497	resource_size_t low_mmio_space;
498	resource_size_t high_mmio_space;
499	struct resource *mem_config;
500	struct resource *low_mmio_res;
501	struct resource *high_mmio_res;
502	struct completion *survey_event;
503	struct pci_bus *pci_bus;
504	spinlock_t config_lock; /* Avoid two threads writing index page */
505	spinlock_t device_list_lock; /* Protect lists below */
506	void __iomem *cfg_addr;
507
508	struct list_head children;
509	struct list_head dr_list;
510
511	struct msi_domain_info msi_info;
512	struct irq_domain *irq_domain;
513
514	struct workqueue_struct *wq;
515
516	/* Highest slot of child device with resources allocated */
517	int wslot_res_allocated;
518	bool use_calls; /* Use hypercalls to access mmio cfg space */
519	};
520
521	/*
522	* Tracks "Device Relations" messages from the host, which must be both
523	* processed in order and deferred so that they don't run in the context
524	* of the incoming packet callback.
525	*/
526	struct hv_dr_work {
527	struct work_struct wrk;
528	struct hv_pcibus_device *bus;
529	};
530
531	struct hv_pcidev_description {
532	u16 v_id; /* vendor ID */
533	u16 d_id; /* device ID */
534	u8 rev;
535	u8 prog_intf;
536	u8 subclass;
537	u8 base_class;
538	u32 subsystem_id;
539	union win_slot_encoding win_slot;
540	u32 ser; /* serial number */
541	u32 flags;
542	u16 virtual_numa_node;
543	};
544
545	struct hv_dr_state {
546	struct list_head list_entry;
547	u32 device_count;
548	struct hv_pcidev_description func[] __counted_by(device_count);
549	};
550
551	struct hv_pci_dev {
552	/* List protected by pci_rescan_remove_lock */
553	struct list_head list_entry;
554	refcount_t refs;
555	struct pci_slot *pci_slot;
556	struct hv_pcidev_description desc;
557	bool reported_missing;
558	struct hv_pcibus_device *hbus;
559	struct work_struct wrk;
560
561	void (*block_invalidate)(void *context, u64 block_mask);
562	void *invalidate_context;
563
564	/*
565	* What would be observed if one wrote 0xFFFFFFFF to a BAR and then
566	* read it back, for each of the BAR offsets within config space.
567	*/
568	u32 probed_bar[PCI_STD_NUM_BARS];
569	};
570
571	struct hv_pci_compl {
572	struct completion host_event;
573	s32 completion_status;
574	};
575
576	static void hv_pci_onchannelcallback(void *context);
577
578	#ifdef CONFIG_X86
579	#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED
580	#define FLOW_HANDLER handle_edge_irq
581	#define FLOW_NAME "edge"
582
583	static int hv_pci_irqchip_init(void)
584	{
585	return 0;
586	}
587
588	static struct irq_domain *hv_pci_get_root_domain(void)
589	{
590	return x86_vector_domain;
591	}
592
593	static unsigned int hv_msi_get_int_vector(struct irq_data *data)
594	{
595	struct irq_cfg *cfg = irqd_cfg(irq_data: data);
596
597	return cfg->vector;
598	}
599
600	#define hv_msi_prepare pci_msi_prepare
601
602	/**
603	* hv_arch_irq_unmask() - "Unmask" the IRQ by setting its current
604	* affinity.
605	* @data: Describes the IRQ
606	*
607	* Build new a destination for the MSI and make a hypercall to
608	* update the Interrupt Redirection Table. "Device Logical ID"
609	* is built out of this PCI bus's instance GUID and the function
610	* number of the device.
611	*/
612	static void hv_arch_irq_unmask(struct irq_data *data)
613	{
614	struct msi_desc *msi_desc = irq_data_get_msi_desc(d: data);
615	struct hv_retarget_device_interrupt *params;
616	struct tran_int_desc *int_desc;
617	struct hv_pcibus_device *hbus;
618	const struct cpumask *dest;
619	cpumask_var_t tmp;
620	struct pci_bus *pbus;
621	struct pci_dev *pdev;
622	unsigned long flags;
623	u32 var_size = 0;
624	int cpu, nr_bank;
625	u64 res;
626
627	dest = irq_data_get_effective_affinity_mask(d: data);
628	pdev = msi_desc_to_pci_dev(desc: msi_desc);
629	pbus = pdev->bus;
630	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
631	int_desc = data->chip_data;
632	if (!int_desc) {
633	dev_warn(&hbus->hdev->device, "%s() can not unmask irq %u\n",
634	__func__, data->irq);
635	return;
636	}
637
638	local_irq_save(flags);
639
640	params = *this_cpu_ptr(hyperv_pcpu_input_arg);
641	memset(params, 0, sizeof(*params));
642	params->partition_id = HV_PARTITION_ID_SELF;
643	params->int_entry.source = HV_INTERRUPT_SOURCE_MSI;
644	params->int_entry.msi_entry.address.as_uint32 = int_desc->address & 0xffffffff;
645	params->int_entry.msi_entry.data.as_uint32 = int_desc->data;
646	params->device_id = (hbus->hdev->dev_instance.b[5] << 24) |
647	(hbus->hdev->dev_instance.b[4] << 16) |
648	(hbus->hdev->dev_instance.b[7] << 8) |
649	(hbus->hdev->dev_instance.b[6] & 0xf8) |
650	PCI_FUNC(pdev->devfn);
651	params->int_target.vector = hv_msi_get_int_vector(data);
652
653	if (hbus->protocol_version >= PCI_PROTOCOL_VERSION_1_2) {
654	/*
655	* PCI_PROTOCOL_VERSION_1_2 supports the VP_SET version of the
656	* HVCALL_RETARGET_INTERRUPT hypercall, which also coincides
657	* with >64 VP support.
658	* ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED
659	* is not sufficient for this hypercall.
660	*/
661	params->int_target.flags |=
662	HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET;
663
664	if (!alloc_cpumask_var(mask: &tmp, GFP_ATOMIC)) {
665	res = 1;
666	goto out;
667	}
668
669	cpumask_and(dstp: tmp, src1p: dest, cpu_online_mask);
670	nr_bank = cpumask_to_vpset(vpset: &params->int_target.vp_set, cpus: tmp);
671	free_cpumask_var(mask: tmp);
672
673	if (nr_bank <= 0) {
674	res = 1;
675	goto out;
676	}
677
678	/*
679	* var-sized hypercall, var-size starts after vp_mask (thus
680	* vp_set.format does not count, but vp_set.valid_bank_mask
681	* does).
682	*/
683	var_size = 1 + nr_bank;
684	} else {
685	for_each_cpu_and(cpu, dest, cpu_online_mask) {
686	params->int_target.vp_mask |=
687	(1ULL << hv_cpu_number_to_vp_number(cpu_number: cpu));
688	}
689	}
690
691	res = hv_do_hypercall(HVCALL_RETARGET_INTERRUPT | (var_size << 17),
692	inputaddr: params, NULL);
693
694	out:
695	local_irq_restore(flags);
696
697	/*
698	* During hibernation, when a CPU is offlined, the kernel tries
699	* to move the interrupt to the remaining CPUs that haven't
700	* been offlined yet. In this case, the below hv_do_hypercall()
701	* always fails since the vmbus channel has been closed:
702	* refer to cpu_disable_common() -> fixup_irqs() ->
703	* irq_migrate_all_off_this_cpu() -> migrate_one_irq().
704	*
705	* Suppress the error message for hibernation because the failure
706	* during hibernation does not matter (at this time all the devices
707	* have been frozen). Note: the correct affinity info is still updated
708	* into the irqdata data structure in migrate_one_irq() ->
709	* irq_do_set_affinity(), so later when the VM resumes,
710	* hv_pci_restore_msi_state() is able to correctly restore the
711	* interrupt with the correct affinity.
712	*/
713	if (!hv_result_success(status: res) && hbus->state != hv_pcibus_removing)
714	dev_err(&hbus->hdev->device,
715	"%s() failed: %#llx", __func__, res);
716	}
717	#elif defined(CONFIG_ARM64)
718	/*
719	* SPI vectors to use for vPCI; arch SPIs range is [32, 1019], but leaving a bit
720	* of room at the start to allow for SPIs to be specified through ACPI and
721	* starting with a power of two to satisfy power of 2 multi-MSI requirement.
722	*/
723	#define HV_PCI_MSI_SPI_START 64
724	#define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START)
725	#define DELIVERY_MODE 0
726	#define FLOW_HANDLER NULL
727	#define FLOW_NAME NULL
728	#define hv_msi_prepare NULL
729
730	struct hv_pci_chip_data {
731	DECLARE_BITMAP(spi_map, HV_PCI_MSI_SPI_NR);
732	struct mutex map_lock;
733	};
734
735	/* Hyper-V vPCI MSI GIC IRQ domain */
736	static struct irq_domain *hv_msi_gic_irq_domain;
737
738	/* Hyper-V PCI MSI IRQ chip */
739	static struct irq_chip hv_arm64_msi_irq_chip = {
740	.name = "MSI",
741	.irq_set_affinity = irq_chip_set_affinity_parent,
742	.irq_eoi = irq_chip_eoi_parent,
743	.irq_mask = irq_chip_mask_parent,
744	.irq_unmask = irq_chip_unmask_parent
745	};
746
747	static unsigned int hv_msi_get_int_vector(struct irq_data *irqd)
748	{
749	return irqd->parent_data->hwirq;
750	}
751
752	/*
753	* @nr_bm_irqs: Indicates the number of IRQs that were allocated from
754	* the bitmap.
755	* @nr_dom_irqs: Indicates the number of IRQs that were allocated from
756	* the parent domain.
757	*/
758	static void hv_pci_vec_irq_free(struct irq_domain *domain,
759	unsigned int virq,
760	unsigned int nr_bm_irqs,
761	unsigned int nr_dom_irqs)
762	{
763	struct hv_pci_chip_data *chip_data = domain->host_data;
764	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
765	int first = d->hwirq - HV_PCI_MSI_SPI_START;
766	int i;
767
768	mutex_lock(&chip_data->map_lock);
769	bitmap_release_region(chip_data->spi_map,
770	first,
771	get_count_order(nr_bm_irqs));
772	mutex_unlock(&chip_data->map_lock);
773	for (i = 0; i < nr_dom_irqs; i++) {
774	if (i)
775	d = irq_domain_get_irq_data(domain, virq + i);
776	irq_domain_reset_irq_data(d);
777	}
778
779	irq_domain_free_irqs_parent(domain, virq, nr_dom_irqs);
780	}
781
782	static void hv_pci_vec_irq_domain_free(struct irq_domain *domain,
783	unsigned int virq,
784	unsigned int nr_irqs)
785	{
786	hv_pci_vec_irq_free(domain, virq, nr_irqs, nr_irqs);
787	}
788
789	static int hv_pci_vec_alloc_device_irq(struct irq_domain *domain,
790	unsigned int nr_irqs,
791	irq_hw_number_t *hwirq)
792	{
793	struct hv_pci_chip_data *chip_data = domain->host_data;
794	int index;
795
796	/* Find and allocate region from the SPI bitmap */
797	mutex_lock(&chip_data->map_lock);
798	index = bitmap_find_free_region(chip_data->spi_map,
799	HV_PCI_MSI_SPI_NR,
800	get_count_order(nr_irqs));
801	mutex_unlock(&chip_data->map_lock);
802	if (index < 0)
803	return -ENOSPC;
804
805	*hwirq = index + HV_PCI_MSI_SPI_START;
806
807	return 0;
808	}
809
810	static int hv_pci_vec_irq_gic_domain_alloc(struct irq_domain *domain,
811	unsigned int virq,
812	irq_hw_number_t hwirq)
813	{
814	struct irq_fwspec fwspec;
815	struct irq_data *d;
816	int ret;
817
818	fwspec.fwnode = domain->parent->fwnode;
819	if (is_of_node(fwspec.fwnode)) {
820	/* SPI lines for OF translations start at offset 32 */
821	fwspec.param_count = 3;
822	fwspec.param[0] = 0;
823	fwspec.param[1] = hwirq - 32;
824	fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
825	} else {
826	fwspec.param_count = 2;
827	fwspec.param[0] = hwirq;
828	fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
829	}
830
831	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
832	if (ret)
833	return ret;
834
835	/*
836	* Since the interrupt specifier is not coming from ACPI or DT, the
837	* trigger type will need to be set explicitly. Otherwise, it will be
838	* set to whatever is in the GIC configuration.
839	*/
840	d = irq_domain_get_irq_data(domain->parent, virq);
841
842	return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
843	}
844
845	static int hv_pci_vec_irq_domain_alloc(struct irq_domain *domain,
846	unsigned int virq, unsigned int nr_irqs,
847	void *args)
848	{
849	irq_hw_number_t hwirq;
850	unsigned int i;
851	int ret;
852
853	ret = hv_pci_vec_alloc_device_irq(domain, nr_irqs, &hwirq);
854	if (ret)
855	return ret;
856
857	for (i = 0; i < nr_irqs; i++) {
858	ret = hv_pci_vec_irq_gic_domain_alloc(domain, virq + i,
859	hwirq + i);
860	if (ret) {
861	hv_pci_vec_irq_free(domain, virq, nr_irqs, i);
862	return ret;
863	}
864
865	irq_domain_set_hwirq_and_chip(domain, virq + i,
866	hwirq + i,
867	&hv_arm64_msi_irq_chip,
868	domain->host_data);
869	pr_debug("pID:%d vID:%u\n", (int)(hwirq + i), virq + i);
870	}
871
872	return 0;
873	}
874
875	/*
876	* Pick the first cpu as the irq affinity that can be temporarily used for
877	* composing MSI from the hypervisor. GIC will eventually set the right
878	* affinity for the irq and the 'unmask' will retarget the interrupt to that
879	* cpu.
880	*/
881	static int hv_pci_vec_irq_domain_activate(struct irq_domain *domain,
882	struct irq_data *irqd, bool reserve)
883	{
884	int cpu = cpumask_first(cpu_present_mask);
885
886	irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
887
888	return 0;
889	}
890
891	static const struct irq_domain_ops hv_pci_domain_ops = {
892	.alloc = hv_pci_vec_irq_domain_alloc,
893	.free = hv_pci_vec_irq_domain_free,
894	.activate = hv_pci_vec_irq_domain_activate,
895	};
896
897	#ifdef CONFIG_OF
898
899	static struct irq_domain *hv_pci_of_irq_domain_parent(void)
900	{
901	struct device_node *parent;
902	struct irq_domain *domain;
903
904	parent = of_irq_find_parent(hv_get_vmbus_root_device()->of_node);
905	if (!parent)
906	return NULL;
907	domain = irq_find_host(parent);
908	of_node_put(parent);
909
910	return domain;
911	}
912
913	#endif
914
915	#ifdef CONFIG_ACPI
916
917	static struct irq_domain *hv_pci_acpi_irq_domain_parent(void)
918	{
919	acpi_gsi_domain_disp_fn gsi_domain_disp_fn;
920
921	gsi_domain_disp_fn = acpi_get_gsi_dispatcher();
922	if (!gsi_domain_disp_fn)
923	return NULL;
924	return irq_find_matching_fwnode(gsi_domain_disp_fn(0),
925	DOMAIN_BUS_ANY);
926	}
927
928	#endif
929
930	static int hv_pci_irqchip_init(void)
931	{
932	static struct hv_pci_chip_data *chip_data;
933	struct fwnode_handle *fn = NULL;
934	struct irq_domain *irq_domain_parent = NULL;
935	int ret = -ENOMEM;
936
937	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
938	if (!chip_data)
939	return ret;
940
941	mutex_init(&chip_data->map_lock);
942	fn = irq_domain_alloc_named_fwnode("hv_vpci_arm64");
943	if (!fn)
944	goto free_chip;
945
946	/*
947	* IRQ domain once enabled, should not be removed since there is no
948	* way to ensure that all the corresponding devices are also gone and
949	* no interrupts will be generated.
950	*/
951	#ifdef CONFIG_ACPI
952	if (!acpi_disabled)
953	irq_domain_parent = hv_pci_acpi_irq_domain_parent();
954	#endif
955	#ifdef CONFIG_OF
956	if (!irq_domain_parent)
957	irq_domain_parent = hv_pci_of_irq_domain_parent();
958	#endif
959	if (!irq_domain_parent) {
960	WARN_ONCE(1, "Invalid firmware configuration for VMBus interrupts\n");
961	ret = -EINVAL;
962	goto free_chip;
963	}
964
965	hv_msi_gic_irq_domain = irq_domain_create_hierarchy(irq_domain_parent, 0,
966	HV_PCI_MSI_SPI_NR,
967	fn, &hv_pci_domain_ops,
968	chip_data);
969
970	if (!hv_msi_gic_irq_domain) {
971	pr_err("Failed to create Hyper-V arm64 vPCI MSI IRQ domain\n");
972	goto free_chip;
973	}
974
975	return 0;
976
977	free_chip:
978	kfree(chip_data);
979	if (fn)
980	irq_domain_free_fwnode(fn);
981
982	return ret;
983	}
984
985	static struct irq_domain *hv_pci_get_root_domain(void)
986	{
987	return hv_msi_gic_irq_domain;
988	}
989
990	/*
991	* SPIs are used for interrupts of PCI devices and SPIs is managed via GICD
992	* registers which Hyper-V already supports, so no hypercall needed.
993	*/
994	static void hv_arch_irq_unmask(struct irq_data *data) { }
995	#endif /* CONFIG_ARM64 */
996
997	/**
998	* hv_pci_generic_compl() - Invoked for a completion packet
999	* @context: Set up by the sender of the packet.
1000	* @resp: The response packet
1001	* @resp_packet_size: Size in bytes of the packet
1002	*
1003	* This function is used to trigger an event and report status
1004	* for any message for which the completion packet contains a
1005	* status and nothing else.
1006	*/
1007	static void hv_pci_generic_compl(void *context, struct pci_response *resp,
1008	int resp_packet_size)
1009	{
1010	struct hv_pci_compl *comp_pkt = context;
1011
1012	comp_pkt->completion_status = resp->status;
1013	complete(&comp_pkt->host_event);
1014	}
1015
1016	static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
1017	u32 wslot);
1018
1019	static void get_pcichild(struct hv_pci_dev *hpdev)
1020	{
1021	refcount_inc(r: &hpdev->refs);
1022	}
1023
1024	static void put_pcichild(struct hv_pci_dev *hpdev)
1025	{
1026	if (refcount_dec_and_test(r: &hpdev->refs))
1027	kfree(objp: hpdev);
1028	}
1029
1030	/*
1031	* There is no good way to get notified from vmbus_onoffer_rescind(),
1032	* so let's use polling here, since this is not a hot path.
1033	*/
1034	static int wait_for_response(struct hv_device *hdev,
1035	struct completion *comp)
1036	{
1037	while (true) {
1038	if (hdev->channel->rescind) {
1039	dev_warn_once(&hdev->device, "The device is gone.\n");
1040	return -ENODEV;
1041	}
1042
1043	if (wait_for_completion_timeout(x: comp, HZ / 10))
1044	break;
1045	}
1046
1047	return 0;
1048	}
1049
1050	/**
1051	* devfn_to_wslot() - Convert from Linux PCI slot to Windows
1052	* @devfn: The Linux representation of PCI slot
1053	*
1054	* Windows uses a slightly different representation of PCI slot.
1055	*
1056	* Return: The Windows representation
1057	*/
1058	static u32 devfn_to_wslot(int devfn)
1059	{
1060	union win_slot_encoding wslot;
1061
1062	wslot.slot = 0;
1063	wslot.bits.dev = PCI_SLOT(devfn);
1064	wslot.bits.func = PCI_FUNC(devfn);
1065
1066	return wslot.slot;
1067	}
1068
1069	/**
1070	* wslot_to_devfn() - Convert from Windows PCI slot to Linux
1071	* @wslot: The Windows representation of PCI slot
1072	*
1073	* Windows uses a slightly different representation of PCI slot.
1074	*
1075	* Return: The Linux representation
1076	*/
1077	static int wslot_to_devfn(u32 wslot)
1078	{
1079	union win_slot_encoding slot_no;
1080
1081	slot_no.slot = wslot;
1082	return PCI_DEVFN(slot_no.bits.dev, slot_no.bits.func);
1083	}
1084
1085	static void hv_pci_read_mmio(struct device *dev, phys_addr_t gpa, int size, u32 *val)
1086	{
1087	struct hv_mmio_read_input *in;
1088	struct hv_mmio_read_output *out;
1089	u64 ret;
1090
1091	/*
1092	* Must be called with interrupts disabled so it is safe
1093	* to use the per-cpu input argument page. Use it for
1094	* both input and output.
1095	*/
1096	in = *this_cpu_ptr(hyperv_pcpu_input_arg);
1097	out = *this_cpu_ptr(hyperv_pcpu_input_arg) + sizeof(*in);
1098	in->gpa = gpa;
1099	in->size = size;
1100
1101	ret = hv_do_hypercall(HVCALL_MMIO_READ, inputaddr: in, outputaddr: out);
1102	if (hv_result_success(status: ret)) {
1103	switch (size) {
1104	case 1:
1105	*val = *(u8 *)(out->data);
1106	break;
1107	case 2:
1108	*val = *(u16 *)(out->data);
1109	break;
1110	default:
1111	*val = *(u32 *)(out->data);
1112	break;
1113	}
1114	} else
1115	dev_err(dev, "MMIO read hypercall error %llx addr %llx size %d\n",
1116	ret, gpa, size);
1117	}
1118
1119	static void hv_pci_write_mmio(struct device *dev, phys_addr_t gpa, int size, u32 val)
1120	{
1121	struct hv_mmio_write_input *in;
1122	u64 ret;
1123
1124	/*
1125	* Must be called with interrupts disabled so it is safe
1126	* to use the per-cpu input argument memory.
1127	*/
1128	in = *this_cpu_ptr(hyperv_pcpu_input_arg);
1129	in->gpa = gpa;
1130	in->size = size;
1131	switch (size) {
1132	case 1:
1133	*(u8 *)(in->data) = val;
1134	break;
1135	case 2:
1136	*(u16 *)(in->data) = val;
1137	break;
1138	default:
1139	*(u32 *)(in->data) = val;
1140	break;
1141	}
1142
1143	ret = hv_do_hypercall(HVCALL_MMIO_WRITE, inputaddr: in, NULL);
1144	if (!hv_result_success(status: ret))
1145	dev_err(dev, "MMIO write hypercall error %llx addr %llx size %d\n",
1146	ret, gpa, size);
1147	}
1148
1149	/*
1150	* PCI Configuration Space for these root PCI buses is implemented as a pair
1151	* of pages in memory-mapped I/O space. Writing to the first page chooses
1152	* the PCI function being written or read. Once the first page has been
1153	* written to, the following page maps in the entire configuration space of
1154	* the function.
1155	*/
1156
1157	/**
1158	* _hv_pcifront_read_config() - Internal PCI config read
1159	* @hpdev: The PCI driver's representation of the device
1160	* @where: Offset within config space
1161	* @size: Size of the transfer
1162	* @val: Pointer to the buffer receiving the data
1163	*/
1164	static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where,
1165	int size, u32 *val)
1166	{
1167	struct hv_pcibus_device *hbus = hpdev->hbus;
1168	struct device *dev = &hbus->hdev->device;
1169	int offset = where + CFG_PAGE_OFFSET;
1170	unsigned long flags;
1171
1172	/*
1173	* If the attempt is to read the IDs or the ROM BAR, simulate that.
1174	*/
1175	if (where + size <= PCI_COMMAND) {
1176	memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size);
1177	} else if (where >= PCI_CLASS_REVISION && where + size <=
1178	PCI_CACHE_LINE_SIZE) {
1179	memcpy(val, ((u8 *)&hpdev->desc.rev) + where -
1180	PCI_CLASS_REVISION, size);
1181	} else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where + size <=
1182	PCI_ROM_ADDRESS) {
1183	memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where -
1184	PCI_SUBSYSTEM_VENDOR_ID, size);
1185	} else if (where >= PCI_ROM_ADDRESS && where + size <=
1186	PCI_CAPABILITY_LIST) {
1187	/* ROM BARs are unimplemented */
1188	*val = 0;
1189	} else if ((where >= PCI_INTERRUPT_LINE && where + size <= PCI_INTERRUPT_PIN) ||
1190	(where >= PCI_INTERRUPT_PIN && where + size <= PCI_MIN_GNT)) {
1191	/*
1192	* Interrupt Line and Interrupt PIN are hard-wired to zero
1193	* because this front-end only supports message-signaled
1194	* interrupts.
1195	*/
1196	*val = 0;
1197	} else if (where + size <= CFG_PAGE_SIZE) {
1198
1199	spin_lock_irqsave(&hbus->config_lock, flags);
1200	if (hbus->use_calls) {
1201	phys_addr_t addr = hbus->mem_config->start + offset;
1202
1203	hv_pci_write_mmio(dev, gpa: hbus->mem_config->start, size: 4,
1204	val: hpdev->desc.win_slot.slot);
1205	hv_pci_read_mmio(dev, gpa: addr, size, val);
1206	} else {
1207	void __iomem *addr = hbus->cfg_addr + offset;
1208
1209	/* Choose the function to be read. (See comment above) */
1210	writel(val: hpdev->desc.win_slot.slot, addr: hbus->cfg_addr);
1211	/* Make sure the function was chosen before reading. */
1212	mb();
1213	/* Read from that function's config space. */
1214	switch (size) {
1215	case 1:
1216	*val = readb(addr);
1217	break;
1218	case 2:
1219	*val = readw(addr);
1220	break;
1221	default:
1222	*val = readl(addr);
1223	break;
1224	}
1225	/*
1226	* Make sure the read was done before we release the
1227	* spinlock allowing consecutive reads/writes.
1228	*/
1229	mb();
1230	}
1231	spin_unlock_irqrestore(lock: &hbus->config_lock, flags);
1232	} else {
1233	dev_err(dev, "Attempt to read beyond a function's config space.\n");
1234	}
1235	}
1236
1237	static u16 hv_pcifront_get_vendor_id(struct hv_pci_dev *hpdev)
1238	{
1239	struct hv_pcibus_device *hbus = hpdev->hbus;
1240	struct device *dev = &hbus->hdev->device;
1241	u32 val;
1242	u16 ret;
1243	unsigned long flags;
1244
1245	spin_lock_irqsave(&hbus->config_lock, flags);
1246
1247	if (hbus->use_calls) {
1248	phys_addr_t addr = hbus->mem_config->start +
1249	CFG_PAGE_OFFSET + PCI_VENDOR_ID;
1250
1251	hv_pci_write_mmio(dev, gpa: hbus->mem_config->start, size: 4,
1252	val: hpdev->desc.win_slot.slot);
1253	hv_pci_read_mmio(dev, gpa: addr, size: 2, val: &val);
1254	ret = val; /* Truncates to 16 bits */
1255	} else {
1256	void __iomem *addr = hbus->cfg_addr + CFG_PAGE_OFFSET +
1257	PCI_VENDOR_ID;
1258	/* Choose the function to be read. (See comment above) */
1259	writel(val: hpdev->desc.win_slot.slot, addr: hbus->cfg_addr);
1260	/* Make sure the function was chosen before we start reading. */
1261	mb();
1262	/* Read from that function's config space. */
1263	ret = readw(addr);
1264	/*
1265	* mb() is not required here, because the
1266	* spin_unlock_irqrestore() is a barrier.
1267	*/
1268	}
1269
1270	spin_unlock_irqrestore(lock: &hbus->config_lock, flags);
1271
1272	return ret;
1273	}
1274
1275	/**
1276	* _hv_pcifront_write_config() - Internal PCI config write
1277	* @hpdev: The PCI driver's representation of the device
1278	* @where: Offset within config space
1279	* @size: Size of the transfer
1280	* @val: The data being transferred
1281	*/
1282	static void _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where,
1283	int size, u32 val)
1284	{
1285	struct hv_pcibus_device *hbus = hpdev->hbus;
1286	struct device *dev = &hbus->hdev->device;
1287	int offset = where + CFG_PAGE_OFFSET;
1288	unsigned long flags;
1289
1290	if (where >= PCI_SUBSYSTEM_VENDOR_ID &&
1291	where + size <= PCI_CAPABILITY_LIST) {
1292	/* SSIDs and ROM BARs are read-only */
1293	} else if (where >= PCI_COMMAND && where + size <= CFG_PAGE_SIZE) {
1294	spin_lock_irqsave(&hbus->config_lock, flags);
1295
1296	if (hbus->use_calls) {
1297	phys_addr_t addr = hbus->mem_config->start + offset;
1298
1299	hv_pci_write_mmio(dev, gpa: hbus->mem_config->start, size: 4,
1300	val: hpdev->desc.win_slot.slot);
1301	hv_pci_write_mmio(dev, gpa: addr, size, val);
1302	} else {
1303	void __iomem *addr = hbus->cfg_addr + offset;
1304
1305	/* Choose the function to write. (See comment above) */
1306	writel(val: hpdev->desc.win_slot.slot, addr: hbus->cfg_addr);
1307	/* Make sure the function was chosen before writing. */
1308	wmb();
1309	/* Write to that function's config space. */
1310	switch (size) {
1311	case 1:
1312	writeb(val, addr);
1313	break;
1314	case 2:
1315	writew(val, addr);
1316	break;
1317	default:
1318	writel(val, addr);
1319	break;
1320	}
1321	/*
1322	* Make sure the write was done before we release the
1323	* spinlock allowing consecutive reads/writes.
1324	*/
1325	mb();
1326	}
1327	spin_unlock_irqrestore(lock: &hbus->config_lock, flags);
1328	} else {
1329	dev_err(dev, "Attempt to write beyond a function's config space.\n");
1330	}
1331	}
1332
1333	/**
1334	* hv_pcifront_read_config() - Read configuration space
1335	* @bus: PCI Bus structure
1336	* @devfn: Device/function
1337	* @where: Offset from base
1338	* @size: Byte/word/dword
1339	* @val: Value to be read
1340	*
1341	* Return: PCIBIOS_SUCCESSFUL on success
1342	* PCIBIOS_DEVICE_NOT_FOUND on failure
1343	*/
1344	static int hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn,
1345	int where, int size, u32 *val)
1346	{
1347	struct hv_pcibus_device *hbus =
1348	container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
1349	struct hv_pci_dev *hpdev;
1350
1351	hpdev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn));
1352	if (!hpdev)
1353	return PCIBIOS_DEVICE_NOT_FOUND;
1354
1355	_hv_pcifront_read_config(hpdev, where, size, val);
1356
1357	put_pcichild(hpdev);
1358	return PCIBIOS_SUCCESSFUL;
1359	}
1360
1361	/**
1362	* hv_pcifront_write_config() - Write configuration space
1363	* @bus: PCI Bus structure
1364	* @devfn: Device/function
1365	* @where: Offset from base
1366	* @size: Byte/word/dword
1367	* @val: Value to be written to device
1368	*
1369	* Return: PCIBIOS_SUCCESSFUL on success
1370	* PCIBIOS_DEVICE_NOT_FOUND on failure
1371	*/
1372	static int hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn,
1373	int where, int size, u32 val)
1374	{
1375	struct hv_pcibus_device *hbus =
1376	container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
1377	struct hv_pci_dev *hpdev;
1378
1379	hpdev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn));
1380	if (!hpdev)
1381	return PCIBIOS_DEVICE_NOT_FOUND;
1382
1383	_hv_pcifront_write_config(hpdev, where, size, val);
1384
1385	put_pcichild(hpdev);
1386	return PCIBIOS_SUCCESSFUL;
1387	}
1388
1389	/* PCIe operations */
1390	static struct pci_ops hv_pcifront_ops = {
1391	.read = hv_pcifront_read_config,
1392	.write = hv_pcifront_write_config,
1393	};
1394
1395	/*
1396	* Paravirtual backchannel
1397	*
1398	* Hyper-V SR-IOV provides a backchannel mechanism in software for
1399	* communication between a VF driver and a PF driver. These
1400	* "configuration blocks" are similar in concept to PCI configuration space,
1401	* but instead of doing reads and writes in 32-bit chunks through a very slow
1402	* path, packets of up to 128 bytes can be sent or received asynchronously.
1403	*
1404	* Nearly every SR-IOV device contains just such a communications channel in
1405	* hardware, so using this one in software is usually optional. Using the
1406	* software channel, however, allows driver implementers to leverage software
1407	* tools that fuzz the communications channel looking for vulnerabilities.
1408	*
1409	* The usage model for these packets puts the responsibility for reading or
1410	* writing on the VF driver. The VF driver sends a read or a write packet,
1411	* indicating which "block" is being referred to by number.
1412	*
1413	* If the PF driver wishes to initiate communication, it can "invalidate" one or
1414	* more of the first 64 blocks. This invalidation is delivered via a callback
1415	* supplied to the VF driver by this driver.
1416	*
1417	* No protocol is implied, except that supplied by the PF and VF drivers.
1418	*/
1419
1420	struct hv_read_config_compl {
1421	struct hv_pci_compl comp_pkt;
1422	void *buf;
1423	unsigned int len;
1424	unsigned int bytes_returned;
1425	};
1426
1427	/**
1428	* hv_pci_read_config_compl() - Invoked when a response packet
1429	* for a read config block operation arrives.
1430	* @context: Identifies the read config operation
1431	* @resp: The response packet itself
1432	* @resp_packet_size: Size in bytes of the response packet
1433	*/
1434	static void hv_pci_read_config_compl(void *context, struct pci_response *resp,
1435	int resp_packet_size)
1436	{
1437	struct hv_read_config_compl *comp = context;
1438	struct pci_read_block_response *read_resp =
1439	(struct pci_read_block_response *)resp;
1440	unsigned int data_len, hdr_len;
1441
1442	hdr_len = offsetof(struct pci_read_block_response, bytes);
1443	if (resp_packet_size < hdr_len) {
1444	comp->comp_pkt.completion_status = -1;
1445	goto out;
1446	}
1447
1448	data_len = resp_packet_size - hdr_len;
1449	if (data_len > 0 && read_resp->status == 0) {
1450	comp->bytes_returned = min(comp->len, data_len);
1451	memcpy(comp->buf, read_resp->bytes, comp->bytes_returned);
1452	} else {
1453	comp->bytes_returned = 0;
1454	}
1455
1456	comp->comp_pkt.completion_status = read_resp->status;
1457	out:
1458	complete(&comp->comp_pkt.host_event);
1459	}
1460
1461	/**
1462	* hv_read_config_block() - Sends a read config block request to
1463	* the back-end driver running in the Hyper-V parent partition.
1464	* @pdev: The PCI driver's representation for this device.
1465	* @buf: Buffer into which the config block will be copied.
1466	* @len: Size in bytes of buf.
1467	* @block_id: Identifies the config block which has been requested.
1468	* @bytes_returned: Size which came back from the back-end driver.
1469	*
1470	* Return: 0 on success, -errno on failure
1471	*/
1472	static int hv_read_config_block(struct pci_dev *pdev, void *buf,
1473	unsigned int len, unsigned int block_id,
1474	unsigned int *bytes_returned)
1475	{
1476	struct hv_pcibus_device *hbus =
1477	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1478	sysdata);
1479	struct {
1480	struct pci_packet pkt;
1481	char buf[sizeof(struct pci_read_block)];
1482	} pkt;
1483	struct hv_read_config_compl comp_pkt;
1484	struct pci_read_block *read_blk;
1485	int ret;
1486
1487	if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
1488	return -EINVAL;
1489
1490	init_completion(x: &comp_pkt.comp_pkt.host_event);
1491	comp_pkt.buf = buf;
1492	comp_pkt.len = len;
1493
1494	memset(&pkt, 0, sizeof(pkt));
1495	pkt.pkt.completion_func = hv_pci_read_config_compl;
1496	pkt.pkt.compl_ctxt = &comp_pkt;
1497	read_blk = (struct pci_read_block *)pkt.buf;
1498	read_blk->message_type.type = PCI_READ_BLOCK;
1499	read_blk->wslot.slot = devfn_to_wslot(devfn: pdev->devfn);
1500	read_blk->block_id = block_id;
1501	read_blk->bytes_requested = len;
1502
1503	ret = vmbus_sendpacket(channel: hbus->hdev->channel, buffer: read_blk,
1504	bufferLen: sizeof(*read_blk), requestid: (unsigned long)&pkt.pkt,
1505	type: VM_PKT_DATA_INBAND,
1506	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1507	if (ret)
1508	return ret;
1509
1510	ret = wait_for_response(hdev: hbus->hdev, comp: &comp_pkt.comp_pkt.host_event);
1511	if (ret)
1512	return ret;
1513
1514	if (comp_pkt.comp_pkt.completion_status != 0 ||
1515	comp_pkt.bytes_returned == 0) {
1516	dev_err(&hbus->hdev->device,
1517	"Read Config Block failed: 0x%x, bytes_returned=%d\n",
1518	comp_pkt.comp_pkt.completion_status,
1519	comp_pkt.bytes_returned);
1520	return -EIO;
1521	}
1522
1523	*bytes_returned = comp_pkt.bytes_returned;
1524	return 0;
1525	}
1526
1527	/**
1528	* hv_pci_write_config_compl() - Invoked when a response packet for a write
1529	* config block operation arrives.
1530	* @context: Identifies the write config operation
1531	* @resp: The response packet itself
1532	* @resp_packet_size: Size in bytes of the response packet
1533	*/
1534	static void hv_pci_write_config_compl(void *context, struct pci_response *resp,
1535	int resp_packet_size)
1536	{
1537	struct hv_pci_compl *comp_pkt = context;
1538
1539	comp_pkt->completion_status = resp->status;
1540	complete(&comp_pkt->host_event);
1541	}
1542
1543	/**
1544	* hv_write_config_block() - Sends a write config block request to the
1545	* back-end driver running in the Hyper-V parent partition.
1546	* @pdev: The PCI driver's representation for this device.
1547	* @buf: Buffer from which the config block will be copied.
1548	* @len: Size in bytes of buf.
1549	* @block_id: Identifies the config block which is being written.
1550	*
1551	* Return: 0 on success, -errno on failure
1552	*/
1553	static int hv_write_config_block(struct pci_dev *pdev, void *buf,
1554	unsigned int len, unsigned int block_id)
1555	{
1556	struct hv_pcibus_device *hbus =
1557	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1558	sysdata);
1559	struct {
1560	struct pci_packet pkt;
1561	char buf[sizeof(struct pci_write_block)];
1562	u32 reserved;
1563	} pkt;
1564	struct hv_pci_compl comp_pkt;
1565	struct pci_write_block *write_blk;
1566	u32 pkt_size;
1567	int ret;
1568
1569	if (len == 0 || len > HV_CONFIG_BLOCK_SIZE_MAX)
1570	return -EINVAL;
1571
1572	init_completion(x: &comp_pkt.host_event);
1573
1574	memset(&pkt, 0, sizeof(pkt));
1575	pkt.pkt.completion_func = hv_pci_write_config_compl;
1576	pkt.pkt.compl_ctxt = &comp_pkt;
1577	write_blk = (struct pci_write_block *)pkt.buf;
1578	write_blk->message_type.type = PCI_WRITE_BLOCK;
1579	write_blk->wslot.slot = devfn_to_wslot(devfn: pdev->devfn);
1580	write_blk->block_id = block_id;
1581	write_blk->byte_count = len;
1582	memcpy(write_blk->bytes, buf, len);
1583	pkt_size = offsetof(struct pci_write_block, bytes) + len;
1584	/*
1585	* This quirk is required on some hosts shipped around 2018, because
1586	* these hosts don't check the pkt_size correctly (new hosts have been
1587	* fixed since early 2019). The quirk is also safe on very old hosts
1588	* and new hosts, because, on them, what really matters is the length
1589	* specified in write_blk->byte_count.
1590	*/
1591	pkt_size += sizeof(pkt.reserved);
1592
1593	ret = vmbus_sendpacket(channel: hbus->hdev->channel, buffer: write_blk, bufferLen: pkt_size,
1594	requestid: (unsigned long)&pkt.pkt, type: VM_PKT_DATA_INBAND,
1595	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
1596	if (ret)
1597	return ret;
1598
1599	ret = wait_for_response(hdev: hbus->hdev, comp: &comp_pkt.host_event);
1600	if (ret)
1601	return ret;
1602
1603	if (comp_pkt.completion_status != 0) {
1604	dev_err(&hbus->hdev->device,
1605	"Write Config Block failed: 0x%x\n",
1606	comp_pkt.completion_status);
1607	return -EIO;
1608	}
1609
1610	return 0;
1611	}
1612
1613	/**
1614	* hv_register_block_invalidate() - Invoked when a config block invalidation
1615	* arrives from the back-end driver.
1616	* @pdev: The PCI driver's representation for this device.
1617	* @context: Identifies the device.
1618	* @block_invalidate: Identifies all of the blocks being invalidated.
1619	*
1620	* Return: 0 on success, -errno on failure
1621	*/
1622	static int hv_register_block_invalidate(struct pci_dev *pdev, void *context,
1623	void (*block_invalidate)(void *context,
1624	u64 block_mask))
1625	{
1626	struct hv_pcibus_device *hbus =
1627	container_of(pdev->bus->sysdata, struct hv_pcibus_device,
1628	sysdata);
1629	struct hv_pci_dev *hpdev;
1630
1631	hpdev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn: pdev->devfn));
1632	if (!hpdev)
1633	return -ENODEV;
1634
1635	hpdev->block_invalidate = block_invalidate;
1636	hpdev->invalidate_context = context;
1637
1638	put_pcichild(hpdev);
1639	return 0;
1640
1641	}
1642
1643	/* Interrupt management hooks */
1644	static void hv_int_desc_free(struct hv_pci_dev *hpdev,
1645	struct tran_int_desc *int_desc)
1646	{
1647	struct pci_delete_interrupt *int_pkt;
1648	struct {
1649	struct pci_packet pkt;
1650	u8 buffer[sizeof(struct pci_delete_interrupt)];
1651	} ctxt;
1652
1653	if (!int_desc->vector_count) {
1654	kfree(objp: int_desc);
1655	return;
1656	}
1657	memset(&ctxt, 0, sizeof(ctxt));
1658	int_pkt = (struct pci_delete_interrupt *)ctxt.buffer;
1659	int_pkt->message_type.type =
1660	PCI_DELETE_INTERRUPT_MESSAGE;
1661	int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
1662	int_pkt->int_desc = *int_desc;
1663	vmbus_sendpacket(channel: hpdev->hbus->hdev->channel, buffer: int_pkt, bufferLen: sizeof(*int_pkt),
1664	requestid: 0, type: VM_PKT_DATA_INBAND, flags: 0);
1665	kfree(objp: int_desc);
1666	}
1667
1668	/**
1669	* hv_msi_free() - Free the MSI.
1670	* @domain: The interrupt domain pointer
1671	* @info: Extra MSI-related context
1672	* @irq: Identifies the IRQ.
1673	*
1674	* The Hyper-V parent partition and hypervisor are tracking the
1675	* messages that are in use, keeping the interrupt redirection
1676	* table up to date. This callback sends a message that frees
1677	* the IRT entry and related tracking nonsense.
1678	*/
1679	static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
1680	unsigned int irq)
1681	{
1682	struct hv_pcibus_device *hbus;
1683	struct hv_pci_dev *hpdev;
1684	struct pci_dev *pdev;
1685	struct tran_int_desc *int_desc;
1686	struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq: irq);
1687	struct msi_desc *msi = irq_data_get_msi_desc(d: irq_data);
1688
1689	pdev = msi_desc_to_pci_dev(desc: msi);
1690	hbus = info->data;
1691	int_desc = irq_data_get_irq_chip_data(d: irq_data);
1692	if (!int_desc)
1693	return;
1694
1695	irq_data->chip_data = NULL;
1696	hpdev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn: pdev->devfn));
1697	if (!hpdev) {
1698	kfree(objp: int_desc);
1699	return;
1700	}
1701
1702	hv_int_desc_free(hpdev, int_desc);
1703	put_pcichild(hpdev);
1704	}
1705
1706	static void hv_irq_mask(struct irq_data *data)
1707	{
1708	pci_msi_mask_irq(data);
1709	if (data->parent_data->chip->irq_mask)
1710	irq_chip_mask_parent(data);
1711	}
1712
1713	static void hv_irq_unmask(struct irq_data *data)
1714	{
1715	hv_arch_irq_unmask(data);
1716
1717	if (data->parent_data->chip->irq_unmask)
1718	irq_chip_unmask_parent(data);
1719	pci_msi_unmask_irq(data);
1720	}
1721
1722	struct compose_comp_ctxt {
1723	struct hv_pci_compl comp_pkt;
1724	struct tran_int_desc int_desc;
1725	};
1726
1727	static void hv_pci_compose_compl(void *context, struct pci_response *resp,
1728	int resp_packet_size)
1729	{
1730	struct compose_comp_ctxt *comp_pkt = context;
1731	struct pci_create_int_response *int_resp =
1732	(struct pci_create_int_response *)resp;
1733
1734	if (resp_packet_size < sizeof(*int_resp)) {
1735	comp_pkt->comp_pkt.completion_status = -1;
1736	goto out;
1737	}
1738	comp_pkt->comp_pkt.completion_status = resp->status;
1739	comp_pkt->int_desc = int_resp->int_desc;
1740	out:
1741	complete(&comp_pkt->comp_pkt.host_event);
1742	}
1743
1744	static u32 hv_compose_msi_req_v1(
1745	struct pci_create_interrupt *int_pkt,
1746	u32 slot, u8 vector, u16 vector_count)
1747	{
1748	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE;
1749	int_pkt->wslot.slot = slot;
1750	int_pkt->int_desc.vector = vector;
1751	int_pkt->int_desc.vector_count = vector_count;
1752	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1753
1754	/*
1755	* Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
1756	* hv_irq_unmask().
1757	*/
1758	int_pkt->int_desc.cpu_mask = CPU_AFFINITY_ALL;
1759
1760	return sizeof(*int_pkt);
1761	}
1762
1763	/*
1764	* The vCPU selected by hv_compose_multi_msi_req_get_cpu() and
1765	* hv_compose_msi_req_get_cpu() is a "dummy" vCPU because the final vCPU to be
1766	* interrupted is specified later in hv_irq_unmask() and communicated to Hyper-V
1767	* via the HVCALL_RETARGET_INTERRUPT hypercall. But the choice of dummy vCPU is
1768	* not irrelevant because Hyper-V chooses the physical CPU to handle the
1769	* interrupts based on the vCPU specified in message sent to the vPCI VSP in
1770	* hv_compose_msi_msg(). Hyper-V's choice of pCPU is not visible to the guest,
1771	* but assigning too many vPCI device interrupts to the same pCPU can cause a
1772	* performance bottleneck. So we spread out the dummy vCPUs to influence Hyper-V
1773	* to spread out the pCPUs that it selects.
1774	*
1775	* For the single-MSI and MSI-X cases, it's OK for hv_compose_msi_req_get_cpu()
1776	* to always return the same dummy vCPU, because a second call to
1777	* hv_compose_msi_msg() contains the "real" vCPU, causing Hyper-V to choose a
1778	* new pCPU for the interrupt. But for the multi-MSI case, the second call to
1779	* hv_compose_msi_msg() exits without sending a message to the vPCI VSP, so the
1780	* original dummy vCPU is used. This dummy vCPU must be round-robin'ed so that
1781	* the pCPUs are spread out. All interrupts for a multi-MSI device end up using
1782	* the same pCPU, even though the vCPUs will be spread out by later calls
1783	* to hv_irq_unmask(), but that is the best we can do now.
1784	*
1785	* With Hyper-V in Nov 2022, the HVCALL_RETARGET_INTERRUPT hypercall does *not*
1786	* cause Hyper-V to reselect the pCPU based on the specified vCPU. Such an
1787	* enhancement is planned for a future version. With that enhancement, the
1788	* dummy vCPU selection won't matter, and interrupts for the same multi-MSI
1789	* device will be spread across multiple pCPUs.
1790	*/
1791
1792	/*
1793	* Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten
1794	* by subsequent retarget in hv_irq_unmask().
1795	*/
1796	static int hv_compose_msi_req_get_cpu(const struct cpumask *affinity)
1797	{
1798	return cpumask_first_and(srcp1: affinity, cpu_online_mask);
1799	}
1800
1801	/*
1802	* Make sure the dummy vCPU values for multi-MSI don't all point to vCPU0.
1803	*/
1804	static int hv_compose_multi_msi_req_get_cpu(void)
1805	{
1806	static DEFINE_SPINLOCK(multi_msi_cpu_lock);
1807
1808	/* -1 means starting with CPU 0 */
1809	static int cpu_next = -1;
1810
1811	unsigned long flags;
1812	int cpu;
1813
1814	spin_lock_irqsave(&multi_msi_cpu_lock, flags);
1815
1816	cpu_next = cpumask_next_wrap(n: cpu_next, cpu_online_mask);
1817	cpu = cpu_next;
1818
1819	spin_unlock_irqrestore(lock: &multi_msi_cpu_lock, flags);
1820
1821	return cpu;
1822	}
1823
1824	static u32 hv_compose_msi_req_v2(
1825	struct pci_create_interrupt2 *int_pkt, int cpu,
1826	u32 slot, u8 vector, u16 vector_count)
1827	{
1828	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE2;
1829	int_pkt->wslot.slot = slot;
1830	int_pkt->int_desc.vector = vector;
1831	int_pkt->int_desc.vector_count = vector_count;
1832	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1833	int_pkt->int_desc.processor_array[0] =
1834	hv_cpu_number_to_vp_number(cpu_number: cpu);
1835	int_pkt->int_desc.processor_count = 1;
1836
1837	return sizeof(*int_pkt);
1838	}
1839
1840	static u32 hv_compose_msi_req_v3(
1841	struct pci_create_interrupt3 *int_pkt, int cpu,
1842	u32 slot, u32 vector, u16 vector_count)
1843	{
1844	int_pkt->message_type.type = PCI_CREATE_INTERRUPT_MESSAGE3;
1845	int_pkt->wslot.slot = slot;
1846	int_pkt->int_desc.vector = vector;
1847	int_pkt->int_desc.reserved = 0;
1848	int_pkt->int_desc.vector_count = vector_count;
1849	int_pkt->int_desc.delivery_mode = DELIVERY_MODE;
1850	int_pkt->int_desc.processor_array[0] =
1851	hv_cpu_number_to_vp_number(cpu_number: cpu);
1852	int_pkt->int_desc.processor_count = 1;
1853
1854	return sizeof(*int_pkt);
1855	}
1856
1857	/**
1858	* hv_compose_msi_msg() - Supplies a valid MSI address/data
1859	* @data: Everything about this MSI
1860	* @msg: Buffer that is filled in by this function
1861	*
1862	* This function unpacks the IRQ looking for target CPU set, IDT
1863	* vector and mode and sends a message to the parent partition
1864	* asking for a mapping for that tuple in this partition. The
1865	* response supplies a data value and address to which that data
1866	* should be written to trigger that interrupt.
1867	*/
1868	static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1869	{
1870	struct hv_pcibus_device *hbus;
1871	struct vmbus_channel *channel;
1872	struct hv_pci_dev *hpdev;
1873	struct pci_bus *pbus;
1874	struct pci_dev *pdev;
1875	const struct cpumask *dest;
1876	struct compose_comp_ctxt comp;
1877	struct tran_int_desc *int_desc;
1878	struct msi_desc *msi_desc;
1879	/*
1880	* vector_count should be u16: see hv_msi_desc, hv_msi_desc2
1881	* and hv_msi_desc3. vector must be u32: see hv_msi_desc3.
1882	*/
1883	u16 vector_count;
1884	u32 vector;
1885	struct {
1886	struct pci_packet pci_pkt;
1887	union {
1888	struct pci_create_interrupt v1;
1889	struct pci_create_interrupt2 v2;
1890	struct pci_create_interrupt3 v3;
1891	} int_pkts;
1892	} __packed ctxt;
1893	bool multi_msi;
1894	u64 trans_id;
1895	u32 size;
1896	int ret;
1897	int cpu;
1898
1899	msi_desc = irq_data_get_msi_desc(d: data);
1900	multi_msi = !msi_desc->pci.msi_attrib.is_msix &&
1901	msi_desc->nvec_used > 1;
1902
1903	/* Reuse the previous allocation */
1904	if (data->chip_data && multi_msi) {
1905	int_desc = data->chip_data;
1906	msg->address_hi = int_desc->address >> 32;
1907	msg->address_lo = int_desc->address & 0xffffffff;
1908	msg->data = int_desc->data;
1909	return;
1910	}
1911
1912	pdev = msi_desc_to_pci_dev(desc: msi_desc);
1913	dest = irq_data_get_effective_affinity_mask(d: data);
1914	pbus = pdev->bus;
1915	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
1916	channel = hbus->hdev->channel;
1917	hpdev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn: pdev->devfn));
1918	if (!hpdev)
1919	goto return_null_message;
1920
1921	/* Free any previous message that might have already been composed. */
1922	if (data->chip_data && !multi_msi) {
1923	int_desc = data->chip_data;
1924	data->chip_data = NULL;
1925	hv_int_desc_free(hpdev, int_desc);
1926	}
1927
1928	int_desc = kzalloc(sizeof(*int_desc), GFP_ATOMIC);
1929	if (!int_desc)
1930	goto drop_reference;
1931
1932	if (multi_msi) {
1933	/*
1934	* If this is not the first MSI of Multi MSI, we already have
1935	* a mapping. Can exit early.
1936	*/
1937	if (msi_desc->irq != data->irq) {
1938	data->chip_data = int_desc;
1939	int_desc->address = msi_desc->msg.address_lo |
1940	(u64)msi_desc->msg.address_hi << 32;
1941	int_desc->data = msi_desc->msg.data +
1942	(data->irq - msi_desc->irq);
1943	msg->address_hi = msi_desc->msg.address_hi;
1944	msg->address_lo = msi_desc->msg.address_lo;
1945	msg->data = int_desc->data;
1946	put_pcichild(hpdev);
1947	return;
1948	}
1949	/*
1950	* The vector we select here is a dummy value. The correct
1951	* value gets sent to the hypervisor in unmask(). This needs
1952	* to be aligned with the count, and also not zero. Multi-msi
1953	* is powers of 2 up to 32, so 32 will always work here.
1954	*/
1955	vector = 32;
1956	vector_count = msi_desc->nvec_used;
1957	cpu = hv_compose_multi_msi_req_get_cpu();
1958	} else {
1959	vector = hv_msi_get_int_vector(data);
1960	vector_count = 1;
1961	cpu = hv_compose_msi_req_get_cpu(affinity: dest);
1962	}
1963
1964	/*
1965	* hv_compose_msi_req_v1 and v2 are for x86 only, meaning 'vector'
1966	* can't exceed u8. Cast 'vector' down to u8 for v1/v2 explicitly
1967	* for better readability.
1968	*/
1969	memset(&ctxt, 0, sizeof(ctxt));
1970	init_completion(x: &comp.comp_pkt.host_event);
1971	ctxt.pci_pkt.completion_func = hv_pci_compose_compl;
1972	ctxt.pci_pkt.compl_ctxt = &comp;
1973
1974	switch (hbus->protocol_version) {
1975	case PCI_PROTOCOL_VERSION_1_1:
1976	size = hv_compose_msi_req_v1(int_pkt: &ctxt.int_pkts.v1,
1977	slot: hpdev->desc.win_slot.slot,
1978	vector: (u8)vector,
1979	vector_count);
1980	break;
1981
1982	case PCI_PROTOCOL_VERSION_1_2:
1983	case PCI_PROTOCOL_VERSION_1_3:
1984	size = hv_compose_msi_req_v2(int_pkt: &ctxt.int_pkts.v2,
1985	cpu,
1986	slot: hpdev->desc.win_slot.slot,
1987	vector: (u8)vector,
1988	vector_count);
1989	break;
1990
1991	case PCI_PROTOCOL_VERSION_1_4:
1992	size = hv_compose_msi_req_v3(int_pkt: &ctxt.int_pkts.v3,
1993	cpu,
1994	slot: hpdev->desc.win_slot.slot,
1995	vector,
1996	vector_count);
1997	break;
1998
1999	default:
2000	/* As we only negotiate protocol versions known to this driver,
2001	* this path should never hit. However, this is it not a hot
2002	* path so we print a message to aid future updates.
2003	*/
2004	dev_err(&hbus->hdev->device,
2005	"Unexpected vPCI protocol, update driver.");
2006	goto free_int_desc;
2007	}
2008
2009	ret = vmbus_sendpacket_getid(channel: hpdev->hbus->hdev->channel, buffer: &ctxt.int_pkts,
2010	bufferLen: size, requestid: (unsigned long)&ctxt.pci_pkt,
2011	trans_id: &trans_id, type: VM_PKT_DATA_INBAND,
2012	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2013	if (ret) {
2014	dev_err(&hbus->hdev->device,
2015	"Sending request for interrupt failed: 0x%x",
2016	comp.comp_pkt.completion_status);
2017	goto free_int_desc;
2018	}
2019
2020	/*
2021	* Prevents hv_pci_onchannelcallback() from running concurrently
2022	* in the tasklet.
2023	*/
2024	tasklet_disable_in_atomic(t: &channel->callback_event);
2025
2026	/*
2027	* Since this function is called with IRQ locks held, can't
2028	* do normal wait for completion; instead poll.
2029	*/
2030	while (!try_wait_for_completion(x: &comp.comp_pkt.host_event)) {
2031	unsigned long flags;
2032
2033	/* 0xFFFF means an invalid PCI VENDOR ID. */
2034	if (hv_pcifront_get_vendor_id(hpdev) == 0xFFFF) {
2035	dev_err_once(&hbus->hdev->device,
2036	"the device has gone\n");
2037	goto enable_tasklet;
2038	}
2039
2040	/*
2041	* Make sure that the ring buffer data structure doesn't get
2042	* freed while we dereference the ring buffer pointer. Test
2043	* for the channel's onchannel_callback being NULL within a
2044	* sched_lock critical section. See also the inline comments
2045	* in vmbus_reset_channel_cb().
2046	*/
2047	spin_lock_irqsave(&channel->sched_lock, flags);
2048	if (unlikely(channel->onchannel_callback == NULL)) {
2049	spin_unlock_irqrestore(lock: &channel->sched_lock, flags);
2050	goto enable_tasklet;
2051	}
2052	hv_pci_onchannelcallback(context: hbus);
2053	spin_unlock_irqrestore(lock: &channel->sched_lock, flags);
2054
2055	udelay(usec: 100);
2056	}
2057
2058	tasklet_enable(t: &channel->callback_event);
2059
2060	if (comp.comp_pkt.completion_status < 0) {
2061	dev_err(&hbus->hdev->device,
2062	"Request for interrupt failed: 0x%x",
2063	comp.comp_pkt.completion_status);
2064	goto free_int_desc;
2065	}
2066
2067	/*
2068	* Record the assignment so that this can be unwound later. Using
2069	* irq_set_chip_data() here would be appropriate, but the lock it takes
2070	* is already held.
2071	*/
2072	*int_desc = comp.int_desc;
2073	data->chip_data = int_desc;
2074
2075	/* Pass up the result. */
2076	msg->address_hi = comp.int_desc.address >> 32;
2077	msg->address_lo = comp.int_desc.address & 0xffffffff;
2078	msg->data = comp.int_desc.data;
2079
2080	put_pcichild(hpdev);
2081	return;
2082
2083	enable_tasklet:
2084	tasklet_enable(t: &channel->callback_event);
2085	/*
2086	* The completion packet on the stack becomes invalid after 'return';
2087	* remove the ID from the VMbus requestor if the identifier is still
2088	* mapped to/associated with the packet. (The identifier could have
2089	* been 're-used', i.e., already removed and (re-)mapped.)
2090	*
2091	* Cf. hv_pci_onchannelcallback().
2092	*/
2093	vmbus_request_addr_match(channel, trans_id, rqst_addr: (unsigned long)&ctxt.pci_pkt);
2094	free_int_desc:
2095	kfree(objp: int_desc);
2096	drop_reference:
2097	put_pcichild(hpdev);
2098	return_null_message:
2099	msg->address_hi = 0;
2100	msg->address_lo = 0;
2101	msg->data = 0;
2102	}
2103
2104	/* HW Interrupt Chip Descriptor */
2105	static struct irq_chip hv_msi_irq_chip = {
2106	.name = "Hyper-V PCIe MSI",
2107	.irq_compose_msi_msg = hv_compose_msi_msg,
2108	.irq_set_affinity = irq_chip_set_affinity_parent,
2109	#ifdef CONFIG_X86
2110	.irq_ack = irq_chip_ack_parent,
2111	.flags = IRQCHIP_MOVE_DEFERRED,
2112	#elif defined(CONFIG_ARM64)
2113	.irq_eoi = irq_chip_eoi_parent,
2114	#endif
2115	.irq_mask = hv_irq_mask,
2116	.irq_unmask = hv_irq_unmask,
2117	};
2118
2119	static struct msi_domain_ops hv_msi_ops = {
2120	.msi_prepare = hv_msi_prepare,
2121	.msi_free = hv_msi_free,
2122	};
2123
2124	/**
2125	* hv_pcie_init_irq_domain() - Initialize IRQ domain
2126	* @hbus: The root PCI bus
2127	*
2128	* This function creates an IRQ domain which will be used for
2129	* interrupts from devices that have been passed through. These
2130	* devices only support MSI and MSI-X, not line-based interrupts
2131	* or simulations of line-based interrupts through PCIe's
2132	* fabric-layer messages. Because interrupts are remapped, we
2133	* can support multi-message MSI here.
2134	*
2135	* Return: '0' on success and error value on failure
2136	*/
2137	static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
2138	{
2139	hbus->msi_info.chip = &hv_msi_irq_chip;
2140	hbus->msi_info.ops = &hv_msi_ops;
2141	hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
2142	MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
2143	MSI_FLAG_PCI_MSIX);
2144	hbus->msi_info.handler = FLOW_HANDLER;
2145	hbus->msi_info.handler_name = FLOW_NAME;
2146	hbus->msi_info.data = hbus;
2147	hbus->irq_domain = pci_msi_create_irq_domain(fwnode: hbus->fwnode,
2148	info: &hbus->msi_info,
2149	parent: hv_pci_get_root_domain());
2150	if (!hbus->irq_domain) {
2151	dev_err(&hbus->hdev->device,
2152	"Failed to build an MSI IRQ domain\n");
2153	return -ENODEV;
2154	}
2155
2156	dev_set_msi_domain(dev: &hbus->bridge->dev, d: hbus->irq_domain);
2157
2158	return 0;
2159	}
2160
2161	/**
2162	* get_bar_size() - Get the address space consumed by a BAR
2163	* @bar_val: Value that a BAR returned after -1 was written
2164	* to it.
2165	*
2166	* This function returns the size of the BAR, rounded up to 1
2167	* page. It has to be rounded up because the hypervisor's page
2168	* table entry that maps the BAR into the VM can't specify an
2169	* offset within a page. The invariant is that the hypervisor
2170	* must place any BARs of smaller than page length at the
2171	* beginning of a page.
2172	*
2173	* Return: Size in bytes of the consumed MMIO space.
2174	*/
2175	static u64 get_bar_size(u64 bar_val)
2176	{
2177	return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
2178	PAGE_SIZE);
2179	}
2180
2181	/**
2182	* survey_child_resources() - Total all MMIO requirements
2183	* @hbus: Root PCI bus, as understood by this driver
2184	*/
2185	static void survey_child_resources(struct hv_pcibus_device *hbus)
2186	{
2187	struct hv_pci_dev *hpdev;
2188	resource_size_t bar_size = 0;
2189	unsigned long flags;
2190	struct completion *event;
2191	u64 bar_val;
2192	int i;
2193
2194	/* If nobody is waiting on the answer, don't compute it. */
2195	event = xchg(&hbus->survey_event, NULL);
2196	if (!event)
2197	return;
2198
2199	/* If the answer has already been computed, go with it. */
2200	if (hbus->low_mmio_space || hbus->high_mmio_space) {
2201	complete(event);
2202	return;
2203	}
2204
2205	spin_lock_irqsave(&hbus->device_list_lock, flags);
2206
2207	/*
2208	* Due to an interesting quirk of the PCI spec, all memory regions
2209	* for a child device are a power of 2 in size and aligned in memory,
2210	* so it's sufficient to just add them up without tracking alignment.
2211	*/
2212	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2213	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2214	if (hpdev->probed_bar[i] & PCI_BASE_ADDRESS_SPACE_IO)
2215	dev_err(&hbus->hdev->device,
2216	"There's an I/O BAR in this list!\n");
2217
2218	if (hpdev->probed_bar[i] != 0) {
2219	/*
2220	* A probed BAR has all the upper bits set that
2221	* can be changed.
2222	*/
2223
2224	bar_val = hpdev->probed_bar[i];
2225	if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
2226	bar_val |=
2227	((u64)hpdev->probed_bar[++i] << 32);
2228	else
2229	bar_val |= 0xffffffff00000000ULL;
2230
2231	bar_size = get_bar_size(bar_val);
2232
2233	if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
2234	hbus->high_mmio_space += bar_size;
2235	else
2236	hbus->low_mmio_space += bar_size;
2237	}
2238	}
2239	}
2240
2241	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2242	complete(event);
2243	}
2244
2245	/**
2246	* prepopulate_bars() - Fill in BARs with defaults
2247	* @hbus: Root PCI bus, as understood by this driver
2248	*
2249	* The core PCI driver code seems much, much happier if the BARs
2250	* for a device have values upon first scan. So fill them in.
2251	* The algorithm below works down from large sizes to small,
2252	* attempting to pack the assignments optimally. The assumption,
2253	* enforced in other parts of the code, is that the beginning of
2254	* the memory-mapped I/O space will be aligned on the largest
2255	* BAR size.
2256	*/
2257	static void prepopulate_bars(struct hv_pcibus_device *hbus)
2258	{
2259	resource_size_t high_size = 0;
2260	resource_size_t low_size = 0;
2261	resource_size_t high_base = 0;
2262	resource_size_t low_base = 0;
2263	resource_size_t bar_size;
2264	struct hv_pci_dev *hpdev;
2265	unsigned long flags;
2266	u64 bar_val;
2267	u32 command;
2268	bool high;
2269	int i;
2270
2271	if (hbus->low_mmio_space) {
2272	low_size = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
2273	low_base = hbus->low_mmio_res->start;
2274	}
2275
2276	if (hbus->high_mmio_space) {
2277	high_size = 1ULL <<
2278	(63 - __builtin_clzll(hbus->high_mmio_space));
2279	high_base = hbus->high_mmio_res->start;
2280	}
2281
2282	spin_lock_irqsave(&hbus->device_list_lock, flags);
2283
2284	/*
2285	* Clear the memory enable bit, in case it's already set. This occurs
2286	* in the suspend path of hibernation, where the device is suspended,
2287	* resumed and suspended again: see hibernation_snapshot() and
2288	* hibernation_platform_enter().
2289	*
2290	* If the memory enable bit is already set, Hyper-V silently ignores
2291	* the below BAR updates, and the related PCI device driver can not
2292	* work, because reading from the device register(s) always returns
2293	* 0xFFFFFFFF (PCI_ERROR_RESPONSE).
2294	*/
2295	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2296	_hv_pcifront_read_config(hpdev, PCI_COMMAND, size: 2, val: &command);
2297	command &= ~PCI_COMMAND_MEMORY;
2298	_hv_pcifront_write_config(hpdev, PCI_COMMAND, size: 2, val: command);
2299	}
2300
2301	/* Pick addresses for the BARs. */
2302	do {
2303	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2304	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2305	bar_val = hpdev->probed_bar[i];
2306	if (bar_val == 0)
2307	continue;
2308	high = bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64;
2309	if (high) {
2310	bar_val |=
2311	((u64)hpdev->probed_bar[i + 1]
2312	<< 32);
2313	} else {
2314	bar_val |= 0xffffffffULL << 32;
2315	}
2316	bar_size = get_bar_size(bar_val);
2317	if (high) {
2318	if (high_size != bar_size) {
2319	i++;
2320	continue;
2321	}
2322	_hv_pcifront_write_config(hpdev,
2323	PCI_BASE_ADDRESS_0 + (4 * i),
2324	size: 4,
2325	val: (u32)(high_base & 0xffffff00));
2326	i++;
2327	_hv_pcifront_write_config(hpdev,
2328	PCI_BASE_ADDRESS_0 + (4 * i),
2329	size: 4, val: (u32)(high_base >> 32));
2330	high_base += bar_size;
2331	} else {
2332	if (low_size != bar_size)
2333	continue;
2334	_hv_pcifront_write_config(hpdev,
2335	PCI_BASE_ADDRESS_0 + (4 * i),
2336	size: 4,
2337	val: (u32)(low_base & 0xffffff00));
2338	low_base += bar_size;
2339	}
2340	}
2341	if (high_size <= 1 && low_size <= 1) {
2342	/*
2343	* No need to set the PCI_COMMAND_MEMORY bit as
2344	* the core PCI driver doesn't require the bit
2345	* to be pre-set. Actually here we intentionally
2346	* keep the bit off so that the PCI BAR probing
2347	* in the core PCI driver doesn't cause Hyper-V
2348	* to unnecessarily unmap/map the virtual BARs
2349	* from/to the physical BARs multiple times.
2350	* This reduces the VM boot time significantly
2351	* if the BAR sizes are huge.
2352	*/
2353	break;
2354	}
2355	}
2356
2357	high_size >>= 1;
2358	low_size >>= 1;
2359	} while (high_size || low_size);
2360
2361	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2362	}
2363
2364	/*
2365	* Assign entries in sysfs pci slot directory.
2366	*
2367	* Note that this function does not need to lock the children list
2368	* because it is called from pci_devices_present_work which
2369	* is serialized with hv_eject_device_work because they are on the
2370	* same ordered workqueue. Therefore hbus->children list will not change
2371	* even when pci_create_slot sleeps.
2372	*/
2373	static void hv_pci_assign_slots(struct hv_pcibus_device *hbus)
2374	{
2375	struct hv_pci_dev *hpdev;
2376	char name[SLOT_NAME_SIZE];
2377	int slot_nr;
2378
2379	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2380	if (hpdev->pci_slot)
2381	continue;
2382
2383	slot_nr = PCI_SLOT(wslot_to_devfn(hpdev->desc.win_slot.slot));
2384	snprintf(buf: name, SLOT_NAME_SIZE, fmt: "%u", hpdev->desc.ser);
2385	hpdev->pci_slot = pci_create_slot(parent: hbus->bridge->bus, slot_nr,
2386	name, NULL);
2387	if (IS_ERR(ptr: hpdev->pci_slot)) {
2388	pr_warn("pci_create slot %s failed\n", name);
2389	hpdev->pci_slot = NULL;
2390	}
2391	}
2392	}
2393
2394	/*
2395	* Remove entries in sysfs pci slot directory.
2396	*/
2397	static void hv_pci_remove_slots(struct hv_pcibus_device *hbus)
2398	{
2399	struct hv_pci_dev *hpdev;
2400
2401	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2402	if (!hpdev->pci_slot)
2403	continue;
2404	pci_destroy_slot(slot: hpdev->pci_slot);
2405	hpdev->pci_slot = NULL;
2406	}
2407	}
2408
2409	/*
2410	* Set NUMA node for the devices on the bus
2411	*/
2412	static void hv_pci_assign_numa_node(struct hv_pcibus_device *hbus)
2413	{
2414	struct pci_dev *dev;
2415	struct pci_bus *bus = hbus->bridge->bus;
2416	struct hv_pci_dev *hv_dev;
2417
2418	list_for_each_entry(dev, &bus->devices, bus_list) {
2419	hv_dev = get_pcichild_wslot(hbus, wslot: devfn_to_wslot(devfn: dev->devfn));
2420	if (!hv_dev)
2421	continue;
2422
2423	if (hv_dev->desc.flags & HV_PCI_DEVICE_FLAG_NUMA_AFFINITY &&
2424	hv_dev->desc.virtual_numa_node < num_possible_nodes())
2425	/*
2426	* The kernel may boot with some NUMA nodes offline
2427	* (e.g. in a KDUMP kernel) or with NUMA disabled via
2428	* "numa=off". In those cases, adjust the host provided
2429	* NUMA node to a valid NUMA node used by the kernel.
2430	*/
2431	set_dev_node(dev: &dev->dev,
2432	numa_map_to_online_node(
2433	hv_dev->desc.virtual_numa_node));
2434
2435	put_pcichild(hpdev: hv_dev);
2436	}
2437	}
2438
2439	/**
2440	* create_root_hv_pci_bus() - Expose a new root PCI bus
2441	* @hbus: Root PCI bus, as understood by this driver
2442	*
2443	* Return: 0 on success, -errno on failure
2444	*/
2445	static int create_root_hv_pci_bus(struct hv_pcibus_device *hbus)
2446	{
2447	int error;
2448	struct pci_host_bridge *bridge = hbus->bridge;
2449
2450	bridge->dev.parent = &hbus->hdev->device;
2451	bridge->sysdata = &hbus->sysdata;
2452	bridge->ops = &hv_pcifront_ops;
2453
2454	error = pci_scan_root_bus_bridge(bridge);
2455	if (error)
2456	return error;
2457
2458	pci_lock_rescan_remove();
2459	hv_pci_assign_numa_node(hbus);
2460	pci_bus_assign_resources(bus: bridge->bus);
2461	hv_pci_assign_slots(hbus);
2462	pci_bus_add_devices(bus: bridge->bus);
2463	pci_unlock_rescan_remove();
2464	hbus->state = hv_pcibus_installed;
2465	return 0;
2466	}
2467
2468	struct q_res_req_compl {
2469	struct completion host_event;
2470	struct hv_pci_dev *hpdev;
2471	};
2472
2473	/**
2474	* q_resource_requirements() - Query Resource Requirements
2475	* @context: The completion context.
2476	* @resp: The response that came from the host.
2477	* @resp_packet_size: The size in bytes of resp.
2478	*
2479	* This function is invoked on completion of a Query Resource
2480	* Requirements packet.
2481	*/
2482	static void q_resource_requirements(void *context, struct pci_response *resp,
2483	int resp_packet_size)
2484	{
2485	struct q_res_req_compl *completion = context;
2486	struct pci_q_res_req_response *q_res_req =
2487	(struct pci_q_res_req_response *)resp;
2488	s32 status;
2489	int i;
2490
2491	status = (resp_packet_size < sizeof(*q_res_req)) ? -1 : resp->status;
2492	if (status < 0) {
2493	dev_err(&completion->hpdev->hbus->hdev->device,
2494	"query resource requirements failed: %x\n",
2495	status);
2496	} else {
2497	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
2498	completion->hpdev->probed_bar[i] =
2499	q_res_req->probed_bar[i];
2500	}
2501	}
2502
2503	complete(&completion->host_event);
2504	}
2505
2506	/**
2507	* new_pcichild_device() - Create a new child device
2508	* @hbus: The internal struct tracking this root PCI bus.
2509	* @desc: The information supplied so far from the host
2510	* about the device.
2511	*
2512	* This function creates the tracking structure for a new child
2513	* device and kicks off the process of figuring out what it is.
2514	*
2515	* Return: Pointer to the new tracking struct
2516	*/
2517	static struct hv_pci_dev *new_pcichild_device(struct hv_pcibus_device *hbus,
2518	struct hv_pcidev_description *desc)
2519	{
2520	struct hv_pci_dev *hpdev;
2521	struct pci_child_message *res_req;
2522	struct q_res_req_compl comp_pkt;
2523	struct {
2524	struct pci_packet init_packet;
2525	u8 buffer[sizeof(struct pci_child_message)];
2526	} pkt;
2527	unsigned long flags;
2528	int ret;
2529
2530	hpdev = kzalloc(sizeof(*hpdev), GFP_KERNEL);
2531	if (!hpdev)
2532	return NULL;
2533
2534	hpdev->hbus = hbus;
2535
2536	memset(&pkt, 0, sizeof(pkt));
2537	init_completion(x: &comp_pkt.host_event);
2538	comp_pkt.hpdev = hpdev;
2539	pkt.init_packet.compl_ctxt = &comp_pkt;
2540	pkt.init_packet.completion_func = q_resource_requirements;
2541	res_req = (struct pci_child_message *)pkt.buffer;
2542	res_req->message_type.type = PCI_QUERY_RESOURCE_REQUIREMENTS;
2543	res_req->wslot.slot = desc->win_slot.slot;
2544
2545	ret = vmbus_sendpacket(channel: hbus->hdev->channel, buffer: res_req,
2546	bufferLen: sizeof(struct pci_child_message),
2547	requestid: (unsigned long)&pkt.init_packet,
2548	type: VM_PKT_DATA_INBAND,
2549	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
2550	if (ret)
2551	goto error;
2552
2553	if (wait_for_response(hdev: hbus->hdev, comp: &comp_pkt.host_event))
2554	goto error;
2555
2556	hpdev->desc = *desc;
2557	refcount_set(r: &hpdev->refs, n: 1);
2558	get_pcichild(hpdev);
2559	spin_lock_irqsave(&hbus->device_list_lock, flags);
2560
2561	list_add_tail(new: &hpdev->list_entry, head: &hbus->children);
2562	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2563	return hpdev;
2564
2565	error:
2566	kfree(objp: hpdev);
2567	return NULL;
2568	}
2569
2570	/**
2571	* get_pcichild_wslot() - Find device from slot
2572	* @hbus: Root PCI bus, as understood by this driver
2573	* @wslot: Location on the bus
2574	*
2575	* This function looks up a PCI device and returns the internal
2576	* representation of it. It acquires a reference on it, so that
2577	* the device won't be deleted while somebody is using it. The
2578	* caller is responsible for calling put_pcichild() to release
2579	* this reference.
2580	*
2581	* Return: Internal representation of a PCI device
2582	*/
2583	static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
2584	u32 wslot)
2585	{
2586	unsigned long flags;
2587	struct hv_pci_dev *iter, *hpdev = NULL;
2588
2589	spin_lock_irqsave(&hbus->device_list_lock, flags);
2590	list_for_each_entry(iter, &hbus->children, list_entry) {
2591	if (iter->desc.win_slot.slot == wslot) {
2592	hpdev = iter;
2593	get_pcichild(hpdev);
2594	break;
2595	}
2596	}
2597	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2598
2599	return hpdev;
2600	}
2601
2602	/**
2603	* pci_devices_present_work() - Handle new list of child devices
2604	* @work: Work struct embedded in struct hv_dr_work
2605	*
2606	* "Bus Relations" is the Windows term for "children of this
2607	* bus." The terminology is preserved here for people trying to
2608	* debug the interaction between Hyper-V and Linux. This
2609	* function is called when the parent partition reports a list
2610	* of functions that should be observed under this PCI Express
2611	* port (bus).
2612	*
2613	* This function updates the list, and must tolerate being
2614	* called multiple times with the same information. The typical
2615	* number of child devices is one, with very atypical cases
2616	* involving three or four, so the algorithms used here can be
2617	* simple and inefficient.
2618	*
2619	* It must also treat the omission of a previously observed device as
2620	* notification that the device no longer exists.
2621	*
2622	* Note that this function is serialized with hv_eject_device_work(),
2623	* because both are pushed to the ordered workqueue hbus->wq.
2624	*/
2625	static void pci_devices_present_work(struct work_struct *work)
2626	{
2627	u32 child_no;
2628	bool found;
2629	struct hv_pcidev_description *new_desc;
2630	struct hv_pci_dev *hpdev;
2631	struct hv_pcibus_device *hbus;
2632	struct list_head removed;
2633	struct hv_dr_work *dr_wrk;
2634	struct hv_dr_state *dr = NULL;
2635	unsigned long flags;
2636
2637	dr_wrk = container_of(work, struct hv_dr_work, wrk);
2638	hbus = dr_wrk->bus;
2639	kfree(objp: dr_wrk);
2640
2641	INIT_LIST_HEAD(list: &removed);
2642
2643	/* Pull this off the queue and process it if it was the last one. */
2644	spin_lock_irqsave(&hbus->device_list_lock, flags);
2645	while (!list_empty(head: &hbus->dr_list)) {
2646	dr = list_first_entry(&hbus->dr_list, struct hv_dr_state,
2647	list_entry);
2648	list_del(entry: &dr->list_entry);
2649
2650	/* Throw this away if the list still has stuff in it. */
2651	if (!list_empty(head: &hbus->dr_list)) {
2652	kfree(objp: dr);
2653	continue;
2654	}
2655	}
2656	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2657
2658	if (!dr)
2659	return;
2660
2661	mutex_lock(&hbus->state_lock);
2662
2663	/* First, mark all existing children as reported missing. */
2664	spin_lock_irqsave(&hbus->device_list_lock, flags);
2665	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2666	hpdev->reported_missing = true;
2667	}
2668	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2669
2670	/* Next, add back any reported devices. */
2671	for (child_no = 0; child_no < dr->device_count; child_no++) {
2672	found = false;
2673	new_desc = &dr->func[child_no];
2674
2675	spin_lock_irqsave(&hbus->device_list_lock, flags);
2676	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2677	if ((hpdev->desc.win_slot.slot == new_desc->win_slot.slot) &&
2678	(hpdev->desc.v_id == new_desc->v_id) &&
2679	(hpdev->desc.d_id == new_desc->d_id) &&
2680	(hpdev->desc.ser == new_desc->ser)) {
2681	hpdev->reported_missing = false;
2682	found = true;
2683	}
2684	}
2685	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2686
2687	if (!found) {
2688	hpdev = new_pcichild_device(hbus, desc: new_desc);
2689	if (!hpdev)
2690	dev_err(&hbus->hdev->device,
2691	"couldn't record a child device.\n");
2692	}
2693	}
2694
2695	/* Move missing children to a list on the stack. */
2696	spin_lock_irqsave(&hbus->device_list_lock, flags);
2697	do {
2698	found = false;
2699	list_for_each_entry(hpdev, &hbus->children, list_entry) {
2700	if (hpdev->reported_missing) {
2701	found = true;
2702	put_pcichild(hpdev);
2703	list_move_tail(list: &hpdev->list_entry, head: &removed);
2704	break;
2705	}
2706	}
2707	} while (found);
2708	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2709
2710	/* Delete everything that should no longer exist. */
2711	while (!list_empty(head: &removed)) {
2712	hpdev = list_first_entry(&removed, struct hv_pci_dev,
2713	list_entry);
2714	list_del(entry: &hpdev->list_entry);
2715
2716	if (hpdev->pci_slot)
2717	pci_destroy_slot(slot: hpdev->pci_slot);
2718
2719	put_pcichild(hpdev);
2720	}
2721
2722	switch (hbus->state) {
2723	case hv_pcibus_installed:
2724	/*
2725	* Tell the core to rescan bus
2726	* because there may have been changes.
2727	*/
2728	pci_lock_rescan_remove();
2729	pci_scan_child_bus(bus: hbus->bridge->bus);
2730	hv_pci_assign_numa_node(hbus);
2731	hv_pci_assign_slots(hbus);
2732	pci_unlock_rescan_remove();
2733	break;
2734
2735	case hv_pcibus_init:
2736	case hv_pcibus_probed:
2737	survey_child_resources(hbus);
2738	break;
2739
2740	default:
2741	break;
2742	}
2743
2744	mutex_unlock(lock: &hbus->state_lock);
2745
2746	kfree(objp: dr);
2747	}
2748
2749	/**
2750	* hv_pci_start_relations_work() - Queue work to start device discovery
2751	* @hbus: Root PCI bus, as understood by this driver
2752	* @dr: The list of children returned from host
2753	*
2754	* Return: 0 on success, -errno on failure
2755	*/
2756	static int hv_pci_start_relations_work(struct hv_pcibus_device *hbus,
2757	struct hv_dr_state *dr)
2758	{
2759	struct hv_dr_work *dr_wrk;
2760	unsigned long flags;
2761	bool pending_dr;
2762
2763	if (hbus->state == hv_pcibus_removing) {
2764	dev_info(&hbus->hdev->device,
2765	"PCI VMBus BUS_RELATIONS: ignored\n");
2766	return -ENOENT;
2767	}
2768
2769	dr_wrk = kzalloc(sizeof(*dr_wrk), GFP_NOWAIT);
2770	if (!dr_wrk)
2771	return -ENOMEM;
2772
2773	INIT_WORK(&dr_wrk->wrk, pci_devices_present_work);
2774	dr_wrk->bus = hbus;
2775
2776	spin_lock_irqsave(&hbus->device_list_lock, flags);
2777	/*
2778	* If pending_dr is true, we have already queued a work,
2779	* which will see the new dr. Otherwise, we need to
2780	* queue a new work.
2781	*/
2782	pending_dr = !list_empty(head: &hbus->dr_list);
2783	list_add_tail(new: &dr->list_entry, head: &hbus->dr_list);
2784	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2785
2786	if (pending_dr)
2787	kfree(objp: dr_wrk);
2788	else
2789	queue_work(wq: hbus->wq, work: &dr_wrk->wrk);
2790
2791	return 0;
2792	}
2793
2794	/**
2795	* hv_pci_devices_present() - Handle list of new children
2796	* @hbus: Root PCI bus, as understood by this driver
2797	* @relations: Packet from host listing children
2798	*
2799	* Process a new list of devices on the bus. The list of devices is
2800	* discovered by VSP and sent to us via VSP message PCI_BUS_RELATIONS,
2801	* whenever a new list of devices for this bus appears.
2802	*/
2803	static void hv_pci_devices_present(struct hv_pcibus_device *hbus,
2804	struct pci_bus_relations *relations)
2805	{
2806	struct hv_dr_state *dr;
2807	int i;
2808
2809	dr = kzalloc(struct_size(dr, func, relations->device_count),
2810	GFP_NOWAIT);
2811	if (!dr)
2812	return;
2813
2814	dr->device_count = relations->device_count;
2815	for (i = 0; i < dr->device_count; i++) {
2816	dr->func[i].v_id = relations->func[i].v_id;
2817	dr->func[i].d_id = relations->func[i].d_id;
2818	dr->func[i].rev = relations->func[i].rev;
2819	dr->func[i].prog_intf = relations->func[i].prog_intf;
2820	dr->func[i].subclass = relations->func[i].subclass;
2821	dr->func[i].base_class = relations->func[i].base_class;
2822	dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2823	dr->func[i].win_slot = relations->func[i].win_slot;
2824	dr->func[i].ser = relations->func[i].ser;
2825	}
2826
2827	if (hv_pci_start_relations_work(hbus, dr))
2828	kfree(objp: dr);
2829	}
2830
2831	/**
2832	* hv_pci_devices_present2() - Handle list of new children
2833	* @hbus: Root PCI bus, as understood by this driver
2834	* @relations: Packet from host listing children
2835	*
2836	* This function is the v2 version of hv_pci_devices_present()
2837	*/
2838	static void hv_pci_devices_present2(struct hv_pcibus_device *hbus,
2839	struct pci_bus_relations2 *relations)
2840	{
2841	struct hv_dr_state *dr;
2842	int i;
2843
2844	dr = kzalloc(struct_size(dr, func, relations->device_count),
2845	GFP_NOWAIT);
2846	if (!dr)
2847	return;
2848
2849	dr->device_count = relations->device_count;
2850	for (i = 0; i < dr->device_count; i++) {
2851	dr->func[i].v_id = relations->func[i].v_id;
2852	dr->func[i].d_id = relations->func[i].d_id;
2853	dr->func[i].rev = relations->func[i].rev;
2854	dr->func[i].prog_intf = relations->func[i].prog_intf;
2855	dr->func[i].subclass = relations->func[i].subclass;
2856	dr->func[i].base_class = relations->func[i].base_class;
2857	dr->func[i].subsystem_id = relations->func[i].subsystem_id;
2858	dr->func[i].win_slot = relations->func[i].win_slot;
2859	dr->func[i].ser = relations->func[i].ser;
2860	dr->func[i].flags = relations->func[i].flags;
2861	dr->func[i].virtual_numa_node =
2862	relations->func[i].virtual_numa_node;
2863	}
2864
2865	if (hv_pci_start_relations_work(hbus, dr))
2866	kfree(objp: dr);
2867	}
2868
2869	/**
2870	* hv_eject_device_work() - Asynchronously handles ejection
2871	* @work: Work struct embedded in internal device struct
2872	*
2873	* This function handles ejecting a device. Windows will
2874	* attempt to gracefully eject a device, waiting 60 seconds to
2875	* hear back from the guest OS that this completed successfully.
2876	* If this timer expires, the device will be forcibly removed.
2877	*/
2878	static void hv_eject_device_work(struct work_struct *work)
2879	{
2880	struct pci_eject_response *ejct_pkt;
2881	struct hv_pcibus_device *hbus;
2882	struct hv_pci_dev *hpdev;
2883	struct pci_dev *pdev;
2884	unsigned long flags;
2885	int wslot;
2886	struct {
2887	struct pci_packet pkt;
2888	u8 buffer[sizeof(struct pci_eject_response)];
2889	} ctxt;
2890
2891	hpdev = container_of(work, struct hv_pci_dev, wrk);
2892	hbus = hpdev->hbus;
2893
2894	mutex_lock(&hbus->state_lock);
2895
2896	/*
2897	* Ejection can come before or after the PCI bus has been set up, so
2898	* attempt to find it and tear down the bus state, if it exists. This
2899	* must be done without constructs like pci_domain_nr(hbus->bridge->bus)
2900	* because hbus->bridge->bus may not exist yet.
2901	*/
2902	wslot = wslot_to_devfn(wslot: hpdev->desc.win_slot.slot);
2903	pdev = pci_get_domain_bus_and_slot(domain: hbus->bridge->domain_nr, bus: 0, devfn: wslot);
2904	if (pdev) {
2905	pci_lock_rescan_remove();
2906	pci_stop_and_remove_bus_device(dev: pdev);
2907	pci_dev_put(dev: pdev);
2908	pci_unlock_rescan_remove();
2909	}
2910
2911	spin_lock_irqsave(&hbus->device_list_lock, flags);
2912	list_del(entry: &hpdev->list_entry);
2913	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
2914
2915	if (hpdev->pci_slot)
2916	pci_destroy_slot(slot: hpdev->pci_slot);
2917
2918	memset(&ctxt, 0, sizeof(ctxt));
2919	ejct_pkt = (struct pci_eject_response *)ctxt.buffer;
2920	ejct_pkt->message_type.type = PCI_EJECTION_COMPLETE;
2921	ejct_pkt->wslot.slot = hpdev->desc.win_slot.slot;
2922	vmbus_sendpacket(channel: hbus->hdev->channel, buffer: ejct_pkt,
2923	bufferLen: sizeof(*ejct_pkt), requestid: 0,
2924	type: VM_PKT_DATA_INBAND, flags: 0);
2925
2926	/* For the get_pcichild() in hv_pci_eject_device() */
2927	put_pcichild(hpdev);
2928	/* For the two refs got in new_pcichild_device() */
2929	put_pcichild(hpdev);
2930	put_pcichild(hpdev);
2931	/* hpdev has been freed. Do not use it any more. */
2932
2933	mutex_unlock(lock: &hbus->state_lock);
2934	}
2935
2936	/**
2937	* hv_pci_eject_device() - Handles device ejection
2938	* @hpdev: Internal device tracking struct
2939	*
2940	* This function is invoked when an ejection packet arrives. It
2941	* just schedules work so that we don't re-enter the packet
2942	* delivery code handling the ejection.
2943	*/
2944	static void hv_pci_eject_device(struct hv_pci_dev *hpdev)
2945	{
2946	struct hv_pcibus_device *hbus = hpdev->hbus;
2947	struct hv_device *hdev = hbus->hdev;
2948
2949	if (hbus->state == hv_pcibus_removing) {
2950	dev_info(&hdev->device, "PCI VMBus EJECT: ignored\n");
2951	return;
2952	}
2953
2954	get_pcichild(hpdev);
2955	INIT_WORK(&hpdev->wrk, hv_eject_device_work);
2956	queue_work(wq: hbus->wq, work: &hpdev->wrk);
2957	}
2958
2959	/**
2960	* hv_pci_onchannelcallback() - Handles incoming packets
2961	* @context: Internal bus tracking struct
2962	*
2963	* This function is invoked whenever the host sends a packet to
2964	* this channel (which is private to this root PCI bus).
2965	*/
2966	static void hv_pci_onchannelcallback(void *context)
2967	{
2968	const int packet_size = 0x100;
2969	int ret;
2970	struct hv_pcibus_device *hbus = context;
2971	struct vmbus_channel *chan = hbus->hdev->channel;
2972	u32 bytes_recvd;
2973	u64 req_id, req_addr;
2974	struct vmpacket_descriptor *desc;
2975	unsigned char *buffer;
2976	int bufferlen = packet_size;
2977	struct pci_packet *comp_packet;
2978	struct pci_response *response;
2979	struct pci_incoming_message *new_message;
2980	struct pci_bus_relations *bus_rel;
2981	struct pci_bus_relations2 *bus_rel2;
2982	struct pci_dev_inval_block *inval;
2983	struct pci_dev_incoming *dev_message;
2984	struct hv_pci_dev *hpdev;
2985	unsigned long flags;
2986
2987	buffer = kmalloc(bufferlen, GFP_ATOMIC);
2988	if (!buffer)
2989	return;
2990
2991	while (1) {
2992	ret = vmbus_recvpacket_raw(channel: chan, buffer, bufferlen,
2993	buffer_actual_len: &bytes_recvd, requestid: &req_id);
2994
2995	if (ret == -ENOBUFS) {
2996	kfree(objp: buffer);
2997	/* Handle large packet */
2998	bufferlen = bytes_recvd;
2999	buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
3000	if (!buffer)
3001	return;
3002	continue;
3003	}
3004
3005	/* Zero length indicates there are no more packets. */
3006	if (ret || !bytes_recvd)
3007	break;
3008
3009	/*
3010	* All incoming packets must be at least as large as a
3011	* response.
3012	*/
3013	if (bytes_recvd <= sizeof(struct pci_response))
3014	continue;
3015	desc = (struct vmpacket_descriptor *)buffer;
3016
3017	switch (desc->type) {
3018	case VM_PKT_COMP:
3019
3020	lock_requestor(chan, flags);
3021	req_addr = __vmbus_request_addr_match(channel: chan, trans_id: req_id,
3022	VMBUS_RQST_ADDR_ANY);
3023	if (req_addr == VMBUS_RQST_ERROR) {
3024	unlock_requestor(channel: chan, flags);
3025	dev_err(&hbus->hdev->device,
3026	"Invalid transaction ID %llx\n",
3027	req_id);
3028	break;
3029	}
3030	comp_packet = (struct pci_packet *)req_addr;
3031	response = (struct pci_response *)buffer;
3032	/*
3033	* Call ->completion_func() within the critical section to make
3034	* sure that the packet pointer is still valid during the call:
3035	* here 'valid' means that there's a task still waiting for the
3036	* completion, and that the packet data is still on the waiting
3037	* task's stack. Cf. hv_compose_msi_msg().
3038	*/
3039	comp_packet->completion_func(comp_packet->compl_ctxt,
3040	response,
3041	bytes_recvd);
3042	unlock_requestor(channel: chan, flags);
3043	break;
3044
3045	case VM_PKT_DATA_INBAND:
3046
3047	new_message = (struct pci_incoming_message *)buffer;
3048	switch (new_message->message_type.type) {
3049	case PCI_BUS_RELATIONS:
3050
3051	bus_rel = (struct pci_bus_relations *)buffer;
3052	if (bytes_recvd < sizeof(*bus_rel) ||
3053	bytes_recvd <
3054	struct_size(bus_rel, func,
3055	bus_rel->device_count)) {
3056	dev_err(&hbus->hdev->device,
3057	"bus relations too small\n");
3058	break;
3059	}
3060
3061	hv_pci_devices_present(hbus, relations: bus_rel);
3062	break;
3063
3064	case PCI_BUS_RELATIONS2:
3065
3066	bus_rel2 = (struct pci_bus_relations2 *)buffer;
3067	if (bytes_recvd < sizeof(*bus_rel2) ||
3068	bytes_recvd <
3069	struct_size(bus_rel2, func,
3070	bus_rel2->device_count)) {
3071	dev_err(&hbus->hdev->device,
3072	"bus relations v2 too small\n");
3073	break;
3074	}
3075
3076	hv_pci_devices_present2(hbus, relations: bus_rel2);
3077	break;
3078
3079	case PCI_EJECT:
3080
3081	dev_message = (struct pci_dev_incoming *)buffer;
3082	if (bytes_recvd < sizeof(*dev_message)) {
3083	dev_err(&hbus->hdev->device,
3084	"eject message too small\n");
3085	break;
3086	}
3087	hpdev = get_pcichild_wslot(hbus,
3088	wslot: dev_message->wslot.slot);
3089	if (hpdev) {
3090	hv_pci_eject_device(hpdev);
3091	put_pcichild(hpdev);
3092	}
3093	break;
3094
3095	case PCI_INVALIDATE_BLOCK:
3096
3097	inval = (struct pci_dev_inval_block *)buffer;
3098	if (bytes_recvd < sizeof(*inval)) {
3099	dev_err(&hbus->hdev->device,
3100	"invalidate message too small\n");
3101	break;
3102	}
3103	hpdev = get_pcichild_wslot(hbus,
3104	wslot: inval->wslot.slot);
3105	if (hpdev) {
3106	if (hpdev->block_invalidate) {
3107	hpdev->block_invalidate(
3108	hpdev->invalidate_context,
3109	inval->block_mask);
3110	}
3111	put_pcichild(hpdev);
3112	}
3113	break;
3114
3115	default:
3116	dev_warn(&hbus->hdev->device,
3117	"Unimplemented protocol message %x\n",
3118	new_message->message_type.type);
3119	break;
3120	}
3121	break;
3122
3123	default:
3124	dev_err(&hbus->hdev->device,
3125	"unhandled packet type %d, tid %llx len %d\n",
3126	desc->type, req_id, bytes_recvd);
3127	break;
3128	}
3129	}
3130
3131	kfree(objp: buffer);
3132	}
3133
3134	/**
3135	* hv_pci_protocol_negotiation() - Set up protocol
3136	* @hdev: VMBus's tracking struct for this root PCI bus.
3137	* @version: Array of supported channel protocol versions in
3138	* the order of probing - highest go first.
3139	* @num_version: Number of elements in the version array.
3140	*
3141	* This driver is intended to support running on Windows 10
3142	* (server) and later versions. It will not run on earlier
3143	* versions, as they assume that many of the operations which
3144	* Linux needs accomplished with a spinlock held were done via
3145	* asynchronous messaging via VMBus. Windows 10 increases the
3146	* surface area of PCI emulation so that these actions can take
3147	* place by suspending a virtual processor for their duration.
3148	*
3149	* This function negotiates the channel protocol version,
3150	* failing if the host doesn't support the necessary protocol
3151	* level.
3152	*/
3153	static int hv_pci_protocol_negotiation(struct hv_device *hdev,
3154	enum pci_protocol_version_t version[],
3155	int num_version)
3156	{
3157	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3158	struct pci_version_request *version_req;
3159	struct hv_pci_compl comp_pkt;
3160	struct pci_packet *pkt;
3161	int ret;
3162	int i;
3163
3164	/*
3165	* Initiate the handshake with the host and negotiate
3166	* a version that the host can support. We start with the
3167	* highest version number and go down if the host cannot
3168	* support it.
3169	*/
3170	pkt = kzalloc(sizeof(*pkt) + sizeof(*version_req), GFP_KERNEL);
3171	if (!pkt)
3172	return -ENOMEM;
3173
3174	init_completion(x: &comp_pkt.host_event);
3175	pkt->completion_func = hv_pci_generic_compl;
3176	pkt->compl_ctxt = &comp_pkt;
3177	version_req = (struct pci_version_request *)(pkt + 1);
3178	version_req->message_type.type = PCI_QUERY_PROTOCOL_VERSION;
3179
3180	for (i = 0; i < num_version; i++) {
3181	version_req->protocol_version = version[i];
3182	ret = vmbus_sendpacket(channel: hdev->channel, buffer: version_req,
3183	bufferLen: sizeof(struct pci_version_request),
3184	requestid: (unsigned long)pkt, type: VM_PKT_DATA_INBAND,
3185	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3186	if (!ret)
3187	ret = wait_for_response(hdev, comp: &comp_pkt.host_event);
3188
3189	if (ret) {
3190	dev_err(&hdev->device,
3191	"PCI Pass-through VSP failed to request version: %d",
3192	ret);
3193	goto exit;
3194	}
3195
3196	if (comp_pkt.completion_status >= 0) {
3197	hbus->protocol_version = version[i];
3198	dev_info(&hdev->device,
3199	"PCI VMBus probing: Using version %#x\n",
3200	hbus->protocol_version);
3201	goto exit;
3202	}
3203
3204	if (comp_pkt.completion_status != STATUS_REVISION_MISMATCH) {
3205	dev_err(&hdev->device,
3206	"PCI Pass-through VSP failed version request: %#x",
3207	comp_pkt.completion_status);
3208	ret = -EPROTO;
3209	goto exit;
3210	}
3211
3212	reinit_completion(x: &comp_pkt.host_event);
3213	}
3214
3215	dev_err(&hdev->device,
3216	"PCI pass-through VSP failed to find supported version");
3217	ret = -EPROTO;
3218
3219	exit:
3220	kfree(objp: pkt);
3221	return ret;
3222	}
3223
3224	/**
3225	* hv_pci_free_bridge_windows() - Release memory regions for the
3226	* bus
3227	* @hbus: Root PCI bus, as understood by this driver
3228	*/
3229	static void hv_pci_free_bridge_windows(struct hv_pcibus_device *hbus)
3230	{
3231	/*
3232	* Set the resources back to the way they looked when they
3233	* were allocated by setting IORESOURCE_BUSY again.
3234	*/
3235
3236	if (hbus->low_mmio_space && hbus->low_mmio_res) {
3237	hbus->low_mmio_res->flags |= IORESOURCE_BUSY;
3238	vmbus_free_mmio(start: hbus->low_mmio_res->start,
3239	size: resource_size(res: hbus->low_mmio_res));
3240	}
3241
3242	if (hbus->high_mmio_space && hbus->high_mmio_res) {
3243	hbus->high_mmio_res->flags |= IORESOURCE_BUSY;
3244	vmbus_free_mmio(start: hbus->high_mmio_res->start,
3245	size: resource_size(res: hbus->high_mmio_res));
3246	}
3247	}
3248
3249	/**
3250	* hv_pci_allocate_bridge_windows() - Allocate memory regions
3251	* for the bus
3252	* @hbus: Root PCI bus, as understood by this driver
3253	*
3254	* This function calls vmbus_allocate_mmio(), which is itself a
3255	* bit of a compromise. Ideally, we might change the pnp layer
3256	* in the kernel such that it comprehends either PCI devices
3257	* which are "grandchildren of ACPI," with some intermediate bus
3258	* node (in this case, VMBus) or change it such that it
3259	* understands VMBus. The pnp layer, however, has been declared
3260	* deprecated, and not subject to change.
3261	*
3262	* The workaround, implemented here, is to ask VMBus to allocate
3263	* MMIO space for this bus. VMBus itself knows which ranges are
3264	* appropriate by looking at its own ACPI objects. Then, after
3265	* these ranges are claimed, they're modified to look like they
3266	* would have looked if the ACPI and pnp code had allocated
3267	* bridge windows. These descriptors have to exist in this form
3268	* in order to satisfy the code which will get invoked when the
3269	* endpoint PCI function driver calls request_mem_region() or
3270	* request_mem_region_exclusive().
3271	*
3272	* Return: 0 on success, -errno on failure
3273	*/
3274	static int hv_pci_allocate_bridge_windows(struct hv_pcibus_device *hbus)
3275	{
3276	resource_size_t align;
3277	int ret;
3278
3279	if (hbus->low_mmio_space) {
3280	align = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
3281	ret = vmbus_allocate_mmio(new: &hbus->low_mmio_res, device_obj: hbus->hdev, min: 0,
3282	max: (u64)(u32)0xffffffff,
3283	size: hbus->low_mmio_space,
3284	align, fb_overlap_ok: false);
3285	if (ret) {
3286	dev_err(&hbus->hdev->device,
3287	"Need %#llx of low MMIO space. Consider reconfiguring the VM.\n",
3288	hbus->low_mmio_space);
3289	return ret;
3290	}
3291
3292	/* Modify this resource to become a bridge window. */
3293	hbus->low_mmio_res->flags |= IORESOURCE_WINDOW;
3294	hbus->low_mmio_res->flags &= ~IORESOURCE_BUSY;
3295	pci_add_resource(resources: &hbus->bridge->windows, res: hbus->low_mmio_res);
3296	}
3297
3298	if (hbus->high_mmio_space) {
3299	align = 1ULL << (63 - __builtin_clzll(hbus->high_mmio_space));
3300	ret = vmbus_allocate_mmio(new: &hbus->high_mmio_res, device_obj: hbus->hdev,
3301	min: 0x100000000, max: -1,
3302	size: hbus->high_mmio_space, align,
3303	fb_overlap_ok: false);
3304	if (ret) {
3305	dev_err(&hbus->hdev->device,
3306	"Need %#llx of high MMIO space. Consider reconfiguring the VM.\n",
3307	hbus->high_mmio_space);
3308	goto release_low_mmio;
3309	}
3310
3311	/* Modify this resource to become a bridge window. */
3312	hbus->high_mmio_res->flags |= IORESOURCE_WINDOW;
3313	hbus->high_mmio_res->flags &= ~IORESOURCE_BUSY;
3314	pci_add_resource(resources: &hbus->bridge->windows, res: hbus->high_mmio_res);
3315	}
3316
3317	return 0;
3318
3319	release_low_mmio:
3320	if (hbus->low_mmio_res) {
3321	vmbus_free_mmio(start: hbus->low_mmio_res->start,
3322	size: resource_size(res: hbus->low_mmio_res));
3323	}
3324
3325	return ret;
3326	}
3327
3328	/**
3329	* hv_allocate_config_window() - Find MMIO space for PCI Config
3330	* @hbus: Root PCI bus, as understood by this driver
3331	*
3332	* This function claims memory-mapped I/O space for accessing
3333	* configuration space for the functions on this bus.
3334	*
3335	* Return: 0 on success, -errno on failure
3336	*/
3337	static int hv_allocate_config_window(struct hv_pcibus_device *hbus)
3338	{
3339	int ret;
3340
3341	/*
3342	* Set up a region of MMIO space to use for accessing configuration
3343	* space.
3344	*/
3345	ret = vmbus_allocate_mmio(new: &hbus->mem_config, device_obj: hbus->hdev, min: 0, max: -1,
3346	PCI_CONFIG_MMIO_LENGTH, align: 0x1000, fb_overlap_ok: false);
3347	if (ret)
3348	return ret;
3349
3350	/*
3351	* vmbus_allocate_mmio() gets used for allocating both device endpoint
3352	* resource claims (those which cannot be overlapped) and the ranges
3353	* which are valid for the children of this bus, which are intended
3354	* to be overlapped by those children. Set the flag on this claim
3355	* meaning that this region can't be overlapped.
3356	*/
3357
3358	hbus->mem_config->flags |= IORESOURCE_BUSY;
3359
3360	return 0;
3361	}
3362
3363	static void hv_free_config_window(struct hv_pcibus_device *hbus)
3364	{
3365	vmbus_free_mmio(start: hbus->mem_config->start, PCI_CONFIG_MMIO_LENGTH);
3366	}
3367
3368	static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs);
3369
3370	/**
3371	* hv_pci_enter_d0() - Bring the "bus" into the D0 power state
3372	* @hdev: VMBus's tracking struct for this root PCI bus
3373	*
3374	* Return: 0 on success, -errno on failure
3375	*/
3376	static int hv_pci_enter_d0(struct hv_device *hdev)
3377	{
3378	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3379	struct pci_bus_d0_entry *d0_entry;
3380	struct hv_pci_compl comp_pkt;
3381	struct pci_packet *pkt;
3382	bool retry = true;
3383	int ret;
3384
3385	enter_d0_retry:
3386	/*
3387	* Tell the host that the bus is ready to use, and moved into the
3388	* powered-on state. This includes telling the host which region
3389	* of memory-mapped I/O space has been chosen for configuration space
3390	* access.
3391	*/
3392	pkt = kzalloc(sizeof(*pkt) + sizeof(*d0_entry), GFP_KERNEL);
3393	if (!pkt)
3394	return -ENOMEM;
3395
3396	init_completion(x: &comp_pkt.host_event);
3397	pkt->completion_func = hv_pci_generic_compl;
3398	pkt->compl_ctxt = &comp_pkt;
3399	d0_entry = (struct pci_bus_d0_entry *)(pkt + 1);
3400	d0_entry->message_type.type = PCI_BUS_D0ENTRY;
3401	d0_entry->mmio_base = hbus->mem_config->start;
3402
3403	ret = vmbus_sendpacket(channel: hdev->channel, buffer: d0_entry, bufferLen: sizeof(*d0_entry),
3404	requestid: (unsigned long)pkt, type: VM_PKT_DATA_INBAND,
3405	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3406	if (!ret)
3407	ret = wait_for_response(hdev, comp: &comp_pkt.host_event);
3408
3409	if (ret)
3410	goto exit;
3411
3412	/*
3413	* In certain case (Kdump) the pci device of interest was
3414	* not cleanly shut down and resource is still held on host
3415	* side, the host could return invalid device status.
3416	* We need to explicitly request host to release the resource
3417	* and try to enter D0 again.
3418	*/
3419	if (comp_pkt.completion_status < 0 && retry) {
3420	retry = false;
3421
3422	dev_err(&hdev->device, "Retrying D0 Entry\n");
3423
3424	/*
3425	* Hv_pci_bus_exit() calls hv_send_resource_released()
3426	* to free up resources of its child devices.
3427	* In the kdump kernel we need to set the
3428	* wslot_res_allocated to 255 so it scans all child
3429	* devices to release resources allocated in the
3430	* normal kernel before panic happened.
3431	*/
3432	hbus->wslot_res_allocated = 255;
3433
3434	ret = hv_pci_bus_exit(hdev, keep_devs: true);
3435
3436	if (ret == 0) {
3437	kfree(objp: pkt);
3438	goto enter_d0_retry;
3439	}
3440	dev_err(&hdev->device,
3441	"Retrying D0 failed with ret %d\n", ret);
3442	}
3443
3444	if (comp_pkt.completion_status < 0) {
3445	dev_err(&hdev->device,
3446	"PCI Pass-through VSP failed D0 Entry with status %x\n",
3447	comp_pkt.completion_status);
3448	ret = -EPROTO;
3449	goto exit;
3450	}
3451
3452	ret = 0;
3453
3454	exit:
3455	kfree(objp: pkt);
3456	return ret;
3457	}
3458
3459	/**
3460	* hv_pci_query_relations() - Ask host to send list of child
3461	* devices
3462	* @hdev: VMBus's tracking struct for this root PCI bus
3463	*
3464	* Return: 0 on success, -errno on failure
3465	*/
3466	static int hv_pci_query_relations(struct hv_device *hdev)
3467	{
3468	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3469	struct pci_message message;
3470	struct completion comp;
3471	int ret;
3472
3473	/* Ask the host to send along the list of child devices */
3474	init_completion(x: &comp);
3475	if (cmpxchg(&hbus->survey_event, NULL, &comp))
3476	return -ENOTEMPTY;
3477
3478	memset(&message, 0, sizeof(message));
3479	message.type = PCI_QUERY_BUS_RELATIONS;
3480
3481	ret = vmbus_sendpacket(channel: hdev->channel, buffer: &message, bufferLen: sizeof(message),
3482	requestid: 0, type: VM_PKT_DATA_INBAND, flags: 0);
3483	if (!ret)
3484	ret = wait_for_response(hdev, comp: &comp);
3485
3486	/*
3487	* In the case of fast device addition/removal, it's possible that
3488	* vmbus_sendpacket() or wait_for_response() returns -ENODEV but we
3489	* already got a PCI_BUS_RELATIONS* message from the host and the
3490	* channel callback already scheduled a work to hbus->wq, which can be
3491	* running pci_devices_present_work() -> survey_child_resources() ->
3492	* complete(&hbus->survey_event), even after hv_pci_query_relations()
3493	* exits and the stack variable 'comp' is no longer valid; as a result,
3494	* a hang or a page fault may happen when the complete() calls
3495	* raw_spin_lock_irqsave(). Flush hbus->wq before we exit from
3496	* hv_pci_query_relations() to avoid the issues. Note: if 'ret' is
3497	* -ENODEV, there can't be any more work item scheduled to hbus->wq
3498	* after the flush_workqueue(): see vmbus_onoffer_rescind() ->
3499	* vmbus_reset_channel_cb(), vmbus_rescind_cleanup() ->
3500	* channel->rescind = true.
3501	*/
3502	flush_workqueue(hbus->wq);
3503
3504	return ret;
3505	}
3506
3507	/**
3508	* hv_send_resources_allocated() - Report local resource choices
3509	* @hdev: VMBus's tracking struct for this root PCI bus
3510	*
3511	* The host OS is expecting to be sent a request as a message
3512	* which contains all the resources that the device will use.
3513	* The response contains those same resources, "translated"
3514	* which is to say, the values which should be used by the
3515	* hardware, when it delivers an interrupt. (MMIO resources are
3516	* used in local terms.) This is nice for Windows, and lines up
3517	* with the FDO/PDO split, which doesn't exist in Linux. Linux
3518	* is deeply expecting to scan an emulated PCI configuration
3519	* space. So this message is sent here only to drive the state
3520	* machine on the host forward.
3521	*
3522	* Return: 0 on success, -errno on failure
3523	*/
3524	static int hv_send_resources_allocated(struct hv_device *hdev)
3525	{
3526	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3527	struct pci_resources_assigned *res_assigned;
3528	struct pci_resources_assigned2 *res_assigned2;
3529	struct hv_pci_compl comp_pkt;
3530	struct hv_pci_dev *hpdev;
3531	struct pci_packet *pkt;
3532	size_t size_res;
3533	int wslot;
3534	int ret;
3535
3536	size_res = (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2)
3537	? sizeof(*res_assigned) : sizeof(*res_assigned2);
3538
3539	pkt = kmalloc(sizeof(*pkt) + size_res, GFP_KERNEL);
3540	if (!pkt)
3541	return -ENOMEM;
3542
3543	ret = 0;
3544
3545	for (wslot = 0; wslot < 256; wslot++) {
3546	hpdev = get_pcichild_wslot(hbus, wslot);
3547	if (!hpdev)
3548	continue;
3549
3550	memset(pkt, 0, sizeof(*pkt) + size_res);
3551	init_completion(x: &comp_pkt.host_event);
3552	pkt->completion_func = hv_pci_generic_compl;
3553	pkt->compl_ctxt = &comp_pkt;
3554
3555	if (hbus->protocol_version < PCI_PROTOCOL_VERSION_1_2) {
3556	res_assigned =
3557	(struct pci_resources_assigned *)(pkt + 1);
3558	res_assigned->message_type.type =
3559	PCI_RESOURCES_ASSIGNED;
3560	res_assigned->wslot.slot = hpdev->desc.win_slot.slot;
3561	} else {
3562	res_assigned2 =
3563	(struct pci_resources_assigned2 *)(pkt + 1);
3564	res_assigned2->message_type.type =
3565	PCI_RESOURCES_ASSIGNED2;
3566	res_assigned2->wslot.slot = hpdev->desc.win_slot.slot;
3567	}
3568	put_pcichild(hpdev);
3569
3570	ret = vmbus_sendpacket(channel: hdev->channel, buffer: pkt + 1,
3571	bufferLen: size_res, requestid: (unsigned long)pkt,
3572	type: VM_PKT_DATA_INBAND,
3573	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3574	if (!ret)
3575	ret = wait_for_response(hdev, comp: &comp_pkt.host_event);
3576	if (ret)
3577	break;
3578
3579	if (comp_pkt.completion_status < 0) {
3580	ret = -EPROTO;
3581	dev_err(&hdev->device,
3582	"resource allocated returned 0x%x",
3583	comp_pkt.completion_status);
3584	break;
3585	}
3586
3587	hbus->wslot_res_allocated = wslot;
3588	}
3589
3590	kfree(objp: pkt);
3591	return ret;
3592	}
3593
3594	/**
3595	* hv_send_resources_released() - Report local resources
3596	* released
3597	* @hdev: VMBus's tracking struct for this root PCI bus
3598	*
3599	* Return: 0 on success, -errno on failure
3600	*/
3601	static int hv_send_resources_released(struct hv_device *hdev)
3602	{
3603	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3604	struct pci_child_message pkt;
3605	struct hv_pci_dev *hpdev;
3606	int wslot;
3607	int ret;
3608
3609	for (wslot = hbus->wslot_res_allocated; wslot >= 0; wslot--) {
3610	hpdev = get_pcichild_wslot(hbus, wslot);
3611	if (!hpdev)
3612	continue;
3613
3614	memset(&pkt, 0, sizeof(pkt));
3615	pkt.message_type.type = PCI_RESOURCES_RELEASED;
3616	pkt.wslot.slot = hpdev->desc.win_slot.slot;
3617
3618	put_pcichild(hpdev);
3619
3620	ret = vmbus_sendpacket(channel: hdev->channel, buffer: &pkt, bufferLen: sizeof(pkt), requestid: 0,
3621	type: VM_PKT_DATA_INBAND, flags: 0);
3622	if (ret)
3623	return ret;
3624
3625	hbus->wslot_res_allocated = wslot - 1;
3626	}
3627
3628	hbus->wslot_res_allocated = -1;
3629
3630	return 0;
3631	}
3632
3633	#define HVPCI_DOM_MAP_SIZE (64 * 1024)
3634	static DECLARE_BITMAP(hvpci_dom_map, HVPCI_DOM_MAP_SIZE);
3635
3636	/*
3637	* PCI domain number 0 is used by emulated devices on Gen1 VMs, so define 0
3638	* as invalid for passthrough PCI devices of this driver.
3639	*/
3640	#define HVPCI_DOM_INVALID 0
3641
3642	/**
3643	* hv_get_dom_num() - Get a valid PCI domain number
3644	* Check if the PCI domain number is in use, and return another number if
3645	* it is in use.
3646	*
3647	* @dom: Requested domain number
3648	*
3649	* return: domain number on success, HVPCI_DOM_INVALID on failure
3650	*/
3651	static u16 hv_get_dom_num(u16 dom)
3652	{
3653	unsigned int i;
3654
3655	if (test_and_set_bit(nr: dom, addr: hvpci_dom_map) == 0)
3656	return dom;
3657
3658	for_each_clear_bit(i, hvpci_dom_map, HVPCI_DOM_MAP_SIZE) {
3659	if (test_and_set_bit(nr: i, addr: hvpci_dom_map) == 0)
3660	return i;
3661	}
3662
3663	return HVPCI_DOM_INVALID;
3664	}
3665
3666	/**
3667	* hv_put_dom_num() - Mark the PCI domain number as free
3668	* @dom: Domain number to be freed
3669	*/
3670	static void hv_put_dom_num(u16 dom)
3671	{
3672	clear_bit(nr: dom, addr: hvpci_dom_map);
3673	}
3674
3675	/**
3676	* hv_pci_probe() - New VMBus channel probe, for a root PCI bus
3677	* @hdev: VMBus's tracking struct for this root PCI bus
3678	* @dev_id: Identifies the device itself
3679	*
3680	* Return: 0 on success, -errno on failure
3681	*/
3682	static int hv_pci_probe(struct hv_device *hdev,
3683	const struct hv_vmbus_device_id *dev_id)
3684	{
3685	struct pci_host_bridge *bridge;
3686	struct hv_pcibus_device *hbus;
3687	u16 dom_req, dom;
3688	char *name;
3689	int ret;
3690
3691	bridge = devm_pci_alloc_host_bridge(dev: &hdev->device, priv: 0);
3692	if (!bridge)
3693	return -ENOMEM;
3694
3695	hbus = kzalloc(sizeof(*hbus), GFP_KERNEL);
3696	if (!hbus)
3697	return -ENOMEM;
3698
3699	hbus->bridge = bridge;
3700	mutex_init(&hbus->state_lock);
3701	hbus->state = hv_pcibus_init;
3702	hbus->wslot_res_allocated = -1;
3703
3704	/*
3705	* The PCI bus "domain" is what is called "segment" in ACPI and other
3706	* specs. Pull it from the instance ID, to get something usually
3707	* unique. In rare cases of collision, we will find out another number
3708	* not in use.
3709	*
3710	* Note that, since this code only runs in a Hyper-V VM, Hyper-V
3711	* together with this guest driver can guarantee that (1) The only
3712	* domain used by Gen1 VMs for something that looks like a physical
3713	* PCI bus (which is actually emulated by the hypervisor) is domain 0.
3714	* (2) There will be no overlap between domains (after fixing possible
3715	* collisions) in the same VM.
3716	*/
3717	dom_req = hdev->dev_instance.b[5] << 8 | hdev->dev_instance.b[4];
3718	dom = hv_get_dom_num(dom: dom_req);
3719
3720	if (dom == HVPCI_DOM_INVALID) {
3721	dev_err(&hdev->device,
3722	"Unable to use dom# 0x%x or other numbers", dom_req);
3723	ret = -EINVAL;
3724	goto free_bus;
3725	}
3726
3727	if (dom != dom_req)
3728	dev_info(&hdev->device,
3729	"PCI dom# 0x%x has collision, using 0x%x",
3730	dom_req, dom);
3731
3732	hbus->bridge->domain_nr = dom;
3733	#ifdef CONFIG_X86
3734	hbus->sysdata.domain = dom;
3735	hbus->use_calls = !!(ms_hyperv.hints & HV_X64_USE_MMIO_HYPERCALLS);
3736	#elif defined(CONFIG_ARM64)
3737	/*
3738	* Set the PCI bus parent to be the corresponding VMbus
3739	* device. Then the VMbus device will be assigned as the
3740	* ACPI companion in pcibios_root_bridge_prepare() and
3741	* pci_dma_configure() will propagate device coherence
3742	* information to devices created on the bus.
3743	*/
3744	hbus->sysdata.parent = hdev->device.parent;
3745	hbus->use_calls = false;
3746	#endif
3747
3748	hbus->hdev = hdev;
3749	INIT_LIST_HEAD(list: &hbus->children);
3750	INIT_LIST_HEAD(list: &hbus->dr_list);
3751	spin_lock_init(&hbus->config_lock);
3752	spin_lock_init(&hbus->device_list_lock);
3753	hbus->wq = alloc_ordered_workqueue("hv_pci_%x", 0,
3754	hbus->bridge->domain_nr);
3755	if (!hbus->wq) {
3756	ret = -ENOMEM;
3757	goto free_dom;
3758	}
3759
3760	hdev->channel->next_request_id_callback = vmbus_next_request_id;
3761	hdev->channel->request_addr_callback = vmbus_request_addr;
3762	hdev->channel->rqstor_size = HV_PCI_RQSTOR_SIZE;
3763
3764	ret = vmbus_open(channel: hdev->channel, send_ringbuffersize: pci_ring_size, recv_ringbuffersize: pci_ring_size, NULL, userdatalen: 0,
3765	onchannel_callback: hv_pci_onchannelcallback, context: hbus);
3766	if (ret)
3767	goto destroy_wq;
3768
3769	hv_set_drvdata(dev: hdev, data: hbus);
3770
3771	ret = hv_pci_protocol_negotiation(hdev, version: pci_protocol_versions,
3772	ARRAY_SIZE(pci_protocol_versions));
3773	if (ret)
3774	goto close;
3775
3776	ret = hv_allocate_config_window(hbus);
3777	if (ret)
3778	goto close;
3779
3780	hbus->cfg_addr = ioremap(offset: hbus->mem_config->start,
3781	PCI_CONFIG_MMIO_LENGTH);
3782	if (!hbus->cfg_addr) {
3783	dev_err(&hdev->device,
3784	"Unable to map a virtual address for config space\n");
3785	ret = -ENOMEM;
3786	goto free_config;
3787	}
3788
3789	name = kasprintf(GFP_KERNEL, fmt: "%pUL", &hdev->dev_instance);
3790	if (!name) {
3791	ret = -ENOMEM;
3792	goto unmap;
3793	}
3794
3795	hbus->fwnode = irq_domain_alloc_named_fwnode(name);
3796	kfree(objp: name);
3797	if (!hbus->fwnode) {
3798	ret = -ENOMEM;
3799	goto unmap;
3800	}
3801
3802	ret = hv_pcie_init_irq_domain(hbus);
3803	if (ret)
3804	goto free_fwnode;
3805
3806	ret = hv_pci_query_relations(hdev);
3807	if (ret)
3808	goto free_irq_domain;
3809
3810	mutex_lock(&hbus->state_lock);
3811
3812	ret = hv_pci_enter_d0(hdev);
3813	if (ret)
3814	goto release_state_lock;
3815
3816	ret = hv_pci_allocate_bridge_windows(hbus);
3817	if (ret)
3818	goto exit_d0;
3819
3820	ret = hv_send_resources_allocated(hdev);
3821	if (ret)
3822	goto free_windows;
3823
3824	prepopulate_bars(hbus);
3825
3826	hbus->state = hv_pcibus_probed;
3827
3828	ret = create_root_hv_pci_bus(hbus);
3829	if (ret)
3830	goto free_windows;
3831
3832	mutex_unlock(lock: &hbus->state_lock);
3833	return 0;
3834
3835	free_windows:
3836	hv_pci_free_bridge_windows(hbus);
3837	exit_d0:
3838	(void) hv_pci_bus_exit(hdev, keep_devs: true);
3839	release_state_lock:
3840	mutex_unlock(lock: &hbus->state_lock);
3841	free_irq_domain:
3842	irq_domain_remove(domain: hbus->irq_domain);
3843	free_fwnode:
3844	irq_domain_free_fwnode(fwnode: hbus->fwnode);
3845	unmap:
3846	iounmap(addr: hbus->cfg_addr);
3847	free_config:
3848	hv_free_config_window(hbus);
3849	close:
3850	vmbus_close(channel: hdev->channel);
3851	destroy_wq:
3852	destroy_workqueue(wq: hbus->wq);
3853	free_dom:
3854	hv_put_dom_num(dom: hbus->bridge->domain_nr);
3855	free_bus:
3856	kfree(objp: hbus);
3857	return ret;
3858	}
3859
3860	static int hv_pci_bus_exit(struct hv_device *hdev, bool keep_devs)
3861	{
3862	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3863	struct vmbus_channel *chan = hdev->channel;
3864	struct {
3865	struct pci_packet teardown_packet;
3866	u8 buffer[sizeof(struct pci_message)];
3867	} pkt;
3868	struct pci_message *msg;
3869	struct hv_pci_compl comp_pkt;
3870	struct hv_pci_dev *hpdev, *tmp;
3871	unsigned long flags;
3872	u64 trans_id;
3873	int ret;
3874
3875	/*
3876	* After the host sends the RESCIND_CHANNEL message, it doesn't
3877	* access the per-channel ringbuffer any longer.
3878	*/
3879	if (chan->rescind)
3880	return 0;
3881
3882	if (!keep_devs) {
3883	struct list_head removed;
3884
3885	/* Move all present children to the list on stack */
3886	INIT_LIST_HEAD(list: &removed);
3887	spin_lock_irqsave(&hbus->device_list_lock, flags);
3888	list_for_each_entry_safe(hpdev, tmp, &hbus->children, list_entry)
3889	list_move_tail(list: &hpdev->list_entry, head: &removed);
3890	spin_unlock_irqrestore(lock: &hbus->device_list_lock, flags);
3891
3892	/* Remove all children in the list */
3893	list_for_each_entry_safe(hpdev, tmp, &removed, list_entry) {
3894	list_del(entry: &hpdev->list_entry);
3895	if (hpdev->pci_slot)
3896	pci_destroy_slot(slot: hpdev->pci_slot);
3897	/* For the two refs got in new_pcichild_device() */
3898	put_pcichild(hpdev);
3899	put_pcichild(hpdev);
3900	}
3901	}
3902
3903	ret = hv_send_resources_released(hdev);
3904	if (ret) {
3905	dev_err(&hdev->device,
3906	"Couldn't send resources released packet(s)\n");
3907	return ret;
3908	}
3909
3910	memset(&pkt.teardown_packet, 0, sizeof(pkt.teardown_packet));
3911	init_completion(x: &comp_pkt.host_event);
3912	pkt.teardown_packet.completion_func = hv_pci_generic_compl;
3913	pkt.teardown_packet.compl_ctxt = &comp_pkt;
3914	msg = (struct pci_message *)pkt.buffer;
3915	msg->type = PCI_BUS_D0EXIT;
3916
3917	ret = vmbus_sendpacket_getid(channel: chan, buffer: msg, bufferLen: sizeof(*msg),
3918	requestid: (unsigned long)&pkt.teardown_packet,
3919	trans_id: &trans_id, type: VM_PKT_DATA_INBAND,
3920	VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
3921	if (ret)
3922	return ret;
3923
3924	if (wait_for_completion_timeout(x: &comp_pkt.host_event, timeout: 10 * HZ) == 0) {
3925	/*
3926	* The completion packet on the stack becomes invalid after
3927	* 'return'; remove the ID from the VMbus requestor if the
3928	* identifier is still mapped to/associated with the packet.
3929	*
3930	* Cf. hv_pci_onchannelcallback().
3931	*/
3932	vmbus_request_addr_match(channel: chan, trans_id,
3933	rqst_addr: (unsigned long)&pkt.teardown_packet);
3934	return -ETIMEDOUT;
3935	}
3936
3937	return 0;
3938	}
3939
3940	/**
3941	* hv_pci_remove() - Remove routine for this VMBus channel
3942	* @hdev: VMBus's tracking struct for this root PCI bus
3943	*/
3944	static void hv_pci_remove(struct hv_device *hdev)
3945	{
3946	struct hv_pcibus_device *hbus;
3947
3948	hbus = hv_get_drvdata(dev: hdev);
3949	if (hbus->state == hv_pcibus_installed) {
3950	tasklet_disable(t: &hdev->channel->callback_event);
3951	hbus->state = hv_pcibus_removing;
3952	tasklet_enable(t: &hdev->channel->callback_event);
3953	destroy_workqueue(wq: hbus->wq);
3954	hbus->wq = NULL;
3955	/*
3956	* At this point, no work is running or can be scheduled
3957	* on hbus-wq. We can't race with hv_pci_devices_present()
3958	* or hv_pci_eject_device(), it's safe to proceed.
3959	*/
3960
3961	/* Remove the bus from PCI's point of view. */
3962	pci_lock_rescan_remove();
3963	pci_stop_root_bus(bus: hbus->bridge->bus);
3964	hv_pci_remove_slots(hbus);
3965	pci_remove_root_bus(bus: hbus->bridge->bus);
3966	pci_unlock_rescan_remove();
3967	}
3968
3969	hv_pci_bus_exit(hdev, keep_devs: false);
3970
3971	vmbus_close(channel: hdev->channel);
3972
3973	iounmap(addr: hbus->cfg_addr);
3974	hv_free_config_window(hbus);
3975	hv_pci_free_bridge_windows(hbus);
3976	irq_domain_remove(domain: hbus->irq_domain);
3977	irq_domain_free_fwnode(fwnode: hbus->fwnode);
3978
3979	hv_put_dom_num(dom: hbus->bridge->domain_nr);
3980
3981	kfree(objp: hbus);
3982	}
3983
3984	static int hv_pci_suspend(struct hv_device *hdev)
3985	{
3986	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
3987	enum hv_pcibus_state old_state;
3988	int ret;
3989
3990	/*
3991	* hv_pci_suspend() must make sure there are no pending work items
3992	* before calling vmbus_close(), since it runs in a process context
3993	* as a callback in dpm_suspend(). When it starts to run, the channel
3994	* callback hv_pci_onchannelcallback(), which runs in a tasklet
3995	* context, can be still running concurrently and scheduling new work
3996	* items onto hbus->wq in hv_pci_devices_present() and
3997	* hv_pci_eject_device(), and the work item handlers can access the
3998	* vmbus channel, which can be being closed by hv_pci_suspend(), e.g.
3999	* the work item handler pci_devices_present_work() ->
4000	* new_pcichild_device() writes to the vmbus channel.
4001	*
4002	* To eliminate the race, hv_pci_suspend() disables the channel
4003	* callback tasklet, sets hbus->state to hv_pcibus_removing, and
4004	* re-enables the tasklet. This way, when hv_pci_suspend() proceeds,
4005	* it knows that no new work item can be scheduled, and then it flushes
4006	* hbus->wq and safely closes the vmbus channel.
4007	*/
4008	tasklet_disable(t: &hdev->channel->callback_event);
4009
4010	/* Change the hbus state to prevent new work items. */
4011	old_state = hbus->state;
4012	if (hbus->state == hv_pcibus_installed)
4013	hbus->state = hv_pcibus_removing;
4014
4015	tasklet_enable(t: &hdev->channel->callback_event);
4016
4017	if (old_state != hv_pcibus_installed)
4018	return -EINVAL;
4019
4020	flush_workqueue(hbus->wq);
4021
4022	ret = hv_pci_bus_exit(hdev, keep_devs: true);
4023	if (ret)
4024	return ret;
4025
4026	vmbus_close(channel: hdev->channel);
4027
4028	return 0;
4029	}
4030
4031	static int hv_pci_restore_msi_msg(struct pci_dev *pdev, void *arg)
4032	{
4033	struct irq_data *irq_data;
4034	struct msi_desc *entry;
4035
4036	if (!pdev->msi_enabled && !pdev->msix_enabled)
4037	return 0;
4038
4039	guard(msi_descs_lock)(l: &pdev->dev);
4040	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) {
4041	irq_data = irq_get_irq_data(irq: entry->irq);
4042	if (WARN_ON_ONCE(!irq_data))
4043	return -EINVAL;
4044	hv_compose_msi_msg(data: irq_data, msg: &entry->msg);
4045	}
4046	return 0;
4047	}
4048
4049	/*
4050	* Upon resume, pci_restore_msi_state() -> ... -> __pci_write_msi_msg()
4051	* directly writes the MSI/MSI-X registers via MMIO, but since Hyper-V
4052	* doesn't trap and emulate the MMIO accesses, here hv_compose_msi_msg()
4053	* must be used to ask Hyper-V to re-create the IOMMU Interrupt Remapping
4054	* Table entries.
4055	*/
4056	static void hv_pci_restore_msi_state(struct hv_pcibus_device *hbus)
4057	{
4058	pci_walk_bus(top: hbus->bridge->bus, cb: hv_pci_restore_msi_msg, NULL);
4059	}
4060
4061	static int hv_pci_resume(struct hv_device *hdev)
4062	{
4063	struct hv_pcibus_device *hbus = hv_get_drvdata(dev: hdev);
4064	enum pci_protocol_version_t version[1];
4065	int ret;
4066
4067	hbus->state = hv_pcibus_init;
4068
4069	hdev->channel->next_request_id_callback = vmbus_next_request_id;
4070	hdev->channel->request_addr_callback = vmbus_request_addr;
4071	hdev->channel->rqstor_size = HV_PCI_RQSTOR_SIZE;
4072
4073	ret = vmbus_open(channel: hdev->channel, send_ringbuffersize: pci_ring_size, recv_ringbuffersize: pci_ring_size, NULL, userdatalen: 0,
4074	onchannel_callback: hv_pci_onchannelcallback, context: hbus);
4075	if (ret)
4076	return ret;
4077
4078	/* Only use the version that was in use before hibernation. */
4079	version[0] = hbus->protocol_version;
4080	ret = hv_pci_protocol_negotiation(hdev, version, num_version: 1);
4081	if (ret)
4082	goto out;
4083
4084	ret = hv_pci_query_relations(hdev);
4085	if (ret)
4086	goto out;
4087
4088	mutex_lock(&hbus->state_lock);
4089
4090	ret = hv_pci_enter_d0(hdev);
4091	if (ret)
4092	goto release_state_lock;
4093
4094	ret = hv_send_resources_allocated(hdev);
4095	if (ret)
4096	goto release_state_lock;
4097
4098	prepopulate_bars(hbus);
4099
4100	hv_pci_restore_msi_state(hbus);
4101
4102	hbus->state = hv_pcibus_installed;
4103	mutex_unlock(lock: &hbus->state_lock);
4104	return 0;
4105
4106	release_state_lock:
4107	mutex_unlock(lock: &hbus->state_lock);
4108	out:
4109	vmbus_close(channel: hdev->channel);
4110	return ret;
4111	}
4112
4113	static const struct hv_vmbus_device_id hv_pci_id_table[] = {
4114	/* PCI Pass-through Class ID */
4115	/* 44C4F61D-4444-4400-9D52-802E27EDE19F */
4116	{ HV_PCIE_GUID, },
4117	{ },
4118	};
4119
4120	MODULE_DEVICE_TABLE(vmbus, hv_pci_id_table);
4121
4122	static struct hv_driver hv_pci_drv = {
4123	.name = "hv_pci",
4124	.id_table = hv_pci_id_table,
4125	.probe = hv_pci_probe,
4126	.remove = hv_pci_remove,
4127	.suspend = hv_pci_suspend,
4128	.resume = hv_pci_resume,
4129	};
4130
4131	static void __exit exit_hv_pci_drv(void)
4132	{
4133	vmbus_driver_unregister(hv_driver: &hv_pci_drv);
4134
4135	hvpci_block_ops.read_block = NULL;
4136	hvpci_block_ops.write_block = NULL;
4137	hvpci_block_ops.reg_blk_invalidate = NULL;
4138	}
4139
4140	static int __init init_hv_pci_drv(void)
4141	{
4142	int ret;
4143
4144	if (!hv_is_hyperv_initialized())
4145	return -ENODEV;
4146
4147	ret = hv_pci_irqchip_init();
4148	if (ret)
4149	return ret;
4150
4151	/* Set the invalid domain number's bit, so it will not be used */
4152	set_bit(HVPCI_DOM_INVALID, addr: hvpci_dom_map);
4153
4154	/* Initialize PCI block r/w interface */
4155	hvpci_block_ops.read_block = hv_read_config_block;
4156	hvpci_block_ops.write_block = hv_write_config_block;
4157	hvpci_block_ops.reg_blk_invalidate = hv_register_block_invalidate;
4158
4159	return vmbus_driver_register(&hv_pci_drv);
4160	}
4161
4162	module_init(init_hv_pci_drv);
4163	module_exit(exit_hv_pci_drv);
4164
4165	MODULE_DESCRIPTION("Hyper-V PCI");
4166	MODULE_LICENSE("GPL v2");
4167