1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Allwinner sun4i USB phy driver
4 *
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
6 *
7 * Based on code from
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 *
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
11 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
12 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/extcon-provider.h>
19#include <linux/gpio/consumer.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/mutex.h>
25#include <linux/of.h>
26#include <linux/phy/phy.h>
27#include <linux/phy/phy-sun4i-usb.h>
28#include <linux/platform_device.h>
29#include <linux/power_supply.h>
30#include <linux/regulator/consumer.h>
31#include <linux/reset.h>
32#include <linux/spinlock.h>
33#include <linux/usb/of.h>
34#include <linux/workqueue.h>
35
36#define REG_ISCR 0x00
37#define REG_PHYCTL_A10 0x04
38#define REG_PHYBIST 0x08
39#define REG_PHYTUNE 0x0c
40#define REG_PHYCTL_A33 0x10
41#define REG_PHY_OTGCTL 0x20
42
43#define REG_HCI_PHY_CTL 0x10
44
45#define PHYCTL_DATA BIT(7)
46
47#define OTGCTL_ROUTE_MUSB BIT(0)
48
49#define SUNXI_AHB_ICHR8_EN BIT(10)
50#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
51#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
52#define SUNXI_ULPI_BYPASS_EN BIT(0)
53
54/* ISCR, Interface Status and Control bits */
55#define ISCR_ID_PULLUP_EN (1 << 17)
56#define ISCR_DPDM_PULLUP_EN (1 << 16)
57/* sunxi has the phy id/vbus pins not connected, so we use the force bits */
58#define ISCR_FORCE_ID_MASK (3 << 14)
59#define ISCR_FORCE_ID_LOW (2 << 14)
60#define ISCR_FORCE_ID_HIGH (3 << 14)
61#define ISCR_FORCE_VBUS_MASK (3 << 12)
62#define ISCR_FORCE_VBUS_LOW (2 << 12)
63#define ISCR_FORCE_VBUS_HIGH (3 << 12)
64
65/* Common Control Bits for Both PHYs */
66#define PHY_PLL_BW 0x03
67#define PHY_RES45_CAL_EN 0x0c
68
69/* Private Control Bits for Each PHY */
70#define PHY_TX_AMPLITUDE_TUNE 0x20
71#define PHY_TX_SLEWRATE_TUNE 0x22
72#define PHY_VBUSVALID_TH_SEL 0x25
73#define PHY_PULLUP_RES_SEL 0x27
74#define PHY_OTG_FUNC_EN 0x28
75#define PHY_VBUS_DET_EN 0x29
76#define PHY_DISCON_TH_SEL 0x2a
77#define PHY_SQUELCH_DETECT 0x3c
78
79/* A83T specific control bits for PHY0 */
80#define PHY_CTL_VBUSVLDEXT BIT(5)
81#define PHY_CTL_SIDDQ BIT(3)
82#define PHY_CTL_H3_SIDDQ BIT(1)
83
84/* A83T specific control bits for PHY2 HSIC */
85#define SUNXI_EHCI_HS_FORCE BIT(20)
86#define SUNXI_HSIC_CONNECT_DET BIT(17)
87#define SUNXI_HSIC_CONNECT_INT BIT(16)
88#define SUNXI_HSIC BIT(1)
89
90#define MAX_PHYS 4
91
92/*
93 * Note do not raise the debounce time, we must report Vusb high within 100ms
94 * otherwise we get Vbus errors
95 */
96#define DEBOUNCE_TIME msecs_to_jiffies(50)
97#define POLL_TIME msecs_to_jiffies(250)
98
99struct sun4i_usb_phy_cfg {
100 int num_phys;
101 int hsic_index;
102 u32 disc_thresh;
103 u32 hci_phy_ctl_clear;
104 u8 phyctl_offset;
105 bool dedicated_clocks;
106 bool phy0_dual_route;
107 bool needs_phy2_siddq;
108 bool siddq_in_base;
109 bool poll_vbusen;
110 int missing_phys;
111};
112
113struct sun4i_usb_phy_data {
114 void __iomem *base;
115 const struct sun4i_usb_phy_cfg *cfg;
116 enum usb_dr_mode dr_mode;
117 spinlock_t reg_lock; /* guard access to phyctl reg */
118 struct sun4i_usb_phy {
119 struct phy *phy;
120 void __iomem *pmu;
121 struct regulator *vbus;
122 struct reset_control *reset;
123 struct clk *clk;
124 struct clk *clk2;
125 bool regulator_on;
126 int index;
127 } phys[MAX_PHYS];
128 /* phy0 / otg related variables */
129 struct extcon_dev *extcon;
130 bool phy0_init;
131 struct gpio_desc *id_det_gpio;
132 struct gpio_desc *vbus_det_gpio;
133 struct power_supply *vbus_power_supply;
134 struct notifier_block vbus_power_nb;
135 bool vbus_power_nb_registered;
136 bool force_session_end;
137 int id_det_irq;
138 int vbus_det_irq;
139 int id_det;
140 int vbus_det;
141 struct delayed_work detect;
142};
143
144#define to_sun4i_usb_phy_data(phy) \
145 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
146
147static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
148{
149 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
150 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
151 u32 iscr;
152
153 iscr = readl(addr: data->base + REG_ISCR);
154 iscr &= ~clr;
155 iscr |= set;
156 writel(val: iscr, addr: data->base + REG_ISCR);
157}
158
159static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
160{
161 if (val)
162 val = ISCR_FORCE_ID_HIGH;
163 else
164 val = ISCR_FORCE_ID_LOW;
165
166 sun4i_usb_phy0_update_iscr(phy: phy, ISCR_FORCE_ID_MASK, set: val);
167}
168
169static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
170{
171 if (val)
172 val = ISCR_FORCE_VBUS_HIGH;
173 else
174 val = ISCR_FORCE_VBUS_LOW;
175
176 sun4i_usb_phy0_update_iscr(phy: phy, ISCR_FORCE_VBUS_MASK, set: val);
177}
178
179static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
180 int len)
181{
182 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
183 u32 temp, usbc_bit = BIT(phy->index * 2);
184 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
185 unsigned long flags;
186 int i;
187
188 spin_lock_irqsave(&phy_data->reg_lock, flags);
189
190 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
191 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
192 writel(val: 0, addr: phyctl);
193 }
194
195 for (i = 0; i < len; i++) {
196 temp = readl(addr: phyctl);
197
198 /* clear the address portion */
199 temp &= ~(0xff << 8);
200
201 /* set the address */
202 temp |= ((addr + i) << 8);
203 writel(val: temp, addr: phyctl);
204
205 /* set the data bit and clear usbc bit*/
206 temp = readb(addr: phyctl);
207 if (data & 0x1)
208 temp |= PHYCTL_DATA;
209 else
210 temp &= ~PHYCTL_DATA;
211 temp &= ~usbc_bit;
212 writeb(val: temp, addr: phyctl);
213
214 /* pulse usbc_bit */
215 temp = readb(addr: phyctl);
216 temp |= usbc_bit;
217 writeb(val: temp, addr: phyctl);
218
219 temp = readb(addr: phyctl);
220 temp &= ~usbc_bit;
221 writeb(val: temp, addr: phyctl);
222
223 data >>= 1;
224 }
225
226 spin_unlock_irqrestore(lock: &phy_data->reg_lock, flags);
227}
228
229static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
230{
231 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
232 u32 bits, reg_value;
233
234 if (!phy->pmu)
235 return;
236
237 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
238 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
239
240 /* A83T USB2 is HSIC */
241 if (phy_data->cfg->hsic_index &&
242 phy->index == phy_data->cfg->hsic_index)
243 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
244 SUNXI_HSIC;
245
246 reg_value = readl(addr: phy->pmu);
247
248 if (enable)
249 reg_value |= bits;
250 else
251 reg_value &= ~bits;
252
253 writel(val: reg_value, addr: phy->pmu);
254}
255
256static int sun4i_usb_phy_init(struct phy *_phy)
257{
258 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
259 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
260 int ret;
261 u32 val;
262
263 ret = clk_prepare_enable(clk: phy->clk);
264 if (ret)
265 return ret;
266
267 ret = clk_prepare_enable(clk: phy->clk2);
268 if (ret) {
269 clk_disable_unprepare(clk: phy->clk);
270 return ret;
271 }
272
273 ret = reset_control_deassert(rstc: phy->reset);
274 if (ret) {
275 clk_disable_unprepare(clk: phy->clk2);
276 clk_disable_unprepare(clk: phy->clk);
277 return ret;
278 }
279
280 /* Some PHYs on some SoCs need the help of PHY2 to work. */
281 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
282 struct sun4i_usb_phy *phy2 = &data->phys[2];
283
284 ret = clk_prepare_enable(clk: phy2->clk);
285 if (ret) {
286 reset_control_assert(rstc: phy->reset);
287 clk_disable_unprepare(clk: phy->clk2);
288 clk_disable_unprepare(clk: phy->clk);
289 return ret;
290 }
291
292 ret = reset_control_deassert(rstc: phy2->reset);
293 if (ret) {
294 clk_disable_unprepare(clk: phy2->clk);
295 reset_control_assert(rstc: phy->reset);
296 clk_disable_unprepare(clk: phy->clk2);
297 clk_disable_unprepare(clk: phy->clk);
298 return ret;
299 }
300
301 /*
302 * This extra clock is just needed to access the
303 * REG_HCI_PHY_CTL PMU register for PHY2.
304 */
305 ret = clk_prepare_enable(clk: phy2->clk2);
306 if (ret) {
307 reset_control_assert(rstc: phy2->reset);
308 clk_disable_unprepare(clk: phy2->clk);
309 reset_control_assert(rstc: phy->reset);
310 clk_disable_unprepare(clk: phy->clk2);
311 clk_disable_unprepare(clk: phy->clk);
312 return ret;
313 }
314
315 if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
316 val = readl(addr: phy2->pmu + REG_HCI_PHY_CTL);
317 val &= ~data->cfg->hci_phy_ctl_clear;
318 writel(val, addr: phy2->pmu + REG_HCI_PHY_CTL);
319 }
320
321 clk_disable_unprepare(clk: phy->clk2);
322 }
323
324 if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
325 val = readl(addr: phy->pmu + REG_HCI_PHY_CTL);
326 val &= ~data->cfg->hci_phy_ctl_clear;
327 writel(val, addr: phy->pmu + REG_HCI_PHY_CTL);
328 }
329
330 if (data->cfg->siddq_in_base) {
331 if (phy->index == 0) {
332 val = readl(addr: data->base + data->cfg->phyctl_offset);
333 val |= PHY_CTL_VBUSVLDEXT;
334 val &= ~PHY_CTL_SIDDQ;
335 writel(val, addr: data->base + data->cfg->phyctl_offset);
336 }
337 } else {
338 /* Enable USB 45 Ohm resistor calibration */
339 if (phy->index == 0)
340 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, data: 0x01, len: 1);
341
342 /* Adjust PHY's magnitude and rate */
343 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, data: 0x14, len: 5);
344
345 /* Disconnect threshold adjustment */
346 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
347 data: data->cfg->disc_thresh, len: 2);
348 }
349
350 sun4i_usb_phy_passby(phy, enable: 1);
351
352 if (phy->index == 0) {
353 data->phy0_init = true;
354
355 /* Enable pull-ups */
356 sun4i_usb_phy0_update_iscr(_phy, clr: 0, ISCR_DPDM_PULLUP_EN);
357 sun4i_usb_phy0_update_iscr(_phy, clr: 0, ISCR_ID_PULLUP_EN);
358
359 /* Force ISCR and cable state updates */
360 data->id_det = -1;
361 data->vbus_det = -1;
362 queue_delayed_work(wq: system_wq, dwork: &data->detect, delay: 0);
363 }
364
365 return 0;
366}
367
368static int sun4i_usb_phy_exit(struct phy *_phy)
369{
370 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
371 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
372
373 if (phy->index == 0) {
374 if (data->cfg->siddq_in_base) {
375 void __iomem *phyctl = data->base +
376 data->cfg->phyctl_offset;
377
378 writel(readl(addr: phyctl) | PHY_CTL_SIDDQ, addr: phyctl);
379 }
380
381 /* Disable pull-ups */
382 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, set: 0);
383 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, set: 0);
384 data->phy0_init = false;
385 }
386
387 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
388 struct sun4i_usb_phy *phy2 = &data->phys[2];
389
390 clk_disable_unprepare(clk: phy2->clk);
391 reset_control_assert(rstc: phy2->reset);
392 }
393
394 sun4i_usb_phy_passby(phy, enable: 0);
395 reset_control_assert(rstc: phy->reset);
396 clk_disable_unprepare(clk: phy->clk2);
397 clk_disable_unprepare(clk: phy->clk);
398
399 return 0;
400}
401
402static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
403{
404 switch (data->dr_mode) {
405 case USB_DR_MODE_OTG:
406 if (data->id_det_gpio)
407 return gpiod_get_value_cansleep(desc: data->id_det_gpio);
408 else
409 return 1; /* Fallback to peripheral mode */
410 case USB_DR_MODE_HOST:
411 return 0;
412 case USB_DR_MODE_PERIPHERAL:
413 default:
414 return 1;
415 }
416}
417
418static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
419{
420 if (data->vbus_det_gpio)
421 return gpiod_get_value_cansleep(desc: data->vbus_det_gpio);
422
423 if (data->vbus_power_supply) {
424 union power_supply_propval val;
425 int r;
426
427 r = power_supply_get_property(psy: data->vbus_power_supply,
428 psp: POWER_SUPPLY_PROP_PRESENT, val: &val);
429 if (r == 0)
430 return val.intval;
431 }
432
433 /* Fallback: report vbus as high */
434 return 1;
435}
436
437static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
438{
439 return data->vbus_det_gpio || data->vbus_power_supply;
440}
441
442static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
443{
444 if ((data->id_det_gpio && data->id_det_irq <= 0) ||
445 (data->vbus_det_gpio && data->vbus_det_irq <= 0))
446 return true;
447
448 /*
449 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
450 * generate vbus change interrupts when the board is driving
451 * vbus using the N_VBUSEN pin on the pmic, so we must poll
452 * when using the pmic for vbus-det _and_ we're driving vbus.
453 */
454 if (data->cfg->poll_vbusen && data->vbus_power_supply &&
455 data->phys[0].regulator_on)
456 return true;
457
458 return false;
459}
460
461static int sun4i_usb_phy_power_on(struct phy *_phy)
462{
463 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
464 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
465 int ret;
466
467 if (!phy->vbus || phy->regulator_on)
468 return 0;
469
470 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
471 if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
472 data->vbus_det) {
473 dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
474 return 0;
475 }
476
477 ret = regulator_enable(regulator: phy->vbus);
478 if (ret)
479 return ret;
480
481 phy->regulator_on = true;
482
483 /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
484 if (phy->index == 0 && sun4i_usb_phy0_poll(data))
485 mod_delayed_work(wq: system_wq, dwork: &data->detect, DEBOUNCE_TIME);
486
487 return 0;
488}
489
490static int sun4i_usb_phy_power_off(struct phy *_phy)
491{
492 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
493 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
494
495 if (!phy->vbus || !phy->regulator_on)
496 return 0;
497
498 regulator_disable(regulator: phy->vbus);
499 phy->regulator_on = false;
500
501 /*
502 * phy0 vbus typically slowly discharges, sometimes this causes the
503 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
504 */
505 if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
506 mod_delayed_work(wq: system_wq, dwork: &data->detect, POLL_TIME);
507
508 return 0;
509}
510
511static int sun4i_usb_phy_set_mode(struct phy *_phy,
512 enum phy_mode mode, int submode)
513{
514 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
515 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
516 int new_mode;
517
518 if (phy->index != 0) {
519 if (mode == PHY_MODE_USB_HOST)
520 return 0;
521 return -EINVAL;
522 }
523
524 switch (mode) {
525 case PHY_MODE_USB_HOST:
526 new_mode = USB_DR_MODE_HOST;
527 break;
528 case PHY_MODE_USB_DEVICE:
529 new_mode = USB_DR_MODE_PERIPHERAL;
530 break;
531 case PHY_MODE_USB_OTG:
532 new_mode = USB_DR_MODE_OTG;
533 break;
534 default:
535 return -EINVAL;
536 }
537
538 if (new_mode != data->dr_mode) {
539 dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
540 data->dr_mode = new_mode;
541 }
542
543 data->id_det = -1; /* Force reprocessing of id */
544 data->force_session_end = true;
545 queue_delayed_work(wq: system_wq, dwork: &data->detect, delay: 0);
546
547 return 0;
548}
549
550void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
551{
552 struct sun4i_usb_phy *phy = phy_get_drvdata(phy: _phy);
553
554 sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, data: enabled ? 0 : 2, len: 2);
555}
556EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
557
558static const struct phy_ops sun4i_usb_phy_ops = {
559 .init = sun4i_usb_phy_init,
560 .exit = sun4i_usb_phy_exit,
561 .power_on = sun4i_usb_phy_power_on,
562 .power_off = sun4i_usb_phy_power_off,
563 .set_mode = sun4i_usb_phy_set_mode,
564 .owner = THIS_MODULE,
565};
566
567static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
568{
569 u32 regval;
570
571 regval = readl(addr: data->base + REG_PHY_OTGCTL);
572 if (id_det == 0) {
573 /* Host mode. Route phy0 to EHCI/OHCI */
574 regval &= ~OTGCTL_ROUTE_MUSB;
575 } else {
576 /* Peripheral mode. Route phy0 to MUSB */
577 regval |= OTGCTL_ROUTE_MUSB;
578 }
579 writel(val: regval, addr: data->base + REG_PHY_OTGCTL);
580}
581
582static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
583{
584 struct sun4i_usb_phy_data *data =
585 container_of(work, struct sun4i_usb_phy_data, detect.work);
586 struct phy *phy0 = data->phys[0].phy;
587 struct sun4i_usb_phy *phy;
588 bool force_session_end, id_notify = false, vbus_notify = false;
589 int id_det, vbus_det;
590
591 if (!phy0)
592 return;
593
594 phy = phy_get_drvdata(phy: phy0);
595 id_det = sun4i_usb_phy0_get_id_det(data);
596 vbus_det = sun4i_usb_phy0_get_vbus_det(data);
597
598 mutex_lock(&phy0->mutex);
599
600 if (!data->phy0_init) {
601 mutex_unlock(lock: &phy0->mutex);
602 return;
603 }
604
605 force_session_end = data->force_session_end;
606 data->force_session_end = false;
607
608 if (id_det != data->id_det) {
609 /* id-change, force session end if we've no vbus detection */
610 if (data->dr_mode == USB_DR_MODE_OTG &&
611 !sun4i_usb_phy0_have_vbus_det(data))
612 force_session_end = true;
613
614 /* When entering host mode (id = 0) force end the session now */
615 if (force_session_end && id_det == 0) {
616 sun4i_usb_phy0_set_vbus_detect(phy: phy0, val: 0);
617 msleep(msecs: 200);
618 sun4i_usb_phy0_set_vbus_detect(phy: phy0, val: 1);
619 }
620 sun4i_usb_phy0_set_id_detect(phy: phy0, val: id_det);
621 data->id_det = id_det;
622 id_notify = true;
623 }
624
625 if (vbus_det != data->vbus_det) {
626 sun4i_usb_phy0_set_vbus_detect(phy: phy0, val: vbus_det);
627 data->vbus_det = vbus_det;
628 vbus_notify = true;
629 }
630
631 mutex_unlock(lock: &phy0->mutex);
632
633 if (id_notify) {
634 extcon_set_state_sync(edev: data->extcon, EXTCON_USB_HOST,
635 state: !id_det);
636 /* When leaving host mode force end the session here */
637 if (force_session_end && id_det == 1) {
638 mutex_lock(&phy0->mutex);
639 sun4i_usb_phy0_set_vbus_detect(phy: phy0, val: 0);
640 msleep(msecs: 1000);
641 sun4i_usb_phy0_set_vbus_detect(phy: phy0, val: 1);
642 mutex_unlock(lock: &phy0->mutex);
643 }
644
645 /* Enable PHY0 passby for host mode only. */
646 sun4i_usb_phy_passby(phy, enable: !id_det);
647
648 /* Re-route PHY0 if necessary */
649 if (data->cfg->phy0_dual_route)
650 sun4i_usb_phy0_reroute(data, id_det);
651 }
652
653 if (vbus_notify)
654 extcon_set_state_sync(edev: data->extcon, EXTCON_USB, state: vbus_det);
655
656 if (sun4i_usb_phy0_poll(data))
657 queue_delayed_work(wq: system_wq, dwork: &data->detect, POLL_TIME);
658}
659
660static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
661{
662 struct sun4i_usb_phy_data *data = dev_id;
663
664 /* vbus or id changed, let the pins settle and then scan them */
665 mod_delayed_work(wq: system_wq, dwork: &data->detect, DEBOUNCE_TIME);
666
667 return IRQ_HANDLED;
668}
669
670static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
671 unsigned long val, void *v)
672{
673 struct sun4i_usb_phy_data *data =
674 container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
675 struct power_supply *psy = v;
676
677 /* Properties on the vbus_power_supply changed, scan vbus_det */
678 if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
679 mod_delayed_work(wq: system_wq, dwork: &data->detect, DEBOUNCE_TIME);
680
681 return NOTIFY_OK;
682}
683
684static struct phy *sun4i_usb_phy_xlate(struct device *dev,
685 const struct of_phandle_args *args)
686{
687 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
688
689 if (args->args[0] >= data->cfg->num_phys)
690 return ERR_PTR(error: -ENODEV);
691
692 if (data->cfg->missing_phys & BIT(args->args[0]))
693 return ERR_PTR(error: -ENODEV);
694
695 return data->phys[args->args[0]].phy;
696}
697
698static void sun4i_usb_phy_remove(struct platform_device *pdev)
699{
700 struct device *dev = &pdev->dev;
701 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
702
703 if (data->vbus_power_nb_registered)
704 power_supply_unreg_notifier(nb: &data->vbus_power_nb);
705 if (data->id_det_irq > 0)
706 devm_free_irq(dev, irq: data->id_det_irq, dev_id: data);
707 if (data->vbus_det_irq > 0)
708 devm_free_irq(dev, irq: data->vbus_det_irq, dev_id: data);
709
710 cancel_delayed_work_sync(dwork: &data->detect);
711}
712
713static const unsigned int sun4i_usb_phy0_cable[] = {
714 EXTCON_USB,
715 EXTCON_USB_HOST,
716 EXTCON_NONE,
717};
718
719static int sun4i_usb_phy_probe(struct platform_device *pdev)
720{
721 struct sun4i_usb_phy_data *data;
722 struct device *dev = &pdev->dev;
723 struct device_node *np = dev->of_node;
724 struct phy_provider *phy_provider;
725 int i, ret;
726
727 data = devm_kzalloc(dev, size: sizeof(*data), GFP_KERNEL);
728 if (!data)
729 return -ENOMEM;
730
731 spin_lock_init(&data->reg_lock);
732 INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
733 dev_set_drvdata(dev, data);
734 data->cfg = of_device_get_match_data(dev);
735 if (!data->cfg)
736 return -EINVAL;
737
738 data->base = devm_platform_ioremap_resource_byname(pdev, name: "phy_ctrl");
739 if (IS_ERR(ptr: data->base))
740 return PTR_ERR(ptr: data->base);
741
742 data->id_det_gpio = devm_gpiod_get_optional(dev, con_id: "usb0_id_det",
743 flags: GPIOD_IN);
744 if (IS_ERR(ptr: data->id_det_gpio)) {
745 dev_err(dev, "Couldn't request ID GPIO\n");
746 return PTR_ERR(ptr: data->id_det_gpio);
747 }
748
749 data->vbus_det_gpio = devm_gpiod_get_optional(dev, con_id: "usb0_vbus_det",
750 flags: GPIOD_IN);
751 if (IS_ERR(ptr: data->vbus_det_gpio)) {
752 dev_err(dev, "Couldn't request VBUS detect GPIO\n");
753 return PTR_ERR(ptr: data->vbus_det_gpio);
754 }
755
756 if (of_property_present(np, propname: "usb0_vbus_power-supply")) {
757 data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
758 property: "usb0_vbus_power-supply");
759 if (IS_ERR(ptr: data->vbus_power_supply)) {
760 dev_err(dev, "Couldn't get the VBUS power supply\n");
761 return PTR_ERR(ptr: data->vbus_power_supply);
762 }
763
764 if (!data->vbus_power_supply)
765 return -EPROBE_DEFER;
766 }
767
768 data->dr_mode = of_usb_get_dr_mode_by_phy(np, arg0: 0);
769
770 data->extcon = devm_extcon_dev_allocate(dev, cable: sun4i_usb_phy0_cable);
771 if (IS_ERR(ptr: data->extcon)) {
772 dev_err(dev, "Couldn't allocate our extcon device\n");
773 return PTR_ERR(ptr: data->extcon);
774 }
775
776 ret = devm_extcon_dev_register(dev, edev: data->extcon);
777 if (ret) {
778 dev_err(dev, "failed to register extcon: %d\n", ret);
779 return ret;
780 }
781
782 for (i = 0; i < data->cfg->num_phys; i++) {
783 struct sun4i_usb_phy *phy = data->phys + i;
784 char name[32];
785
786 if (data->cfg->missing_phys & BIT(i))
787 continue;
788
789 snprintf(buf: name, size: sizeof(name), fmt: "usb%d_vbus", i);
790 phy->vbus = devm_regulator_get_optional(dev, id: name);
791 if (IS_ERR(ptr: phy->vbus)) {
792 if (PTR_ERR(ptr: phy->vbus) == -EPROBE_DEFER) {
793 dev_err(dev,
794 "Couldn't get regulator %s... Deferring probe\n",
795 name);
796 return -EPROBE_DEFER;
797 }
798
799 phy->vbus = NULL;
800 }
801
802 if (data->cfg->dedicated_clocks)
803 snprintf(buf: name, size: sizeof(name), fmt: "usb%d_phy", i);
804 else
805 strscpy(name, "usb_phy", sizeof(name));
806
807 phy->clk = devm_clk_get(dev, id: name);
808 if (IS_ERR(ptr: phy->clk)) {
809 dev_err(dev, "failed to get clock %s\n", name);
810 return PTR_ERR(ptr: phy->clk);
811 }
812
813 /* The first PHY is always tied to OTG, and never HSIC */
814 if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
815 /* HSIC needs secondary clock */
816 snprintf(buf: name, size: sizeof(name), fmt: "usb%d_hsic_12M", i);
817 phy->clk2 = devm_clk_get(dev, id: name);
818 if (IS_ERR(ptr: phy->clk2)) {
819 dev_err(dev, "failed to get clock %s\n", name);
820 return PTR_ERR(ptr: phy->clk2);
821 }
822 } else {
823 snprintf(buf: name, size: sizeof(name), fmt: "pmu%d_clk", i);
824 phy->clk2 = devm_clk_get_optional(dev, id: name);
825 if (IS_ERR(ptr: phy->clk2)) {
826 dev_err(dev, "failed to get clock %s\n", name);
827 return PTR_ERR(ptr: phy->clk2);
828 }
829 }
830
831 snprintf(buf: name, size: sizeof(name), fmt: "usb%d_reset", i);
832 phy->reset = devm_reset_control_get(dev, id: name);
833 if (IS_ERR(ptr: phy->reset)) {
834 dev_err(dev, "failed to get reset %s\n", name);
835 return PTR_ERR(ptr: phy->reset);
836 }
837
838 if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
839 snprintf(buf: name, size: sizeof(name), fmt: "pmu%d", i);
840 phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
841 if (IS_ERR(ptr: phy->pmu))
842 return PTR_ERR(ptr: phy->pmu);
843 }
844
845 phy->phy = devm_phy_create(dev, NULL, ops: &sun4i_usb_phy_ops);
846 if (IS_ERR(ptr: phy->phy)) {
847 dev_err(dev, "failed to create PHY %d\n", i);
848 return PTR_ERR(ptr: phy->phy);
849 }
850
851 phy->index = i;
852 phy_set_drvdata(phy: phy->phy, data: &data->phys[i]);
853 }
854
855 data->id_det_irq = gpiod_to_irq(desc: data->id_det_gpio);
856 if (data->id_det_irq > 0) {
857 ret = devm_request_irq(dev, irq: data->id_det_irq,
858 handler: sun4i_usb_phy0_id_vbus_det_irq,
859 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
860 devname: "usb0-id-det", dev_id: data);
861 if (ret) {
862 dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
863 return ret;
864 }
865 }
866
867 data->vbus_det_irq = gpiod_to_irq(desc: data->vbus_det_gpio);
868 if (data->vbus_det_irq > 0) {
869 ret = devm_request_irq(dev, irq: data->vbus_det_irq,
870 handler: sun4i_usb_phy0_id_vbus_det_irq,
871 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
872 devname: "usb0-vbus-det", dev_id: data);
873 if (ret) {
874 dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
875 data->vbus_det_irq = -1;
876 sun4i_usb_phy_remove(pdev); /* Stop detect work */
877 return ret;
878 }
879 }
880
881 if (data->vbus_power_supply) {
882 data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
883 data->vbus_power_nb.priority = 0;
884 ret = power_supply_reg_notifier(nb: &data->vbus_power_nb);
885 if (ret) {
886 sun4i_usb_phy_remove(pdev); /* Stop detect work */
887 return ret;
888 }
889 data->vbus_power_nb_registered = true;
890 }
891
892 phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
893 if (IS_ERR(ptr: phy_provider)) {
894 sun4i_usb_phy_remove(pdev); /* Stop detect work */
895 return PTR_ERR(ptr: phy_provider);
896 }
897
898 dev_dbg(dev, "successfully loaded\n");
899
900 return 0;
901}
902
903static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
904 .num_phys = 1,
905 .disc_thresh = 3,
906 .phyctl_offset = REG_PHYCTL_A10,
907 .dedicated_clocks = true,
908};
909
910static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
911 .num_phys = 3,
912 .disc_thresh = 3,
913 .phyctl_offset = REG_PHYCTL_A10,
914 .dedicated_clocks = false,
915};
916
917static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
918 .num_phys = 2,
919 .disc_thresh = 2,
920 .phyctl_offset = REG_PHYCTL_A10,
921 .dedicated_clocks = false,
922};
923
924static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
925 .num_phys = 3,
926 .disc_thresh = 3,
927 .phyctl_offset = REG_PHYCTL_A10,
928 .dedicated_clocks = true,
929 .poll_vbusen = true,
930};
931
932static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
933 .num_phys = 3,
934 .disc_thresh = 2,
935 .phyctl_offset = REG_PHYCTL_A10,
936 .dedicated_clocks = false,
937};
938
939static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
940 .num_phys = 2,
941 .disc_thresh = 3,
942 .phyctl_offset = REG_PHYCTL_A10,
943 .dedicated_clocks = true,
944 .poll_vbusen = true,
945};
946
947static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
948 .num_phys = 2,
949 .disc_thresh = 3,
950 .phyctl_offset = REG_PHYCTL_A33,
951 .dedicated_clocks = true,
952 .poll_vbusen = true,
953};
954
955static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
956 .num_phys = 3,
957 .hsic_index = 2,
958 .phyctl_offset = REG_PHYCTL_A33,
959 .dedicated_clocks = true,
960 .siddq_in_base = true,
961};
962
963static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
964 .num_phys = 4,
965 .disc_thresh = 3,
966 .phyctl_offset = REG_PHYCTL_A33,
967 .dedicated_clocks = true,
968 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
969 .phy0_dual_route = true,
970};
971
972static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
973 .num_phys = 3,
974 .disc_thresh = 3,
975 .phyctl_offset = REG_PHYCTL_A33,
976 .dedicated_clocks = true,
977 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
978 .phy0_dual_route = true,
979};
980
981static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
982 .num_phys = 1,
983 .disc_thresh = 3,
984 .phyctl_offset = REG_PHYCTL_A33,
985 .dedicated_clocks = true,
986 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
987 .phy0_dual_route = true,
988};
989
990static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
991 .num_phys = 2,
992 .phyctl_offset = REG_PHYCTL_A33,
993 .dedicated_clocks = true,
994 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
995 .phy0_dual_route = true,
996 .siddq_in_base = true,
997};
998
999static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1000 .num_phys = 2,
1001 .disc_thresh = 3,
1002 .phyctl_offset = REG_PHYCTL_A33,
1003 .dedicated_clocks = true,
1004 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
1005 .phy0_dual_route = true,
1006};
1007
1008static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1009 .num_phys = 4,
1010 .phyctl_offset = REG_PHYCTL_A33,
1011 .dedicated_clocks = true,
1012 .phy0_dual_route = true,
1013 .missing_phys = BIT(1) | BIT(2),
1014 .siddq_in_base = true,
1015};
1016
1017static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1018 .num_phys = 4,
1019 .disc_thresh = 3,
1020 .phyctl_offset = REG_PHYCTL_A33,
1021 .dedicated_clocks = true,
1022 .phy0_dual_route = true,
1023 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1024 .needs_phy2_siddq = true,
1025 .siddq_in_base = true,
1026};
1027
1028static const struct of_device_id sun4i_usb_phy_of_match[] = {
1029 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
1030 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
1031 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
1032 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
1033 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
1034 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
1035 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
1036 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
1037 { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
1038 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
1039 { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
1040 { .compatible = "allwinner,sun50i-a64-usb-phy",
1041 .data = &sun50i_a64_cfg},
1042 { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
1043 { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1044 { .compatible = "allwinner,suniv-f1c100s-usb-phy",
1045 .data = &suniv_f1c100s_cfg },
1046 { },
1047};
1048MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
1049
1050static struct platform_driver sun4i_usb_phy_driver = {
1051 .probe = sun4i_usb_phy_probe,
1052 .remove = sun4i_usb_phy_remove,
1053 .driver = {
1054 .of_match_table= sun4i_usb_phy_of_match,
1055 .name = "sun4i-usb-phy",
1056 }
1057};
1058module_platform_driver(sun4i_usb_phy_driver);
1059
1060MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
1061MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1062MODULE_LICENSE("GPL v2");
1063

source code of linux/drivers/phy/allwinner/phy-sun4i-usb.c