1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21#include <linux/reset.h>
22#include <linux/slab.h>
23#include <linux/usb/typec.h>
24#include <linux/usb/typec_mux.h>
25
26#include "phy-qcom-qmp-common.h"
27
28#include "phy-qcom-qmp.h"
29#include "phy-qcom-qmp-pcs-misc-v3.h"
30
31#define PHY_INIT_COMPLETE_TIMEOUT 10000
32
33/* set of registers with offsets different per-PHY */
34enum qphy_reg_layout {
35 /* PCS registers */
36 QPHY_SW_RESET,
37 QPHY_START_CTRL,
38 QPHY_PCS_STATUS,
39 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
40 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
41 QPHY_PCS_POWER_DOWN_CONTROL,
42 /* Keep last to ensure regs_layout arrays are properly initialized */
43 QPHY_LAYOUT_SIZE
44};
45
46static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
47 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
48 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
49 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
50 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
51 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
52 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
53};
54
55static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
56 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
57 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
58 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
59 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
60 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
61 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
62};
63
64static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
65 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
66 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
67 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
68 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
69 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
70 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
71 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
72 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
73 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
74 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
75 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
76 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
77 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
78 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
79 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
80 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
81 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
82 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
83 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
84 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
85 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
86 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
87 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
88 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
89 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
90 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
91 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
92 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
93 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
94 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
95 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
96 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
103};
104
105static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
106 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
107 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
108 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
109 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
110};
111
112static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
113 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
114 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
115 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
116 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
117 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
118 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
119 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
120 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
121 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
122 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
123 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
124 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
125 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
126 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
127 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
128 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
129 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
130};
131
132static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
133 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
134 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
135 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
136 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
137 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
138 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
139 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
140 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
141 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
142 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
143 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
144 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
145 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
146 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
147 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
148 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
149 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
150 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
151 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
152 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
153 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
154 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
155 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
156 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
157 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
158 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
159 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
160 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
161 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
171};
172
173static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
174 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
175 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
176 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
177 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
178 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
179 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
180 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
181 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
182 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
183 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
184 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
185 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
186 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
187 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
188 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
189 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
190 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
191 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
192 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
193 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
194 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
195 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
196 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
197 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
198 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
199 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
200 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
201 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
202 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
203 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
204 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
205 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
206 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
207 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
208 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
209 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
210 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
211 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
212};
213
214static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
215 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
216 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
217 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
218 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
219 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
220};
221
222static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
223 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
224 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
225 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
226 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
227 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
228 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
229 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
230 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
231 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
232 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
233 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
234 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
235 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
236 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
237 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
238 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
239 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
240};
241
242/* the only difference is QSERDES_V3_RX_UCDR_PI_CONTROLS */
243static const struct qmp_phy_init_tbl sdm660_usb3_rx_tbl[] = {
244 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
245 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
246 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
247 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
248 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
249 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
250 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
251 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
252 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
253 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
254 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
255 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
261};
262
263static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
264 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
265 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
266 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
267 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
268 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
285};
286
287struct qmp_usbc_offsets {
288 u16 serdes;
289 u16 pcs;
290 u16 pcs_misc;
291 u16 tx;
292 u16 rx;
293 /* for PHYs with >= 2 lanes */
294 u16 tx2;
295 u16 rx2;
296};
297
298/* struct qmp_phy_cfg - per-PHY initialization config */
299struct qmp_phy_cfg {
300 const struct qmp_usbc_offsets *offsets;
301
302 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
303 const struct qmp_phy_init_tbl *serdes_tbl;
304 int serdes_tbl_num;
305 const struct qmp_phy_init_tbl *tx_tbl;
306 int tx_tbl_num;
307 const struct qmp_phy_init_tbl *rx_tbl;
308 int rx_tbl_num;
309 const struct qmp_phy_init_tbl *pcs_tbl;
310 int pcs_tbl_num;
311
312 /* regulators to be requested */
313 const char * const *vreg_list;
314 int num_vregs;
315
316 /* array of registers with different offsets */
317 const unsigned int *regs;
318};
319
320struct qmp_usbc {
321 struct device *dev;
322
323 const struct qmp_phy_cfg *cfg;
324
325 void __iomem *serdes;
326 void __iomem *pcs;
327 void __iomem *pcs_misc;
328 void __iomem *tx;
329 void __iomem *rx;
330 void __iomem *tx2;
331 void __iomem *rx2;
332
333 struct regmap *tcsr_map;
334 u32 vls_clamp_reg;
335
336 struct clk *pipe_clk;
337 struct clk_bulk_data *clks;
338 int num_clks;
339 int num_resets;
340 struct reset_control_bulk_data *resets;
341 struct regulator_bulk_data *vregs;
342
343 struct mutex phy_mutex;
344
345 enum phy_mode mode;
346 unsigned int usb_init_count;
347
348 struct phy *phy;
349
350 struct clk_fixed_rate pipe_clk_fixed;
351
352 struct typec_switch_dev *sw;
353 enum typec_orientation orientation;
354};
355
356static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
357{
358 u32 reg;
359
360 reg = readl(addr: base + offset);
361 reg |= val;
362 writel(val: reg, addr: base + offset);
363
364 /* ensure that above write is through */
365 readl(addr: base + offset);
366}
367
368static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
369{
370 u32 reg;
371
372 reg = readl(addr: base + offset);
373 reg &= ~val;
374 writel(val: reg, addr: base + offset);
375
376 /* ensure that above write is through */
377 readl(addr: base + offset);
378}
379
380/* list of clocks required by phy */
381static const char * const qmp_usbc_phy_clk_l[] = {
382 "aux", "cfg_ahb", "ref", "com_aux",
383};
384
385/* list of resets */
386static const char * const usb3phy_legacy_reset_l[] = {
387 "phy", "common",
388};
389
390static const char * const usb3phy_reset_l[] = {
391 "phy_phy", "phy",
392};
393
394/* list of regulators */
395static const char * const qmp_phy_vreg_l[] = {
396 "vdda-phy", "vdda-pll",
397};
398
399static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 = {
400 .serdes = 0x0,
401 .pcs = 0xc00,
402 .pcs_misc = 0xa00,
403 .tx = 0x200,
404 .rx = 0x400,
405 .tx2 = 0x600,
406 .rx2 = 0x800,
407};
408
409static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
410 .offsets = &qmp_usbc_offsets_v3_qcm2290,
411
412 .serdes_tbl = msm8998_usb3_serdes_tbl,
413 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
414 .tx_tbl = msm8998_usb3_tx_tbl,
415 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
416 .rx_tbl = msm8998_usb3_rx_tbl,
417 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
418 .pcs_tbl = msm8998_usb3_pcs_tbl,
419 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
420 .vreg_list = qmp_phy_vreg_l,
421 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
422 .regs = qmp_v3_usb3phy_regs_layout,
423};
424
425static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
426 .offsets = &qmp_usbc_offsets_v3_qcm2290,
427
428 .serdes_tbl = qcm2290_usb3_serdes_tbl,
429 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
430 .tx_tbl = qcm2290_usb3_tx_tbl,
431 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
432 .rx_tbl = qcm2290_usb3_rx_tbl,
433 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
434 .pcs_tbl = qcm2290_usb3_pcs_tbl,
435 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
436 .vreg_list = qmp_phy_vreg_l,
437 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
438 .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
439};
440
441static const struct qmp_phy_cfg sdm660_usb3phy_cfg = {
442 .offsets = &qmp_usbc_offsets_v3_qcm2290,
443
444 .serdes_tbl = qcm2290_usb3_serdes_tbl,
445 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
446 .tx_tbl = qcm2290_usb3_tx_tbl,
447 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
448 .rx_tbl = sdm660_usb3_rx_tbl,
449 .rx_tbl_num = ARRAY_SIZE(sdm660_usb3_rx_tbl),
450 .pcs_tbl = qcm2290_usb3_pcs_tbl,
451 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
452 .vreg_list = qmp_phy_vreg_l,
453 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
454 .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
455};
456
457static int qmp_usbc_init(struct phy *phy)
458{
459 struct qmp_usbc *qmp = phy_get_drvdata(phy);
460 const struct qmp_phy_cfg *cfg = qmp->cfg;
461 void __iomem *pcs = qmp->pcs;
462 u32 val = 0;
463 int ret;
464
465 ret = regulator_bulk_enable(num_consumers: cfg->num_vregs, consumers: qmp->vregs);
466 if (ret) {
467 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
468 return ret;
469 }
470
471 ret = reset_control_bulk_assert(num_rstcs: qmp->num_resets, rstcs: qmp->resets);
472 if (ret) {
473 dev_err(qmp->dev, "reset assert failed\n");
474 goto err_disable_regulators;
475 }
476
477 ret = reset_control_bulk_deassert(num_rstcs: qmp->num_resets, rstcs: qmp->resets);
478 if (ret) {
479 dev_err(qmp->dev, "reset deassert failed\n");
480 goto err_disable_regulators;
481 }
482
483 ret = clk_bulk_prepare_enable(num_clks: qmp->num_clks, clks: qmp->clks);
484 if (ret)
485 goto err_assert_reset;
486
487 qphy_setbits(base: pcs, offset: cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
488
489#define SW_PORTSELECT_VAL BIT(0)
490#define SW_PORTSELECT_MUX BIT(1)
491 /* Use software based port select and switch on typec orientation */
492 val = SW_PORTSELECT_MUX;
493 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
494 val |= SW_PORTSELECT_VAL;
495 writel(val, addr: qmp->pcs_misc);
496
497 return 0;
498
499err_assert_reset:
500 reset_control_bulk_assert(num_rstcs: qmp->num_resets, rstcs: qmp->resets);
501err_disable_regulators:
502 regulator_bulk_disable(num_consumers: cfg->num_vregs, consumers: qmp->vregs);
503
504 return ret;
505}
506
507static int qmp_usbc_exit(struct phy *phy)
508{
509 struct qmp_usbc *qmp = phy_get_drvdata(phy);
510 const struct qmp_phy_cfg *cfg = qmp->cfg;
511
512 reset_control_bulk_assert(num_rstcs: qmp->num_resets, rstcs: qmp->resets);
513
514 clk_bulk_disable_unprepare(num_clks: qmp->num_clks, clks: qmp->clks);
515
516 regulator_bulk_disable(num_consumers: cfg->num_vregs, consumers: qmp->vregs);
517
518 return 0;
519}
520
521static int qmp_usbc_power_on(struct phy *phy)
522{
523 struct qmp_usbc *qmp = phy_get_drvdata(phy);
524 const struct qmp_phy_cfg *cfg = qmp->cfg;
525 void __iomem *status;
526 unsigned int val;
527 int ret;
528
529 qmp_configure(base: qmp->serdes, tbl: cfg->serdes_tbl, num: cfg->serdes_tbl_num);
530
531 ret = clk_prepare_enable(clk: qmp->pipe_clk);
532 if (ret) {
533 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
534 return ret;
535 }
536
537 /* Tx, Rx, and PCS configurations */
538 qmp_configure_lane(base: qmp->tx, tbl: cfg->tx_tbl, num: cfg->tx_tbl_num, lane_mask: 1);
539 qmp_configure_lane(base: qmp->rx, tbl: cfg->rx_tbl, num: cfg->rx_tbl_num, lane_mask: 1);
540
541 qmp_configure_lane(base: qmp->tx2, tbl: cfg->tx_tbl, num: cfg->tx_tbl_num, lane_mask: 2);
542 qmp_configure_lane(base: qmp->rx2, tbl: cfg->rx_tbl, num: cfg->rx_tbl_num, lane_mask: 2);
543
544 qmp_configure(base: qmp->pcs, tbl: cfg->pcs_tbl, num: cfg->pcs_tbl_num);
545
546 /* Pull PHY out of reset state */
547 qphy_clrbits(base: qmp->pcs, offset: cfg->regs[QPHY_SW_RESET], SW_RESET);
548
549 /* start SerDes and Phy-Coding-Sublayer */
550 qphy_setbits(base: qmp->pcs, offset: cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
551
552 status = qmp->pcs + cfg->regs[QPHY_PCS_STATUS];
553 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
554 PHY_INIT_COMPLETE_TIMEOUT);
555 if (ret) {
556 dev_err(qmp->dev, "phy initialization timed-out\n");
557 goto err_disable_pipe_clk;
558 }
559
560 return 0;
561
562err_disable_pipe_clk:
563 clk_disable_unprepare(clk: qmp->pipe_clk);
564
565 return ret;
566}
567
568static int qmp_usbc_power_off(struct phy *phy)
569{
570 struct qmp_usbc *qmp = phy_get_drvdata(phy);
571 const struct qmp_phy_cfg *cfg = qmp->cfg;
572
573 clk_disable_unprepare(clk: qmp->pipe_clk);
574
575 /* PHY reset */
576 qphy_setbits(base: qmp->pcs, offset: cfg->regs[QPHY_SW_RESET], SW_RESET);
577
578 /* stop SerDes and Phy-Coding-Sublayer */
579 qphy_clrbits(base: qmp->pcs, offset: cfg->regs[QPHY_START_CTRL],
580 SERDES_START | PCS_START);
581
582 /* Put PHY into POWER DOWN state: active low */
583 qphy_clrbits(base: qmp->pcs, offset: cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
584 SW_PWRDN);
585
586 return 0;
587}
588
589static int qmp_usbc_enable(struct phy *phy)
590{
591 struct qmp_usbc *qmp = phy_get_drvdata(phy);
592 int ret;
593
594 mutex_lock(&qmp->phy_mutex);
595
596 ret = qmp_usbc_init(phy);
597 if (ret)
598 goto out_unlock;
599
600 ret = qmp_usbc_power_on(phy);
601 if (ret) {
602 qmp_usbc_exit(phy);
603 goto out_unlock;
604 }
605
606 qmp->usb_init_count++;
607out_unlock:
608 mutex_unlock(lock: &qmp->phy_mutex);
609
610 return ret;
611}
612
613static int qmp_usbc_disable(struct phy *phy)
614{
615 struct qmp_usbc *qmp = phy_get_drvdata(phy);
616 int ret;
617
618 qmp->usb_init_count--;
619 ret = qmp_usbc_power_off(phy);
620 if (ret)
621 return ret;
622 return qmp_usbc_exit(phy);
623}
624
625static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int submode)
626{
627 struct qmp_usbc *qmp = phy_get_drvdata(phy);
628
629 qmp->mode = mode;
630
631 return 0;
632}
633
634static const struct phy_ops qmp_usbc_phy_ops = {
635 .init = qmp_usbc_enable,
636 .exit = qmp_usbc_disable,
637 .set_mode = qmp_usbc_set_mode,
638 .owner = THIS_MODULE,
639};
640
641static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp)
642{
643 const struct qmp_phy_cfg *cfg = qmp->cfg;
644 void __iomem *pcs = qmp->pcs;
645 u32 intr_mask;
646
647 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
648 qmp->mode == PHY_MODE_USB_DEVICE_SS)
649 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
650 else
651 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
652
653 /* Clear any pending interrupts status */
654 qphy_setbits(base: pcs, offset: cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
655 /* Writing 1 followed by 0 clears the interrupt */
656 qphy_clrbits(base: pcs, offset: cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
657
658 qphy_clrbits(base: pcs, offset: cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
659 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
660
661 /* Enable required PHY autonomous mode interrupts */
662 qphy_setbits(base: pcs, offset: cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], val: intr_mask);
663
664 /* Enable i/o clamp_n for autonomous mode */
665 if (qmp->tcsr_map && qmp->vls_clamp_reg)
666 regmap_write(map: qmp->tcsr_map, reg: qmp->vls_clamp_reg, val: 1);
667}
668
669static void qmp_usbc_disable_autonomous_mode(struct qmp_usbc *qmp)
670{
671 const struct qmp_phy_cfg *cfg = qmp->cfg;
672 void __iomem *pcs = qmp->pcs;
673
674 /* Disable i/o clamp_n on resume for normal mode */
675 if (qmp->tcsr_map && qmp->vls_clamp_reg)
676 regmap_write(map: qmp->tcsr_map, reg: qmp->vls_clamp_reg, val: 0);
677
678 qphy_clrbits(base: pcs, offset: cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
679 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
680
681 qphy_setbits(base: pcs, offset: cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
682 /* Writing 1 followed by 0 clears the interrupt */
683 qphy_clrbits(base: pcs, offset: cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
684}
685
686static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev)
687{
688 struct qmp_usbc *qmp = dev_get_drvdata(dev);
689
690 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
691
692 if (!qmp->phy->init_count) {
693 dev_vdbg(dev, "PHY not initialized, bailing out\n");
694 return 0;
695 }
696
697 qmp_usbc_enable_autonomous_mode(qmp);
698
699 clk_disable_unprepare(clk: qmp->pipe_clk);
700 clk_bulk_disable_unprepare(num_clks: qmp->num_clks, clks: qmp->clks);
701
702 return 0;
703}
704
705static int __maybe_unused qmp_usbc_runtime_resume(struct device *dev)
706{
707 struct qmp_usbc *qmp = dev_get_drvdata(dev);
708 int ret = 0;
709
710 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
711
712 if (!qmp->phy->init_count) {
713 dev_vdbg(dev, "PHY not initialized, bailing out\n");
714 return 0;
715 }
716
717 ret = clk_bulk_prepare_enable(num_clks: qmp->num_clks, clks: qmp->clks);
718 if (ret)
719 return ret;
720
721 ret = clk_prepare_enable(clk: qmp->pipe_clk);
722 if (ret) {
723 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
724 clk_bulk_disable_unprepare(num_clks: qmp->num_clks, clks: qmp->clks);
725 return ret;
726 }
727
728 qmp_usbc_disable_autonomous_mode(qmp);
729
730 return 0;
731}
732
733static const struct dev_pm_ops qmp_usbc_pm_ops = {
734 SET_RUNTIME_PM_OPS(qmp_usbc_runtime_suspend,
735 qmp_usbc_runtime_resume, NULL)
736};
737
738static int qmp_usbc_vreg_init(struct qmp_usbc *qmp)
739{
740 const struct qmp_phy_cfg *cfg = qmp->cfg;
741 struct device *dev = qmp->dev;
742 int num = cfg->num_vregs;
743 int i;
744
745 qmp->vregs = devm_kcalloc(dev, n: num, size: sizeof(*qmp->vregs), GFP_KERNEL);
746 if (!qmp->vregs)
747 return -ENOMEM;
748
749 for (i = 0; i < num; i++)
750 qmp->vregs[i].supply = cfg->vreg_list[i];
751
752 return devm_regulator_bulk_get(dev, num_consumers: num, consumers: qmp->vregs);
753}
754
755static int qmp_usbc_reset_init(struct qmp_usbc *qmp,
756 const char *const *reset_list,
757 int num_resets)
758{
759 struct device *dev = qmp->dev;
760 int i;
761 int ret;
762
763 qmp->resets = devm_kcalloc(dev, n: num_resets,
764 size: sizeof(*qmp->resets), GFP_KERNEL);
765 if (!qmp->resets)
766 return -ENOMEM;
767
768 for (i = 0; i < num_resets; i++)
769 qmp->resets[i].id = reset_list[i];
770
771 qmp->num_resets = num_resets;
772
773 ret = devm_reset_control_bulk_get_exclusive(dev, num_rstcs: num_resets, rstcs: qmp->resets);
774 if (ret)
775 return dev_err_probe(dev, err: ret, fmt: "failed to get resets\n");
776
777 return 0;
778}
779
780static int qmp_usbc_clk_init(struct qmp_usbc *qmp)
781{
782 struct device *dev = qmp->dev;
783 int num = ARRAY_SIZE(qmp_usbc_phy_clk_l);
784 int i;
785
786 qmp->clks = devm_kcalloc(dev, n: num, size: sizeof(*qmp->clks), GFP_KERNEL);
787 if (!qmp->clks)
788 return -ENOMEM;
789
790 for (i = 0; i < num; i++)
791 qmp->clks[i].id = qmp_usbc_phy_clk_l[i];
792
793 qmp->num_clks = num;
794
795 return devm_clk_bulk_get_optional(dev, num_clks: num, clks: qmp->clks);
796}
797
798static void phy_clk_release_provider(void *res)
799{
800 of_clk_del_provider(np: res);
801}
802
803/*
804 * Register a fixed rate pipe clock.
805 *
806 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
807 * controls it. The <s>_pipe_clk coming out of the GCC is requested
808 * by the PHY driver for its operations.
809 * We register the <s>_pipe_clksrc here. The gcc driver takes care
810 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
811 * Below picture shows this relationship.
812 *
813 * +---------------+
814 * | PHY block |<<---------------------------------------+
815 * | | |
816 * | +-------+ | +-----+ |
817 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
818 * clk | +-------+ | +-----+
819 * +---------------+
820 */
821static int phy_pipe_clk_register(struct qmp_usbc *qmp, struct device_node *np)
822{
823 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
824 struct clk_init_data init = { };
825 int ret;
826
827 ret = of_property_read_string(np, propname: "clock-output-names", out_string: &init.name);
828 if (ret) {
829 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
830 return ret;
831 }
832
833 init.ops = &clk_fixed_rate_ops;
834
835 /* controllers using QMP phys use 125MHz pipe clock interface */
836 fixed->fixed_rate = 125000000;
837 fixed->hw.init = &init;
838
839 ret = devm_clk_hw_register(dev: qmp->dev, hw: &fixed->hw);
840 if (ret)
841 return ret;
842
843 ret = of_clk_add_hw_provider(np, get: of_clk_hw_simple_get, data: &fixed->hw);
844 if (ret)
845 return ret;
846
847 /*
848 * Roll a devm action because the clock provider is the child node, but
849 * the child node is not actually a device.
850 */
851 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
852}
853
854#if IS_ENABLED(CONFIG_TYPEC)
855static int qmp_usbc_typec_switch_set(struct typec_switch_dev *sw,
856 enum typec_orientation orientation)
857{
858 struct qmp_usbc *qmp = typec_switch_get_drvdata(sw);
859
860 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
861 return 0;
862
863 mutex_lock(&qmp->phy_mutex);
864 qmp->orientation = orientation;
865
866 if (qmp->usb_init_count) {
867 qmp_usbc_power_off(phy: qmp->phy);
868 qmp_usbc_exit(phy: qmp->phy);
869
870 qmp_usbc_init(phy: qmp->phy);
871 qmp_usbc_power_on(phy: qmp->phy);
872 }
873
874 mutex_unlock(lock: &qmp->phy_mutex);
875
876 return 0;
877}
878
879static void qmp_usbc_typec_unregister(void *data)
880{
881 struct qmp_usbc *qmp = data;
882
883 typec_switch_unregister(sw: qmp->sw);
884}
885
886static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
887{
888 struct typec_switch_desc sw_desc = {};
889 struct device *dev = qmp->dev;
890
891 sw_desc.drvdata = qmp;
892 sw_desc.fwnode = dev->fwnode;
893 sw_desc.set = qmp_usbc_typec_switch_set;
894 qmp->sw = typec_switch_register(parent: dev, desc: &sw_desc);
895 if (IS_ERR(ptr: qmp->sw)) {
896 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
897 return PTR_ERR(ptr: qmp->sw);
898 }
899
900 return devm_add_action_or_reset(dev, qmp_usbc_typec_unregister, qmp);
901}
902#else
903static int qmp_usbc_typec_switch_register(struct qmp_usbc *qmp)
904{
905 return 0;
906}
907#endif
908
909static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_node *np)
910{
911 struct platform_device *pdev = to_platform_device(qmp->dev);
912 struct device *dev = qmp->dev;
913 int ret;
914
915 qmp->serdes = devm_platform_ioremap_resource(pdev, index: 0);
916 if (IS_ERR(ptr: qmp->serdes))
917 return PTR_ERR(ptr: qmp->serdes);
918
919 /*
920 * Get memory resources for the PHY:
921 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
922 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
923 * For single lane PHYs: pcs_misc (optional) -> 3.
924 */
925 qmp->tx = devm_of_iomap(dev, node: np, index: 0, NULL);
926 if (IS_ERR(ptr: qmp->tx))
927 return PTR_ERR(ptr: qmp->tx);
928
929 qmp->rx = devm_of_iomap(dev, node: np, index: 1, NULL);
930 if (IS_ERR(ptr: qmp->rx))
931 return PTR_ERR(ptr: qmp->rx);
932
933 qmp->pcs = devm_of_iomap(dev, node: np, index: 2, NULL);
934 if (IS_ERR(ptr: qmp->pcs))
935 return PTR_ERR(ptr: qmp->pcs);
936
937 qmp->tx2 = devm_of_iomap(dev, node: np, index: 3, NULL);
938 if (IS_ERR(ptr: qmp->tx2))
939 return PTR_ERR(ptr: qmp->tx2);
940
941 qmp->rx2 = devm_of_iomap(dev, node: np, index: 4, NULL);
942 if (IS_ERR(ptr: qmp->rx2))
943 return PTR_ERR(ptr: qmp->rx2);
944
945 qmp->pcs_misc = devm_of_iomap(dev, node: np, index: 5, NULL);
946 if (IS_ERR(ptr: qmp->pcs_misc)) {
947 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
948 qmp->pcs_misc = NULL;
949 }
950
951 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
952 if (IS_ERR(ptr: qmp->pipe_clk)) {
953 return dev_err_probe(dev, err: PTR_ERR(ptr: qmp->pipe_clk),
954 fmt: "failed to get pipe clock\n");
955 }
956
957 ret = devm_clk_bulk_get_all(dev: qmp->dev, clks: &qmp->clks);
958 if (ret < 0)
959 return ret;
960
961 qmp->num_clks = ret;
962
963 ret = qmp_usbc_reset_init(qmp, reset_list: usb3phy_legacy_reset_l,
964 ARRAY_SIZE(usb3phy_legacy_reset_l));
965 if (ret)
966 return ret;
967
968 return 0;
969}
970
971static int qmp_usbc_parse_dt(struct qmp_usbc *qmp)
972{
973 struct platform_device *pdev = to_platform_device(qmp->dev);
974 const struct qmp_phy_cfg *cfg = qmp->cfg;
975 const struct qmp_usbc_offsets *offs = cfg->offsets;
976 struct device *dev = qmp->dev;
977 void __iomem *base;
978 int ret;
979
980 if (!offs)
981 return -EINVAL;
982
983 base = devm_platform_ioremap_resource(pdev, index: 0);
984 if (IS_ERR(ptr: base))
985 return PTR_ERR(ptr: base);
986
987 qmp->serdes = base + offs->serdes;
988 qmp->pcs = base + offs->pcs;
989 if (offs->pcs_misc)
990 qmp->pcs_misc = base + offs->pcs_misc;
991 qmp->tx = base + offs->tx;
992 qmp->rx = base + offs->rx;
993
994 qmp->tx2 = base + offs->tx2;
995 qmp->rx2 = base + offs->rx2;
996
997 ret = qmp_usbc_clk_init(qmp);
998 if (ret)
999 return ret;
1000
1001 qmp->pipe_clk = devm_clk_get(dev, id: "pipe");
1002 if (IS_ERR(ptr: qmp->pipe_clk)) {
1003 return dev_err_probe(dev, err: PTR_ERR(ptr: qmp->pipe_clk),
1004 fmt: "failed to get pipe clock\n");
1005 }
1006
1007 ret = qmp_usbc_reset_init(qmp, reset_list: usb3phy_reset_l,
1008 ARRAY_SIZE(usb3phy_reset_l));
1009 if (ret)
1010 return ret;
1011
1012 return 0;
1013}
1014
1015static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp)
1016{
1017 struct of_phandle_args tcsr_args;
1018 struct device *dev = qmp->dev;
1019 int ret;
1020
1021 /* for backwards compatibility ignore if there is no property */
1022 ret = of_parse_phandle_with_fixed_args(np: dev->of_node, list_name: "qcom,tcsr-reg", cell_count: 1, index: 0,
1023 out_args: &tcsr_args);
1024 if (ret == -ENOENT)
1025 return 0;
1026 else if (ret < 0)
1027 return dev_err_probe(dev, err: ret, fmt: "Failed to parse qcom,tcsr-reg\n");
1028
1029 qmp->tcsr_map = syscon_node_to_regmap(np: tcsr_args.np);
1030 of_node_put(node: tcsr_args.np);
1031 if (IS_ERR(ptr: qmp->tcsr_map))
1032 return PTR_ERR(ptr: qmp->tcsr_map);
1033
1034 qmp->vls_clamp_reg = tcsr_args.args[0];
1035
1036 return 0;
1037}
1038
1039static int qmp_usbc_probe(struct platform_device *pdev)
1040{
1041 struct device *dev = &pdev->dev;
1042 struct phy_provider *phy_provider;
1043 struct device_node *np;
1044 struct qmp_usbc *qmp;
1045 int ret;
1046
1047 qmp = devm_kzalloc(dev, size: sizeof(*qmp), GFP_KERNEL);
1048 if (!qmp)
1049 return -ENOMEM;
1050
1051 qmp->dev = dev;
1052
1053 qmp->orientation = TYPEC_ORIENTATION_NORMAL;
1054
1055 qmp->cfg = of_device_get_match_data(dev);
1056 if (!qmp->cfg)
1057 return -EINVAL;
1058
1059 mutex_init(&qmp->phy_mutex);
1060
1061 ret = qmp_usbc_vreg_init(qmp);
1062 if (ret)
1063 return ret;
1064
1065 ret = qmp_usbc_typec_switch_register(qmp);
1066 if (ret)
1067 return ret;
1068
1069 ret = qmp_usbc_parse_vls_clamp(qmp);
1070 if (ret)
1071 return ret;
1072
1073 /* Check for legacy binding with child node. */
1074 np = of_get_child_by_name(node: dev->of_node, name: "phy");
1075 if (np) {
1076 ret = qmp_usbc_parse_dt_legacy(qmp, np);
1077 } else {
1078 np = of_node_get(node: dev->of_node);
1079 ret = qmp_usbc_parse_dt(qmp);
1080 }
1081 if (ret)
1082 goto err_node_put;
1083
1084 pm_runtime_set_active(dev);
1085 ret = devm_pm_runtime_enable(dev);
1086 if (ret)
1087 goto err_node_put;
1088 /*
1089 * Prevent runtime pm from being ON by default. Users can enable
1090 * it using power/control in sysfs.
1091 */
1092 pm_runtime_forbid(dev);
1093
1094 ret = phy_pipe_clk_register(qmp, np);
1095 if (ret)
1096 goto err_node_put;
1097
1098 qmp->phy = devm_phy_create(dev, node: np, ops: &qmp_usbc_phy_ops);
1099 if (IS_ERR(ptr: qmp->phy)) {
1100 ret = PTR_ERR(ptr: qmp->phy);
1101 dev_err(dev, "failed to create PHY: %d\n", ret);
1102 goto err_node_put;
1103 }
1104
1105 phy_set_drvdata(phy: qmp->phy, data: qmp);
1106
1107 of_node_put(node: np);
1108
1109 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1110
1111 return PTR_ERR_OR_ZERO(ptr: phy_provider);
1112
1113err_node_put:
1114 of_node_put(node: np);
1115 return ret;
1116}
1117
1118static const struct of_device_id qmp_usbc_of_match_table[] = {
1119 {
1120 .compatible = "qcom,msm8998-qmp-usb3-phy",
1121 .data = &msm8998_usb3phy_cfg,
1122 }, {
1123 .compatible = "qcom,qcm2290-qmp-usb3-phy",
1124 .data = &qcm2290_usb3phy_cfg,
1125 }, {
1126 .compatible = "qcom,sdm660-qmp-usb3-phy",
1127 .data = &sdm660_usb3phy_cfg,
1128 }, {
1129 .compatible = "qcom,sm6115-qmp-usb3-phy",
1130 .data = &qcm2290_usb3phy_cfg,
1131 },
1132 { },
1133};
1134MODULE_DEVICE_TABLE(of, qmp_usbc_of_match_table);
1135
1136static struct platform_driver qmp_usbc_driver = {
1137 .probe = qmp_usbc_probe,
1138 .driver = {
1139 .name = "qcom-qmp-usbc-phy",
1140 .pm = &qmp_usbc_pm_ops,
1141 .of_match_table = qmp_usbc_of_match_table,
1142 },
1143};
1144
1145module_platform_driver(qmp_usbc_driver);
1146
1147MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1148MODULE_DESCRIPTION("Qualcomm QMP USB-C PHY driver");
1149MODULE_LICENSE("GPL");
1150

source code of linux/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c