1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G2L Pin Control and GPIO driver core
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation.
6 */
7
8#include <linux/bitfield.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/property.h>
20#include <linux/seq_file.h>
21#include <linux/spinlock.h>
22
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/pinconf-generic.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28
29#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
32
33#include "../core.h"
34#include "../pinconf.h"
35#include "../pinmux.h"
36
37#define DRV_NAME "pinctrl-rzg2l"
38
39/*
40 * Use 16 lower bits [15:0] for pin identifier
41 * Use 16 higher bits [31:16] for pin mux function
42 */
43#define MUX_PIN_ID_MASK GENMASK(15, 0)
44#define MUX_FUNC_MASK GENMASK(31, 16)
45
46/* PIN capabilities */
47#define PIN_CFG_IOLH_A BIT(0)
48#define PIN_CFG_IOLH_B BIT(1)
49#define PIN_CFG_SR BIT(2)
50#define PIN_CFG_IEN BIT(3)
51#define PIN_CFG_PUPD BIT(4)
52#define PIN_CFG_IO_VMC_SD0 BIT(5)
53#define PIN_CFG_IO_VMC_SD1 BIT(6)
54#define PIN_CFG_IO_VMC_QSPI BIT(7)
55#define PIN_CFG_IO_VMC_ETH0 BIT(8)
56#define PIN_CFG_IO_VMC_ETH1 BIT(9)
57#define PIN_CFG_NF BIT(10) /* Digital noise filter */
58#define PIN_CFG_IOLH_C BIT(11)
59#define PIN_CFG_SOFT_PS BIT(12)
60#define PIN_CFG_OEN BIT(13)
61#define PIN_CFG_NOGPIO_INT BIT(14)
62#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
63#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
64#define PIN_CFG_ELC BIT(17)
65#define PIN_CFG_IOLH_RZV2H BIT(18)
66
67#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
68#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
69
70#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
71 (PIN_CFG_IOLH_##group | \
72 PIN_CFG_PUPD | \
73 PIN_CFG_NF)
74
75#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
76 PIN_CFG_SR)
77
78#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
79 PIN_CFG_SOFT_PS)
80
81#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
82 PIN_CFG_NOD | \
83 PIN_CFG_SR | \
84 PIN_CFG_SMT)
85
86#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
87
88#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
89#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
90#define PIN_CFG_MASK GENMASK_ULL(31, 0)
91
92/*
93 * m indicates the bitmap of supported pins, a is the register index
94 * and f is pin configuration capabilities supported.
95 */
96#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
98 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
99#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \
100 (RZG2L_VARIABLE_CFG | \
101 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
102
103/*
104 * n indicates number of pins in the port, a is the register index
105 * and f is pin configuration capabilities supported.
106 */
107#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
108#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \
109 RZG2L_GPIO_PORT_PACK(n, a, 0))
110
111#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
112#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
113/*
114 * p is the register index while referencing to SR/IEN/IOLH/FILxx
115 * registers, b is the register bits (b * 8) and f is the pin
116 * configuration capabilities supported.
117 */
118#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
121 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
122
123#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \
124 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
125 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
126
127#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
128#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
129#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
133
134#define P(off) (0x0000 + (off))
135#define PM(off) (0x0100 + (off) * 2)
136#define PMC(off) (0x0200 + (off))
137#define PFC(off) (0x0400 + (off) * 4)
138#define PIN(off) (0x0800 + (off))
139#define IOLH(off) (0x1000 + (off) * 8)
140#define SR(off) (0x1400 + (off) * 8)
141#define IEN(off) (0x1800 + (off) * 8)
142#define PUPD(off) (0x1C00 + (off) * 8)
143#define ISEL(off) (0x2C00 + (off) * 8)
144#define NOD(off) (0x3000 + (off) * 8)
145#define SMT(off) (0x3400 + (off) * 8)
146#define SD_CH(off, ch) ((off) + (ch) * 4)
147#define ETH_POC(off, ch) ((off) + (ch) * 4)
148#define QSPI (0x3008)
149#define ETH_MODE (0x3018)
150#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
151
152#define PVDD_2500 2 /* I/O domain voltage 2.5V */
153#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
154#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
155
156#define PWPR_B0WI BIT(7) /* Bit Write Disable */
157#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
158#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
159#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
160
161#define PM_MASK 0x03
162#define PFC_MASK 0x0f
163#define IEN_MASK 0x01
164#define IOLH_MASK 0x03
165#define SR_MASK 0x01
166#define PUPD_MASK 0x03
167#define NOD_MASK 0x01
168#define SMT_MASK 0x01
169
170#define PM_INPUT 0x1
171#define PM_OUTPUT 0x2
172
173#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
174#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
175
176#define RZG2L_TINT_MAX_INTERRUPT 32
177#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
178
179/* Custom pinconf parameters */
180#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
181
182static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
183 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
184};
185
186#ifdef CONFIG_DEBUG_FS
187static const struct pin_config_item renesas_rzv2h_conf_items[] = {
188 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
189};
190#endif
191
192/* Read/write 8 bits register */
193#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
194 do { \
195 if (_read) \
196 _val = readb(_addr); \
197 else \
198 writeb(_val, _addr); \
199 } while (0)
200
201/* Read/write 16 bits register */
202#define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \
203 do { \
204 if (_read) \
205 _val = readw(_addr); \
206 else \
207 writew(_val, _addr); \
208 } while (0)
209
210/* Read/write 32 bits register */
211#define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \
212 do { \
213 if (_read) \
214 _val = readl(_addr); \
215 else \
216 writel(_val, _addr); \
217 } while (0)
218
219/**
220 * struct rzg2l_register_offsets - specific register offsets
221 * @pwpr: PWPR register offset
222 * @sd_ch: SD_CH register offset
223 * @eth_poc: ETH_POC register offset
224 */
225struct rzg2l_register_offsets {
226 u16 pwpr;
227 u16 sd_ch;
228 u16 eth_poc;
229};
230
231/**
232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
233 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
234 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
235 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
236 * @RZG2L_IOLH_IDX_MAX: maximum index
237 */
238enum rzg2l_iolh_index {
239 RZG2L_IOLH_IDX_1V8 = 0,
240 RZG2L_IOLH_IDX_2V5 = 4,
241 RZG2L_IOLH_IDX_3V3 = 8,
242 RZG2L_IOLH_IDX_MAX = 12,
243};
244
245/* Maximum number of driver strength entries per power source. */
246#define RZG2L_IOLH_MAX_DS_ENTRIES (4)
247
248/**
249 * struct rzg2l_hwcfg - hardware configuration data structure
250 * @regs: hardware specific register offsets
251 * @iolh_groupa_ua: IOLH group A uA specific values
252 * @iolh_groupb_ua: IOLH group B uA specific values
253 * @iolh_groupc_ua: IOLH group C uA specific values
254 * @iolh_groupb_oi: IOLH group B output impedance specific values
255 * @tint_start_index: the start index for the TINT interrupts
256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
257 * @func_base: base number for port function (see register PFC)
258 * @oen_max_pin: the maximum pin number supporting output enable
259 * @oen_max_port: the maximum port number supporting output enable
260 */
261struct rzg2l_hwcfg {
262 const struct rzg2l_register_offsets regs;
263 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
264 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
265 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
266 u16 iolh_groupb_oi[4];
267 u16 tint_start_index;
268 bool drive_strength_ua;
269 u8 func_base;
270 u8 oen_max_pin;
271 u8 oen_max_port;
272};
273
274struct rzg2l_dedicated_configs {
275 const char *name;
276 u64 config;
277};
278
279struct rzg2l_pinctrl;
280
281struct rzg2l_pinctrl_data {
282 const char * const *port_pins;
283 const u64 *port_pin_configs;
284 unsigned int n_ports;
285 const struct rzg2l_dedicated_configs *dedicated_pins;
286 unsigned int n_port_pins;
287 unsigned int n_dedicated_pins;
288 const struct rzg2l_hwcfg *hwcfg;
289 const u64 *variable_pin_cfg;
290 unsigned int n_variable_pin_cfg;
291 unsigned int num_custom_params;
292 const struct pinconf_generic_params *custom_params;
293#ifdef CONFIG_DEBUG_FS
294 const struct pin_config_item *custom_conf_items;
295#endif
296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
298 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
299 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
300 int (*hw_to_bias_param)(unsigned int val);
301 int (*bias_param_to_hw)(enum pin_config_param param);
302};
303
304/**
305 * struct rzg2l_pinctrl_pin_settings - pin data
306 * @power_source: power source
307 * @drive_strength_ua: drive strength (in micro amps)
308 */
309struct rzg2l_pinctrl_pin_settings {
310 u16 power_source;
311 u16 drive_strength_ua;
312};
313
314/**
315 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
316 * @p: P registers cache
317 * @pm: PM registers cache
318 * @pmc: PMC registers cache
319 * @pfc: PFC registers cache
320 * @iolh: IOLH registers cache
321 * @pupd: PUPD registers cache
322 * @ien: IEN registers cache
323 * @sd_ch: SD_CH registers cache
324 * @eth_poc: ET_POC registers cache
325 * @eth_mode: ETH_MODE register cache
326 * @qspi: QSPI registers cache
327 */
328struct rzg2l_pinctrl_reg_cache {
329 u8 *p;
330 u16 *pm;
331 u8 *pmc;
332 u32 *pfc;
333 u32 *iolh[2];
334 u32 *ien[2];
335 u32 *pupd[2];
336 u8 sd_ch[2];
337 u8 eth_poc[2];
338 u8 eth_mode;
339 u8 qspi;
340};
341
342struct rzg2l_pinctrl {
343 struct pinctrl_dev *pctl;
344 struct pinctrl_desc desc;
345 struct pinctrl_pin_desc *pins;
346
347 const struct rzg2l_pinctrl_data *data;
348 void __iomem *base;
349 struct device *dev;
350
351 struct clk *clk;
352
353 struct gpio_chip gpio_chip;
354 struct pinctrl_gpio_range gpio_range;
355 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
356 spinlock_t bitmap_lock; /* protect tint_slot bitmap */
357 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
358
359 spinlock_t lock; /* lock read/write registers */
360 struct mutex mutex; /* serialize adding groups and functions */
361
362 struct rzg2l_pinctrl_pin_settings *settings;
363 struct rzg2l_pinctrl_reg_cache *cache;
364 struct rzg2l_pinctrl_reg_cache *dedicated_cache;
365 atomic_t wakeup_path;
366};
367
368static const u16 available_ps[] = { 1800, 2500, 3300 };
369
370static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
371 u64 pincfg,
372 unsigned int port,
373 u8 pin)
374{
375 unsigned int i;
376
377 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
378 u64 cfg = pctrl->data->variable_pin_cfg[i];
379
380 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
381 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
382 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
383 }
384
385 return 0;
386}
387
388static const u64 r9a09g047_variable_pin_cfg[] = {
389 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
390 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
391 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
397 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
398 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
399 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
400 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
401 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
408 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
409 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
410 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
411 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
412 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
416 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
417 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
418 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
419 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
420 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
422 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
423 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
424};
425
426static const u64 r9a09g057_variable_pin_cfg[] = {
427 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
428 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
429 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
430 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
431 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
432 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
433};
434
435#ifdef CONFIG_RISCV
436static const u64 r9a07g043f_variable_pin_cfg[] = {
437 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
438 PIN_CFG_NF |
439 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
440 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
441 PIN_CFG_NF |
442 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
443 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
444 PIN_CFG_NF |
445 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
446 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
447 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
448 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
449 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
450 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
451 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
452 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
453 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
454 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
455 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
456 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
457 PIN_CFG_NOGPIO_INT),
458 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
459 PIN_CFG_NOGPIO_INT),
460 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
461 PIN_CFG_NOGPIO_INT),
462 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
463 PIN_CFG_NOGPIO_INT),
464 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
465 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
466 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
467 PIN_CFG_NOGPIO_INT),
468 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
469 PIN_CFG_NOGPIO_INT),
470 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
471 PIN_CFG_NOGPIO_INT),
472 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
473 PIN_CFG_NOGPIO_INT),
474 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
475 PIN_CFG_NF |
476 PIN_CFG_NOGPIO_INT),
477};
478#endif
479
480static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
481{
482 writeb(val, addr: pctrl->base + offset);
483}
484
485static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
486{
487 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
488 u8 pwpr;
489
490 pwpr = readb(addr: pctrl->base + regs->pwpr);
491 writeb(val: pwpr | PWPR_REGWE_A, addr: pctrl->base + regs->pwpr);
492 writeb(val, addr: pctrl->base + offset);
493 writeb(val: pwpr & ~PWPR_REGWE_A, addr: pctrl->base + regs->pwpr);
494}
495
496static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
497 u8 pin, u8 off, u8 func)
498{
499 unsigned long flags;
500 u32 reg;
501
502 spin_lock_irqsave(&pctrl->lock, flags);
503
504 /* Set pin to 'Non-use (Hi-Z input protection)' */
505 reg = readw(addr: pctrl->base + PM(off));
506 reg &= ~(PM_MASK << (pin * 2));
507 writew(val: reg, addr: pctrl->base + PM(off));
508
509 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
510
511 /* Temporarily switch to GPIO mode with PMC register */
512 reg = readb(addr: pctrl->base + PMC(off));
513 writeb(val: reg & ~BIT(pin), addr: pctrl->base + PMC(off));
514
515 /* Select Pin function mode with PFC register */
516 reg = readl(addr: pctrl->base + PFC(off));
517 reg &= ~(PFC_MASK << (pin * 4));
518 writel(val: reg | (func << (pin * 4)), addr: pctrl->base + PFC(off));
519
520 /* Switch to Peripheral pin function with PMC register */
521 reg = readb(addr: pctrl->base + PMC(off));
522 writeb(val: reg | BIT(pin), addr: pctrl->base + PMC(off));
523
524 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
525
526 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
527};
528
529static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
530 unsigned int func_selector,
531 unsigned int group_selector)
532{
533 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
534 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
535 struct function_desc *func;
536 unsigned int i, *psel_val;
537 struct group_desc *group;
538 const unsigned int *pins;
539
540 func = pinmux_generic_get_function(pctldev, selector: func_selector);
541 if (!func)
542 return -EINVAL;
543 group = pinctrl_generic_get_group(pctldev, group_selector);
544 if (!group)
545 return -EINVAL;
546
547 psel_val = func->data;
548 pins = group->grp.pins;
549
550 for (i = 0; i < group->grp.npins; i++) {
551 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
552 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
553 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
554
555 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
556 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
557
558 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func: psel_val[i] - hwcfg->func_base);
559 }
560
561 return 0;
562};
563
564static int rzg2l_map_add_config(struct pinctrl_map *map,
565 const char *group_or_pin,
566 enum pinctrl_map_type type,
567 unsigned long *configs,
568 unsigned int num_configs)
569{
570 unsigned long *cfgs;
571
572 cfgs = kmemdup_array(src: configs, count: num_configs, element_size: sizeof(*cfgs), GFP_KERNEL);
573 if (!cfgs)
574 return -ENOMEM;
575
576 map->type = type;
577 map->data.configs.group_or_pin = group_or_pin;
578 map->data.configs.configs = cfgs;
579 map->data.configs.num_configs = num_configs;
580
581 return 0;
582}
583
584static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
585 struct device_node *np,
586 struct device_node *parent,
587 struct pinctrl_map **map,
588 unsigned int *num_maps,
589 unsigned int *index)
590{
591 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
592 struct pinctrl_map *maps = *map;
593 unsigned int nmaps = *num_maps;
594 unsigned long *configs = NULL;
595 unsigned int *pins, *psel_val;
596 unsigned int num_pinmux = 0;
597 unsigned int idx = *index;
598 unsigned int num_pins, i;
599 unsigned int num_configs;
600 struct property *pinmux;
601 struct property *prop;
602 int ret, gsel, fsel;
603 const char **pin_fn;
604 const char *name;
605 const char *pin;
606
607 pinmux = of_find_property(np, name: "pinmux", NULL);
608 if (pinmux)
609 num_pinmux = pinmux->length / sizeof(u32);
610
611 ret = of_property_count_strings(np, propname: "pins");
612 if (ret == -EINVAL) {
613 num_pins = 0;
614 } else if (ret < 0) {
615 dev_err(pctrl->dev, "Invalid pins list in DT\n");
616 return ret;
617 } else {
618 num_pins = ret;
619 }
620
621 if (!num_pinmux && !num_pins)
622 return 0;
623
624 if (num_pinmux && num_pins) {
625 dev_err(pctrl->dev,
626 "DT node must contain either a pinmux or pins and not both\n");
627 return -EINVAL;
628 }
629
630 ret = pinconf_generic_parse_dt_config(np, pctldev, configs: &configs, nconfigs: &num_configs);
631 if (ret < 0)
632 return ret;
633
634 if (num_pins && !num_configs) {
635 dev_err(pctrl->dev, "DT node must contain a config\n");
636 ret = -ENODEV;
637 goto done;
638 }
639
640 if (num_pinmux) {
641 nmaps += 1;
642 if (num_configs)
643 nmaps += 1;
644 }
645
646 if (num_pins)
647 nmaps += num_pins;
648
649 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
650 if (!maps) {
651 ret = -ENOMEM;
652 goto done;
653 }
654
655 *map = maps;
656 *num_maps = nmaps;
657 if (num_pins) {
658 of_property_for_each_string(np, "pins", prop, pin) {
659 ret = rzg2l_map_add_config(map: &maps[idx], group_or_pin: pin,
660 type: PIN_MAP_TYPE_CONFIGS_PIN,
661 configs, num_configs);
662 if (ret < 0)
663 goto done;
664
665 idx++;
666 }
667 ret = 0;
668 goto done;
669 }
670
671 pins = devm_kcalloc(dev: pctrl->dev, n: num_pinmux, size: sizeof(*pins), GFP_KERNEL);
672 psel_val = devm_kcalloc(dev: pctrl->dev, n: num_pinmux, size: sizeof(*psel_val),
673 GFP_KERNEL);
674 pin_fn = devm_kzalloc(dev: pctrl->dev, size: sizeof(*pin_fn), GFP_KERNEL);
675 if (!pins || !psel_val || !pin_fn) {
676 ret = -ENOMEM;
677 goto done;
678 }
679
680 /* Collect pin locations and mux settings from DT properties */
681 for (i = 0; i < num_pinmux; ++i) {
682 u32 value;
683
684 ret = of_property_read_u32_index(np, propname: "pinmux", index: i, out_value: &value);
685 if (ret)
686 goto done;
687 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
688 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
689 }
690
691 if (parent) {
692 name = devm_kasprintf(dev: pctrl->dev, GFP_KERNEL, fmt: "%pOFn.%pOFn",
693 parent, np);
694 if (!name) {
695 ret = -ENOMEM;
696 goto done;
697 }
698 } else {
699 name = np->name;
700 }
701
702 if (num_configs) {
703 ret = rzg2l_map_add_config(map: &maps[idx], group_or_pin: name,
704 type: PIN_MAP_TYPE_CONFIGS_GROUP,
705 configs, num_configs);
706 if (ret < 0)
707 goto done;
708
709 idx++;
710 }
711
712 mutex_lock(&pctrl->mutex);
713
714 /* Register a single pin group listing all the pins we read from DT */
715 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pins: num_pinmux, NULL);
716 if (gsel < 0) {
717 ret = gsel;
718 goto unlock;
719 }
720
721 /*
722 * Register a single group function where the 'data' is an array PSEL
723 * register values read from DT.
724 */
725 pin_fn[0] = name;
726 fsel = pinmux_generic_add_function(pctldev, name, groups: pin_fn, ngroups: 1, data: psel_val);
727 if (fsel < 0) {
728 ret = fsel;
729 goto remove_group;
730 }
731
732 mutex_unlock(lock: &pctrl->mutex);
733
734 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
735 maps[idx].data.mux.group = name;
736 maps[idx].data.mux.function = name;
737 idx++;
738
739 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
740 ret = 0;
741 goto done;
742
743remove_group:
744 pinctrl_generic_remove_group(pctldev, group_selector: gsel);
745unlock:
746 mutex_unlock(lock: &pctrl->mutex);
747done:
748 *index = idx;
749 kfree(objp: configs);
750 return ret;
751}
752
753static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
754 struct pinctrl_map *map,
755 unsigned int num_maps)
756{
757 unsigned int i;
758
759 if (!map)
760 return;
761
762 for (i = 0; i < num_maps; ++i) {
763 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
764 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
765 kfree(objp: map[i].data.configs.configs);
766 }
767 kfree(objp: map);
768}
769
770static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
771 struct device_node *np,
772 struct pinctrl_map **map,
773 unsigned int *num_maps)
774{
775 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
776 unsigned int index;
777 int ret;
778
779 *map = NULL;
780 *num_maps = 0;
781 index = 0;
782
783 for_each_child_of_node_scoped(np, child) {
784 ret = rzg2l_dt_subnode_to_map(pctldev, np: child, parent: np, map,
785 num_maps, index: &index);
786 if (ret < 0)
787 goto done;
788 }
789
790 if (*num_maps == 0) {
791 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
792 num_maps, index: &index);
793 if (ret < 0)
794 goto done;
795 }
796
797 if (*num_maps)
798 return 0;
799
800 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
801 ret = -EINVAL;
802
803done:
804 rzg2l_dt_free_map(pctldev, map: *map, num_maps: *num_maps);
805
806 return ret;
807}
808
809static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
810 u64 cfg, u32 port, u8 bit)
811{
812 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
813 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
814 u64 data;
815
816 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
817 return -EINVAL;
818
819 data = pctrl->data->port_pin_configs[port];
820 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
821 return -EINVAL;
822
823 return 0;
824}
825
826static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
827 u8 bit, u32 mask)
828{
829 void __iomem *addr = pctrl->base + offset;
830
831 /* handle _L/_H for 32-bit register read/write */
832 if (bit >= 4) {
833 bit -= 4;
834 addr += 4;
835 }
836
837 return (readl(addr) >> (bit * 8)) & mask;
838}
839
840static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
841 u8 bit, u32 mask, u32 val)
842{
843 void __iomem *addr = pctrl->base + offset;
844 unsigned long flags;
845 u32 reg;
846
847 /* handle _L/_H for 32-bit register read/write */
848 if (bit >= 4) {
849 bit -= 4;
850 addr += 4;
851 }
852
853 spin_lock_irqsave(&pctrl->lock, flags);
854 reg = readl(addr) & ~(mask << (bit * 8));
855 writel(val: reg | (val << (bit * 8)), addr);
856 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
857}
858
859static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
860{
861 if (caps & PIN_CFG_IO_VMC_SD0)
862 return SD_CH(regs->sd_ch, 0);
863 if (caps & PIN_CFG_IO_VMC_SD1)
864 return SD_CH(regs->sd_ch, 1);
865 if (caps & PIN_CFG_IO_VMC_ETH0)
866 return ETH_POC(regs->eth_poc, 0);
867 if (caps & PIN_CFG_IO_VMC_ETH1)
868 return ETH_POC(regs->eth_poc, 1);
869 if (caps & PIN_CFG_IO_VMC_QSPI)
870 return QSPI;
871
872 return -EINVAL;
873}
874
875static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
876{
877 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
878 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
879 int pwr_reg;
880 u8 val;
881
882 if (caps & PIN_CFG_SOFT_PS)
883 return pctrl->settings[pin].power_source;
884
885 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
886 if (pwr_reg < 0)
887 return pwr_reg;
888
889 val = readb(addr: pctrl->base + pwr_reg);
890 switch (val) {
891 case PVDD_1800:
892 return 1800;
893 case PVDD_2500:
894 return 2500;
895 case PVDD_3300:
896 return 3300;
897 default:
898 /* Should not happen. */
899 return -EINVAL;
900 }
901}
902
903static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
904{
905 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
906 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
907 int pwr_reg;
908 u8 val;
909
910 if (caps & PIN_CFG_SOFT_PS) {
911 pctrl->settings[pin].power_source = ps;
912 return 0;
913 }
914
915 switch (ps) {
916 case 1800:
917 val = PVDD_1800;
918 break;
919 case 2500:
920 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
921 return -EINVAL;
922 val = PVDD_2500;
923 break;
924 case 3300:
925 val = PVDD_3300;
926 break;
927 default:
928 return -EINVAL;
929 }
930
931 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
932 if (pwr_reg < 0)
933 return pwr_reg;
934
935 writeb(val, addr: pctrl->base + pwr_reg);
936 pctrl->settings[pin].power_source = ps;
937
938 return 0;
939}
940
941static bool rzg2l_ps_is_supported(u16 ps)
942{
943 unsigned int i;
944
945 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
946 if (available_ps[i] == ps)
947 return true;
948 }
949
950 return false;
951}
952
953static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
954{
955 unsigned int i;
956
957 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
958 if (available_ps[i] == ps)
959 break;
960 }
961
962 /*
963 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
964 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
965 */
966 return i * RZG2L_IOLH_MAX_DS_ENTRIES;
967}
968
969static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
970{
971 if (caps & PIN_CFG_IOLH_A)
972 return hwcfg->iolh_groupa_ua[val];
973
974 if (caps & PIN_CFG_IOLH_B)
975 return hwcfg->iolh_groupb_ua[val];
976
977 if (caps & PIN_CFG_IOLH_C)
978 return hwcfg->iolh_groupc_ua[val];
979
980 /* Should not happen. */
981 return 0;
982}
983
984static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
985 enum rzg2l_iolh_index ps_index, u16 ua)
986{
987 const u16 *array = NULL;
988 unsigned int i;
989
990 if (caps & PIN_CFG_IOLH_A)
991 array = &hwcfg->iolh_groupa_ua[ps_index];
992
993 if (caps & PIN_CFG_IOLH_B)
994 array = &hwcfg->iolh_groupb_ua[ps_index];
995
996 if (caps & PIN_CFG_IOLH_C)
997 array = &hwcfg->iolh_groupc_ua[ps_index];
998
999 if (!array)
1000 return -EINVAL;
1001
1002 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1003 if (array[i] == ua)
1004 return i;
1005 }
1006
1007 return -EINVAL;
1008}
1009
1010static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
1011 enum rzg2l_iolh_index iolh_idx,
1012 u16 ds)
1013{
1014 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1015 const u16 *array = NULL;
1016 unsigned int i;
1017
1018 if (caps & PIN_CFG_IOLH_A)
1019 array = hwcfg->iolh_groupa_ua;
1020
1021 if (caps & PIN_CFG_IOLH_B)
1022 array = hwcfg->iolh_groupb_ua;
1023
1024 if (caps & PIN_CFG_IOLH_C)
1025 array = hwcfg->iolh_groupc_ua;
1026
1027 /* Should not happen. */
1028 if (!array)
1029 return false;
1030
1031 if (!array[iolh_idx])
1032 return false;
1033
1034 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1035 if (array[iolh_idx + i] == ds)
1036 return true;
1037 }
1038
1039 return false;
1040}
1041
1042static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1043{
1044 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1045 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1046 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1047
1048 if (pin > pctrl->data->hwcfg->oen_max_pin)
1049 return -EINVAL;
1050
1051 /*
1052 * We can determine which Ethernet interface we're dealing with from
1053 * the caps.
1054 */
1055 if (caps & PIN_CFG_IO_VMC_ETH0)
1056 return 0;
1057 if (caps & PIN_CFG_IO_VMC_ETH1)
1058 return 1;
1059
1060 return -EINVAL;
1061}
1062
1063static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1064{
1065 int bit;
1066
1067 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1068 if (bit < 0)
1069 return 0;
1070
1071 return !(readb(addr: pctrl->base + ETH_MODE) & BIT(bit));
1072}
1073
1074static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1075{
1076 unsigned long flags;
1077 int bit;
1078 u8 val;
1079
1080 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1081 if (bit < 0)
1082 return bit;
1083
1084 spin_lock_irqsave(&pctrl->lock, flags);
1085 val = readb(addr: pctrl->base + ETH_MODE);
1086 if (oen)
1087 val &= ~BIT(bit);
1088 else
1089 val |= BIT(bit);
1090 writeb(val, addr: pctrl->base + ETH_MODE);
1091 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1092
1093 return 0;
1094}
1095
1096static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1097{
1098 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1099 u8 port, pin, bit;
1100
1101 if (*pin_data & RZG2L_SINGLE_PIN)
1102 return -EINVAL;
1103
1104 port = RZG2L_PIN_ID_TO_PORT(_pin);
1105 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1106 if (pin > pctrl->data->hwcfg->oen_max_pin)
1107 return -EINVAL;
1108
1109 bit = pin * 2;
1110 if (port == pctrl->data->hwcfg->oen_max_port)
1111 bit += 1;
1112
1113 return bit;
1114}
1115
1116static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1117{
1118 int bit;
1119
1120 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1121 if (bit < 0)
1122 return bit;
1123
1124 return !(readb(addr: pctrl->base + ETH_MODE) & BIT(bit));
1125}
1126
1127static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1128{
1129 unsigned long flags;
1130 int bit;
1131 u8 val;
1132
1133 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1134 if (bit < 0)
1135 return bit;
1136
1137 spin_lock_irqsave(&pctrl->lock, flags);
1138 val = readb(addr: pctrl->base + ETH_MODE);
1139 if (oen)
1140 val &= ~BIT(bit);
1141 else
1142 val |= BIT(bit);
1143 writeb(val, addr: pctrl->base + ETH_MODE);
1144 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1145
1146 return 0;
1147}
1148
1149static int rzg2l_hw_to_bias_param(unsigned int bias)
1150{
1151 switch (bias) {
1152 case 0:
1153 return PIN_CONFIG_BIAS_DISABLE;
1154 case 1:
1155 return PIN_CONFIG_BIAS_PULL_UP;
1156 case 2:
1157 return PIN_CONFIG_BIAS_PULL_DOWN;
1158 default:
1159 break;
1160 }
1161
1162 return -EINVAL;
1163}
1164
1165static int rzg2l_bias_param_to_hw(enum pin_config_param param)
1166{
1167 switch (param) {
1168 case PIN_CONFIG_BIAS_DISABLE:
1169 return 0;
1170 case PIN_CONFIG_BIAS_PULL_UP:
1171 return 1;
1172 case PIN_CONFIG_BIAS_PULL_DOWN:
1173 return 2;
1174 default:
1175 break;
1176 }
1177
1178 return -EINVAL;
1179}
1180
1181static int rzv2h_hw_to_bias_param(unsigned int bias)
1182{
1183 switch (bias) {
1184 case 0:
1185 case 1:
1186 return PIN_CONFIG_BIAS_DISABLE;
1187 case 2:
1188 return PIN_CONFIG_BIAS_PULL_DOWN;
1189 case 3:
1190 return PIN_CONFIG_BIAS_PULL_UP;
1191 default:
1192 break;
1193 }
1194
1195 return -EINVAL;
1196}
1197
1198static int rzv2h_bias_param_to_hw(enum pin_config_param param)
1199{
1200 switch (param) {
1201 case PIN_CONFIG_BIAS_DISABLE:
1202 return 0;
1203 case PIN_CONFIG_BIAS_PULL_DOWN:
1204 return 2;
1205 case PIN_CONFIG_BIAS_PULL_UP:
1206 return 3;
1207 default:
1208 break;
1209 }
1210
1211 return -EINVAL;
1212}
1213
1214static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1215{
1216 static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
1217 "XSPI0_RESET0N", "XSPI0_CS0N",
1218 "XSPI0_CKN", "XSPI0_CKP" };
1219 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
1220 unsigned int i;
1221
1222 for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
1223 if (!strcmp(pin_desc->name, pin_names[i]))
1224 return i;
1225 }
1226
1227 /* Should not happen. */
1228 return 0;
1229}
1230
1231static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1232{
1233 u8 bit;
1234
1235 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1236
1237 return !(readb(addr: pctrl->base + PFC_OEN) & BIT(bit));
1238}
1239
1240static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1241{
1242 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1243 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1244 unsigned long flags;
1245 u8 val, bit;
1246 u8 pwpr;
1247
1248 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1249 spin_lock_irqsave(&pctrl->lock, flags);
1250 val = readb(addr: pctrl->base + PFC_OEN);
1251 if (oen)
1252 val &= ~BIT(bit);
1253 else
1254 val |= BIT(bit);
1255
1256 pwpr = readb(addr: pctrl->base + regs->pwpr);
1257 writeb(val: pwpr | PWPR_REGWE_B, addr: pctrl->base + regs->pwpr);
1258 writeb(val, addr: pctrl->base + PFC_OEN);
1259 writeb(val: pwpr & ~PWPR_REGWE_B, addr: pctrl->base + regs->pwpr);
1260 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1261
1262 return 0;
1263}
1264
1265static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
1266 unsigned int _pin,
1267 unsigned long *config)
1268{
1269 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1270 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1271 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1272 u32 param = pinconf_to_config_param(config: *config);
1273 u64 *pin_data = pin->drv_data;
1274 unsigned int arg = 0;
1275 u32 off;
1276 u32 cfg;
1277 int ret;
1278 u8 bit;
1279
1280 if (!pin_data)
1281 return -EINVAL;
1282
1283 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1284 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1285 if (*pin_data & RZG2L_SINGLE_PIN) {
1286 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1287 } else {
1288 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1289
1290 if (rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1291 return -EINVAL;
1292 }
1293
1294 switch (param) {
1295 case PIN_CONFIG_INPUT_ENABLE:
1296 if (!(cfg & PIN_CFG_IEN))
1297 return -EINVAL;
1298 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
1299 if (!arg)
1300 return -EINVAL;
1301 break;
1302
1303 case PIN_CONFIG_OUTPUT_ENABLE:
1304 if (!(cfg & PIN_CFG_OEN))
1305 return -EINVAL;
1306 if (!pctrl->data->oen_read)
1307 return -EOPNOTSUPP;
1308 arg = pctrl->data->oen_read(pctrl, _pin);
1309 if (!arg)
1310 return -EINVAL;
1311 break;
1312
1313 case PIN_CONFIG_POWER_SOURCE:
1314 ret = rzg2l_get_power_source(pctrl, pin: _pin, caps: cfg);
1315 if (ret < 0)
1316 return ret;
1317 arg = ret;
1318 break;
1319
1320 case PIN_CONFIG_SLEW_RATE:
1321 if (!(cfg & PIN_CFG_SR))
1322 return -EINVAL;
1323
1324 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
1325 break;
1326
1327 case PIN_CONFIG_BIAS_DISABLE:
1328 case PIN_CONFIG_BIAS_PULL_UP:
1329 case PIN_CONFIG_BIAS_PULL_DOWN:
1330 if (!(cfg & PIN_CFG_PUPD))
1331 return -EINVAL;
1332
1333 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
1334 ret = pctrl->data->hw_to_bias_param(arg);
1335 if (ret < 0)
1336 return ret;
1337
1338 if (ret != param)
1339 return -EINVAL;
1340 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
1341 arg = 1;
1342 break;
1343
1344 case PIN_CONFIG_DRIVE_STRENGTH: {
1345 unsigned int index;
1346
1347 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1348 return -EINVAL;
1349
1350 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1351 /*
1352 * Drive strenght mA is supported only by group A and only
1353 * for 3V3 port source.
1354 */
1355 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
1356 break;
1357 }
1358
1359 case PIN_CONFIG_DRIVE_STRENGTH_UA: {
1360 enum rzg2l_iolh_index iolh_idx;
1361 u8 val;
1362
1363 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1364 !hwcfg->drive_strength_ua)
1365 return -EINVAL;
1366
1367 ret = rzg2l_get_power_source(pctrl, pin: _pin, caps: cfg);
1368 if (ret < 0)
1369 return ret;
1370 iolh_idx = rzg2l_ps_to_iolh_idx(ps: ret);
1371 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1372 arg = rzg2l_iolh_val_to_ua(hwcfg, caps: cfg, val: iolh_idx + val);
1373 break;
1374 }
1375
1376 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
1377 unsigned int index;
1378
1379 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1380 return -EINVAL;
1381
1382 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1383 arg = hwcfg->iolh_groupb_oi[index];
1384 break;
1385 }
1386
1387 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1388 case PIN_CONFIG_DRIVE_PUSH_PULL:
1389 if (!(cfg & PIN_CFG_NOD))
1390 return -EINVAL;
1391
1392 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);
1393 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)
1394 return -EINVAL;
1395 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
1396 return -EINVAL;
1397 break;
1398
1399 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1400 if (!(cfg & PIN_CFG_SMT))
1401 return -EINVAL;
1402
1403 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK);
1404 if (!arg)
1405 return -EINVAL;
1406 break;
1407
1408 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1409 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1410 return -EINVAL;
1411
1412 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1413 break;
1414
1415 default:
1416 return -ENOTSUPP;
1417 }
1418
1419 *config = pinconf_to_config_packed(param, argument: arg);
1420
1421 return 0;
1422};
1423
1424static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
1425 unsigned int _pin,
1426 unsigned long *_configs,
1427 unsigned int num_configs)
1428{
1429 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1430 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1431 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1432 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
1433 u64 *pin_data = pin->drv_data;
1434 unsigned int i, arg, index;
1435 u32 off, param;
1436 u32 cfg;
1437 int ret;
1438 u8 bit;
1439
1440 if (!pin_data)
1441 return -EINVAL;
1442
1443 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1444 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1445 if (*pin_data & RZG2L_SINGLE_PIN) {
1446 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1447 } else {
1448 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1449
1450 if (rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1451 return -EINVAL;
1452 }
1453
1454 for (i = 0; i < num_configs; i++) {
1455 param = pinconf_to_config_param(config: _configs[i]);
1456 arg = pinconf_to_config_argument(config: _configs[i]);
1457 switch (param) {
1458 case PIN_CONFIG_INPUT_ENABLE:
1459
1460 if (!(cfg & PIN_CFG_IEN))
1461 return -EINVAL;
1462
1463 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, val: !!arg);
1464 break;
1465
1466 case PIN_CONFIG_OUTPUT_ENABLE:
1467 if (!(cfg & PIN_CFG_OEN))
1468 return -EINVAL;
1469 if (!pctrl->data->oen_write)
1470 return -EOPNOTSUPP;
1471 ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1472 if (ret)
1473 return ret;
1474 break;
1475
1476 case PIN_CONFIG_POWER_SOURCE:
1477 settings.power_source = arg;
1478 break;
1479
1480 case PIN_CONFIG_SLEW_RATE:
1481 if (!(cfg & PIN_CFG_SR) || arg > 1)
1482 return -EINVAL;
1483
1484 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, val: arg);
1485 break;
1486
1487 case PIN_CONFIG_BIAS_DISABLE:
1488 case PIN_CONFIG_BIAS_PULL_UP:
1489 case PIN_CONFIG_BIAS_PULL_DOWN:
1490 if (!(cfg & PIN_CFG_PUPD))
1491 return -EINVAL;
1492
1493 ret = pctrl->data->bias_param_to_hw(param);
1494 if (ret < 0)
1495 return ret;
1496
1497 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, val: ret);
1498 break;
1499
1500 case PIN_CONFIG_DRIVE_STRENGTH:
1501 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1502 return -EINVAL;
1503
1504 for (index = RZG2L_IOLH_IDX_3V3;
1505 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
1506 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
1507 break;
1508 }
1509 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
1510 return -EINVAL;
1511
1512 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val: index);
1513 break;
1514
1515 case PIN_CONFIG_DRIVE_STRENGTH_UA:
1516 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1517 !hwcfg->drive_strength_ua)
1518 return -EINVAL;
1519
1520 settings.drive_strength_ua = arg;
1521 break;
1522
1523 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1524 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1525 return -EINVAL;
1526
1527 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
1528 if (arg == hwcfg->iolh_groupb_oi[index])
1529 break;
1530 }
1531 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
1532 return -EINVAL;
1533
1534 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val: index);
1535 break;
1536
1537 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1538 case PIN_CONFIG_DRIVE_PUSH_PULL:
1539 if (!(cfg & PIN_CFG_NOD))
1540 return -EINVAL;
1541
1542 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,
1543 val: param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
1544 break;
1545
1546 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1547 if (!(cfg & PIN_CFG_SMT))
1548 return -EINVAL;
1549
1550 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, val: arg);
1551 break;
1552
1553 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1554 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1555 return -EINVAL;
1556
1557 if (arg > 3)
1558 return -EINVAL;
1559 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val: arg);
1560 break;
1561
1562 default:
1563 return -EOPNOTSUPP;
1564 }
1565 }
1566
1567 /* Apply power source. */
1568 if (settings.power_source != pctrl->settings[_pin].power_source) {
1569 ret = rzg2l_ps_is_supported(ps: settings.power_source);
1570 if (!ret)
1571 return -EINVAL;
1572
1573 /* Apply power source. */
1574 ret = rzg2l_set_power_source(pctrl, pin: _pin, caps: cfg, ps: settings.power_source);
1575 if (ret)
1576 return ret;
1577 }
1578
1579 /* Apply drive strength. */
1580 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
1581 enum rzg2l_iolh_index iolh_idx;
1582 int val;
1583
1584 iolh_idx = rzg2l_ps_to_iolh_idx(ps: settings.power_source);
1585 ret = rzg2l_ds_is_supported(pctrl, caps: cfg, iolh_idx,
1586 ds: settings.drive_strength_ua);
1587 if (!ret)
1588 return -EINVAL;
1589
1590 /* Get register value for this PS/DS tuple. */
1591 val = rzg2l_iolh_ua_to_val(hwcfg, caps: cfg, ps_index: iolh_idx, ua: settings.drive_strength_ua);
1592 if (val < 0)
1593 return val;
1594
1595 /* Apply drive strength. */
1596 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
1597 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
1598 }
1599
1600 return 0;
1601}
1602
1603static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
1604 unsigned int group,
1605 unsigned long *configs,
1606 unsigned int num_configs)
1607{
1608 const unsigned int *pins;
1609 unsigned int i, npins;
1610 int ret;
1611
1612 ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
1613 if (ret)
1614 return ret;
1615
1616 for (i = 0; i < npins; i++) {
1617 ret = rzg2l_pinctrl_pinconf_set(pctldev, pin: pins[i], configs: configs,
1618 num_configs);
1619 if (ret)
1620 return ret;
1621 }
1622
1623 return 0;
1624};
1625
1626static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
1627 unsigned int group,
1628 unsigned long *config)
1629{
1630 const unsigned int *pins;
1631 unsigned int i, npins, prev_config = 0;
1632 int ret;
1633
1634 ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
1635 if (ret)
1636 return ret;
1637
1638 for (i = 0; i < npins; i++) {
1639 ret = rzg2l_pinctrl_pinconf_get(pctldev, pin: pins[i], config);
1640 if (ret)
1641 return ret;
1642
1643 /* Check config matching between to pin */
1644 if (i && prev_config != *config)
1645 return -EOPNOTSUPP;
1646
1647 prev_config = *config;
1648 }
1649
1650 return 0;
1651};
1652
1653static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
1654 .get_groups_count = pinctrl_generic_get_group_count,
1655 .get_group_name = pinctrl_generic_get_group_name,
1656 .get_group_pins = pinctrl_generic_get_group_pins,
1657 .dt_node_to_map = rzg2l_dt_node_to_map,
1658 .dt_free_map = rzg2l_dt_free_map,
1659};
1660
1661static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
1662 .get_functions_count = pinmux_generic_get_function_count,
1663 .get_function_name = pinmux_generic_get_function_name,
1664 .get_function_groups = pinmux_generic_get_function_groups,
1665 .set_mux = rzg2l_pinctrl_set_mux,
1666 .strict = true,
1667};
1668
1669static const struct pinconf_ops rzg2l_pinctrl_confops = {
1670 .is_generic = true,
1671 .pin_config_get = rzg2l_pinctrl_pinconf_get,
1672 .pin_config_set = rzg2l_pinctrl_pinconf_set,
1673 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
1674 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
1675 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1676};
1677
1678static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
1679{
1680 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1681 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1682 u64 *pin_data = pin_desc->drv_data;
1683 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1684 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1685 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1686 unsigned long flags;
1687 u8 reg8;
1688 int ret;
1689
1690 ret = rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, port, bit);
1691 if (ret)
1692 return ret;
1693
1694 ret = pinctrl_gpio_request(gc: chip, offset);
1695 if (ret)
1696 return ret;
1697
1698 spin_lock_irqsave(&pctrl->lock, flags);
1699
1700 /* Select GPIO mode in PMC Register */
1701 reg8 = readb(addr: pctrl->base + PMC(off));
1702 reg8 &= ~BIT(bit);
1703 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
1704
1705 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1706
1707 return 0;
1708}
1709
1710static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
1711 bool output)
1712{
1713 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1714 u64 *pin_data = pin_desc->drv_data;
1715 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1716 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1717 unsigned long flags;
1718 u16 reg16;
1719
1720 spin_lock_irqsave(&pctrl->lock, flags);
1721
1722 reg16 = readw(addr: pctrl->base + PM(off));
1723 reg16 &= ~(PM_MASK << (bit * 2));
1724
1725 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
1726 writew(val: reg16, addr: pctrl->base + PM(off));
1727
1728 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1729}
1730
1731static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1732{
1733 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1734 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1735 u64 *pin_data = pin_desc->drv_data;
1736 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1737 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1738
1739 if (!(readb(addr: pctrl->base + PMC(off)) & BIT(bit))) {
1740 u16 reg16;
1741
1742 reg16 = readw(addr: pctrl->base + PM(off));
1743 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1744 if (reg16 == PM_OUTPUT)
1745 return GPIO_LINE_DIRECTION_OUT;
1746 }
1747
1748 return GPIO_LINE_DIRECTION_IN;
1749}
1750
1751static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
1752 unsigned int offset)
1753{
1754 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1755
1756 rzg2l_gpio_set_direction(pctrl, offset, output: false);
1757
1758 return 0;
1759}
1760
1761static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1762 int value)
1763{
1764 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1765 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1766 u64 *pin_data = pin_desc->drv_data;
1767 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1768 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1769 unsigned long flags;
1770 u8 reg8;
1771
1772 spin_lock_irqsave(&pctrl->lock, flags);
1773
1774 reg8 = readb(addr: pctrl->base + P(off));
1775
1776 if (value)
1777 writeb(val: reg8 | BIT(bit), addr: pctrl->base + P(off));
1778 else
1779 writeb(val: reg8 & ~BIT(bit), addr: pctrl->base + P(off));
1780
1781 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1782}
1783
1784static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
1785 unsigned int offset, int value)
1786{
1787 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1788
1789 rzg2l_gpio_set(chip, offset, value);
1790 rzg2l_gpio_set_direction(pctrl, offset, output: true);
1791
1792 return 0;
1793}
1794
1795static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
1796{
1797 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1798 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1799 u64 *pin_data = pin_desc->drv_data;
1800 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1801 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1802 u16 reg16;
1803
1804 reg16 = readw(addr: pctrl->base + PM(off));
1805 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1806
1807 if (reg16 == PM_INPUT)
1808 return !!(readb(addr: pctrl->base + PIN(off)) & BIT(bit));
1809 else if (reg16 == PM_OUTPUT)
1810 return !!(readb(addr: pctrl->base + P(off)) & BIT(bit));
1811 else
1812 return -EINVAL;
1813}
1814
1815static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
1816{
1817 unsigned int virq;
1818
1819 pinctrl_gpio_free(gc: chip, offset);
1820
1821 virq = irq_find_mapping(domain: chip->irq.domain, hwirq: offset);
1822 if (virq)
1823 irq_dispose_mapping(virq);
1824
1825 /*
1826 * Set the GPIO as an input to ensure that the next GPIO request won't
1827 * drive the GPIO pin as an output.
1828 */
1829 rzg2l_gpio_direction_input(chip, offset);
1830}
1831
1832static const char * const rzg2l_gpio_names[] = {
1833 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
1834 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
1835 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
1836 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
1837 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
1838 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
1839 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
1840 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
1841 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
1842 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
1843 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
1844 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
1845 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
1846 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
1847 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
1848 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
1849 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
1850 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
1851 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
1852 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
1853 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
1854 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
1855 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
1856 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
1857 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
1858 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
1859 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
1860 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
1861 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
1862 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
1863 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
1864 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
1865 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
1866 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
1867 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
1868 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
1869 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
1870 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
1871 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
1872 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
1873 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
1874 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
1875 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
1876 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
1877 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
1878 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
1879 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
1880 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
1881 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
1882};
1883
1884static const u64 r9a07g044_gpio_configs[] = {
1885 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
1886 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
1887 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
1888 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
1889 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
1890 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
1891 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
1892 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
1893 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
1894 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
1895 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1896 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1897 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1898 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1899 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1900 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1901 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1902 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1903 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1904 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1905 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1906 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1907 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1908 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1909 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1910 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1911 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1912 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1913 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1914 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1915 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1916 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1917 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1918 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1919 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1920 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1921 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1922 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1923 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1924 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1925 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1926 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1927 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1928 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1929 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1930 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1931 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1932 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1933 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1934};
1935
1936static const u64 r9a07g043_gpio_configs[] = {
1937 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1938 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1939 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1940 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1941 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1942 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1943 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1944 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1945 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1946 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1947 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1948 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1949 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1950 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1951 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1952 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1953 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1954 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1955 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1956#ifdef CONFIG_RISCV
1957 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1958 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1959 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1960 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
1961 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1962 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
1963 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1964 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1965 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
1966 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
1967 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
1968 PIN_CFG_NOGPIO_INT), /* P25 */
1969 0x0, /* P26 */
1970 0x0, /* P27 */
1971 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */
1972#endif
1973};
1974
1975static const u64 r9a08g045_gpio_configs[] = {
1976 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1977 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1978 PIN_CFG_IO_VMC_ETH0)) |
1979 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */
1980 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1981 PIN_CFG_IO_VMC_ETH0)), /* P2 */
1982 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1983 PIN_CFG_IO_VMC_ETH0)), /* P3 */
1984 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1985 PIN_CFG_IO_VMC_ETH0)), /* P4 */
1986 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1987 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1988 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1989 PIN_CFG_IO_VMC_ETH1)) |
1990 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */
1991 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1992 PIN_CFG_IO_VMC_ETH1)), /* P8 */
1993 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1994 PIN_CFG_IO_VMC_ETH1)), /* P9 */
1995 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1996 PIN_CFG_IO_VMC_ETH1)), /* P10 */
1997 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
1998 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
1999 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
2000 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
2001 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
2002 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
2003 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
2004 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
2005};
2006
2007static const char * const rzg3e_gpio_names[] = {
2008 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2009 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2010 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2011 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2012 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2013 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2014 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2015 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2016 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2017 "", "", "", "", "", "", "", "",
2018 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2019 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2020 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
2021 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
2022 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
2023 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
2024 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
2025 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
2026 "", "", "", "", "", "", "", "",
2027 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
2028 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
2029 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
2030 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
2031 "", "", "", "", "", "", "", "",
2032 "", "", "", "", "", "", "", "",
2033 "", "", "", "", "", "", "", "",
2034 "", "", "", "", "", "", "", "",
2035 "", "", "", "", "", "", "", "",
2036 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2037};
2038
2039static const u64 r9a09g047_gpio_configs[] = {
2040 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2041 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
2042 PIN_CFG_ELC), /* P1 */
2043 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2044 PIN_CFG_NOD), /* P2 */
2045 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2046 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2047 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2048 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
2049 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
2050 PIN_CFG_ELC), /* P7 */
2051 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
2052 0x0,
2053 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2054 RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
2055 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
2056 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2057 RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
2058 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
2059 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2060 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2061 0x0,
2062 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2063 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
2064 RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
2065 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
2066 0x0,
2067 0x0,
2068 0x0,
2069 0x0,
2070 0x0,
2071 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
2072};
2073
2074static const char * const rzv2h_gpio_names[] = {
2075 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2076 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2077 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2078 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2079 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2080 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2081 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2082 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2083 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2084 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
2085 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2086 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2087};
2088
2089static const u64 r9a09g057_gpio_configs[] = {
2090 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2091 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
2092 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2093 PIN_CFG_NOD), /* P2 */
2094 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2095 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2096 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2097 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
2098 PIN_CFG_ELC), /* P6 */
2099 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
2100 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
2101 PIN_CFG_ELC), /* P8 */
2102 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
2103 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
2104 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */
2105};
2106
2107static const struct {
2108 struct rzg2l_dedicated_configs common[35];
2109 struct rzg2l_dedicated_configs rzg2l_pins[7];
2110} rzg2l_dedicated_pins = {
2111 .common = {
2112 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2113 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
2114 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2115 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
2116 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2117 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
2118 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
2119 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2120 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2121 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2122 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2123 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
2124 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2125 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
2126 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2127 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
2128 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2129 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
2130 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2131 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
2132 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2133 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
2134 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2135 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
2136 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2137 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
2138 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2139 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
2140 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2141 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
2142 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
2143 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
2144 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2145 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2146 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2147 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2148 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2149 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2150 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2151 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2152 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2153 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2154 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2155 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2156 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2157 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2158 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2159 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2160 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2161 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2162 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2163 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2164 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2165 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
2166 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2167 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
2168 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2169 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
2170 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
2171 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
2172 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
2173 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
2174 },
2175 .rzg2l_pins = {
2176 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2177 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
2178 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2179 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
2180 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2181 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
2182 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2183 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
2184 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2185 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
2186 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2187 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
2188 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2189 }
2190};
2191
2192static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
2193 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
2194 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
2195 PIN_CFG_SOFT_PS)) },
2196 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
2197 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
2198 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
2199 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
2200 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2201 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2202 PIN_CFG_IO_VMC_SD0)) },
2203 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2204 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2205 PIN_CFG_IO_VMC_SD0)) },
2206 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2207 PIN_CFG_IO_VMC_SD0)) },
2208 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2209 PIN_CFG_IO_VMC_SD0)) },
2210 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2211 PIN_CFG_IO_VMC_SD0)) },
2212 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2213 PIN_CFG_IO_VMC_SD0)) },
2214 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2215 PIN_CFG_IO_VMC_SD0)) },
2216 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2217 PIN_CFG_IO_VMC_SD0)) },
2218 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2219 PIN_CFG_IO_VMC_SD0)) },
2220 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
2221 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2222 PIN_CFG_IO_VMC_SD1)) },
2223 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2224 PIN_CFG_IO_VMC_SD1)) },
2225 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2226 PIN_CFG_IO_VMC_SD1)) },
2227 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2228 PIN_CFG_IO_VMC_SD1)) },
2229 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2230 PIN_CFG_IO_VMC_SD1)) },
2231};
2232
2233static const struct {
2234 struct rzg2l_dedicated_configs common[77];
2235 struct rzg2l_dedicated_configs pcie1[1];
2236} rzv2h_dedicated_pins = {
2237 .common = {
2238 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2239 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2240 PIN_CFG_IEN)) },
2241 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2242 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2243 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2244 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2245 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2246 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2247 PIN_CFG_PUPD)) },
2248 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2249 PIN_CFG_PUPD)) },
2250 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2251 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2252 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2253 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2254 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2255 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2256 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2257 PIN_CFG_PUPD)) },
2258 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2259 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2260 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2261 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2262 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2263 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2264 PIN_CFG_PUPD)) },
2265 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2266 PIN_CFG_PUPD)) },
2267 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2268 PIN_CFG_PUPD)) },
2269 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2270 PIN_CFG_PUPD)) },
2271 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2272 PIN_CFG_PUPD)) },
2273 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2274 PIN_CFG_PUPD)) },
2275 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2276 PIN_CFG_PUPD)) },
2277 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2278 PIN_CFG_PUPD)) },
2279 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2280 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2281 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2282 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2283 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2284 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2285 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2286 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2287 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2288 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2289 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2290 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2291 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2292 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2293 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2294 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2295 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2296 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2297 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2298 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2299 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2300 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2301 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2302 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2303 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2304 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2305 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2306 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2307 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2308 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2309 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2310 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H |
2311 PIN_CFG_SR)) },
2312 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2313 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2314 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2315 PIN_CFG_PUPD)) },
2316 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2317 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H |
2318 PIN_CFG_SR |
2319 PIN_CFG_PUPD)) },
2320 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2321 PIN_CFG_PUPD)) },
2322 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2323 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2324 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2325 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2326 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2327 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2328 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2329 PIN_CFG_PUPD)) },
2330 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2331 PIN_CFG_PUPD)) },
2332 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2333 PIN_CFG_PUPD)) },
2334 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2335 PIN_CFG_PUPD)) },
2336 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2337 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2338 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2339 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2340 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2341 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2342 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2343 PIN_CFG_PUPD)) },
2344 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2345 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H |
2346 PIN_CFG_SR |
2347 PIN_CFG_PUPD)) },
2348 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2349 PIN_CFG_PUPD)) },
2350 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2351 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2352 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2353 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2354 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2355 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2356 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2357 PIN_CFG_PUPD)) },
2358 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2359 PIN_CFG_PUPD)) },
2360 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2361 PIN_CFG_PUPD)) },
2362 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2363 PIN_CFG_PUPD)) },
2364 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2365 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2366 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2367 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2368 },
2369 .pcie1 = {
2370 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H |
2371 PIN_CFG_SR)) },
2372 },
2373};
2374
2375static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
2376 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
2377 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2378 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
2379 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2380 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2381 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2382 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2383 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2384 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2385 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2386 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2387 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2388 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2389 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2390 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2391 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2392 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
2393 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2394 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2395 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2396 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2397 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2398 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2399 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2400 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2401 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2402 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2403 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2404 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2405 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2406 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
2407 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2408 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
2409 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2410};
2411
2412static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
2413{
2414 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
2415 const struct rzg2l_pinctrl_data *data = pctrl->data;
2416 u64 *pin_data = pin_desc->drv_data;
2417 unsigned int gpioint;
2418 unsigned int i;
2419 u32 port, bit;
2420
2421 if (*pin_data & PIN_CFG_NOGPIO_INT)
2422 return -EINVAL;
2423
2424 port = virq / 8;
2425 bit = virq % 8;
2426
2427 if (port >= data->n_ports ||
2428 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
2429 return -EINVAL;
2430
2431 gpioint = bit;
2432 for (i = 0; i < port; i++)
2433 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));
2434
2435 return gpioint;
2436}
2437
2438static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,
2439 unsigned int hwirq, bool enable)
2440{
2441 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
2442 u64 *pin_data = pin_desc->drv_data;
2443 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2444 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
2445 unsigned long flags;
2446 void __iomem *addr;
2447
2448 addr = pctrl->base + ISEL(off);
2449 if (bit >= 4) {
2450 bit -= 4;
2451 addr += 4;
2452 }
2453
2454 spin_lock_irqsave(&pctrl->lock, flags);
2455 if (enable)
2456 writel(readl(addr) | BIT(bit * 8), addr);
2457 else
2458 writel(readl(addr) & ~BIT(bit * 8), addr);
2459 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
2460}
2461
2462static void rzg2l_gpio_irq_disable(struct irq_data *d)
2463{
2464 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2465 unsigned int hwirq = irqd_to_hwirq(d);
2466
2467 irq_chip_disable_parent(data: d);
2468 gpiochip_disable_irq(gc, offset: hwirq);
2469}
2470
2471static void rzg2l_gpio_irq_enable(struct irq_data *d)
2472{
2473 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2474 unsigned int hwirq = irqd_to_hwirq(d);
2475
2476 gpiochip_enable_irq(gc, offset: hwirq);
2477 irq_chip_enable_parent(data: d);
2478}
2479
2480static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2481{
2482 return irq_chip_set_type_parent(data: d, type);
2483}
2484
2485static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
2486{
2487 irq_chip_eoi_parent(data: d);
2488}
2489
2490static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
2491{
2492 struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data);
2493
2494 seq_puts(m: p, s: dev_name(dev: gc->parent));
2495}
2496
2497static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
2498{
2499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data);
2500 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2501 int ret;
2502
2503 /* It should not happen. */
2504 if (!data->parent_data)
2505 return -EOPNOTSUPP;
2506
2507 ret = irq_chip_set_wake_parent(data, on);
2508 if (ret)
2509 return ret;
2510
2511 if (on)
2512 atomic_inc(v: &pctrl->wakeup_path);
2513 else
2514 atomic_dec(v: &pctrl->wakeup_path);
2515
2516 return 0;
2517}
2518
2519static const struct irq_chip rzg2l_gpio_irqchip = {
2520 .name = "rzg2l-gpio",
2521 .irq_disable = rzg2l_gpio_irq_disable,
2522 .irq_enable = rzg2l_gpio_irq_enable,
2523 .irq_mask = irq_chip_mask_parent,
2524 .irq_unmask = irq_chip_unmask_parent,
2525 .irq_set_type = rzg2l_gpio_irq_set_type,
2526 .irq_eoi = rzg2l_gpio_irqc_eoi,
2527 .irq_print_chip = rzg2l_gpio_irq_print_chip,
2528 .irq_set_affinity = irq_chip_set_affinity_parent,
2529 .irq_set_wake = rzg2l_gpio_irq_set_wake,
2530 .flags = IRQCHIP_IMMUTABLE,
2531 GPIOCHIP_IRQ_RESOURCE_HELPERS,
2532};
2533
2534static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset)
2535{
2536 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
2537 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
2538 u64 *pin_data = pin_desc->drv_data;
2539 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2540 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
2541 u8 reg8;
2542 int ret;
2543
2544 reg8 = readb(addr: pctrl->base + PMC(off));
2545 if (reg8 & BIT(bit)) {
2546 ret = rzg2l_gpio_request(chip, offset);
2547 if (ret)
2548 return ret;
2549 }
2550
2551 return rzg2l_gpio_direction_input(chip, offset);
2552}
2553
2554static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
2555 unsigned int child,
2556 unsigned int child_type,
2557 unsigned int *parent,
2558 unsigned int *parent_type)
2559{
2560 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2561 unsigned long flags;
2562 int gpioint, irq;
2563 int ret;
2564
2565 gpioint = rzg2l_gpio_get_gpioint(virq: child, pctrl);
2566 if (gpioint < 0)
2567 return gpioint;
2568
2569 ret = rzg2l_gpio_interrupt_input_mode(chip: gc, offset: child);
2570 if (ret)
2571 return ret;
2572
2573 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2574 irq = bitmap_find_free_region(bitmap: pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, order: get_order(size: 1));
2575 spin_unlock_irqrestore(lock: &pctrl->bitmap_lock, flags);
2576 if (irq < 0) {
2577 ret = -ENOSPC;
2578 goto err;
2579 }
2580
2581 rzg2l_gpio_irq_endisable(pctrl, hwirq: child, enable: true);
2582 pctrl->hwirq[irq] = child;
2583 irq += pctrl->data->hwcfg->tint_start_index;
2584
2585 /* All these interrupts are level high in the CPU */
2586 *parent_type = IRQ_TYPE_LEVEL_HIGH;
2587 *parent = RZG2L_PACK_HWIRQ(gpioint, irq);
2588 return 0;
2589
2590err:
2591 rzg2l_gpio_free(chip: gc, offset: child);
2592 return ret;
2593}
2594
2595static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
2596{
2597 struct irq_domain *domain = pctrl->gpio_chip.irq.domain;
2598
2599 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2600 struct irq_data *data;
2601 unsigned long flags;
2602 unsigned int virq;
2603 int ret;
2604
2605 if (!pctrl->hwirq[i])
2606 continue;
2607
2608 virq = irq_find_mapping(domain, hwirq: pctrl->hwirq[i]);
2609 if (!virq) {
2610 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n",
2611 pctrl->hwirq[i]);
2612 continue;
2613 }
2614
2615 data = irq_domain_get_irq_data(domain, virq);
2616 if (!data) {
2617 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq);
2618 continue;
2619 }
2620
2621 /*
2622 * This has to be atomically executed to protect against a concurrent
2623 * interrupt.
2624 */
2625 spin_lock_irqsave(&pctrl->lock, flags);
2626 ret = rzg2l_gpio_irq_set_type(d: data, type: irqd_get_trigger_type(d: data));
2627 if (!ret && !irqd_irq_disabled(d: data))
2628 rzg2l_gpio_irq_enable(d: data);
2629 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
2630
2631 if (ret)
2632 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);
2633 }
2634}
2635
2636static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2637 unsigned int nr_irqs)
2638{
2639 struct irq_data *d;
2640
2641 d = irq_domain_get_irq_data(domain, virq);
2642 if (d) {
2643 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2644 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2645 irq_hw_number_t hwirq = irqd_to_hwirq(d);
2646 unsigned long flags;
2647 unsigned int i;
2648
2649 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2650 if (pctrl->hwirq[i] == hwirq) {
2651 rzg2l_gpio_irq_endisable(pctrl, hwirq, enable: false);
2652 rzg2l_gpio_free(chip: gc, offset: hwirq);
2653 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2654 bitmap_release_region(bitmap: pctrl->tint_slot, pos: i, order: get_order(size: 1));
2655 spin_unlock_irqrestore(lock: &pctrl->bitmap_lock, flags);
2656 pctrl->hwirq[i] = 0;
2657 break;
2658 }
2659 }
2660 }
2661 irq_domain_free_irqs_common(domain, virq, nr_irqs);
2662}
2663
2664static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
2665 unsigned long *valid_mask,
2666 unsigned int ngpios)
2667{
2668 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2669 struct gpio_chip *chip = &pctrl->gpio_chip;
2670 unsigned int offset;
2671
2672 /* Forbid unused lines to be mapped as IRQs */
2673 for (offset = 0; offset < chip->ngpio; offset++) {
2674 u32 port, bit;
2675
2676 port = offset / 8;
2677 bit = offset % 8;
2678
2679 if (port >= pctrl->data->n_ports ||
2680 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,
2681 pctrl->data->port_pin_configs[port])))
2682 clear_bit(nr: offset, addr: valid_mask);
2683 }
2684}
2685
2686static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
2687{
2688 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2689 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache;
2690
2691 cache = devm_kzalloc(dev: pctrl->dev, size: sizeof(*cache), GFP_KERNEL);
2692 if (!cache)
2693 return -ENOMEM;
2694
2695 dedicated_cache = devm_kzalloc(dev: pctrl->dev, size: sizeof(*dedicated_cache), GFP_KERNEL);
2696 if (!dedicated_cache)
2697 return -ENOMEM;
2698
2699 cache->p = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->p), GFP_KERNEL);
2700 if (!cache->p)
2701 return -ENOMEM;
2702
2703 cache->pm = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pm), GFP_KERNEL);
2704 if (!cache->pm)
2705 return -ENOMEM;
2706
2707 cache->pmc = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pmc), GFP_KERNEL);
2708 if (!cache->pmc)
2709 return -ENOMEM;
2710
2711 cache->pfc = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pfc), GFP_KERNEL);
2712 if (!cache->pfc)
2713 return -ENOMEM;
2714
2715 for (u8 i = 0; i < 2; i++) {
2716 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
2717
2718 cache->iolh[i] = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->iolh[i]),
2719 GFP_KERNEL);
2720 if (!cache->iolh[i])
2721 return -ENOMEM;
2722
2723 cache->ien[i] = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->ien[i]),
2724 GFP_KERNEL);
2725 if (!cache->ien[i])
2726 return -ENOMEM;
2727
2728 cache->pupd[i] = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pupd[i]),
2729 GFP_KERNEL);
2730 if (!cache->pupd[i])
2731 return -ENOMEM;
2732
2733 /* Allocate dedicated cache. */
2734 dedicated_cache->iolh[i] = devm_kcalloc(dev: pctrl->dev, n: n_dedicated_pins,
2735 size: sizeof(*dedicated_cache->iolh[i]),
2736 GFP_KERNEL);
2737 if (!dedicated_cache->iolh[i])
2738 return -ENOMEM;
2739
2740 dedicated_cache->ien[i] = devm_kcalloc(dev: pctrl->dev, n: n_dedicated_pins,
2741 size: sizeof(*dedicated_cache->ien[i]),
2742 GFP_KERNEL);
2743 if (!dedicated_cache->ien[i])
2744 return -ENOMEM;
2745 }
2746
2747 pctrl->cache = cache;
2748 pctrl->dedicated_cache = dedicated_cache;
2749
2750 return 0;
2751}
2752
2753static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
2754{
2755 struct device_node *np = pctrl->dev->of_node;
2756 struct gpio_chip *chip = &pctrl->gpio_chip;
2757 const char *name = dev_name(dev: pctrl->dev);
2758 struct irq_domain *parent_domain;
2759 struct of_phandle_args of_args;
2760 struct device_node *parent_np;
2761 struct gpio_irq_chip *girq;
2762 int ret;
2763
2764 parent_np = of_irq_find_parent(child: np);
2765 if (!parent_np)
2766 return -ENXIO;
2767
2768 parent_domain = irq_find_host(node: parent_np);
2769 of_node_put(node: parent_np);
2770 if (!parent_domain)
2771 return -EPROBE_DEFER;
2772
2773 ret = of_parse_phandle_with_fixed_args(np, list_name: "gpio-ranges", cell_count: 3, index: 0, out_args: &of_args);
2774 if (ret)
2775 return dev_err_probe(dev: pctrl->dev, err: ret, fmt: "Unable to parse gpio-ranges\n");
2776
2777 of_node_put(node: of_args.np);
2778
2779 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
2780 of_args.args[2] != pctrl->data->n_port_pins)
2781 return dev_err_probe(dev: pctrl->dev, err: -EINVAL,
2782 fmt: "gpio-ranges does not match selected SOC\n");
2783
2784 chip->names = pctrl->data->port_pins;
2785 chip->request = rzg2l_gpio_request;
2786 chip->free = rzg2l_gpio_free;
2787 chip->get_direction = rzg2l_gpio_get_direction;
2788 chip->direction_input = rzg2l_gpio_direction_input;
2789 chip->direction_output = rzg2l_gpio_direction_output;
2790 chip->get = rzg2l_gpio_get;
2791 chip->set = rzg2l_gpio_set;
2792 chip->label = name;
2793 chip->parent = pctrl->dev;
2794 chip->owner = THIS_MODULE;
2795 chip->base = -1;
2796 chip->ngpio = of_args.args[2];
2797
2798 girq = &chip->irq;
2799 gpio_irq_chip_set_chip(girq, chip: &rzg2l_gpio_irqchip);
2800 girq->fwnode = dev_fwnode(pctrl->dev);
2801 girq->parent_domain = parent_domain;
2802 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
2803 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
2804 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
2805 girq->init_valid_mask = rzg2l_init_irq_valid_mask;
2806
2807 pctrl->gpio_range.id = 0;
2808 pctrl->gpio_range.pin_base = 0;
2809 pctrl->gpio_range.base = 0;
2810 pctrl->gpio_range.npins = chip->ngpio;
2811 pctrl->gpio_range.name = chip->label;
2812 pctrl->gpio_range.gc = chip;
2813 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
2814 if (ret)
2815 return dev_err_probe(dev: pctrl->dev, err: ret, fmt: "failed to add GPIO controller\n");
2816
2817 dev_dbg(pctrl->dev, "Registered gpio controller\n");
2818
2819 return 0;
2820}
2821
2822static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
2823{
2824 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2825 struct pinctrl_pin_desc *pins;
2826 unsigned int i, j;
2827 u64 *pin_data;
2828 int ret;
2829
2830 pctrl->desc.name = DRV_NAME;
2831 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
2832 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
2833 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
2834 pctrl->desc.confops = &rzg2l_pinctrl_confops;
2835 pctrl->desc.owner = THIS_MODULE;
2836 if (pctrl->data->num_custom_params) {
2837 pctrl->desc.num_custom_params = pctrl->data->num_custom_params;
2838 pctrl->desc.custom_params = pctrl->data->custom_params;
2839#ifdef CONFIG_DEBUG_FS
2840 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;
2841#endif
2842 }
2843
2844 pins = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins, size: sizeof(*pins), GFP_KERNEL);
2845 if (!pins)
2846 return -ENOMEM;
2847
2848 pin_data = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins,
2849 size: sizeof(*pin_data), GFP_KERNEL);
2850 if (!pin_data)
2851 return -ENOMEM;
2852
2853 pctrl->pins = pins;
2854 pctrl->desc.pins = pins;
2855
2856 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
2857 pins[i].number = i;
2858 pins[i].name = pctrl->data->port_pins[i];
2859 if (i && !(i % RZG2L_PINS_PER_PORT))
2860 j++;
2861 pin_data[i] = pctrl->data->port_pin_configs[j];
2862 if (pin_data[i] & RZG2L_VARIABLE_CFG)
2863 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
2864 pincfg: pin_data[i],
2865 port: j,
2866 pin: i % RZG2L_PINS_PER_PORT);
2867 pins[i].drv_data = &pin_data[i];
2868 }
2869
2870 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
2871 unsigned int index = pctrl->data->n_port_pins + i;
2872
2873 pins[index].number = index;
2874 pins[index].name = pctrl->data->dedicated_pins[i].name;
2875 pin_data[index] = pctrl->data->dedicated_pins[i].config;
2876 pins[index].drv_data = &pin_data[index];
2877 }
2878
2879 pctrl->settings = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins, size: sizeof(*pctrl->settings),
2880 GFP_KERNEL);
2881 if (!pctrl->settings)
2882 return -ENOMEM;
2883
2884 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
2885 if (pin_data[i] & PIN_CFG_SOFT_PS) {
2886 pctrl->settings[i].power_source = 3300;
2887 } else {
2888 ret = rzg2l_get_power_source(pctrl, pin: i, caps: pin_data[i]);
2889 if (ret < 0)
2890 continue;
2891 pctrl->settings[i].power_source = ret;
2892 }
2893 }
2894
2895 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl);
2896 if (ret)
2897 return ret;
2898
2899 ret = devm_pinctrl_register_and_init(dev: pctrl->dev, pctldesc: &pctrl->desc, driver_data: pctrl,
2900 pctldev: &pctrl->pctl);
2901 if (ret)
2902 return dev_err_probe(dev: pctrl->dev, err: ret, fmt: "pinctrl registration failed\n");
2903
2904 ret = pinctrl_enable(pctldev: pctrl->pctl);
2905 if (ret)
2906 return dev_err_probe(dev: pctrl->dev, err: ret, fmt: "pinctrl enable failed\n");
2907
2908 ret = rzg2l_gpio_register(pctrl);
2909 if (ret)
2910 return dev_err_probe(dev: pctrl->dev, err: ret, fmt: "failed to add GPIO chip\n");
2911
2912 return 0;
2913}
2914
2915static int rzg2l_pinctrl_probe(struct platform_device *pdev)
2916{
2917 struct rzg2l_pinctrl *pctrl;
2918 int ret;
2919
2920 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
2921 ARRAY_SIZE(rzg2l_gpio_names));
2922
2923 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
2924 ARRAY_SIZE(rzg2l_gpio_names));
2925
2926 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2927 ARRAY_SIZE(rzg2l_gpio_names));
2928
2929 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
2930 ARRAY_SIZE(rzg3e_gpio_names));
2931
2932 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
2933 ARRAY_SIZE(rzv2h_gpio_names));
2934
2935 pctrl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctrl), GFP_KERNEL);
2936 if (!pctrl)
2937 return -ENOMEM;
2938
2939 pctrl->dev = &pdev->dev;
2940
2941 pctrl->data = of_device_get_match_data(dev: &pdev->dev);
2942 if (!pctrl->data)
2943 return -EINVAL;
2944
2945 pctrl->base = devm_platform_ioremap_resource(pdev, index: 0);
2946 if (IS_ERR(ptr: pctrl->base))
2947 return PTR_ERR(ptr: pctrl->base);
2948
2949 pctrl->clk = devm_clk_get_enabled(dev: pctrl->dev, NULL);
2950 if (IS_ERR(ptr: pctrl->clk)) {
2951 return dev_err_probe(dev: pctrl->dev, err: PTR_ERR(ptr: pctrl->clk),
2952 fmt: "failed to enable GPIO clk\n");
2953 }
2954
2955 spin_lock_init(&pctrl->lock);
2956 spin_lock_init(&pctrl->bitmap_lock);
2957 mutex_init(&pctrl->mutex);
2958 atomic_set(v: &pctrl->wakeup_path, i: 0);
2959
2960 platform_set_drvdata(pdev, data: pctrl);
2961
2962 ret = rzg2l_pinctrl_register(pctrl);
2963 if (ret)
2964 return ret;
2965
2966 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
2967 return 0;
2968}
2969
2970static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2971{
2972 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2973 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2974
2975 for (u32 port = 0; port < nports; port++) {
2976 bool has_iolh, has_ien, has_pupd;
2977 u32 off, caps;
2978 u8 pincnt;
2979 u64 cfg;
2980
2981 cfg = pctrl->data->port_pin_configs[port];
2982 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2983 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));
2984
2985 caps = FIELD_GET(PIN_CFG_MASK, cfg);
2986 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2987 has_ien = !!(caps & PIN_CFG_IEN);
2988 has_pupd = !!(caps & PIN_CFG_PUPD);
2989
2990 if (suspend)
2991 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
2992
2993 /*
2994 * Now cache the registers or set them in the order suggested by
2995 * HW manual (section "Operation for GPIO Function").
2996 */
2997 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
2998 if (has_iolh) {
2999 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
3000 cache->iolh[0][port]);
3001 if (pincnt >= 4) {
3002 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4,
3003 cache->iolh[1][port]);
3004 }
3005 }
3006
3007 if (has_pupd) {
3008 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
3009 cache->pupd[0][port]);
3010 if (pincnt >= 4) {
3011 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
3012 cache->pupd[1][port]);
3013 }
3014 }
3015
3016 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
3017 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
3018
3019 if (has_ien) {
3020 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3021 cache->ien[0][port]);
3022 if (pincnt >= 4) {
3023 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4,
3024 cache->ien[1][port]);
3025 }
3026 }
3027 }
3028}
3029
3030static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
3031{
3032 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
3033 u32 caps;
3034 u32 i;
3035
3036 /*
3037 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same
3038 * port offset are close together.
3039 */
3040 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
3041 bool has_iolh, has_ien;
3042 u32 off, next_off = 0;
3043 u64 cfg, next_cfg;
3044 u8 pincnt;
3045
3046 cfg = pctrl->data->dedicated_pins[i].config;
3047 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3048 if (i + 1 < pctrl->data->n_dedicated_pins) {
3049 next_cfg = pctrl->data->dedicated_pins[i + 1].config;
3050 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg);
3051 }
3052
3053 if (off == next_off) {
3054 /* Gather caps of all port pins. */
3055 caps |= FIELD_GET(PIN_CFG_MASK, cfg);
3056 continue;
3057 }
3058
3059 /* And apply them in a single shot. */
3060 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
3061 has_ien = !!(caps & PIN_CFG_IEN);
3062 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
3063
3064 if (has_iolh) {
3065 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
3066 cache->iolh[0][i]);
3067 }
3068 if (has_ien) {
3069 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3070 cache->ien[0][i]);
3071 }
3072
3073 if (pincnt >= 4) {
3074 if (has_iolh) {
3075 RZG2L_PCTRL_REG_ACCESS32(suspend,
3076 pctrl->base + IOLH(off) + 4,
3077 cache->iolh[1][i]);
3078 }
3079 if (has_ien) {
3080 RZG2L_PCTRL_REG_ACCESS32(suspend,
3081 pctrl->base + IEN(off) + 4,
3082 cache->ien[1][i]);
3083 }
3084 }
3085 caps = 0;
3086 }
3087}
3088
3089static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
3090{
3091 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
3092 unsigned long flags;
3093
3094 spin_lock_irqsave(&pctrl->lock, flags);
3095 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
3096
3097 /* Restore port registers. */
3098 for (u32 port = 0; port < nports; port++) {
3099 unsigned long pinmap;
3100 u8 pmc = 0, max_pin;
3101 u32 off, pfc = 0;
3102 u64 cfg;
3103 u16 pm;
3104 u8 pin;
3105
3106 cfg = pctrl->data->port_pin_configs[port];
3107 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3108 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
3109 max_pin = fls(x: pinmap);
3110
3111 pm = readw(addr: pctrl->base + PM(off));
3112 for_each_set_bit(pin, &pinmap, max_pin) {
3113 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3114
3115 /* Nothing to do if PFC was not configured before. */
3116 if (!(cache->pmc[port] & BIT(pin)))
3117 continue;
3118
3119 /* Set pin to 'Non-use (Hi-Z input protection)' */
3120 pm &= ~(PM_MASK << (pin * 2));
3121 writew(val: pm, addr: pctrl->base + PM(off));
3122
3123 /* Temporarily switch to GPIO mode with PMC register */
3124 pmc &= ~BIT(pin);
3125 writeb(val: pmc, addr: pctrl->base + PMC(off));
3126
3127 /* Select Pin function mode. */
3128 pfc &= ~(PFC_MASK << (pin * 4));
3129 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
3130 writel(val: pfc, addr: pctrl->base + PFC(off));
3131
3132 /* Switch to Peripheral pin function. */
3133 pmc |= BIT(pin);
3134 writeb(val: pmc, addr: pctrl->base + PMC(off));
3135 }
3136 }
3137
3138 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
3139 spin_unlock_irqrestore(lock: &pctrl->lock, flags);
3140}
3141
3142static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
3143{
3144 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3145 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3146 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3147 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3148
3149 rzg2l_pinctrl_pm_setup_regs(pctrl, suspend: true);
3150 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, suspend: true);
3151
3152 for (u8 i = 0; i < 2; i++) {
3153 if (regs->sd_ch)
3154 cache->sd_ch[i] = readb(addr: pctrl->base + SD_CH(regs->sd_ch, i));
3155 if (regs->eth_poc)
3156 cache->eth_poc[i] = readb(addr: pctrl->base + ETH_POC(regs->eth_poc, i));
3157 }
3158
3159 cache->qspi = readb(addr: pctrl->base + QSPI);
3160 cache->eth_mode = readb(addr: pctrl->base + ETH_MODE);
3161
3162 if (!atomic_read(v: &pctrl->wakeup_path))
3163 clk_disable_unprepare(clk: pctrl->clk);
3164 else
3165 device_set_wakeup_path(dev);
3166
3167 return 0;
3168}
3169
3170static int rzg2l_pinctrl_resume_noirq(struct device *dev)
3171{
3172 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3173 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3174 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3175 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3176 int ret;
3177
3178 if (!atomic_read(v: &pctrl->wakeup_path)) {
3179 ret = clk_prepare_enable(clk: pctrl->clk);
3180 if (ret)
3181 return ret;
3182 }
3183
3184 writeb(val: cache->qspi, addr: pctrl->base + QSPI);
3185 writeb(val: cache->eth_mode, addr: pctrl->base + ETH_MODE);
3186 for (u8 i = 0; i < 2; i++) {
3187 if (regs->sd_ch)
3188 writeb(val: cache->sd_ch[i], addr: pctrl->base + SD_CH(regs->sd_ch, i));
3189 if (regs->eth_poc)
3190 writeb(val: cache->eth_poc[i], addr: pctrl->base + ETH_POC(regs->eth_poc, i));
3191 }
3192
3193 rzg2l_pinctrl_pm_setup_pfc(pctrl);
3194 rzg2l_pinctrl_pm_setup_regs(pctrl, suspend: false);
3195 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, suspend: false);
3196 rzg2l_gpio_irq_restore(pctrl);
3197
3198 return 0;
3199}
3200
3201static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3202{
3203 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3204
3205 if (lock) {
3206 /* Set the PWPR register to be write-protected */
3207 writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3208 writel(PWPR_B0WI, addr: pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
3209 } else {
3210 /* Set the PWPR register to allow PFC register to write */
3211 writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3212 writel(PWPR_PFCWE, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
3213 }
3214}
3215
3216static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3217{
3218 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3219 u8 pwpr;
3220
3221 if (lock) {
3222 /* Set the PWPR register to be write-protected */
3223 pwpr = readb(addr: pctrl->base + regs->pwpr);
3224 writeb(val: pwpr & ~PWPR_REGWE_A, addr: pctrl->base + regs->pwpr);
3225 } else {
3226 /* Set the PWPR register to allow PFC and PMC register to write */
3227 pwpr = readb(addr: pctrl->base + regs->pwpr);
3228 writeb(PWPR_REGWE_A | pwpr, addr: pctrl->base + regs->pwpr);
3229 }
3230}
3231
3232static const struct rzg2l_hwcfg rzg2l_hwcfg = {
3233 .regs = {
3234 .pwpr = 0x3014,
3235 .sd_ch = 0x3000,
3236 .eth_poc = 0x300c,
3237 },
3238 .iolh_groupa_ua = {
3239 /* 3v3 power source */
3240 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
3241 },
3242 .iolh_groupb_oi = { 100, 66, 50, 33, },
3243 .tint_start_index = 9,
3244 .oen_max_pin = 0,
3245};
3246
3247static const struct rzg2l_hwcfg rzg3s_hwcfg = {
3248 .regs = {
3249 .pwpr = 0x3000,
3250 .sd_ch = 0x3004,
3251 .eth_poc = 0x3010,
3252 },
3253 .iolh_groupa_ua = {
3254 /* 1v8 power source */
3255 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
3256 /* 3v3 power source */
3257 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
3258 },
3259 .iolh_groupb_ua = {
3260 /* 1v8 power source */
3261 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
3262 /* 3v3 power source */
3263 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
3264 },
3265 .iolh_groupc_ua = {
3266 /* 1v8 power source */
3267 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
3268 /* 2v5 source */
3269 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
3270 /* 3v3 power source */
3271 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
3272 },
3273 .tint_start_index = 9,
3274 .drive_strength_ua = true,
3275 .func_base = 1,
3276 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
3277 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */
3278};
3279
3280static const struct rzg2l_hwcfg rzv2h_hwcfg = {
3281 .regs = {
3282 .pwpr = 0x3c04,
3283 },
3284 .tint_start_index = 17,
3285};
3286
3287static struct rzg2l_pinctrl_data r9a07g043_data = {
3288 .port_pins = rzg2l_gpio_names,
3289 .port_pin_configs = r9a07g043_gpio_configs,
3290 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
3291 .dedicated_pins = rzg2l_dedicated_pins.common,
3292 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
3293 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
3294 .hwcfg = &rzg2l_hwcfg,
3295#ifdef CONFIG_RISCV
3296 .variable_pin_cfg = r9a07g043f_variable_pin_cfg,
3297 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
3298#endif
3299 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3300 .pmc_writeb = &rzg2l_pmc_writeb,
3301 .oen_read = &rzg2l_read_oen,
3302 .oen_write = &rzg2l_write_oen,
3303 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3304 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3305};
3306
3307static struct rzg2l_pinctrl_data r9a07g044_data = {
3308 .port_pins = rzg2l_gpio_names,
3309 .port_pin_configs = r9a07g044_gpio_configs,
3310 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
3311 .dedicated_pins = rzg2l_dedicated_pins.common,
3312 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
3313 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
3314 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
3315 .hwcfg = &rzg2l_hwcfg,
3316 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3317 .pmc_writeb = &rzg2l_pmc_writeb,
3318 .oen_read = &rzg2l_read_oen,
3319 .oen_write = &rzg2l_write_oen,
3320 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3321 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3322};
3323
3324static struct rzg2l_pinctrl_data r9a08g045_data = {
3325 .port_pins = rzg2l_gpio_names,
3326 .port_pin_configs = r9a08g045_gpio_configs,
3327 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
3328 .dedicated_pins = rzg3s_dedicated_pins,
3329 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
3330 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
3331 .hwcfg = &rzg3s_hwcfg,
3332 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3333 .pmc_writeb = &rzg2l_pmc_writeb,
3334 .oen_read = &rzg3s_oen_read,
3335 .oen_write = &rzg3s_oen_write,
3336 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3337 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3338};
3339
3340static struct rzg2l_pinctrl_data r9a09g047_data = {
3341 .port_pins = rzg3e_gpio_names,
3342 .port_pin_configs = r9a09g047_gpio_configs,
3343 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
3344 .dedicated_pins = rzg3e_dedicated_pins,
3345 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
3346 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
3347 .hwcfg = &rzv2h_hwcfg,
3348 .variable_pin_cfg = r9a09g047_variable_pin_cfg,
3349 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
3350 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3351 .custom_params = renesas_rzv2h_custom_bindings,
3352#ifdef CONFIG_DEBUG_FS
3353 .custom_conf_items = renesas_rzv2h_conf_items,
3354#endif
3355 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3356 .pmc_writeb = &rzv2h_pmc_writeb,
3357 .oen_read = &rzv2h_oen_read,
3358 .oen_write = &rzv2h_oen_write,
3359 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3360 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3361};
3362
3363static struct rzg2l_pinctrl_data r9a09g056_data = {
3364 .port_pins = rzv2h_gpio_names,
3365 .port_pin_configs = r9a09g057_gpio_configs,
3366 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3367 .dedicated_pins = rzv2h_dedicated_pins.common,
3368 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3369 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common),
3370 .hwcfg = &rzv2h_hwcfg,
3371 .variable_pin_cfg = r9a09g057_variable_pin_cfg,
3372 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3373 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3374 .custom_params = renesas_rzv2h_custom_bindings,
3375#ifdef CONFIG_DEBUG_FS
3376 .custom_conf_items = renesas_rzv2h_conf_items,
3377#endif
3378 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3379 .pmc_writeb = &rzv2h_pmc_writeb,
3380 .oen_read = &rzv2h_oen_read,
3381 .oen_write = &rzv2h_oen_write,
3382 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3383 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3384};
3385
3386static struct rzg2l_pinctrl_data r9a09g057_data = {
3387 .port_pins = rzv2h_gpio_names,
3388 .port_pin_configs = r9a09g057_gpio_configs,
3389 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3390 .dedicated_pins = rzv2h_dedicated_pins.common,
3391 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3392 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) +
3393 ARRAY_SIZE(rzv2h_dedicated_pins.pcie1),
3394 .hwcfg = &rzv2h_hwcfg,
3395 .variable_pin_cfg = r9a09g057_variable_pin_cfg,
3396 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3397 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3398 .custom_params = renesas_rzv2h_custom_bindings,
3399#ifdef CONFIG_DEBUG_FS
3400 .custom_conf_items = renesas_rzv2h_conf_items,
3401#endif
3402 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3403 .pmc_writeb = &rzv2h_pmc_writeb,
3404 .oen_read = &rzv2h_oen_read,
3405 .oen_write = &rzv2h_oen_write,
3406 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3407 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3408};
3409
3410static const struct of_device_id rzg2l_pinctrl_of_table[] = {
3411 {
3412 .compatible = "renesas,r9a07g043-pinctrl",
3413 .data = &r9a07g043_data,
3414 },
3415 {
3416 .compatible = "renesas,r9a07g044-pinctrl",
3417 .data = &r9a07g044_data,
3418 },
3419 {
3420 .compatible = "renesas,r9a08g045-pinctrl",
3421 .data = &r9a08g045_data,
3422 },
3423 {
3424 .compatible = "renesas,r9a09g047-pinctrl",
3425 .data = &r9a09g047_data,
3426 },
3427 {
3428 .compatible = "renesas,r9a09g056-pinctrl",
3429 .data = &r9a09g056_data,
3430 },
3431 {
3432 .compatible = "renesas,r9a09g057-pinctrl",
3433 .data = &r9a09g057_data,
3434 },
3435 { /* sentinel */ }
3436};
3437
3438static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = {
3439 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq)
3440};
3441
3442static struct platform_driver rzg2l_pinctrl_driver = {
3443 .driver = {
3444 .name = DRV_NAME,
3445 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
3446 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops),
3447 .suppress_bind_attrs = true,
3448 },
3449 .probe = rzg2l_pinctrl_probe,
3450};
3451
3452static int __init rzg2l_pinctrl_init(void)
3453{
3454 return platform_driver_register(&rzg2l_pinctrl_driver);
3455}
3456core_initcall(rzg2l_pinctrl_init);
3457
3458MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
3459MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
3460

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source code of linux/drivers/pinctrl/renesas/pinctrl-rzg2l.c