1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Renesas RZ/G2L Pin Control and GPIO driver core
4	*
5	* Copyright (C) 2021 Renesas Electronics Corporation.
6	*/
7
8	#include <linux/bitfield.h>
9	#include <linux/bitops.h>
10	#include <linux/clk.h>
11	#include <linux/gpio/driver.h>
12	#include <linux/interrupt.h>
13	#include <linux/io.h>
14	#include <linux/module.h>
15	#include <linux/mutex.h>
16	#include <linux/of.h>
17	#include <linux/of_irq.h>
18	#include <linux/platform_device.h>
19	#include <linux/seq_file.h>
20	#include <linux/spinlock.h>
21
22	#include <linux/pinctrl/consumer.h>
23	#include <linux/pinctrl/pinconf-generic.h>
24	#include <linux/pinctrl/pinconf.h>
25	#include <linux/pinctrl/pinctrl.h>
26	#include <linux/pinctrl/pinmux.h>
27
28	#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
29
30	#include "../core.h"
31	#include "../pinconf.h"
32	#include "../pinmux.h"
33
34	#define DRV_NAME "pinctrl-rzg2l"
35
36	/*
37	* Use 16 lower bits [15:0] for pin identifier
38	* Use 16 higher bits [31:16] for pin mux function
39	*/
40	#define MUX_PIN_ID_MASK GENMASK(15, 0)
41	#define MUX_FUNC_MASK GENMASK(31, 16)
42
43	/* PIN capabilities */
44	#define PIN_CFG_IOLH_A BIT(0)
45	#define PIN_CFG_IOLH_B BIT(1)
46	#define PIN_CFG_SR BIT(2)
47	#define PIN_CFG_IEN BIT(3)
48	#define PIN_CFG_PUPD BIT(4)
49	#define PIN_CFG_IO_VMC_SD0 BIT(5)
50	#define PIN_CFG_IO_VMC_SD1 BIT(6)
51	#define PIN_CFG_IO_VMC_QSPI BIT(7)
52	#define PIN_CFG_IO_VMC_ETH0 BIT(8)
53	#define PIN_CFG_IO_VMC_ETH1 BIT(9)
54	#define PIN_CFG_FILONOFF BIT(10)
55	#define PIN_CFG_FILNUM BIT(11)
56	#define PIN_CFG_FILCLKSEL BIT(12)
57	#define PIN_CFG_IOLH_C BIT(13)
58	#define PIN_CFG_SOFT_PS BIT(14)
59	#define PIN_CFG_OEN BIT(15)
60	#define PIN_CFG_VARIABLE BIT(16)
61	#define PIN_CFG_NOGPIO_INT BIT(17)
62
63	#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
64	(PIN_CFG_IOLH_##group | \
65	PIN_CFG_PUPD | \
66	PIN_CFG_FILONOFF | \
67	PIN_CFG_FILNUM | \
68	PIN_CFG_FILCLKSEL)
69
70	#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
71	PIN_CFG_SR)
72
73	#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
74	PIN_CFG_SOFT_PS)
75
76	#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
77	PIN_CFG_FILONOFF | \
78	PIN_CFG_FILNUM | \
79	PIN_CFG_FILCLKSEL)
80
81	#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28)
82	#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20)
83	#define PIN_CFG_MASK GENMASK(19, 0)
84
85	/*
86	* m indicates the bitmap of supported pins, a is the register index
87	* and f is pin configuration capabilities supported.
88	*/
89	#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
90	FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
91	FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
92
93	/*
94	* n indicates number of pins in the port, a is the register index
95	* and f is pin configuration capabilities supported.
96	*/
97	#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
98
99	/*
100	* BIT(63) indicates dedicated pin, p is the register index while
101	* referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
102	* (b * 8) and f is the pin configuration capabilities supported.
103	*/
104	#define RZG2L_SINGLE_PIN BIT_ULL(63)
105	#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24)
106	#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20)
107
108	#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
109	FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
110	FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
111	FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
112
113	#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \
114	FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
115	FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
116
117	#define P(off) (0x0000 + (off))
118	#define PM(off) (0x0100 + (off) * 2)
119	#define PMC(off) (0x0200 + (off))
120	#define PFC(off) (0x0400 + (off) * 4)
121	#define PIN(off) (0x0800 + (off))
122	#define IOLH(off) (0x1000 + (off) * 8)
123	#define IEN(off) (0x1800 + (off) * 8)
124	#define ISEL(off) (0x2C00 + (off) * 8)
125	#define SD_CH(off, ch) ((off) + (ch) * 4)
126	#define ETH_POC(off, ch) ((off) + (ch) * 4)
127	#define QSPI (0x3008)
128	#define ETH_MODE (0x3018)
129
130	#define PVDD_2500 2 /* I/O domain voltage 2.5V */
131	#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
132	#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
133
134	#define PWPR_B0WI BIT(7) /* Bit Write Disable */
135	#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
136
137	#define PM_MASK 0x03
138	#define PFC_MASK 0x07
139	#define IEN_MASK 0x01
140	#define IOLH_MASK 0x03
141
142	#define PM_INPUT 0x1
143	#define PM_OUTPUT 0x2
144
145	#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
146	#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
147
148	#define RZG2L_TINT_MAX_INTERRUPT 32
149	#define RZG2L_TINT_IRQ_START_INDEX 9
150	#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
151
152	/* Read/write 8 bits register */
153	#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
154	do { \
155	if (_read) \
156	_val = readb(_addr); \
157	else \
158	writeb(_val, _addr); \
159	} while (0)
160
161	/* Read/write 16 bits register */
162	#define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \
163	do { \
164	if (_read) \
165	_val = readw(_addr); \
166	else \
167	writew(_val, _addr); \
168	} while (0)
169
170	/* Read/write 32 bits register */
171	#define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \
172	do { \
173	if (_read) \
174	_val = readl(_addr); \
175	else \
176	writel(_val, _addr); \
177	} while (0)
178
179	/**
180	* struct rzg2l_register_offsets - specific register offsets
181	* @pwpr: PWPR register offset
182	* @sd_ch: SD_CH register offset
183	* @eth_poc: ETH_POC register offset
184	*/
185	struct rzg2l_register_offsets {
186	u16 pwpr;
187	u16 sd_ch;
188	u16 eth_poc;
189	};
190
191	/**
192	* enum rzg2l_iolh_index - starting indices in IOLH specific arrays
193	* @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
194	* @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
195	* @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
196	* @RZG2L_IOLH_IDX_MAX: maximum index
197	*/
198	enum rzg2l_iolh_index {
199	RZG2L_IOLH_IDX_1V8 = 0,
200	RZG2L_IOLH_IDX_2V5 = 4,
201	RZG2L_IOLH_IDX_3V3 = 8,
202	RZG2L_IOLH_IDX_MAX = 12,
203	};
204
205	/* Maximum number of driver strength entries per power source. */
206	#define RZG2L_IOLH_MAX_DS_ENTRIES (4)
207
208	/**
209	* struct rzg2l_hwcfg - hardware configuration data structure
210	* @regs: hardware specific register offsets
211	* @iolh_groupa_ua: IOLH group A uA specific values
212	* @iolh_groupb_ua: IOLH group B uA specific values
213	* @iolh_groupc_ua: IOLH group C uA specific values
214	* @iolh_groupb_oi: IOLH group B output impedance specific values
215	* @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
216	* @func_base: base number for port function (see register PFC)
217	* @oen_max_pin: the maximum pin number supporting output enable
218	* @oen_max_port: the maximum port number supporting output enable
219	*/
220	struct rzg2l_hwcfg {
221	const struct rzg2l_register_offsets regs;
222	u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
223	u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
224	u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
225	u16 iolh_groupb_oi[4];
226	bool drive_strength_ua;
227	u8 func_base;
228	u8 oen_max_pin;
229	u8 oen_max_port;
230	};
231
232	struct rzg2l_dedicated_configs {
233	const char *name;
234	u64 config;
235	};
236
237	/**
238	* struct rzg2l_variable_pin_cfg - pin data cfg
239	* @cfg: port pin configuration
240	* @port: port number
241	* @pin: port pin
242	*/
243	struct rzg2l_variable_pin_cfg {
244	u32 cfg:20;
245	u32 port:5;
246	u32 pin:3;
247	};
248
249	struct rzg2l_pinctrl_data {
250	const char * const *port_pins;
251	const u64 *port_pin_configs;
252	unsigned int n_ports;
253	const struct rzg2l_dedicated_configs *dedicated_pins;
254	unsigned int n_port_pins;
255	unsigned int n_dedicated_pins;
256	const struct rzg2l_hwcfg *hwcfg;
257	const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
258	unsigned int n_variable_pin_cfg;
259	};
260
261	/**
262	* struct rzg2l_pinctrl_pin_settings - pin data
263	* @power_source: power source
264	* @drive_strength_ua: drive strength (in micro amps)
265	*/
266	struct rzg2l_pinctrl_pin_settings {
267	u16 power_source;
268	u16 drive_strength_ua;
269	};
270
271	/**
272	* struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
273	* @p: P registers cache
274	* @pm: PM registers cache
275	* @pmc: PMC registers cache
276	* @pfc: PFC registers cache
277	* @iolh: IOLH registers cache
278	* @ien: IEN registers cache
279	* @sd_ch: SD_CH registers cache
280	* @eth_poc: ET_POC registers cache
281	* @eth_mode: ETH_MODE register cache
282	* @qspi: QSPI registers cache
283	*/
284	struct rzg2l_pinctrl_reg_cache {
285	u8 *p;
286	u16 *pm;
287	u8 *pmc;
288	u32 *pfc;
289	u32 *iolh[2];
290	u32 *ien[2];
291	u8 sd_ch[2];
292	u8 eth_poc[2];
293	u8 eth_mode;
294	u8 qspi;
295	};
296
297	struct rzg2l_pinctrl {
298	struct pinctrl_dev *pctl;
299	struct pinctrl_desc desc;
300	struct pinctrl_pin_desc *pins;
301
302	const struct rzg2l_pinctrl_data *data;
303	void __iomem *base;
304	struct device *dev;
305
306	struct clk *clk;
307
308	struct gpio_chip gpio_chip;
309	struct pinctrl_gpio_range gpio_range;
310	DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
311	spinlock_t bitmap_lock; /* protect tint_slot bitmap */
312	unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
313
314	spinlock_t lock; /* lock read/write registers */
315	struct mutex mutex; /* serialize adding groups and functions */
316
317	struct rzg2l_pinctrl_pin_settings *settings;
318	struct rzg2l_pinctrl_reg_cache *cache;
319	struct rzg2l_pinctrl_reg_cache *dedicated_cache;
320	atomic_t wakeup_path;
321	};
322
323	static const u16 available_ps[] = { 1800, 2500, 3300 };
324
325	#ifdef CONFIG_RISCV
326	static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
327	u64 pincfg,
328	unsigned int port,
329	u8 pin)
330	{
331	unsigned int i;
332
333	for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
334	if (pctrl->data->variable_pin_cfg[i].port == port &&
335	pctrl->data->variable_pin_cfg[i].pin == pin)
336	return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;
337	}
338
339	return 0;
340	}
341
342	static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {
343	{
344	.port = 20,
345	.pin = 0,
346	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
347	PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
348	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
349	},
350	{
351	.port = 20,
352	.pin = 1,
353	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
354	PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
355	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
356	},
357	{
358	.port = 20,
359	.pin = 2,
360	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
361	PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
362	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
363	},
364	{
365	.port = 20,
366	.pin = 3,
367	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
368	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
369	},
370	{
371	.port = 20,
372	.pin = 4,
373	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
374	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
375	},
376	{
377	.port = 20,
378	.pin = 5,
379	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
380	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
381	},
382	{
383	.port = 20,
384	.pin = 6,
385	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
386	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
387	},
388	{
389	.port = 20,
390	.pin = 7,
391	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
392	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
393	},
394	{
395	.port = 23,
396	.pin = 1,
397	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
398	PIN_CFG_NOGPIO_INT
399	},
400	{
401	.port = 23,
402	.pin = 2,
403	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
404	PIN_CFG_NOGPIO_INT,
405	},
406	{
407	.port = 23,
408	.pin = 3,
409	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
410	PIN_CFG_NOGPIO_INT,
411	},
412	{
413	.port = 23,
414	.pin = 4,
415	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
416	PIN_CFG_NOGPIO_INT,
417	},
418	{
419	.port = 23,
420	.pin = 5,
421	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
422	},
423	{
424	.port = 24,
425	.pin = 0,
426	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
427	},
428	{
429	.port = 24,
430	.pin = 1,
431	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
432	PIN_CFG_NOGPIO_INT,
433	},
434	{
435	.port = 24,
436	.pin = 2,
437	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
438	PIN_CFG_NOGPIO_INT,
439	},
440	{
441	.port = 24,
442	.pin = 3,
443	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
444	PIN_CFG_NOGPIO_INT,
445	},
446	{
447	.port = 24,
448	.pin = 4,
449	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
450	PIN_CFG_NOGPIO_INT,
451	},
452	{
453	.port = 24,
454	.pin = 5,
455	.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
456	PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
457	PIN_CFG_NOGPIO_INT,
458	},
459	};
460	#endif
461
462	static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
463	u8 pin, u8 off, u8 func)
464	{
465	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
466	unsigned long flags;
467	u32 reg;
468
469	spin_lock_irqsave(&pctrl->lock, flags);
470
471	/* Set pin to 'Non-use (Hi-Z input protection)' */
472	reg = readw(addr: pctrl->base + PM(off));
473	reg &= ~(PM_MASK << (pin * 2));
474	writew(val: reg, addr: pctrl->base + PM(off));
475
476	/* Temporarily switch to GPIO mode with PMC register */
477	reg = readb(addr: pctrl->base + PMC(off));
478	writeb(val: reg & ~BIT(pin), addr: pctrl->base + PMC(off));
479
480	/* Set the PWPR register to allow PFC register to write */
481	writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
482	writel(PWPR_PFCWE, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
483
484	/* Select Pin function mode with PFC register */
485	reg = readl(addr: pctrl->base + PFC(off));
486	reg &= ~(PFC_MASK << (pin * 4));
487	writel(val: reg | (func << (pin * 4)), addr: pctrl->base + PFC(off));
488
489	/* Set the PWPR register to be write-protected */
490	writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
491	writel(PWPR_B0WI, addr: pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
492
493	/* Switch to Peripheral pin function with PMC register */
494	reg = readb(addr: pctrl->base + PMC(off));
495	writeb(val: reg | BIT(pin), addr: pctrl->base + PMC(off));
496
497	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
498	};
499
500	static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
501	unsigned int func_selector,
502	unsigned int group_selector)
503	{
504	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
505	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
506	struct function_desc *func;
507	unsigned int i, *psel_val;
508	struct group_desc *group;
509	const unsigned int *pins;
510
511	func = pinmux_generic_get_function(pctldev, selector: func_selector);
512	if (!func)
513	return -EINVAL;
514	group = pinctrl_generic_get_group(pctldev, group_selector);
515	if (!group)
516	return -EINVAL;
517
518	psel_val = func->data;
519	pins = group->grp.pins;
520
521	for (i = 0; i < group->grp.npins; i++) {
522	u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
523	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
524	u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
525
526	dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
527	RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
528
529	rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func: psel_val[i] - hwcfg->func_base);
530	}
531
532	return 0;
533	};
534
535	static int rzg2l_map_add_config(struct pinctrl_map *map,
536	const char *group_or_pin,
537	enum pinctrl_map_type type,
538	unsigned long *configs,
539	unsigned int num_configs)
540	{
541	unsigned long *cfgs;
542
543	cfgs = kmemdup(p: configs, size: num_configs * sizeof(*cfgs),
544	GFP_KERNEL);
545	if (!cfgs)
546	return -ENOMEM;
547
548	map->type = type;
549	map->data.configs.group_or_pin = group_or_pin;
550	map->data.configs.configs = cfgs;
551	map->data.configs.num_configs = num_configs;
552
553	return 0;
554	}
555
556	static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
557	struct device_node *np,
558	struct device_node *parent,
559	struct pinctrl_map **map,
560	unsigned int *num_maps,
561	unsigned int *index)
562	{
563	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
564	struct pinctrl_map *maps = *map;
565	unsigned int nmaps = *num_maps;
566	unsigned long *configs = NULL;
567	unsigned int *pins, *psel_val;
568	unsigned int num_pinmux = 0;
569	unsigned int idx = *index;
570	unsigned int num_pins, i;
571	unsigned int num_configs;
572	struct property *pinmux;
573	struct property *prop;
574	int ret, gsel, fsel;
575	const char **pin_fn;
576	const char *name;
577	const char *pin;
578
579	pinmux = of_find_property(np, name: "pinmux", NULL);
580	if (pinmux)
581	num_pinmux = pinmux->length / sizeof(u32);
582
583	ret = of_property_count_strings(np, propname: "pins");
584	if (ret == -EINVAL) {
585	num_pins = 0;
586	} else if (ret < 0) {
587	dev_err(pctrl->dev, "Invalid pins list in DT\n");
588	return ret;
589	} else {
590	num_pins = ret;
591	}
592
593	if (!num_pinmux && !num_pins)
594	return 0;
595
596	if (num_pinmux && num_pins) {
597	dev_err(pctrl->dev,
598	"DT node must contain either a pinmux or pins and not both\n");
599	return -EINVAL;
600	}
601
602	ret = pinconf_generic_parse_dt_config(np, NULL, configs: &configs, nconfigs: &num_configs);
603	if (ret < 0)
604	return ret;
605
606	if (num_pins && !num_configs) {
607	dev_err(pctrl->dev, "DT node must contain a config\n");
608	ret = -ENODEV;
609	goto done;
610	}
611
612	if (num_pinmux) {
613	nmaps += 1;
614	if (num_configs)
615	nmaps += 1;
616	}
617
618	if (num_pins)
619	nmaps += num_pins;
620
621	maps = krealloc_array(p: maps, new_n: nmaps, new_size: sizeof(*maps), GFP_KERNEL);
622	if (!maps) {
623	ret = -ENOMEM;
624	goto done;
625	}
626
627	*map = maps;
628	*num_maps = nmaps;
629	if (num_pins) {
630	of_property_for_each_string(np, "pins", prop, pin) {
631	ret = rzg2l_map_add_config(map: &maps[idx], group_or_pin: pin,
632	type: PIN_MAP_TYPE_CONFIGS_PIN,
633	configs, num_configs);
634	if (ret < 0)
635	goto done;
636
637	idx++;
638	}
639	ret = 0;
640	goto done;
641	}
642
643	pins = devm_kcalloc(dev: pctrl->dev, n: num_pinmux, size: sizeof(*pins), GFP_KERNEL);
644	psel_val = devm_kcalloc(dev: pctrl->dev, n: num_pinmux, size: sizeof(*psel_val),
645	GFP_KERNEL);
646	pin_fn = devm_kzalloc(dev: pctrl->dev, size: sizeof(*pin_fn), GFP_KERNEL);
647	if (!pins || !psel_val || !pin_fn) {
648	ret = -ENOMEM;
649	goto done;
650	}
651
652	/* Collect pin locations and mux settings from DT properties */
653	for (i = 0; i < num_pinmux; ++i) {
654	u32 value;
655
656	ret = of_property_read_u32_index(np, propname: "pinmux", index: i, out_value: &value);
657	if (ret)
658	goto done;
659	pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
660	psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
661	}
662
663	if (parent) {
664	name = devm_kasprintf(dev: pctrl->dev, GFP_KERNEL, fmt: "%pOFn.%pOFn",
665	parent, np);
666	if (!name) {
667	ret = -ENOMEM;
668	goto done;
669	}
670	} else {
671	name = np->name;
672	}
673
674	if (num_configs) {
675	ret = rzg2l_map_add_config(map: &maps[idx], group_or_pin: name,
676	type: PIN_MAP_TYPE_CONFIGS_GROUP,
677	configs, num_configs);
678	if (ret < 0)
679	goto done;
680
681	idx++;
682	}
683
684	mutex_lock(&pctrl->mutex);
685
686	/* Register a single pin group listing all the pins we read from DT */
687	gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pins: num_pinmux, NULL);
688	if (gsel < 0) {
689	ret = gsel;
690	goto unlock;
691	}
692
693	/*
694	* Register a single group function where the 'data' is an array PSEL
695	* register values read from DT.
696	*/
697	pin_fn[0] = name;
698	fsel = pinmux_generic_add_function(pctldev, name, groups: pin_fn, num_groups: 1, data: psel_val);
699	if (fsel < 0) {
700	ret = fsel;
701	goto remove_group;
702	}
703
704	mutex_unlock(lock: &pctrl->mutex);
705
706	maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
707	maps[idx].data.mux.group = name;
708	maps[idx].data.mux.function = name;
709	idx++;
710
711	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
712	ret = 0;
713	goto done;
714
715	remove_group:
716	pinctrl_generic_remove_group(pctldev, group_selector: gsel);
717	unlock:
718	mutex_unlock(lock: &pctrl->mutex);
719	done:
720	*index = idx;
721	kfree(objp: configs);
722	return ret;
723	}
724
725	static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
726	struct pinctrl_map *map,
727	unsigned int num_maps)
728	{
729	unsigned int i;
730
731	if (!map)
732	return;
733
734	for (i = 0; i < num_maps; ++i) {
735	if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
736	map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
737	kfree(objp: map[i].data.configs.configs);
738	}
739	kfree(objp: map);
740	}
741
742	static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
743	struct device_node *np,
744	struct pinctrl_map **map,
745	unsigned int *num_maps)
746	{
747	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
748	struct device_node *child;
749	unsigned int index;
750	int ret;
751
752	*map = NULL;
753	*num_maps = 0;
754	index = 0;
755
756	for_each_child_of_node(np, child) {
757	ret = rzg2l_dt_subnode_to_map(pctldev, np: child, parent: np, map,
758	num_maps, index: &index);
759	if (ret < 0) {
760	of_node_put(node: child);
761	goto done;
762	}
763	}
764
765	if (*num_maps == 0) {
766	ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
767	num_maps, index: &index);
768	if (ret < 0)
769	goto done;
770	}
771
772	if (*num_maps)
773	return 0;
774
775	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
776	ret = -EINVAL;
777
778	done:
779	rzg2l_dt_free_map(pctldev, map: *map, num_maps: *num_maps);
780
781	return ret;
782	}
783
784	static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
785	u64 cfg, u32 port, u8 bit)
786	{
787	u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
788	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
789	u64 data;
790
791	if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
792	return -EINVAL;
793
794	data = pctrl->data->port_pin_configs[port];
795	if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
796	return -EINVAL;
797
798	return 0;
799	}
800
801	static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
802	u8 bit, u32 mask)
803	{
804	void __iomem *addr = pctrl->base + offset;
805
806	/* handle _L/_H for 32-bit register read/write */
807	if (bit >= 4) {
808	bit -= 4;
809	addr += 4;
810	}
811
812	return (readl(addr) >> (bit * 8)) & mask;
813	}
814
815	static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
816	u8 bit, u32 mask, u32 val)
817	{
818	void __iomem *addr = pctrl->base + offset;
819	unsigned long flags;
820	u32 reg;
821
822	/* handle _L/_H for 32-bit register read/write */
823	if (bit >= 4) {
824	bit -= 4;
825	addr += 4;
826	}
827
828	spin_lock_irqsave(&pctrl->lock, flags);
829	reg = readl(addr) & ~(mask << (bit * 8));
830	writel(val: reg | (val << (bit * 8)), addr);
831	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
832	}
833
834	static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
835	{
836	if (caps & PIN_CFG_IO_VMC_SD0)
837	return SD_CH(regs->sd_ch, 0);
838	if (caps & PIN_CFG_IO_VMC_SD1)
839	return SD_CH(regs->sd_ch, 1);
840	if (caps & PIN_CFG_IO_VMC_ETH0)
841	return ETH_POC(regs->eth_poc, 0);
842	if (caps & PIN_CFG_IO_VMC_ETH1)
843	return ETH_POC(regs->eth_poc, 1);
844	if (caps & PIN_CFG_IO_VMC_QSPI)
845	return QSPI;
846
847	return -EINVAL;
848	}
849
850	static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
851	{
852	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
853	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
854	int pwr_reg;
855	u8 val;
856
857	if (caps & PIN_CFG_SOFT_PS)
858	return pctrl->settings[pin].power_source;
859
860	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
861	if (pwr_reg < 0)
862	return pwr_reg;
863
864	val = readb(addr: pctrl->base + pwr_reg);
865	switch (val) {
866	case PVDD_1800:
867	return 1800;
868	case PVDD_2500:
869	return 2500;
870	case PVDD_3300:
871	return 3300;
872	default:
873	/* Should not happen. */
874	return -EINVAL;
875	}
876	}
877
878	static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
879	{
880	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
881	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
882	int pwr_reg;
883	u8 val;
884
885	if (caps & PIN_CFG_SOFT_PS) {
886	pctrl->settings[pin].power_source = ps;
887	return 0;
888	}
889
890	switch (ps) {
891	case 1800:
892	val = PVDD_1800;
893	break;
894	case 2500:
895	val = PVDD_2500;
896	break;
897	case 3300:
898	val = PVDD_3300;
899	break;
900	default:
901	return -EINVAL;
902	}
903
904	pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
905	if (pwr_reg < 0)
906	return pwr_reg;
907
908	writeb(val, addr: pctrl->base + pwr_reg);
909	pctrl->settings[pin].power_source = ps;
910
911	return 0;
912	}
913
914	static bool rzg2l_ps_is_supported(u16 ps)
915	{
916	unsigned int i;
917
918	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
919	if (available_ps[i] == ps)
920	return true;
921	}
922
923	return false;
924	}
925
926	static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
927	{
928	unsigned int i;
929
930	for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
931	if (available_ps[i] == ps)
932	break;
933	}
934
935	/*
936	* We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
937	* RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
938	*/
939	return i * RZG2L_IOLH_MAX_DS_ENTRIES;
940	}
941
942	static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
943	{
944	if (caps & PIN_CFG_IOLH_A)
945	return hwcfg->iolh_groupa_ua[val];
946
947	if (caps & PIN_CFG_IOLH_B)
948	return hwcfg->iolh_groupb_ua[val];
949
950	if (caps & PIN_CFG_IOLH_C)
951	return hwcfg->iolh_groupc_ua[val];
952
953	/* Should not happen. */
954	return 0;
955	}
956
957	static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
958	enum rzg2l_iolh_index ps_index, u16 ua)
959	{
960	const u16 *array = NULL;
961	unsigned int i;
962
963	if (caps & PIN_CFG_IOLH_A)
964	array = &hwcfg->iolh_groupa_ua[ps_index];
965
966	if (caps & PIN_CFG_IOLH_B)
967	array = &hwcfg->iolh_groupb_ua[ps_index];
968
969	if (caps & PIN_CFG_IOLH_C)
970	array = &hwcfg->iolh_groupc_ua[ps_index];
971
972	if (!array)
973	return -EINVAL;
974
975	for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
976	if (array[i] == ua)
977	return i;
978	}
979
980	return -EINVAL;
981	}
982
983	static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
984	enum rzg2l_iolh_index iolh_idx,
985	u16 ds)
986	{
987	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
988	const u16 *array = NULL;
989	unsigned int i;
990
991	if (caps & PIN_CFG_IOLH_A)
992	array = hwcfg->iolh_groupa_ua;
993
994	if (caps & PIN_CFG_IOLH_B)
995	array = hwcfg->iolh_groupb_ua;
996
997	if (caps & PIN_CFG_IOLH_C)
998	array = hwcfg->iolh_groupc_ua;
999
1000	/* Should not happen. */
1001	if (!array)
1002	return false;
1003
1004	if (!array[iolh_idx])
1005	return false;
1006
1007	for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1008	if (array[iolh_idx + i] == ds)
1009	return true;
1010	}
1011
1012	return false;
1013	}
1014
1015	static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
1016	{
1017	if (!(caps & PIN_CFG_OEN))
1018	return false;
1019
1020	if (pin > max_pin)
1021	return false;
1022
1023	return true;
1024	}
1025
1026	static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
1027	{
1028	if (pin)
1029	pin *= 2;
1030
1031	if (offset / RZG2L_PINS_PER_PORT == max_port)
1032	pin += 1;
1033
1034	return pin;
1035	}
1036
1037	static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1038	{
1039	u8 max_port = pctrl->data->hwcfg->oen_max_port;
1040	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1041	u8 bit;
1042
1043	if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1044	return 0;
1045
1046	bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1047
1048	return !(readb(addr: pctrl->base + ETH_MODE) & BIT(bit));
1049	}
1050
1051	static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1052	{
1053	u8 max_port = pctrl->data->hwcfg->oen_max_port;
1054	u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1055	unsigned long flags;
1056	u8 val, bit;
1057
1058	if (!rzg2l_oen_is_supported(caps, pin, max_pin))
1059	return -EINVAL;
1060
1061	bit = rzg2l_pin_to_oen_bit(offset, pin, max_port);
1062
1063	spin_lock_irqsave(&pctrl->lock, flags);
1064	val = readb(addr: pctrl->base + ETH_MODE);
1065	if (oen)
1066	val &= ~BIT(bit);
1067	else
1068	val |= BIT(bit);
1069	writeb(val, addr: pctrl->base + ETH_MODE);
1070	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1071
1072	return 0;
1073	}
1074
1075	static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
1076	unsigned int _pin,
1077	unsigned long *config)
1078	{
1079	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1080	enum pin_config_param param = pinconf_to_config_param(config: *config);
1081	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1082	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1083	u64 *pin_data = pin->drv_data;
1084	unsigned int arg = 0;
1085	u32 off, cfg;
1086	int ret;
1087	u8 bit;
1088
1089	if (!pin_data)
1090	return -EINVAL;
1091
1092	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1093	cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1094	if (*pin_data & RZG2L_SINGLE_PIN) {
1095	bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1096	} else {
1097	bit = RZG2L_PIN_ID_TO_PIN(_pin);
1098
1099	if (rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1100	return -EINVAL;
1101	}
1102
1103	switch (param) {
1104	case PIN_CONFIG_INPUT_ENABLE:
1105	if (!(cfg & PIN_CFG_IEN))
1106	return -EINVAL;
1107	arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
1108	if (!arg)
1109	return -EINVAL;
1110	break;
1111
1112	case PIN_CONFIG_OUTPUT_ENABLE:
1113	arg = rzg2l_read_oen(pctrl, caps: cfg, offset: _pin, pin: bit);
1114	if (!arg)
1115	return -EINVAL;
1116	break;
1117
1118	case PIN_CONFIG_POWER_SOURCE:
1119	ret = rzg2l_get_power_source(pctrl, pin: _pin, caps: cfg);
1120	if (ret < 0)
1121	return ret;
1122	arg = ret;
1123	break;
1124
1125	case PIN_CONFIG_DRIVE_STRENGTH: {
1126	unsigned int index;
1127
1128	if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1129	return -EINVAL;
1130
1131	index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1132	/*
1133	* Drive strenght mA is supported only by group A and only
1134	* for 3V3 port source.
1135	*/
1136	arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
1137	break;
1138	}
1139
1140	case PIN_CONFIG_DRIVE_STRENGTH_UA: {
1141	enum rzg2l_iolh_index iolh_idx;
1142	u8 val;
1143
1144	if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1145	!hwcfg->drive_strength_ua)
1146	return -EINVAL;
1147
1148	ret = rzg2l_get_power_source(pctrl, pin: _pin, caps: cfg);
1149	if (ret < 0)
1150	return ret;
1151	iolh_idx = rzg2l_ps_to_iolh_idx(ps: ret);
1152	val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1153	arg = rzg2l_iolh_val_to_ua(hwcfg, caps: cfg, val: iolh_idx + val);
1154	break;
1155	}
1156
1157	case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
1158	unsigned int index;
1159
1160	if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1161	return -EINVAL;
1162
1163	index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1164	arg = hwcfg->iolh_groupb_oi[index];
1165	break;
1166	}
1167
1168	default:
1169	return -ENOTSUPP;
1170	}
1171
1172	*config = pinconf_to_config_packed(param, argument: arg);
1173
1174	return 0;
1175	};
1176
1177	static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
1178	unsigned int _pin,
1179	unsigned long *_configs,
1180	unsigned int num_configs)
1181	{
1182	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1183	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1184	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1185	struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
1186	u64 *pin_data = pin->drv_data;
1187	enum pin_config_param param;
1188	unsigned int i, arg, index;
1189	u32 cfg, off;
1190	int ret;
1191	u8 bit;
1192
1193	if (!pin_data)
1194	return -EINVAL;
1195
1196	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1197	cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1198	if (*pin_data & RZG2L_SINGLE_PIN) {
1199	bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1200	} else {
1201	bit = RZG2L_PIN_ID_TO_PIN(_pin);
1202
1203	if (rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1204	return -EINVAL;
1205	}
1206
1207	for (i = 0; i < num_configs; i++) {
1208	param = pinconf_to_config_param(config: _configs[i]);
1209	switch (param) {
1210	case PIN_CONFIG_INPUT_ENABLE:
1211	arg = pinconf_to_config_argument(config: _configs[i]);
1212
1213	if (!(cfg & PIN_CFG_IEN))
1214	return -EINVAL;
1215
1216	rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, val: !!arg);
1217	break;
1218
1219	case PIN_CONFIG_OUTPUT_ENABLE:
1220	arg = pinconf_to_config_argument(config: _configs[i]);
1221	ret = rzg2l_write_oen(pctrl, caps: cfg, offset: _pin, pin: bit, oen: !!arg);
1222	if (ret)
1223	return ret;
1224	break;
1225
1226	case PIN_CONFIG_POWER_SOURCE:
1227	settings.power_source = pinconf_to_config_argument(config: _configs[i]);
1228	break;
1229
1230	case PIN_CONFIG_DRIVE_STRENGTH:
1231	arg = pinconf_to_config_argument(config: _configs[i]);
1232
1233	if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1234	return -EINVAL;
1235
1236	for (index = RZG2L_IOLH_IDX_3V3;
1237	index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
1238	if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
1239	break;
1240	}
1241	if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
1242	return -EINVAL;
1243
1244	rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val: index);
1245	break;
1246
1247	case PIN_CONFIG_DRIVE_STRENGTH_UA:
1248	if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1249	!hwcfg->drive_strength_ua)
1250	return -EINVAL;
1251
1252	settings.drive_strength_ua = pinconf_to_config_argument(config: _configs[i]);
1253	break;
1254
1255	case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1256	arg = pinconf_to_config_argument(config: _configs[i]);
1257
1258	if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1259	return -EINVAL;
1260
1261	for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
1262	if (arg == hwcfg->iolh_groupb_oi[index])
1263	break;
1264	}
1265	if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
1266	return -EINVAL;
1267
1268	rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val: index);
1269	break;
1270
1271	default:
1272	return -EOPNOTSUPP;
1273	}
1274	}
1275
1276	/* Apply power source. */
1277	if (settings.power_source != pctrl->settings[_pin].power_source) {
1278	ret = rzg2l_ps_is_supported(ps: settings.power_source);
1279	if (!ret)
1280	return -EINVAL;
1281
1282	/* Apply power source. */
1283	ret = rzg2l_set_power_source(pctrl, pin: _pin, caps: cfg, ps: settings.power_source);
1284	if (ret)
1285	return ret;
1286	}
1287
1288	/* Apply drive strength. */
1289	if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
1290	enum rzg2l_iolh_index iolh_idx;
1291	int val;
1292
1293	iolh_idx = rzg2l_ps_to_iolh_idx(ps: settings.power_source);
1294	ret = rzg2l_ds_is_supported(pctrl, caps: cfg, iolh_idx,
1295	ds: settings.drive_strength_ua);
1296	if (!ret)
1297	return -EINVAL;
1298
1299	/* Get register value for this PS/DS tuple. */
1300	val = rzg2l_iolh_ua_to_val(hwcfg, caps: cfg, ps_index: iolh_idx, ua: settings.drive_strength_ua);
1301	if (val < 0)
1302	return val;
1303
1304	/* Apply drive strength. */
1305	rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
1306	pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
1307	}
1308
1309	return 0;
1310	}
1311
1312	static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
1313	unsigned int group,
1314	unsigned long *configs,
1315	unsigned int num_configs)
1316	{
1317	const unsigned int *pins;
1318	unsigned int i, npins;
1319	int ret;
1320
1321	ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
1322	if (ret)
1323	return ret;
1324
1325	for (i = 0; i < npins; i++) {
1326	ret = rzg2l_pinctrl_pinconf_set(pctldev, pin: pins[i], configs: configs,
1327	num_configs);
1328	if (ret)
1329	return ret;
1330	}
1331
1332	return 0;
1333	};
1334
1335	static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
1336	unsigned int group,
1337	unsigned long *config)
1338	{
1339	const unsigned int *pins;
1340	unsigned int i, npins, prev_config = 0;
1341	int ret;
1342
1343	ret = pinctrl_generic_get_group_pins(pctldev, group_selector: group, pins: &pins, npins: &npins);
1344	if (ret)
1345	return ret;
1346
1347	for (i = 0; i < npins; i++) {
1348	ret = rzg2l_pinctrl_pinconf_get(pctldev, pin: pins[i], config);
1349	if (ret)
1350	return ret;
1351
1352	/* Check config matching between to pin */
1353	if (i && prev_config != *config)
1354	return -EOPNOTSUPP;
1355
1356	prev_config = *config;
1357	}
1358
1359	return 0;
1360	};
1361
1362	static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
1363	.get_groups_count = pinctrl_generic_get_group_count,
1364	.get_group_name = pinctrl_generic_get_group_name,
1365	.get_group_pins = pinctrl_generic_get_group_pins,
1366	.dt_node_to_map = rzg2l_dt_node_to_map,
1367	.dt_free_map = rzg2l_dt_free_map,
1368	};
1369
1370	static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
1371	.get_functions_count = pinmux_generic_get_function_count,
1372	.get_function_name = pinmux_generic_get_function_name,
1373	.get_function_groups = pinmux_generic_get_function_groups,
1374	.set_mux = rzg2l_pinctrl_set_mux,
1375	.strict = true,
1376	};
1377
1378	static const struct pinconf_ops rzg2l_pinctrl_confops = {
1379	.is_generic = true,
1380	.pin_config_get = rzg2l_pinctrl_pinconf_get,
1381	.pin_config_set = rzg2l_pinctrl_pinconf_set,
1382	.pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
1383	.pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
1384	.pin_config_config_dbg_show = pinconf_generic_dump_config,
1385	};
1386
1387	static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
1388	{
1389	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1390	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1391	u64 *pin_data = pin_desc->drv_data;
1392	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1393	u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1394	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1395	unsigned long flags;
1396	u8 reg8;
1397	int ret;
1398
1399	ret = rzg2l_validate_gpio_pin(pctrl, cfg: *pin_data, port, bit);
1400	if (ret)
1401	return ret;
1402
1403	ret = pinctrl_gpio_request(gc: chip, offset);
1404	if (ret)
1405	return ret;
1406
1407	spin_lock_irqsave(&pctrl->lock, flags);
1408
1409	/* Select GPIO mode in PMC Register */
1410	reg8 = readb(addr: pctrl->base + PMC(off));
1411	reg8 &= ~BIT(bit);
1412	writeb(val: reg8, addr: pctrl->base + PMC(off));
1413
1414	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1415
1416	return 0;
1417	}
1418
1419	static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
1420	bool output)
1421	{
1422	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1423	u64 *pin_data = pin_desc->drv_data;
1424	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1425	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1426	unsigned long flags;
1427	u16 reg16;
1428
1429	spin_lock_irqsave(&pctrl->lock, flags);
1430
1431	reg16 = readw(addr: pctrl->base + PM(off));
1432	reg16 &= ~(PM_MASK << (bit * 2));
1433
1434	reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
1435	writew(val: reg16, addr: pctrl->base + PM(off));
1436
1437	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1438	}
1439
1440	static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1441	{
1442	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1443	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1444	u64 *pin_data = pin_desc->drv_data;
1445	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1446	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1447
1448	if (!(readb(addr: pctrl->base + PMC(off)) & BIT(bit))) {
1449	u16 reg16;
1450
1451	reg16 = readw(addr: pctrl->base + PM(off));
1452	reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1453	if (reg16 == PM_OUTPUT)
1454	return GPIO_LINE_DIRECTION_OUT;
1455	}
1456
1457	return GPIO_LINE_DIRECTION_IN;
1458	}
1459
1460	static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
1461	unsigned int offset)
1462	{
1463	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1464
1465	rzg2l_gpio_set_direction(pctrl, offset, output: false);
1466
1467	return 0;
1468	}
1469
1470	static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1471	int value)
1472	{
1473	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1474	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1475	u64 *pin_data = pin_desc->drv_data;
1476	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1477	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1478	unsigned long flags;
1479	u8 reg8;
1480
1481	spin_lock_irqsave(&pctrl->lock, flags);
1482
1483	reg8 = readb(addr: pctrl->base + P(off));
1484
1485	if (value)
1486	writeb(val: reg8 | BIT(bit), addr: pctrl->base + P(off));
1487	else
1488	writeb(val: reg8 & ~BIT(bit), addr: pctrl->base + P(off));
1489
1490	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1491	}
1492
1493	static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
1494	unsigned int offset, int value)
1495	{
1496	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1497
1498	rzg2l_gpio_set(chip, offset, value);
1499	rzg2l_gpio_set_direction(pctrl, offset, output: true);
1500
1501	return 0;
1502	}
1503
1504	static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
1505	{
1506	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1507	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1508	u64 *pin_data = pin_desc->drv_data;
1509	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1510	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1511	u16 reg16;
1512
1513	reg16 = readw(addr: pctrl->base + PM(off));
1514	reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1515
1516	if (reg16 == PM_INPUT)
1517	return !!(readb(addr: pctrl->base + PIN(off)) & BIT(bit));
1518	else if (reg16 == PM_OUTPUT)
1519	return !!(readb(addr: pctrl->base + P(off)) & BIT(bit));
1520	else
1521	return -EINVAL;
1522	}
1523
1524	static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
1525	{
1526	unsigned int virq;
1527
1528	pinctrl_gpio_free(gc: chip, offset);
1529
1530	virq = irq_find_mapping(domain: chip->irq.domain, hwirq: offset);
1531	if (virq)
1532	irq_dispose_mapping(virq);
1533
1534	/*
1535	* Set the GPIO as an input to ensure that the next GPIO request won't
1536	* drive the GPIO pin as an output.
1537	*/
1538	rzg2l_gpio_direction_input(chip, offset);
1539	}
1540
1541	static const char * const rzg2l_gpio_names[] = {
1542	"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
1543	"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
1544	"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
1545	"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
1546	"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
1547	"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
1548	"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
1549	"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
1550	"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
1551	"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
1552	"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
1553	"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
1554	"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
1555	"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
1556	"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
1557	"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
1558	"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
1559	"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
1560	"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
1561	"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
1562	"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
1563	"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
1564	"P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
1565	"P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
1566	"P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
1567	"P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
1568	"P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
1569	"P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
1570	"P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
1571	"P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
1572	"P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
1573	"P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
1574	"P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
1575	"P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
1576	"P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
1577	"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
1578	"P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
1579	"P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
1580	"P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
1581	"P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
1582	"P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
1583	"P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
1584	"P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
1585	"P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
1586	"P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
1587	"P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
1588	"P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
1589	"P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
1590	"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
1591	};
1592
1593	static const u64 r9a07g044_gpio_configs[] = {
1594	RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
1595	RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
1596	RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
1597	RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
1598	RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
1599	RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
1600	RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
1601	RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
1602	RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
1603	RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
1604	RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1605	RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1606	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1607	RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1608	RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1609	RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1610	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1611	RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1612	RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1613	RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1614	RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1615	RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1616	RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1617	RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1618	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1619	RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1620	RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1621	RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1622	RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1623	RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1624	RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1625	RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1626	RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1627	RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1628	RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1629	RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1630	RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1631	RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1632	RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1633	RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1634	RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1635	RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1636	RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1637	RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1638	RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1639	RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1640	RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1641	RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1642	RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1643	};
1644
1645	static const u64 r9a07g043_gpio_configs[] = {
1646	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1647	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1648	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1649	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1650	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1651	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1652	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1653	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1654	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1655	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1656	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1657	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1658	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1659	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1660	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1661	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1662	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1663	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1664	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1665	#ifdef CONFIG_RISCV
1666	/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1667	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1668	PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1669	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1670	RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */
1671	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1672	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
1673	RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1674	PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1675	RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */
1676	RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */
1677	RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |
1678	PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
1679	PIN_CFG_NOGPIO_INT), /* P25 */
1680	0x0, /* P26 */
1681	0x0, /* P27 */
1682	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */
1683	#endif
1684	};
1685
1686	static const u64 r9a08g045_gpio_configs[] = {
1687	RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1688	RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1689	PIN_CFG_IO_VMC_ETH0)) |
1690	PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */
1691	RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1692	PIN_CFG_IO_VMC_ETH0)), /* P2 */
1693	RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1694	PIN_CFG_IO_VMC_ETH0)), /* P3 */
1695	RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1696	PIN_CFG_IO_VMC_ETH0)), /* P4 */
1697	RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1698	RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1699	RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1700	PIN_CFG_IO_VMC_ETH1)) |
1701	PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */
1702	RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1703	PIN_CFG_IO_VMC_ETH1)), /* P8 */
1704	RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1705	PIN_CFG_IO_VMC_ETH1)), /* P9 */
1706	RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1707	PIN_CFG_IO_VMC_ETH1)), /* P10 */
1708	RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
1709	RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
1710	RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
1711	RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
1712	RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
1713	RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
1714	RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
1715	RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
1716	};
1717
1718	static const struct {
1719	struct rzg2l_dedicated_configs common[35];
1720	struct rzg2l_dedicated_configs rzg2l_pins[7];
1721	} rzg2l_dedicated_pins = {
1722	.common = {
1723	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
1724	(PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
1725	{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
1726	(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1727	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
1728	(PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1729	{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
1730	{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
1731	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
1732	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1733	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
1734	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1735	{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
1736	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1737	{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
1738	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1739	{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
1740	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1741	{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
1742	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1743	{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
1744	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1745	{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
1746	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1747	{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
1748	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1749	{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
1750	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1751	{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
1752	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1753	{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
1754	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
1755	{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
1756	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1757	{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
1758	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1759	{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
1760	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1761	{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
1762	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1763	{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
1764	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1765	{ "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
1766	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1767	{ "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
1768	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1769	{ "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
1770	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1771	{ "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
1772	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1773	{ "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
1774	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1775	{ "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
1776	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1777	{ "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1778	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1779	{ "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1780	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1781	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
1782	{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
1783	{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
1784	{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
1785	{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
1786	},
1787	.rzg2l_pins = {
1788	{ "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1789	{ "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
1790	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1791	{ "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
1792	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1793	{ "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
1794	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1795	{ "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
1796	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1797	{ "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
1798	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1799	{ "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1800	(PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1801	}
1802	};
1803
1804	static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
1805	{ "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
1806	PIN_CFG_FILCLKSEL)) },
1807	{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
1808	PIN_CFG_SOFT_PS)) },
1809	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
1810	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
1811	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1812	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1813	PIN_CFG_IO_VMC_SD0)) },
1814	{ "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
1815	{ "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1816	PIN_CFG_IO_VMC_SD0)) },
1817	{ "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1818	PIN_CFG_IO_VMC_SD0)) },
1819	{ "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1820	PIN_CFG_IO_VMC_SD0)) },
1821	{ "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1822	PIN_CFG_IO_VMC_SD0)) },
1823	{ "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1824	PIN_CFG_IO_VMC_SD0)) },
1825	{ "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1826	PIN_CFG_IO_VMC_SD0)) },
1827	{ "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1828	PIN_CFG_IO_VMC_SD0)) },
1829	{ "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1830	PIN_CFG_IO_VMC_SD0)) },
1831	{ "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
1832	{ "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1833	PIN_CFG_IO_VMC_SD1)) },
1834	{ "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1835	PIN_CFG_IO_VMC_SD1)) },
1836	{ "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1837	PIN_CFG_IO_VMC_SD1)) },
1838	{ "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1839	PIN_CFG_IO_VMC_SD1)) },
1840	{ "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
1841	PIN_CFG_IO_VMC_SD1)) },
1842	};
1843
1844	static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
1845	{
1846	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
1847	const struct rzg2l_pinctrl_data *data = pctrl->data;
1848	u64 *pin_data = pin_desc->drv_data;
1849	unsigned int gpioint;
1850	unsigned int i;
1851	u32 port, bit;
1852
1853	if (*pin_data & PIN_CFG_NOGPIO_INT)
1854	return -EINVAL;
1855
1856	port = virq / 8;
1857	bit = virq % 8;
1858
1859	if (port >= data->n_ports ||
1860	bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
1861	return -EINVAL;
1862
1863	gpioint = bit;
1864	for (i = 0; i < port; i++)
1865	gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));
1866
1867	return gpioint;
1868	}
1869
1870	static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,
1871	unsigned int hwirq, bool enable)
1872	{
1873	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
1874	u64 *pin_data = pin_desc->drv_data;
1875	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1876	u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
1877	unsigned long flags;
1878	void __iomem *addr;
1879
1880	addr = pctrl->base + ISEL(off);
1881	if (bit >= 4) {
1882	bit -= 4;
1883	addr += 4;
1884	}
1885
1886	spin_lock_irqsave(&pctrl->lock, flags);
1887	if (enable)
1888	writel(readl(addr) | BIT(bit * 8), addr);
1889	else
1890	writel(readl(addr) & ~BIT(bit * 8), addr);
1891	spin_unlock_irqrestore(lock: &pctrl->lock, flags);
1892	}
1893
1894	static void rzg2l_gpio_irq_disable(struct irq_data *d)
1895	{
1896	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1897	unsigned int hwirq = irqd_to_hwirq(d);
1898
1899	irq_chip_disable_parent(data: d);
1900	gpiochip_disable_irq(gc, offset: hwirq);
1901	}
1902
1903	static void rzg2l_gpio_irq_enable(struct irq_data *d)
1904	{
1905	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1906	unsigned int hwirq = irqd_to_hwirq(d);
1907
1908	gpiochip_enable_irq(gc, offset: hwirq);
1909	irq_chip_enable_parent(data: d);
1910	}
1911
1912	static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1913	{
1914	return irq_chip_set_type_parent(data: d, type);
1915	}
1916
1917	static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
1918	{
1919	irq_chip_eoi_parent(data: d);
1920	}
1921
1922	static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
1923	{
1924	struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data);
1925
1926	seq_printf(m: p, fmt: dev_name(dev: gc->parent));
1927	}
1928
1929	static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
1930	{
1931	struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data);
1932	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
1933	int ret;
1934
1935	/* It should not happen. */
1936	if (!data->parent_data)
1937	return -EOPNOTSUPP;
1938
1939	ret = irq_chip_set_wake_parent(data, on);
1940	if (ret)
1941	return ret;
1942
1943	if (on)
1944	atomic_inc(v: &pctrl->wakeup_path);
1945	else
1946	atomic_dec(v: &pctrl->wakeup_path);
1947
1948	return 0;
1949	}
1950
1951	static const struct irq_chip rzg2l_gpio_irqchip = {
1952	.name = "rzg2l-gpio",
1953	.irq_disable = rzg2l_gpio_irq_disable,
1954	.irq_enable = rzg2l_gpio_irq_enable,
1955	.irq_mask = irq_chip_mask_parent,
1956	.irq_unmask = irq_chip_unmask_parent,
1957	.irq_set_type = rzg2l_gpio_irq_set_type,
1958	.irq_eoi = rzg2l_gpio_irqc_eoi,
1959	.irq_print_chip = rzg2l_gpio_irq_print_chip,
1960	.irq_set_affinity = irq_chip_set_affinity_parent,
1961	.irq_set_wake = rzg2l_gpio_irq_set_wake,
1962	.flags = IRQCHIP_IMMUTABLE,
1963	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1964	};
1965
1966	static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset)
1967	{
1968	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc: chip);
1969	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1970	u64 *pin_data = pin_desc->drv_data;
1971	u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1972	u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1973	u8 reg8;
1974	int ret;
1975
1976	reg8 = readb(addr: pctrl->base + PMC(off));
1977	if (reg8 & BIT(bit)) {
1978	ret = rzg2l_gpio_request(chip, offset);
1979	if (ret)
1980	return ret;
1981	}
1982
1983	return rzg2l_gpio_direction_input(chip, offset);
1984	}
1985
1986	static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
1987	unsigned int child,
1988	unsigned int child_type,
1989	unsigned int *parent,
1990	unsigned int *parent_type)
1991	{
1992	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
1993	unsigned long flags;
1994	int gpioint, irq;
1995	int ret;
1996
1997	gpioint = rzg2l_gpio_get_gpioint(virq: child, pctrl);
1998	if (gpioint < 0)
1999	return gpioint;
2000
2001	ret = rzg2l_gpio_interrupt_input_mode(chip: gc, offset: child);
2002	if (ret)
2003	return ret;
2004
2005	spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2006	irq = bitmap_find_free_region(bitmap: pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, order: get_order(size: 1));
2007	spin_unlock_irqrestore(lock: &pctrl->bitmap_lock, flags);
2008	if (irq < 0) {
2009	ret = -ENOSPC;
2010	goto err;
2011	}
2012
2013	rzg2l_gpio_irq_endisable(pctrl, hwirq: child, enable: true);
2014	pctrl->hwirq[irq] = child;
2015	irq += RZG2L_TINT_IRQ_START_INDEX;
2016
2017	/* All these interrupts are level high in the CPU */
2018	*parent_type = IRQ_TYPE_LEVEL_HIGH;
2019	*parent = RZG2L_PACK_HWIRQ(gpioint, irq);
2020	return 0;
2021
2022	err:
2023	rzg2l_gpio_free(chip: gc, offset: child);
2024	return ret;
2025	}
2026
2027	static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
2028	union gpio_irq_fwspec *gfwspec,
2029	unsigned int parent_hwirq,
2030	unsigned int parent_type)
2031	{
2032	struct irq_fwspec *fwspec = &gfwspec->fwspec;
2033
2034	fwspec->fwnode = chip->irq.parent_domain->fwnode;
2035	fwspec->param_count = 2;
2036	fwspec->param[0] = parent_hwirq;
2037	fwspec->param[1] = parent_type;
2038
2039	return 0;
2040	}
2041
2042	static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
2043	{
2044	struct irq_domain *domain = pctrl->gpio_chip.irq.domain;
2045
2046	for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2047	struct irq_data *data;
2048	unsigned int virq;
2049
2050	if (!pctrl->hwirq[i])
2051	continue;
2052
2053	virq = irq_find_mapping(domain, hwirq: pctrl->hwirq[i]);
2054	if (!virq) {
2055	dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n",
2056	pctrl->hwirq[i]);
2057	continue;
2058	}
2059
2060	data = irq_domain_get_irq_data(domain, virq);
2061	if (!data) {
2062	dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq);
2063	continue;
2064	}
2065
2066	if (!irqd_irq_disabled(d: data))
2067	rzg2l_gpio_irq_enable(d: data);
2068	}
2069	}
2070
2071	static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2072	unsigned int nr_irqs)
2073	{
2074	struct irq_data *d;
2075
2076	d = irq_domain_get_irq_data(domain, virq);
2077	if (d) {
2078	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2079	struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2080	irq_hw_number_t hwirq = irqd_to_hwirq(d);
2081	unsigned long flags;
2082	unsigned int i;
2083
2084	for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2085	if (pctrl->hwirq[i] == hwirq) {
2086	rzg2l_gpio_irq_endisable(pctrl, hwirq, enable: false);
2087	rzg2l_gpio_free(chip: gc, offset: hwirq);
2088	spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2089	bitmap_release_region(bitmap: pctrl->tint_slot, pos: i, order: get_order(size: 1));
2090	spin_unlock_irqrestore(lock: &pctrl->bitmap_lock, flags);
2091	pctrl->hwirq[i] = 0;
2092	break;
2093	}
2094	}
2095	}
2096	irq_domain_free_irqs_common(domain, virq, nr_irqs);
2097	}
2098
2099	static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
2100	unsigned long *valid_mask,
2101	unsigned int ngpios)
2102	{
2103	struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2104	struct gpio_chip *chip = &pctrl->gpio_chip;
2105	unsigned int offset;
2106
2107	/* Forbid unused lines to be mapped as IRQs */
2108	for (offset = 0; offset < chip->ngpio; offset++) {
2109	u32 port, bit;
2110
2111	port = offset / 8;
2112	bit = offset % 8;
2113
2114	if (port >= pctrl->data->n_ports ||
2115	bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,
2116	pctrl->data->port_pin_configs[port])))
2117	clear_bit(nr: offset, addr: valid_mask);
2118	}
2119	}
2120
2121	static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
2122	{
2123	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2124	struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache;
2125
2126	cache = devm_kzalloc(dev: pctrl->dev, size: sizeof(*cache), GFP_KERNEL);
2127	if (!cache)
2128	return -ENOMEM;
2129
2130	dedicated_cache = devm_kzalloc(dev: pctrl->dev, size: sizeof(*dedicated_cache), GFP_KERNEL);
2131	if (!dedicated_cache)
2132	return -ENOMEM;
2133
2134	cache->p = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->p), GFP_KERNEL);
2135	if (!cache->p)
2136	return -ENOMEM;
2137
2138	cache->pm = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pm), GFP_KERNEL);
2139	if (!cache->pm)
2140	return -ENOMEM;
2141
2142	cache->pmc = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pmc), GFP_KERNEL);
2143	if (!cache->pmc)
2144	return -ENOMEM;
2145
2146	cache->pfc = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->pfc), GFP_KERNEL);
2147	if (!cache->pfc)
2148	return -ENOMEM;
2149
2150	for (u8 i = 0; i < 2; i++) {
2151	u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
2152
2153	cache->iolh[i] = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->iolh[i]),
2154	GFP_KERNEL);
2155	if (!cache->iolh[i])
2156	return -ENOMEM;
2157
2158	cache->ien[i] = devm_kcalloc(dev: pctrl->dev, n: nports, size: sizeof(*cache->ien[i]),
2159	GFP_KERNEL);
2160	if (!cache->ien[i])
2161	return -ENOMEM;
2162
2163	/* Allocate dedicated cache. */
2164	dedicated_cache->iolh[i] = devm_kcalloc(dev: pctrl->dev, n: n_dedicated_pins,
2165	size: sizeof(*dedicated_cache->iolh[i]),
2166	GFP_KERNEL);
2167	if (!dedicated_cache->iolh[i])
2168	return -ENOMEM;
2169
2170	dedicated_cache->ien[i] = devm_kcalloc(dev: pctrl->dev, n: n_dedicated_pins,
2171	size: sizeof(*dedicated_cache->ien[i]),
2172	GFP_KERNEL);
2173	if (!dedicated_cache->ien[i])
2174	return -ENOMEM;
2175	}
2176
2177	pctrl->cache = cache;
2178	pctrl->dedicated_cache = dedicated_cache;
2179
2180	return 0;
2181	}
2182
2183	static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
2184	{
2185	struct device_node *np = pctrl->dev->of_node;
2186	struct gpio_chip *chip = &pctrl->gpio_chip;
2187	const char *name = dev_name(dev: pctrl->dev);
2188	struct irq_domain *parent_domain;
2189	struct of_phandle_args of_args;
2190	struct device_node *parent_np;
2191	struct gpio_irq_chip *girq;
2192	int ret;
2193
2194	parent_np = of_irq_find_parent(child: np);
2195	if (!parent_np)
2196	return -ENXIO;
2197
2198	parent_domain = irq_find_host(node: parent_np);
2199	of_node_put(node: parent_np);
2200	if (!parent_domain)
2201	return -EPROBE_DEFER;
2202
2203	ret = of_parse_phandle_with_fixed_args(np, list_name: "gpio-ranges", cell_count: 3, index: 0, out_args: &of_args);
2204	if (ret) {
2205	dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
2206	return ret;
2207	}
2208
2209	if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
2210	of_args.args[2] != pctrl->data->n_port_pins) {
2211	dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
2212	return -EINVAL;
2213	}
2214
2215	chip->names = pctrl->data->port_pins;
2216	chip->request = rzg2l_gpio_request;
2217	chip->free = rzg2l_gpio_free;
2218	chip->get_direction = rzg2l_gpio_get_direction;
2219	chip->direction_input = rzg2l_gpio_direction_input;
2220	chip->direction_output = rzg2l_gpio_direction_output;
2221	chip->get = rzg2l_gpio_get;
2222	chip->set = rzg2l_gpio_set;
2223	chip->label = name;
2224	chip->parent = pctrl->dev;
2225	chip->owner = THIS_MODULE;
2226	chip->base = -1;
2227	chip->ngpio = of_args.args[2];
2228
2229	girq = &chip->irq;
2230	gpio_irq_chip_set_chip(girq, chip: &rzg2l_gpio_irqchip);
2231	girq->fwnode = of_node_to_fwnode(node: np);
2232	girq->parent_domain = parent_domain;
2233	girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
2234	girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
2235	girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
2236	girq->init_valid_mask = rzg2l_init_irq_valid_mask;
2237
2238	pctrl->gpio_range.id = 0;
2239	pctrl->gpio_range.pin_base = 0;
2240	pctrl->gpio_range.base = 0;
2241	pctrl->gpio_range.npins = chip->ngpio;
2242	pctrl->gpio_range.name = chip->label;
2243	pctrl->gpio_range.gc = chip;
2244	ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
2245	if (ret) {
2246	dev_err(pctrl->dev, "failed to add GPIO controller\n");
2247	return ret;
2248	}
2249
2250	dev_dbg(pctrl->dev, "Registered gpio controller\n");
2251
2252	return 0;
2253	}
2254
2255	static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
2256	{
2257	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2258	struct pinctrl_pin_desc *pins;
2259	unsigned int i, j;
2260	u64 *pin_data;
2261	int ret;
2262
2263	pctrl->desc.name = DRV_NAME;
2264	pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
2265	pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
2266	pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
2267	pctrl->desc.confops = &rzg2l_pinctrl_confops;
2268	pctrl->desc.owner = THIS_MODULE;
2269
2270	pins = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins, size: sizeof(*pins), GFP_KERNEL);
2271	if (!pins)
2272	return -ENOMEM;
2273
2274	pin_data = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins,
2275	size: sizeof(*pin_data), GFP_KERNEL);
2276	if (!pin_data)
2277	return -ENOMEM;
2278
2279	pctrl->pins = pins;
2280	pctrl->desc.pins = pins;
2281
2282	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
2283	pins[i].number = i;
2284	pins[i].name = pctrl->data->port_pins[i];
2285	if (i && !(i % RZG2L_PINS_PER_PORT))
2286	j++;
2287	pin_data[i] = pctrl->data->port_pin_configs[j];
2288	#ifdef CONFIG_RISCV
2289	if (pin_data[i] & PIN_CFG_VARIABLE)
2290	pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
2291	pin_data[i],
2292	j,
2293	i % RZG2L_PINS_PER_PORT);
2294	#endif
2295	pins[i].drv_data = &pin_data[i];
2296	}
2297
2298	for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
2299	unsigned int index = pctrl->data->n_port_pins + i;
2300
2301	pins[index].number = index;
2302	pins[index].name = pctrl->data->dedicated_pins[i].name;
2303	pin_data[index] = pctrl->data->dedicated_pins[i].config;
2304	pins[index].drv_data = &pin_data[index];
2305	}
2306
2307	pctrl->settings = devm_kcalloc(dev: pctrl->dev, n: pctrl->desc.npins, size: sizeof(*pctrl->settings),
2308	GFP_KERNEL);
2309	if (!pctrl->settings)
2310	return -ENOMEM;
2311
2312	for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
2313	if (pin_data[i] & PIN_CFG_SOFT_PS) {
2314	pctrl->settings[i].power_source = 3300;
2315	} else {
2316	ret = rzg2l_get_power_source(pctrl, pin: i, caps: pin_data[i]);
2317	if (ret < 0)
2318	continue;
2319	pctrl->settings[i].power_source = ret;
2320	}
2321	}
2322
2323	ret = rzg2l_pinctrl_reg_cache_alloc(pctrl);
2324	if (ret)
2325	return ret;
2326
2327	ret = devm_pinctrl_register_and_init(dev: pctrl->dev, pctldesc: &pctrl->desc, driver_data: pctrl,
2328	pctldev: &pctrl->pctl);
2329	if (ret) {
2330	dev_err(pctrl->dev, "pinctrl registration failed\n");
2331	return ret;
2332	}
2333
2334	ret = pinctrl_enable(pctldev: pctrl->pctl);
2335	if (ret) {
2336	dev_err(pctrl->dev, "pinctrl enable failed\n");
2337	return ret;
2338	}
2339
2340	ret = rzg2l_gpio_register(pctrl);
2341	if (ret) {
2342	dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
2343	return ret;
2344	}
2345
2346	return 0;
2347	}
2348
2349	static int rzg2l_pinctrl_probe(struct platform_device *pdev)
2350	{
2351	struct rzg2l_pinctrl *pctrl;
2352	int ret;
2353
2354	BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
2355	ARRAY_SIZE(rzg2l_gpio_names));
2356
2357	BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
2358	ARRAY_SIZE(rzg2l_gpio_names));
2359
2360	BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2361	ARRAY_SIZE(rzg2l_gpio_names));
2362
2363	pctrl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctrl), GFP_KERNEL);
2364	if (!pctrl)
2365	return -ENOMEM;
2366
2367	pctrl->dev = &pdev->dev;
2368
2369	pctrl->data = of_device_get_match_data(dev: &pdev->dev);
2370	if (!pctrl->data)
2371	return -EINVAL;
2372
2373	pctrl->base = devm_platform_ioremap_resource(pdev, index: 0);
2374	if (IS_ERR(ptr: pctrl->base))
2375	return PTR_ERR(ptr: pctrl->base);
2376
2377	pctrl->clk = devm_clk_get_enabled(dev: pctrl->dev, NULL);
2378	if (IS_ERR(ptr: pctrl->clk)) {
2379	return dev_err_probe(dev: pctrl->dev, err: PTR_ERR(ptr: pctrl->clk),
2380	fmt: "failed to enable GPIO clk\n");
2381	}
2382
2383	spin_lock_init(&pctrl->lock);
2384	spin_lock_init(&pctrl->bitmap_lock);
2385	mutex_init(&pctrl->mutex);
2386	atomic_set(v: &pctrl->wakeup_path, i: 0);
2387
2388	platform_set_drvdata(pdev, data: pctrl);
2389
2390	ret = rzg2l_pinctrl_register(pctrl);
2391	if (ret)
2392	return ret;
2393
2394	dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
2395	return 0;
2396	}
2397
2398	static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2399	{
2400	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2401	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2402
2403	for (u32 port = 0; port < nports; port++) {
2404	bool has_iolh, has_ien;
2405	u32 off, caps;
2406	u8 pincnt;
2407	u64 cfg;
2408
2409	cfg = pctrl->data->port_pin_configs[port];
2410	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2411	pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));
2412
2413	caps = FIELD_GET(PIN_CFG_MASK, cfg);
2414	has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2415	has_ien = !!(caps & PIN_CFG_IEN);
2416
2417	if (suspend)
2418	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
2419
2420	/*
2421	* Now cache the registers or set them in the order suggested by
2422	* HW manual (section "Operation for GPIO Function").
2423	*/
2424	RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
2425	if (has_iolh) {
2426	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
2427	cache->iolh[0][port]);
2428	if (pincnt >= 4) {
2429	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4,
2430	cache->iolh[1][port]);
2431	}
2432	}
2433
2434	RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
2435	RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
2436
2437	if (has_ien) {
2438	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
2439	cache->ien[0][port]);
2440	if (pincnt >= 4) {
2441	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4,
2442	cache->ien[1][port]);
2443	}
2444	}
2445	}
2446	}
2447
2448	static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2449	{
2450	struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
2451
2452	/*
2453	* Make sure entries in pctrl->data->n_dedicated_pins[] having the same
2454	* port offset are close together.
2455	*/
2456	for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
2457	bool has_iolh, has_ien;
2458	u32 off, next_off = 0;
2459	u64 cfg, next_cfg;
2460	u8 pincnt;
2461
2462	cfg = pctrl->data->dedicated_pins[i].config;
2463	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2464	if (i + 1 < pctrl->data->n_dedicated_pins) {
2465	next_cfg = pctrl->data->dedicated_pins[i + 1].config;
2466	next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg);
2467	}
2468
2469	if (off == next_off) {
2470	/* Gather caps of all port pins. */
2471	caps |= FIELD_GET(PIN_CFG_MASK, cfg);
2472	continue;
2473	}
2474
2475	/* And apply them in a single shot. */
2476	has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2477	has_ien = !!(caps & PIN_CFG_IEN);
2478	pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
2479
2480	if (has_iolh) {
2481	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
2482	cache->iolh[0][i]);
2483	}
2484	if (has_ien) {
2485	RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
2486	cache->ien[0][i]);
2487	}
2488
2489	if (pincnt >= 4) {
2490	if (has_iolh) {
2491	RZG2L_PCTRL_REG_ACCESS32(suspend,
2492	pctrl->base + IOLH(off) + 4,
2493	cache->iolh[1][i]);
2494	}
2495	if (has_ien) {
2496	RZG2L_PCTRL_REG_ACCESS32(suspend,
2497	pctrl->base + IEN(off) + 4,
2498	cache->ien[1][i]);
2499	}
2500	}
2501	caps = 0;
2502	}
2503	}
2504
2505	static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
2506	{
2507	u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2508	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2509	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
2510
2511	/* Set the PWPR register to allow PFC register to write. */
2512	writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2513	writel(PWPR_PFCWE, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
2514
2515	/* Restore port registers. */
2516	for (u32 port = 0; port < nports; port++) {
2517	unsigned long pinmap;
2518	u8 pmc = 0, max_pin;
2519	u32 off, pfc = 0;
2520	u64 cfg;
2521	u16 pm;
2522	u8 pin;
2523
2524	cfg = pctrl->data->port_pin_configs[port];
2525	off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2526	pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
2527	max_pin = fls(x: pinmap);
2528
2529	pm = readw(addr: pctrl->base + PM(off));
2530	for_each_set_bit(pin, &pinmap, max_pin) {
2531	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2532
2533	/* Nothing to do if PFC was not configured before. */
2534	if (!(cache->pmc[port] & BIT(pin)))
2535	continue;
2536
2537	/* Set pin to 'Non-use (Hi-Z input protection)' */
2538	pm &= ~(PM_MASK << (pin * 2));
2539	writew(val: pm, addr: pctrl->base + PM(off));
2540
2541	/* Temporarily switch to GPIO mode with PMC register */
2542	pmc &= ~BIT(pin);
2543	writeb(val: pmc, addr: pctrl->base + PMC(off));
2544
2545	/* Select Pin function mode. */
2546	pfc &= ~(PFC_MASK << (pin * 4));
2547	pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
2548	writel(val: pfc, addr: pctrl->base + PFC(off));
2549
2550	/* Switch to Peripheral pin function. */
2551	pmc |= BIT(pin);
2552	writeb(val: pmc, addr: pctrl->base + PMC(off));
2553	}
2554	}
2555
2556	/* Set the PWPR register to be write-protected. */
2557	writel(val: 0x0, addr: pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
2558	writel(PWPR_B0WI, addr: pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
2559	}
2560
2561	static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
2562	{
2563	struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
2564	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2565	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
2566	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2567
2568	rzg2l_pinctrl_pm_setup_regs(pctrl, suspend: true);
2569	rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, suspend: true);
2570
2571	for (u8 i = 0; i < 2; i++) {
2572	cache->sd_ch[i] = readb(addr: pctrl->base + SD_CH(regs->sd_ch, i));
2573	cache->eth_poc[i] = readb(addr: pctrl->base + ETH_POC(regs->eth_poc, i));
2574	}
2575
2576	cache->qspi = readb(addr: pctrl->base + QSPI);
2577	cache->eth_mode = readb(addr: pctrl->base + ETH_MODE);
2578
2579	if (!atomic_read(v: &pctrl->wakeup_path))
2580	clk_disable_unprepare(clk: pctrl->clk);
2581	else
2582	device_set_wakeup_path(dev);
2583
2584	return 0;
2585	}
2586
2587	static int rzg2l_pinctrl_resume_noirq(struct device *dev)
2588	{
2589	struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
2590	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2591	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
2592	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2593	int ret;
2594
2595	if (!atomic_read(v: &pctrl->wakeup_path)) {
2596	ret = clk_prepare_enable(clk: pctrl->clk);
2597	if (ret)
2598	return ret;
2599	}
2600
2601	writeb(val: cache->qspi, addr: pctrl->base + QSPI);
2602	writeb(val: cache->eth_mode, addr: pctrl->base + ETH_MODE);
2603	for (u8 i = 0; i < 2; i++) {
2604	writeb(val: cache->sd_ch[i], addr: pctrl->base + SD_CH(regs->sd_ch, i));
2605	writeb(val: cache->eth_poc[i], addr: pctrl->base + ETH_POC(regs->eth_poc, i));
2606	}
2607
2608	rzg2l_pinctrl_pm_setup_pfc(pctrl);
2609	rzg2l_pinctrl_pm_setup_regs(pctrl, suspend: false);
2610	rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, suspend: false);
2611	rzg2l_gpio_irq_restore(pctrl);
2612
2613	return 0;
2614	}
2615
2616	static const struct rzg2l_hwcfg rzg2l_hwcfg = {
2617	.regs = {
2618	.pwpr = 0x3014,
2619	.sd_ch = 0x3000,
2620	.eth_poc = 0x300c,
2621	},
2622	.iolh_groupa_ua = {
2623	/* 3v3 power source */
2624	[RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
2625	},
2626	.iolh_groupb_oi = { 100, 66, 50, 33, },
2627	};
2628
2629	static const struct rzg2l_hwcfg rzg3s_hwcfg = {
2630	.regs = {
2631	.pwpr = 0x3000,
2632	.sd_ch = 0x3004,
2633	.eth_poc = 0x3010,
2634	},
2635	.iolh_groupa_ua = {
2636	/* 1v8 power source */
2637	[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
2638	/* 3v3 power source */
2639	[RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
2640	},
2641	.iolh_groupb_ua = {
2642	/* 1v8 power source */
2643	[RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
2644	/* 3v3 power source */
2645	[RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
2646	},
2647	.iolh_groupc_ua = {
2648	/* 1v8 power source */
2649	[RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
2650	/* 2v5 source */
2651	[RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
2652	/* 3v3 power source */
2653	[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
2654	},
2655	.drive_strength_ua = true,
2656	.func_base = 1,
2657	.oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
2658	.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
2659	};
2660
2661	static struct rzg2l_pinctrl_data r9a07g043_data = {
2662	.port_pins = rzg2l_gpio_names,
2663	.port_pin_configs = r9a07g043_gpio_configs,
2664	.n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
2665	.dedicated_pins = rzg2l_dedicated_pins.common,
2666	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
2667	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
2668	.hwcfg = &rzg2l_hwcfg,
2669	#ifdef CONFIG_RISCV
2670	.variable_pin_cfg = r9a07g043f_variable_pin_cfg,
2671	.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
2672	#endif
2673	};
2674
2675	static struct rzg2l_pinctrl_data r9a07g044_data = {
2676	.port_pins = rzg2l_gpio_names,
2677	.port_pin_configs = r9a07g044_gpio_configs,
2678	.n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
2679	.dedicated_pins = rzg2l_dedicated_pins.common,
2680	.n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
2681	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
2682	ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
2683	.hwcfg = &rzg2l_hwcfg,
2684	};
2685
2686	static struct rzg2l_pinctrl_data r9a08g045_data = {
2687	.port_pins = rzg2l_gpio_names,
2688	.port_pin_configs = r9a08g045_gpio_configs,
2689	.n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
2690	.dedicated_pins = rzg3s_dedicated_pins,
2691	.n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
2692	.n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
2693	.hwcfg = &rzg3s_hwcfg,
2694	};
2695
2696	static const struct of_device_id rzg2l_pinctrl_of_table[] = {
2697	{
2698	.compatible = "renesas,r9a07g043-pinctrl",
2699	.data = &r9a07g043_data,
2700	},
2701	{
2702	.compatible = "renesas,r9a07g044-pinctrl",
2703	.data = &r9a07g044_data,
2704	},
2705	{
2706	.compatible = "renesas,r9a08g045-pinctrl",
2707	.data = &r9a08g045_data,
2708	},
2709	{ /* sentinel */ }
2710	};
2711
2712	static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = {
2713	NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq)
2714	};
2715
2716	static struct platform_driver rzg2l_pinctrl_driver = {
2717	.driver = {
2718	.name = DRV_NAME,
2719	.of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
2720	.pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops),
2721	},
2722	.probe = rzg2l_pinctrl_probe,
2723	};
2724
2725	static int __init rzg2l_pinctrl_init(void)
2726	{
2727	return platform_driver_register(&rzg2l_pinctrl_driver);
2728	}
2729	core_initcall(rzg2l_pinctrl_init);
2730
2731	MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
2732	MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
2733