1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * MediaTek Pulse Width Modulator driver |
4 | * |
5 | * Copyright (C) 2015 John Crispin <blogic@openwrt.org> |
6 | * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> |
7 | * |
8 | */ |
9 | |
10 | #include <linux/err.h> |
11 | #include <linux/io.h> |
12 | #include <linux/ioport.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> |
15 | #include <linux/clk.h> |
16 | #include <linux/of.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/pwm.h> |
19 | #include <linux/slab.h> |
20 | #include <linux/types.h> |
21 | |
22 | /* PWM registers and bits definitions */ |
23 | #define PWMCON 0x00 |
24 | #define PWMHDUR 0x04 |
25 | #define PWMLDUR 0x08 |
26 | #define PWMGDUR 0x0c |
27 | #define PWMWAVENUM 0x28 |
28 | #define PWMDWIDTH 0x2c |
29 | #define PWM45DWIDTH_FIXUP 0x30 |
30 | #define PWMTHRES 0x30 |
31 | #define PWM45THRES_FIXUP 0x34 |
32 | #define PWM_CK_26M_SEL 0x210 |
33 | |
34 | #define PWM_CLK_DIV_MAX 7 |
35 | |
36 | struct pwm_mediatek_of_data { |
37 | unsigned int num_pwms; |
38 | bool pwm45_fixup; |
39 | bool has_ck_26m_sel; |
40 | const unsigned int *reg_offset; |
41 | }; |
42 | |
43 | /** |
44 | * struct pwm_mediatek_chip - struct representing PWM chip |
45 | * @regs: base address of PWM chip |
46 | * @clk_top: the top clock generator |
47 | * @clk_main: the clock used by PWM core |
48 | * @clk_pwms: the clock used by each PWM channel |
49 | * @soc: pointer to chip's platform data |
50 | */ |
51 | struct pwm_mediatek_chip { |
52 | void __iomem *regs; |
53 | struct clk *clk_top; |
54 | struct clk *clk_main; |
55 | struct clk **clk_pwms; |
56 | const struct pwm_mediatek_of_data *soc; |
57 | }; |
58 | |
59 | static const unsigned int mtk_pwm_reg_offset_v1[] = { |
60 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 |
61 | }; |
62 | |
63 | static const unsigned int mtk_pwm_reg_offset_v2[] = { |
64 | 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 |
65 | }; |
66 | |
67 | static inline struct pwm_mediatek_chip * |
68 | to_pwm_mediatek_chip(struct pwm_chip *chip) |
69 | { |
70 | return pwmchip_get_drvdata(chip); |
71 | } |
72 | |
73 | static int pwm_mediatek_clk_enable(struct pwm_chip *chip, |
74 | struct pwm_device *pwm) |
75 | { |
76 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
77 | int ret; |
78 | |
79 | ret = clk_prepare_enable(clk: pc->clk_top); |
80 | if (ret < 0) |
81 | return ret; |
82 | |
83 | ret = clk_prepare_enable(clk: pc->clk_main); |
84 | if (ret < 0) |
85 | goto disable_clk_top; |
86 | |
87 | ret = clk_prepare_enable(clk: pc->clk_pwms[pwm->hwpwm]); |
88 | if (ret < 0) |
89 | goto disable_clk_main; |
90 | |
91 | return 0; |
92 | |
93 | disable_clk_main: |
94 | clk_disable_unprepare(clk: pc->clk_main); |
95 | disable_clk_top: |
96 | clk_disable_unprepare(clk: pc->clk_top); |
97 | |
98 | return ret; |
99 | } |
100 | |
101 | static void pwm_mediatek_clk_disable(struct pwm_chip *chip, |
102 | struct pwm_device *pwm) |
103 | { |
104 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
105 | |
106 | clk_disable_unprepare(clk: pc->clk_pwms[pwm->hwpwm]); |
107 | clk_disable_unprepare(clk: pc->clk_main); |
108 | clk_disable_unprepare(clk: pc->clk_top); |
109 | } |
110 | |
111 | static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, |
112 | unsigned int num, unsigned int offset, |
113 | u32 value) |
114 | { |
115 | writel(val: value, addr: chip->regs + chip->soc->reg_offset[num] + offset); |
116 | } |
117 | |
118 | static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, |
119 | int duty_ns, int period_ns) |
120 | { |
121 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
122 | u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, |
123 | reg_thres = PWMTHRES; |
124 | u64 resolution; |
125 | int ret; |
126 | |
127 | ret = pwm_mediatek_clk_enable(chip, pwm); |
128 | |
129 | if (ret < 0) |
130 | return ret; |
131 | |
132 | /* Make sure we use the bus clock and not the 26MHz clock */ |
133 | if (pc->soc->has_ck_26m_sel) |
134 | writel(val: 0, addr: pc->regs + PWM_CK_26M_SEL); |
135 | |
136 | /* Using resolution in picosecond gets accuracy higher */ |
137 | resolution = (u64)NSEC_PER_SEC * 1000; |
138 | do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); |
139 | |
140 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); |
141 | while (cnt_period > 8191) { |
142 | resolution *= 2; |
143 | clkdiv++; |
144 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, |
145 | resolution); |
146 | } |
147 | |
148 | if (clkdiv > PWM_CLK_DIV_MAX) { |
149 | pwm_mediatek_clk_disable(chip, pwm); |
150 | dev_err(pwmchip_parent(chip), "period of %d ns not supported\n" , period_ns); |
151 | return -EINVAL; |
152 | } |
153 | |
154 | if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { |
155 | /* |
156 | * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES |
157 | * from the other PWMs on MT7623. |
158 | */ |
159 | reg_width = PWM45DWIDTH_FIXUP; |
160 | reg_thres = PWM45THRES_FIXUP; |
161 | } |
162 | |
163 | cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); |
164 | pwm_mediatek_writel(chip: pc, num: pwm->hwpwm, PWMCON, BIT(15) | clkdiv); |
165 | pwm_mediatek_writel(chip: pc, num: pwm->hwpwm, offset: reg_width, value: cnt_period); |
166 | pwm_mediatek_writel(chip: pc, num: pwm->hwpwm, offset: reg_thres, value: cnt_duty); |
167 | |
168 | pwm_mediatek_clk_disable(chip, pwm); |
169 | |
170 | return 0; |
171 | } |
172 | |
173 | static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
174 | { |
175 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
176 | u32 value; |
177 | int ret; |
178 | |
179 | ret = pwm_mediatek_clk_enable(chip, pwm); |
180 | if (ret < 0) |
181 | return ret; |
182 | |
183 | value = readl(addr: pc->regs); |
184 | value |= BIT(pwm->hwpwm); |
185 | writel(val: value, addr: pc->regs); |
186 | |
187 | return 0; |
188 | } |
189 | |
190 | static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
191 | { |
192 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
193 | u32 value; |
194 | |
195 | value = readl(addr: pc->regs); |
196 | value &= ~BIT(pwm->hwpwm); |
197 | writel(val: value, addr: pc->regs); |
198 | |
199 | pwm_mediatek_clk_disable(chip, pwm); |
200 | } |
201 | |
202 | static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
203 | const struct pwm_state *state) |
204 | { |
205 | int err; |
206 | |
207 | if (state->polarity != PWM_POLARITY_NORMAL) |
208 | return -EINVAL; |
209 | |
210 | if (!state->enabled) { |
211 | if (pwm->state.enabled) |
212 | pwm_mediatek_disable(chip, pwm); |
213 | |
214 | return 0; |
215 | } |
216 | |
217 | err = pwm_mediatek_config(chip, pwm, duty_ns: state->duty_cycle, period_ns: state->period); |
218 | if (err) |
219 | return err; |
220 | |
221 | if (!pwm->state.enabled) |
222 | err = pwm_mediatek_enable(chip, pwm); |
223 | |
224 | return err; |
225 | } |
226 | |
227 | static const struct pwm_ops pwm_mediatek_ops = { |
228 | .apply = pwm_mediatek_apply, |
229 | }; |
230 | |
231 | static int pwm_mediatek_probe(struct platform_device *pdev) |
232 | { |
233 | struct pwm_chip *chip; |
234 | struct pwm_mediatek_chip *pc; |
235 | const struct pwm_mediatek_of_data *soc; |
236 | unsigned int i; |
237 | int ret; |
238 | |
239 | soc = of_device_get_match_data(dev: &pdev->dev); |
240 | |
241 | chip = devm_pwmchip_alloc(parent: &pdev->dev, npwm: soc->num_pwms, sizeof_priv: sizeof(*pc)); |
242 | if (IS_ERR(ptr: chip)) |
243 | return PTR_ERR(ptr: chip); |
244 | pc = to_pwm_mediatek_chip(chip); |
245 | |
246 | pc->soc = soc; |
247 | |
248 | pc->regs = devm_platform_ioremap_resource(pdev, index: 0); |
249 | if (IS_ERR(ptr: pc->regs)) |
250 | return PTR_ERR(ptr: pc->regs); |
251 | |
252 | pc->clk_pwms = devm_kmalloc_array(dev: &pdev->dev, n: soc->num_pwms, |
253 | size: sizeof(*pc->clk_pwms), GFP_KERNEL); |
254 | if (!pc->clk_pwms) |
255 | return -ENOMEM; |
256 | |
257 | pc->clk_top = devm_clk_get(dev: &pdev->dev, id: "top" ); |
258 | if (IS_ERR(ptr: pc->clk_top)) |
259 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: pc->clk_top), |
260 | fmt: "Failed to get top clock\n" ); |
261 | |
262 | pc->clk_main = devm_clk_get(dev: &pdev->dev, id: "main" ); |
263 | if (IS_ERR(ptr: pc->clk_main)) |
264 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: pc->clk_main), |
265 | fmt: "Failed to get main clock\n" ); |
266 | |
267 | for (i = 0; i < soc->num_pwms; i++) { |
268 | char name[8]; |
269 | |
270 | snprintf(buf: name, size: sizeof(name), fmt: "pwm%d" , i + 1); |
271 | |
272 | pc->clk_pwms[i] = devm_clk_get(dev: &pdev->dev, id: name); |
273 | if (IS_ERR(ptr: pc->clk_pwms[i])) |
274 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: pc->clk_pwms[i]), |
275 | fmt: "Failed to get %s clock\n" , name); |
276 | } |
277 | |
278 | chip->ops = &pwm_mediatek_ops; |
279 | |
280 | ret = devm_pwmchip_add(&pdev->dev, chip); |
281 | if (ret < 0) |
282 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "pwmchip_add() failed\n" ); |
283 | |
284 | return 0; |
285 | } |
286 | |
287 | static const struct pwm_mediatek_of_data mt2712_pwm_data = { |
288 | .num_pwms = 8, |
289 | .pwm45_fixup = false, |
290 | .has_ck_26m_sel = false, |
291 | .reg_offset = mtk_pwm_reg_offset_v1, |
292 | }; |
293 | |
294 | static const struct pwm_mediatek_of_data mt6795_pwm_data = { |
295 | .num_pwms = 7, |
296 | .pwm45_fixup = false, |
297 | .has_ck_26m_sel = false, |
298 | .reg_offset = mtk_pwm_reg_offset_v1, |
299 | }; |
300 | |
301 | static const struct pwm_mediatek_of_data mt7622_pwm_data = { |
302 | .num_pwms = 6, |
303 | .pwm45_fixup = false, |
304 | .has_ck_26m_sel = true, |
305 | .reg_offset = mtk_pwm_reg_offset_v1, |
306 | }; |
307 | |
308 | static const struct pwm_mediatek_of_data mt7623_pwm_data = { |
309 | .num_pwms = 5, |
310 | .pwm45_fixup = true, |
311 | .has_ck_26m_sel = false, |
312 | .reg_offset = mtk_pwm_reg_offset_v1, |
313 | }; |
314 | |
315 | static const struct pwm_mediatek_of_data mt7628_pwm_data = { |
316 | .num_pwms = 4, |
317 | .pwm45_fixup = true, |
318 | .has_ck_26m_sel = false, |
319 | .reg_offset = mtk_pwm_reg_offset_v1, |
320 | }; |
321 | |
322 | static const struct pwm_mediatek_of_data mt7629_pwm_data = { |
323 | .num_pwms = 1, |
324 | .pwm45_fixup = false, |
325 | .has_ck_26m_sel = false, |
326 | .reg_offset = mtk_pwm_reg_offset_v1, |
327 | }; |
328 | |
329 | static const struct pwm_mediatek_of_data mt7981_pwm_data = { |
330 | .num_pwms = 3, |
331 | .pwm45_fixup = false, |
332 | .has_ck_26m_sel = true, |
333 | .reg_offset = mtk_pwm_reg_offset_v2, |
334 | }; |
335 | |
336 | static const struct pwm_mediatek_of_data mt7986_pwm_data = { |
337 | .num_pwms = 2, |
338 | .pwm45_fixup = false, |
339 | .has_ck_26m_sel = true, |
340 | .reg_offset = mtk_pwm_reg_offset_v1, |
341 | }; |
342 | |
343 | static const struct pwm_mediatek_of_data mt7988_pwm_data = { |
344 | .num_pwms = 8, |
345 | .pwm45_fixup = false, |
346 | .has_ck_26m_sel = false, |
347 | .reg_offset = mtk_pwm_reg_offset_v2, |
348 | }; |
349 | |
350 | static const struct pwm_mediatek_of_data mt8183_pwm_data = { |
351 | .num_pwms = 4, |
352 | .pwm45_fixup = false, |
353 | .has_ck_26m_sel = true, |
354 | .reg_offset = mtk_pwm_reg_offset_v1, |
355 | }; |
356 | |
357 | static const struct pwm_mediatek_of_data mt8365_pwm_data = { |
358 | .num_pwms = 3, |
359 | .pwm45_fixup = false, |
360 | .has_ck_26m_sel = true, |
361 | .reg_offset = mtk_pwm_reg_offset_v1, |
362 | }; |
363 | |
364 | static const struct pwm_mediatek_of_data mt8516_pwm_data = { |
365 | .num_pwms = 5, |
366 | .pwm45_fixup = false, |
367 | .has_ck_26m_sel = true, |
368 | .reg_offset = mtk_pwm_reg_offset_v1, |
369 | }; |
370 | |
371 | static const struct of_device_id pwm_mediatek_of_match[] = { |
372 | { .compatible = "mediatek,mt2712-pwm" , .data = &mt2712_pwm_data }, |
373 | { .compatible = "mediatek,mt6795-pwm" , .data = &mt6795_pwm_data }, |
374 | { .compatible = "mediatek,mt7622-pwm" , .data = &mt7622_pwm_data }, |
375 | { .compatible = "mediatek,mt7623-pwm" , .data = &mt7623_pwm_data }, |
376 | { .compatible = "mediatek,mt7628-pwm" , .data = &mt7628_pwm_data }, |
377 | { .compatible = "mediatek,mt7629-pwm" , .data = &mt7629_pwm_data }, |
378 | { .compatible = "mediatek,mt7981-pwm" , .data = &mt7981_pwm_data }, |
379 | { .compatible = "mediatek,mt7986-pwm" , .data = &mt7986_pwm_data }, |
380 | { .compatible = "mediatek,mt7988-pwm" , .data = &mt7988_pwm_data }, |
381 | { .compatible = "mediatek,mt8183-pwm" , .data = &mt8183_pwm_data }, |
382 | { .compatible = "mediatek,mt8365-pwm" , .data = &mt8365_pwm_data }, |
383 | { .compatible = "mediatek,mt8516-pwm" , .data = &mt8516_pwm_data }, |
384 | { }, |
385 | }; |
386 | MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); |
387 | |
388 | static struct platform_driver pwm_mediatek_driver = { |
389 | .driver = { |
390 | .name = "pwm-mediatek" , |
391 | .of_match_table = pwm_mediatek_of_match, |
392 | }, |
393 | .probe = pwm_mediatek_probe, |
394 | }; |
395 | module_platform_driver(pwm_mediatek_driver); |
396 | |
397 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>" ); |
398 | MODULE_LICENSE("GPL v2" ); |
399 | |