1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.
4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/firmware.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/iommu.h>
13#include <linux/iopoll.h>
14#include <linux/kernel.h>
15#include <linux/mfd/syscon.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/platform_device.h>
20#include <linux/pm_domain.h>
21#include <linux/pm_runtime.h>
22#include <linux/regmap.h>
23#include <linux/remoteproc.h>
24#include <linux/reset.h>
25#include <linux/soc/qcom/mdt_loader.h>
26#include <linux/soc/qcom/smem.h>
27#include <linux/soc/qcom/smem_state.h>
28
29#include "qcom_common.h"
30#include "qcom_pil_info.h"
31#include "qcom_q6v5.h"
32#include "remoteproc_internal.h"
33
34/* time out value */
35#define ACK_TIMEOUT 1000
36#define ACK_TIMEOUT_US 1000000
37#define BOOT_FSM_TIMEOUT 10000
38/* mask values */
39#define EVB_MASK GENMASK(27, 4)
40/*QDSP6SS register offsets*/
41#define RST_EVB_REG 0x10
42#define CORE_START_REG 0x400
43#define BOOT_CMD_REG 0x404
44#define BOOT_STATUS_REG 0x408
45#define RET_CFG_REG 0x1C
46/*TCSR register offsets*/
47#define LPASS_MASTER_IDLE_REG 0x8
48#define LPASS_HALTACK_REG 0x4
49#define LPASS_PWR_ON_REG 0x10
50#define LPASS_HALTREQ_REG 0x0
51
52#define SID_MASK_DEFAULT 0xF
53
54#define QDSP6SS_XO_CBCR 0x38
55#define QDSP6SS_CORE_CBCR 0x20
56#define QDSP6SS_SLEEP_CBCR 0x3c
57
58#define LPASS_BOOT_CORE_START BIT(0)
59#define LPASS_BOOT_CMD_START BIT(0)
60#define LPASS_EFUSE_Q6SS_EVB_SEL 0x0
61
62struct adsp_pil_data {
63 int crash_reason_smem;
64 const char *firmware_name;
65
66 const char *ssr_name;
67 const char *sysmon_name;
68 int ssctl_id;
69 bool is_wpss;
70 bool has_iommu;
71 bool auto_boot;
72
73 const char **clk_ids;
74 int num_clks;
75 const char **pd_names;
76 unsigned int num_pds;
77 const char *load_state;
78};
79
80struct qcom_adsp {
81 struct device *dev;
82 struct rproc *rproc;
83
84 struct qcom_q6v5 q6v5;
85
86 struct clk *xo;
87
88 int num_clks;
89 struct clk_bulk_data *clks;
90
91 void __iomem *qdsp6ss_base;
92 void __iomem *lpass_efuse;
93
94 struct reset_control *pdc_sync_reset;
95 struct reset_control *restart;
96
97 struct regmap *halt_map;
98 unsigned int halt_lpass;
99
100 int crash_reason_smem;
101 const char *info_name;
102
103 struct completion start_done;
104 struct completion stop_done;
105
106 phys_addr_t mem_phys;
107 phys_addr_t mem_reloc;
108 void *mem_region;
109 size_t mem_size;
110 bool has_iommu;
111
112 struct dev_pm_domain_list *pd_list;
113
114 struct qcom_rproc_glink glink_subdev;
115 struct qcom_rproc_pdm pdm_subdev;
116 struct qcom_rproc_ssr ssr_subdev;
117 struct qcom_sysmon *sysmon;
118
119 int (*shutdown)(struct qcom_adsp *adsp);
120};
121
122static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names,
123 unsigned int num_pds)
124{
125 struct device *dev = adsp->dev;
126 struct dev_pm_domain_attach_data pd_data = {
127 .pd_names = pd_names,
128 .num_pd_names = num_pds,
129 };
130 int ret;
131
132 /* Handle single power domain */
133 if (dev->pm_domain)
134 goto out;
135
136 if (!pd_names)
137 return 0;
138
139 ret = dev_pm_domain_attach_list(dev, data: &pd_data, list: &adsp->pd_list);
140 if (ret < 0)
141 return ret;
142
143out:
144 pm_runtime_enable(dev);
145 return 0;
146}
147
148static void qcom_rproc_pds_detach(struct qcom_adsp *adsp)
149{
150 struct device *dev = adsp->dev;
151 struct dev_pm_domain_list *pds = adsp->pd_list;
152
153 dev_pm_domain_detach_list(list: pds);
154
155 if (dev->pm_domain || pds)
156 pm_runtime_disable(dev: adsp->dev);
157}
158
159static int qcom_rproc_pds_enable(struct qcom_adsp *adsp)
160{
161 struct device *dev = adsp->dev;
162 struct dev_pm_domain_list *pds = adsp->pd_list;
163 int ret, i = 0;
164
165 if (!dev->pm_domain && !pds)
166 return 0;
167
168 if (dev->pm_domain)
169 dev_pm_genpd_set_performance_state(dev, INT_MAX);
170
171 while (pds && i < pds->num_pds) {
172 dev_pm_genpd_set_performance_state(dev: pds->pd_devs[i], INT_MAX);
173 i++;
174 }
175
176 ret = pm_runtime_resume_and_get(dev);
177 if (ret < 0) {
178 while (pds && i > 0) {
179 i--;
180 dev_pm_genpd_set_performance_state(dev: pds->pd_devs[i], state: 0);
181 }
182
183 if (dev->pm_domain)
184 dev_pm_genpd_set_performance_state(dev, state: 0);
185 }
186
187 return ret;
188}
189
190static void qcom_rproc_pds_disable(struct qcom_adsp *adsp)
191{
192 struct device *dev = adsp->dev;
193 struct dev_pm_domain_list *pds = adsp->pd_list;
194 int i = 0;
195
196 if (!dev->pm_domain && !pds)
197 return;
198
199 if (dev->pm_domain)
200 dev_pm_genpd_set_performance_state(dev, state: 0);
201
202 while (pds && i < pds->num_pds) {
203 dev_pm_genpd_set_performance_state(dev: pds->pd_devs[i], state: 0);
204 i++;
205 }
206
207 pm_runtime_put(dev);
208}
209
210static int qcom_wpss_shutdown(struct qcom_adsp *adsp)
211{
212 unsigned int val;
213
214 regmap_write(map: adsp->halt_map, reg: adsp->halt_lpass + LPASS_HALTREQ_REG, val: 1);
215
216 /* Wait for halt ACK from QDSP6 */
217 regmap_read_poll_timeout(adsp->halt_map,
218 adsp->halt_lpass + LPASS_HALTACK_REG, val,
219 val, 1000, ACK_TIMEOUT_US);
220
221 /* Assert the WPSS PDC Reset */
222 reset_control_assert(rstc: adsp->pdc_sync_reset);
223
224 /* Place the WPSS processor into reset */
225 reset_control_assert(rstc: adsp->restart);
226
227 /* wait after asserting subsystem restart from AOSS */
228 usleep_range(min: 200, max: 205);
229
230 /* Remove the WPSS reset */
231 reset_control_deassert(rstc: adsp->restart);
232
233 /* De-assert the WPSS PDC Reset */
234 reset_control_deassert(rstc: adsp->pdc_sync_reset);
235
236 usleep_range(min: 100, max: 105);
237
238 clk_bulk_disable_unprepare(num_clks: adsp->num_clks, clks: adsp->clks);
239
240 regmap_write(map: adsp->halt_map, reg: adsp->halt_lpass + LPASS_HALTREQ_REG, val: 0);
241
242 /* Wait for halt ACK from QDSP6 */
243 regmap_read_poll_timeout(adsp->halt_map,
244 adsp->halt_lpass + LPASS_HALTACK_REG, val,
245 !val, 1000, ACK_TIMEOUT_US);
246
247 return 0;
248}
249
250static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
251{
252 unsigned long timeout;
253 unsigned int val;
254 int ret;
255
256 /* Reset the retention logic */
257 val = readl(addr: adsp->qdsp6ss_base + RET_CFG_REG);
258 val |= 0x1;
259 writel(val, addr: adsp->qdsp6ss_base + RET_CFG_REG);
260
261 clk_bulk_disable_unprepare(num_clks: adsp->num_clks, clks: adsp->clks);
262
263 /* QDSP6 master port needs to be explicitly halted */
264 ret = regmap_read(map: adsp->halt_map,
265 reg: adsp->halt_lpass + LPASS_PWR_ON_REG, val: &val);
266 if (ret || !val)
267 goto reset;
268
269 ret = regmap_read(map: adsp->halt_map,
270 reg: adsp->halt_lpass + LPASS_MASTER_IDLE_REG,
271 val: &val);
272 if (ret || val)
273 goto reset;
274
275 regmap_write(map: adsp->halt_map,
276 reg: adsp->halt_lpass + LPASS_HALTREQ_REG, val: 1);
277
278 /* Wait for halt ACK from QDSP6 */
279 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);
280 for (;;) {
281 ret = regmap_read(map: adsp->halt_map,
282 reg: adsp->halt_lpass + LPASS_HALTACK_REG, val: &val);
283 if (ret || val || time_after(jiffies, timeout))
284 break;
285
286 usleep_range(min: 1000, max: 1100);
287 }
288
289 ret = regmap_read(map: adsp->halt_map,
290 reg: adsp->halt_lpass + LPASS_MASTER_IDLE_REG, val: &val);
291 if (ret || !val)
292 dev_err(adsp->dev, "port failed halt\n");
293
294reset:
295 /* Assert the LPASS PDC Reset */
296 reset_control_assert(rstc: adsp->pdc_sync_reset);
297 /* Place the LPASS processor into reset */
298 reset_control_assert(rstc: adsp->restart);
299 /* wait after asserting subsystem restart from AOSS */
300 usleep_range(min: 200, max: 300);
301
302 /* Clear the halt request for the AXIM and AHBM for Q6 */
303 regmap_write(map: adsp->halt_map, reg: adsp->halt_lpass + LPASS_HALTREQ_REG, val: 0);
304
305 /* De-assert the LPASS PDC Reset */
306 reset_control_deassert(rstc: adsp->pdc_sync_reset);
307 /* Remove the LPASS reset */
308 reset_control_deassert(rstc: adsp->restart);
309 /* wait after de-asserting subsystem restart from AOSS */
310 usleep_range(min: 200, max: 300);
311
312 return 0;
313}
314
315static int adsp_load(struct rproc *rproc, const struct firmware *fw)
316{
317 struct qcom_adsp *adsp = rproc->priv;
318 int ret;
319
320 ret = qcom_mdt_load_no_init(dev: adsp->dev, fw, fw_name: rproc->firmware, pas_id: 0,
321 mem_region: adsp->mem_region, mem_phys: adsp->mem_phys,
322 mem_size: adsp->mem_size, reloc_base: &adsp->mem_reloc);
323 if (ret)
324 return ret;
325
326 qcom_pil_info_store(image: adsp->info_name, base: adsp->mem_phys, size: adsp->mem_size);
327
328 return 0;
329}
330
331static void adsp_unmap_carveout(struct rproc *rproc)
332{
333 struct qcom_adsp *adsp = rproc->priv;
334
335 if (adsp->has_iommu)
336 iommu_unmap(domain: rproc->domain, iova: adsp->mem_phys, size: adsp->mem_size);
337}
338
339static int adsp_map_carveout(struct rproc *rproc)
340{
341 struct qcom_adsp *adsp = rproc->priv;
342 struct of_phandle_args args;
343 long long sid;
344 unsigned long iova;
345 int ret;
346
347 if (!adsp->has_iommu)
348 return 0;
349
350 if (!rproc->domain)
351 return -EINVAL;
352
353 ret = of_parse_phandle_with_args(np: adsp->dev->of_node, list_name: "iommus", cells_name: "#iommu-cells", index: 0, out_args: &args);
354 if (ret < 0)
355 return ret;
356
357 sid = args.args[0] & SID_MASK_DEFAULT;
358
359 /* Add SID configuration for ADSP Firmware to SMMU */
360 iova = adsp->mem_phys | (sid << 32);
361
362 ret = iommu_map(domain: rproc->domain, iova, paddr: adsp->mem_phys,
363 size: adsp->mem_size, IOMMU_READ | IOMMU_WRITE,
364 GFP_KERNEL);
365 if (ret) {
366 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");
367 return ret;
368 }
369
370 return 0;
371}
372
373static int adsp_start(struct rproc *rproc)
374{
375 struct qcom_adsp *adsp = rproc->priv;
376 int ret;
377 unsigned int val;
378
379 ret = qcom_q6v5_prepare(q6v5: &adsp->q6v5);
380 if (ret)
381 return ret;
382
383 ret = adsp_map_carveout(rproc);
384 if (ret) {
385 dev_err(adsp->dev, "ADSP smmu mapping failed\n");
386 goto disable_irqs;
387 }
388
389 ret = clk_prepare_enable(clk: adsp->xo);
390 if (ret)
391 goto adsp_smmu_unmap;
392
393 ret = qcom_rproc_pds_enable(adsp);
394 if (ret < 0)
395 goto disable_xo_clk;
396
397 ret = clk_bulk_prepare_enable(num_clks: adsp->num_clks, clks: adsp->clks);
398 if (ret) {
399 dev_err(adsp->dev, "adsp clk_enable failed\n");
400 goto disable_power_domain;
401 }
402
403 /* Enable the XO clock */
404 writel(val: 1, addr: adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
405
406 /* Enable the QDSP6SS sleep clock */
407 writel(val: 1, addr: adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
408
409 /* Enable the QDSP6 core clock */
410 writel(val: 1, addr: adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
411
412 /* Program boot address */
413 writel(val: adsp->mem_phys >> 4, addr: adsp->qdsp6ss_base + RST_EVB_REG);
414
415 if (adsp->lpass_efuse)
416 writel(LPASS_EFUSE_Q6SS_EVB_SEL, addr: adsp->lpass_efuse);
417
418 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */
419 writel(LPASS_BOOT_CORE_START, addr: adsp->qdsp6ss_base + CORE_START_REG);
420
421 /* Trigger boot FSM to start QDSP6 */
422 writel(LPASS_BOOT_CMD_START, addr: adsp->qdsp6ss_base + BOOT_CMD_REG);
423
424 /* Wait for core to come out of reset */
425 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,
426 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
427 if (ret) {
428 dev_err(adsp->dev, "failed to bootup adsp\n");
429 goto disable_adsp_clks;
430 }
431
432 ret = qcom_q6v5_wait_for_start(q6v5: &adsp->q6v5, timeout: msecs_to_jiffies(m: 5 * HZ));
433 if (ret == -ETIMEDOUT) {
434 dev_err(adsp->dev, "start timed out\n");
435 goto disable_adsp_clks;
436 }
437
438 return 0;
439
440disable_adsp_clks:
441 clk_bulk_disable_unprepare(num_clks: adsp->num_clks, clks: adsp->clks);
442disable_power_domain:
443 qcom_rproc_pds_disable(adsp);
444disable_xo_clk:
445 clk_disable_unprepare(clk: adsp->xo);
446adsp_smmu_unmap:
447 adsp_unmap_carveout(rproc);
448disable_irqs:
449 qcom_q6v5_unprepare(q6v5: &adsp->q6v5);
450
451 return ret;
452}
453
454static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)
455{
456 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
457
458 clk_disable_unprepare(clk: adsp->xo);
459 qcom_rproc_pds_disable(adsp);
460}
461
462static int adsp_stop(struct rproc *rproc)
463{
464 struct qcom_adsp *adsp = rproc->priv;
465 int handover;
466 int ret;
467
468 ret = qcom_q6v5_request_stop(q6v5: &adsp->q6v5, sysmon: adsp->sysmon);
469 if (ret == -ETIMEDOUT)
470 dev_err(adsp->dev, "timed out on wait\n");
471
472 ret = adsp->shutdown(adsp);
473 if (ret)
474 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
475
476 adsp_unmap_carveout(rproc);
477
478 handover = qcom_q6v5_unprepare(q6v5: &adsp->q6v5);
479 if (handover)
480 qcom_adsp_pil_handover(q6v5: &adsp->q6v5);
481
482 return ret;
483}
484
485static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
486{
487 struct qcom_adsp *adsp = rproc->priv;
488 int offset;
489
490 offset = da - adsp->mem_reloc;
491 if (offset < 0 || offset + len > adsp->mem_size)
492 return NULL;
493
494 return adsp->mem_region + offset;
495}
496
497static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)
498{
499 struct qcom_adsp *adsp = rproc->priv;
500 int ret;
501
502 ret = qcom_register_dump_segments(rproc, fw);
503 if (ret) {
504 dev_err(&rproc->dev, "Error in registering dump segments\n");
505 return ret;
506 }
507
508 if (adsp->has_iommu) {
509 ret = rproc_elf_load_rsc_table(rproc, fw);
510 if (ret) {
511 dev_err(&rproc->dev, "Error in loading resource table\n");
512 return ret;
513 }
514 }
515 return 0;
516}
517
518static unsigned long adsp_panic(struct rproc *rproc)
519{
520 struct qcom_adsp *adsp = rproc->priv;
521
522 return qcom_q6v5_panic(q6v5: &adsp->q6v5);
523}
524
525static const struct rproc_ops adsp_ops = {
526 .start = adsp_start,
527 .stop = adsp_stop,
528 .da_to_va = adsp_da_to_va,
529 .parse_fw = adsp_parse_firmware,
530 .load = adsp_load,
531 .panic = adsp_panic,
532};
533
534static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)
535{
536 int num_clks = 0;
537 int i;
538
539 adsp->xo = devm_clk_get(dev: adsp->dev, id: "xo");
540 if (IS_ERR(ptr: adsp->xo))
541 return dev_err_probe(dev: adsp->dev, err: PTR_ERR(ptr: adsp->xo), fmt: "failed to get xo clock");
542
543 for (i = 0; clk_ids[i]; i++)
544 num_clks++;
545
546 adsp->num_clks = num_clks;
547 adsp->clks = devm_kcalloc(dev: adsp->dev, n: adsp->num_clks,
548 size: sizeof(*adsp->clks), GFP_KERNEL);
549 if (!adsp->clks)
550 return -ENOMEM;
551
552 for (i = 0; i < adsp->num_clks; i++)
553 adsp->clks[i].id = clk_ids[i];
554
555 return devm_clk_bulk_get(dev: adsp->dev, num_clks: adsp->num_clks, clks: adsp->clks);
556}
557
558static int adsp_init_reset(struct qcom_adsp *adsp)
559{
560 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(dev: adsp->dev,
561 id: "pdc_sync");
562 if (IS_ERR(ptr: adsp->pdc_sync_reset)) {
563 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");
564 return PTR_ERR(ptr: adsp->pdc_sync_reset);
565 }
566
567 adsp->restart = devm_reset_control_get_optional_exclusive(dev: adsp->dev, id: "restart");
568
569 /* Fall back to the old "cc_lpass" if "restart" is absent */
570 if (!adsp->restart)
571 adsp->restart = devm_reset_control_get_exclusive(dev: adsp->dev, id: "cc_lpass");
572
573 if (IS_ERR(ptr: adsp->restart)) {
574 dev_err(adsp->dev, "failed to acquire restart\n");
575 return PTR_ERR(ptr: adsp->restart);
576 }
577
578 return 0;
579}
580
581static int adsp_init_mmio(struct qcom_adsp *adsp,
582 struct platform_device *pdev)
583{
584 struct resource *efuse_region;
585 struct device_node *syscon;
586 int ret;
587
588 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, index: 0);
589 if (IS_ERR(ptr: adsp->qdsp6ss_base)) {
590 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");
591 return PTR_ERR(ptr: adsp->qdsp6ss_base);
592 }
593
594 efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);
595 if (!efuse_region) {
596 adsp->lpass_efuse = NULL;
597 dev_dbg(adsp->dev, "failed to get efuse memory region\n");
598 } else {
599 adsp->lpass_efuse = devm_ioremap_resource(dev: &pdev->dev, res: efuse_region);
600 if (IS_ERR(ptr: adsp->lpass_efuse)) {
601 dev_err(adsp->dev, "failed to map efuse registers\n");
602 return PTR_ERR(ptr: adsp->lpass_efuse);
603 }
604 }
605 syscon = of_parse_phandle(np: pdev->dev.of_node, phandle_name: "qcom,halt-regs", index: 0);
606 if (!syscon) {
607 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
608 return -EINVAL;
609 }
610
611 adsp->halt_map = syscon_node_to_regmap(np: syscon);
612 of_node_put(node: syscon);
613 if (IS_ERR(ptr: adsp->halt_map))
614 return PTR_ERR(ptr: adsp->halt_map);
615
616 ret = of_property_read_u32_index(np: pdev->dev.of_node, propname: "qcom,halt-regs",
617 index: 1, out_value: &adsp->halt_lpass);
618 if (ret < 0) {
619 dev_err(&pdev->dev, "no offset in syscon\n");
620 return ret;
621 }
622
623 return 0;
624}
625
626static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
627{
628 struct reserved_mem *rmem = NULL;
629 struct device_node *node;
630
631 node = of_parse_phandle(np: adsp->dev->of_node, phandle_name: "memory-region", index: 0);
632 if (node)
633 rmem = of_reserved_mem_lookup(np: node);
634 of_node_put(node);
635
636 if (!rmem) {
637 dev_err(adsp->dev, "unable to resolve memory-region\n");
638 return -EINVAL;
639 }
640
641 adsp->mem_phys = adsp->mem_reloc = rmem->base;
642 adsp->mem_size = rmem->size;
643 adsp->mem_region = devm_ioremap_wc(dev: adsp->dev,
644 offset: adsp->mem_phys, size: adsp->mem_size);
645 if (!adsp->mem_region) {
646 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
647 &rmem->base, adsp->mem_size);
648 return -EBUSY;
649 }
650
651 return 0;
652}
653
654static int adsp_probe(struct platform_device *pdev)
655{
656 const struct adsp_pil_data *desc;
657 const char *firmware_name;
658 struct qcom_adsp *adsp;
659 struct rproc *rproc;
660 int ret;
661
662 desc = of_device_get_match_data(dev: &pdev->dev);
663 if (!desc)
664 return -EINVAL;
665
666 firmware_name = desc->firmware_name;
667 ret = of_property_read_string(np: pdev->dev.of_node, propname: "firmware-name",
668 out_string: &firmware_name);
669 if (ret < 0 && ret != -EINVAL) {
670 dev_err(&pdev->dev, "unable to read firmware-name\n");
671 return ret;
672 }
673
674 rproc = devm_rproc_alloc(dev: &pdev->dev, name: pdev->name, ops: &adsp_ops,
675 firmware: firmware_name, len: sizeof(*adsp));
676 if (!rproc) {
677 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
678 return -ENOMEM;
679 }
680
681 rproc->auto_boot = desc->auto_boot;
682 rproc->has_iommu = desc->has_iommu;
683 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
684
685 adsp = rproc->priv;
686 adsp->dev = &pdev->dev;
687 adsp->rproc = rproc;
688 adsp->info_name = desc->sysmon_name;
689 adsp->has_iommu = desc->has_iommu;
690
691 platform_set_drvdata(pdev, data: adsp);
692
693 if (desc->is_wpss)
694 adsp->shutdown = qcom_wpss_shutdown;
695 else
696 adsp->shutdown = qcom_adsp_shutdown;
697
698 ret = adsp_alloc_memory_region(adsp);
699 if (ret)
700 return ret;
701
702 ret = adsp_init_clock(adsp, clk_ids: desc->clk_ids);
703 if (ret)
704 return ret;
705
706 ret = qcom_rproc_pds_attach(adsp, pd_names: desc->pd_names, num_pds: desc->num_pds);
707 if (ret < 0)
708 return dev_err_probe(dev: &pdev->dev, err: ret,
709 fmt: "Failed to attach proxy power domains\n");
710
711 ret = adsp_init_reset(adsp);
712 if (ret)
713 goto disable_pm;
714
715 ret = adsp_init_mmio(adsp, pdev);
716 if (ret)
717 goto disable_pm;
718
719 ret = qcom_q6v5_init(q6v5: &adsp->q6v5, pdev, rproc, crash_reason: desc->crash_reason_smem,
720 load_state: desc->load_state, handover: qcom_adsp_pil_handover);
721 if (ret)
722 goto disable_pm;
723
724 qcom_add_glink_subdev(rproc, glink: &adsp->glink_subdev, ssr_name: desc->ssr_name);
725 qcom_add_pdm_subdev(rproc, pdm: &adsp->pdm_subdev);
726 qcom_add_ssr_subdev(rproc, ssr: &adsp->ssr_subdev, ssr_name: desc->ssr_name);
727 adsp->sysmon = qcom_add_sysmon_subdev(rproc,
728 name: desc->sysmon_name,
729 ssctl_instance: desc->ssctl_id);
730 if (IS_ERR(ptr: adsp->sysmon)) {
731 ret = PTR_ERR(ptr: adsp->sysmon);
732 goto deinit_remove_glink_pdm_ssr;
733 }
734
735 ret = rproc_add(rproc);
736 if (ret)
737 goto remove_sysmon;
738
739 return 0;
740
741remove_sysmon:
742 qcom_remove_sysmon_subdev(sysmon: adsp->sysmon);
743deinit_remove_glink_pdm_ssr:
744 qcom_q6v5_deinit(q6v5: &adsp->q6v5);
745 qcom_remove_glink_subdev(rproc, glink: &adsp->glink_subdev);
746 qcom_remove_pdm_subdev(rproc, pdm: &adsp->pdm_subdev);
747 qcom_remove_ssr_subdev(rproc, ssr: &adsp->ssr_subdev);
748disable_pm:
749 qcom_rproc_pds_detach(adsp);
750
751 return ret;
752}
753
754static void adsp_remove(struct platform_device *pdev)
755{
756 struct qcom_adsp *adsp = platform_get_drvdata(pdev);
757
758 rproc_del(rproc: adsp->rproc);
759
760 qcom_q6v5_deinit(q6v5: &adsp->q6v5);
761 qcom_remove_glink_subdev(rproc: adsp->rproc, glink: &adsp->glink_subdev);
762 qcom_remove_pdm_subdev(rproc: adsp->rproc, pdm: &adsp->pdm_subdev);
763 qcom_remove_sysmon_subdev(sysmon: adsp->sysmon);
764 qcom_remove_ssr_subdev(rproc: adsp->rproc, ssr: &adsp->ssr_subdev);
765 qcom_rproc_pds_detach(adsp);
766}
767
768static const struct adsp_pil_data adsp_resource_init = {
769 .crash_reason_smem = 423,
770 .firmware_name = "adsp.mdt",
771 .ssr_name = "lpass",
772 .sysmon_name = "adsp",
773 .ssctl_id = 0x14,
774 .is_wpss = false,
775 .auto_boot = true,
776 .clk_ids = (const char*[]) {
777 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",
778 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL
779 },
780 .num_clks = 7,
781 .pd_names = (const char*[]) { "cx" },
782 .num_pds = 1,
783};
784
785static const struct adsp_pil_data adsp_sc7280_resource_init = {
786 .crash_reason_smem = 423,
787 .firmware_name = "adsp.pbn",
788 .load_state = "adsp",
789 .ssr_name = "lpass",
790 .sysmon_name = "adsp",
791 .ssctl_id = 0x14,
792 .has_iommu = true,
793 .auto_boot = true,
794 .clk_ids = (const char*[]) {
795 "gcc_cfg_noc_lpass", NULL
796 },
797 .num_clks = 1,
798};
799
800static const struct adsp_pil_data cdsp_resource_init = {
801 .crash_reason_smem = 601,
802 .firmware_name = "cdsp.mdt",
803 .ssr_name = "cdsp",
804 .sysmon_name = "cdsp",
805 .ssctl_id = 0x17,
806 .is_wpss = false,
807 .auto_boot = true,
808 .clk_ids = (const char*[]) {
809 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",
810 "q6_axim", NULL
811 },
812 .num_clks = 7,
813 .pd_names = (const char*[]) { "cx" },
814 .num_pds = 1,
815};
816
817static const struct adsp_pil_data wpss_resource_init = {
818 .crash_reason_smem = 626,
819 .firmware_name = "wpss.mdt",
820 .ssr_name = "wpss",
821 .sysmon_name = "wpss",
822 .ssctl_id = 0x19,
823 .is_wpss = true,
824 .auto_boot = false,
825 .load_state = "wpss",
826 .clk_ids = (const char*[]) {
827 "ahb_bdg", "ahb", "rscp", NULL
828 },
829 .num_clks = 3,
830 .pd_names = (const char*[]) { "cx", "mx" },
831 .num_pds = 2,
832};
833
834static const struct of_device_id adsp_of_match[] = {
835 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },
836 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },
837 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },
838 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },
839 { },
840};
841MODULE_DEVICE_TABLE(of, adsp_of_match);
842
843static struct platform_driver adsp_pil_driver = {
844 .probe = adsp_probe,
845 .remove = adsp_remove,
846 .driver = {
847 .name = "qcom_q6v5_adsp",
848 .of_match_table = adsp_of_match,
849 },
850};
851
852module_platform_driver(adsp_pil_driver);
853MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");
854MODULE_LICENSE("GPL v2");
855

source code of linux/drivers/remoteproc/qcom_q6v5_adsp.c