1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Copyright (c) 2017 Hisilicon Limited.
4	*/
5
6	#include <linux/sched/clock.h>
7	#include "hisi_sas.h"
8	#define DRV_NAME "hisi_sas_v3_hw"
9
10	/* global registers need init */
11	#define DLVRY_QUEUE_ENABLE 0x0
12	#define IOST_BASE_ADDR_LO 0x8
13	#define IOST_BASE_ADDR_HI 0xc
14	#define ITCT_BASE_ADDR_LO 0x10
15	#define ITCT_BASE_ADDR_HI 0x14
16	#define IO_BROKEN_MSG_ADDR_LO 0x18
17	#define IO_BROKEN_MSG_ADDR_HI 0x1c
18	#define PHY_CONTEXT 0x20
19	#define PHY_STATE 0x24
20	#define PHY_PORT_NUM_MA 0x28
21	#define PHY_CONN_RATE 0x30
22	#define ITCT_CLR 0x44
23	#define ITCT_CLR_EN_OFF 16
24	#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
25	#define ITCT_DEV_OFF 0
26	#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
27	#define SAS_AXI_USER3 0x50
28	#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
29	#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
30	#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
31	#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
32	#define CFG_MAX_TAG 0x68
33	#define TRANS_LOCK_ICT_TIME 0X70
34	#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
35	#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
36	#define HGC_GET_ITV_TIME 0x90
37	#define DEVICE_MSG_WORK_MODE 0x94
38	#define OPENA_WT_CONTI_TIME 0x9c
39	#define I_T_NEXUS_LOSS_TIME 0xa0
40	#define MAX_CON_TIME_LIMIT_TIME 0xa4
41	#define BUS_INACTIVE_LIMIT_TIME 0xa8
42	#define REJECT_TO_OPEN_LIMIT_TIME 0xac
43	#define CQ_INT_CONVERGE_EN 0xb0
44	#define CFG_AGING_TIME 0xbc
45	#define HGC_DFX_CFG2 0xc0
46	#define CFG_ABT_SET_QUERY_IPTT 0xd4
47	#define CFG_SET_ABORTED_IPTT_OFF 0
48	#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
49	#define CFG_SET_ABORTED_EN_OFF 12
50	#define CFG_ABT_SET_IPTT_DONE 0xd8
51	#define CFG_ABT_SET_IPTT_DONE_OFF 0
52	#define HGC_IOMB_PROC1_STATUS 0x104
53	#define HGC_LM_DFX_STATUS2 0x128
54	#define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
55	#define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
56	HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
57	#define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
58	#define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
59	HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
60	#define HGC_CQE_ECC_ADDR 0x13c
61	#define HGC_CQE_ECC_1B_ADDR_OFF 0
62	#define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
63	#define HGC_CQE_ECC_MB_ADDR_OFF 8
64	#define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
65	#define HGC_IOST_ECC_ADDR 0x140
66	#define HGC_IOST_ECC_1B_ADDR_OFF 0
67	#define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
68	#define HGC_IOST_ECC_MB_ADDR_OFF 16
69	#define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
70	#define HGC_DQE_ECC_ADDR 0x144
71	#define HGC_DQE_ECC_1B_ADDR_OFF 0
72	#define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
73	#define HGC_DQE_ECC_MB_ADDR_OFF 16
74	#define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
75	#define CHNL_INT_STATUS 0x148
76	#define TAB_DFX 0x14c
77	#define HGC_ITCT_ECC_ADDR 0x150
78	#define HGC_ITCT_ECC_1B_ADDR_OFF 0
79	#define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
80	HGC_ITCT_ECC_1B_ADDR_OFF)
81	#define HGC_ITCT_ECC_MB_ADDR_OFF 16
82	#define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
83	HGC_ITCT_ECC_MB_ADDR_OFF)
84	#define HGC_AXI_FIFO_ERR_INFO 0x154
85	#define AXI_ERR_INFO_OFF 0
86	#define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
87	#define FIFO_ERR_INFO_OFF 8
88	#define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
89	#define TAB_RD_TYPE 0x15c
90	#define INT_COAL_EN 0x19c
91	#define OQ_INT_COAL_TIME 0x1a0
92	#define OQ_INT_COAL_CNT 0x1a4
93	#define ENT_INT_COAL_TIME 0x1a8
94	#define ENT_INT_COAL_CNT 0x1ac
95	#define OQ_INT_SRC 0x1b0
96	#define OQ_INT_SRC_MSK 0x1b4
97	#define ENT_INT_SRC1 0x1b8
98	#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
99	#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
100	#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
101	#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
102	#define ENT_INT_SRC2 0x1bc
103	#define ENT_INT_SRC3 0x1c0
104	#define ENT_INT_SRC3_WP_DEPTH_OFF 8
105	#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
106	#define ENT_INT_SRC3_RP_DEPTH_OFF 10
107	#define ENT_INT_SRC3_AXI_OFF 11
108	#define ENT_INT_SRC3_FIFO_OFF 12
109	#define ENT_INT_SRC3_LM_OFF 14
110	#define ENT_INT_SRC3_ITC_INT_OFF 15
111	#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
112	#define ENT_INT_SRC3_ABT_OFF 16
113	#define ENT_INT_SRC3_DQE_POISON_OFF 18
114	#define ENT_INT_SRC3_IOST_POISON_OFF 19
115	#define ENT_INT_SRC3_ITCT_POISON_OFF 20
116	#define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21
117	#define ENT_INT_SRC_MSK1 0x1c4
118	#define ENT_INT_SRC_MSK2 0x1c8
119	#define ENT_INT_SRC_MSK3 0x1cc
120	#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
121	#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
122	#define CHNL_ENT_INT_MSK 0x1d4
123	#define HGC_COM_INT_MSK 0x1d8
124	#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
125	#define SAS_ECC_INTR 0x1e8
126	#define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
127	#define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
128	#define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
129	#define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
130	#define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4
131	#define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5
132	#define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6
133	#define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7
134	#define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8
135	#define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9
136	#define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
137	#define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
138	#define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12
139	#define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13
140	#define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14
141	#define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15
142	#define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16
143	#define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17
144	#define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18
145	#define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19
146	#define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20
147	#define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21
148	#define SAS_ECC_INTR_MSK 0x1ec
149	#define HGC_ERR_STAT_EN 0x238
150	#define CQE_SEND_CNT 0x248
151	#define DLVRY_Q_0_BASE_ADDR_LO 0x260
152	#define DLVRY_Q_0_BASE_ADDR_HI 0x264
153	#define DLVRY_Q_0_DEPTH 0x268
154	#define DLVRY_Q_0_WR_PTR 0x26c
155	#define DLVRY_Q_0_RD_PTR 0x270
156	#define HYPER_STREAM_ID_EN_CFG 0xc80
157	#define OQ0_INT_SRC_MSK 0xc90
158	#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
159	#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
160	#define COMPL_Q_0_DEPTH 0x4e8
161	#define COMPL_Q_0_WR_PTR 0x4ec
162	#define COMPL_Q_0_RD_PTR 0x4f0
163	#define HGC_RXM_DFX_STATUS14 0xae8
164	#define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
165	#define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
166	HGC_RXM_DFX_STATUS14_MEM0_OFF)
167	#define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
168	#define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
169	HGC_RXM_DFX_STATUS14_MEM1_OFF)
170	#define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
171	#define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
172	HGC_RXM_DFX_STATUS14_MEM2_OFF)
173	#define HGC_RXM_DFX_STATUS15 0xaec
174	#define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
175	#define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
176	HGC_RXM_DFX_STATUS15_MEM3_OFF)
177	#define AWQOS_AWCACHE_CFG 0xc84
178	#define ARQOS_ARCACHE_CFG 0xc88
179	#define HILINK_ERR_DFX 0xe04
180	#define SAS_GPIO_CFG_0 0x1000
181	#define SAS_GPIO_CFG_1 0x1004
182	#define SAS_GPIO_TX_0_1 0x1040
183	#define SAS_CFG_DRIVE_VLD 0x1070
184
185	/* phy registers requiring init */
186	#define PORT_BASE (0x2000)
187	#define PHY_CFG (PORT_BASE + 0x0)
188	#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
189	#define PHY_CFG_ENA_OFF 0
190	#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
191	#define PHY_CFG_DC_OPT_OFF 2
192	#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
193	#define PHY_CFG_PHY_RST_OFF 3
194	#define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
195	#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
196	#define CFG_PROG_PHY_LINK_RATE_OFF 0
197	#define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
198	#define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
199	#define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
200	#define PHY_CTRL (PORT_BASE + 0x14)
201	#define PHY_CTRL_RESET_OFF 0
202	#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
203	#define CMD_HDR_PIR_OFF 8
204	#define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF)
205	#define SERDES_CFG (PORT_BASE + 0x1c)
206	#define CFG_ALOS_CHK_DISABLE_OFF 9
207	#define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
208	#define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c)
209	#define CFG_BIST_MODE_SEL_OFF 0
210	#define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF)
211	#define CFG_LOOP_TEST_MODE_OFF 14
212	#define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF)
213	#define CFG_RX_BIST_EN_OFF 16
214	#define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF)
215	#define CFG_TX_BIST_EN_OFF 17
216	#define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF)
217	#define CFG_BIST_TEST_OFF 18
218	#define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF)
219	#define SAS_PHY_BIST_CODE (PORT_BASE + 0x30)
220	#define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34)
221	#define SAS_BIST_ERR_CNT (PORT_BASE + 0x38)
222	#define SL_CFG (PORT_BASE + 0x84)
223	#define AIP_LIMIT (PORT_BASE + 0x90)
224	#define SL_CONTROL (PORT_BASE + 0x94)
225	#define SL_CONTROL_NOTIFY_EN_OFF 0
226	#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
227	#define SL_CTA_OFF 17
228	#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
229	#define RX_PRIMS_STATUS (PORT_BASE + 0x98)
230	#define RX_BCAST_CHG_OFF 1
231	#define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
232	#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
233	#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
234	#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
235	#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
236	#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
237	#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
238	#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
239	#define TXID_AUTO (PORT_BASE + 0xb8)
240	#define CT3_OFF 1
241	#define CT3_MSK (0x1 << CT3_OFF)
242	#define TX_HARDRST_OFF 2
243	#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
244	#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
245	#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
246	#define STP_LINK_TIMER (PORT_BASE + 0x120)
247	#define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124)
248	#define CON_CFG_DRIVER (PORT_BASE + 0x130)
249	#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
250	#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
251	#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
252	#define CHL_INT0 (PORT_BASE + 0x1b4)
253	#define CHL_INT0_HOTPLUG_TOUT_OFF 0
254	#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
255	#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
256	#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
257	#define CHL_INT0_SL_PHY_ENABLE_OFF 2
258	#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
259	#define CHL_INT0_NOT_RDY_OFF 4
260	#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
261	#define CHL_INT0_PHY_RDY_OFF 5
262	#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
263	#define CHL_INT1 (PORT_BASE + 0x1b8)
264	#define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
265	#define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
266	#define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
267	#define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
268	#define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
269	#define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
270	#define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
271	#define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
272	#define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23
273	#define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24
274	#define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26
275	#define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27
276	#define CHL_INT2 (PORT_BASE + 0x1bc)
277	#define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
278	#define CHL_INT2_RX_DISP_ERR_OFF 28
279	#define CHL_INT2_RX_CODE_ERR_OFF 29
280	#define CHL_INT2_RX_INVLD_DW_OFF 30
281	#define CHL_INT2_STP_LINK_TIMEOUT_OFF 31
282	#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
283	#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
284	#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
285	#define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
286	#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
287	#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
288	#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
289	#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
290	#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
291	#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
292	#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
293	#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
294	#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
295	#define DMA_TX_STATUS_BUSY_OFF 0
296	#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
297	#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
298	#define DMA_RX_STATUS_BUSY_OFF 0
299	#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
300
301	#define COARSETUNE_TIME (PORT_BASE + 0x304)
302	#define TXDEEMPH_G1 (PORT_BASE + 0x350)
303	#define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
304	#define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
305	#define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
306	#define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
307	#define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
308	#define DFX_FIFO_CTRL (PORT_BASE + 0x3a0)
309	#define DFX_FIFO_CTRL_TRIGGER_MODE_OFF 0
310	#define DFX_FIFO_CTRL_TRIGGER_MODE_MSK (0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
311	#define DFX_FIFO_CTRL_DUMP_MODE_OFF 3
312	#define DFX_FIFO_CTRL_DUMP_MODE_MSK (0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
313	#define DFX_FIFO_CTRL_SIGNAL_SEL_OFF 6
314	#define DFX_FIFO_CTRL_SIGNAL_SEL_MSK (0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
315	#define DFX_FIFO_CTRL_DUMP_DISABLE_OFF 10
316	#define DFX_FIFO_CTRL_DUMP_DISABLE_MSK (0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
317	#define DFX_FIFO_TRIGGER (PORT_BASE + 0x3a4)
318	#define DFX_FIFO_TRIGGER_MSK (PORT_BASE + 0x3a8)
319	#define DFX_FIFO_DUMP_MSK (PORT_BASE + 0x3aC)
320	#define DFX_FIFO_RD_DATA (PORT_BASE + 0x3b0)
321
322	#define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
323	#if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
324	#error Max ITCT exceeded
325	#endif
326
327	#define AXI_MASTER_CFG_BASE (0x5000)
328	#define AM_CTRL_GLOBAL (0x0)
329	#define AM_CTRL_SHUTDOWN_REQ_OFF 0
330	#define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
331	#define AM_CURR_TRANS_RETURN (0x150)
332
333	#define AM_CFG_MAX_TRANS (0x5010)
334	#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
335	#define AXI_CFG (0x5100)
336	#define AM_ROB_ECC_ERR_ADDR (0x510c)
337	#define AM_ROB_ECC_ERR_ADDR_OFF 0
338	#define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
339
340	/* RAS registers need init */
341	#define RAS_BASE (0x6000)
342	#define SAS_RAS_INTR0 (RAS_BASE)
343	#define SAS_RAS_INTR1 (RAS_BASE + 0x04)
344	#define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08)
345	#define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c)
346	#define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c)
347	#define SAS_RAS_INTR2 (RAS_BASE + 0x20)
348	#define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24)
349
350	/* HW dma structures */
351	/* Delivery queue header */
352	/* dw0 */
353	#define CMD_HDR_ABORT_FLAG_OFF 0
354	#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
355	#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
356	#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
357	#define CMD_HDR_RESP_REPORT_OFF 5
358	#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
359	#define CMD_HDR_TLR_CTRL_OFF 6
360	#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
361	#define CMD_HDR_PORT_OFF 18
362	#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
363	#define CMD_HDR_PRIORITY_OFF 27
364	#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
365	#define CMD_HDR_CMD_OFF 29
366	#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
367	/* dw1 */
368	#define CMD_HDR_UNCON_CMD_OFF 3
369	#define CMD_HDR_DIR_OFF 5
370	#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
371	#define CMD_HDR_RESET_OFF 7
372	#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
373	#define CMD_HDR_VDTL_OFF 10
374	#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
375	#define CMD_HDR_FRAME_TYPE_OFF 11
376	#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
377	#define CMD_HDR_DEV_ID_OFF 16
378	#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
379	/* dw2 */
380	#define CMD_HDR_CFL_OFF 0
381	#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
382	#define CMD_HDR_NCQ_TAG_OFF 10
383	#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
384	#define CMD_HDR_MRFL_OFF 15
385	#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
386	#define CMD_HDR_SG_MOD_OFF 24
387	#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
388	/* dw3 */
389	#define CMD_HDR_IPTT_OFF 0
390	#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
391	/* dw6 */
392	#define CMD_HDR_DIF_SGL_LEN_OFF 0
393	#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
394	#define CMD_HDR_DATA_SGL_LEN_OFF 16
395	#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
396	/* dw7 */
397	#define CMD_HDR_ADDR_MODE_SEL_OFF 15
398	#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
399	#define CMD_HDR_ABORT_IPTT_OFF 16
400	#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
401
402	/* Completion header */
403	/* dw0 */
404	#define CMPLT_HDR_CMPLT_OFF 0
405	#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
406	#define CMPLT_HDR_ERROR_PHASE_OFF 2
407	#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
408	/* bit[9:2] Error Phase */
409	#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF \
410	8
411	#define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK \
412	(0x1 << ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF)
413	#define CMPLT_HDR_RSPNS_XFRD_OFF 10
414	#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
415	#define CMPLT_HDR_RSPNS_GOOD_OFF 11
416	#define CMPLT_HDR_RSPNS_GOOD_MSK (0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
417	#define CMPLT_HDR_ERX_OFF 12
418	#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
419	#define CMPLT_HDR_ABORT_STAT_OFF 13
420	#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
421	/* abort_stat */
422	#define STAT_IO_NOT_VALID 0x1
423	#define STAT_IO_NO_DEVICE 0x2
424	#define STAT_IO_COMPLETE 0x3
425	#define STAT_IO_ABORTED 0x4
426	/* dw1 */
427	#define CMPLT_HDR_IPTT_OFF 0
428	#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
429	#define CMPLT_HDR_DEV_ID_OFF 16
430	#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
431	/* dw3 */
432	#define SATA_DISK_IN_ERROR_STATUS_OFF 8
433	#define SATA_DISK_IN_ERROR_STATUS_MSK (0x1 << SATA_DISK_IN_ERROR_STATUS_OFF)
434	#define CMPLT_HDR_SATA_DISK_ERR_OFF 16
435	#define CMPLT_HDR_SATA_DISK_ERR_MSK (0x1 << CMPLT_HDR_SATA_DISK_ERR_OFF)
436	#define CMPLT_HDR_IO_IN_TARGET_OFF 17
437	#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
438	/* bit[23:18] ERR_FIS_ATA_STATUS */
439	#define FIS_ATA_STATUS_ERR_OFF 18
440	#define FIS_ATA_STATUS_ERR_MSK (0x1 << FIS_ATA_STATUS_ERR_OFF)
441	#define FIS_TYPE_SDB_OFF 31
442	#define FIS_TYPE_SDB_MSK (0x1 << FIS_TYPE_SDB_OFF)
443
444	/* ITCT header */
445	/* qw0 */
446	#define ITCT_HDR_DEV_TYPE_OFF 0
447	#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
448	#define ITCT_HDR_VALID_OFF 2
449	#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
450	#define ITCT_HDR_MCR_OFF 5
451	#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
452	#define ITCT_HDR_VLN_OFF 9
453	#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
454	#define ITCT_HDR_SMP_TIMEOUT_OFF 16
455	#define ITCT_HDR_AWT_CONTINUE_OFF 25
456	#define ITCT_HDR_PORT_ID_OFF 28
457	#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
458	/* qw2 */
459	#define ITCT_HDR_INLT_OFF 0
460	#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
461	#define ITCT_HDR_RTOLT_OFF 48
462	#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
463
464	struct hisi_sas_protect_iu_v3_hw {
465	u32 dw0;
466	u32 lbrtcv;
467	u32 lbrtgv;
468	u32 dw3;
469	u32 dw4;
470	u32 dw5;
471	u32 rsv;
472	};
473
474	struct hisi_sas_complete_v3_hdr {
475	__le32 dw0;
476	__le32 dw1;
477	__le32 act;
478	__le32 dw3;
479	};
480
481	struct hisi_sas_err_record_v3 {
482	/* dw0 */
483	__le32 trans_tx_fail_type;
484
485	/* dw1 */
486	__le32 trans_rx_fail_type;
487
488	/* dw2 */
489	__le16 dma_tx_err_type;
490	__le16 sipc_rx_err_type;
491
492	/* dw3 */
493	__le32 dma_rx_err_type;
494	};
495
496	#define RX_DATA_LEN_UNDERFLOW_OFF 6
497	#define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
498
499	#define RX_FIS_STATUS_ERR_OFF 0
500	#define RX_FIS_STATUS_ERR_MSK (1 << RX_FIS_STATUS_ERR_OFF)
501
502	#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
503	#define HISI_SAS_MSI_COUNT_V3_HW 32
504
505	#define DIR_NO_DATA 0
506	#define DIR_TO_INI 1
507	#define DIR_TO_DEVICE 2
508	#define DIR_RESERVED 3
509
510	#define FIS_CMD_IS_UNCONSTRAINED(fis) \
511	((fis.command == ATA_CMD_READ_LOG_EXT) || \
512	(fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
513	((fis.command == ATA_CMD_DEV_RESET) && \
514	((fis.control & ATA_SRST) != 0)))
515
516	#define T10_INSRT_EN_OFF 0
517	#define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF)
518	#define T10_RMV_EN_OFF 1
519	#define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF)
520	#define T10_RPLC_EN_OFF 2
521	#define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF)
522	#define T10_CHK_EN_OFF 3
523	#define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF)
524	#define INCR_LBRT_OFF 5
525	#define INCR_LBRT_MSK (1 << INCR_LBRT_OFF)
526	#define USR_DATA_BLOCK_SZ_OFF 20
527	#define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF)
528	#define T10_CHK_MSK_OFF 16
529	#define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
530	#define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
531
532	#define BASE_VECTORS_V3_HW 16
533	#define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
534
535	#define CHNL_INT_STS_MSK 0xeeeeeeee
536	#define CHNL_INT_STS_PHY_MSK 0xe
537	#define CHNL_INT_STS_INT0_MSK BIT(1)
538	#define CHNL_INT_STS_INT1_MSK BIT(2)
539	#define CHNL_INT_STS_INT2_MSK BIT(3)
540	#define CHNL_WIDTH 4
541
542	#define BAR_NO_V3_HW 5
543
544	enum {
545	DSM_FUNC_ERR_HANDLE_MSI = 0,
546	};
547
548	static bool hisi_sas_intr_conv;
549	MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
550
551	/* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
552	static int prot_mask;
553	module_param(prot_mask, int, 0444);
554	MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
555
556	/* the index of iopoll queues are bigger than interrupt queues' */
557	static int experimental_iopoll_q_cnt;
558	module_param(experimental_iopoll_q_cnt, int, 0444);
559	MODULE_PARM_DESC(experimental_iopoll_q_cnt, "number of queues to be used as poll mode, def=0");
560
561	static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
562
563	static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
564	{
565	void __iomem *regs = hisi_hba->regs + off;
566
567	return readl(addr: regs);
568	}
569
570	static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
571	{
572	void __iomem *regs = hisi_hba->regs + off;
573
574	writel(val, addr: regs);
575	}
576
577	static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
578	u32 off, u32 val)
579	{
580	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
581
582	writel(val, addr: regs);
583	}
584
585	static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
586	int phy_no, u32 off)
587	{
588	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
589
590	return readl(addr: regs);
591	}
592
593	#define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
594	timeout_us) \
595	({ \
596	void __iomem *regs = hisi_hba->regs + off; \
597	readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
598	})
599
600	#define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
601	timeout_us) \
602	({ \
603	void __iomem *regs = hisi_hba->regs + off; \
604	readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
605	})
606
607	static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba)
608	{
609	int i;
610
611	for (i = 0; i < hisi_hba->queue_count; i++)
612	hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, val: 0);
613
614	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, val: 0xfefefefe);
615	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, val: 0xfefefefe);
616	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, val: 0xffc220ff);
617	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, val: 0x155555);
618
619	for (i = 0; i < hisi_hba->n_phy; i++) {
620	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT1_MSK, val: 0xf2057fff);
621	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2_MSK, val: 0xffffbfe);
622	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_NOT_RDY_MSK, val: 0x0);
623	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_PHY_ENA_MSK, val: 0x0);
624	hisi_sas_phy_write32(hisi_hba, phy_no: i, SL_RX_BCAST_CHK_MSK, val: 0x0);
625	}
626	}
627
628	static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
629	{
630	struct pci_dev *pdev = hisi_hba->pci_dev;
631	int i, j;
632
633	/* Global registers init */
634	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
635	val: (u32)((1ULL << hisi_hba->queue_count) - 1));
636	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, val: 0xfff0400);
637	/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */
638	hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, val: 0x4A817C80);
639	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, val: 0x108);
640	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, val: 0x1);
641	hisi_sas_write32(hisi_hba, INT_COAL_EN, val: 0x1);
642	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, val: 0x1);
643	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, val: 0x1);
644	hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
645	val: hisi_sas_intr_conv);
646	hisi_sas_write32(hisi_hba, OQ_INT_SRC, val: 0xffff);
647	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, val: 0xffffffff);
648	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, val: 0xffffffff);
649	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, val: 0xffffffff);
650	hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, val: 0x0);
651	hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, val: 0x0);
652	hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, val: 0x0);
653	hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, val: 0xf0f0);
654	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, val: 0xf0f0);
655	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, val: 1);
656
657	if (pdev->revision < 0x30)
658	hisi_sas_write32(hisi_hba, SAS_AXI_USER3, val: 0);
659
660	interrupt_enable_v3_hw(hisi_hba);
661	for (i = 0; i < hisi_hba->n_phy; i++) {
662	enum sas_linkrate max;
663	struct hisi_sas_phy *phy = &hisi_hba->phy[i];
664	struct asd_sas_phy *sas_phy = &phy->sas_phy;
665	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no: i,
666	PROG_PHY_LINK_RATE);
667
668	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
669	if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
670	SAS_LINK_RATE_1_5_GBPS))
671	max = SAS_LINK_RATE_12_0_GBPS;
672	else
673	max = sas_phy->phy->maximum_linkrate;
674	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
675	hisi_sas_phy_write32(hisi_hba, phy_no: i, PROG_PHY_LINK_RATE,
676	val: prog_phy_link_rate);
677	hisi_sas_phy_write32(hisi_hba, phy_no: i, SAS_RX_TRAIN_TIMER, val: 0x13e80);
678	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT0, val: 0xffffffff);
679	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT1, val: 0xffffffff);
680	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2, val: 0xffffffff);
681	hisi_sas_phy_write32(hisi_hba, phy_no: i, RXOP_CHECK_CFG_H, val: 0x1000);
682	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHY_CTRL_RDY_MSK, val: 0x0);
683	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_DWS_RESET_MSK, val: 0x0);
684	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_OOB_RESTART_MSK, val: 0x1);
685	hisi_sas_phy_write32(hisi_hba, phy_no: i, STP_LINK_TIMER, val: 0x7f7a120);
686	hisi_sas_phy_write32(hisi_hba, phy_no: i, CON_CFG_DRIVER, val: 0x2a0a01);
687	hisi_sas_phy_write32(hisi_hba, phy_no: i, SAS_EC_INT_COAL_TIME,
688	val: 0x30f4240);
689	hisi_sas_phy_write32(hisi_hba, phy_no: i, AIP_LIMIT, val: 0x2ffff);
690
691	/* set value through firmware for 920B and later version */
692	if (pdev->revision < 0x30) {
693	hisi_sas_phy_write32(hisi_hba, phy_no: i, SAS_SSP_CON_TIMER_CFG, val: 0x32);
694	hisi_sas_phy_write32(hisi_hba, phy_no: i, SERDES_CFG, val: 0xffc00);
695	/* used for 12G negotiate */
696	hisi_sas_phy_write32(hisi_hba, phy_no: i, COARSETUNE_TIME, val: 0x1e);
697	}
698
699	/* get default FFE configuration for BIST */
700	for (j = 0; j < FFE_CFG_MAX; j++) {
701	u32 val = hisi_sas_phy_read32(hisi_hba, phy_no: i,
702	TXDEEMPH_G1 + (j * 0x4));
703	hisi_hba->debugfs_bist_ffe[i][j] = val;
704	}
705	}
706
707	for (i = 0; i < hisi_hba->queue_count; i++) {
708	/* Delivery queue */
709	hisi_sas_write32(hisi_hba,
710	DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
711	upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
712
713	hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
714	lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
715
716	hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
717	HISI_SAS_QUEUE_SLOTS);
718
719	/* Completion queue */
720	hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
721	upper_32_bits(hisi_hba->complete_hdr_dma[i]));
722
723	hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
724	lower_32_bits(hisi_hba->complete_hdr_dma[i]));
725
726	hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
727	HISI_SAS_QUEUE_SLOTS);
728	}
729
730	/* itct */
731	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
732	lower_32_bits(hisi_hba->itct_dma));
733
734	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
735	upper_32_bits(hisi_hba->itct_dma));
736
737	/* iost */
738	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
739	lower_32_bits(hisi_hba->iost_dma));
740
741	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
742	upper_32_bits(hisi_hba->iost_dma));
743
744	/* breakpoint */
745	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
746	lower_32_bits(hisi_hba->breakpoint_dma));
747
748	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
749	upper_32_bits(hisi_hba->breakpoint_dma));
750
751	/* SATA broken msg */
752	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
753	lower_32_bits(hisi_hba->sata_breakpoint_dma));
754
755	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
756	upper_32_bits(hisi_hba->sata_breakpoint_dma));
757
758	/* SATA initial fis */
759	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
760	lower_32_bits(hisi_hba->initial_fis_dma));
761
762	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
763	upper_32_bits(hisi_hba->initial_fis_dma));
764
765	/* RAS registers init */
766	hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, val: 0x0);
767	hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, val: 0x0);
768	hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, val: 0x0);
769	hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, val: 0x0);
770
771	/* LED registers init */
772	hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, val: 0x80000ff);
773	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, val: 0x80808080);
774	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, val: 0x80808080);
775	/* Configure blink generator rate A to 1Hz and B to 4Hz */
776	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, val: 0x121700);
777	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, val: 0x800000);
778	}
779
780	static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
781	{
782	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
783
784	cfg &= ~PHY_CFG_DC_OPT_MSK;
785	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
786	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg);
787	}
788
789	static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
790	{
791	struct sas_identify_frame identify_frame;
792	u32 *identify_buffer;
793
794	memset(&identify_frame, 0, sizeof(identify_frame));
795	identify_frame.dev_type = SAS_END_DEVICE;
796	identify_frame.frame_type = 0;
797	identify_frame._un1 = 1;
798	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
799	identify_frame.target_bits = SAS_PROTOCOL_NONE;
800	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
801	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
802	identify_frame.phy_id = phy_no;
803	identify_buffer = (u32 *)(&identify_frame);
804
805	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
806	__swab32(identify_buffer[0]));
807	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
808	__swab32(identify_buffer[1]));
809	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
810	__swab32(identify_buffer[2]));
811	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
812	__swab32(identify_buffer[3]));
813	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
814	__swab32(identify_buffer[4]));
815	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
816	__swab32(identify_buffer[5]));
817	}
818
819	static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
820	struct hisi_sas_device *sas_dev)
821	{
822	struct domain_device *device = sas_dev->sas_device;
823	struct device *dev = hisi_hba->dev;
824	u64 qw0, device_id = sas_dev->device_id;
825	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
826	struct domain_device *parent_dev = device->parent;
827	struct asd_sas_port *sas_port = device->port;
828	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
829	u64 sas_addr;
830
831	memset(itct, 0, sizeof(*itct));
832
833	/* qw0 */
834	qw0 = 0;
835	switch (sas_dev->dev_type) {
836	case SAS_END_DEVICE:
837	case SAS_EDGE_EXPANDER_DEVICE:
838	case SAS_FANOUT_EXPANDER_DEVICE:
839	qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
840	break;
841	case SAS_SATA_DEV:
842	case SAS_SATA_PENDING:
843	if (parent_dev && dev_is_expander(type: parent_dev->dev_type))
844	qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
845	else
846	qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
847	break;
848	default:
849	dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
850	sas_dev->dev_type);
851	}
852
853	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
854	(device->linkrate << ITCT_HDR_MCR_OFF) |
855	(1 << ITCT_HDR_VLN_OFF) |
856	(0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
857	(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
858	(port->id << ITCT_HDR_PORT_ID_OFF));
859	itct->qw0 = cpu_to_le64(qw0);
860
861	/* qw1 */
862	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
863	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
864
865	/* qw2 */
866	if (!dev_is_sata(dev: device))
867	itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
868	(0x1ULL << ITCT_HDR_RTOLT_OFF));
869	}
870
871	static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
872	struct hisi_sas_device *sas_dev)
873	{
874	DECLARE_COMPLETION_ONSTACK(completion);
875	u64 dev_id = sas_dev->device_id;
876	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
877	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
878	struct device *dev = hisi_hba->dev;
879
880	sas_dev->completion = &completion;
881
882	/* clear the itct interrupt state */
883	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
884	hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
885	ENT_INT_SRC3_ITC_INT_MSK);
886
887	/* clear the itct table */
888	reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
889	hisi_sas_write32(hisi_hba, ITCT_CLR, val: reg_val);
890
891	if (!wait_for_completion_timeout(x: sas_dev->completion,
892	HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
893	dev_warn(dev, "failed to clear ITCT\n");
894	return -ETIMEDOUT;
895	}
896
897	memset(itct, 0, sizeof(struct hisi_sas_itct));
898	return 0;
899	}
900
901	static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
902	struct domain_device *device)
903	{
904	struct hisi_sas_slot *slot, *slot2;
905	struct hisi_sas_device *sas_dev = device->lldd_dev;
906	u32 cfg_abt_set_query_iptt;
907
908	cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
909	CFG_ABT_SET_QUERY_IPTT);
910	spin_lock(lock: &sas_dev->lock);
911	list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
912	cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
913	cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
914	(slot->idx << CFG_SET_ABORTED_IPTT_OFF);
915	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
916	val: cfg_abt_set_query_iptt);
917	}
918	spin_unlock(lock: &sas_dev->lock);
919	cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
920	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
921	val: cfg_abt_set_query_iptt);
922	hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
923	val: 1 << CFG_ABT_SET_IPTT_DONE_OFF);
924	}
925
926	static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
927	{
928	struct device *dev = hisi_hba->dev;
929	int ret;
930	u32 val;
931
932	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, val: 0);
933
934	/* Disable all of the PHYs */
935	hisi_sas_stop_phys(hisi_hba);
936	udelay(50);
937
938	/* Ensure axi bus idle */
939	ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
940	20000, 1000000);
941	if (ret) {
942	dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
943	return -EIO;
944	}
945
946	if (ACPI_HANDLE(dev)) {
947	acpi_status s;
948
949	s = acpi_evaluate_object(ACPI_HANDLE(dev), pathname: "_RST", NULL, NULL);
950	if (ACPI_FAILURE(s)) {
951	dev_err(dev, "Reset failed\n");
952	return -EIO;
953	}
954	} else {
955	dev_err(dev, "no reset method!\n");
956	return -EINVAL;
957	}
958
959	return 0;
960	}
961
962	static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
963	{
964	struct device *dev = hisi_hba->dev;
965	struct acpi_device *acpi_dev;
966	union acpi_object *obj;
967	guid_t guid;
968	int rc;
969
970	rc = reset_hw_v3_hw(hisi_hba);
971	if (rc) {
972	dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
973	return rc;
974	}
975
976	msleep(msecs: 100);
977	init_reg_v3_hw(hisi_hba);
978
979	if (guid_parse(uuid: "D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", u: &guid)) {
980	dev_err(dev, "Parse GUID failed\n");
981	return -EINVAL;
982	}
983
984	/*
985	* This DSM handles some hardware-related configurations:
986	* 1. Switch over to MSI error handling in kernel
987	* 2. BIOS *may* reset some register values through this method
988	*/
989	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), guid: &guid, rev: 0,
990	func: DSM_FUNC_ERR_HANDLE_MSI, NULL);
991	if (!obj)
992	dev_warn(dev, "can not find DSM method, ignore\n");
993	else
994	ACPI_FREE(obj);
995
996	acpi_dev = ACPI_COMPANION(dev);
997	if (!acpi_device_power_manageable(adev: acpi_dev))
998	dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
999	return 0;
1000	}
1001
1002	static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1003	{
1004	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1005
1006	cfg |= PHY_CFG_ENA_MSK;
1007	cfg &= ~PHY_CFG_PHY_RST_MSK;
1008	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg);
1009	}
1010
1011	static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1012	{
1013	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1014	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1015	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1016	BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1017	BIT(CHL_INT2_RX_INVLD_DW_OFF);
1018	u32 state;
1019
1020	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, val: msk | irq_msk);
1021
1022	cfg &= ~PHY_CFG_ENA_MSK;
1023	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg);
1024
1025	mdelay(50);
1026
1027	state = hisi_sas_read32(hisi_hba, PHY_STATE);
1028	if (state & BIT(phy_no)) {
1029	cfg |= PHY_CFG_PHY_RST_MSK;
1030	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, val: cfg);
1031	}
1032
1033	udelay(1);
1034
1035	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1036	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1037	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1038
1039	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, val: msk);
1040	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, val: irq_msk);
1041	}
1042
1043	static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1044	{
1045	config_id_frame_v3_hw(hisi_hba, phy_no);
1046	config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1047	enable_phy_v3_hw(hisi_hba, phy_no);
1048	}
1049
1050	static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1051	{
1052	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1053	u32 txid_auto;
1054
1055	hisi_sas_phy_enable(hisi_hba, phy_no, enable: 0);
1056	if (phy->identify.device_type == SAS_END_DEVICE) {
1057	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1058	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1059	val: txid_auto | TX_HARDRST_MSK);
1060	}
1061	msleep(msecs: 100);
1062	hisi_sas_phy_enable(hisi_hba, phy_no, enable: 1);
1063	}
1064
1065	static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1066	{
1067	return SAS_LINK_RATE_12_0_GBPS;
1068	}
1069
1070	static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1071	{
1072	int i;
1073
1074	for (i = 0; i < hisi_hba->n_phy; i++) {
1075	struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1076	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1077
1078	if (!sas_phy->phy->enabled)
1079	continue;
1080
1081	hisi_sas_phy_enable(hisi_hba, phy_no: i, enable: 1);
1082	}
1083	}
1084
1085	static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1086	{
1087	u32 sl_control;
1088
1089	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1090	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1091	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, val: sl_control);
1092	msleep(msecs: 1);
1093	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1094	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1095	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, val: sl_control);
1096	}
1097
1098	static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1099	{
1100	int i, bitmap = 0;
1101	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1102	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1103
1104	for (i = 0; i < hisi_hba->n_phy; i++)
1105	if (phy_state & BIT(i))
1106	if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1107	bitmap |= BIT(i);
1108
1109	return bitmap;
1110	}
1111
1112	static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1113	{
1114	struct hisi_hba *hisi_hba = dq->hisi_hba;
1115	struct hisi_sas_slot *s, *s1, *s2 = NULL;
1116	int dlvry_queue = dq->id;
1117	int wp;
1118
1119	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1120	if (!s->ready)
1121	break;
1122	s2 = s;
1123	list_del(entry: &s->delivery);
1124	}
1125
1126	if (!s2)
1127	return;
1128
1129	/*
1130	* Ensure that memories for slots built on other CPUs is observed.
1131	*/
1132	smp_rmb();
1133	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1134
1135	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), val: wp);
1136	}
1137
1138	static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1139	struct hisi_sas_slot *slot,
1140	struct hisi_sas_cmd_hdr *hdr,
1141	struct scatterlist *scatter,
1142	int n_elem)
1143	{
1144	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1145	struct scatterlist *sg;
1146	int i;
1147
1148	for_each_sg(scatter, sg, n_elem, i) {
1149	struct hisi_sas_sge *entry = &sge_page->sge[i];
1150
1151	entry->addr = cpu_to_le64(sg_dma_address(sg));
1152	entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1153	entry->data_len = cpu_to_le32(sg_dma_len(sg));
1154	entry->data_off = 0;
1155	}
1156
1157	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1158
1159	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1160	}
1161
1162	static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1163	struct hisi_sas_slot *slot,
1164	struct hisi_sas_cmd_hdr *hdr,
1165	struct scatterlist *scatter,
1166	int n_elem)
1167	{
1168	struct hisi_sas_sge_dif_page *sge_dif_page;
1169	struct scatterlist *sg;
1170	int i;
1171
1172	sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1173
1174	for_each_sg(scatter, sg, n_elem, i) {
1175	struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1176
1177	entry->addr = cpu_to_le64(sg_dma_address(sg));
1178	entry->page_ctrl_0 = 0;
1179	entry->page_ctrl_1 = 0;
1180	entry->data_len = cpu_to_le32(sg_dma_len(sg));
1181	entry->data_off = 0;
1182	}
1183
1184	hdr->dif_prd_table_addr =
1185	cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1186
1187	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1188	}
1189
1190	static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1191	{
1192	unsigned char prot_flags = scsi_cmnd->prot_flags;
1193
1194	if (prot_flags & SCSI_PROT_REF_CHECK)
1195	return T10_CHK_APP_TAG_MSK;
1196	return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1197	}
1198
1199	static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1200	struct hisi_sas_protect_iu_v3_hw *prot)
1201	{
1202	unsigned char prot_op = scsi_get_prot_op(scmd: scsi_cmnd);
1203	unsigned int interval = scsi_prot_interval(scmd: scsi_cmnd);
1204	u32 lbrt_chk_val = t10_pi_ref_tag(rq: scsi_cmd_to_rq(scmd: scsi_cmnd));
1205
1206	switch (prot_op) {
1207	case SCSI_PROT_READ_INSERT:
1208	prot->dw0 |= T10_INSRT_EN_MSK;
1209	prot->lbrtgv = lbrt_chk_val;
1210	break;
1211	case SCSI_PROT_READ_STRIP:
1212	prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1213	prot->lbrtcv = lbrt_chk_val;
1214	prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1215	break;
1216	case SCSI_PROT_READ_PASS:
1217	prot->dw0 |= T10_CHK_EN_MSK;
1218	prot->lbrtcv = lbrt_chk_val;
1219	prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1220	break;
1221	case SCSI_PROT_WRITE_INSERT:
1222	prot->dw0 |= T10_INSRT_EN_MSK;
1223	prot->lbrtgv = lbrt_chk_val;
1224	break;
1225	case SCSI_PROT_WRITE_STRIP:
1226	prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1227	prot->lbrtcv = lbrt_chk_val;
1228	break;
1229	case SCSI_PROT_WRITE_PASS:
1230	prot->dw0 |= T10_CHK_EN_MSK;
1231	prot->lbrtcv = lbrt_chk_val;
1232	prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1233	break;
1234	default:
1235	WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1236	break;
1237	}
1238
1239	switch (interval) {
1240	case 512:
1241	break;
1242	case 4096:
1243	prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1244	break;
1245	case 520:
1246	prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1247	break;
1248	default:
1249	WARN(1, "protection interval (0x%x) invalid\n",
1250	interval);
1251	break;
1252	}
1253
1254	prot->dw0 |= INCR_LBRT_MSK;
1255	}
1256
1257	static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1258	struct hisi_sas_slot *slot)
1259	{
1260	struct sas_task *task = slot->task;
1261	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1262	struct domain_device *device = task->dev;
1263	struct hisi_sas_device *sas_dev = device->lldd_dev;
1264	struct hisi_sas_port *port = slot->port;
1265	struct sas_ssp_task *ssp_task = &task->ssp_task;
1266	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1267	struct sas_tmf_task *tmf = slot->tmf;
1268	int has_data = 0, priority = !!tmf;
1269	unsigned char prot_op;
1270	u8 *buf_cmd;
1271	u32 dw1 = 0, dw2 = 0, len = 0;
1272
1273	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1274	(2 << CMD_HDR_TLR_CTRL_OFF) |
1275	(port->id << CMD_HDR_PORT_OFF) |
1276	(priority << CMD_HDR_PRIORITY_OFF) |
1277	(1 << CMD_HDR_CMD_OFF)); /* ssp */
1278
1279	dw1 = 1 << CMD_HDR_VDTL_OFF;
1280	if (tmf) {
1281	dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1282	dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1283	} else {
1284	prot_op = scsi_get_prot_op(scmd: scsi_cmnd);
1285	dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1286	switch (scsi_cmnd->sc_data_direction) {
1287	case DMA_TO_DEVICE:
1288	has_data = 1;
1289	dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1290	break;
1291	case DMA_FROM_DEVICE:
1292	has_data = 1;
1293	dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1294	break;
1295	default:
1296	dw1 &= ~CMD_HDR_DIR_MSK;
1297	}
1298	}
1299
1300	/* map itct entry */
1301	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1302
1303	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1304	+ 3) / 4) << CMD_HDR_CFL_OFF) |
1305	((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1306	(2 << CMD_HDR_SG_MOD_OFF);
1307	hdr->dw2 = cpu_to_le32(dw2);
1308	hdr->transfer_tags = cpu_to_le32(slot->idx);
1309
1310	if (has_data) {
1311	prep_prd_sge_v3_hw(hisi_hba, slot, hdr, scatter: task->scatter,
1312	n_elem: slot->n_elem);
1313
1314	if (scsi_prot_sg_count(cmd: scsi_cmnd))
1315	prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1316	scatter: scsi_prot_sglist(cmd: scsi_cmnd),
1317	n_elem: slot->n_elem_dif);
1318	}
1319
1320	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1321	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1322
1323	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1324	sizeof(struct ssp_frame_hdr);
1325
1326	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1327	if (!tmf) {
1328	buf_cmd[9] = ssp_task->task_attr;
1329	memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1330	} else {
1331	buf_cmd[10] = tmf->tmf;
1332	switch (tmf->tmf) {
1333	case TMF_ABORT_TASK:
1334	case TMF_QUERY_TASK:
1335	buf_cmd[12] =
1336	(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1337	buf_cmd[13] =
1338	tmf->tag_of_task_to_be_managed & 0xff;
1339	break;
1340	default:
1341	break;
1342	}
1343	}
1344
1345	if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1346	struct hisi_sas_protect_iu_v3_hw prot;
1347	u8 *buf_cmd_prot;
1348
1349	hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1350	dw1 |= CMD_HDR_PIR_MSK;
1351	buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1352	sizeof(struct ssp_frame_hdr) +
1353	sizeof(struct ssp_command_iu);
1354
1355	memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1356	fill_prot_v3_hw(scsi_cmnd, prot: &prot);
1357	memcpy(buf_cmd_prot, &prot,
1358	sizeof(struct hisi_sas_protect_iu_v3_hw));
1359	/*
1360	* For READ, we need length of info read to memory, while for
1361	* WRITE we need length of data written to the disk.
1362	*/
1363	if (prot_op == SCSI_PROT_WRITE_INSERT ||
1364	prot_op == SCSI_PROT_READ_INSERT ||
1365	prot_op == SCSI_PROT_WRITE_PASS ||
1366	prot_op == SCSI_PROT_READ_PASS) {
1367	unsigned int interval = scsi_prot_interval(scmd: scsi_cmnd);
1368	unsigned int ilog2_interval = ilog2(interval);
1369
1370	len = (task->total_xfer_len >> ilog2_interval) * 8;
1371	}
1372	}
1373
1374	hdr->dw1 = cpu_to_le32(dw1);
1375
1376	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1377	}
1378
1379	static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1380	struct hisi_sas_slot *slot)
1381	{
1382	struct sas_task *task = slot->task;
1383	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1384	struct domain_device *device = task->dev;
1385	struct hisi_sas_port *port = slot->port;
1386	struct scatterlist *sg_req;
1387	struct hisi_sas_device *sas_dev = device->lldd_dev;
1388	dma_addr_t req_dma_addr;
1389	unsigned int req_len;
1390
1391	/* req */
1392	sg_req = &task->smp_task.smp_req;
1393	req_len = sg_dma_len(sg_req);
1394	req_dma_addr = sg_dma_address(sg_req);
1395
1396	/* create header */
1397	/* dw0 */
1398	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1399	(1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1400	(2 << CMD_HDR_CMD_OFF)); /* smp */
1401
1402	/* map itct entry */
1403	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1404	(1 << CMD_HDR_FRAME_TYPE_OFF) |
1405	(DIR_NO_DATA << CMD_HDR_DIR_OFF));
1406
1407	/* dw2 */
1408	hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1409	(HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1410	CMD_HDR_MRFL_OFF));
1411
1412	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1413
1414	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1415	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1416	}
1417
1418	static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1419	struct hisi_sas_slot *slot)
1420	{
1421	struct sas_task *task = slot->task;
1422	struct domain_device *device = task->dev;
1423	struct domain_device *parent_dev = device->parent;
1424	struct hisi_sas_device *sas_dev = device->lldd_dev;
1425	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1426	struct asd_sas_port *sas_port = device->port;
1427	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1428	u8 *buf_cmd;
1429	int has_data = 0, hdr_tag = 0;
1430	u32 dw1 = 0, dw2 = 0;
1431
1432	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1433	if (parent_dev && dev_is_expander(type: parent_dev->dev_type))
1434	hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1435	else
1436	hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1437
1438	switch (task->data_dir) {
1439	case DMA_TO_DEVICE:
1440	has_data = 1;
1441	dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1442	break;
1443	case DMA_FROM_DEVICE:
1444	has_data = 1;
1445	dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1446	break;
1447	default:
1448	dw1 &= ~CMD_HDR_DIR_MSK;
1449	}
1450
1451	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1452	(task->ata_task.fis.control & ATA_SRST))
1453	dw1 |= 1 << CMD_HDR_RESET_OFF;
1454
1455	dw1 |= (hisi_sas_get_ata_protocol(
1456	fis: &task->ata_task.fis, direction: task->data_dir))
1457	<< CMD_HDR_FRAME_TYPE_OFF;
1458	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1459
1460	if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1461	dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1462
1463	hdr->dw1 = cpu_to_le32(dw1);
1464
1465	/* dw2 */
1466	if (task->ata_task.use_ncq) {
1467	struct ata_queued_cmd *qc = task->uldd_task;
1468
1469	hdr_tag = qc->tag;
1470	task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1471	dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1472	}
1473
1474	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1475	2 << CMD_HDR_SG_MOD_OFF;
1476	hdr->dw2 = cpu_to_le32(dw2);
1477
1478	/* dw3 */
1479	hdr->transfer_tags = cpu_to_le32(slot->idx);
1480
1481	if (has_data)
1482	prep_prd_sge_v3_hw(hisi_hba, slot, hdr, scatter: task->scatter,
1483	n_elem: slot->n_elem);
1484
1485	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1486	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1487	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1488
1489	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1490
1491	if (likely(!task->ata_task.device_control_reg_update))
1492	task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1493	/* fill in command FIS */
1494	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1495	}
1496
1497	static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1498	struct hisi_sas_slot *slot)
1499	{
1500	struct sas_task *task = slot->task;
1501	struct sas_internal_abort_task *abort = &task->abort_task;
1502	struct domain_device *dev = task->dev;
1503	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1504	struct hisi_sas_port *port = slot->port;
1505	struct hisi_sas_device *sas_dev = dev->lldd_dev;
1506	bool sata = dev_is_sata(dev);
1507
1508	/* dw0 */
1509	hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1510	(port->id << CMD_HDR_PORT_OFF) |
1511	(sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1512	(abort->type << CMD_HDR_ABORT_FLAG_OFF));
1513
1514	/* dw1 */
1515	hdr->dw1 = cpu_to_le32(sas_dev->device_id
1516	<< CMD_HDR_DEV_ID_OFF);
1517
1518	/* dw7 */
1519	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1520	hdr->transfer_tags = cpu_to_le32(slot->idx);
1521	}
1522
1523	static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1524	{
1525	int i;
1526	irqreturn_t res;
1527	u32 context, port_id, link_rate;
1528	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1529	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1530	struct device *dev = hisi_hba->dev;
1531
1532	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, val: 1);
1533
1534	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1535	port_id = (port_id >> (4 * phy_no)) & 0xf;
1536	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1537	link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1538
1539	if (port_id == 0xf) {
1540	dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1541	res = IRQ_NONE;
1542	goto end;
1543	}
1544	sas_phy->linkrate = link_rate;
1545	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1546
1547	/* Check for SATA dev */
1548	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1549	if (context & (1 << phy_no)) {
1550	struct hisi_sas_initial_fis *initial_fis;
1551	struct dev_to_host_fis *fis;
1552	u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1553	struct Scsi_Host *shost = hisi_hba->shost;
1554
1555	dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1556	initial_fis = &hisi_hba->initial_fis[phy_no];
1557	fis = &initial_fis->fis;
1558
1559	/* check ERR bit of Status Register */
1560	if (fis->status & ATA_ERR) {
1561	dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1562	phy_no, fis->status);
1563	hisi_sas_notify_phy_event(phy, event: HISI_PHYE_LINK_RESET);
1564	res = IRQ_NONE;
1565	goto end;
1566	}
1567
1568	sas_phy->oob_mode = SATA_OOB_MODE;
1569	attached_sas_addr[0] = 0x50;
1570	attached_sas_addr[6] = shost->host_no;
1571	attached_sas_addr[7] = phy_no;
1572	memcpy(sas_phy->attached_sas_addr,
1573	attached_sas_addr,
1574	SAS_ADDR_SIZE);
1575	memcpy(sas_phy->frame_rcvd, fis,
1576	sizeof(struct dev_to_host_fis));
1577	phy->phy_type |= PORT_TYPE_SATA;
1578	phy->identify.device_type = SAS_SATA_DEV;
1579	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1580	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1581	} else {
1582	u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1583	struct sas_identify_frame *id =
1584	(struct sas_identify_frame *)frame_rcvd;
1585
1586	dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1587	for (i = 0; i < 6; i++) {
1588	u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1589	RX_IDAF_DWORD0 + (i * 4));
1590	frame_rcvd[i] = __swab32(idaf);
1591	}
1592	sas_phy->oob_mode = SAS_OOB_MODE;
1593	memcpy(sas_phy->attached_sas_addr,
1594	&id->sas_addr,
1595	SAS_ADDR_SIZE);
1596	phy->phy_type |= PORT_TYPE_SAS;
1597	phy->identify.device_type = id->dev_type;
1598	phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1599	if (phy->identify.device_type == SAS_END_DEVICE)
1600	phy->identify.target_port_protocols =
1601	SAS_PROTOCOL_SSP;
1602	else if (phy->identify.device_type != SAS_PHY_UNUSED)
1603	phy->identify.target_port_protocols =
1604	SAS_PROTOCOL_SMP;
1605	}
1606
1607	phy->port_id = port_id;
1608	spin_lock(lock: &phy->lock);
1609	/* Delete timer and set phy_attached atomically */
1610	del_timer(timer: &phy->timer);
1611	phy->phy_attached = 1;
1612	spin_unlock(lock: &phy->lock);
1613
1614	/*
1615	* Call pm_runtime_get_noresume() which pairs with
1616	* hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
1617	* For failure call pm_runtime_put() as we are in a hardirq context.
1618	*/
1619	pm_runtime_get_noresume(dev);
1620	res = hisi_sas_notify_phy_event(phy, event: HISI_PHYE_PHY_UP_PM);
1621	if (!res)
1622	pm_runtime_put(dev);
1623
1624	res = IRQ_HANDLED;
1625
1626	end:
1627	if (phy->reset_completion)
1628	complete(phy->reset_completion);
1629	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1630	CHL_INT0_SL_PHY_ENABLE_MSK);
1631	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, val: 0);
1632
1633	return res;
1634	}
1635
1636	static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1637	{
1638	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1639	u32 phy_state, sl_ctrl, txid_auto;
1640	struct device *dev = hisi_hba->dev;
1641
1642	atomic_inc(v: &phy->down_cnt);
1643
1644	del_timer(timer: &phy->timer);
1645	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, val: 1);
1646
1647	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1648	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1649	hisi_sas_phy_down(hisi_hba, phy_no, rdy: (phy_state & 1 << phy_no) ? 1 : 0,
1650	GFP_ATOMIC);
1651
1652	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1653	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1654	val: sl_ctrl&(~SL_CTA_MSK));
1655
1656	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1657	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1658	val: txid_auto | CT3_MSK);
1659
1660	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1661	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, val: 0);
1662
1663	return IRQ_HANDLED;
1664	}
1665
1666	static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1667	{
1668	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1669	u32 bcast_status;
1670
1671	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, val: 1);
1672	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1673	if (bcast_status & RX_BCAST_CHG_MSK)
1674	hisi_sas_phy_bcast(phy);
1675	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1676	CHL_INT0_SL_RX_BCST_ACK_MSK);
1677	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, val: 0);
1678
1679	return IRQ_HANDLED;
1680	}
1681
1682	static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1683	{
1684	struct hisi_hba *hisi_hba = p;
1685	u32 irq_msk;
1686	int phy_no = 0;
1687	irqreturn_t res = IRQ_NONE;
1688
1689	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1690	& 0x11111111;
1691	while (irq_msk) {
1692	if (irq_msk & 1) {
1693	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1694	CHL_INT0);
1695	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1696	int rdy = phy_state & (1 << phy_no);
1697
1698	if (rdy) {
1699	if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1700	/* phy up */
1701	if (phy_up_v3_hw(phy_no, hisi_hba)
1702	== IRQ_HANDLED)
1703	res = IRQ_HANDLED;
1704	if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1705	/* phy bcast */
1706	if (phy_bcast_v3_hw(phy_no, hisi_hba)
1707	== IRQ_HANDLED)
1708	res = IRQ_HANDLED;
1709	} else {
1710	if (irq_value & CHL_INT0_NOT_RDY_MSK)
1711	/* phy down */
1712	if (phy_down_v3_hw(phy_no, hisi_hba)
1713	== IRQ_HANDLED)
1714	res = IRQ_HANDLED;
1715	}
1716	}
1717	irq_msk >>= 4;
1718	phy_no++;
1719	}
1720
1721	return res;
1722	}
1723
1724	static const struct hisi_sas_hw_error port_axi_error[] = {
1725	{
1726	.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1727	.msg = "dmac_tx_ecc_bad_err",
1728	},
1729	{
1730	.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1731	.msg = "dmac_rx_ecc_bad_err",
1732	},
1733	{
1734	.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1735	.msg = "dma_tx_axi_wr_err",
1736	},
1737	{
1738	.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1739	.msg = "dma_tx_axi_rd_err",
1740	},
1741	{
1742	.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1743	.msg = "dma_rx_axi_wr_err",
1744	},
1745	{
1746	.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1747	.msg = "dma_rx_axi_rd_err",
1748	},
1749	{
1750	.irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1751	.msg = "dma_tx_fifo_err",
1752	},
1753	{
1754	.irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1755	.msg = "dma_rx_fifo_err",
1756	},
1757	{
1758	.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1759	.msg = "dma_tx_axi_ruser_err",
1760	},
1761	{
1762	.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1763	.msg = "dma_rx_axi_ruser_err",
1764	},
1765	};
1766
1767	static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1768	{
1769	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1770	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1771	struct device *dev = hisi_hba->dev;
1772	int i;
1773
1774	irq_value &= ~irq_msk;
1775	if (!irq_value) {
1776	dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1777	phy_no);
1778	return;
1779	}
1780
1781	for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1782	const struct hisi_sas_hw_error *error = &port_axi_error[i];
1783
1784	if (!(irq_value & error->irq_msk))
1785	continue;
1786
1787	dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1788	error->msg, phy_no, irq_value);
1789	queue_work(wq: hisi_hba->wq, work: &hisi_hba->rst_work);
1790	}
1791
1792	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, val: irq_value);
1793	}
1794
1795	static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1796	{
1797	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1798	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1799	struct sas_phy *sphy = sas_phy->phy;
1800	unsigned long flags;
1801	u32 reg_value;
1802
1803	spin_lock_irqsave(&phy->lock, flags);
1804
1805	/* loss dword sync */
1806	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1807	sphy->loss_of_dword_sync_count += reg_value;
1808
1809	/* phy reset problem */
1810	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1811	sphy->phy_reset_problem_count += reg_value;
1812
1813	/* invalid dword */
1814	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1815	sphy->invalid_dword_count += reg_value;
1816
1817	/* disparity err */
1818	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1819	sphy->running_disparity_error_count += reg_value;
1820
1821	/* code violation error */
1822	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1823	phy->code_violation_err_count += reg_value;
1824
1825	spin_unlock_irqrestore(lock: &phy->lock, flags);
1826	}
1827
1828	static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1829	{
1830	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1831	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1832	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1833	struct pci_dev *pci_dev = hisi_hba->pci_dev;
1834	struct device *dev = hisi_hba->dev;
1835	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1836	BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1837	BIT(CHL_INT2_RX_INVLD_DW_OFF);
1838
1839	irq_value &= ~irq_msk;
1840	if (!irq_value) {
1841	dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1842	phy_no);
1843	return;
1844	}
1845
1846	if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1847	dev_warn(dev, "phy%d identify timeout\n", phy_no);
1848	hisi_sas_notify_phy_event(phy, event: HISI_PHYE_LINK_RESET);
1849	}
1850
1851	if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1852	u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1853	STP_LINK_TIMEOUT_STATE);
1854
1855	dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1856	phy_no, reg_value);
1857	if (reg_value & BIT(4))
1858	hisi_sas_notify_phy_event(phy, event: HISI_PHYE_LINK_RESET);
1859	}
1860
1861	if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1862	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1863	struct sas_phy *sphy = sas_phy->phy;
1864
1865	phy_get_events_v3_hw(hisi_hba, phy_no);
1866
1867	if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1868	dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no,
1869	sphy->invalid_dword_count);
1870
1871	if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1872	dev_info(dev, "phy%d code violation cnt: %u\n", phy_no,
1873	phy->code_violation_err_count);
1874
1875	if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1876	dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1877	sphy->running_disparity_error_count);
1878	}
1879
1880	if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1881	(pci_dev->revision == 0x20)) {
1882	u32 reg_value;
1883	int rc;
1884
1885	rc = hisi_sas_read32_poll_timeout_atomic(
1886	HILINK_ERR_DFX, reg_value,
1887	!((reg_value >> 8) & BIT(phy_no)),
1888	1000, 10000);
1889	if (rc)
1890	hisi_sas_notify_phy_event(phy, event: HISI_PHYE_LINK_RESET);
1891	}
1892
1893	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, val: irq_value);
1894	}
1895
1896	static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1897	{
1898	u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1899
1900	if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1901	hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1902
1903	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1904	val: irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1905	& (~CHL_INT0_SL_PHY_ENABLE_MSK)
1906	& (~CHL_INT0_NOT_RDY_MSK));
1907	}
1908
1909	static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1910	{
1911	struct hisi_hba *hisi_hba = p;
1912	u32 irq_msk;
1913	int phy_no = 0;
1914
1915	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1916	& CHNL_INT_STS_MSK;
1917
1918	while (irq_msk) {
1919	if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1920	handle_chl_int0_v3_hw(hisi_hba, phy_no);
1921
1922	if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1923	handle_chl_int1_v3_hw(hisi_hba, phy_no);
1924
1925	if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1926	handle_chl_int2_v3_hw(hisi_hba, phy_no);
1927
1928	irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1929	phy_no++;
1930	}
1931
1932	return IRQ_HANDLED;
1933	}
1934
1935	static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1936	{
1937	.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1938	.msk = HGC_DQE_ECC_MB_ADDR_MSK,
1939	.shift = HGC_DQE_ECC_MB_ADDR_OFF,
1940	.msg = "hgc_dqe_eccbad_intr",
1941	.reg = HGC_DQE_ECC_ADDR,
1942	},
1943	{
1944	.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1945	.msk = HGC_IOST_ECC_MB_ADDR_MSK,
1946	.shift = HGC_IOST_ECC_MB_ADDR_OFF,
1947	.msg = "hgc_iost_eccbad_intr",
1948	.reg = HGC_IOST_ECC_ADDR,
1949	},
1950	{
1951	.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1952	.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1953	.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1954	.msg = "hgc_itct_eccbad_intr",
1955	.reg = HGC_ITCT_ECC_ADDR,
1956	},
1957	{
1958	.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1959	.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1960	.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1961	.msg = "hgc_iostl_eccbad_intr",
1962	.reg = HGC_LM_DFX_STATUS2,
1963	},
1964	{
1965	.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1966	.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1967	.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1968	.msg = "hgc_itctl_eccbad_intr",
1969	.reg = HGC_LM_DFX_STATUS2,
1970	},
1971	{
1972	.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1973	.msk = HGC_CQE_ECC_MB_ADDR_MSK,
1974	.shift = HGC_CQE_ECC_MB_ADDR_OFF,
1975	.msg = "hgc_cqe_eccbad_intr",
1976	.reg = HGC_CQE_ECC_ADDR,
1977	},
1978	{
1979	.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1980	.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1981	.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1982	.msg = "rxm_mem0_eccbad_intr",
1983	.reg = HGC_RXM_DFX_STATUS14,
1984	},
1985	{
1986	.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1987	.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1988	.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1989	.msg = "rxm_mem1_eccbad_intr",
1990	.reg = HGC_RXM_DFX_STATUS14,
1991	},
1992	{
1993	.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1994	.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1995	.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1996	.msg = "rxm_mem2_eccbad_intr",
1997	.reg = HGC_RXM_DFX_STATUS14,
1998	},
1999	{
2000	.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
2001	.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
2002	.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
2003	.msg = "rxm_mem3_eccbad_intr",
2004	.reg = HGC_RXM_DFX_STATUS15,
2005	},
2006	{
2007	.irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
2008	.msk = AM_ROB_ECC_ERR_ADDR_MSK,
2009	.shift = AM_ROB_ECC_ERR_ADDR_OFF,
2010	.msg = "ooo_ram_eccbad_intr",
2011	.reg = AM_ROB_ECC_ERR_ADDR,
2012	},
2013	};
2014
2015	static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
2016	u32 irq_value)
2017	{
2018	struct device *dev = hisi_hba->dev;
2019	const struct hisi_sas_hw_error *ecc_error;
2020	u32 val;
2021	int i;
2022
2023	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2024	ecc_error = &multi_bit_ecc_errors[i];
2025	if (irq_value & ecc_error->irq_msk) {
2026	val = hisi_sas_read32(hisi_hba, off: ecc_error->reg);
2027	val &= ecc_error->msk;
2028	val >>= ecc_error->shift;
2029	dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2030	ecc_error->msg, irq_value, val);
2031	queue_work(wq: hisi_hba->wq, work: &hisi_hba->rst_work);
2032	}
2033	}
2034	}
2035
2036	static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
2037	{
2038	u32 irq_value, irq_msk;
2039
2040	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2041	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, val: 0xffffffff);
2042
2043	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2044	if (irq_value)
2045	multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2046
2047	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, val: irq_value);
2048	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, val: irq_msk);
2049	}
2050
2051	static const struct hisi_sas_hw_error axi_error[] = {
2052	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2053	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2054	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2055	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2056	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2057	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2058	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2059	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2060	{}
2061	};
2062
2063	static const struct hisi_sas_hw_error fifo_error[] = {
2064	{ .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
2065	{ .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
2066	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
2067	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
2068	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2069	{}
2070	};
2071
2072	static const struct hisi_sas_hw_error fatal_axi_error[] = {
2073	{
2074	.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2075	.msg = "write pointer and depth",
2076	},
2077	{
2078	.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2079	.msg = "iptt no match slot",
2080	},
2081	{
2082	.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2083	.msg = "read pointer and depth",
2084	},
2085	{
2086	.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2087	.reg = HGC_AXI_FIFO_ERR_INFO,
2088	.sub = axi_error,
2089	},
2090	{
2091	.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2092	.reg = HGC_AXI_FIFO_ERR_INFO,
2093	.sub = fifo_error,
2094	},
2095	{
2096	.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2097	.msg = "LM add/fetch list",
2098	},
2099	{
2100	.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2101	.msg = "SAS_HGC_ABT fetch LM list",
2102	},
2103	{
2104	.irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2105	.msg = "read dqe poison",
2106	},
2107	{
2108	.irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2109	.msg = "read iost poison",
2110	},
2111	{
2112	.irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2113	.msg = "read itct poison",
2114	},
2115	{
2116	.irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2117	.msg = "read itct ncq poison",
2118	},
2119
2120	};
2121
2122	static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2123	{
2124	u32 irq_value, irq_msk;
2125	struct hisi_hba *hisi_hba = p;
2126	struct device *dev = hisi_hba->dev;
2127	struct pci_dev *pdev = hisi_hba->pci_dev;
2128	int i;
2129
2130	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2131	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, val: irq_msk | 0x1df00);
2132
2133	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2134	irq_value &= ~irq_msk;
2135
2136	for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2137	const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2138
2139	if (!(irq_value & error->irq_msk))
2140	continue;
2141
2142	if (error->sub) {
2143	const struct hisi_sas_hw_error *sub = error->sub;
2144	u32 err_value = hisi_sas_read32(hisi_hba, off: error->reg);
2145
2146	for (; sub->msk || sub->msg; sub++) {
2147	if (!(err_value & sub->msk))
2148	continue;
2149
2150	dev_err(dev, "%s error (0x%x) found!\n",
2151	sub->msg, irq_value);
2152	queue_work(wq: hisi_hba->wq, work: &hisi_hba->rst_work);
2153	}
2154	} else {
2155	dev_err(dev, "%s error (0x%x) found!\n",
2156	error->msg, irq_value);
2157	queue_work(wq: hisi_hba->wq, work: &hisi_hba->rst_work);
2158	}
2159
2160	if (pdev->revision < 0x21) {
2161	u32 reg_val;
2162
2163	reg_val = hisi_sas_read32(hisi_hba,
2164	AXI_MASTER_CFG_BASE +
2165	AM_CTRL_GLOBAL);
2166	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2167	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2168	AM_CTRL_GLOBAL, val: reg_val);
2169	}
2170	}
2171
2172	fatal_ecc_int_v3_hw(hisi_hba);
2173
2174	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2175	u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2176	u32 dev_id = reg_val & ITCT_DEV_MSK;
2177	struct hisi_sas_device *sas_dev =
2178	&hisi_hba->devices[dev_id];
2179
2180	hisi_sas_write32(hisi_hba, ITCT_CLR, val: 0);
2181	dev_dbg(dev, "clear ITCT ok\n");
2182	complete(sas_dev->completion);
2183	}
2184
2185	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, val: irq_value & 0x1df00);
2186	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, val: irq_msk);
2187
2188	return IRQ_HANDLED;
2189	}
2190
2191	static bool is_ncq_err_v3_hw(struct hisi_sas_complete_v3_hdr *complete_hdr)
2192	{
2193	u32 dw0, dw3;
2194
2195	dw0 = le32_to_cpu(complete_hdr->dw0);
2196	dw3 = le32_to_cpu(complete_hdr->dw3);
2197
2198	return (dw0 & ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK) &&
2199	(dw3 & FIS_TYPE_SDB_MSK) &&
2200	(dw3 & FIS_ATA_STATUS_ERR_MSK);
2201	}
2202
2203	static bool
2204	slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2205	struct hisi_sas_slot *slot)
2206	{
2207	struct task_status_struct *ts = &task->task_status;
2208	struct hisi_sas_complete_v3_hdr *complete_queue =
2209	hisi_hba->complete_hdr[slot->cmplt_queue];
2210	struct hisi_sas_complete_v3_hdr *complete_hdr =
2211	&complete_queue[slot->cmplt_queue_slot];
2212	struct hisi_sas_err_record_v3 *record =
2213	hisi_sas_status_buf_addr_mem(slot);
2214	u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2215	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2216	u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2217	u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2218	u32 dw0 = le32_to_cpu(complete_hdr->dw0);
2219
2220	switch (task->task_proto) {
2221	case SAS_PROTOCOL_SSP:
2222	if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2223	/*
2224	* If returned response frame is incorrect because of data underflow,
2225	* but I/O information has been written to the host memory, we examine
2226	* response IU.
2227	*/
2228	if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2229	(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2230	return false;
2231
2232	ts->residual = trans_tx_fail_type;
2233	ts->stat = SAS_DATA_UNDERRUN;
2234	} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2235	ts->stat = SAS_QUEUE_FULL;
2236	slot->abort = 1;
2237	} else {
2238	ts->stat = SAS_OPEN_REJECT;
2239	ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2240	}
2241	break;
2242	case SAS_PROTOCOL_SATA:
2243	case SAS_PROTOCOL_STP:
2244	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2245	if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2246	(sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2247	if (task->ata_task.use_ncq) {
2248	struct domain_device *device = task->dev;
2249	struct hisi_sas_device *sas_dev = device->lldd_dev;
2250
2251	sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2252	slot->abort = 1;
2253	} else {
2254	ts->stat = SAS_PROTO_RESPONSE;
2255	}
2256	} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2257	ts->residual = trans_tx_fail_type;
2258	ts->stat = SAS_DATA_UNDERRUN;
2259	} else if ((dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) ||
2260	(dw3 & SATA_DISK_IN_ERROR_STATUS_MSK)) {
2261	ts->stat = SAS_PHY_DOWN;
2262	slot->abort = 1;
2263	} else {
2264	ts->stat = SAS_OPEN_REJECT;
2265	ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2266	}
2267	if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2268	hisi_sas_sata_done(task, slot);
2269	break;
2270	case SAS_PROTOCOL_SMP:
2271	ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2272	break;
2273	default:
2274	break;
2275	}
2276	return true;
2277	}
2278
2279	static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2280	struct hisi_sas_slot *slot)
2281	{
2282	struct sas_task *task = slot->task;
2283	struct hisi_sas_device *sas_dev;
2284	struct device *dev = hisi_hba->dev;
2285	struct task_status_struct *ts;
2286	struct domain_device *device;
2287	struct sas_ha_struct *ha;
2288	struct hisi_sas_complete_v3_hdr *complete_queue =
2289	hisi_hba->complete_hdr[slot->cmplt_queue];
2290	struct hisi_sas_complete_v3_hdr *complete_hdr =
2291	&complete_queue[slot->cmplt_queue_slot];
2292	unsigned long flags;
2293	bool is_internal = slot->is_internal;
2294	u32 dw0, dw1, dw3;
2295
2296	if (unlikely(!task || !task->lldd_task || !task->dev))
2297	return;
2298
2299	ts = &task->task_status;
2300	device = task->dev;
2301	ha = device->port->ha;
2302	sas_dev = device->lldd_dev;
2303
2304	spin_lock_irqsave(&task->task_state_lock, flags);
2305	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2306	spin_unlock_irqrestore(lock: &task->task_state_lock, flags);
2307
2308	memset(ts, 0, sizeof(*ts));
2309	ts->resp = SAS_TASK_COMPLETE;
2310
2311	if (unlikely(!sas_dev)) {
2312	dev_dbg(dev, "slot complete: port has not device\n");
2313	ts->stat = SAS_PHY_DOWN;
2314	goto out;
2315	}
2316
2317	dw0 = le32_to_cpu(complete_hdr->dw0);
2318	dw1 = le32_to_cpu(complete_hdr->dw1);
2319	dw3 = le32_to_cpu(complete_hdr->dw3);
2320
2321	/*
2322	* Use SAS+TMF status codes
2323	*/
2324	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2325	case STAT_IO_ABORTED:
2326	/* this IO has been aborted by abort command */
2327	ts->stat = SAS_ABORTED_TASK;
2328	goto out;
2329	case STAT_IO_COMPLETE:
2330	/* internal abort command complete */
2331	ts->stat = TMF_RESP_FUNC_SUCC;
2332	goto out;
2333	case STAT_IO_NO_DEVICE:
2334	ts->stat = TMF_RESP_FUNC_COMPLETE;
2335	goto out;
2336	case STAT_IO_NOT_VALID:
2337	/*
2338	* abort single IO, the controller can't find the IO
2339	*/
2340	ts->stat = TMF_RESP_FUNC_FAILED;
2341	goto out;
2342	default:
2343	break;
2344	}
2345
2346	/* check for erroneous completion */
2347	if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2348	u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2349
2350	if (slot_err_v3_hw(hisi_hba, task, slot)) {
2351	if (ts->stat != SAS_DATA_UNDERRUN)
2352	dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2353	slot->idx, task, sas_dev->device_id,
2354	SAS_ADDR(device->sas_addr),
2355	dw0, dw1, complete_hdr->act, dw3,
2356	error_info[0], error_info[1],
2357	error_info[2], error_info[3]);
2358	if (unlikely(slot->abort)) {
2359	if (dev_is_sata(dev: device) && task->ata_task.use_ncq)
2360	sas_ata_device_link_abort(dev: device, force_reset: true);
2361	else
2362	sas_task_abort(task);
2363
2364	return;
2365	}
2366	goto out;
2367	}
2368	}
2369
2370	switch (task->task_proto) {
2371	case SAS_PROTOCOL_SSP: {
2372	struct ssp_response_iu *iu =
2373	hisi_sas_status_buf_addr_mem(slot) +
2374	sizeof(struct hisi_sas_err_record);
2375
2376	sas_ssp_task_response(dev, task, iu);
2377	break;
2378	}
2379	case SAS_PROTOCOL_SMP: {
2380	struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2381	void *to = page_address(sg_page(sg_resp));
2382
2383	ts->stat = SAS_SAM_STAT_GOOD;
2384
2385	memcpy(to + sg_resp->offset,
2386	hisi_sas_status_buf_addr_mem(slot) +
2387	sizeof(struct hisi_sas_err_record),
2388	sg_resp->length);
2389	break;
2390	}
2391	case SAS_PROTOCOL_SATA:
2392	case SAS_PROTOCOL_STP:
2393	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2394	ts->stat = SAS_SAM_STAT_GOOD;
2395	if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2396	hisi_sas_sata_done(task, slot);
2397	break;
2398	default:
2399	ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2400	break;
2401	}
2402
2403	if (!slot->port->port_attached) {
2404	dev_warn(dev, "slot complete: port %d has removed\n",
2405	slot->port->sas_port.id);
2406	ts->stat = SAS_PHY_DOWN;
2407	}
2408
2409	out:
2410	spin_lock_irqsave(&task->task_state_lock, flags);
2411	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2412	spin_unlock_irqrestore(lock: &task->task_state_lock, flags);
2413	dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2414	return;
2415	}
2416	task->task_state_flags |= SAS_TASK_STATE_DONE;
2417	spin_unlock_irqrestore(lock: &task->task_state_lock, flags);
2418	hisi_sas_slot_task_free(hisi_hba, task, slot, need_lock: true);
2419
2420	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2421	spin_lock_irqsave(&device->done_lock, flags);
2422	if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2423	spin_unlock_irqrestore(lock: &device->done_lock, flags);
2424	dev_info(dev, "slot complete: task(%pK) ignored\n ",
2425	task);
2426	return;
2427	}
2428	spin_unlock_irqrestore(lock: &device->done_lock, flags);
2429	}
2430
2431	if (task->task_done)
2432	task->task_done(task);
2433	}
2434
2435	static int complete_v3_hw(struct hisi_sas_cq *cq)
2436	{
2437	struct hisi_sas_complete_v3_hdr *complete_queue;
2438	struct hisi_hba *hisi_hba = cq->hisi_hba;
2439	u32 rd_point, wr_point;
2440	int queue = cq->id;
2441	int completed;
2442
2443	rd_point = cq->rd_point;
2444	complete_queue = hisi_hba->complete_hdr[queue];
2445
2446	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2447	(0x14 * queue));
2448	completed = (wr_point + HISI_SAS_QUEUE_SLOTS - rd_point) % HISI_SAS_QUEUE_SLOTS;
2449
2450	while (rd_point != wr_point) {
2451	struct hisi_sas_complete_v3_hdr *complete_hdr;
2452	struct device *dev = hisi_hba->dev;
2453	struct hisi_sas_slot *slot;
2454	u32 dw0, dw1, dw3;
2455	int iptt;
2456
2457	complete_hdr = &complete_queue[rd_point];
2458	dw0 = le32_to_cpu(complete_hdr->dw0);
2459	dw1 = le32_to_cpu(complete_hdr->dw1);
2460	dw3 = le32_to_cpu(complete_hdr->dw3);
2461
2462	iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2463	if (unlikely((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) &&
2464	(dw3 & CMPLT_HDR_SATA_DISK_ERR_MSK)) {
2465	int device_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2466	CMPLT_HDR_DEV_ID_OFF;
2467	struct hisi_sas_itct *itct =
2468	&hisi_hba->itct[device_id];
2469	struct hisi_sas_device *sas_dev =
2470	&hisi_hba->devices[device_id];
2471	struct domain_device *device = sas_dev->sas_device;
2472
2473	dev_err(dev, "erroneous completion disk err dev id=%d sas_addr=0x%llx CQ hdr: 0x%x 0x%x 0x%x 0x%x\n",
2474	device_id, itct->sas_addr, dw0, dw1,
2475	complete_hdr->act, dw3);
2476
2477	if (is_ncq_err_v3_hw(complete_hdr))
2478	sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2479
2480	sas_ata_device_link_abort(dev: device, force_reset: true);
2481	} else if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2482	slot = &hisi_hba->slot_info[iptt];
2483	slot->cmplt_queue_slot = rd_point;
2484	slot->cmplt_queue = queue;
2485	slot_complete_v3_hw(hisi_hba, slot);
2486	} else
2487	dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2488
2489	if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2490	rd_point = 0;
2491	}
2492
2493	/* update rd_point */
2494	cq->rd_point = rd_point;
2495	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), val: rd_point);
2496
2497	return completed;
2498	}
2499
2500	static int queue_complete_v3_hw(struct Scsi_Host *shost, unsigned int queue)
2501	{
2502	struct hisi_hba *hisi_hba = shost_priv(shost);
2503	struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2504	int completed;
2505
2506	spin_lock(lock: &cq->poll_lock);
2507	completed = complete_v3_hw(cq);
2508	spin_unlock(lock: &cq->poll_lock);
2509
2510	return completed;
2511	}
2512
2513	static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2514	{
2515	struct hisi_sas_cq *cq = p;
2516
2517	complete_v3_hw(cq);
2518
2519	return IRQ_HANDLED;
2520	}
2521
2522	static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2523	{
2524	struct hisi_sas_cq *cq = p;
2525	struct hisi_hba *hisi_hba = cq->hisi_hba;
2526	int queue = cq->id;
2527
2528	hisi_sas_write32(hisi_hba, OQ_INT_SRC, val: 1 << queue);
2529
2530	return IRQ_WAKE_THREAD;
2531	}
2532
2533	static void hisi_sas_v3_free_vectors(void *data)
2534	{
2535	struct pci_dev *pdev = data;
2536
2537	pci_free_irq_vectors(dev: pdev);
2538	}
2539
2540	static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2541	{
2542	/* Allocate all MSI vectors to avoid re-insertion issue */
2543	int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
2544	int vectors, min_msi;
2545	struct Scsi_Host *shost = hisi_hba->shost;
2546	struct pci_dev *pdev = hisi_hba->pci_dev;
2547	struct irq_affinity desc = {
2548	.pre_vectors = BASE_VECTORS_V3_HW,
2549	};
2550
2551	min_msi = MIN_AFFINE_VECTORS_V3_HW;
2552	vectors = pci_alloc_irq_vectors_affinity(dev: pdev,
2553	min_vecs: min_msi, max_vecs: max_msi,
2554	PCI_IRQ_MSI |
2555	PCI_IRQ_AFFINITY,
2556	affd: &desc);
2557	if (vectors < 0)
2558	return -ENOENT;
2559
2560
2561	hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW - hisi_hba->iopoll_q_cnt;
2562	shost->nr_hw_queues = hisi_hba->cq_nvecs + hisi_hba->iopoll_q_cnt;
2563
2564	return devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2565	}
2566
2567	static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2568	{
2569	struct device *dev = hisi_hba->dev;
2570	struct pci_dev *pdev = hisi_hba->pci_dev;
2571	int rc, i;
2572
2573	rc = devm_request_irq(dev, irq: pci_irq_vector(dev: pdev, nr: 1),
2574	handler: int_phy_up_down_bcast_v3_hw, irqflags: 0,
2575	DRV_NAME " phy", dev_id: hisi_hba);
2576	if (rc) {
2577	dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2578	return -ENOENT;
2579	}
2580
2581	rc = devm_request_irq(dev, irq: pci_irq_vector(dev: pdev, nr: 2),
2582	handler: int_chnl_int_v3_hw, irqflags: 0,
2583	DRV_NAME " channel", dev_id: hisi_hba);
2584	if (rc) {
2585	dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2586	return -ENOENT;
2587	}
2588
2589	rc = devm_request_irq(dev, irq: pci_irq_vector(dev: pdev, nr: 11),
2590	handler: fatal_axi_int_v3_hw, irqflags: 0,
2591	DRV_NAME " fatal", dev_id: hisi_hba);
2592	if (rc) {
2593	dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2594	return -ENOENT;
2595	}
2596
2597	if (hisi_sas_intr_conv)
2598	dev_info(dev, "Enable interrupt converge\n");
2599
2600	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2601	struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2602	int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2603	unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2604	IRQF_ONESHOT;
2605
2606	cq->irq_no = pci_irq_vector(dev: pdev, nr);
2607	rc = devm_request_threaded_irq(dev, irq: cq->irq_no,
2608	handler: cq_interrupt_v3_hw,
2609	thread_fn: cq_thread_v3_hw,
2610	irqflags,
2611	DRV_NAME " cq", dev_id: cq);
2612	if (rc) {
2613	dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2614	i, rc);
2615	return -ENOENT;
2616	}
2617	cq->irq_mask = pci_irq_get_affinity(pdev, vec: i + BASE_VECTORS_V3_HW);
2618	if (!cq->irq_mask) {
2619	dev_err(dev, "could not get cq%d irq affinity!\n", i);
2620	return -ENOENT;
2621	}
2622	}
2623
2624	return 0;
2625	}
2626
2627	static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2628	{
2629	int rc;
2630
2631	rc = hw_init_v3_hw(hisi_hba);
2632	if (rc)
2633	return rc;
2634
2635	rc = interrupt_init_v3_hw(hisi_hba);
2636	if (rc)
2637	return rc;
2638
2639	return 0;
2640	}
2641
2642	static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2643	struct sas_phy_linkrates *r)
2644	{
2645	enum sas_linkrate max = r->maximum_linkrate;
2646	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2647	PROG_PHY_LINK_RATE);
2648
2649	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2650	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2651	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2652	val: prog_phy_link_rate);
2653	}
2654
2655	static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2656	{
2657	struct pci_dev *pdev = hisi_hba->pci_dev;
2658	int i;
2659
2660	synchronize_irq(irq: pci_irq_vector(dev: pdev, nr: 1));
2661	synchronize_irq(irq: pci_irq_vector(dev: pdev, nr: 2));
2662	synchronize_irq(irq: pci_irq_vector(dev: pdev, nr: 11));
2663	for (i = 0; i < hisi_hba->queue_count; i++)
2664	hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, val: 0x1);
2665
2666	for (i = 0; i < hisi_hba->cq_nvecs; i++)
2667	synchronize_irq(irq: pci_irq_vector(dev: pdev, nr: i + 16));
2668
2669	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, val: 0xffffffff);
2670	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, val: 0xffffffff);
2671	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, val: 0xffffffff);
2672	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, val: 0xffffffff);
2673
2674	for (i = 0; i < hisi_hba->n_phy; i++) {
2675	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT1_MSK, val: 0xffffffff);
2676	hisi_sas_phy_write32(hisi_hba, phy_no: i, CHL_INT2_MSK, val: 0xffffffff);
2677	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_NOT_RDY_MSK, val: 0x1);
2678	hisi_sas_phy_write32(hisi_hba, phy_no: i, PHYCTRL_PHY_ENA_MSK, val: 0x1);
2679	hisi_sas_phy_write32(hisi_hba, phy_no: i, SL_RX_BCAST_CHK_MSK, val: 0x1);
2680	}
2681	}
2682
2683	static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2684	{
2685	return hisi_sas_read32(hisi_hba, PHY_STATE);
2686	}
2687
2688	static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2689	{
2690	struct device *dev = hisi_hba->dev;
2691	u32 status, reg_val;
2692	int rc;
2693
2694	hisi_sas_sync_poll_cqs(hisi_hba);
2695	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, val: 0x0);
2696
2697	hisi_sas_stop_phys(hisi_hba);
2698
2699	mdelay(10);
2700
2701	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2702	AM_CTRL_GLOBAL);
2703	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2704	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2705	AM_CTRL_GLOBAL, val: reg_val);
2706
2707	/* wait until bus idle */
2708	rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2709	AM_CURR_TRANS_RETURN, status,
2710	status == 0x3, 10, 100);
2711	if (rc) {
2712	dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2713	return rc;
2714	}
2715
2716	return 0;
2717	}
2718
2719	static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2720	{
2721	struct device *dev = hisi_hba->dev;
2722	int rc;
2723
2724	interrupt_disable_v3_hw(hisi_hba);
2725	rc = disable_host_v3_hw(hisi_hba);
2726	if (rc) {
2727	dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2728	return rc;
2729	}
2730
2731	hisi_sas_init_mem(hisi_hba);
2732
2733	return hw_init_v3_hw(hisi_hba);
2734	}
2735
2736	static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2737	u8 reg_index, u8 reg_count, u8 *write_data)
2738	{
2739	struct device *dev = hisi_hba->dev;
2740	u32 *data = (u32 *)write_data;
2741	int i;
2742
2743	switch (reg_type) {
2744	case SAS_GPIO_REG_TX:
2745	if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2746	dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2747	reg_index, reg_index + reg_count - 1);
2748	return -EINVAL;
2749	}
2750
2751	for (i = 0; i < reg_count; i++)
2752	hisi_sas_write32(hisi_hba,
2753	SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2754	val: data[i]);
2755	break;
2756	default:
2757	dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2758	reg_type);
2759	return -EINVAL;
2760	}
2761
2762	return 0;
2763	}
2764
2765	static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2766	int delay_ms, int timeout_ms)
2767	{
2768	struct device *dev = hisi_hba->dev;
2769	int entries, entries_old = 0, time;
2770
2771	for (time = 0; time < timeout_ms; time += delay_ms) {
2772	entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2773	if (entries == entries_old)
2774	break;
2775
2776	entries_old = entries;
2777	msleep(msecs: delay_ms);
2778	}
2779
2780	if (time >= timeout_ms) {
2781	dev_dbg(dev, "Wait commands complete timeout!\n");
2782	return;
2783	}
2784
2785	dev_dbg(dev, "wait commands complete %dms\n", time);
2786	}
2787
2788	static ssize_t intr_conv_v3_hw_show(struct device *dev,
2789	struct device_attribute *attr, char *buf)
2790	{
2791	return scnprintf(buf, PAGE_SIZE, fmt: "%u\n", hisi_sas_intr_conv);
2792	}
2793	static DEVICE_ATTR_RO(intr_conv_v3_hw);
2794
2795	static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2796	{
2797	/* config those registers between enable and disable PHYs */
2798	hisi_sas_stop_phys(hisi_hba);
2799
2800	if (hisi_hba->intr_coal_ticks == 0 ||
2801	hisi_hba->intr_coal_count == 0) {
2802	hisi_sas_write32(hisi_hba, INT_COAL_EN, val: 0x1);
2803	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, val: 0x1);
2804	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, val: 0x1);
2805	} else {
2806	hisi_sas_write32(hisi_hba, INT_COAL_EN, val: 0x3);
2807	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2808	val: hisi_hba->intr_coal_ticks);
2809	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2810	val: hisi_hba->intr_coal_count);
2811	}
2812	phys_init_v3_hw(hisi_hba);
2813	}
2814
2815	static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2816	struct device_attribute *attr,
2817	char *buf)
2818	{
2819	struct Scsi_Host *shost = class_to_shost(dev);
2820	struct hisi_hba *hisi_hba = shost_priv(shost);
2821
2822	return scnprintf(buf, PAGE_SIZE, fmt: "%u\n",
2823	hisi_hba->intr_coal_ticks);
2824	}
2825
2826	static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2827	struct device_attribute *attr,
2828	const char *buf, size_t count)
2829	{
2830	struct Scsi_Host *shost = class_to_shost(dev);
2831	struct hisi_hba *hisi_hba = shost_priv(shost);
2832	u32 intr_coal_ticks;
2833	int ret;
2834
2835	ret = kstrtou32(s: buf, base: 10, res: &intr_coal_ticks);
2836	if (ret) {
2837	dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2838	return -EINVAL;
2839	}
2840
2841	if (intr_coal_ticks >= BIT(24)) {
2842	dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2843	return -EINVAL;
2844	}
2845
2846	hisi_hba->intr_coal_ticks = intr_coal_ticks;
2847
2848	config_intr_coal_v3_hw(hisi_hba);
2849
2850	return count;
2851	}
2852	static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2853
2854	static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2855	struct device_attribute
2856	*attr, char *buf)
2857	{
2858	struct Scsi_Host *shost = class_to_shost(dev);
2859	struct hisi_hba *hisi_hba = shost_priv(shost);
2860
2861	return scnprintf(buf, PAGE_SIZE, fmt: "%u\n",
2862	hisi_hba->intr_coal_count);
2863	}
2864
2865	static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2866	struct device_attribute
2867	*attr, const char *buf, size_t count)
2868	{
2869	struct Scsi_Host *shost = class_to_shost(dev);
2870	struct hisi_hba *hisi_hba = shost_priv(shost);
2871	u32 intr_coal_count;
2872	int ret;
2873
2874	ret = kstrtou32(s: buf, base: 10, res: &intr_coal_count);
2875	if (ret) {
2876	dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2877	return -EINVAL;
2878	}
2879
2880	if (intr_coal_count >= BIT(8)) {
2881	dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2882	return -EINVAL;
2883	}
2884
2885	hisi_hba->intr_coal_count = intr_coal_count;
2886
2887	config_intr_coal_v3_hw(hisi_hba);
2888
2889	return count;
2890	}
2891	static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2892
2893	static ssize_t iopoll_q_cnt_v3_hw_show(struct device *dev,
2894	struct device_attribute
2895	*attr, char *buf)
2896	{
2897	struct Scsi_Host *shost = class_to_shost(dev);
2898	struct hisi_hba *hisi_hba = shost_priv(shost);
2899
2900	return scnprintf(buf, PAGE_SIZE, fmt: "%u\n",
2901	hisi_hba->iopoll_q_cnt);
2902	}
2903	static DEVICE_ATTR_RO(iopoll_q_cnt_v3_hw);
2904
2905	static int slave_configure_v3_hw(struct scsi_device *sdev)
2906	{
2907	struct Scsi_Host *shost = dev_to_shost(dev: &sdev->sdev_gendev);
2908	struct hisi_hba *hisi_hba = shost_priv(shost);
2909	int ret = hisi_sas_slave_configure(sdev);
2910	struct device *dev = hisi_hba->dev;
2911
2912	if (ret)
2913	return ret;
2914
2915	if (sdev->type == TYPE_ENCLOSURE)
2916	return 0;
2917
2918	if (!device_link_add(consumer: &sdev->sdev_gendev, supplier: dev,
2919	DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2920	if (pm_runtime_enabled(dev)) {
2921	dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2922	pm_runtime_disable(dev);
2923	}
2924	}
2925
2926	return 0;
2927	}
2928
2929	static struct attribute *host_v3_hw_attrs[] = {
2930	&dev_attr_phy_event_threshold.attr,
2931	&dev_attr_intr_conv_v3_hw.attr,
2932	&dev_attr_intr_coal_ticks_v3_hw.attr,
2933	&dev_attr_intr_coal_count_v3_hw.attr,
2934	&dev_attr_iopoll_q_cnt_v3_hw.attr,
2935	NULL
2936	};
2937
2938	ATTRIBUTE_GROUPS(host_v3_hw);
2939
2940	#define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2941
2942	struct hisi_sas_debugfs_reg_lu {
2943	char *name;
2944	int off;
2945	};
2946
2947	struct hisi_sas_debugfs_reg {
2948	const struct hisi_sas_debugfs_reg_lu *lu;
2949	int count;
2950	int base_off;
2951	};
2952
2953	static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2954	HISI_SAS_DEBUGFS_REG(PHY_CFG),
2955	HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2956	HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2957	HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2958	HISI_SAS_DEBUGFS_REG(SL_CFG),
2959	HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2960	HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2961	HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2962	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2963	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2964	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2965	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2966	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2967	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2968	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2969	HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2970	HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2971	HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2972	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2973	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2974	HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2975	HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2976	HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2977	HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2978	HISI_SAS_DEBUGFS_REG(CHL_INT0),
2979	HISI_SAS_DEBUGFS_REG(CHL_INT1),
2980	HISI_SAS_DEBUGFS_REG(CHL_INT2),
2981	HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2982	HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2983	HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2984	HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2985	HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2986	HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2987	HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2988	HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2989	HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2990	HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2991	HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2992	HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2993	HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2994	HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2995	HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2996	HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2997	HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2998	HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2999	HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
3000	HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
3001	{}
3002	};
3003
3004	static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
3005	.lu = debugfs_port_reg_lu,
3006	.count = 0x100,
3007	.base_off = PORT_BASE,
3008	};
3009
3010	static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
3011	HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
3012	HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
3013	HISI_SAS_DEBUGFS_REG(PHY_STATE),
3014	HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
3015	HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
3016	HISI_SAS_DEBUGFS_REG(ITCT_CLR),
3017	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
3018	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
3019	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
3020	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
3021	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
3022	HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),
3023	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
3024	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
3025	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
3026	HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
3027	HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
3028	HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
3029	HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
3030	HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
3031	HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
3032	HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
3033	HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
3034	HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
3035	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
3036	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
3037	HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
3038	HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
3039	HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
3040	HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
3041	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
3042	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
3043	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
3044	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
3045	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
3046	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
3047	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
3048	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
3049	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
3050	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
3051	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
3052	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
3053	HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
3054	HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
3055	HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
3056	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
3057	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
3058	HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
3059	HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
3060	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
3061	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
3062	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
3063	HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
3064	HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
3065	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
3066	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
3067	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
3068	HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
3069	HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
3070	HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
3071	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
3072	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
3073	HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
3074	HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
3075	{}
3076	};
3077
3078	static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
3079	.lu = debugfs_global_reg_lu,
3080	.count = 0x800,
3081	};
3082
3083	static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
3084	HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
3085	HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
3086	HISI_SAS_DEBUGFS_REG(AXI_CFG),
3087	HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
3088	{}
3089	};
3090
3091	static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
3092	.lu = debugfs_axi_reg_lu,
3093	.count = 0x61,
3094	.base_off = AXI_MASTER_CFG_BASE,
3095	};
3096
3097	static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
3098	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
3099	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
3100	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
3101	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
3102	HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
3103	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
3104	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
3105	{}
3106	};
3107
3108	static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
3109	.lu = debugfs_ras_reg_lu,
3110	.count = 0x10,
3111	.base_off = RAS_BASE,
3112	};
3113
3114	static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
3115	{
3116	struct Scsi_Host *shost = hisi_hba->shost;
3117
3118	scsi_block_requests(shost);
3119	wait_cmds_complete_timeout_v3_hw(hisi_hba, delay_ms: 100, timeout_ms: 5000);
3120
3121	set_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
3122	hisi_sas_sync_cqs(hisi_hba);
3123	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, val: 0);
3124	}
3125
3126	static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
3127	{
3128	struct Scsi_Host *shost = hisi_hba->shost;
3129
3130	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
3131	val: (u32)((1ULL << hisi_hba->queue_count) - 1));
3132
3133	clear_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
3134	scsi_unblock_requests(shost);
3135	}
3136
3137	static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3138	enum hisi_sas_debugfs_cache_type type,
3139	u32 *cache)
3140	{
3141	u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3142	HISI_SAS_IOST_ITCT_CACHE_NUM;
3143	struct device *dev = hisi_hba->dev;
3144	u32 *buf = cache;
3145	u32 i, val;
3146
3147	hisi_sas_write32(hisi_hba, TAB_RD_TYPE, val: type);
3148
3149	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3150	val = hisi_sas_read32(hisi_hba, TAB_DFX);
3151	if (val == 0xffffffff)
3152	break;
3153	}
3154
3155	if (val != 0xffffffff) {
3156	dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3157	return;
3158	}
3159
3160	memset(buf, 0, cache_dw_size * 4);
3161	buf[0] = val;
3162
3163	for (i = 1; i < cache_dw_size; i++)
3164	buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3165	}
3166
3167	static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3168	{
3169	u32 reg_val;
3170	int phy_no = hisi_hba->debugfs_bist_phy_no;
3171	int i;
3172
3173	/* disable PHY */
3174	hisi_sas_phy_enable(hisi_hba, phy_no, enable: 0);
3175
3176	/* update FFE */
3177	for (i = 0; i < FFE_CFG_MAX; i++)
3178	hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3179	val: hisi_hba->debugfs_bist_ffe[phy_no][i]);
3180
3181	/* disable ALOS */
3182	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3183	reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3184	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, val: reg_val);
3185	}
3186
3187	static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3188	{
3189	u32 reg_val;
3190	int phy_no = hisi_hba->debugfs_bist_phy_no;
3191
3192	/* disable loopback */
3193	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3194	reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3195	CFG_BIST_TEST_MSK);
3196	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, val: reg_val);
3197
3198	/* enable ALOS */
3199	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3200	reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3201	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, val: reg_val);
3202
3203	/* restore the linkrate */
3204	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3205	/* init OOB link rate as 1.5 Gbits */
3206	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3207	reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3208	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, val: reg_val);
3209
3210	/* enable PHY */
3211	hisi_sas_phy_enable(hisi_hba, phy_no, enable: 1);
3212	}
3213
3214	#define SAS_PHY_BIST_CODE_INIT 0x1
3215	#define SAS_PHY_BIST_CODE1_INIT 0X80
3216	static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3217	{
3218	u32 reg_val, mode_tmp;
3219	u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3220	u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3221	u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3222	u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3223	u32 path_mode = hisi_hba->debugfs_bist_mode;
3224	u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3225	struct device *dev = hisi_hba->dev;
3226
3227	dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3228	phy_no, linkrate, code_mode, path_mode,
3229	ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3230	ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3231	ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3232	ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3233	fix_code[FIXED_CODE_1]);
3234	mode_tmp = path_mode ? 2 : 1;
3235	if (enable) {
3236	/* some preparations before bist test */
3237	hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3238
3239	/* set linkrate of bit test*/
3240	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3241	PROG_PHY_LINK_RATE);
3242	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3243	reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3244	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3245	val: reg_val);
3246
3247	/* set code mode of bit test */
3248	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3249	SAS_PHY_BIST_CTRL);
3250	reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3251	CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3252	CFG_BIST_TEST_MSK);
3253	reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3254	(mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3255	CFG_BIST_TEST_MSK);
3256	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3257	val: reg_val);
3258
3259	/* set the bist init value */
3260	if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3261	reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3262	hisi_sas_phy_write32(hisi_hba, phy_no,
3263	SAS_PHY_BIST_CODE, val: reg_val);
3264
3265	reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3266	hisi_sas_phy_write32(hisi_hba, phy_no,
3267	SAS_PHY_BIST_CODE1, val: reg_val);
3268	} else {
3269	hisi_sas_phy_write32(hisi_hba, phy_no,
3270	SAS_PHY_BIST_CODE,
3271	SAS_PHY_BIST_CODE_INIT);
3272	hisi_sas_phy_write32(hisi_hba, phy_no,
3273	SAS_PHY_BIST_CODE1,
3274	SAS_PHY_BIST_CODE1_INIT);
3275	}
3276
3277	mdelay(100);
3278	reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3279	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3280	val: reg_val);
3281
3282	/* clear error bit */
3283	mdelay(100);
3284	hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3285	} else {
3286	/* disable bist test and recover it */
3287	hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3288	phy_no, SAS_BIST_ERR_CNT);
3289	hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3290	}
3291
3292	return 0;
3293	}
3294
3295	static void hisi_sas_map_queues(struct Scsi_Host *shost)
3296	{
3297	struct hisi_hba *hisi_hba = shost_priv(shost);
3298	struct blk_mq_queue_map *qmap;
3299	int i, qoff;
3300
3301	for (i = 0, qoff = 0; i < shost->nr_maps; i++) {
3302	qmap = &shost->tag_set.map[i];
3303	if (i == HCTX_TYPE_DEFAULT) {
3304	qmap->nr_queues = hisi_hba->cq_nvecs;
3305	} else if (i == HCTX_TYPE_POLL) {
3306	qmap->nr_queues = hisi_hba->iopoll_q_cnt;
3307	} else {
3308	qmap->nr_queues = 0;
3309	continue;
3310	}
3311
3312	/* At least one interrupt hardware queue */
3313	if (!qmap->nr_queues)
3314	WARN_ON(i == HCTX_TYPE_DEFAULT);
3315	qmap->queue_offset = qoff;
3316	if (i == HCTX_TYPE_POLL)
3317	blk_mq_map_queues(qmap);
3318	else
3319	blk_mq_pci_map_queues(qmap, pdev: hisi_hba->pci_dev,
3320	BASE_VECTORS_V3_HW);
3321	qoff += qmap->nr_queues;
3322	}
3323	}
3324
3325	static const struct scsi_host_template sht_v3_hw = {
3326	.name = DRV_NAME,
3327	.proc_name = DRV_NAME,
3328	.module = THIS_MODULE,
3329	.queuecommand = sas_queuecommand,
3330	.dma_need_drain = ata_scsi_dma_need_drain,
3331	.target_alloc = sas_target_alloc,
3332	.slave_configure = slave_configure_v3_hw,
3333	.scan_finished = hisi_sas_scan_finished,
3334	.scan_start = hisi_sas_scan_start,
3335	.map_queues = hisi_sas_map_queues,
3336	.change_queue_depth = sas_change_queue_depth,
3337	.bios_param = sas_bios_param,
3338	.this_id = -1,
3339	.sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3340	.sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT,
3341	.max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3342	.eh_device_reset_handler = sas_eh_device_reset_handler,
3343	.eh_target_reset_handler = sas_eh_target_reset_handler,
3344	.slave_alloc = hisi_sas_slave_alloc,
3345	.target_destroy = sas_target_destroy,
3346	.ioctl = sas_ioctl,
3347	#ifdef CONFIG_COMPAT
3348	.compat_ioctl = sas_ioctl,
3349	#endif
3350	.shost_groups = host_v3_hw_groups,
3351	.tag_alloc_policy = BLK_TAG_ALLOC_RR,
3352	.host_reset = hisi_sas_host_reset,
3353	.host_tagset = 1,
3354	.mq_poll = queue_complete_v3_hw,
3355	};
3356
3357	static const struct hisi_sas_hw hisi_sas_v3_hw = {
3358	.setup_itct = setup_itct_v3_hw,
3359	.get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3360	.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3361	.clear_itct = clear_itct_v3_hw,
3362	.sl_notify_ssp = sl_notify_ssp_v3_hw,
3363	.prep_ssp = prep_ssp_v3_hw,
3364	.prep_smp = prep_smp_v3_hw,
3365	.prep_stp = prep_ata_v3_hw,
3366	.prep_abort = prep_abort_v3_hw,
3367	.start_delivery = start_delivery_v3_hw,
3368	.phys_init = phys_init_v3_hw,
3369	.phy_start = start_phy_v3_hw,
3370	.phy_disable = disable_phy_v3_hw,
3371	.phy_hard_reset = phy_hard_reset_v3_hw,
3372	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3373	.phy_set_linkrate = phy_set_linkrate_v3_hw,
3374	.dereg_device = dereg_device_v3_hw,
3375	.soft_reset = soft_reset_v3_hw,
3376	.get_phys_state = get_phys_state_v3_hw,
3377	.get_events = phy_get_events_v3_hw,
3378	.write_gpio = write_gpio_v3_hw,
3379	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3380	.debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3381	};
3382
3383	static struct Scsi_Host *
3384	hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3385	{
3386	struct Scsi_Host *shost;
3387	struct hisi_hba *hisi_hba;
3388	struct device *dev = &pdev->dev;
3389
3390	shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3391	if (!shost) {
3392	dev_err(dev, "shost alloc failed\n");
3393	return NULL;
3394	}
3395	hisi_hba = shost_priv(shost);
3396
3397	INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3398	hisi_hba->hw = &hisi_sas_v3_hw;
3399	hisi_hba->pci_dev = pdev;
3400	hisi_hba->dev = dev;
3401	hisi_hba->shost = shost;
3402	SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3403
3404	if (prot_mask & ~HISI_SAS_PROT_MASK)
3405	dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3406	prot_mask);
3407	else
3408	hisi_hba->prot_mask = prot_mask;
3409
3410	if (hisi_sas_get_fw_info(hisi_hba) < 0)
3411	goto err_out;
3412
3413	if (experimental_iopoll_q_cnt < 0 ||
3414	experimental_iopoll_q_cnt >= hisi_hba->queue_count)
3415	dev_err(dev, "iopoll queue count %d cannot exceed or equal 16, using default 0\n",
3416	experimental_iopoll_q_cnt);
3417	else
3418	hisi_hba->iopoll_q_cnt = experimental_iopoll_q_cnt;
3419
3420	if (hisi_sas_alloc(hisi_hba)) {
3421	hisi_sas_free(hisi_hba);
3422	goto err_out;
3423	}
3424
3425	return shost;
3426	err_out:
3427	scsi_host_put(t: shost);
3428	dev_err(dev, "shost alloc failed\n");
3429	return NULL;
3430	}
3431
3432	static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3433	{
3434	int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3435	int dump_index = hisi_hba->debugfs_dump_index;
3436	int i;
3437
3438	for (i = 0; i < hisi_hba->queue_count; i++)
3439	memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3440	hisi_hba->complete_hdr[i],
3441	HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3442	}
3443
3444	static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3445	{
3446	int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3447	int dump_index = hisi_hba->debugfs_dump_index;
3448	int i;
3449
3450	for (i = 0; i < hisi_hba->queue_count; i++) {
3451	struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3452	int j;
3453
3454	debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3455	cmd_hdr = hisi_hba->cmd_hdr[i];
3456
3457	for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3458	memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3459	queue_entry_size);
3460	}
3461	}
3462
3463	static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3464	{
3465	int dump_index = hisi_hba->debugfs_dump_index;
3466	const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3467	int i, phy_cnt;
3468	u32 offset;
3469	u32 *databuf;
3470
3471	for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3472	databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3473	for (i = 0; i < port->count; i++, databuf++) {
3474	offset = port->base_off + 4 * i;
3475	*databuf = hisi_sas_phy_read32(hisi_hba, phy_no: phy_cnt,
3476	off: offset);
3477	}
3478	}
3479	}
3480
3481	static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3482	{
3483	int dump_index = hisi_hba->debugfs_dump_index;
3484	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3485	int i;
3486
3487	for (i = 0; i < debugfs_global_reg.count; i++, databuf++)
3488	*databuf = hisi_sas_read32(hisi_hba, off: 4 * i);
3489	}
3490
3491	static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3492	{
3493	int dump_index = hisi_hba->debugfs_dump_index;
3494	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3495	const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3496	int i;
3497
3498	for (i = 0; i < axi->count; i++, databuf++)
3499	*databuf = hisi_sas_read32(hisi_hba, off: 4 * i + axi->base_off);
3500	}
3501
3502	static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3503	{
3504	int dump_index = hisi_hba->debugfs_dump_index;
3505	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3506	const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3507	int i;
3508
3509	for (i = 0; i < ras->count; i++, databuf++)
3510	*databuf = hisi_sas_read32(hisi_hba, off: 4 * i + ras->base_off);
3511	}
3512
3513	static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3514	{
3515	int dump_index = hisi_hba->debugfs_dump_index;
3516	void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3517	void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3518	struct hisi_sas_itct *itct;
3519	int i;
3520
3521	read_iost_itct_cache_v3_hw(hisi_hba, type: HISI_SAS_ITCT_CACHE, cache: cachebuf);
3522
3523	itct = hisi_hba->itct;
3524
3525	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3526	memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3527	databuf += sizeof(struct hisi_sas_itct);
3528	}
3529	}
3530
3531	static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3532	{
3533	int dump_index = hisi_hba->debugfs_dump_index;
3534	int max_command_entries = HISI_SAS_MAX_COMMANDS;
3535	void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3536	void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3537	struct hisi_sas_iost *iost;
3538	int i;
3539
3540	read_iost_itct_cache_v3_hw(hisi_hba, type: HISI_SAS_IOST_CACHE, cache: cachebuf);
3541
3542	iost = hisi_hba->iost;
3543
3544	for (i = 0; i < max_command_entries; i++, iost++) {
3545	memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3546	databuf += sizeof(struct hisi_sas_iost);
3547	}
3548	}
3549
3550	static const char *
3551	debugfs_to_reg_name_v3_hw(int off, int base_off,
3552	const struct hisi_sas_debugfs_reg_lu *lu)
3553	{
3554	for (; lu->name; lu++) {
3555	if (off == lu->off - base_off)
3556	return lu->name;
3557	}
3558
3559	return NULL;
3560	}
3561
3562	static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3563	const struct hisi_sas_debugfs_reg *reg)
3564	{
3565	int i;
3566
3567	for (i = 0; i < reg->count; i++) {
3568	int off = i * 4;
3569	const char *name;
3570
3571	name = debugfs_to_reg_name_v3_hw(off, base_off: reg->base_off,
3572	lu: reg->lu);
3573
3574	if (name)
3575	seq_printf(m: s, fmt: "0x%08x 0x%08x %s\n", off,
3576	regs_val[i], name);
3577	else
3578	seq_printf(m: s, fmt: "0x%08x 0x%08x\n", off,
3579	regs_val[i]);
3580	}
3581	}
3582
3583	static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3584	{
3585	struct hisi_sas_debugfs_regs *global = s->private;
3586
3587	debugfs_print_reg_v3_hw(regs_val: global->data, s,
3588	reg: &debugfs_global_reg);
3589
3590	return 0;
3591	}
3592	DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3593
3594	static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3595	{
3596	struct hisi_sas_debugfs_regs *axi = s->private;
3597
3598	debugfs_print_reg_v3_hw(regs_val: axi->data, s,
3599	reg: &debugfs_axi_reg);
3600
3601	return 0;
3602	}
3603	DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3604
3605	static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3606	{
3607	struct hisi_sas_debugfs_regs *ras = s->private;
3608
3609	debugfs_print_reg_v3_hw(regs_val: ras->data, s,
3610	reg: &debugfs_ras_reg);
3611
3612	return 0;
3613	}
3614	DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3615
3616	static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3617	{
3618	struct hisi_sas_debugfs_port *port = s->private;
3619	const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3620
3621	debugfs_print_reg_v3_hw(regs_val: port->data, s, reg: reg_port);
3622
3623	return 0;
3624	}
3625	DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3626
3627	static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3628	int sz, __le64 *ptr)
3629	{
3630	int i;
3631
3632	/* completion header size not fixed per HW version */
3633	seq_printf(m: s, fmt: "index %04d:\n\t", index);
3634	for (i = 1; i <= sz / 8; i++, ptr++) {
3635	seq_printf(m: s, fmt: " 0x%016llx", le64_to_cpu(*ptr));
3636	if (!(i % 2))
3637	seq_puts(m: s, s: "\n\t");
3638	}
3639
3640	seq_puts(m: s, s: "\n");
3641	}
3642
3643	static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3644	int sz, __le32 *ptr)
3645	{
3646	int i;
3647
3648	/* completion header size not fixed per HW version */
3649	seq_printf(m: s, fmt: "index %04d:\n\t", index);
3650	for (i = 1; i <= sz / 4; i++, ptr++) {
3651	seq_printf(m: s, fmt: " 0x%08x", le32_to_cpu(*ptr));
3652	if (!(i % 4))
3653	seq_puts(m: s, s: "\n\t");
3654	}
3655	seq_puts(m: s, s: "\n");
3656	}
3657
3658	static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3659	struct hisi_sas_debugfs_cq *debugfs_cq)
3660	{
3661	struct hisi_sas_cq *cq = debugfs_cq->cq;
3662	struct hisi_hba *hisi_hba = cq->hisi_hba;
3663	__le32 *complete_hdr = debugfs_cq->complete_hdr +
3664	(hisi_hba->hw->complete_hdr_size * slot);
3665
3666	debugfs_show_row_32_v3_hw(s, index: slot,
3667	sz: hisi_hba->hw->complete_hdr_size,
3668	ptr: complete_hdr);
3669	}
3670
3671	static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3672	{
3673	struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3674	int slot;
3675
3676	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3677	debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3678
3679	return 0;
3680	}
3681	DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3682
3683	static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3684	void *dq_ptr)
3685	{
3686	struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3687	void *cmd_queue = debugfs_dq->hdr;
3688	__le32 *cmd_hdr = cmd_queue +
3689	sizeof(struct hisi_sas_cmd_hdr) * slot;
3690
3691	debugfs_show_row_32_v3_hw(s, index: slot, sz: sizeof(struct hisi_sas_cmd_hdr),
3692	ptr: cmd_hdr);
3693	}
3694
3695	static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3696	{
3697	int slot;
3698
3699	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3700	debugfs_dq_show_slot_v3_hw(s, slot, dq_ptr: s->private);
3701
3702	return 0;
3703	}
3704	DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3705
3706	static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3707	{
3708	struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3709	struct hisi_sas_iost *iost = debugfs_iost->iost;
3710	int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3711
3712	for (i = 0; i < max_command_entries; i++, iost++) {
3713	__le64 *data = &iost->qw0;
3714
3715	debugfs_show_row_64_v3_hw(s, index: i, sz: sizeof(*iost), ptr: data);
3716	}
3717
3718	return 0;
3719	}
3720	DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3721
3722	static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3723	{
3724	struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3725	struct hisi_sas_iost_itct_cache *iost_cache =
3726	debugfs_iost_cache->cache;
3727	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3728	int i, tab_idx;
3729	__le64 *iost;
3730
3731	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3732	/*
3733	* Data struct of IOST cache:
3734	* Data[1]: BIT0~15: Table index
3735	* Bit16: Valid mask
3736	* Data[2]~[9]: IOST table
3737	*/
3738	tab_idx = (iost_cache->data[1] & 0xffff);
3739	iost = (__le64 *)iost_cache;
3740
3741	debugfs_show_row_64_v3_hw(s, index: tab_idx, sz: cache_size, ptr: iost);
3742	}
3743
3744	return 0;
3745	}
3746	DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3747
3748	static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3749	{
3750	int i;
3751	struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3752	struct hisi_sas_itct *itct = debugfs_itct->itct;
3753
3754	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3755	__le64 *data = &itct->qw0;
3756
3757	debugfs_show_row_64_v3_hw(s, index: i, sz: sizeof(*itct), ptr: data);
3758	}
3759
3760	return 0;
3761	}
3762	DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3763
3764	static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3765	{
3766	struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3767	struct hisi_sas_iost_itct_cache *itct_cache =
3768	debugfs_itct_cache->cache;
3769	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3770	int i, tab_idx;
3771	__le64 *itct;
3772
3773	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3774	/*
3775	* Data struct of ITCT cache:
3776	* Data[1]: BIT0~15: Table index
3777	* Bit16: Valid mask
3778	* Data[2]~[9]: ITCT table
3779	*/
3780	tab_idx = itct_cache->data[1] & 0xffff;
3781	itct = (__le64 *)itct_cache;
3782
3783	debugfs_show_row_64_v3_hw(s, index: tab_idx, sz: cache_size, ptr: itct);
3784	}
3785
3786	return 0;
3787	}
3788	DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3789
3790	static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3791	{
3792	u64 *debugfs_timestamp;
3793	int dump_index = hisi_hba->debugfs_dump_index;
3794	struct dentry *dump_dentry;
3795	struct dentry *dentry;
3796	char name[256];
3797	int p;
3798	int c;
3799	int d;
3800
3801	snprintf(buf: name, size: 256, fmt: "%d", dump_index);
3802
3803	dump_dentry = debugfs_create_dir(name, parent: hisi_hba->debugfs_dump_dentry);
3804
3805	debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3806
3807	debugfs_create_u64(name: "timestamp", mode: 0400, parent: dump_dentry,
3808	value: debugfs_timestamp);
3809
3810	debugfs_create_file(name: "global", mode: 0400, parent: dump_dentry,
3811	data: &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3812	fops: &debugfs_global_v3_hw_fops);
3813
3814	/* Create port dir and files */
3815	dentry = debugfs_create_dir(name: "port", parent: dump_dentry);
3816	for (p = 0; p < hisi_hba->n_phy; p++) {
3817	snprintf(buf: name, size: 256, fmt: "%d", p);
3818
3819	debugfs_create_file(name, mode: 0400, parent: dentry,
3820	data: &hisi_hba->debugfs_port_reg[dump_index][p],
3821	fops: &debugfs_port_v3_hw_fops);
3822	}
3823
3824	/* Create CQ dir and files */
3825	dentry = debugfs_create_dir(name: "cq", parent: dump_dentry);
3826	for (c = 0; c < hisi_hba->queue_count; c++) {
3827	snprintf(buf: name, size: 256, fmt: "%d", c);
3828
3829	debugfs_create_file(name, mode: 0400, parent: dentry,
3830	data: &hisi_hba->debugfs_cq[dump_index][c],
3831	fops: &debugfs_cq_v3_hw_fops);
3832	}
3833
3834	/* Create DQ dir and files */
3835	dentry = debugfs_create_dir(name: "dq", parent: dump_dentry);
3836	for (d = 0; d < hisi_hba->queue_count; d++) {
3837	snprintf(buf: name, size: 256, fmt: "%d", d);
3838
3839	debugfs_create_file(name, mode: 0400, parent: dentry,
3840	data: &hisi_hba->debugfs_dq[dump_index][d],
3841	fops: &debugfs_dq_v3_hw_fops);
3842	}
3843
3844	debugfs_create_file(name: "iost", mode: 0400, parent: dump_dentry,
3845	data: &hisi_hba->debugfs_iost[dump_index],
3846	fops: &debugfs_iost_v3_hw_fops);
3847
3848	debugfs_create_file(name: "iost_cache", mode: 0400, parent: dump_dentry,
3849	data: &hisi_hba->debugfs_iost_cache[dump_index],
3850	fops: &debugfs_iost_cache_v3_hw_fops);
3851
3852	debugfs_create_file(name: "itct", mode: 0400, parent: dump_dentry,
3853	data: &hisi_hba->debugfs_itct[dump_index],
3854	fops: &debugfs_itct_v3_hw_fops);
3855
3856	debugfs_create_file(name: "itct_cache", mode: 0400, parent: dump_dentry,
3857	data: &hisi_hba->debugfs_itct_cache[dump_index],
3858	fops: &debugfs_itct_cache_v3_hw_fops);
3859
3860	debugfs_create_file(name: "axi", mode: 0400, parent: dump_dentry,
3861	data: &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3862	fops: &debugfs_axi_v3_hw_fops);
3863
3864	debugfs_create_file(name: "ras", mode: 0400, parent: dump_dentry,
3865	data: &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3866	fops: &debugfs_ras_v3_hw_fops);
3867	}
3868
3869	static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3870	const char __user *user_buf,
3871	size_t count, loff_t *ppos)
3872	{
3873	struct hisi_hba *hisi_hba = file->f_inode->i_private;
3874	char buf[8];
3875
3876	if (count > 8)
3877	return -EFAULT;
3878
3879	if (copy_from_user(to: buf, from: user_buf, n: count))
3880	return -EFAULT;
3881
3882	if (buf[0] != '1')
3883	return -EFAULT;
3884
3885	down(sem: &hisi_hba->sem);
3886	if (debugfs_snapshot_regs_v3_hw(hisi_hba)) {
3887	up(sem: &hisi_hba->sem);
3888	return -EFAULT;
3889	}
3890	up(sem: &hisi_hba->sem);
3891
3892	return count;
3893	}
3894
3895	static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3896	.write = &debugfs_trigger_dump_v3_hw_write,
3897	.owner = THIS_MODULE,
3898	};
3899
3900	enum {
3901	HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3902	HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3903	HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3904	};
3905
3906	static const struct {
3907	int value;
3908	char *name;
3909	} debugfs_loop_linkrate_v3_hw[] = {
3910	{ SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3911	{ SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3912	{ SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3913	{ SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3914	};
3915
3916	static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3917	{
3918	struct hisi_hba *hisi_hba = s->private;
3919	int i;
3920
3921	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3922	int match = (hisi_hba->debugfs_bist_linkrate ==
3923	debugfs_loop_linkrate_v3_hw[i].value);
3924
3925	seq_printf(m: s, fmt: "%s%s%s ", match ? "[" : "",
3926	debugfs_loop_linkrate_v3_hw[i].name,
3927	match ? "]" : "");
3928	}
3929	seq_puts(m: s, s: "\n");
3930
3931	return 0;
3932	}
3933
3934	static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3935	const char __user *buf,
3936	size_t count, loff_t *ppos)
3937	{
3938	struct seq_file *m = filp->private_data;
3939	struct hisi_hba *hisi_hba = m->private;
3940	char kbuf[16] = {}, *pkbuf;
3941	bool found = false;
3942	int i;
3943
3944	if (hisi_hba->debugfs_bist_enable)
3945	return -EPERM;
3946
3947	if (count >= sizeof(kbuf))
3948	return -EOVERFLOW;
3949
3950	if (copy_from_user(to: kbuf, from: buf, n: count))
3951	return -EINVAL;
3952
3953	pkbuf = strstrip(str: kbuf);
3954
3955	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3956	if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3957	pkbuf, 16)) {
3958	hisi_hba->debugfs_bist_linkrate =
3959	debugfs_loop_linkrate_v3_hw[i].value;
3960	found = true;
3961	break;
3962	}
3963	}
3964
3965	if (!found)
3966	return -EINVAL;
3967
3968	return count;
3969	}
3970	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_linkrate_v3_hw);
3971
3972	static const struct {
3973	int value;
3974	char *name;
3975	} debugfs_loop_code_mode_v3_hw[] = {
3976	{ HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
3977	{ HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
3978	{ HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
3979	{ HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
3980	{ HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
3981	{ HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
3982	{ HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
3983	{ HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
3984	{ HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
3985	{ HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
3986	{ HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
3987	{ HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
3988	};
3989
3990	static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
3991	{
3992	struct hisi_hba *hisi_hba = s->private;
3993	int i;
3994
3995	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3996	int match = (hisi_hba->debugfs_bist_code_mode ==
3997	debugfs_loop_code_mode_v3_hw[i].value);
3998
3999	seq_printf(m: s, fmt: "%s%s%s ", match ? "[" : "",
4000	debugfs_loop_code_mode_v3_hw[i].name,
4001	match ? "]" : "");
4002	}
4003	seq_puts(m: s, s: "\n");
4004
4005	return 0;
4006	}
4007
4008	static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
4009	const char __user *buf,
4010	size_t count,
4011	loff_t *ppos)
4012	{
4013	struct seq_file *m = filp->private_data;
4014	struct hisi_hba *hisi_hba = m->private;
4015	char kbuf[16] = {}, *pkbuf;
4016	bool found = false;
4017	int i;
4018
4019	if (hisi_hba->debugfs_bist_enable)
4020	return -EPERM;
4021
4022	if (count >= sizeof(kbuf))
4023	return -EINVAL;
4024
4025	if (copy_from_user(to: kbuf, from: buf, n: count))
4026	return -EOVERFLOW;
4027
4028	pkbuf = strstrip(str: kbuf);
4029
4030	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
4031	if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
4032	pkbuf, 16)) {
4033	hisi_hba->debugfs_bist_code_mode =
4034	debugfs_loop_code_mode_v3_hw[i].value;
4035	found = true;
4036	break;
4037	}
4038	}
4039
4040	if (!found)
4041	return -EINVAL;
4042
4043	return count;
4044	}
4045	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_code_mode_v3_hw);
4046
4047	static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
4048	const char __user *buf,
4049	size_t count, loff_t *ppos)
4050	{
4051	struct seq_file *m = filp->private_data;
4052	struct hisi_hba *hisi_hba = m->private;
4053	unsigned int phy_no;
4054	int val;
4055
4056	if (hisi_hba->debugfs_bist_enable)
4057	return -EPERM;
4058
4059	val = kstrtouint_from_user(s: buf, count, base: 0, res: &phy_no);
4060	if (val)
4061	return val;
4062
4063	if (phy_no >= hisi_hba->n_phy)
4064	return -EINVAL;
4065
4066	hisi_hba->debugfs_bist_phy_no = phy_no;
4067
4068	return count;
4069	}
4070
4071	static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
4072	{
4073	struct hisi_hba *hisi_hba = s->private;
4074
4075	seq_printf(m: s, fmt: "%d\n", hisi_hba->debugfs_bist_phy_no);
4076
4077	return 0;
4078	}
4079	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_phy_v3_hw);
4080
4081	static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
4082	const char __user *buf,
4083	size_t count, loff_t *ppos)
4084	{
4085	struct seq_file *m = filp->private_data;
4086	struct hisi_hba *hisi_hba = m->private;
4087	unsigned int cnt;
4088	int val;
4089
4090	if (hisi_hba->debugfs_bist_enable)
4091	return -EPERM;
4092
4093	val = kstrtouint_from_user(s: buf, count, base: 0, res: &cnt);
4094	if (val)
4095	return val;
4096
4097	if (cnt)
4098	return -EINVAL;
4099
4100	hisi_hba->debugfs_bist_cnt = 0;
4101	return count;
4102	}
4103
4104	static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4105	{
4106	struct hisi_hba *hisi_hba = s->private;
4107
4108	seq_printf(m: s, fmt: "%u\n", hisi_hba->debugfs_bist_cnt);
4109
4110	return 0;
4111	}
4112	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_cnt_v3_hw);
4113
4114	static const struct {
4115	int value;
4116	char *name;
4117	} debugfs_loop_modes_v3_hw[] = {
4118	{ HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4119	{ HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4120	{ HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4121	};
4122
4123	static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4124	{
4125	struct hisi_hba *hisi_hba = s->private;
4126	int i;
4127
4128	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4129	int match = (hisi_hba->debugfs_bist_mode ==
4130	debugfs_loop_modes_v3_hw[i].value);
4131
4132	seq_printf(m: s, fmt: "%s%s%s ", match ? "[" : "",
4133	debugfs_loop_modes_v3_hw[i].name,
4134	match ? "]" : "");
4135	}
4136	seq_puts(m: s, s: "\n");
4137
4138	return 0;
4139	}
4140
4141	static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4142	const char __user *buf,
4143	size_t count, loff_t *ppos)
4144	{
4145	struct seq_file *m = filp->private_data;
4146	struct hisi_hba *hisi_hba = m->private;
4147	char kbuf[16] = {}, *pkbuf;
4148	bool found = false;
4149	int i;
4150
4151	if (hisi_hba->debugfs_bist_enable)
4152	return -EPERM;
4153
4154	if (count >= sizeof(kbuf))
4155	return -EINVAL;
4156
4157	if (copy_from_user(to: kbuf, from: buf, n: count))
4158	return -EOVERFLOW;
4159
4160	pkbuf = strstrip(str: kbuf);
4161
4162	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4163	if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4164	hisi_hba->debugfs_bist_mode =
4165	debugfs_loop_modes_v3_hw[i].value;
4166	found = true;
4167	break;
4168	}
4169	}
4170
4171	if (!found)
4172	return -EINVAL;
4173
4174	return count;
4175	}
4176	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_mode_v3_hw);
4177
4178	static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4179	const char __user *buf,
4180	size_t count, loff_t *ppos)
4181	{
4182	struct seq_file *m = filp->private_data;
4183	struct hisi_hba *hisi_hba = m->private;
4184	unsigned int enable;
4185	int val;
4186
4187	val = kstrtouint_from_user(s: buf, count, base: 0, res: &enable);
4188	if (val)
4189	return val;
4190
4191	if (enable > 1)
4192	return -EINVAL;
4193
4194	if (enable == hisi_hba->debugfs_bist_enable)
4195	return count;
4196
4197	val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4198	if (val < 0)
4199	return val;
4200
4201	hisi_hba->debugfs_bist_enable = enable;
4202
4203	return count;
4204	}
4205
4206	static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4207	{
4208	struct hisi_hba *hisi_hba = s->private;
4209
4210	seq_printf(m: s, fmt: "%d\n", hisi_hba->debugfs_bist_enable);
4211
4212	return 0;
4213	}
4214	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_bist_enable_v3_hw);
4215
4216	static const struct {
4217	char *name;
4218	} debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4219	{ "SAS_1_5_GBPS" },
4220	{ "SAS_3_0_GBPS" },
4221	{ "SAS_6_0_GBPS" },
4222	{ "SAS_12_0_GBPS" },
4223	{ "FFE_RESV" },
4224	{ "SATA_1_5_GBPS" },
4225	{ "SATA_3_0_GBPS" },
4226	{ "SATA_6_0_GBPS" },
4227	};
4228
4229	static ssize_t debugfs_v3_hw_write(struct file *filp,
4230	const char __user *buf,
4231	size_t count, loff_t *ppos)
4232	{
4233	struct seq_file *m = filp->private_data;
4234	u32 *val = m->private;
4235	int res;
4236
4237	res = kstrtouint_from_user(s: buf, count, base: 0, res: val);
4238	if (res)
4239	return res;
4240
4241	return count;
4242	}
4243
4244	static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4245	{
4246	u32 *val = s->private;
4247
4248	seq_printf(m: s, fmt: "0x%x\n", *val);
4249
4250	return 0;
4251	}
4252	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_v3_hw);
4253
4254	static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4255	const char __user *buf,
4256	size_t count, loff_t *ppos)
4257	{
4258	struct seq_file *s = filp->private_data;
4259	struct hisi_sas_phy *phy = s->private;
4260	unsigned int set_val;
4261	int res;
4262
4263	res = kstrtouint_from_user(s: buf, count, base: 0, res: &set_val);
4264	if (res)
4265	return res;
4266
4267	if (set_val > 0)
4268	return -EINVAL;
4269
4270	atomic_set(v: &phy->down_cnt, i: 0);
4271
4272	return count;
4273	}
4274
4275	static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4276	{
4277	struct hisi_sas_phy *phy = s->private;
4278
4279	seq_printf(m: s, fmt: "%d\n", atomic_read(v: &phy->down_cnt));
4280
4281	return 0;
4282	}
4283	DEFINE_SHOW_STORE_ATTRIBUTE(debugfs_phy_down_cnt_v3_hw);
4284
4285	enum fifo_dump_mode_v3_hw {
4286	FIFO_DUMP_FORVER = (1U << 0),
4287	FIFO_DUMP_AFTER_TRIGGER = (1U << 1),
4288	FIFO_DUMP_UNTILL_TRIGGER = (1U << 2),
4289	};
4290
4291	enum fifo_trigger_mode_v3_hw {
4292	FIFO_TRIGGER_EDGE = (1U << 0),
4293	FIFO_TRIGGER_SAME_LEVEL = (1U << 1),
4294	FIFO_TRIGGER_DIFF_LEVEL = (1U << 2),
4295	};
4296
4297	static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4298	{
4299	struct hisi_hba *hisi_hba = phy->hisi_hba;
4300
4301	if (phy->fifo.signal_sel > 0xf) {
4302	dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4303	phy->fifo.signal_sel);
4304	return -EINVAL;
4305	}
4306
4307	switch (phy->fifo.dump_mode) {
4308	case FIFO_DUMP_FORVER:
4309	case FIFO_DUMP_AFTER_TRIGGER:
4310	case FIFO_DUMP_UNTILL_TRIGGER:
4311	break;
4312	default:
4313	dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4314	phy->fifo.dump_mode);
4315	return -EINVAL;
4316	}
4317
4318	/* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4319	if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4320	return 0;
4321
4322	switch (phy->fifo.trigger_mode) {
4323	case FIFO_TRIGGER_EDGE:
4324	case FIFO_TRIGGER_SAME_LEVEL:
4325	case FIFO_TRIGGER_DIFF_LEVEL:
4326	break;
4327	default:
4328	dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4329	phy->fifo.trigger_mode);
4330	return -EINVAL;
4331	}
4332	return 0;
4333	}
4334
4335	static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4336	{
4337	u32 trigger_mode = phy->fifo.trigger_mode;
4338	u32 signal_sel = phy->fifo.signal_sel;
4339	u32 dump_mode = phy->fifo.dump_mode;
4340	struct hisi_hba *hisi_hba = phy->hisi_hba;
4341	int phy_no = phy->sas_phy.id;
4342	u32 reg_val;
4343	int res;
4344
4345	/* Check the validity of trace FIFO configuration */
4346	res = debugfs_is_fifo_config_valid_v3_hw(phy);
4347	if (res)
4348	return res;
4349
4350	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4351	/* Disable trace FIFO before update configuration */
4352	reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4353
4354	/* Update trace FIFO configuration */
4355	reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4356	DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4357	DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4358
4359	reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4360	(dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4361	(signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4362	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val: reg_val);
4363
4364	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4365	val: phy->fifo.dump_msk);
4366
4367	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4368	val: phy->fifo.trigger);
4369
4370	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4371	val: phy->fifo.trigger_msk);
4372
4373	/* Enable trace FIFO after updated configuration */
4374	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4375	reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4376	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val: reg_val);
4377
4378	return 0;
4379	}
4380
4381	static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4382	const char __user *buf,
4383	size_t count, loff_t *ppos)
4384	{
4385	struct hisi_sas_phy *phy = filp->private_data;
4386	bool update;
4387	int val;
4388
4389	val = kstrtobool_from_user(s: buf, count, res: &update);
4390	if (val)
4391	return val;
4392
4393	if (update != 1)
4394	return -EINVAL;
4395
4396	val = debugfs_update_fifo_config_v3_hw(phy);
4397	if (val)
4398	return val;
4399
4400	return count;
4401	}
4402
4403	static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4404	.open = simple_open,
4405	.write = debugfs_fifo_update_cfg_v3_hw_write,
4406	.owner = THIS_MODULE,
4407	};
4408
4409	static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4410	{
4411	struct hisi_hba *hisi_hba = phy->hisi_hba;
4412	u32 *buf = phy->fifo.rd_data;
4413	int phy_no = phy->sas_phy.id;
4414	u32 val;
4415	int i;
4416
4417	memset(buf, 0, sizeof(phy->fifo.rd_data));
4418
4419	/* Disable trace FIFO before read data */
4420	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4421	val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4422	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4423
4424	for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4425	val = hisi_sas_phy_read32(hisi_hba, phy_no,
4426	DFX_FIFO_RD_DATA);
4427	buf[i] = val;
4428	}
4429
4430	/* Enable trace FIFO after read data */
4431	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4432	val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4433	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4434	}
4435
4436	static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4437	{
4438	struct hisi_sas_phy *phy = s->private;
4439
4440	debugfs_read_fifo_data_v3_hw(phy);
4441
4442	debugfs_show_row_32_v3_hw(s, index: 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4443	ptr: (__le32 *)phy->fifo.rd_data);
4444
4445	return 0;
4446	}
4447	DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4448
4449	static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4450	{
4451	int phy_no;
4452
4453	hisi_hba->debugfs_fifo_dentry =
4454	debugfs_create_dir(name: "fifo", parent: hisi_hba->debugfs_dir);
4455
4456	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4457	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4458	struct dentry *port_dentry;
4459	char name[256];
4460	u32 val;
4461
4462	/* get default configuration for trace FIFO */
4463	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4464	val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4465	val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4466	phy->fifo.dump_mode = val;
4467
4468	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4469	val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4470	val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4471	phy->fifo.trigger_mode = val;
4472
4473	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4474	val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4475	val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4476	phy->fifo.signal_sel = val;
4477
4478	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4479	phy->fifo.dump_msk = val;
4480
4481	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4482	phy->fifo.trigger = val;
4483	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4484	phy->fifo.trigger_msk = val;
4485
4486	snprintf(buf: name, size: 256, fmt: "%d", phy_no);
4487	port_dentry = debugfs_create_dir(name,
4488	parent: hisi_hba->debugfs_fifo_dentry);
4489
4490	debugfs_create_file(name: "update_config", mode: 0200, parent: port_dentry, data: phy,
4491	fops: &debugfs_fifo_update_cfg_v3_hw_fops);
4492
4493	debugfs_create_file(name: "signal_sel", mode: 0600, parent: port_dentry,
4494	data: &phy->fifo.signal_sel,
4495	fops: &debugfs_v3_hw_fops);
4496
4497	debugfs_create_file(name: "dump_msk", mode: 0600, parent: port_dentry,
4498	data: &phy->fifo.dump_msk,
4499	fops: &debugfs_v3_hw_fops);
4500
4501	debugfs_create_file(name: "dump_mode", mode: 0600, parent: port_dentry,
4502	data: &phy->fifo.dump_mode,
4503	fops: &debugfs_v3_hw_fops);
4504
4505	debugfs_create_file(name: "trigger_mode", mode: 0600, parent: port_dentry,
4506	data: &phy->fifo.trigger_mode,
4507	fops: &debugfs_v3_hw_fops);
4508
4509	debugfs_create_file(name: "trigger", mode: 0600, parent: port_dentry,
4510	data: &phy->fifo.trigger,
4511	fops: &debugfs_v3_hw_fops);
4512
4513	debugfs_create_file(name: "trigger_msk", mode: 0600, parent: port_dentry,
4514	data: &phy->fifo.trigger_msk,
4515	fops: &debugfs_v3_hw_fops);
4516
4517	debugfs_create_file(name: "fifo_data", mode: 0400, parent: port_dentry, data: phy,
4518	fops: &debugfs_fifo_data_v3_hw_fops);
4519	}
4520	}
4521
4522	static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4523	{
4524	struct device *dev = hisi_hba->dev;
4525	int i;
4526
4527	devm_kfree(dev, p: hisi_hba->debugfs_iost_cache[dump_index].cache);
4528	devm_kfree(dev, p: hisi_hba->debugfs_itct_cache[dump_index].cache);
4529	devm_kfree(dev, p: hisi_hba->debugfs_iost[dump_index].iost);
4530	devm_kfree(dev, p: hisi_hba->debugfs_itct[dump_index].itct);
4531
4532	for (i = 0; i < hisi_hba->queue_count; i++)
4533	devm_kfree(dev, p: hisi_hba->debugfs_dq[dump_index][i].hdr);
4534
4535	for (i = 0; i < hisi_hba->queue_count; i++)
4536	devm_kfree(dev,
4537	p: hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4538
4539	for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4540	devm_kfree(dev, p: hisi_hba->debugfs_regs[dump_index][i].data);
4541
4542	for (i = 0; i < hisi_hba->n_phy; i++)
4543	devm_kfree(dev, p: hisi_hba->debugfs_port_reg[dump_index][i].data);
4544	}
4545
4546	static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4547	[DEBUGFS_GLOBAL] = &debugfs_global_reg,
4548	[DEBUGFS_AXI] = &debugfs_axi_reg,
4549	[DEBUGFS_RAS] = &debugfs_ras_reg,
4550	};
4551
4552	static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4553	{
4554	const struct hisi_sas_hw *hw = hisi_hba->hw;
4555	struct device *dev = hisi_hba->dev;
4556	int p, c, d, r;
4557	size_t sz;
4558
4559	for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4560	struct hisi_sas_debugfs_regs *regs =
4561	&hisi_hba->debugfs_regs[dump_index][r];
4562
4563	sz = debugfs_reg_array_v3_hw[r]->count * 4;
4564	regs->data = devm_kmalloc(dev, size: sz, GFP_KERNEL);
4565	if (!regs->data)
4566	goto fail;
4567	regs->hisi_hba = hisi_hba;
4568	}
4569
4570	sz = debugfs_port_reg.count * 4;
4571	for (p = 0; p < hisi_hba->n_phy; p++) {
4572	struct hisi_sas_debugfs_port *port =
4573	&hisi_hba->debugfs_port_reg[dump_index][p];
4574
4575	port->data = devm_kmalloc(dev, size: sz, GFP_KERNEL);
4576	if (!port->data)
4577	goto fail;
4578	port->phy = &hisi_hba->phy[p];
4579	}
4580
4581	sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4582	for (c = 0; c < hisi_hba->queue_count; c++) {
4583	struct hisi_sas_debugfs_cq *cq =
4584	&hisi_hba->debugfs_cq[dump_index][c];
4585
4586	cq->complete_hdr = devm_kmalloc(dev, size: sz, GFP_KERNEL);
4587	if (!cq->complete_hdr)
4588	goto fail;
4589	cq->cq = &hisi_hba->cq[c];
4590	}
4591
4592	sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4593	for (d = 0; d < hisi_hba->queue_count; d++) {
4594	struct hisi_sas_debugfs_dq *dq =
4595	&hisi_hba->debugfs_dq[dump_index][d];
4596
4597	dq->hdr = devm_kmalloc(dev, size: sz, GFP_KERNEL);
4598	if (!dq->hdr)
4599	goto fail;
4600	dq->dq = &hisi_hba->dq[d];
4601	}
4602
4603	sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4604
4605	hisi_hba->debugfs_iost[dump_index].iost =
4606	devm_kmalloc(dev, size: sz, GFP_KERNEL);
4607	if (!hisi_hba->debugfs_iost[dump_index].iost)
4608	goto fail;
4609
4610	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4611	sizeof(struct hisi_sas_iost_itct_cache);
4612
4613	hisi_hba->debugfs_iost_cache[dump_index].cache =
4614	devm_kmalloc(dev, size: sz, GFP_KERNEL);
4615	if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4616	goto fail;
4617
4618	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4619	sizeof(struct hisi_sas_iost_itct_cache);
4620
4621	hisi_hba->debugfs_itct_cache[dump_index].cache =
4622	devm_kmalloc(dev, size: sz, GFP_KERNEL);
4623	if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4624	goto fail;
4625
4626	/* New memory allocation must be locate before itct */
4627	sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4628
4629	hisi_hba->debugfs_itct[dump_index].itct =
4630	devm_kmalloc(dev, size: sz, GFP_KERNEL);
4631	if (!hisi_hba->debugfs_itct[dump_index].itct)
4632	goto fail;
4633
4634	return 0;
4635	fail:
4636	debugfs_release_v3_hw(hisi_hba, dump_index);
4637	return -ENOMEM;
4638	}
4639
4640	static int debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
4641	{
4642	int debugfs_dump_index = hisi_hba->debugfs_dump_index;
4643	struct device *dev = hisi_hba->dev;
4644	u64 timestamp = local_clock();
4645
4646	if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
4647	dev_warn(dev, "dump count exceeded!\n");
4648	return -EINVAL;
4649	}
4650
4651	if (debugfs_alloc_v3_hw(hisi_hba, dump_index: debugfs_dump_index)) {
4652	dev_warn(dev, "failed to alloc memory\n");
4653	return -ENOMEM;
4654	}
4655
4656	do_div(timestamp, NSEC_PER_MSEC);
4657	hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
4658
4659	debugfs_snapshot_prepare_v3_hw(hisi_hba);
4660
4661	debugfs_snapshot_global_reg_v3_hw(hisi_hba);
4662	debugfs_snapshot_port_reg_v3_hw(hisi_hba);
4663	debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
4664	debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
4665	debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
4666	debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
4667	debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
4668	debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
4669
4670	debugfs_create_files_v3_hw(hisi_hba);
4671
4672	debugfs_snapshot_restore_v3_hw(hisi_hba);
4673	hisi_hba->debugfs_dump_index++;
4674
4675	return 0;
4676	}
4677
4678	static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4679	{
4680	struct dentry *dir = debugfs_create_dir(name: "phy_down_cnt",
4681	parent: hisi_hba->debugfs_dir);
4682	char name[16];
4683	int phy_no;
4684
4685	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4686	snprintf(buf: name, size: 16, fmt: "%d", phy_no);
4687	debugfs_create_file(name, mode: 0600, parent: dir,
4688	data: &hisi_hba->phy[phy_no],
4689	fops: &debugfs_phy_down_cnt_v3_hw_fops);
4690	}
4691	}
4692
4693	static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4694	{
4695	struct dentry *ports_dentry;
4696	int phy_no;
4697
4698	hisi_hba->debugfs_bist_dentry =
4699	debugfs_create_dir(name: "bist", parent: hisi_hba->debugfs_dir);
4700	debugfs_create_file(name: "link_rate", mode: 0600,
4701	parent: hisi_hba->debugfs_bist_dentry, data: hisi_hba,
4702	fops: &debugfs_bist_linkrate_v3_hw_fops);
4703
4704	debugfs_create_file(name: "code_mode", mode: 0600,
4705	parent: hisi_hba->debugfs_bist_dentry, data: hisi_hba,
4706	fops: &debugfs_bist_code_mode_v3_hw_fops);
4707
4708	debugfs_create_file(name: "fixed_code", mode: 0600,
4709	parent: hisi_hba->debugfs_bist_dentry,
4710	data: &hisi_hba->debugfs_bist_fixed_code[0],
4711	fops: &debugfs_v3_hw_fops);
4712
4713	debugfs_create_file(name: "fixed_code_1", mode: 0600,
4714	parent: hisi_hba->debugfs_bist_dentry,
4715	data: &hisi_hba->debugfs_bist_fixed_code[1],
4716	fops: &debugfs_v3_hw_fops);
4717
4718	debugfs_create_file(name: "phy_id", mode: 0600, parent: hisi_hba->debugfs_bist_dentry,
4719	data: hisi_hba, fops: &debugfs_bist_phy_v3_hw_fops);
4720
4721	debugfs_create_file(name: "cnt", mode: 0600, parent: hisi_hba->debugfs_bist_dentry,
4722	data: hisi_hba, fops: &debugfs_bist_cnt_v3_hw_fops);
4723
4724	debugfs_create_file(name: "loopback_mode", mode: 0600,
4725	parent: hisi_hba->debugfs_bist_dentry,
4726	data: hisi_hba, fops: &debugfs_bist_mode_v3_hw_fops);
4727
4728	debugfs_create_file(name: "enable", mode: 0600, parent: hisi_hba->debugfs_bist_dentry,
4729	data: hisi_hba, fops: &debugfs_bist_enable_v3_hw_fops);
4730
4731	ports_dentry = debugfs_create_dir(name: "port", parent: hisi_hba->debugfs_bist_dentry);
4732
4733	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4734	struct dentry *port_dentry;
4735	struct dentry *ffe_dentry;
4736	char name[256];
4737	int i;
4738
4739	snprintf(buf: name, size: 256, fmt: "%d", phy_no);
4740	port_dentry = debugfs_create_dir(name, parent: ports_dentry);
4741	ffe_dentry = debugfs_create_dir(name: "ffe", parent: port_dentry);
4742	for (i = 0; i < FFE_CFG_MAX; i++) {
4743	if (i == FFE_RESV)
4744	continue;
4745	debugfs_create_file(name: debugfs_ffe_name_v3_hw[i].name,
4746	mode: 0600, parent: ffe_dentry,
4747	data: &hisi_hba->debugfs_bist_ffe[phy_no][i],
4748	fops: &debugfs_v3_hw_fops);
4749	}
4750	}
4751
4752	hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4753	}
4754
4755	static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4756	{
4757	debugfs_remove_recursive(dentry: hisi_hba->debugfs_dir);
4758	hisi_hba->debugfs_dir = NULL;
4759	}
4760
4761	static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4762	{
4763	struct device *dev = hisi_hba->dev;
4764
4765	hisi_hba->debugfs_dir = debugfs_create_dir(name: dev_name(dev),
4766	parent: hisi_sas_debugfs_dir);
4767	debugfs_create_file(name: "trigger_dump", mode: 0200,
4768	parent: hisi_hba->debugfs_dir,
4769	data: hisi_hba,
4770	fops: &debugfs_trigger_dump_v3_hw_fops);
4771
4772	/* create bist structures */
4773	debugfs_bist_init_v3_hw(hisi_hba);
4774
4775	hisi_hba->debugfs_dump_dentry =
4776	debugfs_create_dir(name: "dump", parent: hisi_hba->debugfs_dir);
4777
4778	debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4779	debugfs_fifo_init_v3_hw(hisi_hba);
4780	}
4781
4782	static int
4783	hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4784	{
4785	struct Scsi_Host *shost;
4786	struct hisi_hba *hisi_hba;
4787	struct device *dev = &pdev->dev;
4788	struct asd_sas_phy **arr_phy;
4789	struct asd_sas_port **arr_port;
4790	struct sas_ha_struct *sha;
4791	int rc, phy_nr, port_nr, i;
4792
4793	rc = pcim_enable_device(pdev);
4794	if (rc)
4795	goto err_out;
4796
4797	pci_set_master(dev: pdev);
4798
4799	rc = pcim_iomap_regions(pdev, mask: 1 << BAR_NO_V3_HW, DRV_NAME);
4800	if (rc)
4801	goto err_out;
4802
4803	rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
4804	if (rc) {
4805	dev_err(dev, "No usable DMA addressing method\n");
4806	rc = -ENODEV;
4807	goto err_out;
4808	}
4809
4810	shost = hisi_sas_shost_alloc_pci(pdev);
4811	if (!shost) {
4812	rc = -ENOMEM;
4813	goto err_out;
4814	}
4815
4816	sha = SHOST_TO_SAS_HA(shost);
4817	hisi_hba = shost_priv(shost);
4818	dev_set_drvdata(dev, data: sha);
4819
4820	hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4821	if (!hisi_hba->regs) {
4822	dev_err(dev, "cannot map register\n");
4823	rc = -ENOMEM;
4824	goto err_out_free_host;
4825	}
4826
4827	phy_nr = port_nr = hisi_hba->n_phy;
4828
4829	arr_phy = devm_kcalloc(dev, n: phy_nr, size: sizeof(void *), GFP_KERNEL);
4830	arr_port = devm_kcalloc(dev, n: port_nr, size: sizeof(void *), GFP_KERNEL);
4831	if (!arr_phy || !arr_port) {
4832	rc = -ENOMEM;
4833	goto err_out_free_host;
4834	}
4835
4836	sha->sas_phy = arr_phy;
4837	sha->sas_port = arr_port;
4838	sha->shost = shost;
4839	sha->lldd_ha = hisi_hba;
4840
4841	shost->transportt = hisi_sas_stt;
4842	shost->max_id = HISI_SAS_MAX_DEVICES;
4843	shost->max_lun = ~0;
4844	shost->max_channel = 1;
4845	shost->max_cmd_len = 16;
4846	shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4847	shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4848	if (hisi_hba->iopoll_q_cnt)
4849	shost->nr_maps = 3;
4850	else
4851	shost->nr_maps = 1;
4852
4853	sha->sas_ha_name = DRV_NAME;
4854	sha->dev = dev;
4855	sha->sas_addr = &hisi_hba->sas_addr[0];
4856	sha->num_phys = hisi_hba->n_phy;
4857
4858	for (i = 0; i < hisi_hba->n_phy; i++) {
4859	sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4860	sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4861	}
4862
4863	if (hisi_hba->prot_mask) {
4864	dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4865	prot_mask);
4866	scsi_host_set_prot(shost: hisi_hba->shost, mask: prot_mask);
4867	if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4868	scsi_host_set_guard(shost: hisi_hba->shost,
4869	type: SHOST_DIX_GUARD_CRC);
4870	}
4871
4872	if (hisi_sas_debugfs_enable)
4873	debugfs_init_v3_hw(hisi_hba);
4874
4875	rc = interrupt_preinit_v3_hw(hisi_hba);
4876	if (rc)
4877	goto err_out_undo_debugfs;
4878
4879	rc = scsi_add_host(host: shost, dev);
4880	if (rc)
4881	goto err_out_undo_debugfs;
4882
4883	rc = sas_register_ha(sha);
4884	if (rc)
4885	goto err_out_remove_host;
4886
4887	rc = hisi_sas_v3_init(hisi_hba);
4888	if (rc)
4889	goto err_out_unregister_ha;
4890
4891	scsi_scan_host(shost);
4892
4893	pm_runtime_set_autosuspend_delay(dev, delay: 5000);
4894	pm_runtime_use_autosuspend(dev);
4895	/*
4896	* For the situation that there are ATA disks connected with SAS
4897	* controller, it additionally creates ata_port which will affect the
4898	* child_count of hisi_hba->dev. Even if suspended all the disks,
4899	* ata_port is still and the child_count of hisi_hba->dev is not 0.
4900	* So use pm_suspend_ignore_children() to ignore the effect to
4901	* hisi_hba->dev.
4902	*/
4903	pm_suspend_ignore_children(dev, enable: true);
4904	pm_runtime_put_noidle(dev: &pdev->dev);
4905
4906	return 0;
4907
4908	err_out_unregister_ha:
4909	sas_unregister_ha(sha);
4910	err_out_remove_host:
4911	scsi_remove_host(shost);
4912	err_out_undo_debugfs:
4913	if (hisi_sas_debugfs_enable)
4914	debugfs_exit_v3_hw(hisi_hba);
4915	err_out_free_host:
4916	hisi_sas_free(hisi_hba);
4917	scsi_host_put(t: shost);
4918	err_out:
4919	return rc;
4920	}
4921
4922	static void
4923	hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
4924	{
4925	int i;
4926
4927	devm_free_irq(dev: &pdev->dev, irq: pci_irq_vector(dev: pdev, nr: 1), dev_id: hisi_hba);
4928	devm_free_irq(dev: &pdev->dev, irq: pci_irq_vector(dev: pdev, nr: 2), dev_id: hisi_hba);
4929	devm_free_irq(dev: &pdev->dev, irq: pci_irq_vector(dev: pdev, nr: 11), dev_id: hisi_hba);
4930	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
4931	struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4932	int nr = hisi_sas_intr_conv ? 16 : 16 + i;
4933
4934	devm_free_irq(dev: &pdev->dev, irq: pci_irq_vector(dev: pdev, nr), dev_id: cq);
4935	}
4936	}
4937
4938	static void hisi_sas_v3_remove(struct pci_dev *pdev)
4939	{
4940	struct device *dev = &pdev->dev;
4941	struct sas_ha_struct *sha = dev_get_drvdata(dev);
4942	struct hisi_hba *hisi_hba = sha->lldd_ha;
4943	struct Scsi_Host *shost = sha->shost;
4944
4945	pm_runtime_get_noresume(dev);
4946
4947	sas_unregister_ha(sha);
4948	flush_workqueue(hisi_hba->wq);
4949	sas_remove_host(shost);
4950
4951	hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
4952	hisi_sas_free(hisi_hba);
4953	if (hisi_sas_debugfs_enable)
4954	debugfs_exit_v3_hw(hisi_hba);
4955
4956	scsi_host_put(t: shost);
4957	}
4958
4959	static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
4960	{
4961	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4962	struct hisi_hba *hisi_hba = sha->lldd_ha;
4963	struct device *dev = hisi_hba->dev;
4964	int rc;
4965
4966	dev_info(dev, "FLR prepare\n");
4967	down(sem: &hisi_hba->sem);
4968	set_bit(HISI_SAS_RESETTING_BIT, addr: &hisi_hba->flags);
4969	hisi_sas_controller_reset_prepare(hisi_hba);
4970
4971	interrupt_disable_v3_hw(hisi_hba);
4972	rc = disable_host_v3_hw(hisi_hba);
4973	if (rc)
4974	dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
4975	}
4976
4977	static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
4978	{
4979	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4980	struct hisi_hba *hisi_hba = sha->lldd_ha;
4981	struct Scsi_Host *shost = hisi_hba->shost;
4982	struct device *dev = hisi_hba->dev;
4983	int rc;
4984
4985	hisi_sas_init_mem(hisi_hba);
4986
4987	rc = hw_init_v3_hw(hisi_hba);
4988	if (rc) {
4989	dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
4990	clear_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
4991	scsi_unblock_requests(shost);
4992	clear_bit(HISI_SAS_RESETTING_BIT, addr: &hisi_hba->flags);
4993	up(sem: &hisi_hba->sem);
4994	return;
4995	}
4996
4997	hisi_sas_controller_reset_done(hisi_hba);
4998	dev_info(dev, "FLR done\n");
4999	}
5000
5001	enum {
5002	/* instances of the controller */
5003	hip08,
5004	};
5005
5006	static void enable_host_v3_hw(struct hisi_hba *hisi_hba)
5007	{
5008	u32 reg_val;
5009
5010	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
5011	val: (u32)((1ULL << hisi_hba->queue_count) - 1));
5012
5013	phys_init_v3_hw(hisi_hba);
5014	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
5015	AM_CTRL_GLOBAL);
5016	reg_val &= ~AM_CTRL_SHUTDOWN_REQ_MSK;
5017	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
5018	AM_CTRL_GLOBAL, val: reg_val);
5019	}
5020
5021	static int _suspend_v3_hw(struct device *device)
5022	{
5023	struct pci_dev *pdev = to_pci_dev(device);
5024	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5025	struct hisi_hba *hisi_hba = sha->lldd_ha;
5026	struct device *dev = hisi_hba->dev;
5027	struct Scsi_Host *shost = hisi_hba->shost;
5028	int rc;
5029
5030	if (!pdev->pm_cap) {
5031	dev_err(dev, "PCI PM not supported\n");
5032	return -ENODEV;
5033	}
5034
5035	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, addr: &hisi_hba->flags))
5036	return -EPERM;
5037
5038	dev_warn(dev, "entering suspend state\n");
5039
5040	scsi_block_requests(shost);
5041	set_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
5042	flush_workqueue(hisi_hba->wq);
5043	interrupt_disable_v3_hw(hisi_hba);
5044
5045	#ifdef CONFIG_PM
5046	if (atomic_read(v: &device->power.usage_count)) {
5047	dev_err(dev, "PM suspend: host status cannot be suspended\n");
5048	rc = -EBUSY;
5049	goto err_out;
5050	}
5051	#endif
5052
5053	rc = disable_host_v3_hw(hisi_hba);
5054	if (rc) {
5055	dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
5056	goto err_out_recover_host;
5057	}
5058
5059	hisi_sas_init_mem(hisi_hba);
5060
5061	hisi_sas_release_tasks(hisi_hba);
5062
5063	sas_suspend_ha(sas_ha: sha);
5064
5065	dev_warn(dev, "end of suspending controller\n");
5066	return 0;
5067
5068	err_out_recover_host:
5069	enable_host_v3_hw(hisi_hba);
5070	#ifdef CONFIG_PM
5071	err_out:
5072	#endif
5073	interrupt_enable_v3_hw(hisi_hba);
5074	clear_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
5075	clear_bit(HISI_SAS_RESETTING_BIT, addr: &hisi_hba->flags);
5076	scsi_unblock_requests(shost);
5077	return rc;
5078	}
5079
5080	static int _resume_v3_hw(struct device *device)
5081	{
5082	struct pci_dev *pdev = to_pci_dev(device);
5083	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5084	struct hisi_hba *hisi_hba = sha->lldd_ha;
5085	struct Scsi_Host *shost = hisi_hba->shost;
5086	struct device *dev = hisi_hba->dev;
5087	unsigned int rc;
5088	pci_power_t device_state = pdev->current_state;
5089
5090	dev_warn(dev, "resuming from operating state [D%d]\n",
5091	device_state);
5092
5093	scsi_unblock_requests(shost);
5094	clear_bit(HISI_SAS_REJECT_CMD_BIT, addr: &hisi_hba->flags);
5095
5096	sas_prep_resume_ha(sas_ha: sha);
5097	rc = hw_init_v3_hw(hisi_hba);
5098	if (rc) {
5099	scsi_remove_host(shost);
5100	return rc;
5101	}
5102	phys_init_v3_hw(hisi_hba);
5103
5104	/*
5105	* If a directly-attached disk is removed during suspend, a deadlock
5106	* may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5107	* hisi_hba->device to be active, which can only happen when resume
5108	* completes. So don't wait for the HA event workqueue to drain upon
5109	* resume.
5110	*/
5111	sas_resume_ha_no_sync(sas_ha: sha);
5112	clear_bit(HISI_SAS_RESETTING_BIT, addr: &hisi_hba->flags);
5113
5114	dev_warn(dev, "end of resuming controller\n");
5115
5116	return 0;
5117	}
5118
5119	static int __maybe_unused suspend_v3_hw(struct device *device)
5120	{
5121	struct pci_dev *pdev = to_pci_dev(device);
5122	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5123	struct hisi_hba *hisi_hba = sha->lldd_ha;
5124	int rc;
5125
5126	set_bit(HISI_SAS_PM_BIT, addr: &hisi_hba->flags);
5127
5128	rc = _suspend_v3_hw(device);
5129	if (rc)
5130	clear_bit(HISI_SAS_PM_BIT, addr: &hisi_hba->flags);
5131
5132	return rc;
5133	}
5134
5135	static int __maybe_unused resume_v3_hw(struct device *device)
5136	{
5137	struct pci_dev *pdev = to_pci_dev(device);
5138	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5139	struct hisi_hba *hisi_hba = sha->lldd_ha;
5140	int rc = _resume_v3_hw(device);
5141
5142	clear_bit(HISI_SAS_PM_BIT, addr: &hisi_hba->flags);
5143
5144	return rc;
5145	}
5146
5147	static const struct pci_device_id sas_v3_pci_table[] = {
5148	{ PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5149	{}
5150	};
5151	MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5152
5153	static const struct pci_error_handlers hisi_sas_err_handler = {
5154	.reset_prepare = hisi_sas_reset_prepare_v3_hw,
5155	.reset_done = hisi_sas_reset_done_v3_hw,
5156	};
5157
5158	static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5159	suspend_v3_hw,
5160	resume_v3_hw,
5161	NULL);
5162
5163	static struct pci_driver sas_v3_pci_driver = {
5164	.name = DRV_NAME,
5165	.id_table = sas_v3_pci_table,
5166	.probe = hisi_sas_v3_probe,
5167	.remove = hisi_sas_v3_remove,
5168	.err_handler = &hisi_sas_err_handler,
5169	.driver.pm = &hisi_sas_v3_pm_ops,
5170	};
5171
5172	module_pci_driver(sas_v3_pci_driver);
5173	module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5174
5175	MODULE_LICENSE("GPL");
5176	MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5177	MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5178	MODULE_ALIAS("pci:" DRV_NAME);
5179