1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MPC52xx SPI bus driver.
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
6 *
7 * This is the driver for the MPC5200's dedicated SPI controller.
8 *
9 * Note: this driver does not support the MPC5200 PSC in SPI mode. For
10 * that driver see drivers/spi/mpc52xx_psc_spi.c
11 */
12
13#include <linux/module.h>
14#include <linux/err.h>
15#include <linux/errno.h>
16#include <linux/of_platform.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/spi/spi.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/platform_device.h>
26
27#include <asm/time.h>
28#include <asm/mpc52xx.h>
29
30MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
31MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
32MODULE_LICENSE("GPL");
33
34/* Register offsets */
35#define SPI_CTRL1 0x00
36#define SPI_CTRL1_SPIE (1 << 7)
37#define SPI_CTRL1_SPE (1 << 6)
38#define SPI_CTRL1_MSTR (1 << 4)
39#define SPI_CTRL1_CPOL (1 << 3)
40#define SPI_CTRL1_CPHA (1 << 2)
41#define SPI_CTRL1_SSOE (1 << 1)
42#define SPI_CTRL1_LSBFE (1 << 0)
43
44#define SPI_CTRL2 0x01
45#define SPI_BRR 0x04
46
47#define SPI_STATUS 0x05
48#define SPI_STATUS_SPIF (1 << 7)
49#define SPI_STATUS_WCOL (1 << 6)
50#define SPI_STATUS_MODF (1 << 4)
51
52#define SPI_DATA 0x09
53#define SPI_PORTDATA 0x0d
54#define SPI_DATADIR 0x10
55
56/* FSM state return values */
57#define FSM_STOP 0 /* Nothing more for the state machine to */
58 /* do. If something interesting happens */
59 /* then an IRQ will be received */
60#define FSM_POLL 1 /* need to poll for completion, an IRQ is */
61 /* not expected */
62#define FSM_CONTINUE 2 /* Keep iterating the state machine */
63
64/* Driver internal data */
65struct mpc52xx_spi {
66 struct spi_controller *host;
67 void __iomem *regs;
68 int irq0; /* MODF irq */
69 int irq1; /* SPIF irq */
70 unsigned int ipb_freq;
71
72 /* Statistics; not used now, but will be reintroduced for debugfs */
73 int msg_count;
74 int wcol_count;
75 int wcol_ticks;
76 u32 wcol_tx_timestamp;
77 int modf_count;
78 int byte_count;
79
80 struct list_head queue; /* queue of pending messages */
81 spinlock_t lock;
82 struct work_struct work;
83
84 /* Details of current transfer (length, and buffer pointers) */
85 struct spi_message *message; /* current message */
86 struct spi_transfer *transfer; /* current transfer */
87 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
88 int len;
89 int timestamp;
90 u8 *rx_buf;
91 const u8 *tx_buf;
92 int cs_change;
93 int gpio_cs_count;
94 struct gpio_desc **gpio_cs;
95};
96
97/*
98 * CS control function
99 */
100static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
101{
102 int cs;
103
104 if (ms->gpio_cs_count > 0) {
105 cs = spi_get_chipselect(spi: ms->message->spi, idx: 0);
106 gpiod_set_value(desc: ms->gpio_cs[cs], value);
107 } else {
108 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
109 }
110}
111
112/*
113 * Start a new transfer. This is called both by the idle state
114 * for the first transfer in a message, and by the wait state when the
115 * previous transfer in a message is complete.
116 */
117static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
118{
119 ms->rx_buf = ms->transfer->rx_buf;
120 ms->tx_buf = ms->transfer->tx_buf;
121 ms->len = ms->transfer->len;
122
123 /* Activate the chip select */
124 if (ms->cs_change)
125 mpc52xx_spi_chipsel(ms, value: 1);
126 ms->cs_change = ms->transfer->cs_change;
127
128 /* Write out the first byte */
129 ms->wcol_tx_timestamp = mftb();
130 if (ms->tx_buf)
131 out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
132 else
133 out_8(ms->regs + SPI_DATA, 0);
134}
135
136/* Forward declaration of state handlers */
137static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
138 u8 status, u8 data);
139static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
140 u8 status, u8 data);
141
142/*
143 * IDLE state
144 *
145 * No transfers are in progress; if another transfer is pending then retrieve
146 * it and kick it off. Otherwise, stop processing the state machine
147 */
148static int
149mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
150{
151 struct spi_device *spi;
152 int spr, sppr;
153 u8 ctrl1;
154
155 if (status && irq)
156 dev_err(&ms->host->dev, "spurious irq, status=0x%.2x\n",
157 status);
158
159 /* Check if there is another transfer waiting. */
160 if (list_empty(head: &ms->queue))
161 return FSM_STOP;
162
163 /* get the head of the queue */
164 ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
165 list_del_init(entry: &ms->message->queue);
166
167 /* Setup the controller parameters */
168 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
169 spi = ms->message->spi;
170 if (spi->mode & SPI_CPHA)
171 ctrl1 |= SPI_CTRL1_CPHA;
172 if (spi->mode & SPI_CPOL)
173 ctrl1 |= SPI_CTRL1_CPOL;
174 if (spi->mode & SPI_LSB_FIRST)
175 ctrl1 |= SPI_CTRL1_LSBFE;
176 out_8(ms->regs + SPI_CTRL1, ctrl1);
177
178 /* Setup the controller speed */
179 /* minimum divider is '2'. Also, add '1' to force rounding the
180 * divider up. */
181 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
182 spr = 0;
183 if (sppr < 1)
184 sppr = 1;
185 while (((sppr - 1) & ~0x7) != 0) {
186 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
187 spr++;
188 }
189 sppr--; /* sppr quantity in register is offset by 1 */
190 if (spr > 7) {
191 /* Don't overrun limits of SPI baudrate register */
192 spr = 7;
193 sppr = 7;
194 }
195 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
196
197 ms->cs_change = 1;
198 ms->transfer = container_of(ms->message->transfers.next,
199 struct spi_transfer, transfer_list);
200
201 mpc52xx_spi_start_transfer(ms);
202 ms->state = mpc52xx_spi_fsmstate_transfer;
203
204 return FSM_CONTINUE;
205}
206
207/*
208 * TRANSFER state
209 *
210 * In the middle of a transfer. If the SPI core has completed processing
211 * a byte, then read out the received data and write out the next byte
212 * (unless this transfer is finished; in which case go on to the wait
213 * state)
214 */
215static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
216 u8 status, u8 data)
217{
218 if (!status)
219 return ms->irq0 ? FSM_STOP : FSM_POLL;
220
221 if (status & SPI_STATUS_WCOL) {
222 /* The SPI controller is stoopid. At slower speeds, it may
223 * raise the SPIF flag before the state machine is actually
224 * finished, which causes a collision (internal to the state
225 * machine only). The manual recommends inserting a delay
226 * between receiving the interrupt and sending the next byte,
227 * but it can also be worked around simply by retrying the
228 * transfer which is what we do here. */
229 ms->wcol_count++;
230 ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
231 ms->wcol_tx_timestamp = mftb();
232 data = 0;
233 if (ms->tx_buf)
234 data = *(ms->tx_buf - 1);
235 out_8(ms->regs + SPI_DATA, data); /* try again */
236 return FSM_CONTINUE;
237 } else if (status & SPI_STATUS_MODF) {
238 ms->modf_count++;
239 dev_err(&ms->host->dev, "mode fault\n");
240 mpc52xx_spi_chipsel(ms, value: 0);
241 ms->message->status = -EIO;
242 if (ms->message->complete)
243 ms->message->complete(ms->message->context);
244 ms->state = mpc52xx_spi_fsmstate_idle;
245 return FSM_CONTINUE;
246 }
247
248 /* Read data out of the spi device */
249 ms->byte_count++;
250 if (ms->rx_buf)
251 *ms->rx_buf++ = data;
252
253 /* Is the transfer complete? */
254 ms->len--;
255 if (ms->len == 0) {
256 ms->timestamp = mftb();
257 if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
258 ms->timestamp += ms->transfer->delay.value *
259 tb_ticks_per_usec;
260 ms->state = mpc52xx_spi_fsmstate_wait;
261 return FSM_CONTINUE;
262 }
263
264 /* Write out the next byte */
265 ms->wcol_tx_timestamp = mftb();
266 if (ms->tx_buf)
267 out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
268 else
269 out_8(ms->regs + SPI_DATA, 0);
270
271 return FSM_CONTINUE;
272}
273
274/*
275 * WAIT state
276 *
277 * A transfer has completed; need to wait for the delay period to complete
278 * before starting the next transfer
279 */
280static int
281mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
282{
283 if (status && irq)
284 dev_err(&ms->host->dev, "spurious irq, status=0x%.2x\n",
285 status);
286
287 if (((int)mftb()) - ms->timestamp < 0)
288 return FSM_POLL;
289
290 ms->message->actual_length += ms->transfer->len;
291
292 /* Check if there is another transfer in this message. If there
293 * aren't then deactivate CS, notify sender, and drop back to idle
294 * to start the next message. */
295 if (ms->transfer->transfer_list.next == &ms->message->transfers) {
296 ms->msg_count++;
297 mpc52xx_spi_chipsel(ms, value: 0);
298 ms->message->status = 0;
299 if (ms->message->complete)
300 ms->message->complete(ms->message->context);
301 ms->state = mpc52xx_spi_fsmstate_idle;
302 return FSM_CONTINUE;
303 }
304
305 /* There is another transfer; kick it off */
306
307 if (ms->cs_change)
308 mpc52xx_spi_chipsel(ms, value: 0);
309
310 ms->transfer = container_of(ms->transfer->transfer_list.next,
311 struct spi_transfer, transfer_list);
312 mpc52xx_spi_start_transfer(ms);
313 ms->state = mpc52xx_spi_fsmstate_transfer;
314 return FSM_CONTINUE;
315}
316
317/**
318 * mpc52xx_spi_fsm_process - Finite State Machine iteration function
319 * @irq: irq number that triggered the FSM or 0 for polling
320 * @ms: pointer to mpc52xx_spi driver data
321 */
322static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
323{
324 int rc = FSM_CONTINUE;
325 u8 status, data;
326
327 while (rc == FSM_CONTINUE) {
328 /* Interrupt cleared by read of STATUS followed by
329 * read of DATA registers */
330 status = in_8(ms->regs + SPI_STATUS);
331 data = in_8(ms->regs + SPI_DATA);
332 rc = ms->state(irq, ms, status, data);
333 }
334
335 if (rc == FSM_POLL)
336 schedule_work(work: &ms->work);
337}
338
339/**
340 * mpc52xx_spi_irq - IRQ handler
341 */
342static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
343{
344 struct mpc52xx_spi *ms = _ms;
345 spin_lock(lock: &ms->lock);
346 mpc52xx_spi_fsm_process(irq, ms);
347 spin_unlock(lock: &ms->lock);
348 return IRQ_HANDLED;
349}
350
351/**
352 * mpc52xx_spi_wq - Workqueue function for polling the state machine
353 */
354static void mpc52xx_spi_wq(struct work_struct *work)
355{
356 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
357 unsigned long flags;
358
359 spin_lock_irqsave(&ms->lock, flags);
360 mpc52xx_spi_fsm_process(irq: 0, ms);
361 spin_unlock_irqrestore(lock: &ms->lock, flags);
362}
363
364/*
365 * spi_controller ops
366 */
367
368static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
369{
370 struct mpc52xx_spi *ms = spi_controller_get_devdata(ctlr: spi->controller);
371 unsigned long flags;
372
373 m->actual_length = 0;
374 m->status = -EINPROGRESS;
375
376 spin_lock_irqsave(&ms->lock, flags);
377 list_add_tail(new: &m->queue, head: &ms->queue);
378 spin_unlock_irqrestore(lock: &ms->lock, flags);
379 schedule_work(work: &ms->work);
380
381 return 0;
382}
383
384/*
385 * OF Platform Bus Binding
386 */
387static int mpc52xx_spi_probe(struct platform_device *op)
388{
389 struct spi_controller *host;
390 struct mpc52xx_spi *ms;
391 struct gpio_desc *gpio_cs;
392 void __iomem *regs;
393 u8 ctrl1;
394 int rc, i = 0;
395
396 /* MMIO registers */
397 dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
398 regs = of_iomap(node: op->dev.of_node, index: 0);
399 if (!regs)
400 return -ENODEV;
401
402 /* initialize the device */
403 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
404 out_8(regs + SPI_CTRL1, ctrl1);
405 out_8(regs + SPI_CTRL2, 0x0);
406 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
407 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
408
409 /* Clear the status register and re-read it to check for a MODF
410 * failure. This driver cannot currently handle multiple hosts
411 * on the SPI bus. This fault will also occur if the SPI signals
412 * are not connected to any pins (port_config setting) */
413 in_8(regs + SPI_STATUS);
414 out_8(regs + SPI_CTRL1, ctrl1);
415
416 in_8(regs + SPI_DATA);
417 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
418 dev_err(&op->dev, "mode fault; is port_config correct?\n");
419 rc = -EIO;
420 goto err_init;
421 }
422
423 dev_dbg(&op->dev, "allocating spi_controller struct\n");
424 host = spi_alloc_host(dev: &op->dev, size: sizeof(*ms));
425 if (!host) {
426 rc = -ENOMEM;
427 goto err_alloc;
428 }
429
430 host->transfer = mpc52xx_spi_transfer;
431 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
432 host->bits_per_word_mask = SPI_BPW_MASK(8);
433 host->dev.of_node = op->dev.of_node;
434
435 platform_set_drvdata(pdev: op, data: host);
436
437 ms = spi_controller_get_devdata(ctlr: host);
438 ms->host = host;
439 ms->regs = regs;
440 ms->irq0 = irq_of_parse_and_map(node: op->dev.of_node, index: 0);
441 ms->irq1 = irq_of_parse_and_map(node: op->dev.of_node, index: 1);
442 ms->state = mpc52xx_spi_fsmstate_idle;
443 ms->ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
444 ms->gpio_cs_count = gpiod_count(dev: &op->dev, NULL);
445 if (ms->gpio_cs_count > 0) {
446 host->num_chipselect = ms->gpio_cs_count;
447 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
448 sizeof(*ms->gpio_cs),
449 GFP_KERNEL);
450 if (!ms->gpio_cs) {
451 rc = -ENOMEM;
452 goto err_alloc_gpio;
453 }
454
455 for (i = 0; i < ms->gpio_cs_count; i++) {
456 gpio_cs = gpiod_get_index(dev: &op->dev,
457 NULL, idx: i, flags: GPIOD_OUT_LOW);
458 rc = PTR_ERR_OR_ZERO(ptr: gpio_cs);
459 if (rc) {
460 dev_err(&op->dev,
461 "failed to get spi cs gpio #%d: %d\n",
462 i, rc);
463 goto err_gpio;
464 }
465
466 ms->gpio_cs[i] = gpio_cs;
467 }
468 }
469
470 spin_lock_init(&ms->lock);
471 INIT_LIST_HEAD(list: &ms->queue);
472 INIT_WORK(&ms->work, mpc52xx_spi_wq);
473
474 /* Decide if interrupts can be used */
475 if (ms->irq0 && ms->irq1) {
476 rc = request_irq(irq: ms->irq0, handler: mpc52xx_spi_irq, flags: 0,
477 name: "mpc5200-spi-modf", dev: ms);
478 rc |= request_irq(irq: ms->irq1, handler: mpc52xx_spi_irq, flags: 0,
479 name: "mpc5200-spi-spif", dev: ms);
480 if (rc) {
481 free_irq(ms->irq0, ms);
482 free_irq(ms->irq1, ms);
483 ms->irq0 = ms->irq1 = 0;
484 }
485 } else {
486 /* operate in polled mode */
487 ms->irq0 = ms->irq1 = 0;
488 }
489
490 if (!ms->irq0)
491 dev_info(&op->dev, "using polled mode\n");
492
493 dev_dbg(&op->dev, "registering spi_controller struct\n");
494 rc = spi_register_controller(ctlr: host);
495 if (rc)
496 goto err_register;
497
498 dev_info(&ms->host->dev, "registered MPC5200 SPI bus\n");
499
500 return rc;
501
502 err_register:
503 dev_err(&ms->host->dev, "initialization failed\n");
504 err_gpio:
505 while (i-- > 0)
506 gpiod_put(desc: ms->gpio_cs[i]);
507
508 kfree(objp: ms->gpio_cs);
509 err_alloc_gpio:
510 spi_controller_put(ctlr: host);
511 err_alloc:
512 err_init:
513 iounmap(addr: regs);
514 return rc;
515}
516
517static void mpc52xx_spi_remove(struct platform_device *op)
518{
519 struct spi_controller *host = spi_controller_get(ctlr: platform_get_drvdata(pdev: op));
520 struct mpc52xx_spi *ms = spi_controller_get_devdata(ctlr: host);
521 int i;
522
523 cancel_work_sync(work: &ms->work);
524 free_irq(ms->irq0, ms);
525 free_irq(ms->irq1, ms);
526
527 for (i = 0; i < ms->gpio_cs_count; i++)
528 gpiod_put(desc: ms->gpio_cs[i]);
529
530 kfree(objp: ms->gpio_cs);
531 spi_unregister_controller(ctlr: host);
532 iounmap(addr: ms->regs);
533 spi_controller_put(ctlr: host);
534}
535
536static const struct of_device_id mpc52xx_spi_match[] = {
537 { .compatible = "fsl,mpc5200-spi", },
538 {}
539};
540MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
541
542static struct platform_driver mpc52xx_spi_of_driver = {
543 .driver = {
544 .name = "mpc52xx-spi",
545 .of_match_table = mpc52xx_spi_match,
546 },
547 .probe = mpc52xx_spi_probe,
548 .remove = mpc52xx_spi_remove,
549};
550module_platform_driver(mpc52xx_spi_of_driver);
551

source code of linux/drivers/spi/spi-mpc52xx.c