1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // |
3 | // Driver for the SPI-NAND mode of Mediatek NAND Flash Interface |
4 | // |
5 | // Copyright (c) 2022 Chuanhong Guo <gch981213@gmail.com> |
6 | // |
7 | // This driver is based on the SPI-NAND mtd driver from Mediatek SDK: |
8 | // |
9 | // Copyright (C) 2020 MediaTek Inc. |
10 | // Author: Weijie Gao <weijie.gao@mediatek.com> |
11 | // |
12 | // This controller organize the page data as several interleaved sectors |
13 | // like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) |
14 | // +---------+------+------+---------+------+------+-----+ |
15 | // | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | |
16 | // +---------+------+------+---------+------+------+-----+ |
17 | // With auto-format turned on, DMA only returns this part: |
18 | // +---------+---------+-----+ |
19 | // | Sector1 | Sector2 | ... | |
20 | // +---------+---------+-----+ |
21 | // The FDM data will be filled to the registers, and ECC parity data isn't |
22 | // accessible. |
23 | // With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA |
24 | // in it's original order shown in the first table. ECC can't be turned on when |
25 | // auto-format is off. |
26 | // |
27 | // However, Linux SPI-NAND driver expects the data returned as: |
28 | // +------+-----+ |
29 | // | Page | OOB | |
30 | // +------+-----+ |
31 | // where the page data is continuously stored instead of interleaved. |
32 | // So we assume all instructions matching the page_op template between ECC |
33 | // prepare_io_req and finish_io_req are for page cache r/w. |
34 | // Here's how this spi-mem driver operates when reading: |
35 | // 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). |
36 | // 2. Perform page ops and let the controller fill the DMA bounce buffer with |
37 | // de-interleaved sector data and set FDM registers. |
38 | // 3. Return the data as: |
39 | // +---------+---------+-----+------+------+-----+ |
40 | // | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | |
41 | // +---------+---------+-----+------+------+-----+ |
42 | // 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, |
43 | // read the data with auto-format off into the bounce buffer and copy |
44 | // needed data to the buffer specified in the request. |
45 | // |
46 | // Write requests operates in a similar manner. |
47 | // As a limitation of this strategy, we won't be able to access any ECC parity |
48 | // data at all in Linux. |
49 | // |
50 | // Here's the bad block mark situation on MTK chips: |
51 | // In older chips like mt7622, MTK uses the first FDM byte in the first sector |
52 | // as the bad block mark. After de-interleaving, this byte appears at [pagesize] |
53 | // in the returned data, which is the BBM position expected by kernel. However, |
54 | // the conventional bad block mark is the first byte of the OOB, which is part |
55 | // of the last sector data in the interleaved layout. Instead of fixing their |
56 | // hardware, MTK decided to address this inconsistency in software. On these |
57 | // later chips, the BootROM expects the following: |
58 | // 1. The [pagesize] byte on a nand page is used as BBM, which will appear at |
59 | // (page_size - (nsectors - 1) * spare_size) in the DMA buffer. |
60 | // 2. The original byte stored at that position in the DMA buffer will be stored |
61 | // as the first byte of the FDM section in the last sector. |
62 | // We can't disagree with the BootROM, so after de-interleaving, we need to |
63 | // perform the following swaps in read: |
64 | // 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], |
65 | // which is the expected BBM position by kernel. |
66 | // 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to |
67 | // [page_size - (nsectors - 1) * spare_size] |
68 | // Similarly, when writing, we need to perform swaps in the other direction. |
69 | |
70 | #include <linux/kernel.h> |
71 | #include <linux/module.h> |
72 | #include <linux/init.h> |
73 | #include <linux/device.h> |
74 | #include <linux/mutex.h> |
75 | #include <linux/clk.h> |
76 | #include <linux/interrupt.h> |
77 | #include <linux/dma-mapping.h> |
78 | #include <linux/iopoll.h> |
79 | #include <linux/of.h> |
80 | #include <linux/platform_device.h> |
81 | #include <linux/mtd/nand-ecc-mtk.h> |
82 | #include <linux/spi/spi.h> |
83 | #include <linux/spi/spi-mem.h> |
84 | #include <linux/mtd/nand.h> |
85 | |
86 | // NFI registers |
87 | #define NFI_CNFG 0x000 |
88 | #define CNFG_OP_MODE_S 12 |
89 | #define CNFG_OP_MODE_CUST 6 |
90 | #define CNFG_OP_MODE_PROGRAM 3 |
91 | #define CNFG_AUTO_FMT_EN BIT(9) |
92 | #define CNFG_HW_ECC_EN BIT(8) |
93 | #define CNFG_DMA_BURST_EN BIT(2) |
94 | #define CNFG_READ_MODE BIT(1) |
95 | #define CNFG_DMA_MODE BIT(0) |
96 | |
97 | #define NFI_PAGEFMT 0x0004 |
98 | #define NFI_SPARE_SIZE_LS_S 16 |
99 | #define NFI_FDM_ECC_NUM_S 12 |
100 | #define NFI_FDM_NUM_S 8 |
101 | #define NFI_SPARE_SIZE_S 4 |
102 | #define NFI_SEC_SEL_512 BIT(2) |
103 | #define NFI_PAGE_SIZE_S 0 |
104 | #define NFI_PAGE_SIZE_512_2K 0 |
105 | #define NFI_PAGE_SIZE_2K_4K 1 |
106 | #define NFI_PAGE_SIZE_4K_8K 2 |
107 | #define NFI_PAGE_SIZE_8K_16K 3 |
108 | |
109 | #define NFI_CON 0x008 |
110 | #define CON_SEC_NUM_S 12 |
111 | #define CON_BWR BIT(9) |
112 | #define CON_BRD BIT(8) |
113 | #define CON_NFI_RST BIT(1) |
114 | #define CON_FIFO_FLUSH BIT(0) |
115 | |
116 | #define NFI_INTR_EN 0x010 |
117 | #define NFI_INTR_STA 0x014 |
118 | #define NFI_IRQ_INTR_EN BIT(31) |
119 | #define NFI_IRQ_CUS_READ BIT(8) |
120 | #define NFI_IRQ_CUS_PG BIT(7) |
121 | |
122 | #define NFI_CMD 0x020 |
123 | #define NFI_CMD_DUMMY_READ 0x00 |
124 | #define NFI_CMD_DUMMY_WRITE 0x80 |
125 | |
126 | #define NFI_STRDATA 0x040 |
127 | #define STR_DATA BIT(0) |
128 | |
129 | #define NFI_STA 0x060 |
130 | #define NFI_NAND_FSM_7622 GENMASK(28, 24) |
131 | #define NFI_NAND_FSM_7986 GENMASK(29, 23) |
132 | #define NFI_FSM GENMASK(19, 16) |
133 | #define READ_EMPTY BIT(12) |
134 | |
135 | #define NFI_FIFOSTA 0x064 |
136 | #define FIFO_WR_REMAIN_S 8 |
137 | #define FIFO_RD_REMAIN_S 0 |
138 | |
139 | #define NFI_ADDRCNTR 0x070 |
140 | #define SEC_CNTR GENMASK(16, 12) |
141 | #define SEC_CNTR_S 12 |
142 | #define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) |
143 | |
144 | #define NFI_STRADDR 0x080 |
145 | |
146 | #define NFI_BYTELEN 0x084 |
147 | #define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) |
148 | |
149 | #define NFI_FDM0L 0x0a0 |
150 | #define NFI_FDM0M 0x0a4 |
151 | #define NFI_FDML(n) (NFI_FDM0L + (n)*8) |
152 | #define NFI_FDMM(n) (NFI_FDM0M + (n)*8) |
153 | |
154 | #define NFI_DEBUG_CON1 0x220 |
155 | #define WBUF_EN BIT(2) |
156 | |
157 | #define NFI_MASTERSTA 0x224 |
158 | #define MAS_ADDR GENMASK(11, 9) |
159 | #define MAS_RD GENMASK(8, 6) |
160 | #define MAS_WR GENMASK(5, 3) |
161 | #define MAS_RDDLY GENMASK(2, 0) |
162 | #define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) |
163 | #define NFI_MASTERSTA_MASK_7986 3 |
164 | |
165 | // SNFI registers |
166 | #define SNF_MAC_CTL 0x500 |
167 | #define MAC_XIO_SEL BIT(4) |
168 | #define SF_MAC_EN BIT(3) |
169 | #define SF_TRIG BIT(2) |
170 | #define WIP_READY BIT(1) |
171 | #define WIP BIT(0) |
172 | |
173 | #define SNF_MAC_OUTL 0x504 |
174 | #define SNF_MAC_INL 0x508 |
175 | |
176 | #define SNF_RD_CTL2 0x510 |
177 | #define DATA_READ_DUMMY_S 8 |
178 | #define DATA_READ_MAX_DUMMY 0xf |
179 | #define DATA_READ_CMD_S 0 |
180 | |
181 | #define SNF_RD_CTL3 0x514 |
182 | |
183 | #define SNF_PG_CTL1 0x524 |
184 | #define PG_LOAD_CMD_S 8 |
185 | |
186 | #define SNF_PG_CTL2 0x528 |
187 | |
188 | #define SNF_MISC_CTL 0x538 |
189 | #define SW_RST BIT(28) |
190 | #define FIFO_RD_LTC_S 25 |
191 | #define PG_LOAD_X4_EN BIT(20) |
192 | #define DATA_READ_MODE_S 16 |
193 | #define DATA_READ_MODE GENMASK(18, 16) |
194 | #define DATA_READ_MODE_X1 0 |
195 | #define DATA_READ_MODE_X2 1 |
196 | #define DATA_READ_MODE_X4 2 |
197 | #define DATA_READ_MODE_DUAL 5 |
198 | #define DATA_READ_MODE_QUAD 6 |
199 | #define DATA_READ_LATCH_LAT GENMASK(9, 8) |
200 | #define DATA_READ_LATCH_LAT_S 8 |
201 | #define PG_LOAD_CUSTOM_EN BIT(7) |
202 | #define DATARD_CUSTOM_EN BIT(6) |
203 | #define CS_DESELECT_CYC_S 0 |
204 | |
205 | #define SNF_MISC_CTL2 0x53c |
206 | #define PROGRAM_LOAD_BYTE_NUM_S 16 |
207 | #define READ_DATA_BYTE_NUM_S 11 |
208 | |
209 | #define SNF_DLY_CTL3 0x548 |
210 | #define SFCK_SAM_DLY_S 0 |
211 | #define SFCK_SAM_DLY GENMASK(5, 0) |
212 | #define SFCK_SAM_DLY_TOTAL 9 |
213 | #define SFCK_SAM_DLY_RANGE 47 |
214 | |
215 | #define SNF_STA_CTL1 0x550 |
216 | #define CUS_PG_DONE BIT(28) |
217 | #define CUS_READ_DONE BIT(27) |
218 | #define SPI_STATE_S 0 |
219 | #define SPI_STATE GENMASK(3, 0) |
220 | |
221 | #define SNF_CFG 0x55c |
222 | #define SPI_MODE BIT(0) |
223 | |
224 | #define SNF_GPRAM 0x800 |
225 | #define SNF_GPRAM_SIZE 0xa0 |
226 | |
227 | #define SNFI_POLL_INTERVAL 1000000 |
228 | |
229 | static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; |
230 | |
231 | static const u8 mt7986_spare_sizes[] = { |
232 | 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, |
233 | 74 |
234 | }; |
235 | |
236 | struct mtk_snand_caps { |
237 | u16 sector_size; |
238 | u16 max_sectors; |
239 | u16 fdm_size; |
240 | u16 fdm_ecc_size; |
241 | u16 fifo_size; |
242 | |
243 | bool bbm_swap; |
244 | bool empty_page_check; |
245 | u32 mastersta_mask; |
246 | u32 nandfsm_mask; |
247 | |
248 | const u8 *spare_sizes; |
249 | u32 num_spare_size; |
250 | }; |
251 | |
252 | static const struct mtk_snand_caps mt7622_snand_caps = { |
253 | .sector_size = 512, |
254 | .max_sectors = 8, |
255 | .fdm_size = 8, |
256 | .fdm_ecc_size = 1, |
257 | .fifo_size = 32, |
258 | .bbm_swap = false, |
259 | .empty_page_check = false, |
260 | .mastersta_mask = NFI_MASTERSTA_MASK_7622, |
261 | .nandfsm_mask = NFI_NAND_FSM_7622, |
262 | .spare_sizes = mt7622_spare_sizes, |
263 | .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) |
264 | }; |
265 | |
266 | static const struct mtk_snand_caps mt7629_snand_caps = { |
267 | .sector_size = 512, |
268 | .max_sectors = 8, |
269 | .fdm_size = 8, |
270 | .fdm_ecc_size = 1, |
271 | .fifo_size = 32, |
272 | .bbm_swap = true, |
273 | .empty_page_check = false, |
274 | .mastersta_mask = NFI_MASTERSTA_MASK_7622, |
275 | .nandfsm_mask = NFI_NAND_FSM_7622, |
276 | .spare_sizes = mt7622_spare_sizes, |
277 | .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) |
278 | }; |
279 | |
280 | static const struct mtk_snand_caps mt7986_snand_caps = { |
281 | .sector_size = 1024, |
282 | .max_sectors = 8, |
283 | .fdm_size = 8, |
284 | .fdm_ecc_size = 1, |
285 | .fifo_size = 64, |
286 | .bbm_swap = true, |
287 | .empty_page_check = true, |
288 | .mastersta_mask = NFI_MASTERSTA_MASK_7986, |
289 | .nandfsm_mask = NFI_NAND_FSM_7986, |
290 | .spare_sizes = mt7986_spare_sizes, |
291 | .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes) |
292 | }; |
293 | |
294 | struct mtk_snand_conf { |
295 | size_t page_size; |
296 | size_t oob_size; |
297 | u8 nsectors; |
298 | u8 spare_size; |
299 | }; |
300 | |
301 | struct mtk_snand { |
302 | struct spi_controller *ctlr; |
303 | struct device *dev; |
304 | struct clk *nfi_clk; |
305 | struct clk *pad_clk; |
306 | struct clk *nfi_hclk; |
307 | void __iomem *nfi_base; |
308 | int irq; |
309 | struct completion op_done; |
310 | const struct mtk_snand_caps *caps; |
311 | struct mtk_ecc_config *ecc_cfg; |
312 | struct mtk_ecc *ecc; |
313 | struct mtk_snand_conf nfi_cfg; |
314 | struct mtk_ecc_stats ecc_stats; |
315 | struct nand_ecc_engine ecc_eng; |
316 | bool autofmt; |
317 | u8 *buf; |
318 | size_t buf_len; |
319 | }; |
320 | |
321 | static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) |
322 | { |
323 | struct nand_ecc_engine *eng = nand->ecc.engine; |
324 | |
325 | return container_of(eng, struct mtk_snand, ecc_eng); |
326 | } |
327 | |
328 | static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) |
329 | { |
330 | if (snf->buf_len >= size) |
331 | return 0; |
332 | kfree(objp: snf->buf); |
333 | snf->buf = kmalloc(size, GFP_KERNEL); |
334 | if (!snf->buf) |
335 | return -ENOMEM; |
336 | snf->buf_len = size; |
337 | memset(snf->buf, 0xff, snf->buf_len); |
338 | return 0; |
339 | } |
340 | |
341 | static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) |
342 | { |
343 | return readl(addr: snf->nfi_base + reg); |
344 | } |
345 | |
346 | static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) |
347 | { |
348 | writel(val, addr: snf->nfi_base + reg); |
349 | } |
350 | |
351 | static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) |
352 | { |
353 | writew(val, addr: snf->nfi_base + reg); |
354 | } |
355 | |
356 | static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) |
357 | { |
358 | u32 val; |
359 | |
360 | val = readl(addr: snf->nfi_base + reg); |
361 | val &= ~clr; |
362 | val |= set; |
363 | writel(val, addr: snf->nfi_base + reg); |
364 | } |
365 | |
366 | static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) |
367 | { |
368 | u32 i, val = 0, es = sizeof(u32); |
369 | |
370 | for (i = reg; i < reg + len; i++) { |
371 | if (i == reg || i % es == 0) |
372 | val = nfi_read32(snf, reg: i & ~(es - 1)); |
373 | |
374 | *data++ = (u8)(val >> (8 * (i % es))); |
375 | } |
376 | } |
377 | |
378 | static int mtk_nfi_reset(struct mtk_snand *snf) |
379 | { |
380 | u32 val, fifo_mask; |
381 | int ret; |
382 | |
383 | nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); |
384 | |
385 | ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, |
386 | !(val & snf->caps->mastersta_mask), 0, |
387 | SNFI_POLL_INTERVAL); |
388 | if (ret) { |
389 | dev_err(snf->dev, "NFI master is still busy after reset\n" ); |
390 | return ret; |
391 | } |
392 | |
393 | ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, |
394 | !(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0, |
395 | SNFI_POLL_INTERVAL); |
396 | if (ret) { |
397 | dev_err(snf->dev, "Failed to reset NFI\n" ); |
398 | return ret; |
399 | } |
400 | |
401 | fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | |
402 | ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); |
403 | ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, |
404 | !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); |
405 | if (ret) { |
406 | dev_err(snf->dev, "NFI FIFOs are not empty\n" ); |
407 | return ret; |
408 | } |
409 | |
410 | return 0; |
411 | } |
412 | |
413 | static int mtk_snand_mac_reset(struct mtk_snand *snf) |
414 | { |
415 | int ret; |
416 | u32 val; |
417 | |
418 | nfi_rmw32(snf, SNF_MISC_CTL, clr: 0, SW_RST); |
419 | |
420 | ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, |
421 | !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); |
422 | if (ret) |
423 | dev_err(snf->dev, "Failed to reset SNFI MAC\n" ); |
424 | |
425 | nfi_write32(snf, SNF_MISC_CTL, |
426 | val: (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); |
427 | |
428 | return ret; |
429 | } |
430 | |
431 | static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) |
432 | { |
433 | int ret; |
434 | u32 val; |
435 | |
436 | nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); |
437 | nfi_write32(snf, SNF_MAC_OUTL, val: outlen); |
438 | nfi_write32(snf, SNF_MAC_INL, val: inlen); |
439 | |
440 | nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); |
441 | |
442 | ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, |
443 | val & WIP_READY, 0, SNFI_POLL_INTERVAL); |
444 | if (ret) { |
445 | dev_err(snf->dev, "Timed out waiting for WIP_READY\n" ); |
446 | goto cleanup; |
447 | } |
448 | |
449 | ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), |
450 | 0, SNFI_POLL_INTERVAL); |
451 | if (ret) |
452 | dev_err(snf->dev, "Timed out waiting for WIP cleared\n" ); |
453 | |
454 | cleanup: |
455 | nfi_write32(snf, SNF_MAC_CTL, val: 0); |
456 | |
457 | return ret; |
458 | } |
459 | |
460 | static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) |
461 | { |
462 | u32 rx_len = 0; |
463 | u32 reg_offs = 0; |
464 | u32 val = 0; |
465 | const u8 *tx_buf = NULL; |
466 | u8 *rx_buf = NULL; |
467 | int i, ret; |
468 | u8 b; |
469 | |
470 | if (op->data.dir == SPI_MEM_DATA_IN) { |
471 | rx_len = op->data.nbytes; |
472 | rx_buf = op->data.buf.in; |
473 | } else { |
474 | tx_buf = op->data.buf.out; |
475 | } |
476 | |
477 | mtk_snand_mac_reset(snf); |
478 | |
479 | for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { |
480 | b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; |
481 | val |= b << (8 * (reg_offs % 4)); |
482 | if (reg_offs % 4 == 3) { |
483 | nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); |
484 | val = 0; |
485 | } |
486 | } |
487 | |
488 | for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { |
489 | b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; |
490 | val |= b << (8 * (reg_offs % 4)); |
491 | if (reg_offs % 4 == 3) { |
492 | nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); |
493 | val = 0; |
494 | } |
495 | } |
496 | |
497 | for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { |
498 | if (reg_offs % 4 == 3) { |
499 | nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); |
500 | val = 0; |
501 | } |
502 | } |
503 | |
504 | if (op->data.dir == SPI_MEM_DATA_OUT) { |
505 | for (i = 0; i < op->data.nbytes; i++, reg_offs++) { |
506 | val |= tx_buf[i] << (8 * (reg_offs % 4)); |
507 | if (reg_offs % 4 == 3) { |
508 | nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); |
509 | val = 0; |
510 | } |
511 | } |
512 | } |
513 | |
514 | if (reg_offs % 4) |
515 | nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); |
516 | |
517 | for (i = 0; i < reg_offs; i += 4) |
518 | dev_dbg(snf->dev, "%d: %08X" , i, |
519 | nfi_read32(snf, SNF_GPRAM + i)); |
520 | |
521 | dev_dbg(snf->dev, "SNF TX: %u RX: %u" , reg_offs, rx_len); |
522 | |
523 | ret = mtk_snand_mac_trigger(snf, outlen: reg_offs, inlen: rx_len); |
524 | if (ret) |
525 | return ret; |
526 | |
527 | if (!rx_len) |
528 | return 0; |
529 | |
530 | nfi_read_data(snf, SNF_GPRAM + reg_offs, data: rx_buf, len: rx_len); |
531 | return 0; |
532 | } |
533 | |
534 | static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, |
535 | u32 oob_size) |
536 | { |
537 | int spare_idx = -1; |
538 | u32 spare_size, spare_size_shift, pagesize_idx; |
539 | u32 sector_size_512; |
540 | u8 nsectors; |
541 | int i; |
542 | |
543 | // skip if it's already configured as required. |
544 | if (snf->nfi_cfg.page_size == page_size && |
545 | snf->nfi_cfg.oob_size == oob_size) |
546 | return 0; |
547 | |
548 | nsectors = page_size / snf->caps->sector_size; |
549 | if (nsectors > snf->caps->max_sectors) { |
550 | dev_err(snf->dev, "too many sectors required.\n" ); |
551 | goto err; |
552 | } |
553 | |
554 | if (snf->caps->sector_size == 512) { |
555 | sector_size_512 = NFI_SEC_SEL_512; |
556 | spare_size_shift = NFI_SPARE_SIZE_S; |
557 | } else { |
558 | sector_size_512 = 0; |
559 | spare_size_shift = NFI_SPARE_SIZE_LS_S; |
560 | } |
561 | |
562 | switch (page_size) { |
563 | case SZ_512: |
564 | pagesize_idx = NFI_PAGE_SIZE_512_2K; |
565 | break; |
566 | case SZ_2K: |
567 | if (snf->caps->sector_size == 512) |
568 | pagesize_idx = NFI_PAGE_SIZE_2K_4K; |
569 | else |
570 | pagesize_idx = NFI_PAGE_SIZE_512_2K; |
571 | break; |
572 | case SZ_4K: |
573 | if (snf->caps->sector_size == 512) |
574 | pagesize_idx = NFI_PAGE_SIZE_4K_8K; |
575 | else |
576 | pagesize_idx = NFI_PAGE_SIZE_2K_4K; |
577 | break; |
578 | case SZ_8K: |
579 | if (snf->caps->sector_size == 512) |
580 | pagesize_idx = NFI_PAGE_SIZE_8K_16K; |
581 | else |
582 | pagesize_idx = NFI_PAGE_SIZE_4K_8K; |
583 | break; |
584 | case SZ_16K: |
585 | pagesize_idx = NFI_PAGE_SIZE_8K_16K; |
586 | break; |
587 | default: |
588 | dev_err(snf->dev, "unsupported page size.\n" ); |
589 | goto err; |
590 | } |
591 | |
592 | spare_size = oob_size / nsectors; |
593 | // If we're using the 1KB sector size, HW will automatically double the |
594 | // spare size. We should only use half of the value in this case. |
595 | if (snf->caps->sector_size == 1024) |
596 | spare_size /= 2; |
597 | |
598 | for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { |
599 | if (snf->caps->spare_sizes[i] <= spare_size) { |
600 | spare_size = snf->caps->spare_sizes[i]; |
601 | if (snf->caps->sector_size == 1024) |
602 | spare_size *= 2; |
603 | spare_idx = i; |
604 | break; |
605 | } |
606 | } |
607 | |
608 | if (spare_idx < 0) { |
609 | dev_err(snf->dev, "unsupported spare size: %u\n" , spare_size); |
610 | goto err; |
611 | } |
612 | |
613 | nfi_write32(snf, NFI_PAGEFMT, |
614 | val: (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | |
615 | (snf->caps->fdm_size << NFI_FDM_NUM_S) | |
616 | (spare_idx << spare_size_shift) | |
617 | (pagesize_idx << NFI_PAGE_SIZE_S) | |
618 | sector_size_512); |
619 | |
620 | snf->nfi_cfg.page_size = page_size; |
621 | snf->nfi_cfg.oob_size = oob_size; |
622 | snf->nfi_cfg.nsectors = nsectors; |
623 | snf->nfi_cfg.spare_size = spare_size; |
624 | |
625 | dev_dbg(snf->dev, "page format: (%u + %u) * %u\n" , |
626 | snf->caps->sector_size, spare_size, nsectors); |
627 | return snand_prepare_bouncebuf(snf, size: page_size + oob_size); |
628 | err: |
629 | dev_err(snf->dev, "page size %u + %u is not supported\n" , page_size, |
630 | oob_size); |
631 | return -EOPNOTSUPP; |
632 | } |
633 | |
634 | static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, |
635 | struct mtd_oob_region *oobecc) |
636 | { |
637 | // ECC area is not accessible |
638 | return -ERANGE; |
639 | } |
640 | |
641 | static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, |
642 | struct mtd_oob_region *oobfree) |
643 | { |
644 | struct nand_device *nand = mtd_to_nanddev(mtd); |
645 | struct mtk_snand *ms = nand_to_mtk_snand(nand); |
646 | |
647 | if (section >= ms->nfi_cfg.nsectors) |
648 | return -ERANGE; |
649 | |
650 | oobfree->length = ms->caps->fdm_size - 1; |
651 | oobfree->offset = section * ms->caps->fdm_size + 1; |
652 | return 0; |
653 | } |
654 | |
655 | static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { |
656 | .ecc = mtk_snand_ooblayout_ecc, |
657 | .free = mtk_snand_ooblayout_free, |
658 | }; |
659 | |
660 | static int mtk_snand_ecc_init_ctx(struct nand_device *nand) |
661 | { |
662 | struct mtk_snand *snf = nand_to_mtk_snand(nand); |
663 | struct nand_ecc_props *conf = &nand->ecc.ctx.conf; |
664 | struct nand_ecc_props *reqs = &nand->ecc.requirements; |
665 | struct nand_ecc_props *user = &nand->ecc.user_conf; |
666 | struct mtd_info *mtd = nanddev_to_mtd(nand); |
667 | int step_size = 0, strength = 0, desired_correction = 0, steps; |
668 | bool ecc_user = false; |
669 | int ret; |
670 | u32 parity_bits, max_ecc_bytes; |
671 | struct mtk_ecc_config *ecc_cfg; |
672 | |
673 | ret = mtk_snand_setup_pagefmt(snf, page_size: nand->memorg.pagesize, |
674 | oob_size: nand->memorg.oobsize); |
675 | if (ret) |
676 | return ret; |
677 | |
678 | ecc_cfg = kzalloc(size: sizeof(*ecc_cfg), GFP_KERNEL); |
679 | if (!ecc_cfg) |
680 | return -ENOMEM; |
681 | |
682 | nand->ecc.ctx.priv = ecc_cfg; |
683 | |
684 | if (user->step_size && user->strength) { |
685 | step_size = user->step_size; |
686 | strength = user->strength; |
687 | ecc_user = true; |
688 | } else if (reqs->step_size && reqs->strength) { |
689 | step_size = reqs->step_size; |
690 | strength = reqs->strength; |
691 | } |
692 | |
693 | if (step_size && strength) { |
694 | steps = mtd->writesize / step_size; |
695 | desired_correction = steps * strength; |
696 | strength = desired_correction / snf->nfi_cfg.nsectors; |
697 | } |
698 | |
699 | ecc_cfg->mode = ECC_NFI_MODE; |
700 | ecc_cfg->sectors = snf->nfi_cfg.nsectors; |
701 | ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; |
702 | |
703 | // calculate the max possible strength under current page format |
704 | parity_bits = mtk_ecc_get_parity_bits(ecc: snf->ecc); |
705 | max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; |
706 | ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; |
707 | mtk_ecc_adjust_strength(ecc: snf->ecc, p: &ecc_cfg->strength); |
708 | |
709 | // if there's a user requested strength, find the minimum strength that |
710 | // meets the requirement. Otherwise use the maximum strength which is |
711 | // expected by BootROM. |
712 | if (ecc_user && strength) { |
713 | u32 s_next = ecc_cfg->strength - 1; |
714 | |
715 | while (1) { |
716 | mtk_ecc_adjust_strength(ecc: snf->ecc, p: &s_next); |
717 | if (s_next >= ecc_cfg->strength) |
718 | break; |
719 | if (s_next < strength) |
720 | break; |
721 | s_next = ecc_cfg->strength - 1; |
722 | } |
723 | } |
724 | |
725 | mtd_set_ooblayout(mtd, ooblayout: &mtk_snand_ooblayout); |
726 | |
727 | conf->step_size = snf->caps->sector_size; |
728 | conf->strength = ecc_cfg->strength; |
729 | |
730 | if (ecc_cfg->strength < strength) |
731 | dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n" , |
732 | strength); |
733 | dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n" , |
734 | ecc_cfg->strength, snf->caps->sector_size); |
735 | |
736 | return 0; |
737 | } |
738 | |
739 | static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) |
740 | { |
741 | struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); |
742 | |
743 | kfree(objp: ecc_cfg); |
744 | } |
745 | |
746 | static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, |
747 | struct nand_page_io_req *req) |
748 | { |
749 | struct mtk_snand *snf = nand_to_mtk_snand(nand); |
750 | struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); |
751 | int ret; |
752 | |
753 | ret = mtk_snand_setup_pagefmt(snf, page_size: nand->memorg.pagesize, |
754 | oob_size: nand->memorg.oobsize); |
755 | if (ret) |
756 | return ret; |
757 | snf->autofmt = true; |
758 | snf->ecc_cfg = ecc_cfg; |
759 | return 0; |
760 | } |
761 | |
762 | static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, |
763 | struct nand_page_io_req *req) |
764 | { |
765 | struct mtk_snand *snf = nand_to_mtk_snand(nand); |
766 | struct mtd_info *mtd = nanddev_to_mtd(nand); |
767 | |
768 | snf->ecc_cfg = NULL; |
769 | snf->autofmt = false; |
770 | if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) |
771 | return 0; |
772 | |
773 | if (snf->ecc_stats.failed) |
774 | mtd->ecc_stats.failed += snf->ecc_stats.failed; |
775 | mtd->ecc_stats.corrected += snf->ecc_stats.corrected; |
776 | return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; |
777 | } |
778 | |
779 | static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { |
780 | .init_ctx = mtk_snand_ecc_init_ctx, |
781 | .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, |
782 | .prepare_io_req = mtk_snand_ecc_prepare_io_req, |
783 | .finish_io_req = mtk_snand_ecc_finish_io_req, |
784 | }; |
785 | |
786 | static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) |
787 | { |
788 | u32 vall, valm; |
789 | u8 *oobptr = buf; |
790 | int i, j; |
791 | |
792 | for (i = 0; i < snf->nfi_cfg.nsectors; i++) { |
793 | vall = nfi_read32(snf, NFI_FDML(i)); |
794 | valm = nfi_read32(snf, NFI_FDMM(i)); |
795 | |
796 | for (j = 0; j < snf->caps->fdm_size; j++) |
797 | oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); |
798 | |
799 | oobptr += snf->caps->fdm_size; |
800 | } |
801 | } |
802 | |
803 | static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) |
804 | { |
805 | u32 fdm_size = snf->caps->fdm_size; |
806 | const u8 *oobptr = buf; |
807 | u32 vall, valm; |
808 | int i, j; |
809 | |
810 | for (i = 0; i < snf->nfi_cfg.nsectors; i++) { |
811 | vall = 0; |
812 | valm = 0; |
813 | |
814 | for (j = 0; j < 8; j++) { |
815 | if (j < 4) |
816 | vall |= (j < fdm_size ? oobptr[j] : 0xff) |
817 | << (j * 8); |
818 | else |
819 | valm |= (j < fdm_size ? oobptr[j] : 0xff) |
820 | << ((j - 4) * 8); |
821 | } |
822 | |
823 | nfi_write32(snf, NFI_FDML(i), val: vall); |
824 | nfi_write32(snf, NFI_FDMM(i), val: valm); |
825 | |
826 | oobptr += fdm_size; |
827 | } |
828 | } |
829 | |
830 | static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) |
831 | { |
832 | u32 buf_bbm_pos, fdm_bbm_pos; |
833 | |
834 | if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) |
835 | return; |
836 | |
837 | // swap [pagesize] byte on nand with the first fdm byte |
838 | // in the last sector. |
839 | buf_bbm_pos = snf->nfi_cfg.page_size - |
840 | (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; |
841 | fdm_bbm_pos = snf->nfi_cfg.page_size + |
842 | (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; |
843 | |
844 | swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); |
845 | } |
846 | |
847 | static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) |
848 | { |
849 | u32 fdm_bbm_pos1, fdm_bbm_pos2; |
850 | |
851 | if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) |
852 | return; |
853 | |
854 | // swap the first fdm byte in the first and the last sector. |
855 | fdm_bbm_pos1 = snf->nfi_cfg.page_size; |
856 | fdm_bbm_pos2 = snf->nfi_cfg.page_size + |
857 | (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; |
858 | swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); |
859 | } |
860 | |
861 | static int mtk_snand_read_page_cache(struct mtk_snand *snf, |
862 | const struct spi_mem_op *op) |
863 | { |
864 | u8 *buf = snf->buf; |
865 | u8 *buf_fdm = buf + snf->nfi_cfg.page_size; |
866 | // the address part to be sent by the controller |
867 | u32 op_addr = op->addr.val; |
868 | // where to start copying data from bounce buffer |
869 | u32 rd_offset = 0; |
870 | u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); |
871 | u32 op_mode = 0; |
872 | u32 dma_len = snf->buf_len; |
873 | int ret = 0; |
874 | u32 rd_mode, rd_bytes, val; |
875 | dma_addr_t buf_dma; |
876 | |
877 | if (snf->autofmt) { |
878 | u32 last_bit; |
879 | u32 mask; |
880 | |
881 | dma_len = snf->nfi_cfg.page_size; |
882 | op_mode = CNFG_AUTO_FMT_EN; |
883 | if (op->data.ecc) |
884 | op_mode |= CNFG_HW_ECC_EN; |
885 | // extract the plane bit: |
886 | // Find the highest bit set in (pagesize+oobsize). |
887 | // Bits higher than that in op->addr are kept and sent over SPI |
888 | // Lower bits are used as an offset for copying data from DMA |
889 | // bounce buffer. |
890 | last_bit = fls(x: snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); |
891 | mask = (1 << last_bit) - 1; |
892 | rd_offset = op_addr & mask; |
893 | op_addr &= ~mask; |
894 | |
895 | // check if we can dma to the caller memory |
896 | if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) |
897 | buf = op->data.buf.in; |
898 | } |
899 | mtk_snand_mac_reset(snf); |
900 | mtk_nfi_reset(snf); |
901 | |
902 | // command and dummy cycles |
903 | nfi_write32(snf, SNF_RD_CTL2, |
904 | val: (dummy_clk << DATA_READ_DUMMY_S) | |
905 | (op->cmd.opcode << DATA_READ_CMD_S)); |
906 | |
907 | // read address |
908 | nfi_write32(snf, SNF_RD_CTL3, val: op_addr); |
909 | |
910 | // Set read op_mode |
911 | if (op->data.buswidth == 4) |
912 | rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : |
913 | DATA_READ_MODE_X4; |
914 | else if (op->data.buswidth == 2) |
915 | rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : |
916 | DATA_READ_MODE_X2; |
917 | else |
918 | rd_mode = DATA_READ_MODE_X1; |
919 | rd_mode <<= DATA_READ_MODE_S; |
920 | nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, |
921 | set: rd_mode | DATARD_CUSTOM_EN); |
922 | |
923 | // Set bytes to read |
924 | rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * |
925 | snf->nfi_cfg.nsectors; |
926 | nfi_write32(snf, SNF_MISC_CTL2, |
927 | val: (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); |
928 | |
929 | // NFI read prepare |
930 | nfi_write16(snf, NFI_CNFG, |
931 | val: (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | |
932 | CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); |
933 | |
934 | nfi_write32(snf, NFI_CON, val: (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); |
935 | |
936 | buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); |
937 | ret = dma_mapping_error(dev: snf->dev, dma_addr: buf_dma); |
938 | if (ret) { |
939 | dev_err(snf->dev, "DMA mapping failed.\n" ); |
940 | goto cleanup; |
941 | } |
942 | nfi_write32(snf, NFI_STRADDR, val: buf_dma); |
943 | if (op->data.ecc) { |
944 | snf->ecc_cfg->op = ECC_DECODE; |
945 | ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); |
946 | if (ret) |
947 | goto cleanup_dma; |
948 | } |
949 | // Prepare for custom read interrupt |
950 | nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); |
951 | reinit_completion(x: &snf->op_done); |
952 | |
953 | // Trigger NFI into custom mode |
954 | nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); |
955 | |
956 | // Start DMA read |
957 | nfi_rmw32(snf, NFI_CON, clr: 0, CON_BRD); |
958 | nfi_write16(snf, NFI_STRDATA, STR_DATA); |
959 | |
960 | if (!wait_for_completion_timeout( |
961 | x: &snf->op_done, timeout: usecs_to_jiffies(SNFI_POLL_INTERVAL))) { |
962 | dev_err(snf->dev, "DMA timed out for reading from cache.\n" ); |
963 | ret = -ETIMEDOUT; |
964 | goto cleanup; |
965 | } |
966 | |
967 | // Wait for BUS_SEC_CNTR returning expected value |
968 | ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, |
969 | BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, |
970 | SNFI_POLL_INTERVAL); |
971 | if (ret) { |
972 | dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n" ); |
973 | goto cleanup2; |
974 | } |
975 | |
976 | // Wait for bus becoming idle |
977 | ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, |
978 | !(val & snf->caps->mastersta_mask), 0, |
979 | SNFI_POLL_INTERVAL); |
980 | if (ret) { |
981 | dev_err(snf->dev, "Timed out waiting for bus becoming idle\n" ); |
982 | goto cleanup2; |
983 | } |
984 | |
985 | if (op->data.ecc) { |
986 | ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); |
987 | if (ret) { |
988 | dev_err(snf->dev, "wait ecc done timeout\n" ); |
989 | goto cleanup2; |
990 | } |
991 | // save status before disabling ecc |
992 | mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, |
993 | snf->nfi_cfg.nsectors); |
994 | } |
995 | |
996 | dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); |
997 | |
998 | if (snf->autofmt) { |
999 | mtk_snand_read_fdm(snf, buf: buf_fdm); |
1000 | if (snf->caps->bbm_swap) { |
1001 | mtk_snand_bm_swap(snf, buf); |
1002 | mtk_snand_fdm_bm_swap(snf); |
1003 | } |
1004 | } |
1005 | |
1006 | // copy data back |
1007 | if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { |
1008 | memset(op->data.buf.in, 0xff, op->data.nbytes); |
1009 | snf->ecc_stats.bitflips = 0; |
1010 | snf->ecc_stats.failed = 0; |
1011 | snf->ecc_stats.corrected = 0; |
1012 | } else { |
1013 | if (buf == op->data.buf.in) { |
1014 | u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; |
1015 | u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; |
1016 | |
1017 | if (req_left) |
1018 | memcpy(op->data.buf.in + snf->nfi_cfg.page_size, |
1019 | buf_fdm, |
1020 | cap_len < req_left ? cap_len : req_left); |
1021 | } else if (rd_offset < snf->buf_len) { |
1022 | u32 cap_len = snf->buf_len - rd_offset; |
1023 | |
1024 | if (op->data.nbytes < cap_len) |
1025 | cap_len = op->data.nbytes; |
1026 | memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); |
1027 | } |
1028 | } |
1029 | cleanup2: |
1030 | if (op->data.ecc) |
1031 | mtk_ecc_disable(snf->ecc); |
1032 | cleanup_dma: |
1033 | // unmap dma only if any error happens. (otherwise it's done before |
1034 | // data copying) |
1035 | if (ret) |
1036 | dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); |
1037 | cleanup: |
1038 | // Stop read |
1039 | nfi_write32(snf, NFI_CON, val: 0); |
1040 | nfi_write16(snf, NFI_CNFG, val: 0); |
1041 | |
1042 | // Clear SNF done flag |
1043 | nfi_rmw32(snf, SNF_STA_CTL1, clr: 0, CUS_READ_DONE); |
1044 | nfi_write32(snf, SNF_STA_CTL1, val: 0); |
1045 | |
1046 | // Disable interrupt |
1047 | nfi_read32(snf, NFI_INTR_STA); |
1048 | nfi_write32(snf, NFI_INTR_EN, val: 0); |
1049 | |
1050 | nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, set: 0); |
1051 | return ret; |
1052 | } |
1053 | |
1054 | static int mtk_snand_write_page_cache(struct mtk_snand *snf, |
1055 | const struct spi_mem_op *op) |
1056 | { |
1057 | // the address part to be sent by the controller |
1058 | u32 op_addr = op->addr.val; |
1059 | // where to start copying data from bounce buffer |
1060 | u32 wr_offset = 0; |
1061 | u32 op_mode = 0; |
1062 | int ret = 0; |
1063 | u32 wr_mode = 0; |
1064 | u32 dma_len = snf->buf_len; |
1065 | u32 wr_bytes, val; |
1066 | size_t cap_len; |
1067 | dma_addr_t buf_dma; |
1068 | |
1069 | if (snf->autofmt) { |
1070 | u32 last_bit; |
1071 | u32 mask; |
1072 | |
1073 | dma_len = snf->nfi_cfg.page_size; |
1074 | op_mode = CNFG_AUTO_FMT_EN; |
1075 | if (op->data.ecc) |
1076 | op_mode |= CNFG_HW_ECC_EN; |
1077 | |
1078 | last_bit = fls(x: snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); |
1079 | mask = (1 << last_bit) - 1; |
1080 | wr_offset = op_addr & mask; |
1081 | op_addr &= ~mask; |
1082 | } |
1083 | mtk_snand_mac_reset(snf); |
1084 | mtk_nfi_reset(snf); |
1085 | |
1086 | if (wr_offset) |
1087 | memset(snf->buf, 0xff, wr_offset); |
1088 | |
1089 | cap_len = snf->buf_len - wr_offset; |
1090 | if (op->data.nbytes < cap_len) |
1091 | cap_len = op->data.nbytes; |
1092 | memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); |
1093 | if (snf->autofmt) { |
1094 | if (snf->caps->bbm_swap) { |
1095 | mtk_snand_fdm_bm_swap(snf); |
1096 | mtk_snand_bm_swap(snf, buf: snf->buf); |
1097 | } |
1098 | mtk_snand_write_fdm(snf, buf: snf->buf + snf->nfi_cfg.page_size); |
1099 | } |
1100 | |
1101 | // Command |
1102 | nfi_write32(snf, SNF_PG_CTL1, val: (op->cmd.opcode << PG_LOAD_CMD_S)); |
1103 | |
1104 | // write address |
1105 | nfi_write32(snf, SNF_PG_CTL2, val: op_addr); |
1106 | |
1107 | // Set read op_mode |
1108 | if (op->data.buswidth == 4) |
1109 | wr_mode = PG_LOAD_X4_EN; |
1110 | |
1111 | nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, |
1112 | set: wr_mode | PG_LOAD_CUSTOM_EN); |
1113 | |
1114 | // Set bytes to write |
1115 | wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * |
1116 | snf->nfi_cfg.nsectors; |
1117 | nfi_write32(snf, SNF_MISC_CTL2, |
1118 | val: (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); |
1119 | |
1120 | // NFI write prepare |
1121 | nfi_write16(snf, NFI_CNFG, |
1122 | val: (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | |
1123 | CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); |
1124 | |
1125 | nfi_write32(snf, NFI_CON, val: (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); |
1126 | buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); |
1127 | ret = dma_mapping_error(dev: snf->dev, dma_addr: buf_dma); |
1128 | if (ret) { |
1129 | dev_err(snf->dev, "DMA mapping failed.\n" ); |
1130 | goto cleanup; |
1131 | } |
1132 | nfi_write32(snf, NFI_STRADDR, val: buf_dma); |
1133 | if (op->data.ecc) { |
1134 | snf->ecc_cfg->op = ECC_ENCODE; |
1135 | ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); |
1136 | if (ret) |
1137 | goto cleanup_dma; |
1138 | } |
1139 | // Prepare for custom write interrupt |
1140 | nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); |
1141 | reinit_completion(x: &snf->op_done); |
1142 | ; |
1143 | |
1144 | // Trigger NFI into custom mode |
1145 | nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); |
1146 | |
1147 | // Start DMA write |
1148 | nfi_rmw32(snf, NFI_CON, clr: 0, CON_BWR); |
1149 | nfi_write16(snf, NFI_STRDATA, STR_DATA); |
1150 | |
1151 | if (!wait_for_completion_timeout( |
1152 | x: &snf->op_done, timeout: usecs_to_jiffies(SNFI_POLL_INTERVAL))) { |
1153 | dev_err(snf->dev, "DMA timed out for program load.\n" ); |
1154 | ret = -ETIMEDOUT; |
1155 | goto cleanup_ecc; |
1156 | } |
1157 | |
1158 | // Wait for NFI_SEC_CNTR returning expected value |
1159 | ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, |
1160 | NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, |
1161 | SNFI_POLL_INTERVAL); |
1162 | if (ret) |
1163 | dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n" ); |
1164 | |
1165 | cleanup_ecc: |
1166 | if (op->data.ecc) |
1167 | mtk_ecc_disable(snf->ecc); |
1168 | cleanup_dma: |
1169 | dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); |
1170 | cleanup: |
1171 | // Stop write |
1172 | nfi_write32(snf, NFI_CON, val: 0); |
1173 | nfi_write16(snf, NFI_CNFG, val: 0); |
1174 | |
1175 | // Clear SNF done flag |
1176 | nfi_rmw32(snf, SNF_STA_CTL1, clr: 0, CUS_PG_DONE); |
1177 | nfi_write32(snf, SNF_STA_CTL1, val: 0); |
1178 | |
1179 | // Disable interrupt |
1180 | nfi_read32(snf, NFI_INTR_STA); |
1181 | nfi_write32(snf, NFI_INTR_EN, val: 0); |
1182 | |
1183 | nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, set: 0); |
1184 | |
1185 | return ret; |
1186 | } |
1187 | |
1188 | /** |
1189 | * mtk_snand_is_page_ops() - check if the op is a controller supported page op. |
1190 | * @op spi-mem op to check |
1191 | * |
1192 | * Check whether op can be executed with read_from_cache or program_load |
1193 | * mode in the controller. |
1194 | * This controller can execute typical Read From Cache and Program Load |
1195 | * instructions found on SPI-NAND with 2-byte address. |
1196 | * DTR and cmd buswidth & nbytes should be checked before calling this. |
1197 | * |
1198 | * Return: true if the op matches the instruction template |
1199 | */ |
1200 | static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) |
1201 | { |
1202 | if (op->addr.nbytes != 2) |
1203 | return false; |
1204 | |
1205 | if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && |
1206 | op->addr.buswidth != 4) |
1207 | return false; |
1208 | |
1209 | // match read from page instructions |
1210 | if (op->data.dir == SPI_MEM_DATA_IN) { |
1211 | // check dummy cycle first |
1212 | if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > |
1213 | DATA_READ_MAX_DUMMY) |
1214 | return false; |
1215 | // quad io / quad out |
1216 | if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && |
1217 | op->data.buswidth == 4) |
1218 | return true; |
1219 | |
1220 | // dual io / dual out |
1221 | if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && |
1222 | op->data.buswidth == 2) |
1223 | return true; |
1224 | |
1225 | // standard spi |
1226 | if (op->addr.buswidth == 1 && op->data.buswidth == 1) |
1227 | return true; |
1228 | } else if (op->data.dir == SPI_MEM_DATA_OUT) { |
1229 | // check dummy cycle first |
1230 | if (op->dummy.nbytes) |
1231 | return false; |
1232 | // program load quad out |
1233 | if (op->addr.buswidth == 1 && op->data.buswidth == 4) |
1234 | return true; |
1235 | // standard spi |
1236 | if (op->addr.buswidth == 1 && op->data.buswidth == 1) |
1237 | return true; |
1238 | } |
1239 | return false; |
1240 | } |
1241 | |
1242 | static bool mtk_snand_supports_op(struct spi_mem *mem, |
1243 | const struct spi_mem_op *op) |
1244 | { |
1245 | if (!spi_mem_default_supports_op(mem, op)) |
1246 | return false; |
1247 | if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) |
1248 | return false; |
1249 | if (mtk_snand_is_page_ops(op)) |
1250 | return true; |
1251 | return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && |
1252 | (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && |
1253 | (op->data.nbytes == 0 || op->data.buswidth == 1)); |
1254 | } |
1255 | |
1256 | static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) |
1257 | { |
1258 | struct mtk_snand *ms = spi_controller_get_devdata(ctlr: mem->spi->controller); |
1259 | // page ops transfer size must be exactly ((sector_size + spare_size) * |
1260 | // nsectors). Limit the op size if the caller requests more than that. |
1261 | // exec_op will read more than needed and discard the leftover if the |
1262 | // caller requests less data. |
1263 | if (mtk_snand_is_page_ops(op)) { |
1264 | size_t l; |
1265 | // skip adjust_op_size for page ops |
1266 | if (ms->autofmt) |
1267 | return 0; |
1268 | l = ms->caps->sector_size + ms->nfi_cfg.spare_size; |
1269 | l *= ms->nfi_cfg.nsectors; |
1270 | if (op->data.nbytes > l) |
1271 | op->data.nbytes = l; |
1272 | } else { |
1273 | size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; |
1274 | |
1275 | if (hl >= SNF_GPRAM_SIZE) |
1276 | return -EOPNOTSUPP; |
1277 | if (op->data.nbytes > SNF_GPRAM_SIZE - hl) |
1278 | op->data.nbytes = SNF_GPRAM_SIZE - hl; |
1279 | } |
1280 | return 0; |
1281 | } |
1282 | |
1283 | static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) |
1284 | { |
1285 | struct mtk_snand *ms = spi_controller_get_devdata(ctlr: mem->spi->controller); |
1286 | |
1287 | dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u" , op->cmd.opcode, |
1288 | op->addr.val, op->addr.buswidth, op->addr.nbytes, |
1289 | op->data.buswidth, op->data.nbytes); |
1290 | if (mtk_snand_is_page_ops(op)) { |
1291 | if (op->data.dir == SPI_MEM_DATA_IN) |
1292 | return mtk_snand_read_page_cache(snf: ms, op); |
1293 | else |
1294 | return mtk_snand_write_page_cache(snf: ms, op); |
1295 | } else { |
1296 | return mtk_snand_mac_io(snf: ms, op); |
1297 | } |
1298 | } |
1299 | |
1300 | static const struct spi_controller_mem_ops mtk_snand_mem_ops = { |
1301 | .adjust_op_size = mtk_snand_adjust_op_size, |
1302 | .supports_op = mtk_snand_supports_op, |
1303 | .exec_op = mtk_snand_exec_op, |
1304 | }; |
1305 | |
1306 | static const struct spi_controller_mem_caps mtk_snand_mem_caps = { |
1307 | .ecc = true, |
1308 | }; |
1309 | |
1310 | static irqreturn_t mtk_snand_irq(int irq, void *id) |
1311 | { |
1312 | struct mtk_snand *snf = id; |
1313 | u32 sta, ien; |
1314 | |
1315 | sta = nfi_read32(snf, NFI_INTR_STA); |
1316 | ien = nfi_read32(snf, NFI_INTR_EN); |
1317 | |
1318 | if (!(sta & ien)) |
1319 | return IRQ_NONE; |
1320 | |
1321 | nfi_write32(snf, NFI_INTR_EN, val: 0); |
1322 | complete(&snf->op_done); |
1323 | return IRQ_HANDLED; |
1324 | } |
1325 | |
1326 | static const struct of_device_id mtk_snand_ids[] = { |
1327 | { .compatible = "mediatek,mt7622-snand" , .data = &mt7622_snand_caps }, |
1328 | { .compatible = "mediatek,mt7629-snand" , .data = &mt7629_snand_caps }, |
1329 | { .compatible = "mediatek,mt7986-snand" , .data = &mt7986_snand_caps }, |
1330 | {}, |
1331 | }; |
1332 | |
1333 | MODULE_DEVICE_TABLE(of, mtk_snand_ids); |
1334 | |
1335 | static int mtk_snand_probe(struct platform_device *pdev) |
1336 | { |
1337 | struct device_node *np = pdev->dev.of_node; |
1338 | const struct of_device_id *dev_id; |
1339 | struct spi_controller *ctlr; |
1340 | struct mtk_snand *ms; |
1341 | unsigned long spi_freq; |
1342 | u32 val = 0; |
1343 | int ret; |
1344 | |
1345 | dev_id = of_match_node(matches: mtk_snand_ids, node: np); |
1346 | if (!dev_id) |
1347 | return -EINVAL; |
1348 | |
1349 | ctlr = devm_spi_alloc_host(dev: &pdev->dev, size: sizeof(*ms)); |
1350 | if (!ctlr) |
1351 | return -ENOMEM; |
1352 | platform_set_drvdata(pdev, data: ctlr); |
1353 | |
1354 | ms = spi_controller_get_devdata(ctlr); |
1355 | |
1356 | ms->ctlr = ctlr; |
1357 | ms->caps = dev_id->data; |
1358 | |
1359 | ms->ecc = of_mtk_ecc_get(np); |
1360 | if (IS_ERR(ptr: ms->ecc)) |
1361 | return PTR_ERR(ptr: ms->ecc); |
1362 | else if (!ms->ecc) |
1363 | return -ENODEV; |
1364 | |
1365 | ms->nfi_base = devm_platform_ioremap_resource(pdev, index: 0); |
1366 | if (IS_ERR(ptr: ms->nfi_base)) { |
1367 | ret = PTR_ERR(ptr: ms->nfi_base); |
1368 | goto release_ecc; |
1369 | } |
1370 | |
1371 | ms->dev = &pdev->dev; |
1372 | |
1373 | ms->nfi_clk = devm_clk_get_enabled(dev: &pdev->dev, id: "nfi_clk" ); |
1374 | if (IS_ERR(ptr: ms->nfi_clk)) { |
1375 | ret = PTR_ERR(ptr: ms->nfi_clk); |
1376 | dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n" , ret); |
1377 | goto release_ecc; |
1378 | } |
1379 | |
1380 | ms->pad_clk = devm_clk_get_enabled(dev: &pdev->dev, id: "pad_clk" ); |
1381 | if (IS_ERR(ptr: ms->pad_clk)) { |
1382 | ret = PTR_ERR(ptr: ms->pad_clk); |
1383 | dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n" , ret); |
1384 | goto release_ecc; |
1385 | } |
1386 | |
1387 | ms->nfi_hclk = devm_clk_get_optional_enabled(dev: &pdev->dev, id: "nfi_hclk" ); |
1388 | if (IS_ERR(ptr: ms->nfi_hclk)) { |
1389 | ret = PTR_ERR(ptr: ms->nfi_hclk); |
1390 | dev_err(&pdev->dev, "unable to get nfi_hclk, err = %d\n" , ret); |
1391 | goto release_ecc; |
1392 | } |
1393 | |
1394 | init_completion(x: &ms->op_done); |
1395 | |
1396 | ms->irq = platform_get_irq(pdev, 0); |
1397 | if (ms->irq < 0) { |
1398 | ret = ms->irq; |
1399 | goto release_ecc; |
1400 | } |
1401 | ret = devm_request_irq(dev: ms->dev, irq: ms->irq, handler: mtk_snand_irq, irqflags: 0x0, |
1402 | devname: "mtk-snand" , dev_id: ms); |
1403 | if (ret) { |
1404 | dev_err(ms->dev, "failed to request snfi irq\n" ); |
1405 | goto release_ecc; |
1406 | } |
1407 | |
1408 | ret = dma_set_mask(dev: ms->dev, DMA_BIT_MASK(32)); |
1409 | if (ret) { |
1410 | dev_err(ms->dev, "failed to set dma mask\n" ); |
1411 | goto release_ecc; |
1412 | } |
1413 | |
1414 | // switch to SNFI mode |
1415 | nfi_write32(snf: ms, SNF_CFG, SPI_MODE); |
1416 | |
1417 | ret = of_property_read_u32(np, propname: "rx-sample-delay-ns" , out_value: &val); |
1418 | if (!ret) |
1419 | nfi_rmw32(snf: ms, SNF_DLY_CTL3, SFCK_SAM_DLY, |
1420 | set: val * SFCK_SAM_DLY_RANGE / SFCK_SAM_DLY_TOTAL); |
1421 | |
1422 | ret = of_property_read_u32(np, propname: "mediatek,rx-latch-latency-ns" , out_value: &val); |
1423 | if (!ret) { |
1424 | spi_freq = clk_get_rate(clk: ms->pad_clk); |
1425 | val = DIV_ROUND_CLOSEST(val, NSEC_PER_SEC / spi_freq); |
1426 | nfi_rmw32(snf: ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT, |
1427 | set: val << DATA_READ_LATCH_LAT_S); |
1428 | } |
1429 | |
1430 | // setup an initial page format for ops matching page_cache_op template |
1431 | // before ECC is called. |
1432 | ret = mtk_snand_setup_pagefmt(snf: ms, SZ_2K, SZ_64); |
1433 | if (ret) { |
1434 | dev_err(ms->dev, "failed to set initial page format\n" ); |
1435 | goto release_ecc; |
1436 | } |
1437 | |
1438 | // setup ECC engine |
1439 | ms->ecc_eng.dev = &pdev->dev; |
1440 | ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; |
1441 | ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; |
1442 | ms->ecc_eng.priv = ms; |
1443 | |
1444 | ret = nand_ecc_register_on_host_hw_engine(engine: &ms->ecc_eng); |
1445 | if (ret) { |
1446 | dev_err(&pdev->dev, "failed to register ecc engine.\n" ); |
1447 | goto release_ecc; |
1448 | } |
1449 | |
1450 | ctlr->num_chipselect = 1; |
1451 | ctlr->mem_ops = &mtk_snand_mem_ops; |
1452 | ctlr->mem_caps = &mtk_snand_mem_caps; |
1453 | ctlr->bits_per_word_mask = SPI_BPW_MASK(8); |
1454 | ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; |
1455 | ctlr->dev.of_node = pdev->dev.of_node; |
1456 | ret = spi_register_controller(ctlr); |
1457 | if (ret) { |
1458 | dev_err(&pdev->dev, "spi_register_controller failed.\n" ); |
1459 | goto release_ecc; |
1460 | } |
1461 | |
1462 | return 0; |
1463 | release_ecc: |
1464 | mtk_ecc_release(ms->ecc); |
1465 | return ret; |
1466 | } |
1467 | |
1468 | static void mtk_snand_remove(struct platform_device *pdev) |
1469 | { |
1470 | struct spi_controller *ctlr = platform_get_drvdata(pdev); |
1471 | struct mtk_snand *ms = spi_controller_get_devdata(ctlr); |
1472 | |
1473 | spi_unregister_controller(ctlr); |
1474 | mtk_ecc_release(ms->ecc); |
1475 | kfree(objp: ms->buf); |
1476 | } |
1477 | |
1478 | static struct platform_driver mtk_snand_driver = { |
1479 | .probe = mtk_snand_probe, |
1480 | .remove_new = mtk_snand_remove, |
1481 | .driver = { |
1482 | .name = "mtk-snand" , |
1483 | .of_match_table = mtk_snand_ids, |
1484 | }, |
1485 | }; |
1486 | |
1487 | module_platform_driver(mtk_snand_driver); |
1488 | |
1489 | MODULE_LICENSE("GPL" ); |
1490 | MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>" ); |
1491 | MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver" ); |
1492 | |