1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Synopsys DesignWare 8250 driver.
4 *
5 * Copyright 2011 Picochip, Jamie Iles.
6 * Copyright 2013 Intel Corporation
7 *
8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
9 * LCR is written whilst busy. If it is, then a busy detect interrupt is
10 * raised, the LCR needs to be rewritten and the uart status register read.
11 */
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/io.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/notifier.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/property.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25
26#include <asm/byteorder.h>
27
28#include <linux/serial_8250.h>
29#include <linux/serial_reg.h>
30
31#include "8250_dwlib.h"
32
33/* Offsets for the DesignWare specific registers */
34#define DW_UART_USR 0x1f /* UART Status Register */
35#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
36
37#define OCTEON_UART_USR 0x27 /* UART Status Register */
38
39#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
40#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
41
42/* DesignWare specific register fields */
43#define DW_UART_MCR_SIRE BIT(6)
44
45/* Renesas specific register fields */
46#define RZN1_UART_xDMACR_DMA_EN BIT(0)
47#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
48#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
49#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
50#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
51
52/* Quirks */
53#define DW_UART_QUIRK_OCTEON BIT(0)
54#define DW_UART_QUIRK_ARMADA_38X BIT(1)
55#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
56#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
57#define DW_UART_QUIRK_APMC0D08 BIT(4)
58#define DW_UART_QUIRK_CPR_VALUE BIT(5)
59
60struct dw8250_platform_data {
61 u8 usr_reg;
62 u32 cpr_value;
63 unsigned int quirks;
64};
65
66struct dw8250_data {
67 struct dw8250_port_data data;
68 const struct dw8250_platform_data *pdata;
69
70 u32 msr_mask_on;
71 u32 msr_mask_off;
72 struct clk *clk;
73 struct clk *pclk;
74 struct notifier_block clk_notifier;
75 struct work_struct clk_work;
76 struct reset_control *rst;
77
78 unsigned int skip_autocfg:1;
79 unsigned int uart_16550_compatible:1;
80};
81
82static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
83{
84 return container_of(data, struct dw8250_data, data);
85}
86
87static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
88{
89 return container_of(nb, struct dw8250_data, clk_notifier);
90}
91
92static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
93{
94 return container_of(work, struct dw8250_data, clk_work);
95}
96
97static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value)
98{
99 struct dw8250_data *d = to_dw8250_data(data: p->private_data);
100
101 /* Override any modem control signals if needed */
102 if (offset == UART_MSR) {
103 value |= d->msr_mask_on;
104 value &= ~d->msr_mask_off;
105 }
106
107 return value;
108}
109
110/*
111 * This function is being called as part of the uart_port::serial_out()
112 * routine. Hence, it must not call serial_port_out() or serial_out()
113 * against the modified registers here, i.e. LCR.
114 */
115static void dw8250_force_idle(struct uart_port *p)
116{
117 struct uart_8250_port *up = up_to_u8250p(up: p);
118 unsigned int lsr;
119
120 /*
121 * The following call currently performs serial_out()
122 * against the FCR register. Because it differs to LCR
123 * there will be no infinite loop, but if it ever gets
124 * modified, we might need a new custom version of it
125 * that avoids infinite recursion.
126 */
127 serial8250_clear_and_reinit_fifos(p: up);
128
129 /*
130 * With PSLVERR_RESP_EN parameter set to 1, the device generates an
131 * error response when an attempt to read an empty RBR with FIFO
132 * enabled.
133 */
134 if (up->fcr & UART_FCR_ENABLE_FIFO) {
135 lsr = serial_port_in(up: p, UART_LSR);
136 if (!(lsr & UART_LSR_DR))
137 return;
138 }
139
140 serial_port_in(up: p, UART_RX);
141}
142
143/*
144 * This function is being called as part of the uart_port::serial_out()
145 * routine. Hence, it must not call serial_port_out() or serial_out()
146 * against the modified registers here, i.e. LCR.
147 */
148static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value)
149{
150 struct dw8250_data *d = to_dw8250_data(data: p->private_data);
151 void __iomem *addr = p->membase + (offset << p->regshift);
152 int tries = 1000;
153
154 if (offset != UART_LCR || d->uart_16550_compatible)
155 return;
156
157 /* Make sure LCR write wasn't ignored */
158 while (tries--) {
159 u32 lcr = serial_port_in(up: p, offset);
160
161 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
162 return;
163
164 dw8250_force_idle(p);
165
166#ifdef CONFIG_64BIT
167 if (p->type == PORT_OCTEON)
168 __raw_writeq(val: value & 0xff, addr);
169 else
170#endif
171 if (p->iotype == UPIO_MEM32)
172 writel(val: value, addr);
173 else if (p->iotype == UPIO_MEM32BE)
174 iowrite32be(value, addr);
175 else
176 writeb(val: value, addr);
177 }
178 /*
179 * FIXME: this deadlocks if port->lock is already held
180 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
181 */
182}
183
184/* Returns once the transmitter is empty or we run out of retries */
185static void dw8250_tx_wait_empty(struct uart_port *p)
186{
187 struct uart_8250_port *up = up_to_u8250p(up: p);
188 unsigned int tries = 20000;
189 unsigned int delay_threshold = tries - 1000;
190 unsigned int lsr;
191
192 while (tries--) {
193 lsr = readb (addr: p->membase + (UART_LSR << p->regshift));
194 up->lsr_saved_flags |= lsr & up->lsr_save_mask;
195
196 if (lsr & UART_LSR_TEMT)
197 break;
198
199 /* The device is first given a chance to empty without delay,
200 * to avoid slowdowns at high bitrates. If after 1000 tries
201 * the buffer has still not emptied, allow more time for low-
202 * speed links. */
203 if (tries < delay_threshold)
204 udelay (usec: 1);
205 }
206}
207
208static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value)
209{
210 writeb(val: value, addr: p->membase + (offset << p->regshift));
211 dw8250_check_lcr(p, offset, value);
212}
213
214static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value)
215{
216 /* Allow the TX to drain before we reconfigure */
217 if (offset == UART_LCR)
218 dw8250_tx_wait_empty(p);
219
220 dw8250_serial_out(p, offset, value);
221}
222
223static u32 dw8250_serial_in(struct uart_port *p, unsigned int offset)
224{
225 u32 value = readb(addr: p->membase + (offset << p->regshift));
226
227 return dw8250_modify_msr(p, offset, value);
228}
229
230#ifdef CONFIG_64BIT
231static u32 dw8250_serial_inq(struct uart_port *p, unsigned int offset)
232{
233 u8 value = __raw_readq(addr: p->membase + (offset << p->regshift));
234
235 return dw8250_modify_msr(p, offset, value);
236}
237
238static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value)
239{
240 value &= 0xff;
241 __raw_writeq(val: value, addr: p->membase + (offset << p->regshift));
242 /* Read back to ensure register write ordering. */
243 __raw_readq(addr: p->membase + (UART_LCR << p->regshift));
244
245 dw8250_check_lcr(p, offset, value);
246}
247#endif /* CONFIG_64BIT */
248
249static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value)
250{
251 writel(val: value, addr: p->membase + (offset << p->regshift));
252 dw8250_check_lcr(p, offset, value);
253}
254
255static u32 dw8250_serial_in32(struct uart_port *p, unsigned int offset)
256{
257 u32 value = readl(addr: p->membase + (offset << p->regshift));
258
259 return dw8250_modify_msr(p, offset, value);
260}
261
262static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value)
263{
264 iowrite32be(value, p->membase + (offset << p->regshift));
265 dw8250_check_lcr(p, offset, value);
266}
267
268static u32 dw8250_serial_in32be(struct uart_port *p, unsigned int offset)
269{
270 u32 value = ioread32be(p->membase + (offset << p->regshift));
271
272 return dw8250_modify_msr(p, offset, value);
273}
274
275
276static int dw8250_handle_irq(struct uart_port *p)
277{
278 struct uart_8250_port *up = up_to_u8250p(up: p);
279 struct dw8250_data *d = to_dw8250_data(data: p->private_data);
280 unsigned int iir = serial_port_in(up: p, UART_IIR);
281 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
282 unsigned int quirks = d->pdata->quirks;
283 unsigned int status;
284 unsigned long flags;
285
286 /*
287 * There are ways to get Designware-based UARTs into a state where
288 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
289 * data available. If we see such a case then we'll do a bogus
290 * read. If we don't do this then the "RX TIMEOUT" interrupt will
291 * fire forever.
292 *
293 * This problem has only been observed so far when not in DMA mode
294 * so we limit the workaround only to non-DMA mode.
295 */
296 if (!up->dma && rx_timeout) {
297 uart_port_lock_irqsave(up: p, flags: &flags);
298 status = serial_lsr_in(up);
299
300 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
301 serial_port_in(up: p, UART_RX);
302
303 uart_port_unlock_irqrestore(up: p, flags);
304 }
305
306 /* Manually stop the Rx DMA transfer when acting as flow controller */
307 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
308 uart_port_lock_irqsave(up: p, flags: &flags);
309 status = serial_lsr_in(up);
310 uart_port_unlock_irqrestore(up: p, flags);
311
312 if (status & (UART_LSR_DR | UART_LSR_BI)) {
313 dw8250_writel_ext(p, RZN1_UART_RDMACR, reg: 0);
314 dw8250_writel_ext(p, DW_UART_DMASA, reg: 1);
315 }
316 }
317
318 if (serial8250_handle_irq(port: p, iir))
319 return 1;
320
321 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
322 /* Clear the USR */
323 serial_port_in(up: p, offset: d->pdata->usr_reg);
324
325 return 1;
326 }
327
328 return 0;
329}
330
331static void dw8250_clk_work_cb(struct work_struct *work)
332{
333 struct dw8250_data *d = work_to_dw8250_data(work);
334 struct uart_8250_port *up;
335 unsigned long rate;
336
337 rate = clk_get_rate(clk: d->clk);
338 if (rate <= 0)
339 return;
340
341 up = serial8250_get_port(line: d->data.line);
342
343 serial8250_update_uartclk(port: &up->port, uartclk: rate);
344}
345
346static int dw8250_clk_notifier_cb(struct notifier_block *nb,
347 unsigned long event, void *data)
348{
349 struct dw8250_data *d = clk_to_dw8250_data(nb);
350
351 /*
352 * We have no choice but to defer the uartclk update due to two
353 * deadlocks. First one is caused by a recursive mutex lock which
354 * happens when clk_set_rate() is called from dw8250_set_termios().
355 * Second deadlock is more tricky and is caused by an inverted order of
356 * the clk and tty-port mutexes lock. It happens if clock rate change
357 * is requested asynchronously while set_termios() is executed between
358 * tty-port mutex lock and clk_set_rate() function invocation and
359 * vise-versa. Anyway if we didn't have the reference clock alteration
360 * in the dw8250_set_termios() method we wouldn't have needed this
361 * deferred event handling complication.
362 */
363 if (event == POST_RATE_CHANGE) {
364 queue_work(wq: system_dfl_wq, work: &d->clk_work);
365 return NOTIFY_OK;
366 }
367
368 return NOTIFY_DONE;
369}
370
371static void
372dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
373{
374 if (!state)
375 pm_runtime_get_sync(dev: port->dev);
376
377 serial8250_do_pm(port, state, oldstate: old);
378
379 if (state)
380 pm_runtime_put_sync_suspend(dev: port->dev);
381}
382
383static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
384 const struct ktermios *old)
385{
386 unsigned long newrate = tty_termios_baud_rate(termios) * 16;
387 struct dw8250_data *d = to_dw8250_data(data: p->private_data);
388 long rate;
389 int ret;
390
391 clk_disable_unprepare(clk: d->clk);
392 rate = clk_round_rate(clk: d->clk, rate: newrate);
393 if (rate > 0) {
394 /*
395 * Note that any clock-notifier worker will block in
396 * serial8250_update_uartclk() until we are done.
397 */
398 ret = clk_set_rate(clk: d->clk, rate: newrate);
399 if (!ret)
400 p->uartclk = rate;
401 }
402 clk_prepare_enable(clk: d->clk);
403
404 dw8250_do_set_termios(p, termios, old);
405}
406
407static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
408{
409 struct uart_8250_port *up = up_to_u8250p(up: p);
410 unsigned int mcr = serial_port_in(up: p, UART_MCR);
411
412 if (up->capabilities & UART_CAP_IRDA) {
413 if (termios->c_line == N_IRDA)
414 mcr |= DW_UART_MCR_SIRE;
415 else
416 mcr &= ~DW_UART_MCR_SIRE;
417
418 serial_port_out(up: p, UART_MCR, value: mcr);
419 }
420 serial8250_do_set_ldisc(port: p, termios);
421}
422
423/*
424 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
425 * channel on platforms that have DMA engines, but don't have any channels
426 * assigned to the UART.
427 *
428 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
429 * core problem is fixed, this function is no longer needed.
430 */
431static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
432{
433 return false;
434}
435
436static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
437{
438 return param == chan->device->dev;
439}
440
441static void dw8250_setup_dma_filter(struct uart_port *p, struct dw8250_data *data)
442{
443 /* Platforms with iDMA 64-bit */
444 if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) {
445 data->data.dma.rx_param = p->dev->parent;
446 data->data.dma.tx_param = p->dev->parent;
447 data->data.dma.fn = dw8250_idma_filter;
448 } else {
449 data->data.dma.fn = dw8250_fallback_dma_filter;
450 }
451}
452
453static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
454{
455 if (max_burst >= 8)
456 return RZN1_UART_xDMACR_8_WORD_BURST;
457 else if (max_burst >= 4)
458 return RZN1_UART_xDMACR_4_WORD_BURST;
459 else
460 return RZN1_UART_xDMACR_1_WORD_BURST;
461}
462
463static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
464{
465 struct uart_port *up = &p->port;
466 struct uart_8250_dma *dma = p->dma;
467 u32 val;
468
469 dw8250_writel_ext(p: up, RZN1_UART_TDMACR, reg: 0);
470 val = dw8250_rzn1_get_dmacr_burst(max_burst: dma->txconf.dst_maxburst) |
471 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
472 RZN1_UART_xDMACR_DMA_EN;
473 dw8250_writel_ext(p: up, RZN1_UART_TDMACR, reg: val);
474}
475
476static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
477{
478 struct uart_port *up = &p->port;
479 struct uart_8250_dma *dma = p->dma;
480 u32 val;
481
482 dw8250_writel_ext(p: up, RZN1_UART_RDMACR, reg: 0);
483 val = dw8250_rzn1_get_dmacr_burst(max_burst: dma->rxconf.src_maxburst) |
484 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
485 RZN1_UART_xDMACR_DMA_EN;
486 dw8250_writel_ext(p: up, RZN1_UART_RDMACR, reg: val);
487}
488
489static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
490{
491 unsigned int quirks = data->pdata->quirks;
492 u32 cpr_value = data->pdata->cpr_value;
493
494 if (quirks & DW_UART_QUIRK_CPR_VALUE)
495 data->data.cpr_value = cpr_value;
496
497#ifdef CONFIG_64BIT
498 if (quirks & DW_UART_QUIRK_OCTEON) {
499 p->serial_in = dw8250_serial_inq;
500 p->serial_out = dw8250_serial_outq;
501 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
502 p->type = PORT_OCTEON;
503 data->skip_autocfg = true;
504 }
505#endif
506
507 if (quirks & DW_UART_QUIRK_ARMADA_38X)
508 p->serial_out = dw8250_serial_out38x;
509 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
510 p->set_termios = dw8250_do_set_termios;
511 if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
512 data->data.dma.txconf.device_fc = 1;
513 data->data.dma.rxconf.device_fc = 1;
514 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
515 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
516 }
517 if (quirks & DW_UART_QUIRK_APMC0D08) {
518 p->iotype = UPIO_MEM32;
519 p->regshift = 2;
520 p->serial_in = dw8250_serial_in32;
521 data->uart_16550_compatible = true;
522 }
523}
524
525static void dw8250_reset_control_assert(void *data)
526{
527 reset_control_assert(rstc: data);
528}
529
530static int dw8250_probe(struct platform_device *pdev)
531{
532 struct uart_8250_port uart = {}, *up = &uart;
533 struct uart_port *p = &up->port;
534 struct device *dev = &pdev->dev;
535 struct dw8250_data *data;
536 struct resource *regs;
537 int err;
538
539 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
540 if (!regs)
541 return dev_err_probe(dev, err: -EINVAL, fmt: "no registers defined\n");
542
543 spin_lock_init(&p->lock);
544 p->pm = dw8250_do_pm;
545 p->type = PORT_8250;
546 p->flags = UPF_FIXED_PORT;
547 p->dev = dev;
548 p->set_ldisc = dw8250_set_ldisc;
549 p->set_termios = dw8250_set_termios;
550
551 data = devm_kzalloc(dev, size: sizeof(*data), GFP_KERNEL);
552 if (!data)
553 return -ENOMEM;
554
555 p->private_data = &data->data;
556
557 p->mapbase = regs->start;
558 p->mapsize = resource_size(res: regs);
559
560 p->membase = devm_ioremap(dev, offset: p->mapbase, size: p->mapsize);
561 if (!p->membase)
562 return -ENOMEM;
563
564 err = uart_read_port_properties(port: p);
565 /* no interrupt -> fall back to polling */
566 if (err == -ENXIO)
567 err = 0;
568 if (err)
569 return err;
570
571 switch (p->iotype) {
572 case UPIO_MEM:
573 p->serial_in = dw8250_serial_in;
574 p->serial_out = dw8250_serial_out;
575 break;
576 case UPIO_MEM32:
577 p->serial_in = dw8250_serial_in32;
578 p->serial_out = dw8250_serial_out32;
579 break;
580 case UPIO_MEM32BE:
581 p->serial_in = dw8250_serial_in32be;
582 p->serial_out = dw8250_serial_out32be;
583 break;
584 default:
585 return -ENODEV;
586 }
587
588 if (device_property_read_bool(dev, propname: "dcd-override")) {
589 /* Always report DCD as active */
590 data->msr_mask_on |= UART_MSR_DCD;
591 data->msr_mask_off |= UART_MSR_DDCD;
592 }
593
594 if (device_property_read_bool(dev, propname: "dsr-override")) {
595 /* Always report DSR as active */
596 data->msr_mask_on |= UART_MSR_DSR;
597 data->msr_mask_off |= UART_MSR_DDSR;
598 }
599
600 if (device_property_read_bool(dev, propname: "cts-override")) {
601 /* Always report CTS as active */
602 data->msr_mask_on |= UART_MSR_CTS;
603 data->msr_mask_off |= UART_MSR_DCTS;
604 }
605
606 if (device_property_read_bool(dev, propname: "ri-override")) {
607 /* Always report Ring indicator as inactive */
608 data->msr_mask_off |= UART_MSR_RI;
609 data->msr_mask_off |= UART_MSR_TERI;
610 }
611
612 /* If there is separate baudclk, get the rate from it. */
613 data->clk = devm_clk_get_optional_enabled(dev, id: "baudclk");
614 if (data->clk == NULL)
615 data->clk = devm_clk_get_optional_enabled(dev, NULL);
616 if (IS_ERR(ptr: data->clk))
617 return dev_err_probe(dev, err: PTR_ERR(ptr: data->clk),
618 fmt: "failed to get baudclk\n");
619
620 INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
621 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
622
623 if (data->clk)
624 p->uartclk = clk_get_rate(clk: data->clk);
625
626 /* If no clock rate is defined, fail. */
627 if (!p->uartclk)
628 return dev_err_probe(dev, err: -EINVAL, fmt: "clock rate not defined\n");
629
630 data->pclk = devm_clk_get_optional_enabled(dev, id: "apb_pclk");
631 if (IS_ERR(ptr: data->pclk))
632 return PTR_ERR(ptr: data->pclk);
633
634 data->rst = devm_reset_control_array_get_optional_exclusive(dev);
635 if (IS_ERR(ptr: data->rst))
636 return PTR_ERR(ptr: data->rst);
637
638 err = reset_control_deassert(rstc: data->rst);
639 if (err)
640 return dev_err_probe(dev, err, fmt: "failed to deassert resets\n");
641
642 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
643 if (err)
644 return err;
645
646 data->uart_16550_compatible = device_property_read_bool(dev, propname: "snps,uart-16550-compatible");
647
648 data->pdata = device_get_match_data(dev: p->dev);
649 if (data->pdata)
650 dw8250_quirks(p, data);
651
652 /* If the Busy Functionality is not implemented, don't handle it */
653 if (data->uart_16550_compatible)
654 p->handle_irq = NULL;
655 else if (data->pdata)
656 p->handle_irq = dw8250_handle_irq;
657
658 dw8250_setup_dma_filter(p, data);
659
660 if (!data->skip_autocfg)
661 dw8250_setup_port(p);
662
663 /* If we have a valid fifosize, try hooking up DMA */
664 if (p->fifosize) {
665 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
666 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
667 up->dma = &data->data.dma;
668 }
669
670 data->data.line = serial8250_register_8250_port(up);
671 if (data->data.line < 0)
672 return data->data.line;
673
674 /*
675 * Some platforms may provide a reference clock shared between several
676 * devices. In this case any clock state change must be known to the
677 * UART port at least post factum.
678 */
679 if (data->clk) {
680 err = clk_notifier_register(clk: data->clk, nb: &data->clk_notifier);
681 if (err)
682 return dev_err_probe(dev, err, fmt: "Failed to set the clock notifier\n");
683 queue_work(wq: system_dfl_wq, work: &data->clk_work);
684 }
685
686 platform_set_drvdata(pdev, data);
687
688 pm_runtime_set_active(dev);
689 pm_runtime_enable(dev);
690
691 return 0;
692}
693
694static void dw8250_remove(struct platform_device *pdev)
695{
696 struct dw8250_data *data = platform_get_drvdata(pdev);
697 struct device *dev = &pdev->dev;
698
699 pm_runtime_get_sync(dev);
700
701 if (data->clk) {
702 clk_notifier_unregister(clk: data->clk, nb: &data->clk_notifier);
703
704 flush_work(work: &data->clk_work);
705 }
706
707 serial8250_unregister_port(line: data->data.line);
708
709 pm_runtime_disable(dev);
710 pm_runtime_put_noidle(dev);
711}
712
713static int dw8250_suspend(struct device *dev)
714{
715 struct dw8250_data *data = dev_get_drvdata(dev);
716
717 serial8250_suspend_port(line: data->data.line);
718
719 return 0;
720}
721
722static int dw8250_resume(struct device *dev)
723{
724 struct dw8250_data *data = dev_get_drvdata(dev);
725
726 serial8250_resume_port(line: data->data.line);
727
728 return 0;
729}
730
731static int dw8250_runtime_suspend(struct device *dev)
732{
733 struct dw8250_data *data = dev_get_drvdata(dev);
734
735 clk_disable_unprepare(clk: data->clk);
736
737 clk_disable_unprepare(clk: data->pclk);
738
739 return 0;
740}
741
742static int dw8250_runtime_resume(struct device *dev)
743{
744 struct dw8250_data *data = dev_get_drvdata(dev);
745
746 clk_prepare_enable(clk: data->pclk);
747
748 clk_prepare_enable(clk: data->clk);
749
750 return 0;
751}
752
753static const struct dev_pm_ops dw8250_pm_ops = {
754 SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
755 RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
756};
757
758static const struct dw8250_platform_data dw8250_dw_apb = {
759 .usr_reg = DW_UART_USR,
760};
761
762static const struct dw8250_platform_data dw8250_octeon_3860_data = {
763 .usr_reg = OCTEON_UART_USR,
764 .quirks = DW_UART_QUIRK_OCTEON,
765};
766
767static const struct dw8250_platform_data dw8250_armada_38x_data = {
768 .usr_reg = DW_UART_USR,
769 .quirks = DW_UART_QUIRK_ARMADA_38X,
770};
771
772static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
773 .usr_reg = DW_UART_USR,
774 .cpr_value = 0x00012f32,
775 .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
776};
777
778static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
779 .usr_reg = DW_UART_USR,
780 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
781};
782
783static const struct of_device_id dw8250_of_match[] = {
784 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
785 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
786 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
787 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
788 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
789 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
790 { /* Sentinel */ }
791};
792MODULE_DEVICE_TABLE(of, dw8250_of_match);
793
794static const struct dw8250_platform_data dw8250_apmc0d08 = {
795 .usr_reg = DW_UART_USR,
796 .quirks = DW_UART_QUIRK_APMC0D08,
797};
798
799static const struct acpi_device_id dw8250_acpi_match[] = {
800 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
801 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
802 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
803 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
804 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
805 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },
806 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
807 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
808 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
809 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
810 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
811 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
812 { "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb },
813 { },
814};
815MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
816
817static struct platform_driver dw8250_platform_driver = {
818 .driver = {
819 .name = "dw-apb-uart",
820 .pm = pm_ptr(&dw8250_pm_ops),
821 .of_match_table = dw8250_of_match,
822 .acpi_match_table = dw8250_acpi_match,
823 },
824 .probe = dw8250_probe,
825 .remove = dw8250_remove,
826};
827
828module_platform_driver(dw8250_platform_driver);
829
830MODULE_AUTHOR("Jamie Iles");
831MODULE_LICENSE("GPL");
832MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
833MODULE_ALIAS("platform:dw-apb-uart");
834

source code of linux/drivers/tty/serial/8250/8250_dw.c