1// SPDX-License-Identifier: GPL-2.0
2//
3// CS42L43 CODEC driver
4//
5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6// Cirrus Logic International Semiconductor Ltd.
7
8#include <linux/bitops.h>
9#include <linux/bits.h>
10#include <linux/build_bug.h>
11#include <linux/clk.h>
12#include <linux/device.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/bitmap.h>
16#include <linux/gcd.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/jiffies.h>
20#include <linux/mfd/cs42l43.h>
21#include <linux/mfd/cs42l43-regs.h>
22#include <linux/mod_devicetable.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/regmap.h>
27#include <linux/string.h>
28#include <linux/workqueue.h>
29#include <sound/control.h>
30#include <sound/cs42l43.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc-component.h>
34#include <sound/soc-dapm.h>
35#include <sound/soc-dai.h>
36#include <sound/soc.h>
37#include <sound/tlv.h>
38
39#include "cs42l43.h"
40
41#define CS42L43_DECL_MUX(name, reg) \
42static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \
43 0, CS42L43_MIXER_SRC_MASK, \
44 cs42l43_mixer_texts, cs42l43_mixer_values); \
45static const struct snd_kcontrol_new cs42l43_##name##_mux = \
46 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum)
47
48#define CS42L43_DECL_MIXER(name, reg) \
49 CS42L43_DECL_MUX(name##_in1, reg); \
50 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \
51 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \
52 CS42L43_DECL_MUX(name##_in4, reg + 0xC)
53
54#define CS42L43_DAPM_MUX(name_str, name) \
55 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux)
56
57#define CS42L43_DAPM_MIXER(name_str, name) \
58 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \
59 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \
60 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \
61 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \
62 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
63
64#define CS42L43_BASE_ROUTES(name_str) \
65 { name_str, "Tone Generator 1", "Tone 1" }, \
66 { name_str, "Tone Generator 2", "Tone 2" }, \
67 { name_str, "Decimator 1", "Decimator 1" }, \
68 { name_str, "Decimator 2", "Decimator 2" }, \
69 { name_str, "Decimator 3", "Decimator 3" }, \
70 { name_str, "Decimator 4", "Decimator 4" }, \
71 { name_str, "ASPRX1", "ASPRX1" }, \
72 { name_str, "ASPRX2", "ASPRX2" }, \
73 { name_str, "ASPRX3", "ASPRX3" }, \
74 { name_str, "ASPRX4", "ASPRX4" }, \
75 { name_str, "ASPRX5", "ASPRX5" }, \
76 { name_str, "ASPRX6", "ASPRX6" }, \
77 { name_str, "DP5RX1", "DP5RX1" }, \
78 { name_str, "DP5RX2", "DP5RX2" }, \
79 { name_str, "DP6RX1", "DP6RX1" }, \
80 { name_str, "DP6RX2", "DP6RX2" }, \
81 { name_str, "DP7RX1", "DP7RX1" }, \
82 { name_str, "DP7RX2", "DP7RX2" }, \
83 { name_str, "ASRC INT1", "ASRC_INT1" }, \
84 { name_str, "ASRC INT2", "ASRC_INT2" }, \
85 { name_str, "ASRC INT3", "ASRC_INT3" }, \
86 { name_str, "ASRC INT4", "ASRC_INT4" }, \
87 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
88 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
89 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
90 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
91 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \
92 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \
93 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \
94 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \
95 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \
96 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \
97 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \
98 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \
99 { name_str, "EQ1", "EQ" }, \
100 { name_str, "EQ2", "EQ" }
101
102#define CS42L43_MUX_ROUTES(name_str, widget) \
103 { widget, NULL, name_str " Input" }, \
104 { name_str " Input", NULL, "Mixer Core" }, \
105 CS42L43_BASE_ROUTES(name_str " Input")
106
107#define CS42L43_MIXER_ROUTES(name_str, widget) \
108 { name_str " Mixer", NULL, name_str " Input 1" }, \
109 { name_str " Mixer", NULL, name_str " Input 2" }, \
110 { name_str " Mixer", NULL, name_str " Input 3" }, \
111 { name_str " Mixer", NULL, name_str " Input 4" }, \
112 { widget, NULL, name_str " Mixer" }, \
113 { name_str " Mixer", NULL, "Mixer Core" }, \
114 CS42L43_BASE_ROUTES(name_str " Input 1"), \
115 CS42L43_BASE_ROUTES(name_str " Input 2"), \
116 CS42L43_BASE_ROUTES(name_str " Input 3"), \
117 CS42L43_BASE_ROUTES(name_str " Input 4")
118
119#define CS42L43_MIXER_VOLUMES(name_str, base) \
120 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \
121 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
122 cs42l43_mixer_tlv), \
123 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \
124 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
125 cs42l43_mixer_tlv), \
126 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \
127 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
128 cs42l43_mixer_tlv), \
129 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \
130 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
131 cs42l43_mixer_tlv)
132
133#define CS42L43_IRQ_ERROR(name) \
134static irqreturn_t cs42l43_##name(int irq, void *data) \
135{ \
136 struct cs42l43_codec *priv = data; \
137 dev_err(priv->dev, "Error " #name " IRQ\n"); \
138 return IRQ_HANDLED; \
139}
140
141CS42L43_IRQ_ERROR(pll_lost_lock)
142CS42L43_IRQ_ERROR(spkr_clock_stop)
143CS42L43_IRQ_ERROR(spkl_clock_stop)
144CS42L43_IRQ_ERROR(spkr_brown_out)
145CS42L43_IRQ_ERROR(spkl_brown_out)
146CS42L43_IRQ_ERROR(spkr_therm_shutdown)
147CS42L43_IRQ_ERROR(spkl_therm_shutdown)
148CS42L43_IRQ_ERROR(spkr_therm_warm)
149CS42L43_IRQ_ERROR(spkl_therm_warm)
150CS42L43_IRQ_ERROR(spkr_sc_detect)
151CS42L43_IRQ_ERROR(spkl_sc_detect)
152
153static void cs42l43_hp_ilimit_clear_work(struct work_struct *work)
154{
155 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec,
156 hp_ilimit_clear_work.work);
157 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component: priv->component);
158
159 snd_soc_dapm_mutex_lock(dapm);
160
161 priv->hp_ilimit_count--;
162
163 if (priv->hp_ilimit_count)
164 queue_delayed_work(wq: system_dfl_wq, dwork: &priv->hp_ilimit_clear_work,
165 delay: msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
166
167 snd_soc_dapm_mutex_unlock(dapm);
168}
169
170static irqreturn_t cs42l43_hp_ilimit(int irq, void *data)
171{
172 struct cs42l43_codec *priv = data;
173 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component: priv->component);
174 struct cs42l43 *cs42l43 = priv->core;
175
176 dev_dbg(priv->dev, "headphone ilimit IRQ\n");
177
178 snd_soc_dapm_mutex_lock(dapm);
179
180 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) {
181 if (!priv->hp_ilimit_count)
182 queue_delayed_work(wq: system_dfl_wq, dwork: &priv->hp_ilimit_clear_work,
183 delay: msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS));
184
185 priv->hp_ilimit_count++;
186 snd_soc_dapm_mutex_unlock(dapm);
187 return IRQ_HANDLED;
188 }
189
190 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n",
191 CS42L43_HP_ILIMIT_BACKOFF_MS);
192
193 priv->hp_ilimited = true;
194
195 // No need to wait for disable, as just disabling for a period of time
196 regmap_update_bits(map: cs42l43->regmap, CS42L43_BLOCK_EN8,
197 CS42L43_HP_EN_MASK, val: 0);
198
199 snd_soc_dapm_mutex_unlock(dapm);
200
201 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS);
202
203 snd_soc_dapm_mutex_lock(dapm);
204
205 if (priv->hp_ena && !priv->load_detect_running) {
206 unsigned long time_left;
207
208 reinit_completion(x: &priv->hp_startup);
209
210 regmap_update_bits(map: cs42l43->regmap, CS42L43_BLOCK_EN8,
211 CS42L43_HP_EN_MASK, val: priv->hp_ena);
212
213 time_left = wait_for_completion_timeout(x: &priv->hp_startup,
214 timeout: msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS));
215 if (!time_left)
216 dev_err(priv->dev, "ilimit HP restore timed out\n");
217 }
218
219 priv->hp_ilimited = false;
220
221 snd_soc_dapm_mutex_unlock(dapm);
222
223 return IRQ_HANDLED;
224}
225
226#define CS42L43_IRQ_COMPLETE(name) \
227static irqreturn_t cs42l43_##name(int irq, void *data) \
228{ \
229 struct cs42l43_codec *priv = data; \
230 dev_dbg(priv->dev, #name " completed\n"); \
231 complete(&priv->name); \
232 return IRQ_HANDLED; \
233}
234
235CS42L43_IRQ_COMPLETE(pll_ready)
236CS42L43_IRQ_COMPLETE(hp_startup)
237CS42L43_IRQ_COMPLETE(hp_shutdown)
238CS42L43_IRQ_COMPLETE(type_detect)
239CS42L43_IRQ_COMPLETE(spkr_shutdown)
240CS42L43_IRQ_COMPLETE(spkl_shutdown)
241CS42L43_IRQ_COMPLETE(spkr_startup)
242CS42L43_IRQ_COMPLETE(spkl_startup)
243CS42L43_IRQ_COMPLETE(load_detect)
244
245static irqreturn_t cs42l43_mic_shutter(int irq, void *data)
246{
247 struct cs42l43_codec *priv = data;
248 struct snd_soc_component *component = priv->component;
249 int i;
250
251 dev_dbg(priv->dev, "Microphone shutter changed\n");
252
253 if (!component)
254 return IRQ_NONE;
255
256 for (i = 1; i < ARRAY_SIZE(priv->kctl); i++) {
257 if (!priv->kctl[i])
258 return IRQ_NONE;
259
260 snd_ctl_notify(card: component->card->snd_card,
261 SNDRV_CTL_EVENT_MASK_VALUE, id: &priv->kctl[i]->id);
262 }
263
264 return IRQ_HANDLED;
265}
266
267static irqreturn_t cs42l43_spk_shutter(int irq, void *data)
268{
269 struct cs42l43_codec *priv = data;
270 struct snd_soc_component *component = priv->component;
271
272 dev_dbg(priv->dev, "Speaker shutter changed\n");
273
274 if (!component)
275 return IRQ_NONE;
276
277 if (!priv->kctl[0])
278 return IRQ_NONE;
279
280 snd_ctl_notify(card: component->card->snd_card,
281 SNDRV_CTL_EVENT_MASK_VALUE, id: &priv->kctl[0]->id);
282
283 return IRQ_HANDLED;
284}
285
286static const unsigned int cs42l43_sample_rates[] = {
287 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000,
288};
289
290#define CS42L43_CONSUMER_RATE_MASK 0xFF
291#define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer
292
293static const struct snd_pcm_hw_constraint_list cs42l43_constraint = {
294 .count = ARRAY_SIZE(cs42l43_sample_rates),
295 .list = cs42l43_sample_rates,
296};
297
298static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
299{
300 struct snd_soc_component *component = dai->component;
301 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
302 struct cs42l43 *cs42l43 = priv->core;
303 int provider = !dai->id || !!regmap_test_bits(map: cs42l43->regmap,
304 CS42L43_ASP_CLK_CONFIG2,
305 CS42L43_ASP_MASTER_MODE_MASK);
306
307 if (provider)
308 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
309 else
310 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
311
312 return snd_pcm_hw_constraint_list(runtime: substream->runtime, cond: 0,
313 SNDRV_PCM_HW_PARAM_RATE,
314 l: &priv->constraint);
315}
316
317static int cs42l43_convert_sample_rate(unsigned int rate)
318{
319 switch (rate) {
320 case 8000:
321 return 0x11;
322 case 16000:
323 return 0x12;
324 case 24000:
325 return 0x02;
326 case 32000:
327 return 0x13;
328 case 44100:
329 return 0x0B;
330 case 48000:
331 return 0x03;
332 case 96000:
333 return 0x04;
334 case 192000:
335 return 0x05;
336 default:
337 return -EINVAL;
338 }
339}
340
341static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream,
342 struct snd_pcm_hw_params *params,
343 struct snd_soc_dai *dai)
344{
345 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: dai->component);
346 struct cs42l43 *cs42l43 = priv->core;
347 int ret;
348
349 ret = cs42l43_convert_sample_rate(rate: params_rate(p: params));
350 if (ret < 0) {
351 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
352 return ret;
353 }
354
355 //FIXME: For now lets just set sample rate 1, this needs expanded in the future
356 regmap_update_bits(map: cs42l43->regmap, CS42L43_SAMPLE_RATE1,
357 CS42L43_SAMPLE_RATE_MASK, val: ret);
358
359 return 0;
360}
361
362static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream,
363 struct snd_pcm_hw_params *params,
364 struct snd_soc_dai *dai)
365{
366 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: dai->component);
367 struct cs42l43 *cs42l43 = priv->core;
368 int dsp_mode = !!regmap_test_bits(map: cs42l43->regmap, CS42L43_ASP_CTRL,
369 CS42L43_ASP_FSYNC_MODE_MASK);
370 int provider = !!regmap_test_bits(map: cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
371 CS42L43_ASP_MASTER_MODE_MASK);
372 int n_chans = params_channels(p: params);
373 int data_width = params_width(p: params);
374 int n_slots = n_chans;
375 int slot_width = data_width;
376 int frame, bclk_target, i;
377 unsigned int reg;
378 int *slots;
379
380 if (priv->n_slots) {
381 n_slots = priv->n_slots;
382 slot_width = priv->slot_width;
383 }
384
385 if (!dsp_mode && (n_slots & 0x1)) {
386 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
387 n_slots++;
388 }
389
390 frame = n_slots * slot_width;
391 bclk_target = params_rate(p: params) * frame;
392
393 if (provider) {
394 unsigned int gcd_nm = gcd(a: bclk_target, CS42L43_INTERNAL_SYSCLK);
395 int n = bclk_target / gcd_nm;
396 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm;
397
398 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) ||
399 m > CS42L43_ASP_BCLK_M_MASK) {
400 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
401 return -EINVAL;
402 }
403
404 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
405 n, m, bclk_target, n_slots, slot_width);
406
407 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
408 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK,
409 val: n << CS42L43_ASP_BCLK_N_SHIFT |
410 m << CS42L43_ASP_BCLK_M_SHIFT);
411 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
412 CS42L43_ASP_FSYNC_M_MASK, val: frame);
413 }
414
415 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
416 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK,
417 val: frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT);
418
419 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
420 reg = CS42L43_ASP_TX_CH1_CTRL;
421 slots = priv->tx_slots;
422 } else {
423 reg = CS42L43_ASP_RX_CH1_CTRL;
424 slots = priv->rx_slots;
425 }
426
427 for (i = 0; i < n_chans; i++, reg += 4) {
428 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK);
429 int slot_pos;
430
431 if (dsp_mode)
432 slot_pos = slots[i] * slot_width;
433 else
434 slot_pos = (slots[i] / 2) * slot_width;
435
436 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
437 i, slots[i], slot_pos, slot_phase);
438
439 regmap_update_bits(map: cs42l43->regmap, reg,
440 CS42L43_ASP_CH_WIDTH_MASK |
441 CS42L43_ASP_CH_SLOT_MASK |
442 CS42L43_ASP_CH_SLOT_PHASE_MASK,
443 val: ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
444 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) |
445 slot_phase);
446 }
447
448 return cs42l43_set_sample_rate(substream, params, dai);
449}
450
451static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
452{
453 struct snd_soc_component *component = dai->component;
454 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
455 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
456 struct cs42l43 *cs42l43 = priv->core;
457 int provider = regmap_test_bits(map: cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
458 CS42L43_ASP_MASTER_MODE_MASK);
459 struct snd_soc_dapm_route routes[] = {
460 { "BCLK", NULL, "FSYNC" },
461 };
462 unsigned int asp_ctrl = 0;
463 unsigned int data_ctrl = 0;
464 unsigned int fsync_ctrl = 0;
465 unsigned int clk_config = 0;
466
467 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
468 case SND_SOC_DAIFMT_DSP_A:
469 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
470 fallthrough;
471 case SND_SOC_DAIFMT_DSP_B:
472 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK;
473 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
474 break;
475 case SND_SOC_DAIFMT_I2S:
476 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT;
477 break;
478 case SND_SOC_DAIFMT_LEFT_J:
479 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK;
480 break;
481 default:
482 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
483 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
484 return -EINVAL;
485 }
486
487 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
488 case SND_SOC_DAIFMT_CBC_CFC:
489 if (provider)
490 snd_soc_dapm_del_routes(dapm, route: routes, ARRAY_SIZE(routes));
491 break;
492 case SND_SOC_DAIFMT_CBP_CFP:
493 if (!provider)
494 snd_soc_dapm_add_routes(dapm, route: routes, ARRAY_SIZE(routes));
495 clk_config |= CS42L43_ASP_MASTER_MODE_MASK;
496 break;
497 default:
498 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
499 fmt & SND_SOC_DAIFMT_MASTER_MASK);
500 return -EINVAL;
501 }
502
503 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
504 case SND_SOC_DAIFMT_NB_NF:
505 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */
506 break;
507 case SND_SOC_DAIFMT_IB_NF:
508 break;
509 case SND_SOC_DAIFMT_NB_IF:
510 clk_config |= CS42L43_ASP_BCLK_INV_MASK;
511 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
512 CS42L43_ASP_FSYNC_OUT_INV_MASK;
513 break;
514 case SND_SOC_DAIFMT_IB_IF:
515 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK |
516 CS42L43_ASP_FSYNC_OUT_INV_MASK;
517 break;
518 default:
519 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
520 fmt & SND_SOC_DAIFMT_INV_MASK);
521 return -EINVAL;
522 }
523
524 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_CTRL,
525 CS42L43_ASP_FSYNC_MODE_MASK,
526 val: asp_ctrl);
527 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
528 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK |
529 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK,
530 val: data_ctrl);
531 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
532 CS42L43_ASP_MASTER_MODE_MASK |
533 CS42L43_ASP_BCLK_INV_MASK,
534 val: clk_config);
535 regmap_update_bits(map: cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
536 CS42L43_ASP_FSYNC_IN_INV_MASK |
537 CS42L43_ASP_FSYNC_OUT_INV_MASK,
538 val: fsync_ctrl);
539
540 return 0;
541}
542
543static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask,
544 int *slots, unsigned int nslots)
545{
546 int i = 0;
547 int slot;
548
549 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) {
550 if (i == nslots) {
551 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n",
552 mask);
553 return;
554 }
555
556 slots[i++] = slot;
557 }
558
559}
560
561static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
562 unsigned int rx_mask, int slots, int slot_width)
563{
564 struct snd_soc_component *component = dai->component;
565 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
566
567 priv->n_slots = slots;
568 priv->slot_width = slot_width;
569
570 if (!slots) {
571 tx_mask = CS42L43_DEFAULT_SLOTS;
572 rx_mask = CS42L43_DEFAULT_SLOTS;
573 }
574
575 cs42l43_mask_to_slots(priv, mask: tx_mask, slots: priv->tx_slots,
576 ARRAY_SIZE(priv->tx_slots));
577 cs42l43_mask_to_slots(priv, mask: rx_mask, slots: priv->rx_slots,
578 ARRAY_SIZE(priv->rx_slots));
579
580 return 0;
581}
582
583static int cs42l43_dai_probe(struct snd_soc_dai *dai)
584{
585 struct snd_soc_component *component = dai->component;
586 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
587 static const char * const controls[] = {
588 "Speaker Digital Switch",
589 "Decimator 1 Switch",
590 "Decimator 2 Switch",
591 "Decimator 3 Switch",
592 "Decimator 4 Switch",
593 };
594 int i;
595
596 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl));
597
598 for (i = 0; i < ARRAY_SIZE(controls); i++) {
599 if (priv->kctl[i])
600 continue;
601
602 priv->kctl[i] = snd_soc_component_get_kcontrol(component, ctl: controls[i]);
603 }
604
605 return 0;
606}
607
608static int cs42l43_dai_remove(struct snd_soc_dai *dai)
609{
610 struct snd_soc_component *component = dai->component;
611 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
612 int i;
613
614 for (i = 0; i < ARRAY_SIZE(priv->kctl); i++)
615 priv->kctl[i] = NULL;
616
617 return 0;
618}
619
620static const struct snd_soc_dai_ops cs42l43_asp_ops = {
621 .probe = cs42l43_dai_probe,
622 .remove = cs42l43_dai_remove,
623 .startup = cs42l43_startup,
624 .hw_params = cs42l43_asp_hw_params,
625 .set_fmt = cs42l43_asp_set_fmt,
626 .set_tdm_slot = cs42l43_asp_set_tdm_slot,
627};
628
629static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream,
630 struct snd_pcm_hw_params *params,
631 struct snd_soc_dai *dai)
632{
633 int ret;
634
635 ret = cs42l43_sdw_add_peripheral(substream, params, dai);
636 if (ret)
637 return ret;
638
639 return cs42l43_set_sample_rate(substream, params, dai);
640}
641
642static const struct snd_soc_dai_ops cs42l43_sdw_ops = {
643 .probe = cs42l43_dai_probe,
644 .remove = cs42l43_dai_remove,
645 .startup = cs42l43_startup,
646 .set_stream = cs42l43_sdw_set_stream,
647 .hw_params = cs42l43_sdw_hw_params,
648 .hw_free = cs42l43_sdw_remove_peripheral,
649};
650
651#define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
652 SNDRV_PCM_FMTBIT_S32_LE)
653#define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
654
655static struct snd_soc_dai_driver cs42l43_dais[] = {
656 {
657 .name = "cs42l43-asp",
658 .ops = &cs42l43_asp_ops,
659 .symmetric_rate = 1,
660 .capture = {
661 .stream_name = "ASP Capture",
662 .channels_min = 1,
663 .channels_max = CS42L43_ASP_MAX_CHANNELS,
664 .rates = SNDRV_PCM_RATE_KNOT,
665 .formats = CS42L43_ASP_FORMATS,
666 },
667 .playback = {
668 .stream_name = "ASP Playback",
669 .channels_min = 1,
670 .channels_max = CS42L43_ASP_MAX_CHANNELS,
671 .rates = SNDRV_PCM_RATE_KNOT,
672 .formats = CS42L43_ASP_FORMATS,
673 },
674 },
675 {
676 .name = "cs42l43-dp1",
677 .id = 1,
678 .ops = &cs42l43_sdw_ops,
679 .capture = {
680 .stream_name = "DP1 Capture",
681 .channels_min = 1,
682 .channels_max = 4,
683 .rates = SNDRV_PCM_RATE_KNOT,
684 .formats = CS42L43_SDW_FORMATS,
685 },
686 },
687 {
688 .name = "cs42l43-dp2",
689 .id = 2,
690 .ops = &cs42l43_sdw_ops,
691 .capture = {
692 .stream_name = "DP2 Capture",
693 .channels_min = 1,
694 .channels_max = 2,
695 .rates = SNDRV_PCM_RATE_KNOT,
696 .formats = CS42L43_SDW_FORMATS,
697 },
698 },
699 {
700 .name = "cs42l43-dp3",
701 .id = 3,
702 .ops = &cs42l43_sdw_ops,
703 .capture = {
704 .stream_name = "DP3 Capture",
705 .channels_min = 1,
706 .channels_max = 2,
707 .rates = SNDRV_PCM_RATE_KNOT,
708 .formats = CS42L43_SDW_FORMATS,
709 },
710 },
711 {
712 .name = "cs42l43-dp4",
713 .id = 4,
714 .ops = &cs42l43_sdw_ops,
715 .capture = {
716 .stream_name = "DP4 Capture",
717 .channels_min = 1,
718 .channels_max = 2,
719 .rates = SNDRV_PCM_RATE_KNOT,
720 .formats = CS42L43_SDW_FORMATS,
721 },
722 },
723 {
724 .name = "cs42l43-dp5",
725 .id = 5,
726 .ops = &cs42l43_sdw_ops,
727 .playback = {
728 .stream_name = "DP5 Playback",
729 .channels_min = 1,
730 .channels_max = 2,
731 .rates = SNDRV_PCM_RATE_KNOT,
732 .formats = CS42L43_SDW_FORMATS,
733 },
734 },
735 {
736 .name = "cs42l43-dp6",
737 .id = 6,
738 .ops = &cs42l43_sdw_ops,
739 .playback = {
740 .stream_name = "DP6 Playback",
741 .channels_min = 1,
742 .channels_max = 2,
743 .rates = SNDRV_PCM_RATE_KNOT,
744 .formats = CS42L43_SDW_FORMATS,
745 },
746 },
747 {
748 .name = "cs42l43-dp7",
749 .id = 7,
750 .ops = &cs42l43_sdw_ops,
751 .playback = {
752 .stream_name = "DP7 Playback",
753 .channels_min = 1,
754 .channels_max = 2,
755 .rates = SNDRV_PCM_RATE_KNOT,
756 .formats = CS42L43_SDW_FORMATS,
757 },
758 },
759};
760
761static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
762
763static const char * const cs42l43_ramp_text[] = {
764 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
765 "15ms/6dB", "30ms/6dB",
766};
767
768static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" };
769
770static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1,
771 CS42L43_ADC_AIN_SEL_SHIFT,
772 cs42l43_adc1_input_text);
773
774static const struct snd_kcontrol_new cs42l43_adc1_input_ctl =
775 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input);
776
777static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
778
779static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text);
780static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text);
781
782static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = {
783 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode),
784 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode),
785};
786
787static const char * const cs42l43_pdm_clk_text[] = {
788 "3.072MHz", "1.536MHz", "768kHz",
789};
790
791static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL,
792 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
793static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL,
794 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text);
795
796static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
797static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
798
799static const char * const cs42l43_wnf_corner_text[] = {
800 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz",
801};
802
803static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
804 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
805static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
806 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
807static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
808 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
809static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
810 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text);
811
812static const char * const cs42l43_hpf_corner_text[] = {
813 "3Hz", "12Hz", "48Hz", "96Hz",
814};
815
816static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1,
817 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
818static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2,
819 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
820static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3,
821 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
822static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4,
823 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text);
824
825static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
826 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text);
827static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
828 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text);
829static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
830 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text);
831static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2,
832 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text);
833static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
834 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text);
835static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
836 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text);
837static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
838 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text);
839static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4,
840 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text);
841
842static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
843
844static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP,
845 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text);
846
847static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP,
848 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text);
849
850static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
851
852static const char * const cs42l43_headphone_ramp_text[] = {
853 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44",
854 "48", "66", "72",
855};
856
857static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL,
858 CS42L43_HP_PATH_VOL_RAMP_SHIFT,
859 cs42l43_headphone_ramp_text);
860
861static const char * const cs42l43_tone_freq_text[] = {
862 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz",
863};
864
865static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL,
866 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
867
868static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL,
869 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text);
870
871static const char * const cs42l43_mixer_texts[] = {
872 "None",
873 "Tone Generator 1", "Tone Generator 2",
874 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4",
875 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6",
876 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2",
877 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
878 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
879 "ISRC1 INT1", "ISRC1 INT2",
880 "ISRC1 DEC1", "ISRC1 DEC2",
881 "ISRC2 INT1", "ISRC2 INT2",
882 "ISRC2 DEC1", "ISRC2 DEC2",
883 "EQ1", "EQ2",
884};
885
886static const unsigned int cs42l43_mixer_values[] = {
887 0x00, // None
888 0x04, 0x05, // Tone Generator 1, 2
889 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4
890 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6
891 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2
892 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
893 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
894 0x50, 0x51, // ISRC1 INT1, 2
895 0x52, 0x53, // ISRC1 DEC1, 2
896 0x54, 0x55, // ISRC2 INT1, 2
897 0x56, 0x57, // ISRC2 DEC1, 2
898 0x58, 0x59, // EQ1, 2
899};
900
901CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT);
902CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT);
903CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT);
904CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT);
905CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT);
906CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT);
907
908CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT);
909CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT);
910CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT);
911CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT);
912CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT);
913CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT);
914CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT);
915CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT);
916CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT);
917CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT);
918
919CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1);
920CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1);
921CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1);
922CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1);
923CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1);
924CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1);
925CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1);
926CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1);
927
928CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1);
929CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1);
930CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1);
931CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1);
932CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1);
933CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1);
934CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1);
935CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1);
936
937CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1);
938CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1);
939
940CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1);
941CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1);
942
943CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1);
944CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1);
945
946CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1);
947CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1);
948
949static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol,
950 struct snd_ctl_elem_value *ucontrol)
951{
952 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
953 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
954 int ret;
955
956 snd_soc_dapm_mutex_lock(dapm);
957 ret = snd_soc_get_volsw(kcontrol, ucontrol);
958 snd_soc_dapm_mutex_unlock(dapm);
959
960 return ret;
961}
962
963static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol,
964 struct snd_ctl_elem_value *ucontrol)
965{
966 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
967 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
968 int ret;
969
970 snd_soc_dapm_mutex_lock(dapm);
971 ret = snd_soc_put_volsw(kcontrol, ucontrol);
972 snd_soc_dapm_mutex_unlock(dapm);
973
974 return ret;
975}
976
977static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol,
978 struct snd_ctl_elem_value *ucontrol)
979{
980 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
981 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
982 int ret;
983
984 snd_soc_dapm_mutex_lock(dapm);
985 ret = snd_soc_get_enum_double(kcontrol, ucontrol);
986 snd_soc_dapm_mutex_unlock(dapm);
987
988 return ret;
989}
990
991static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol,
992 struct snd_ctl_elem_value *ucontrol)
993{
994 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
995 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
996 int ret;
997
998 snd_soc_dapm_mutex_lock(dapm);
999 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
1000 snd_soc_dapm_mutex_unlock(dapm);
1001
1002 return ret;
1003}
1004
1005static int cs42l43_eq_get(struct snd_kcontrol *kcontrol,
1006 struct snd_ctl_elem_value *ucontrol)
1007{
1008 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1009 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1010
1011 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
1012
1013 return 0;
1014}
1015
1016static int cs42l43_eq_put(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_value *ucontrol)
1018{
1019 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1020 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1021 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1022
1023 snd_soc_dapm_mutex_lock(dapm);
1024
1025 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
1026
1027 snd_soc_dapm_mutex_unlock(dapm);
1028
1029 return 0;
1030}
1031
1032static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv)
1033{
1034 struct cs42l43 *cs42l43 = priv->core;
1035
1036 mutex_lock(&priv->spk_vu_lock);
1037
1038 regmap_update_bits(map: cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1039 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK);
1040 regmap_update_bits(map: cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1041 CS42L43_AMP1_2_VU_MASK, val: 0);
1042
1043 mutex_unlock(lock: &priv->spk_vu_lock);
1044}
1045
1046static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift)
1047{
1048 struct cs42l43 *cs42l43 = priv->core;
1049 unsigned int val;
1050 int ret;
1051
1052 ret = pm_runtime_resume_and_get(dev: priv->dev);
1053 if (ret) {
1054 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
1055 return ret;
1056 }
1057
1058 /*
1059 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
1060 * be cached for the non-volatiles, so drop it from the cache here so
1061 * we force a read.
1062 */
1063 ret = regcache_drop_region(map: cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
1064 CS42L43_SHUTTER_CONTROL);
1065 if (ret) {
1066 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
1067 goto error;
1068 }
1069
1070 ret = regmap_read(map: cs42l43->regmap, CS42L43_SHUTTER_CONTROL, val: &val);
1071 if (ret) {
1072 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
1073 goto error;
1074 }
1075
1076 ret = !(val & BIT(shift));
1077
1078 dev_dbg(priv->dev, "%s shutter is %s\n",
1079 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker",
1080 ret ? "open" : "closed");
1081
1082error:
1083 pm_runtime_put_autosuspend(dev: priv->dev);
1084
1085 return ret;
1086}
1087
1088static int cs42l43_decim_get(struct snd_kcontrol *kcontrol,
1089 struct snd_ctl_elem_value *ucontrol)
1090{
1091 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1092 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1093 int ret;
1094
1095 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT);
1096 if (ret > 0)
1097 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol);
1098 else if (!ret)
1099 ucontrol->value.integer.value[0] = ret;
1100
1101 return ret;
1102}
1103
1104static int cs42l43_spk_get(struct snd_kcontrol *kcontrol,
1105 struct snd_ctl_elem_value *ucontrol)
1106{
1107 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1108 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1109 int ret;
1110
1111 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT);
1112 if (ret > 0)
1113 ret = snd_soc_get_volsw(kcontrol, ucontrol);
1114 else if (!ret)
1115 ucontrol->value.integer.value[0] = ret;
1116
1117 return ret;
1118}
1119
1120static int cs42l43_spk_put(struct snd_kcontrol *kcontrol,
1121 struct snd_ctl_elem_value *ucontrol)
1122{
1123 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1124 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1125 int ret;
1126
1127 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1128 if (ret > 0)
1129 cs42l43_spk_vu_sync(priv);
1130
1131 return ret;
1132}
1133
1134static const struct snd_kcontrol_new cs42l43_controls[] = {
1135 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum,
1136 cs42l43_jack_get, cs42l43_jack_put),
1137
1138 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2,
1139 CS42L43_ADC_PGA_GAIN_SHIFT,
1140 0xF, 4, cs42l43_adc_tlv),
1141
1142 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1143 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0),
1144 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL,
1145 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0),
1146 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk),
1147 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk),
1148
1149 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1150 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1151 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1152 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1153 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1154 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1155 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1156 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0),
1157
1158 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner),
1159 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner),
1160 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner),
1161 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner),
1162
1163 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1,
1164 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1165 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2,
1166 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1167 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3,
1168 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1169 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4,
1170 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0),
1171
1172 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner),
1173 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner),
1174 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner),
1175 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner),
1176
1177 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1178 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1179 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1180 CS42L43_DECIM1_MUTE_SHIFT, 1, 1,
1181 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1182 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1183 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1184 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2,
1185 CS42L43_DECIM2_MUTE_SHIFT, 1, 1,
1186 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1187 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1188 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1189 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1190 CS42L43_DECIM3_MUTE_SHIFT, 1, 1,
1191 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1192 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1193 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv),
1194 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4,
1195 CS42L43_DECIM4_MUTE_SHIFT, 1, 1,
1196 cs42l43_decim_get, cs42l43_dapm_put_volsw),
1197
1198 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up,
1199 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1200 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down,
1201 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1202 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up,
1203 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1204 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down,
1205 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1206 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up,
1207 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1208 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down,
1209 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1210 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up,
1211 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1212 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down,
1213 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum),
1214
1215 SOC_DOUBLE_R_EXT("Speaker Digital Switch",
1216 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1217 CS42L43_AMP_MUTE_SHIFT, 1, 1,
1218 cs42l43_spk_get, cs42l43_spk_put),
1219
1220 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume",
1221 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2,
1222 CS42L43_AMP_VOL_SHIFT,
1223 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put,
1224 cs42l43_speaker_tlv),
1225
1226 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up),
1227 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down),
1228
1229 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1),
1230 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1),
1231
1232 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL,
1233 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT,
1234 0x11B, 229, cs42l43_headphone_tlv),
1235
1236 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1,
1237 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0),
1238
1239 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL,
1240 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0),
1241 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL,
1242 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0),
1243 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp),
1244
1245 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1),
1246 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1),
1247
1248 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq),
1249 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq),
1250
1251 SOC_DOUBLE_EXT("EQ Switch",
1252 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT,
1253 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1,
1254 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw),
1255
1256 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS,
1257 cs42l43_eq_get, cs42l43_eq_put),
1258
1259 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1),
1260 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1),
1261};
1262
1263static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w,
1264 struct snd_kcontrol *kcontrol, int event)
1265{
1266 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1267 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1268 struct cs42l43 *cs42l43 = priv->core;
1269 unsigned int val;
1270 int i, ret;
1271
1272 switch (event) {
1273 case SND_SOC_DAPM_PRE_PMU:
1274 regmap_update_bits(map: cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1275 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK,
1276 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK);
1277
1278 regmap_update_bits(map: cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1279 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK);
1280
1281 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++)
1282 regmap_write(map: cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1283 val: priv->eq_coeffs[i]);
1284
1285 regmap_update_bits(map: cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1286 CS42L43_WRITE_MODE_MASK, val: 0);
1287
1288 return 0;
1289 case SND_SOC_DAPM_POST_PMU:
1290 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1291 val, (val & CS42L43_INITIALIZE_DONE_MASK),
1292 2000, 10000);
1293 if (ret)
1294 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1295
1296 regmap_update_bits(map: cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1297 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, val: 0);
1298 return ret;
1299 default:
1300 return 0;
1301 }
1302}
1303
1304struct cs42l43_pll_config {
1305 unsigned int freq;
1306
1307 unsigned int div;
1308 unsigned int mode;
1309 unsigned int cal;
1310};
1311
1312static const struct cs42l43_pll_config cs42l43_pll_configs[] = {
1313 { 2400000, 0x50000000, 0x1, 0xA4 },
1314 { 3000000, 0x40000000, 0x1, 0x83 },
1315 { 3072000, 0x40000000, 0x3, 0x80 },
1316};
1317
1318static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src,
1319 unsigned int freq)
1320{
1321 struct cs42l43 *cs42l43 = priv->core;
1322
1323 lockdep_assert_held(&cs42l43->pll_lock);
1324
1325 if (priv->refclk_src == src && priv->refclk_freq == freq)
1326 return 0;
1327
1328 if (regmap_test_bits(map: cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1329 dev_err(priv->dev, "PLL active, can't change configuration\n");
1330 return -EBUSY;
1331 }
1332
1333 switch (src) {
1334 case CS42L43_SYSCLK_MCLK:
1335 case CS42L43_SYSCLK_SDW:
1336 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1337 src ? "SoundWire" : "MCLK", freq);
1338
1339 priv->refclk_src = src;
1340 priv->refclk_freq = freq;
1341
1342 return 0;
1343 default:
1344 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1345 return -EINVAL;
1346 }
1347}
1348
1349static int cs42l43_enable_pll(struct cs42l43_codec *priv)
1350{
1351 static const struct reg_sequence enable_seq[] = {
1352 { CS42L43_OSC_DIV_SEL, 0x0, },
1353 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, },
1354 };
1355 struct cs42l43 *cs42l43 = priv->core;
1356 const struct cs42l43_pll_config *config = NULL;
1357 unsigned int div = 0;
1358 unsigned int freq = priv->refclk_freq;
1359 unsigned long time_left;
1360
1361 lockdep_assert_held(&cs42l43->pll_lock);
1362
1363 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1364 if (!freq)
1365 freq = cs42l43->sdw_freq;
1366 else if (!cs42l43->sdw_freq)
1367 cs42l43->sdw_freq = freq;
1368 }
1369
1370 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1371
1372 div = fls(x: freq) -
1373 fls(x: cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
1374 freq >>= div;
1375
1376 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
1377 int i;
1378
1379 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) {
1380 if (freq == cs42l43_pll_configs[i].freq) {
1381 config = &cs42l43_pll_configs[i];
1382 break;
1383 }
1384 }
1385 }
1386
1387 if (!config) {
1388 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1389 return -EINVAL;
1390 }
1391
1392 regmap_update_bits(map: cs42l43->regmap, CS42L43_PLL_CONTROL,
1393 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK,
1394 val: div << CS42L43_PLL_REFCLK_DIV_SHIFT |
1395 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1396 regmap_write(map: cs42l43->regmap, CS42L43_FDIV_FRAC, val: config->div);
1397 regmap_update_bits(map: cs42l43->regmap, CS42L43_CTRL_REG,
1398 CS42L43_PLL_MODE_BYPASS_500_MASK |
1399 CS42L43_PLL_MODE_BYPASS_1029_MASK,
1400 val: config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1401 regmap_update_bits(map: cs42l43->regmap, CS42L43_CAL_RATIO,
1402 CS42L43_PLL_CAL_RATIO_MASK, val: config->cal);
1403 regmap_update_bits(map: cs42l43->regmap, CS42L43_PLL_CONTROL,
1404 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK);
1405
1406 reinit_completion(x: &priv->pll_ready);
1407
1408 regmap_update_bits(map: cs42l43->regmap, CS42L43_CTRL_REG,
1409 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK);
1410
1411 time_left = wait_for_completion_timeout(x: &priv->pll_ready,
1412 timeout: msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS));
1413 if (!time_left) {
1414 regmap_update_bits(map: cs42l43->regmap, CS42L43_CTRL_REG,
1415 CS42L43_PLL_EN_MASK, val: 0);
1416 regmap_update_bits(map: cs42l43->regmap, CS42L43_PLL_CONTROL,
1417 CS42L43_PLL_REFCLK_EN_MASK, val: 0);
1418
1419 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1420 return -ETIMEDOUT;
1421 }
1422
1423 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1424 cs42l43->sdw_pll_active = true;
1425
1426 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1427
1428 /*
1429 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL,
1430 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole
1431 * change over happens under the regmap lock to prevent any reads.
1432 */
1433 regmap_multi_reg_write(map: cs42l43->regmap, regs: enable_seq, ARRAY_SIZE(enable_seq));
1434
1435 return 0;
1436}
1437
1438static int cs42l43_disable_pll(struct cs42l43_codec *priv)
1439{
1440 static const struct reg_sequence disable_seq[] = {
1441 { CS42L43_MCLK_SRC_SEL, 0x0, 5, },
1442 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, },
1443 };
1444 struct cs42l43 *cs42l43 = priv->core;
1445
1446 dev_dbg(priv->dev, "Disabling PLL\n");
1447
1448 lockdep_assert_held(&cs42l43->pll_lock);
1449
1450 regmap_multi_reg_write(map: cs42l43->regmap, regs: disable_seq, ARRAY_SIZE(disable_seq));
1451 regmap_update_bits(map: cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, val: 0);
1452 regmap_update_bits(map: cs42l43->regmap, CS42L43_PLL_CONTROL,
1453 CS42L43_PLL_REFCLK_EN_MASK, val: 0);
1454
1455 cs42l43->sdw_pll_active = false;
1456
1457 return 0;
1458}
1459
1460static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w,
1461 struct snd_kcontrol *kcontrol, int event)
1462{
1463 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1464 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1465 struct cs42l43 *cs42l43 = priv->core;
1466 int ret;
1467
1468 mutex_lock(&cs42l43->pll_lock);
1469
1470 switch (event) {
1471 case SND_SOC_DAPM_PRE_PMU:
1472 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1473 ret = clk_prepare_enable(clk: priv->mclk);
1474 if (ret) {
1475 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1476 break;
1477 }
1478 }
1479
1480 ret = cs42l43_enable_pll(priv);
1481 break;
1482 case SND_SOC_DAPM_POST_PMD:
1483 ret = cs42l43_disable_pll(priv);
1484
1485 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1486 clk_disable_unprepare(clk: priv->mclk);
1487 break;
1488 default:
1489 ret = 0;
1490 break;
1491 }
1492
1493 mutex_unlock(lock: &cs42l43->pll_lock);
1494
1495 return ret;
1496}
1497
1498static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd,
1499 int event, int timeout_ms)
1500{
1501 unsigned long time_left;
1502
1503 switch (event) {
1504 case SND_SOC_DAPM_PRE_PMU:
1505 reinit_completion(x: pmu);
1506 return 0;
1507 case SND_SOC_DAPM_PRE_PMD:
1508 reinit_completion(x: pmd);
1509 return 0;
1510 case SND_SOC_DAPM_POST_PMU:
1511 time_left = wait_for_completion_timeout(x: pmu, timeout: msecs_to_jiffies(m: timeout_ms));
1512 break;
1513 case SND_SOC_DAPM_POST_PMD:
1514 time_left = wait_for_completion_timeout(x: pmd, timeout: msecs_to_jiffies(m: timeout_ms));
1515 break;
1516 default:
1517 return 0;
1518 }
1519
1520 if (!time_left)
1521 return -ETIMEDOUT;
1522 else
1523 return 0;
1524}
1525
1526static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w,
1527 struct snd_kcontrol *kcontrol, int event)
1528{
1529 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1530 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1531
1532 return cs42l43_dapm_wait_completion(pmu: &priv->spkr_startup,
1533 pmd: &priv->spkr_shutdown, event,
1534 CS42L43_SPK_TIMEOUT_MS);
1535}
1536
1537static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w,
1538 struct snd_kcontrol *kcontrol, int event)
1539{
1540 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1541 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1542
1543 return cs42l43_dapm_wait_completion(pmu: &priv->spkl_startup,
1544 pmd: &priv->spkl_shutdown, event,
1545 CS42L43_SPK_TIMEOUT_MS);
1546}
1547
1548static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w,
1549 struct snd_kcontrol *kcontrol, int event)
1550{
1551 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1552 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1553 struct cs42l43 *cs42l43 = priv->core;
1554 unsigned int mask = 1 << w->shift;
1555 unsigned int val = 0;
1556 int ret;
1557
1558 switch (event) {
1559 case SND_SOC_DAPM_PRE_PMU:
1560 val = mask;
1561 fallthrough;
1562 case SND_SOC_DAPM_PRE_PMD:
1563 priv->hp_ena &= ~mask;
1564 priv->hp_ena |= val;
1565
1566 ret = cs42l43_dapm_wait_completion(pmu: &priv->hp_startup,
1567 pmd: &priv->hp_shutdown, event,
1568 CS42L43_HP_TIMEOUT_MS);
1569 if (ret)
1570 return ret;
1571
1572 if (!priv->load_detect_running && !priv->hp_ilimited)
1573 regmap_update_bits(map: cs42l43->regmap, CS42L43_BLOCK_EN8,
1574 mask, val);
1575 break;
1576 case SND_SOC_DAPM_POST_PMU:
1577 case SND_SOC_DAPM_POST_PMD:
1578 if (priv->load_detect_running || priv->hp_ilimited)
1579 break;
1580
1581 ret = cs42l43_dapm_wait_completion(pmu: &priv->hp_startup,
1582 pmd: &priv->hp_shutdown, event,
1583 CS42L43_HP_TIMEOUT_MS);
1584 if (ret)
1585 return ret;
1586 break;
1587 default:
1588 break;
1589 }
1590
1591 return 0;
1592}
1593
1594static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w,
1595 struct snd_kcontrol *kcontrol, int event)
1596{
1597 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1598 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1599 struct cs42l43 *cs42l43 = priv->core;
1600 unsigned int reg, ramp, mute;
1601 unsigned int *val;
1602 int ret;
1603
1604 switch (w->shift) {
1605 case CS42L43_ADC1_EN_SHIFT:
1606 case CS42L43_PDM1_DIN_L_EN_SHIFT:
1607 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1608 ramp = CS42L43_DECIM1_VD_RAMP_MASK;
1609 mute = CS42L43_DECIM1_MUTE_MASK;
1610 val = &priv->decim_cache[0];
1611 break;
1612 case CS42L43_ADC2_EN_SHIFT:
1613 case CS42L43_PDM1_DIN_R_EN_SHIFT:
1614 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2;
1615 ramp = CS42L43_DECIM2_VD_RAMP_MASK;
1616 mute = CS42L43_DECIM2_MUTE_MASK;
1617 val = &priv->decim_cache[1];
1618 break;
1619 case CS42L43_PDM2_DIN_L_EN_SHIFT:
1620 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1621 ramp = CS42L43_DECIM3_VD_RAMP_MASK;
1622 mute = CS42L43_DECIM3_MUTE_MASK;
1623 val = &priv->decim_cache[2];
1624 break;
1625 case CS42L43_PDM2_DIN_R_EN_SHIFT:
1626 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4;
1627 ramp = CS42L43_DECIM4_VD_RAMP_MASK;
1628 mute = CS42L43_DECIM4_MUTE_MASK;
1629 val = &priv->decim_cache[3];
1630 break;
1631 default:
1632 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1633 return -EINVAL;
1634 }
1635
1636 switch (event) {
1637 case SND_SOC_DAPM_PRE_PMU:
1638 ret = regmap_read(map: cs42l43->regmap, reg, val);
1639 if (ret) {
1640 dev_err(priv->dev,
1641 "Failed to cache decimator settings: %d\n",
1642 ret);
1643 return ret;
1644 }
1645
1646 regmap_update_bits(map: cs42l43->regmap, reg, mask: mute | ramp, val: mute);
1647 break;
1648 case SND_SOC_DAPM_POST_PMU:
1649 regmap_update_bits(map: cs42l43->regmap, reg, mask: mute | ramp, val: *val);
1650 break;
1651 default:
1652 break;
1653 }
1654
1655 return 0;
1656}
1657
1658static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w,
1659 struct snd_kcontrol *kcontrol, int event)
1660{
1661 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1662 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
1663 struct cs42l43 *cs42l43 = priv->core;
1664 unsigned int mask = 1 << w->shift;
1665 unsigned int val = 0;
1666 int ret;
1667
1668 ret = cs42l43_mic_ev(w, kcontrol, event);
1669 if (ret)
1670 return ret;
1671
1672 switch (event) {
1673 case SND_SOC_DAPM_PRE_PMU:
1674 val = mask;
1675 fallthrough;
1676 case SND_SOC_DAPM_PRE_PMD:
1677 priv->adc_ena &= ~mask;
1678 priv->adc_ena |= val;
1679
1680 if (!priv->load_detect_running)
1681 regmap_update_bits(map: cs42l43->regmap, CS42L43_BLOCK_EN3,
1682 mask, val);
1683 fallthrough;
1684 default:
1685 return 0;
1686 }
1687}
1688
1689static const struct snd_soc_dapm_widget cs42l43_widgets[] = {
1690 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev,
1691 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1692
1693 SND_SOC_DAPM_INPUT("ADC1_IN1_P"),
1694 SND_SOC_DAPM_INPUT("ADC1_IN1_N"),
1695 SND_SOC_DAPM_INPUT("ADC1_IN2_P"),
1696 SND_SOC_DAPM_INPUT("ADC1_IN2_N"),
1697 SND_SOC_DAPM_INPUT("ADC2_IN_P"),
1698 SND_SOC_DAPM_INPUT("ADC2_IN_N"),
1699
1700 SND_SOC_DAPM_INPUT("PDM1_DIN"),
1701 SND_SOC_DAPM_INPUT("PDM2_DIN"),
1702
1703 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl),
1704
1705 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0,
1706 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1707 SND_SOC_DAPM_PRE_PMD),
1708 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0,
1709 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1710 SND_SOC_DAPM_PRE_PMD),
1711
1712 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT,
1713 0, NULL, 0, cs42l43_mic_ev,
1714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1715 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT,
1716 0, NULL, 0, cs42l43_mic_ev,
1717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1718 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT,
1719 0, NULL, 0, cs42l43_mic_ev,
1720 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1721 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT,
1722 0, NULL, 0, cs42l43_mic_ev,
1723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1724
1725 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0,
1726 &cs42l43_dec_mode_ctl[0]),
1727 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0,
1728 &cs42l43_dec_mode_ctl[1]),
1729
1730 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1731 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1732 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0),
1733 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT,
1736 0, NULL, 0),
1737 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT,
1738 0, NULL, 0),
1739
1740 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0,
1741 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0),
1742 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1,
1743 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0),
1744 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2,
1745 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0),
1746 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3,
1747 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0),
1748 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4,
1749 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0),
1750 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5,
1751 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0),
1752
1753 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0,
1754 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0),
1755 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1,
1756 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0),
1757 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2,
1758 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0),
1759 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3,
1760 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0),
1761 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4,
1762 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0),
1763 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5,
1764 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0),
1765
1766 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1767 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1768 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0),
1769 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0),
1770
1771 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1772 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1773
1774 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1775 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1776
1777 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1778 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1779
1780 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1781 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1782
1783 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1784 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1785
1786 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
1787 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0),
1788
1789 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1790
1791 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0,
1792 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1793 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1794 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0,
1795 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1796 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1797
1798 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"),
1799 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"),
1800 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"),
1801 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"),
1802
1803 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1804 0, NULL, 0),
1805 SND_SOC_DAPM_OUTPUT("SPDIF_TX"),
1806
1807 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0,
1808 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1809 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1810 SND_SOC_DAPM_OUTPUT("AMP3_OUT"),
1811 SND_SOC_DAPM_OUTPUT("AMP4_OUT"),
1812
1813 SND_SOC_DAPM_SIGGEN("Tone"),
1814 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT,
1815 0, NULL, 0),
1816 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL,
1817 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1818 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL,
1819 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0),
1820
1821 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT,
1822 0, NULL, 0),
1823 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT,
1824 0, NULL, 0),
1825
1826 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL,
1827 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL,
1829 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL,
1831 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL,
1833 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1834
1835 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL,
1836 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL,
1838 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL,
1840 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0),
1841 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL,
1842 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0),
1843
1844 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4,
1845 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0),
1846 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4,
1847 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0),
1848
1849 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES,
1850 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0),
1851 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES,
1852 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0),
1853 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES,
1854 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0),
1855 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES,
1856 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0),
1857 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES,
1858 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0),
1859 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES,
1860 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0),
1861 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES,
1862 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0),
1863 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES,
1864 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0),
1865
1866 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT,
1867 0, NULL, 0),
1868 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT,
1869 0, NULL, 0, cs42l43_eq_ev,
1870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1871
1872 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT,
1873 0, NULL, 0),
1874 CS42L43_DAPM_MUX("ASPTX1", asptx1),
1875 CS42L43_DAPM_MUX("ASPTX2", asptx2),
1876 CS42L43_DAPM_MUX("ASPTX3", asptx3),
1877 CS42L43_DAPM_MUX("ASPTX4", asptx4),
1878 CS42L43_DAPM_MUX("ASPTX5", asptx5),
1879 CS42L43_DAPM_MUX("ASPTX6", asptx6),
1880
1881 CS42L43_DAPM_MUX("DP1TX1", dp1tx1),
1882 CS42L43_DAPM_MUX("DP1TX2", dp1tx2),
1883 CS42L43_DAPM_MUX("DP1TX3", dp1tx3),
1884 CS42L43_DAPM_MUX("DP1TX4", dp1tx4),
1885 CS42L43_DAPM_MUX("DP2TX1", dp2tx1),
1886 CS42L43_DAPM_MUX("DP2TX2", dp2tx2),
1887 CS42L43_DAPM_MUX("DP3TX1", dp3tx1),
1888 CS42L43_DAPM_MUX("DP3TX2", dp3tx2),
1889 CS42L43_DAPM_MUX("DP4TX1", dp4tx1),
1890 CS42L43_DAPM_MUX("DP4TX2", dp4tx2),
1891
1892 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
1893 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
1894 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
1895 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
1896 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
1897 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
1898 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
1899 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
1900
1901 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1),
1902 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2),
1903 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1),
1904 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2),
1905 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1),
1906 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2),
1907 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1),
1908 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2),
1909
1910 CS42L43_DAPM_MUX("SPDIF1", spdif1),
1911 CS42L43_DAPM_MUX("SPDIF2", spdif2),
1912
1913 CS42L43_DAPM_MIXER("EQ1", eq1),
1914 CS42L43_DAPM_MIXER("EQ2", eq2),
1915
1916 CS42L43_DAPM_MIXER("Speaker L", amp1),
1917 CS42L43_DAPM_MIXER("Speaker R", amp2),
1918
1919 CS42L43_DAPM_MIXER("Headphone L", amp3),
1920 CS42L43_DAPM_MIXER("Headphone R", amp4),
1921};
1922
1923static const struct snd_soc_dapm_route cs42l43_routes[] = {
1924 { "ADC1_IN1_P", NULL, "PLL" },
1925 { "ADC1_IN1_N", NULL, "PLL" },
1926 { "ADC1_IN2_P", NULL, "PLL" },
1927 { "ADC1_IN2_N", NULL, "PLL" },
1928 { "ADC2_IN_P", NULL, "PLL" },
1929 { "ADC2_IN_N", NULL, "PLL" },
1930 { "PDM1_DIN", NULL, "PLL" },
1931 { "PDM2_DIN", NULL, "PLL" },
1932 { "AMP1_OUT_P", NULL, "PLL" },
1933 { "AMP1_OUT_N", NULL, "PLL" },
1934 { "AMP2_OUT_P", NULL, "PLL" },
1935 { "AMP2_OUT_N", NULL, "PLL" },
1936 { "SPDIF_TX", NULL, "PLL" },
1937 { "HP", NULL, "PLL" },
1938 { "AMP3_OUT", NULL, "PLL" },
1939 { "AMP4_OUT", NULL, "PLL" },
1940 { "Tone 1", NULL, "PLL" },
1941 { "Tone 2", NULL, "PLL" },
1942 { "ASP Playback", NULL, "PLL" },
1943 { "ASP Capture", NULL, "PLL" },
1944 { "DP1 Capture", NULL, "PLL" },
1945 { "DP2 Capture", NULL, "PLL" },
1946 { "DP3 Capture", NULL, "PLL" },
1947 { "DP4 Capture", NULL, "PLL" },
1948 { "DP5 Playback", NULL, "PLL" },
1949 { "DP6 Playback", NULL, "PLL" },
1950 { "DP7 Playback", NULL, "PLL" },
1951
1952 { "ADC1 Input", "IN1", "ADC1_IN1_P" },
1953 { "ADC1 Input", "IN1", "ADC1_IN1_N" },
1954 { "ADC1 Input", "IN2", "ADC1_IN2_P" },
1955 { "ADC1 Input", "IN2", "ADC1_IN2_N" },
1956
1957 { "ADC1", NULL, "ADC1 Input" },
1958 { "ADC2", NULL, "ADC2_IN_P" },
1959 { "ADC2", NULL, "ADC2_IN_N" },
1960
1961 { "PDM1L", NULL, "PDM1_DIN" },
1962 { "PDM1R", NULL, "PDM1_DIN" },
1963 { "PDM2L", NULL, "PDM2_DIN" },
1964 { "PDM2R", NULL, "PDM2_DIN" },
1965
1966 { "Decimator 1 Mode", "PDM", "PDM1L" },
1967 { "Decimator 1 Mode", "ADC", "ADC1" },
1968 { "Decimator 2 Mode", "PDM", "PDM1R" },
1969 { "Decimator 2 Mode", "ADC", "ADC2" },
1970
1971 { "Decimator 1", NULL, "Decimator 1 Mode" },
1972 { "Decimator 2", NULL, "Decimator 2 Mode" },
1973 { "Decimator 3", NULL, "PDM2L" },
1974 { "Decimator 4", NULL, "PDM2R" },
1975
1976 { "ASP Capture", NULL, "ASPTX1" },
1977 { "ASP Capture", NULL, "ASPTX2" },
1978 { "ASP Capture", NULL, "ASPTX3" },
1979 { "ASP Capture", NULL, "ASPTX4" },
1980 { "ASP Capture", NULL, "ASPTX5" },
1981 { "ASP Capture", NULL, "ASPTX6" },
1982 { "ASPTX1", NULL, "BCLK" },
1983 { "ASPTX2", NULL, "BCLK" },
1984 { "ASPTX3", NULL, "BCLK" },
1985 { "ASPTX4", NULL, "BCLK" },
1986 { "ASPTX5", NULL, "BCLK" },
1987 { "ASPTX6", NULL, "BCLK" },
1988
1989 { "ASPRX1", NULL, "ASP Playback" },
1990 { "ASPRX2", NULL, "ASP Playback" },
1991 { "ASPRX3", NULL, "ASP Playback" },
1992 { "ASPRX4", NULL, "ASP Playback" },
1993 { "ASPRX5", NULL, "ASP Playback" },
1994 { "ASPRX6", NULL, "ASP Playback" },
1995 { "ASPRX1", NULL, "BCLK" },
1996 { "ASPRX2", NULL, "BCLK" },
1997 { "ASPRX3", NULL, "BCLK" },
1998 { "ASPRX4", NULL, "BCLK" },
1999 { "ASPRX5", NULL, "BCLK" },
2000 { "ASPRX6", NULL, "BCLK" },
2001
2002 { "DP1 Capture", NULL, "DP1TX1" },
2003 { "DP1 Capture", NULL, "DP1TX2" },
2004 { "DP1 Capture", NULL, "DP1TX3" },
2005 { "DP1 Capture", NULL, "DP1TX4" },
2006
2007 { "DP2 Capture", NULL, "DP2TX1" },
2008 { "DP2 Capture", NULL, "DP2TX2" },
2009
2010 { "DP3 Capture", NULL, "DP3TX1" },
2011 { "DP3 Capture", NULL, "DP3TX2" },
2012
2013 { "DP4 Capture", NULL, "DP4TX1" },
2014 { "DP4 Capture", NULL, "DP4TX2" },
2015
2016 { "DP5RX1", NULL, "DP5 Playback" },
2017 { "DP5RX2", NULL, "DP5 Playback" },
2018
2019 { "DP6RX1", NULL, "DP6 Playback" },
2020 { "DP6RX2", NULL, "DP6 Playback" },
2021
2022 { "DP7RX1", NULL, "DP7 Playback" },
2023 { "DP7RX2", NULL, "DP7 Playback" },
2024
2025 { "AMP1", NULL, "vdd-amp" },
2026 { "AMP2", NULL, "vdd-amp" },
2027
2028 { "AMP1_OUT_P", NULL, "AMP1" },
2029 { "AMP1_OUT_N", NULL, "AMP1" },
2030 { "AMP2_OUT_P", NULL, "AMP2" },
2031 { "AMP2_OUT_N", NULL, "AMP2" },
2032
2033 { "SPDIF_TX", NULL, "SPDIF" },
2034
2035 { "AMP3_OUT", NULL, "HP" },
2036 { "AMP4_OUT", NULL, "HP" },
2037
2038 { "Tone 1", NULL, "Tone" },
2039 { "Tone 1", NULL, "Tone Generator" },
2040 { "Tone 2", NULL, "Tone" },
2041 { "Tone 2", NULL, "Tone Generator" },
2042
2043 { "ISRC1INT2", NULL, "ISRC1" },
2044 { "ISRC1INT1", NULL, "ISRC1" },
2045 { "ISRC1DEC2", NULL, "ISRC1" },
2046 { "ISRC1DEC1", NULL, "ISRC1" },
2047
2048 { "ISRC2INT2", NULL, "ISRC2" },
2049 { "ISRC2INT1", NULL, "ISRC2" },
2050 { "ISRC2DEC2", NULL, "ISRC2" },
2051 { "ISRC2DEC1", NULL, "ISRC2" },
2052
2053 { "ASRC_INT1", NULL, "ASRC_INT" },
2054 { "ASRC_INT2", NULL, "ASRC_INT" },
2055 { "ASRC_INT3", NULL, "ASRC_INT" },
2056 { "ASRC_INT4", NULL, "ASRC_INT" },
2057 { "ASRC_DEC1", NULL, "ASRC_DEC" },
2058 { "ASRC_DEC2", NULL, "ASRC_DEC" },
2059 { "ASRC_DEC3", NULL, "ASRC_DEC" },
2060 { "ASRC_DEC4", NULL, "ASRC_DEC" },
2061
2062 { "EQ", NULL, "EQ Clock" },
2063
2064 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"),
2065 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"),
2066 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"),
2067 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"),
2068 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"),
2069 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"),
2070
2071 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"),
2072 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"),
2073 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"),
2074 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"),
2075 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"),
2076 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"),
2077 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"),
2078 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"),
2079 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"),
2080 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"),
2081
2082 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2083 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2084 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2085 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2086 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2087 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2088 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2089 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2090
2091 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"),
2092 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"),
2093 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"),
2094 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"),
2095 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"),
2096 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"),
2097 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"),
2098 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"),
2099
2100 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
2101 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
2102
2103 CS42L43_MIXER_ROUTES("EQ1", "EQ"),
2104 CS42L43_MIXER_ROUTES("EQ2", "EQ"),
2105
2106 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"),
2107 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"),
2108
2109 CS42L43_MIXER_ROUTES("Headphone L", "HP"),
2110 CS42L43_MIXER_ROUTES("Headphone R", "HP"),
2111};
2112
2113static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id,
2114 int src, unsigned int freq, int dir)
2115{
2116 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
2117 struct cs42l43 *cs42l43 = priv->core;
2118 int ret;
2119
2120 mutex_lock(&cs42l43->pll_lock);
2121 ret = cs42l43_set_pll(priv, src, freq);
2122 mutex_unlock(lock: &cs42l43->pll_lock);
2123
2124 return ret;
2125}
2126
2127static int cs42l43_component_probe(struct snd_soc_component *component)
2128{
2129 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
2130 struct cs42l43 *cs42l43 = priv->core;
2131
2132 snd_soc_component_init_regmap(component, regmap: cs42l43->regmap);
2133
2134 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, slots: priv->tx_slots,
2135 ARRAY_SIZE(priv->tx_slots));
2136 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, slots: priv->rx_slots,
2137 ARRAY_SIZE(priv->rx_slots));
2138
2139 priv->component = component;
2140 priv->constraint = cs42l43_constraint;
2141
2142 return 0;
2143}
2144
2145static void cs42l43_component_remove(struct snd_soc_component *component)
2146{
2147 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(c: component);
2148
2149 cs42l43_set_jack(component: priv->component, NULL, NULL);
2150
2151 cancel_delayed_work_sync(dwork: &priv->bias_sense_timeout);
2152 cancel_delayed_work_sync(dwork: &priv->tip_sense_work);
2153
2154 cancel_delayed_work_sync(dwork: &priv->hp_ilimit_clear_work);
2155
2156 priv->component = NULL;
2157}
2158
2159static const struct snd_soc_component_driver cs42l43_component_drv = {
2160 .name = "cs42l43-codec",
2161
2162 .probe = cs42l43_component_probe,
2163 .remove = cs42l43_component_remove,
2164 .set_sysclk = cs42l43_set_sysclk,
2165 .set_jack = cs42l43_set_jack,
2166
2167 .endianness = 1,
2168
2169 .controls = cs42l43_controls,
2170 .num_controls = ARRAY_SIZE(cs42l43_controls),
2171 .dapm_widgets = cs42l43_widgets,
2172 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets),
2173 .dapm_routes = cs42l43_routes,
2174 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes),
2175};
2176
2177struct cs42l43_irq {
2178 unsigned int irq;
2179 const char *name;
2180 irq_handler_t handler;
2181};
2182
2183static const struct cs42l43_irq cs42l43_irqs[] = {
2184 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock },
2185 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready },
2186 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup },
2187 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown },
2188 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect },
2189 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense },
2190 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense },
2191 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press },
2192 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release },
2193 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp },
2194 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop },
2195 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop },
2196 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out },
2197 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out },
2198 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown },
2199 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown },
2200 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup },
2201 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup },
2202 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown },
2203 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown },
2204 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm },
2205 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm },
2206 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect },
2207 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect },
2208 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit },
2209 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect },
2210};
2211
2212static int cs42l43_request_irq(struct cs42l43_codec *priv,
2213 const char * const name, unsigned int irq,
2214 irq_handler_t handler, unsigned long flags)
2215{
2216 int ret;
2217
2218 ret = irq_create_mapping(domain: priv->dom, hwirq: irq);
2219 if (ret < 0)
2220 return dev_err_probe(dev: priv->dev, err: ret, fmt: "Failed to map IRQ %s\n", name);
2221
2222 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2223
2224 ret = devm_request_threaded_irq(dev: priv->dev, irq: ret, NULL, thread_fn: handler,
2225 IRQF_ONESHOT | flags, devname: name, dev_id: priv);
2226 if (ret)
2227 return dev_err_probe(dev: priv->dev, err: ret, fmt: "Failed to request IRQ %s\n", name);
2228
2229 return 0;
2230}
2231
2232static void cs42l43_disable_irq(struct cs42l43_codec *priv, unsigned int irq)
2233{
2234 int ret;
2235
2236 ret = irq_find_mapping(domain: priv->dom, hwirq: irq);
2237 if (ret > 0)
2238 disable_irq(irq: ret);
2239}
2240
2241static void cs42l43_enable_irq(struct cs42l43_codec *priv, unsigned int irq)
2242{
2243 int ret;
2244
2245 ret = irq_find_mapping(domain: priv->dom, hwirq: irq);
2246 if (ret > 0)
2247 enable_irq(irq: ret);
2248}
2249
2250static int cs42l43_shutter_irq(struct cs42l43_codec *priv, unsigned int shutter,
2251 const char * const open_name, unsigned int *open_irq,
2252 const char * const close_name, unsigned int *close_irq,
2253 irq_handler_t handler)
2254{
2255 int ret;
2256
2257 switch (shutter) {
2258 case 0x1:
2259 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2260 return 0;
2261 case 0x2:
2262 *open_irq = CS42L43_GPIO1_RISE;
2263 *close_irq = CS42L43_GPIO1_FALL;
2264 break;
2265 case 0x4:
2266 *open_irq = CS42L43_GPIO2_RISE;
2267 *close_irq = CS42L43_GPIO2_FALL;
2268 break;
2269 case 0x8:
2270 *open_irq = CS42L43_GPIO3_RISE;
2271 *close_irq = CS42L43_GPIO3_FALL;
2272 break;
2273 default:
2274 return 0;
2275 }
2276
2277 ret = cs42l43_request_irq(priv, name: close_name, irq: *close_irq, handler, IRQF_SHARED);
2278 if (ret)
2279 return ret;
2280
2281 return cs42l43_request_irq(priv, name: open_name, irq: *open_irq, handler, IRQF_SHARED);
2282}
2283
2284static int cs42l43_codec_probe(struct platform_device *pdev)
2285{
2286 struct cs42l43 *cs42l43 = dev_get_drvdata(dev: pdev->dev.parent);
2287 struct cs42l43_codec *priv;
2288 unsigned int val;
2289 int i, ret;
2290
2291 priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL);
2292 if (!priv)
2293 return -ENOMEM;
2294
2295 priv->dev = &pdev->dev;
2296 priv->core = cs42l43;
2297
2298 priv->dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), bus_token: DOMAIN_BUS_ANY);
2299 if (!priv->dom)
2300 return -EPROBE_DEFER;
2301
2302 platform_set_drvdata(pdev, data: priv);
2303
2304 mutex_init(&priv->jack_lock);
2305 mutex_init(&priv->spk_vu_lock);
2306
2307 init_completion(x: &priv->hp_startup);
2308 init_completion(x: &priv->hp_shutdown);
2309 init_completion(x: &priv->spkr_shutdown);
2310 init_completion(x: &priv->spkl_shutdown);
2311 init_completion(x: &priv->spkr_startup);
2312 init_completion(x: &priv->spkl_startup);
2313 init_completion(x: &priv->pll_ready);
2314 init_completion(x: &priv->type_detect);
2315 init_completion(x: &priv->load_detect);
2316
2317 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2318 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2319 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work);
2320
2321 pm_runtime_set_autosuspend_delay(dev: priv->dev, delay: 100);
2322 pm_runtime_use_autosuspend(dev: priv->dev);
2323 pm_runtime_set_active(dev: priv->dev);
2324 pm_runtime_get_noresume(dev: priv->dev);
2325
2326 ret = devm_pm_runtime_enable(dev: priv->dev);
2327 if (ret)
2328 goto err_pm;
2329
2330 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) {
2331 ret = cs42l43_request_irq(priv, name: cs42l43_irqs[i].name,
2332 irq: cs42l43_irqs[i].irq,
2333 handler: cs42l43_irqs[i].handler, flags: 0);
2334 if (ret)
2335 goto err_pm;
2336 }
2337
2338 ret = regmap_read(map: cs42l43->regmap, CS42L43_SHUTTER_CONTROL, val: &val);
2339 if (ret) {
2340 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2341 goto err_pm;
2342 }
2343
2344 ret = cs42l43_shutter_irq(priv, shutter: val & CS42L43_MIC_SHUTTER_CFG_MASK,
2345 open_name: "mic shutter open", open_irq: &priv->shutter_irqs[0],
2346 close_name: "mic shutter close", close_irq: &priv->shutter_irqs[1],
2347 handler: cs42l43_mic_shutter);
2348 if (ret)
2349 goto err_pm;
2350
2351 ret = cs42l43_shutter_irq(priv, shutter: (val & CS42L43_SPK_SHUTTER_CFG_MASK) >>
2352 CS42L43_SPK_SHUTTER_CFG_SHIFT,
2353 open_name: "spk shutter open", open_irq: &priv->shutter_irqs[2],
2354 close_name: "spk shutter close", close_irq: &priv->shutter_irqs[3],
2355 handler: cs42l43_spk_shutter);
2356 if (ret)
2357 goto err_pm;
2358
2359 // Don't use devm as we need to get against the MFD device
2360 priv->mclk = clk_get_optional(dev: cs42l43->dev, id: "mclk");
2361 if (IS_ERR(ptr: priv->mclk)) {
2362 ret = PTR_ERR(ptr: priv->mclk);
2363 dev_err_probe(dev: priv->dev, err: ret, fmt: "Failed to get mclk\n");
2364 goto err_pm;
2365 }
2366
2367 ret = devm_snd_soc_register_component(dev: priv->dev, component_driver: &cs42l43_component_drv,
2368 dai_drv: cs42l43_dais, ARRAY_SIZE(cs42l43_dais));
2369 if (ret) {
2370 dev_err_probe(dev: priv->dev, err: ret, fmt: "Failed to register component\n");
2371 goto err_clk;
2372 }
2373
2374 pm_runtime_put_autosuspend(dev: priv->dev);
2375
2376 return 0;
2377
2378err_clk:
2379 clk_put(clk: priv->mclk);
2380err_pm:
2381 pm_runtime_put_sync(dev: priv->dev);
2382
2383 return ret;
2384}
2385
2386static void cs42l43_codec_remove(struct platform_device *pdev)
2387{
2388 struct cs42l43_codec *priv = platform_get_drvdata(pdev);
2389
2390 clk_put(clk: priv->mclk);
2391}
2392
2393static int cs42l43_codec_runtime_resume(struct device *dev)
2394{
2395 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2396
2397 dev_dbg(priv->dev, "Runtime resume\n");
2398
2399 // Toggle the speaker volume update incase the speaker volume was synced
2400 cs42l43_spk_vu_sync(priv);
2401
2402 return 0;
2403}
2404
2405static int cs42l43_codec_suspend(struct device *dev)
2406{
2407 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2408 int i;
2409
2410 dev_dbg(priv->dev, "System suspend\n");
2411
2412 priv->suspend_jack_debounce = true;
2413
2414 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++)
2415 cs42l43_disable_irq(priv, irq: cs42l43_irqs[i].irq);
2416
2417 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2418 if (priv->shutter_irqs[i])
2419 cs42l43_disable_irq(priv, irq: priv->shutter_irqs[i]);
2420
2421 cancel_delayed_work_sync(dwork: &priv->bias_sense_timeout);
2422 cancel_delayed_work_sync(dwork: &priv->tip_sense_work);
2423 cancel_delayed_work_sync(dwork: &priv->hp_ilimit_clear_work);
2424
2425 cs42l43_clear_jack(priv);
2426
2427 return pm_runtime_force_suspend(dev);
2428}
2429
2430static int cs42l43_codec_resume(struct device *dev)
2431{
2432 struct cs42l43_codec *priv = dev_get_drvdata(dev);
2433 int ret, i;
2434
2435 ret = pm_runtime_force_resume(dev);
2436 if (ret)
2437 return ret;
2438
2439 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++)
2440 cs42l43_enable_irq(priv, irq: cs42l43_irqs[i].irq);
2441
2442 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2443 if (priv->shutter_irqs[i])
2444 cs42l43_enable_irq(priv, irq: priv->shutter_irqs[i]);
2445
2446 return 0;
2447}
2448
2449static const struct dev_pm_ops cs42l43_codec_pm_ops = {
2450 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL)
2451 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume)
2452};
2453
2454static const struct platform_device_id cs42l43_codec_id_table[] = {
2455 { "cs42l43-codec", },
2456 {}
2457};
2458MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table);
2459
2460static struct platform_driver cs42l43_codec_driver = {
2461 .driver = {
2462 .name = "cs42l43-codec",
2463 .pm = pm_ptr(&cs42l43_codec_pm_ops),
2464 },
2465
2466 .probe = cs42l43_codec_probe,
2467 .remove = cs42l43_codec_remove,
2468 .id_table = cs42l43_codec_id_table,
2469};
2470module_platform_driver(cs42l43_codec_driver);
2471
2472MODULE_IMPORT_NS("SND_SOC_CS42L43");
2473
2474MODULE_DESCRIPTION("CS42L43 CODEC Driver");
2475MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
2476MODULE_LICENSE("GPL");
2477

source code of linux/sound/soc/codecs/cs42l43.c