1// SPDX-License-Identifier: GPL-2.0-only
2//
3// rt5682.c -- RT5682 ALSA SoC audio component driver
4//
5// Copyright 2018 Realtek Semiconductor Corp.
6// Author: Bard Liao <bardliao@realtek.com>
7//
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/pm_runtime.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/acpi.h>
18#include <linux/gpio/consumer.h>
19#include <linux/mutex.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/rt5682.h>
29
30#include "rl6231.h"
31#include "rt5682.h"
32
33const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
34 "AVDD",
35 "MICVDD",
36 "VBAT",
37 "DBVDD",
38 "LDO1-IN",
39};
40EXPORT_SYMBOL_GPL(rt5682_supply_names);
41
42static const struct reg_sequence patch_list[] = {
43 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
44 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
45 {RT5682_I2C_CTRL, 0x000f},
46 {RT5682_PLL2_INTERNAL, 0x8266},
47 {RT5682_SAR_IL_CMD_1, 0x22b7},
48 {RT5682_SAR_IL_CMD_3, 0x0365},
49 {RT5682_SAR_IL_CMD_6, 0x0110},
50 {RT5682_CHARGE_PUMP_1, 0x0210},
51 {RT5682_HP_LOGIC_CTRL_2, 0x0007},
52 {RT5682_SAR_IL_CMD_2, 0xac00},
53 {RT5682_CBJ_CTRL_7, 0x0104},
54};
55
56void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
57{
58 int ret;
59
60 ret = regmap_multi_reg_write(map: rt5682->regmap, regs: patch_list,
61 ARRAY_SIZE(patch_list));
62 if (ret)
63 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
64}
65EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
66
67const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
68 {0x0002, 0x8080},
69 {0x0003, 0x8000},
70 {0x0005, 0x0000},
71 {0x0006, 0x0000},
72 {0x0008, 0x800f},
73 {0x000b, 0x0000},
74 {0x0010, 0x4040},
75 {0x0011, 0x0000},
76 {0x0012, 0x1404},
77 {0x0013, 0x1000},
78 {0x0014, 0xa00a},
79 {0x0015, 0x0404},
80 {0x0016, 0x0404},
81 {0x0019, 0xafaf},
82 {0x001c, 0x2f2f},
83 {0x001f, 0x0000},
84 {0x0022, 0x5757},
85 {0x0023, 0x0039},
86 {0x0024, 0x000b},
87 {0x0026, 0xc0c4},
88 {0x0029, 0x8080},
89 {0x002a, 0xa0a0},
90 {0x002b, 0x0300},
91 {0x0030, 0x0000},
92 {0x003c, 0x0080},
93 {0x0044, 0x0c0c},
94 {0x0049, 0x0000},
95 {0x0061, 0x0000},
96 {0x0062, 0x0000},
97 {0x0063, 0x003f},
98 {0x0064, 0x0000},
99 {0x0065, 0x0000},
100 {0x0066, 0x0030},
101 {0x0067, 0x0000},
102 {0x006b, 0x0000},
103 {0x006c, 0x0000},
104 {0x006d, 0x2200},
105 {0x006e, 0x0a10},
106 {0x0070, 0x8000},
107 {0x0071, 0x8000},
108 {0x0073, 0x0000},
109 {0x0074, 0x0000},
110 {0x0075, 0x0002},
111 {0x0076, 0x0001},
112 {0x0079, 0x0000},
113 {0x007a, 0x0000},
114 {0x007b, 0x0000},
115 {0x007c, 0x0100},
116 {0x007e, 0x0000},
117 {0x0080, 0x0000},
118 {0x0081, 0x0000},
119 {0x0082, 0x0000},
120 {0x0083, 0x0000},
121 {0x0084, 0x0000},
122 {0x0085, 0x0000},
123 {0x0086, 0x0005},
124 {0x0087, 0x0000},
125 {0x0088, 0x0000},
126 {0x008c, 0x0003},
127 {0x008d, 0x0000},
128 {0x008e, 0x0060},
129 {0x008f, 0x1000},
130 {0x0091, 0x0c26},
131 {0x0092, 0x0073},
132 {0x0093, 0x0000},
133 {0x0094, 0x0080},
134 {0x0098, 0x0000},
135 {0x009a, 0x0000},
136 {0x009b, 0x0000},
137 {0x009c, 0x0000},
138 {0x009d, 0x0000},
139 {0x009e, 0x100c},
140 {0x009f, 0x0000},
141 {0x00a0, 0x0000},
142 {0x00a3, 0x0002},
143 {0x00a4, 0x0001},
144 {0x00ae, 0x2040},
145 {0x00af, 0x0000},
146 {0x00b6, 0x0000},
147 {0x00b7, 0x0000},
148 {0x00b8, 0x0000},
149 {0x00b9, 0x0002},
150 {0x00be, 0x0000},
151 {0x00c0, 0x0160},
152 {0x00c1, 0x82a0},
153 {0x00c2, 0x0000},
154 {0x00d0, 0x0000},
155 {0x00d1, 0x2244},
156 {0x00d2, 0x3300},
157 {0x00d3, 0x2200},
158 {0x00d4, 0x0000},
159 {0x00d9, 0x0009},
160 {0x00da, 0x0000},
161 {0x00db, 0x0000},
162 {0x00dc, 0x00c0},
163 {0x00dd, 0x2220},
164 {0x00de, 0x3131},
165 {0x00df, 0x3131},
166 {0x00e0, 0x3131},
167 {0x00e2, 0x0000},
168 {0x00e3, 0x4000},
169 {0x00e4, 0x0aa0},
170 {0x00e5, 0x3131},
171 {0x00e6, 0x3131},
172 {0x00e7, 0x3131},
173 {0x00e8, 0x3131},
174 {0x00ea, 0xb320},
175 {0x00eb, 0x0000},
176 {0x00f0, 0x0000},
177 {0x00f1, 0x00d0},
178 {0x00f2, 0x00d0},
179 {0x00f6, 0x0000},
180 {0x00fa, 0x0000},
181 {0x00fb, 0x0000},
182 {0x00fc, 0x0000},
183 {0x00fd, 0x0000},
184 {0x00fe, 0x10ec},
185 {0x00ff, 0x6530},
186 {0x0100, 0xa0a0},
187 {0x010b, 0x0000},
188 {0x010c, 0xae00},
189 {0x010d, 0xaaa0},
190 {0x010e, 0x8aa2},
191 {0x010f, 0x02a2},
192 {0x0110, 0xc000},
193 {0x0111, 0x04a2},
194 {0x0112, 0x2800},
195 {0x0113, 0x0000},
196 {0x0117, 0x0100},
197 {0x0125, 0x0410},
198 {0x0132, 0x6026},
199 {0x0136, 0x5555},
200 {0x0138, 0x3700},
201 {0x013a, 0x2000},
202 {0x013b, 0x2000},
203 {0x013c, 0x2005},
204 {0x013f, 0x0000},
205 {0x0142, 0x0000},
206 {0x0145, 0x0002},
207 {0x0146, 0x0000},
208 {0x0147, 0x0000},
209 {0x0148, 0x0000},
210 {0x0149, 0x0000},
211 {0x0150, 0x79a1},
212 {0x0156, 0xaaaa},
213 {0x0160, 0x4ec0},
214 {0x0161, 0x0080},
215 {0x0162, 0x0200},
216 {0x0163, 0x0800},
217 {0x0164, 0x0000},
218 {0x0165, 0x0000},
219 {0x0166, 0x0000},
220 {0x0167, 0x000f},
221 {0x0168, 0x000f},
222 {0x0169, 0x0021},
223 {0x0190, 0x413d},
224 {0x0194, 0x0000},
225 {0x0195, 0x0000},
226 {0x0197, 0x0022},
227 {0x0198, 0x0000},
228 {0x0199, 0x0000},
229 {0x01af, 0x0000},
230 {0x01b0, 0x0400},
231 {0x01b1, 0x0000},
232 {0x01b2, 0x0000},
233 {0x01b3, 0x0000},
234 {0x01b4, 0x0000},
235 {0x01b5, 0x0000},
236 {0x01b6, 0x01c3},
237 {0x01b7, 0x02a0},
238 {0x01b8, 0x03e9},
239 {0x01b9, 0x1389},
240 {0x01ba, 0xc351},
241 {0x01bb, 0x0009},
242 {0x01bc, 0x0018},
243 {0x01bd, 0x002a},
244 {0x01be, 0x004c},
245 {0x01bf, 0x0097},
246 {0x01c0, 0x433d},
247 {0x01c2, 0x0000},
248 {0x01c3, 0x0000},
249 {0x01c4, 0x0000},
250 {0x01c5, 0x0000},
251 {0x01c6, 0x0000},
252 {0x01c7, 0x0000},
253 {0x01c8, 0x40af},
254 {0x01c9, 0x0702},
255 {0x01ca, 0x0000},
256 {0x01cb, 0x0000},
257 {0x01cc, 0x5757},
258 {0x01cd, 0x5757},
259 {0x01ce, 0x5757},
260 {0x01cf, 0x5757},
261 {0x01d0, 0x5757},
262 {0x01d1, 0x5757},
263 {0x01d2, 0x5757},
264 {0x01d3, 0x5757},
265 {0x01d4, 0x5757},
266 {0x01d5, 0x5757},
267 {0x01d6, 0x0000},
268 {0x01d7, 0x0008},
269 {0x01d8, 0x0029},
270 {0x01d9, 0x3333},
271 {0x01da, 0x0000},
272 {0x01db, 0x0004},
273 {0x01dc, 0x0000},
274 {0x01de, 0x7c00},
275 {0x01df, 0x0320},
276 {0x01e0, 0x06a1},
277 {0x01e1, 0x0000},
278 {0x01e2, 0x0000},
279 {0x01e3, 0x0000},
280 {0x01e4, 0x0000},
281 {0x01e6, 0x0001},
282 {0x01e7, 0x0000},
283 {0x01e8, 0x0000},
284 {0x01ea, 0x0000},
285 {0x01eb, 0x0000},
286 {0x01ec, 0x0000},
287 {0x01ed, 0x0000},
288 {0x01ee, 0x0000},
289 {0x01ef, 0x0000},
290 {0x01f0, 0x0000},
291 {0x01f1, 0x0000},
292 {0x01f2, 0x0000},
293 {0x01f3, 0x0000},
294 {0x01f4, 0x0000},
295 {0x0210, 0x6297},
296 {0x0211, 0xa005},
297 {0x0212, 0x824c},
298 {0x0213, 0xf7ff},
299 {0x0214, 0xf24c},
300 {0x0215, 0x0102},
301 {0x0216, 0x00a3},
302 {0x0217, 0x0048},
303 {0x0218, 0xa2c0},
304 {0x0219, 0x0400},
305 {0x021a, 0x00c8},
306 {0x021b, 0x00c0},
307 {0x021c, 0x0000},
308 {0x0250, 0x4500},
309 {0x0251, 0x40b3},
310 {0x0252, 0x0000},
311 {0x0253, 0x0000},
312 {0x0254, 0x0000},
313 {0x0255, 0x0000},
314 {0x0256, 0x0000},
315 {0x0257, 0x0000},
316 {0x0258, 0x0000},
317 {0x0259, 0x0000},
318 {0x025a, 0x0005},
319 {0x0270, 0x0000},
320 {0x02ff, 0x0110},
321 {0x0300, 0x001f},
322 {0x0301, 0x032c},
323 {0x0302, 0x5f21},
324 {0x0303, 0x4000},
325 {0x0304, 0x4000},
326 {0x0305, 0x06d5},
327 {0x0306, 0x8000},
328 {0x0307, 0x0700},
329 {0x0310, 0x4560},
330 {0x0311, 0xa4a8},
331 {0x0312, 0x7418},
332 {0x0313, 0x0000},
333 {0x0314, 0x0006},
334 {0x0315, 0xffff},
335 {0x0316, 0xc400},
336 {0x0317, 0x0000},
337 {0x03c0, 0x7e00},
338 {0x03c1, 0x8000},
339 {0x03c2, 0x8000},
340 {0x03c3, 0x8000},
341 {0x03c4, 0x8000},
342 {0x03c5, 0x8000},
343 {0x03c6, 0x8000},
344 {0x03c7, 0x8000},
345 {0x03c8, 0x8000},
346 {0x03c9, 0x8000},
347 {0x03ca, 0x8000},
348 {0x03cb, 0x8000},
349 {0x03cc, 0x8000},
350 {0x03d0, 0x0000},
351 {0x03d1, 0x0000},
352 {0x03d2, 0x0000},
353 {0x03d3, 0x0000},
354 {0x03d4, 0x2000},
355 {0x03d5, 0x2000},
356 {0x03d6, 0x0000},
357 {0x03d7, 0x0000},
358 {0x03d8, 0x2000},
359 {0x03d9, 0x2000},
360 {0x03da, 0x2000},
361 {0x03db, 0x2000},
362 {0x03dc, 0x0000},
363 {0x03dd, 0x0000},
364 {0x03de, 0x0000},
365 {0x03df, 0x2000},
366 {0x03e0, 0x0000},
367 {0x03e1, 0x0000},
368 {0x03e2, 0x0000},
369 {0x03e3, 0x0000},
370 {0x03e4, 0x0000},
371 {0x03e5, 0x0000},
372 {0x03e6, 0x0000},
373 {0x03e7, 0x0000},
374 {0x03e8, 0x0000},
375 {0x03e9, 0x0000},
376 {0x03ea, 0x0000},
377 {0x03eb, 0x0000},
378 {0x03ec, 0x0000},
379 {0x03ed, 0x0000},
380 {0x03ee, 0x0000},
381 {0x03ef, 0x0000},
382 {0x03f0, 0x0800},
383 {0x03f1, 0x0800},
384 {0x03f2, 0x0800},
385 {0x03f3, 0x0800},
386};
387EXPORT_SYMBOL_GPL(rt5682_reg);
388
389bool rt5682_volatile_register(struct device *dev, unsigned int reg)
390{
391 switch (reg) {
392 case RT5682_RESET:
393 case RT5682_CBJ_CTRL_2:
394 case RT5682_INT_ST_1:
395 case RT5682_4BTN_IL_CMD_1:
396 case RT5682_AJD1_CTRL:
397 case RT5682_HP_CALIB_CTRL_1:
398 case RT5682_INT_DEVICE_ID:
399 case RT5682_DEVICE_ID:
400 case RT5682_I2C_MODE:
401 case RT5682_HP_CALIB_CTRL_10:
402 case RT5682_EFUSE_CTRL_2:
403 case RT5682_JD_TOP_VC_VTRL:
404 case RT5682_HP_IMP_SENS_CTRL_19:
405 case RT5682_IL_CMD_1:
406 case RT5682_SAR_IL_CMD_2:
407 case RT5682_SAR_IL_CMD_4:
408 case RT5682_SAR_IL_CMD_10:
409 case RT5682_SAR_IL_CMD_11:
410 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
411 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
412 return true;
413 default:
414 return false;
415 }
416}
417EXPORT_SYMBOL_GPL(rt5682_volatile_register);
418
419bool rt5682_readable_register(struct device *dev, unsigned int reg)
420{
421 switch (reg) {
422 case RT5682_RESET:
423 case RT5682_INT_DEVICE_ID:
424 case RT5682_VERSION_ID:
425 case RT5682_VENDOR_ID:
426 case RT5682_DEVICE_ID:
427 case RT5682_HP_CTRL_1:
428 case RT5682_HP_CTRL_2:
429 case RT5682_HPL_GAIN:
430 case RT5682_HPR_GAIN:
431 case RT5682_I2C_CTRL:
432 case RT5682_CBJ_BST_CTRL:
433 case RT5682_CBJ_CTRL_1:
434 case RT5682_CBJ_CTRL_2:
435 case RT5682_CBJ_CTRL_3:
436 case RT5682_CBJ_CTRL_4:
437 case RT5682_CBJ_CTRL_5:
438 case RT5682_CBJ_CTRL_6:
439 case RT5682_CBJ_CTRL_7:
440 case RT5682_DAC1_DIG_VOL:
441 case RT5682_STO1_ADC_DIG_VOL:
442 case RT5682_STO1_ADC_BOOST:
443 case RT5682_HP_IMP_GAIN_1:
444 case RT5682_HP_IMP_GAIN_2:
445 case RT5682_SIDETONE_CTRL:
446 case RT5682_STO1_ADC_MIXER:
447 case RT5682_AD_DA_MIXER:
448 case RT5682_STO1_DAC_MIXER:
449 case RT5682_A_DAC1_MUX:
450 case RT5682_DIG_INF2_DATA:
451 case RT5682_REC_MIXER:
452 case RT5682_CAL_REC:
453 case RT5682_ALC_BACK_GAIN:
454 case RT5682_PWR_DIG_1:
455 case RT5682_PWR_DIG_2:
456 case RT5682_PWR_ANLG_1:
457 case RT5682_PWR_ANLG_2:
458 case RT5682_PWR_ANLG_3:
459 case RT5682_PWR_MIXER:
460 case RT5682_PWR_VOL:
461 case RT5682_CLK_DET:
462 case RT5682_RESET_LPF_CTRL:
463 case RT5682_RESET_HPF_CTRL:
464 case RT5682_DMIC_CTRL_1:
465 case RT5682_I2S1_SDP:
466 case RT5682_I2S2_SDP:
467 case RT5682_ADDA_CLK_1:
468 case RT5682_ADDA_CLK_2:
469 case RT5682_I2S1_F_DIV_CTRL_1:
470 case RT5682_I2S1_F_DIV_CTRL_2:
471 case RT5682_TDM_CTRL:
472 case RT5682_TDM_ADDA_CTRL_1:
473 case RT5682_TDM_ADDA_CTRL_2:
474 case RT5682_DATA_SEL_CTRL_1:
475 case RT5682_TDM_TCON_CTRL:
476 case RT5682_GLB_CLK:
477 case RT5682_PLL_CTRL_1:
478 case RT5682_PLL_CTRL_2:
479 case RT5682_PLL_TRACK_1:
480 case RT5682_PLL_TRACK_2:
481 case RT5682_PLL_TRACK_3:
482 case RT5682_PLL_TRACK_4:
483 case RT5682_PLL_TRACK_5:
484 case RT5682_PLL_TRACK_6:
485 case RT5682_PLL_TRACK_11:
486 case RT5682_SDW_REF_CLK:
487 case RT5682_DEPOP_1:
488 case RT5682_DEPOP_2:
489 case RT5682_HP_CHARGE_PUMP_1:
490 case RT5682_HP_CHARGE_PUMP_2:
491 case RT5682_MICBIAS_1:
492 case RT5682_MICBIAS_2:
493 case RT5682_PLL_TRACK_12:
494 case RT5682_PLL_TRACK_14:
495 case RT5682_PLL2_CTRL_1:
496 case RT5682_PLL2_CTRL_2:
497 case RT5682_PLL2_CTRL_3:
498 case RT5682_PLL2_CTRL_4:
499 case RT5682_RC_CLK_CTRL:
500 case RT5682_I2S_M_CLK_CTRL_1:
501 case RT5682_I2S2_F_DIV_CTRL_1:
502 case RT5682_I2S2_F_DIV_CTRL_2:
503 case RT5682_EQ_CTRL_1:
504 case RT5682_EQ_CTRL_2:
505 case RT5682_IRQ_CTRL_1:
506 case RT5682_IRQ_CTRL_2:
507 case RT5682_IRQ_CTRL_3:
508 case RT5682_IRQ_CTRL_4:
509 case RT5682_INT_ST_1:
510 case RT5682_GPIO_CTRL_1:
511 case RT5682_GPIO_CTRL_2:
512 case RT5682_GPIO_CTRL_3:
513 case RT5682_HP_AMP_DET_CTRL_1:
514 case RT5682_HP_AMP_DET_CTRL_2:
515 case RT5682_MID_HP_AMP_DET:
516 case RT5682_LOW_HP_AMP_DET:
517 case RT5682_DELAY_BUF_CTRL:
518 case RT5682_SV_ZCD_1:
519 case RT5682_SV_ZCD_2:
520 case RT5682_IL_CMD_1:
521 case RT5682_IL_CMD_2:
522 case RT5682_IL_CMD_3:
523 case RT5682_IL_CMD_4:
524 case RT5682_IL_CMD_5:
525 case RT5682_IL_CMD_6:
526 case RT5682_4BTN_IL_CMD_1:
527 case RT5682_4BTN_IL_CMD_2:
528 case RT5682_4BTN_IL_CMD_3:
529 case RT5682_4BTN_IL_CMD_4:
530 case RT5682_4BTN_IL_CMD_5:
531 case RT5682_4BTN_IL_CMD_6:
532 case RT5682_4BTN_IL_CMD_7:
533 case RT5682_ADC_STO1_HP_CTRL_1:
534 case RT5682_ADC_STO1_HP_CTRL_2:
535 case RT5682_AJD1_CTRL:
536 case RT5682_JD1_THD:
537 case RT5682_JD2_THD:
538 case RT5682_JD_CTRL_1:
539 case RT5682_DUMMY_1:
540 case RT5682_DUMMY_2:
541 case RT5682_DUMMY_3:
542 case RT5682_DAC_ADC_DIG_VOL1:
543 case RT5682_BIAS_CUR_CTRL_2:
544 case RT5682_BIAS_CUR_CTRL_3:
545 case RT5682_BIAS_CUR_CTRL_4:
546 case RT5682_BIAS_CUR_CTRL_5:
547 case RT5682_BIAS_CUR_CTRL_6:
548 case RT5682_BIAS_CUR_CTRL_7:
549 case RT5682_BIAS_CUR_CTRL_8:
550 case RT5682_BIAS_CUR_CTRL_9:
551 case RT5682_BIAS_CUR_CTRL_10:
552 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
553 case RT5682_CHARGE_PUMP_1:
554 case RT5682_DIG_IN_CTRL_1:
555 case RT5682_PAD_DRIVING_CTRL:
556 case RT5682_SOFT_RAMP_DEPOP:
557 case RT5682_CHOP_DAC:
558 case RT5682_CHOP_ADC:
559 case RT5682_CALIB_ADC_CTRL:
560 case RT5682_VOL_TEST:
561 case RT5682_SPKVDD_DET_STA:
562 case RT5682_TEST_MODE_CTRL_1:
563 case RT5682_TEST_MODE_CTRL_2:
564 case RT5682_TEST_MODE_CTRL_3:
565 case RT5682_TEST_MODE_CTRL_4:
566 case RT5682_TEST_MODE_CTRL_5:
567 case RT5682_PLL1_INTERNAL:
568 case RT5682_PLL2_INTERNAL:
569 case RT5682_STO_NG2_CTRL_1:
570 case RT5682_STO_NG2_CTRL_2:
571 case RT5682_STO_NG2_CTRL_3:
572 case RT5682_STO_NG2_CTRL_4:
573 case RT5682_STO_NG2_CTRL_5:
574 case RT5682_STO_NG2_CTRL_6:
575 case RT5682_STO_NG2_CTRL_7:
576 case RT5682_STO_NG2_CTRL_8:
577 case RT5682_STO_NG2_CTRL_9:
578 case RT5682_STO_NG2_CTRL_10:
579 case RT5682_STO1_DAC_SIL_DET:
580 case RT5682_SIL_PSV_CTRL1:
581 case RT5682_SIL_PSV_CTRL2:
582 case RT5682_SIL_PSV_CTRL3:
583 case RT5682_SIL_PSV_CTRL4:
584 case RT5682_SIL_PSV_CTRL5:
585 case RT5682_HP_IMP_SENS_CTRL_01:
586 case RT5682_HP_IMP_SENS_CTRL_02:
587 case RT5682_HP_IMP_SENS_CTRL_03:
588 case RT5682_HP_IMP_SENS_CTRL_04:
589 case RT5682_HP_IMP_SENS_CTRL_05:
590 case RT5682_HP_IMP_SENS_CTRL_06:
591 case RT5682_HP_IMP_SENS_CTRL_07:
592 case RT5682_HP_IMP_SENS_CTRL_08:
593 case RT5682_HP_IMP_SENS_CTRL_09:
594 case RT5682_HP_IMP_SENS_CTRL_10:
595 case RT5682_HP_IMP_SENS_CTRL_11:
596 case RT5682_HP_IMP_SENS_CTRL_12:
597 case RT5682_HP_IMP_SENS_CTRL_13:
598 case RT5682_HP_IMP_SENS_CTRL_14:
599 case RT5682_HP_IMP_SENS_CTRL_15:
600 case RT5682_HP_IMP_SENS_CTRL_16:
601 case RT5682_HP_IMP_SENS_CTRL_17:
602 case RT5682_HP_IMP_SENS_CTRL_18:
603 case RT5682_HP_IMP_SENS_CTRL_19:
604 case RT5682_HP_IMP_SENS_CTRL_20:
605 case RT5682_HP_IMP_SENS_CTRL_21:
606 case RT5682_HP_IMP_SENS_CTRL_22:
607 case RT5682_HP_IMP_SENS_CTRL_23:
608 case RT5682_HP_IMP_SENS_CTRL_24:
609 case RT5682_HP_IMP_SENS_CTRL_25:
610 case RT5682_HP_IMP_SENS_CTRL_26:
611 case RT5682_HP_IMP_SENS_CTRL_27:
612 case RT5682_HP_IMP_SENS_CTRL_28:
613 case RT5682_HP_IMP_SENS_CTRL_29:
614 case RT5682_HP_IMP_SENS_CTRL_30:
615 case RT5682_HP_IMP_SENS_CTRL_31:
616 case RT5682_HP_IMP_SENS_CTRL_32:
617 case RT5682_HP_IMP_SENS_CTRL_33:
618 case RT5682_HP_IMP_SENS_CTRL_34:
619 case RT5682_HP_IMP_SENS_CTRL_35:
620 case RT5682_HP_IMP_SENS_CTRL_36:
621 case RT5682_HP_IMP_SENS_CTRL_37:
622 case RT5682_HP_IMP_SENS_CTRL_38:
623 case RT5682_HP_IMP_SENS_CTRL_39:
624 case RT5682_HP_IMP_SENS_CTRL_40:
625 case RT5682_HP_IMP_SENS_CTRL_41:
626 case RT5682_HP_IMP_SENS_CTRL_42:
627 case RT5682_HP_IMP_SENS_CTRL_43:
628 case RT5682_HP_LOGIC_CTRL_1:
629 case RT5682_HP_LOGIC_CTRL_2:
630 case RT5682_HP_LOGIC_CTRL_3:
631 case RT5682_HP_CALIB_CTRL_1:
632 case RT5682_HP_CALIB_CTRL_2:
633 case RT5682_HP_CALIB_CTRL_3:
634 case RT5682_HP_CALIB_CTRL_4:
635 case RT5682_HP_CALIB_CTRL_5:
636 case RT5682_HP_CALIB_CTRL_6:
637 case RT5682_HP_CALIB_CTRL_7:
638 case RT5682_HP_CALIB_CTRL_9:
639 case RT5682_HP_CALIB_CTRL_10:
640 case RT5682_HP_CALIB_CTRL_11:
641 case RT5682_HP_CALIB_STA_1:
642 case RT5682_HP_CALIB_STA_2:
643 case RT5682_HP_CALIB_STA_3:
644 case RT5682_HP_CALIB_STA_4:
645 case RT5682_HP_CALIB_STA_5:
646 case RT5682_HP_CALIB_STA_6:
647 case RT5682_HP_CALIB_STA_7:
648 case RT5682_HP_CALIB_STA_8:
649 case RT5682_HP_CALIB_STA_9:
650 case RT5682_HP_CALIB_STA_10:
651 case RT5682_HP_CALIB_STA_11:
652 case RT5682_SAR_IL_CMD_1:
653 case RT5682_SAR_IL_CMD_2:
654 case RT5682_SAR_IL_CMD_3:
655 case RT5682_SAR_IL_CMD_4:
656 case RT5682_SAR_IL_CMD_5:
657 case RT5682_SAR_IL_CMD_6:
658 case RT5682_SAR_IL_CMD_7:
659 case RT5682_SAR_IL_CMD_8:
660 case RT5682_SAR_IL_CMD_9:
661 case RT5682_SAR_IL_CMD_10:
662 case RT5682_SAR_IL_CMD_11:
663 case RT5682_SAR_IL_CMD_12:
664 case RT5682_SAR_IL_CMD_13:
665 case RT5682_EFUSE_CTRL_1:
666 case RT5682_EFUSE_CTRL_2:
667 case RT5682_EFUSE_CTRL_3:
668 case RT5682_EFUSE_CTRL_4:
669 case RT5682_EFUSE_CTRL_5:
670 case RT5682_EFUSE_CTRL_6:
671 case RT5682_EFUSE_CTRL_7:
672 case RT5682_EFUSE_CTRL_8:
673 case RT5682_EFUSE_CTRL_9:
674 case RT5682_EFUSE_CTRL_10:
675 case RT5682_EFUSE_CTRL_11:
676 case RT5682_JD_TOP_VC_VTRL:
677 case RT5682_DRC1_CTRL_0:
678 case RT5682_DRC1_CTRL_1:
679 case RT5682_DRC1_CTRL_2:
680 case RT5682_DRC1_CTRL_3:
681 case RT5682_DRC1_CTRL_4:
682 case RT5682_DRC1_CTRL_5:
683 case RT5682_DRC1_CTRL_6:
684 case RT5682_DRC1_HARD_LMT_CTRL_1:
685 case RT5682_DRC1_HARD_LMT_CTRL_2:
686 case RT5682_DRC1_PRIV_1:
687 case RT5682_DRC1_PRIV_2:
688 case RT5682_DRC1_PRIV_3:
689 case RT5682_DRC1_PRIV_4:
690 case RT5682_DRC1_PRIV_5:
691 case RT5682_DRC1_PRIV_6:
692 case RT5682_DRC1_PRIV_7:
693 case RT5682_DRC1_PRIV_8:
694 case RT5682_EQ_AUTO_RCV_CTRL1:
695 case RT5682_EQ_AUTO_RCV_CTRL2:
696 case RT5682_EQ_AUTO_RCV_CTRL3:
697 case RT5682_EQ_AUTO_RCV_CTRL4:
698 case RT5682_EQ_AUTO_RCV_CTRL5:
699 case RT5682_EQ_AUTO_RCV_CTRL6:
700 case RT5682_EQ_AUTO_RCV_CTRL7:
701 case RT5682_EQ_AUTO_RCV_CTRL8:
702 case RT5682_EQ_AUTO_RCV_CTRL9:
703 case RT5682_EQ_AUTO_RCV_CTRL10:
704 case RT5682_EQ_AUTO_RCV_CTRL11:
705 case RT5682_EQ_AUTO_RCV_CTRL12:
706 case RT5682_EQ_AUTO_RCV_CTRL13:
707 case RT5682_ADC_L_EQ_LPF1_A1:
708 case RT5682_R_EQ_LPF1_A1:
709 case RT5682_L_EQ_LPF1_H0:
710 case RT5682_R_EQ_LPF1_H0:
711 case RT5682_L_EQ_BPF1_A1:
712 case RT5682_R_EQ_BPF1_A1:
713 case RT5682_L_EQ_BPF1_A2:
714 case RT5682_R_EQ_BPF1_A2:
715 case RT5682_L_EQ_BPF1_H0:
716 case RT5682_R_EQ_BPF1_H0:
717 case RT5682_L_EQ_BPF2_A1:
718 case RT5682_R_EQ_BPF2_A1:
719 case RT5682_L_EQ_BPF2_A2:
720 case RT5682_R_EQ_BPF2_A2:
721 case RT5682_L_EQ_BPF2_H0:
722 case RT5682_R_EQ_BPF2_H0:
723 case RT5682_L_EQ_BPF3_A1:
724 case RT5682_R_EQ_BPF3_A1:
725 case RT5682_L_EQ_BPF3_A2:
726 case RT5682_R_EQ_BPF3_A2:
727 case RT5682_L_EQ_BPF3_H0:
728 case RT5682_R_EQ_BPF3_H0:
729 case RT5682_L_EQ_BPF4_A1:
730 case RT5682_R_EQ_BPF4_A1:
731 case RT5682_L_EQ_BPF4_A2:
732 case RT5682_R_EQ_BPF4_A2:
733 case RT5682_L_EQ_BPF4_H0:
734 case RT5682_R_EQ_BPF4_H0:
735 case RT5682_L_EQ_HPF1_A1:
736 case RT5682_R_EQ_HPF1_A1:
737 case RT5682_L_EQ_HPF1_H0:
738 case RT5682_R_EQ_HPF1_H0:
739 case RT5682_L_EQ_PRE_VOL:
740 case RT5682_R_EQ_PRE_VOL:
741 case RT5682_L_EQ_POST_VOL:
742 case RT5682_R_EQ_POST_VOL:
743 case RT5682_I2C_MODE:
744 return true;
745 default:
746 return false;
747 }
748}
749EXPORT_SYMBOL_GPL(rt5682_readable_register);
750
751static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
752static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
753static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
754
755/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
756static const DECLARE_TLV_DB_RANGE(bst_tlv,
757 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
758 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
759 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
760 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
761 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
762 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
763 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
764);
765
766/* Interface data select */
767static const char * const rt5682_data_select[] = {
768 "L/R", "R/L", "L/L", "R/R"
769};
770
771static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
772 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
773
774static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
776
777static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
778 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
779
780static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
782
783static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
784 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
785
786static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
787 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
788
789static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
790 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
791
792static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
793 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
794
795static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
796 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
797
798static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
799 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
800
801static const char * const rt5682_dac_select[] = {
802 "IF1", "SOUND"
803};
804
805static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
806 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
807
808static const struct snd_kcontrol_new rt5682_dac_l_mux =
809 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
810
811static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
812 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
813
814static const struct snd_kcontrol_new rt5682_dac_r_mux =
815 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
816
817void rt5682_reset(struct rt5682_priv *rt5682)
818{
819 regmap_write(map: rt5682->regmap, RT5682_RESET, val: 0);
820 if (!rt5682->is_sdw)
821 regmap_write(map: rt5682->regmap, RT5682_I2C_MODE, val: 1);
822}
823EXPORT_SYMBOL_GPL(rt5682_reset);
824
825/**
826 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
827 * @component: SoC audio component device.
828 * @filter_mask: mask of filters.
829 * @clk_src: clock source
830 *
831 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
832 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
833 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
834 * ASRC function will track i2s clock and generate a corresponding system clock
835 * for codec. This function provides an API to select the clock source for a
836 * set of filters specified by the mask. And the component driver will turn on
837 * ASRC for these filters if ASRC is selected as their clock source.
838 */
839int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
840 unsigned int filter_mask, unsigned int clk_src)
841{
842 switch (clk_src) {
843 case RT5682_CLK_SEL_SYS:
844 case RT5682_CLK_SEL_I2S1_ASRC:
845 case RT5682_CLK_SEL_I2S2_ASRC:
846 break;
847
848 default:
849 return -EINVAL;
850 }
851
852 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
853 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
854 RT5682_FILTER_CLK_SEL_MASK,
855 val: clk_src << RT5682_FILTER_CLK_SEL_SFT);
856 }
857
858 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
859 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
860 RT5682_FILTER_CLK_SEL_MASK,
861 val: clk_src << RT5682_FILTER_CLK_SEL_SFT);
862 }
863
864 return 0;
865}
866EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
867
868static int rt5682_button_detect(struct snd_soc_component *component)
869{
870 int btn_type, val;
871
872 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
873 btn_type = val & 0xfff0;
874 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
875 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
876 snd_soc_component_update_bits(component,
877 RT5682_SAR_IL_CMD_2, mask: 0x10, val: 0x10);
878
879 return btn_type;
880}
881
882static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
883 bool enable)
884{
885 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
886
887 if (enable) {
888 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
889 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
890 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
891 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
892 snd_soc_component_write(component, RT5682_IL_CMD_1, val: 0x0040);
893 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
894 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
895 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
896 if (rt5682->is_sdw)
897 snd_soc_component_update_bits(component,
898 RT5682_IRQ_CTRL_3,
899 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
900 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
901 else
902 snd_soc_component_update_bits(component,
903 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
904 RT5682_IL_IRQ_EN);
905 } else {
906 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
907 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
908 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
909 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
910 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
911 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
912 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
913 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
914 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
915 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
916 }
917}
918
919/**
920 * rt5682_headset_detect - Detect headset.
921 * @component: SoC audio component device.
922 * @jack_insert: Jack insert or not.
923 *
924 * Detect whether is headset or not when jack inserted.
925 *
926 * Returns detect status.
927 */
928static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
929{
930 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
931 struct snd_soc_dapm_context *dapm = &component->dapm;
932 unsigned int val, count;
933
934 if (jack_insert) {
935 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
936 RT5682_PWR_VREF2 | RT5682_PWR_MB,
937 RT5682_PWR_VREF2 | RT5682_PWR_MB);
938 snd_soc_component_update_bits(component,
939 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, val: 0);
940 usleep_range(min: 15000, max: 20000);
941 snd_soc_component_update_bits(component,
942 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
943 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
944 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
945 snd_soc_component_update_bits(component,
946 RT5682_HP_CHARGE_PUMP_1,
947 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, val: 0);
948 rt5682_enable_push_button_irq(component, enable: false);
949 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
950 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
951 usleep_range(min: 55000, max: 60000);
952 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
953 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
954
955 count = 0;
956 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
957 & RT5682_JACK_TYPE_MASK;
958 while (val == 0 && count < 50) {
959 usleep_range(min: 10000, max: 15000);
960 val = snd_soc_component_read(component,
961 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
962 count++;
963 }
964
965 switch (val) {
966 case 0x1:
967 case 0x2:
968 rt5682->jack_type = SND_JACK_HEADSET;
969 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
970 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
971 rt5682_enable_push_button_irq(component, enable: true);
972 break;
973 default:
974 rt5682->jack_type = SND_JACK_HEADPHONE;
975 break;
976 }
977
978 snd_soc_component_update_bits(component,
979 RT5682_HP_CHARGE_PUMP_1,
980 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
981 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
982 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
983 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
984 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
985 } else {
986 rt5682_enable_push_button_irq(component, enable: false);
987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
988 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
989 if (!snd_soc_dapm_get_pin_status(dapm, pin: "MICBIAS") &&
990 !snd_soc_dapm_get_pin_status(dapm, pin: "PLL1") &&
991 !snd_soc_dapm_get_pin_status(dapm, pin: "PLL2B"))
992 snd_soc_component_update_bits(component,
993 RT5682_PWR_ANLG_1, RT5682_PWR_MB, val: 0);
994 if (!snd_soc_dapm_get_pin_status(dapm, pin: "Vref2") &&
995 !snd_soc_dapm_get_pin_status(dapm, pin: "PLL1") &&
996 !snd_soc_dapm_get_pin_status(dapm, pin: "PLL2B"))
997 snd_soc_component_update_bits(component,
998 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, val: 0);
999 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
1000 RT5682_PWR_CBJ, val: 0);
1001 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
1002 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1003 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1004 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1005 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1006
1007 rt5682->jack_type = 0;
1008 }
1009
1010 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1011 return rt5682->jack_type;
1012}
1013
1014static int rt5682_set_jack_detect(struct snd_soc_component *component,
1015 struct snd_soc_jack *hs_jack, void *data)
1016{
1017 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
1018
1019 rt5682->hs_jack = hs_jack;
1020
1021 if (rt5682->is_sdw && !rt5682->first_hw_init)
1022 return 0;
1023
1024 if (!hs_jack) {
1025 regmap_update_bits(map: rt5682->regmap, RT5682_IRQ_CTRL_2,
1026 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1027 regmap_update_bits(map: rt5682->regmap, RT5682_RC_CLK_CTRL,
1028 RT5682_POW_JDH | RT5682_POW_JDL, val: 0);
1029 cancel_delayed_work_sync(dwork: &rt5682->jack_detect_work);
1030
1031 return 0;
1032 }
1033
1034 if (!rt5682->is_sdw) {
1035 switch (rt5682->pdata.jd_src) {
1036 case RT5682_JD1:
1037 snd_soc_component_update_bits(component,
1038 RT5682_CBJ_CTRL_5, mask: 0x0700, val: 0x0600);
1039 snd_soc_component_update_bits(component,
1040 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1041 RT5682_EXT_JD_SRC_MANUAL);
1042 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1043 val: 0xd142);
1044 snd_soc_component_update_bits(component,
1045 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1046 RT5682_CBJ_IN_BUF_EN);
1047 snd_soc_component_update_bits(component,
1048 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1049 RT5682_SAR_POW_EN);
1050 regmap_update_bits(map: rt5682->regmap, RT5682_GPIO_CTRL_1,
1051 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1052 regmap_update_bits(map: rt5682->regmap, RT5682_RC_CLK_CTRL,
1053 RT5682_POW_IRQ | RT5682_POW_JDH |
1054 RT5682_POW_ANA, RT5682_POW_IRQ |
1055 RT5682_POW_JDH | RT5682_POW_ANA);
1056 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_ANLG_2,
1057 RT5682_PWR_JDH, RT5682_PWR_JDH);
1058 regmap_update_bits(map: rt5682->regmap, RT5682_IRQ_CTRL_2,
1059 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1060 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1061 regmap_update_bits(map: rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1062 mask: 0x7f7f, val: (rt5682->pdata.btndet_delay << 8 |
1063 rt5682->pdata.btndet_delay));
1064 regmap_update_bits(map: rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1065 mask: 0x7f7f, val: (rt5682->pdata.btndet_delay << 8 |
1066 rt5682->pdata.btndet_delay));
1067 regmap_update_bits(map: rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1068 mask: 0x7f7f, val: (rt5682->pdata.btndet_delay << 8 |
1069 rt5682->pdata.btndet_delay));
1070 regmap_update_bits(map: rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1071 mask: 0x7f7f, val: (rt5682->pdata.btndet_delay << 8 |
1072 rt5682->pdata.btndet_delay));
1073 mod_delayed_work(wq: system_power_efficient_wq,
1074 dwork: &rt5682->jack_detect_work,
1075 delay: msecs_to_jiffies(m: 250));
1076 break;
1077
1078 case RT5682_JD_NULL:
1079 regmap_update_bits(map: rt5682->regmap, RT5682_IRQ_CTRL_2,
1080 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1081 regmap_update_bits(map: rt5682->regmap, RT5682_RC_CLK_CTRL,
1082 RT5682_POW_JDH | RT5682_POW_JDL, val: 0);
1083 break;
1084
1085 default:
1086 dev_warn(component->dev, "Wrong JD source\n");
1087 break;
1088 }
1089 }
1090
1091 return 0;
1092}
1093
1094void rt5682_jack_detect_handler(struct work_struct *work)
1095{
1096 struct rt5682_priv *rt5682 =
1097 container_of(work, struct rt5682_priv, jack_detect_work.work);
1098 struct snd_soc_dapm_context *dapm;
1099 int val, btn_type;
1100
1101 if (!rt5682->component ||
1102 !snd_soc_card_is_instantiated(card: rt5682->component->card)) {
1103 /* card not yet ready, try later */
1104 mod_delayed_work(wq: system_power_efficient_wq,
1105 dwork: &rt5682->jack_detect_work, delay: msecs_to_jiffies(m: 15));
1106 return;
1107 }
1108
1109 if (rt5682->is_sdw) {
1110 if (pm_runtime_status_suspended(dev: rt5682->slave->dev.parent)) {
1111 dev_dbg(&rt5682->slave->dev,
1112 "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
1113 __func__);
1114 return;
1115 }
1116 }
1117
1118 dapm = snd_soc_component_get_dapm(component: rt5682->component);
1119
1120 snd_soc_dapm_mutex_lock(dapm);
1121 mutex_lock(&rt5682->calibrate_mutex);
1122
1123 val = snd_soc_component_read(component: rt5682->component, RT5682_AJD1_CTRL)
1124 & RT5682_JDH_RS_MASK;
1125 if (!val) {
1126 /* jack in */
1127 if (rt5682->jack_type == 0) {
1128 /* jack was out, report jack type */
1129 rt5682->jack_type =
1130 rt5682_headset_detect(component: rt5682->component, jack_insert: 1);
1131 rt5682->irq_work_delay_time = 0;
1132 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1133 SND_JACK_HEADSET) {
1134 /* jack is already in, report button event */
1135 rt5682->jack_type = SND_JACK_HEADSET;
1136 btn_type = rt5682_button_detect(component: rt5682->component);
1137 /**
1138 * rt5682 can report three kinds of button behavior,
1139 * one click, double click and hold. However,
1140 * currently we will report button pressed/released
1141 * event. So all the three button behaviors are
1142 * treated as button pressed.
1143 */
1144 switch (btn_type) {
1145 case 0x8000:
1146 case 0x4000:
1147 case 0x2000:
1148 rt5682->jack_type |= SND_JACK_BTN_0;
1149 break;
1150 case 0x1000:
1151 case 0x0800:
1152 case 0x0400:
1153 rt5682->jack_type |= SND_JACK_BTN_1;
1154 break;
1155 case 0x0200:
1156 case 0x0100:
1157 case 0x0080:
1158 rt5682->jack_type |= SND_JACK_BTN_2;
1159 break;
1160 case 0x0040:
1161 case 0x0020:
1162 case 0x0010:
1163 rt5682->jack_type |= SND_JACK_BTN_3;
1164 break;
1165 case 0x0000: /* unpressed */
1166 break;
1167 default:
1168 dev_err(rt5682->component->dev,
1169 "Unexpected button code 0x%04x\n",
1170 btn_type);
1171 break;
1172 }
1173 }
1174 } else {
1175 /* jack out */
1176 rt5682->jack_type = rt5682_headset_detect(component: rt5682->component, jack_insert: 0);
1177 rt5682->irq_work_delay_time = 50;
1178 }
1179
1180 mutex_unlock(lock: &rt5682->calibrate_mutex);
1181 snd_soc_dapm_mutex_unlock(dapm);
1182
1183 snd_soc_jack_report(jack: rt5682->hs_jack, status: rt5682->jack_type,
1184 mask: SND_JACK_HEADSET |
1185 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1186 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1187
1188 if (!rt5682->is_sdw) {
1189 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1190 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1191 schedule_delayed_work(dwork: &rt5682->jd_check_work, delay: 0);
1192 else
1193 cancel_delayed_work_sync(dwork: &rt5682->jd_check_work);
1194 }
1195}
1196EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1197
1198static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1199 /* DAC Digital Volume */
1200 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1201 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1202
1203 /* IN Boost Volume */
1204 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1205 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1206
1207 /* ADC Digital Volume Control */
1208 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1209 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1210 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1211 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1212
1213 /* ADC Boost Volume Control */
1214 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1215 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1216 3, 0, adc_bst_tlv),
1217};
1218
1219static int rt5682_div_sel(struct rt5682_priv *rt5682,
1220 int target, const int div[], int size)
1221{
1222 int i;
1223
1224 if (rt5682->sysclk < target) {
1225 dev_err(rt5682->component->dev,
1226 "sysclk rate %d is too low\n", rt5682->sysclk);
1227 return 0;
1228 }
1229
1230 for (i = 0; i < size - 1; i++) {
1231 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1232 if (target * div[i] == rt5682->sysclk)
1233 return i;
1234 if (target * div[i + 1] > rt5682->sysclk) {
1235 dev_dbg(rt5682->component->dev,
1236 "can't find div for sysclk %d\n",
1237 rt5682->sysclk);
1238 return i;
1239 }
1240 }
1241
1242 if (target * div[i] < rt5682->sysclk)
1243 dev_err(rt5682->component->dev,
1244 "sysclk rate %d is too high\n", rt5682->sysclk);
1245
1246 return size - 1;
1247}
1248
1249/**
1250 * set_dmic_clk - Set parameter of dmic.
1251 *
1252 * @w: DAPM widget.
1253 * @kcontrol: The kcontrol of this widget.
1254 * @event: Event id.
1255 *
1256 * Choose dmic clock between 1MHz and 3MHz.
1257 * It is better for clock to approximate 3MHz.
1258 */
1259static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1260 struct snd_kcontrol *kcontrol, int event)
1261{
1262 struct snd_soc_component *component =
1263 snd_soc_dapm_to_component(dapm: w->dapm);
1264 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
1265 int idx, dmic_clk_rate = 3072000;
1266 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1267
1268 if (rt5682->pdata.dmic_clk_rate)
1269 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1270
1271 idx = rt5682_div_sel(rt5682, target: dmic_clk_rate, div, ARRAY_SIZE(div));
1272
1273 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1274 RT5682_DMIC_CLK_MASK, val: idx << RT5682_DMIC_CLK_SFT);
1275
1276 return 0;
1277}
1278
1279static int set_filter_clk(struct snd_soc_dapm_widget *w,
1280 struct snd_kcontrol *kcontrol, int event)
1281{
1282 struct snd_soc_component *component =
1283 snd_soc_dapm_to_component(dapm: w->dapm);
1284 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
1285 int ref, val, reg, idx;
1286 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1287 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1288
1289 if (rt5682->is_sdw)
1290 return 0;
1291
1292 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1293 RT5682_GP4_PIN_MASK;
1294 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1295 val == RT5682_GP4_PIN_ADCDAT2)
1296 ref = 256 * rt5682->lrck[RT5682_AIF2];
1297 else
1298 ref = 256 * rt5682->lrck[RT5682_AIF1];
1299
1300 idx = rt5682_div_sel(rt5682, target: ref, div: div_f, ARRAY_SIZE(div_f));
1301
1302 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1303 reg = RT5682_PLL_TRACK_3;
1304 else
1305 reg = RT5682_PLL_TRACK_2;
1306
1307 snd_soc_component_update_bits(component, reg,
1308 RT5682_FILTER_CLK_DIV_MASK, val: idx << RT5682_FILTER_CLK_DIV_SFT);
1309
1310 /* select over sample rate */
1311 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1312 if (rt5682->sysclk <= 12288000 * div_o[idx])
1313 break;
1314 }
1315
1316 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1317 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1318 val: (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1319
1320 return 0;
1321}
1322
1323static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1324 struct snd_soc_dapm_widget *sink)
1325{
1326 unsigned int val;
1327 struct snd_soc_component *component =
1328 snd_soc_dapm_to_component(dapm: w->dapm);
1329
1330 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1331 val &= RT5682_SCLK_SRC_MASK;
1332 if (val == RT5682_SCLK_SRC_PLL1)
1333 return 1;
1334 else
1335 return 0;
1336}
1337
1338static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1339 struct snd_soc_dapm_widget *sink)
1340{
1341 unsigned int val;
1342 struct snd_soc_component *component =
1343 snd_soc_dapm_to_component(dapm: w->dapm);
1344
1345 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1346 val &= RT5682_SCLK_SRC_MASK;
1347 if (val == RT5682_SCLK_SRC_PLL2)
1348 return 1;
1349 else
1350 return 0;
1351}
1352
1353static int is_using_asrc(struct snd_soc_dapm_widget *w,
1354 struct snd_soc_dapm_widget *sink)
1355{
1356 unsigned int reg, shift, val;
1357 struct snd_soc_component *component =
1358 snd_soc_dapm_to_component(dapm: w->dapm);
1359
1360 switch (w->shift) {
1361 case RT5682_ADC_STO1_ASRC_SFT:
1362 reg = RT5682_PLL_TRACK_3;
1363 shift = RT5682_FILTER_CLK_SEL_SFT;
1364 break;
1365 case RT5682_DAC_STO1_ASRC_SFT:
1366 reg = RT5682_PLL_TRACK_2;
1367 shift = RT5682_FILTER_CLK_SEL_SFT;
1368 break;
1369 default:
1370 return 0;
1371 }
1372
1373 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1374 switch (val) {
1375 case RT5682_CLK_SEL_I2S1_ASRC:
1376 case RT5682_CLK_SEL_I2S2_ASRC:
1377 return 1;
1378 default:
1379 return 0;
1380 }
1381}
1382
1383/* Digital Mixer */
1384static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1385 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1386 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1387 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1388 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1389};
1390
1391static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1392 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1393 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1394 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1395 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1396};
1397
1398static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1399 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1400 RT5682_M_ADCMIX_L_SFT, 1, 1),
1401 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1402 RT5682_M_DAC1_L_SFT, 1, 1),
1403};
1404
1405static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1406 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1407 RT5682_M_ADCMIX_R_SFT, 1, 1),
1408 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1409 RT5682_M_DAC1_R_SFT, 1, 1),
1410};
1411
1412static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1413 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1414 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1415 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1416 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1417};
1418
1419static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1420 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1421 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1422 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1423 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1424};
1425
1426/* Analog Input Mixer */
1427static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1428 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1429 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1430};
1431
1432/* STO1 ADC1 Source */
1433/* MX-26 [13] [5] */
1434static const char * const rt5682_sto1_adc1_src[] = {
1435 "DAC MIX", "ADC"
1436};
1437
1438static SOC_ENUM_SINGLE_DECL(
1439 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1440 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1441
1442static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1443 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1444
1445static SOC_ENUM_SINGLE_DECL(
1446 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1447 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1448
1449static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1450 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1451
1452/* STO1 ADC Source */
1453/* MX-26 [11:10] [3:2] */
1454static const char * const rt5682_sto1_adc_src[] = {
1455 "ADC1 L", "ADC1 R"
1456};
1457
1458static SOC_ENUM_SINGLE_DECL(
1459 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1460 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1461
1462static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1463 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1464
1465static SOC_ENUM_SINGLE_DECL(
1466 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1467 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1468
1469static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1470 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1471
1472/* STO1 ADC2 Source */
1473/* MX-26 [12] [4] */
1474static const char * const rt5682_sto1_adc2_src[] = {
1475 "DAC MIX", "DMIC"
1476};
1477
1478static SOC_ENUM_SINGLE_DECL(
1479 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1480 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1481
1482static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1483 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1484
1485static SOC_ENUM_SINGLE_DECL(
1486 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1487 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1488
1489static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1490 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1491
1492/* MX-79 [6:4] I2S1 ADC data location */
1493static const unsigned int rt5682_if1_adc_slot_values[] = {
1494 0,
1495 2,
1496 4,
1497 6,
1498};
1499
1500static const char * const rt5682_if1_adc_slot_src[] = {
1501 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1502};
1503
1504static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1505 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1506 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1507
1508static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1509 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1510
1511/* Analog DAC L1 Source, Analog DAC R1 Source*/
1512/* MX-2B [4], MX-2B [0]*/
1513static const char * const rt5682_alg_dac1_src[] = {
1514 "Stereo1 DAC Mixer", "DAC1"
1515};
1516
1517static SOC_ENUM_SINGLE_DECL(
1518 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1519 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1520
1521static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1522 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1523
1524static SOC_ENUM_SINGLE_DECL(
1525 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1526 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1527
1528static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1529 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1530
1531/* Out Switch */
1532static const struct snd_kcontrol_new hpol_switch =
1533 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1534 RT5682_L_MUTE_SFT, 1, 1);
1535static const struct snd_kcontrol_new hpor_switch =
1536 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1537 RT5682_R_MUTE_SFT, 1, 1);
1538
1539static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1540 struct snd_kcontrol *kcontrol, int event)
1541{
1542 struct snd_soc_component *component =
1543 snd_soc_dapm_to_component(dapm: w->dapm);
1544
1545 switch (event) {
1546 case SND_SOC_DAPM_PRE_PMU:
1547 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1548 RT5682_HP_C2_DAC_AMP_MUTE, val: 0);
1549 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1550 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1551 snd_soc_component_update_bits(component,
1552 RT5682_DEPOP_1, mask: 0x60, val: 0x60);
1553 snd_soc_component_update_bits(component,
1554 RT5682_DAC_ADC_DIG_VOL1, mask: 0x00c0, val: 0x0080);
1555 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1556 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1557 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1558 usleep_range(min: 5000, max: 10000);
1559 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1560 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1561 break;
1562
1563 case SND_SOC_DAPM_POST_PMD:
1564 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1565 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, val: 0);
1566 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1567 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1568 snd_soc_component_update_bits(component,
1569 RT5682_DEPOP_1, mask: 0x60, val: 0x0);
1570 snd_soc_component_update_bits(component,
1571 RT5682_DAC_ADC_DIG_VOL1, mask: 0x00c0, val: 0x0000);
1572 break;
1573 }
1574
1575 return 0;
1576}
1577
1578static int set_dmic_power(struct snd_soc_dapm_widget *w,
1579 struct snd_kcontrol *kcontrol, int event)
1580{
1581 struct snd_soc_component *component =
1582 snd_soc_dapm_to_component(dapm: w->dapm);
1583 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
1584 unsigned int delay = 50, val;
1585
1586 if (rt5682->pdata.dmic_delay)
1587 delay = rt5682->pdata.dmic_delay;
1588
1589 switch (event) {
1590 case SND_SOC_DAPM_POST_PMU:
1591 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1592 val &= RT5682_SCLK_SRC_MASK;
1593 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1594 snd_soc_component_update_bits(component,
1595 RT5682_PWR_ANLG_1,
1596 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1597 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1598
1599 /*Add delay to avoid pop noise*/
1600 msleep(msecs: delay);
1601 break;
1602
1603 case SND_SOC_DAPM_POST_PMD:
1604 if (!rt5682->jack_type) {
1605 if (!snd_soc_dapm_get_pin_status(dapm: w->dapm, pin: "MICBIAS"))
1606 snd_soc_component_update_bits(component,
1607 RT5682_PWR_ANLG_1, RT5682_PWR_MB, val: 0);
1608 if (!snd_soc_dapm_get_pin_status(dapm: w->dapm, pin: "Vref2"))
1609 snd_soc_component_update_bits(component,
1610 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, val: 0);
1611 }
1612 break;
1613 }
1614
1615 return 0;
1616}
1617
1618static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1619 struct snd_kcontrol *kcontrol, int event)
1620{
1621 struct snd_soc_component *component =
1622 snd_soc_dapm_to_component(dapm: w->dapm);
1623
1624 switch (event) {
1625 case SND_SOC_DAPM_PRE_PMU:
1626 switch (w->shift) {
1627 case RT5682_PWR_VREF1_BIT:
1628 snd_soc_component_update_bits(component,
1629 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, val: 0);
1630 break;
1631
1632 case RT5682_PWR_VREF2_BIT:
1633 snd_soc_component_update_bits(component,
1634 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, val: 0);
1635 break;
1636 }
1637 break;
1638
1639 case SND_SOC_DAPM_POST_PMU:
1640 usleep_range(min: 15000, max: 20000);
1641 switch (w->shift) {
1642 case RT5682_PWR_VREF1_BIT:
1643 snd_soc_component_update_bits(component,
1644 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1645 RT5682_PWR_FV1);
1646 break;
1647
1648 case RT5682_PWR_VREF2_BIT:
1649 snd_soc_component_update_bits(component,
1650 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1651 RT5682_PWR_FV2);
1652 break;
1653 }
1654 break;
1655 }
1656
1657 return 0;
1658}
1659
1660static const unsigned int rt5682_adcdat_pin_values[] = {
1661 1,
1662 3,
1663};
1664
1665static const char * const rt5682_adcdat_pin_select[] = {
1666 "ADCDAT1",
1667 "ADCDAT2",
1668};
1669
1670static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1671 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1672 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1673
1674static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1675 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1676
1677static const unsigned int rt5682_hpo_sig_out_values[] = {
1678 2,
1679 7,
1680};
1681
1682static const char * const rt5682_hpo_sig_out_mode[] = {
1683 "Legacy",
1684 "OneBit",
1685};
1686
1687static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1688 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1689 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1690
1691static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1692 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1693
1694static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1695 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1696 0, NULL, 0),
1697 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1698 0, NULL, 0),
1699 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1700 0, NULL, 0),
1701 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1702 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1703 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1704 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1705 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1706 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1707
1708 /* ASRC */
1709 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1710 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1711 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1712 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1714 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1715 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1716 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1717 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1718 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1719
1720 /* Input Side */
1721 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1722 0, NULL, 0),
1723 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1724 0, NULL, 0),
1725
1726 /* Input Lines */
1727 SND_SOC_DAPM_INPUT("DMIC L1"),
1728 SND_SOC_DAPM_INPUT("DMIC R1"),
1729
1730 SND_SOC_DAPM_INPUT("IN1P"),
1731
1732 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1733 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1734 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1735 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1736 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1737
1738 /* Boost */
1739 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1740 0, 0, NULL, 0),
1741
1742 /* REC Mixer */
1743 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1744 ARRAY_SIZE(rt5682_rec1_l_mix)),
1745 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1746 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1747
1748 /* ADCs */
1749 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1750 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1751
1752 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1753 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1754 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1755 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1756 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1757 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1758
1759 /* ADC Mux */
1760 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5682_sto1_adc1l_mux),
1762 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5682_sto1_adc1r_mux),
1764 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5682_sto1_adc2l_mux),
1766 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5682_sto1_adc2r_mux),
1768 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5682_sto1_adcl_mux),
1770 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1771 &rt5682_sto1_adcr_mux),
1772 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5682_if1_adc_slot_mux),
1774
1775 /* ADC Mixer */
1776 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1777 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1778 SND_SOC_DAPM_PRE_PMU),
1779 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1780 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1781 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1782 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1783 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1784 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1785
1786 /* ADC PGA */
1787 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1788
1789 /* Digital Interface */
1790 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1791 0, NULL, 0),
1792 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1793 0, NULL, 0),
1794 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1795 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1796 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1797 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1798 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1799
1800 /* Digital Interface Select */
1801 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1802 &rt5682_if1_01_adc_swap_mux),
1803 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1804 &rt5682_if1_23_adc_swap_mux),
1805 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1806 &rt5682_if1_45_adc_swap_mux),
1807 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1808 &rt5682_if1_67_adc_swap_mux),
1809 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1810 &rt5682_if2_adc_swap_mux),
1811
1812 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1813 &rt5682_adcdat_pin_ctrl),
1814
1815 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1816 &rt5682_dac_l_mux),
1817 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1818 &rt5682_dac_r_mux),
1819
1820 /* Audio Interface */
1821 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1822 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1823 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1824 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1825 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1826 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1827 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1828
1829 /* Output Side */
1830 /* DAC mixer before sound effect */
1831 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1832 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1833 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1834 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1835
1836 /* DAC channel Mux */
1837 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1838 &rt5682_alg_dac_l1_mux),
1839 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1840 &rt5682_alg_dac_r1_mux),
1841
1842 /* DAC Mixer */
1843 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1844 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1845 SND_SOC_DAPM_PRE_PMU),
1846 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1847 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1848 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1849 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1850
1851 /* DACs */
1852 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1853 RT5682_PWR_DAC_L1_BIT, 0),
1854 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1855 RT5682_PWR_DAC_R1_BIT, 0),
1856 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1857 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1858
1859 /* HPO */
1860 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1861 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1862
1863 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1864 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1865 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1866 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1867 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1868 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1869 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1870 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1871
1872 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1873 &hpol_switch),
1874 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1875 &hpor_switch),
1876
1877 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1880
1881 /* CLK DET */
1882 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1883 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1884 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1885 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1886 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1887 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1888 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1889 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1890
1891 /* Output Lines */
1892 SND_SOC_DAPM_OUTPUT("HPOL"),
1893 SND_SOC_DAPM_OUTPUT("HPOR"),
1894};
1895
1896static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1897 /*PLL*/
1898 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1899 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1900 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1901 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1902 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1903 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1904
1905 /*ASRC*/
1906 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1907 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1908 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1909 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1910 {"ADC STO1 ASRC", NULL, "CLKDET"},
1911 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1912 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1913 {"DAC STO1 ASRC", NULL, "CLKDET"},
1914
1915 /*Vref*/
1916 {"MICBIAS1", NULL, "Vref1"},
1917 {"MICBIAS2", NULL, "Vref1"},
1918
1919 {"CLKDET SYS", NULL, "CLKDET"},
1920
1921 {"BST1 CBJ", NULL, "IN1P"},
1922
1923 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1924 {"RECMIX1L", NULL, "RECMIX1L Power"},
1925
1926 {"ADC1 L", NULL, "RECMIX1L"},
1927 {"ADC1 L", NULL, "ADC1 L Power"},
1928 {"ADC1 L", NULL, "ADC1 clock"},
1929
1930 {"DMIC L1", NULL, "DMIC CLK"},
1931 {"DMIC L1", NULL, "DMIC1 Power"},
1932 {"DMIC R1", NULL, "DMIC CLK"},
1933 {"DMIC R1", NULL, "DMIC1 Power"},
1934 {"DMIC CLK", NULL, "DMIC ASRC"},
1935
1936 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1937 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1938 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1939 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1940
1941 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1942 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1943 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1944 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1945
1946 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1947 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1948 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1949 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1950
1951 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1952 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1953 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1954
1955 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1956 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1957 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1958
1959 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1960 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1961
1962 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1963 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1964 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1965 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1966 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1967 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1968 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1969 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1970 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1971 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1972 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1973 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1974 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1975 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1976 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1977 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1978
1979 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1980 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1981 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1982 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1983 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1984 {"AIF1TX", NULL, "I2S1"},
1985 {"AIF1TX", NULL, "ADCDAT Mux"},
1986 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1987 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1988 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1989 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1990 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1991 {"AIF2TX", NULL, "ADCDAT Mux"},
1992
1993 {"SDWTX", NULL, "PLL2B"},
1994 {"SDWTX", NULL, "PLL2F"},
1995 {"SDWTX", NULL, "ADCDAT Mux"},
1996
1997 {"IF1 DAC1 L", NULL, "AIF1RX"},
1998 {"IF1 DAC1 L", NULL, "I2S1"},
1999 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
2000 {"IF1 DAC1 R", NULL, "AIF1RX"},
2001 {"IF1 DAC1 R", NULL, "I2S1"},
2002 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
2003
2004 {"SOUND DAC L", NULL, "SDWRX"},
2005 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
2006 {"SOUND DAC L", NULL, "PLL2B"},
2007 {"SOUND DAC L", NULL, "PLL2F"},
2008 {"SOUND DAC R", NULL, "SDWRX"},
2009 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
2010 {"SOUND DAC R", NULL, "PLL2B"},
2011 {"SOUND DAC R", NULL, "PLL2F"},
2012
2013 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
2014 {"DAC L Mux", "SOUND", "SOUND DAC L"},
2015 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2016 {"DAC R Mux", "SOUND", "SOUND DAC R"},
2017
2018 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2019 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2020 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2021 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2022
2023 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2024 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2025
2026 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2027 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2028
2029 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2030 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2031 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2032 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2033
2034 {"DAC L1", NULL, "DAC L1 Source"},
2035 {"DAC R1", NULL, "DAC R1 Source"},
2036
2037 {"DAC L1", NULL, "DAC 1 Clock"},
2038 {"DAC R1", NULL, "DAC 1 Clock"},
2039
2040 {"HP Amp", NULL, "DAC L1"},
2041 {"HP Amp", NULL, "DAC R1"},
2042 {"HP Amp", NULL, "HP Amp L"},
2043 {"HP Amp", NULL, "HP Amp R"},
2044 {"HP Amp", NULL, "Capless"},
2045 {"HP Amp", NULL, "Charge Pump"},
2046 {"HP Amp", NULL, "CLKDET SYS"},
2047 {"HP Amp", NULL, "Vref1"},
2048
2049 {"HPO Signal Demux", NULL, "HP Amp"},
2050
2051 {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2052 {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2053
2054 {"HPOL Playback", "Switch", "HPO Legacy"},
2055 {"HPOR Playback", "Switch", "HPO Legacy"},
2056
2057 {"HPOL", NULL, "HPOL Playback"},
2058 {"HPOR", NULL, "HPOR Playback"},
2059 {"HPOL", NULL, "HPO OneBit"},
2060 {"HPOR", NULL, "HPO OneBit"},
2061};
2062
2063static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2064 unsigned int rx_mask, int slots, int slot_width)
2065{
2066 struct snd_soc_component *component = dai->component;
2067 unsigned int cl, val = 0;
2068
2069 if (tx_mask || rx_mask)
2070 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2071 RT5682_TDM_EN, RT5682_TDM_EN);
2072 else
2073 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2074 RT5682_TDM_EN, val: 0);
2075
2076 switch (slots) {
2077 case 4:
2078 val |= RT5682_TDM_TX_CH_4;
2079 val |= RT5682_TDM_RX_CH_4;
2080 break;
2081 case 6:
2082 val |= RT5682_TDM_TX_CH_6;
2083 val |= RT5682_TDM_RX_CH_6;
2084 break;
2085 case 8:
2086 val |= RT5682_TDM_TX_CH_8;
2087 val |= RT5682_TDM_RX_CH_8;
2088 break;
2089 case 2:
2090 break;
2091 default:
2092 return -EINVAL;
2093 }
2094
2095 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2096 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2097
2098 switch (slot_width) {
2099 case 8:
2100 if (tx_mask || rx_mask)
2101 return -EINVAL;
2102 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2103 break;
2104 case 16:
2105 val = RT5682_TDM_CL_16;
2106 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2107 break;
2108 case 20:
2109 val = RT5682_TDM_CL_20;
2110 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2111 break;
2112 case 24:
2113 val = RT5682_TDM_CL_24;
2114 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2115 break;
2116 case 32:
2117 val = RT5682_TDM_CL_32;
2118 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2119 break;
2120 default:
2121 return -EINVAL;
2122 }
2123
2124 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2125 RT5682_TDM_CL_MASK, val);
2126 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2127 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, val: cl);
2128
2129 return 0;
2130}
2131
2132static int rt5682_hw_params(struct snd_pcm_substream *substream,
2133 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2134{
2135 struct snd_soc_component *component = dai->component;
2136 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2137 unsigned int len_1 = 0, len_2 = 0;
2138 int pre_div, frame_size;
2139
2140 rt5682->lrck[dai->id] = params_rate(p: params);
2141 pre_div = rl6231_get_clk_info(sclk: rt5682->sysclk, rate: rt5682->lrck[dai->id]);
2142
2143 frame_size = snd_soc_params_to_frame_size(params);
2144 if (frame_size < 0) {
2145 dev_err(component->dev, "Unsupported frame size: %d\n",
2146 frame_size);
2147 return -EINVAL;
2148 }
2149
2150 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2151 rt5682->lrck[dai->id], pre_div, dai->id);
2152
2153 switch (params_width(p: params)) {
2154 case 16:
2155 break;
2156 case 20:
2157 len_1 |= RT5682_I2S1_DL_20;
2158 len_2 |= RT5682_I2S2_DL_20;
2159 break;
2160 case 24:
2161 len_1 |= RT5682_I2S1_DL_24;
2162 len_2 |= RT5682_I2S2_DL_24;
2163 break;
2164 case 32:
2165 len_1 |= RT5682_I2S1_DL_32;
2166 len_2 |= RT5682_I2S2_DL_24;
2167 break;
2168 case 8:
2169 len_1 |= RT5682_I2S2_DL_8;
2170 len_2 |= RT5682_I2S2_DL_8;
2171 break;
2172 default:
2173 return -EINVAL;
2174 }
2175
2176 switch (dai->id) {
2177 case RT5682_AIF1:
2178 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2179 RT5682_I2S1_DL_MASK, val: len_1);
2180 if (rt5682->master[RT5682_AIF1]) {
2181 snd_soc_component_update_bits(component,
2182 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2183 RT5682_I2S_CLK_SRC_MASK,
2184 val: pre_div << RT5682_I2S_M_DIV_SFT |
2185 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2186 }
2187 if (params_channels(p: params) == 1) /* mono mode */
2188 snd_soc_component_update_bits(component,
2189 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2190 RT5682_I2S1_MONO_EN);
2191 else
2192 snd_soc_component_update_bits(component,
2193 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2194 RT5682_I2S1_MONO_DIS);
2195 break;
2196 case RT5682_AIF2:
2197 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2198 RT5682_I2S2_DL_MASK, val: len_2);
2199 if (rt5682->master[RT5682_AIF2]) {
2200 snd_soc_component_update_bits(component,
2201 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2202 val: pre_div << RT5682_I2S2_M_PD_SFT);
2203 }
2204 if (params_channels(p: params) == 1) /* mono mode */
2205 snd_soc_component_update_bits(component,
2206 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2207 RT5682_I2S2_MONO_EN);
2208 else
2209 snd_soc_component_update_bits(component,
2210 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2211 RT5682_I2S2_MONO_DIS);
2212 break;
2213 default:
2214 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2215 return -EINVAL;
2216 }
2217
2218 return 0;
2219}
2220
2221static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2222{
2223 struct snd_soc_component *component = dai->component;
2224 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2225 unsigned int reg_val = 0, tdm_ctrl = 0;
2226
2227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2228 case SND_SOC_DAIFMT_CBP_CFP:
2229 rt5682->master[dai->id] = 1;
2230 break;
2231 case SND_SOC_DAIFMT_CBC_CFC:
2232 rt5682->master[dai->id] = 0;
2233 break;
2234 default:
2235 return -EINVAL;
2236 }
2237
2238 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2239 case SND_SOC_DAIFMT_NB_NF:
2240 break;
2241 case SND_SOC_DAIFMT_IB_NF:
2242 reg_val |= RT5682_I2S_BP_INV;
2243 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2244 break;
2245 case SND_SOC_DAIFMT_NB_IF:
2246 if (dai->id == RT5682_AIF1)
2247 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2248 else
2249 return -EINVAL;
2250 break;
2251 case SND_SOC_DAIFMT_IB_IF:
2252 if (dai->id == RT5682_AIF1)
2253 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2254 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2255 else
2256 return -EINVAL;
2257 break;
2258 default:
2259 return -EINVAL;
2260 }
2261
2262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2263 case SND_SOC_DAIFMT_I2S:
2264 break;
2265 case SND_SOC_DAIFMT_LEFT_J:
2266 reg_val |= RT5682_I2S_DF_LEFT;
2267 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2268 break;
2269 case SND_SOC_DAIFMT_DSP_A:
2270 reg_val |= RT5682_I2S_DF_PCM_A;
2271 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2272 break;
2273 case SND_SOC_DAIFMT_DSP_B:
2274 reg_val |= RT5682_I2S_DF_PCM_B;
2275 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2276 break;
2277 default:
2278 return -EINVAL;
2279 }
2280
2281 switch (dai->id) {
2282 case RT5682_AIF1:
2283 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2284 RT5682_I2S_DF_MASK, val: reg_val);
2285 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2286 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2287 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2288 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2289 val: tdm_ctrl | rt5682->master[dai->id]);
2290 break;
2291 case RT5682_AIF2:
2292 if (rt5682->master[dai->id] == 0)
2293 reg_val |= RT5682_I2S2_MS_S;
2294 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2295 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2296 RT5682_I2S_DF_MASK, val: reg_val);
2297 break;
2298 default:
2299 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2300 return -EINVAL;
2301 }
2302 return 0;
2303}
2304
2305static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2306 int clk_id, int source, unsigned int freq, int dir)
2307{
2308 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2309 unsigned int reg_val = 0, src = 0;
2310
2311 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2312 return 0;
2313
2314 switch (clk_id) {
2315 case RT5682_SCLK_S_MCLK:
2316 reg_val |= RT5682_SCLK_SRC_MCLK;
2317 src = RT5682_CLK_SRC_MCLK;
2318 break;
2319 case RT5682_SCLK_S_PLL1:
2320 reg_val |= RT5682_SCLK_SRC_PLL1;
2321 src = RT5682_CLK_SRC_PLL1;
2322 break;
2323 case RT5682_SCLK_S_PLL2:
2324 reg_val |= RT5682_SCLK_SRC_PLL2;
2325 src = RT5682_CLK_SRC_PLL2;
2326 break;
2327 case RT5682_SCLK_S_RCCLK:
2328 reg_val |= RT5682_SCLK_SRC_RCCLK;
2329 src = RT5682_CLK_SRC_RCCLK;
2330 break;
2331 default:
2332 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2333 return -EINVAL;
2334 }
2335 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2336 RT5682_SCLK_SRC_MASK, val: reg_val);
2337
2338 if (rt5682->master[RT5682_AIF2]) {
2339 snd_soc_component_update_bits(component,
2340 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2341 val: src << RT5682_I2S2_SRC_SFT);
2342 }
2343
2344 rt5682->sysclk = freq;
2345 rt5682->sysclk_src = clk_id;
2346
2347 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2348 freq, clk_id);
2349
2350 return 0;
2351}
2352
2353static int rt5682_set_component_pll(struct snd_soc_component *component,
2354 int pll_id, int source, unsigned int freq_in,
2355 unsigned int freq_out)
2356{
2357 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2358 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2359 unsigned int pll2_fout1, pll2_ps_val;
2360 int ret;
2361
2362 if (source == rt5682->pll_src[pll_id] &&
2363 freq_in == rt5682->pll_in[pll_id] &&
2364 freq_out == rt5682->pll_out[pll_id])
2365 return 0;
2366
2367 if (!freq_in || !freq_out) {
2368 dev_dbg(component->dev, "PLL disabled\n");
2369
2370 rt5682->pll_in[pll_id] = 0;
2371 rt5682->pll_out[pll_id] = 0;
2372 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2373 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2374 return 0;
2375 }
2376
2377 if (pll_id == RT5682_PLL2) {
2378 switch (source) {
2379 case RT5682_PLL2_S_MCLK:
2380 snd_soc_component_update_bits(component,
2381 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2382 RT5682_PLL2_SRC_MCLK);
2383 break;
2384 default:
2385 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2386 source);
2387 return -EINVAL;
2388 }
2389
2390 /**
2391 * PLL2 concatenates 2 PLL units.
2392 * We suggest the Fout of the front PLL is 3.84MHz.
2393 */
2394 pll2_fout1 = 3840000;
2395 ret = rl6231_pll_calc(freq_in, freq_out: pll2_fout1, pll_code: &pll2f_code);
2396 if (ret < 0) {
2397 dev_err(component->dev, "Unsupported input clock %d\n",
2398 freq_in);
2399 return ret;
2400 }
2401 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2402 freq_in, pll2_fout1,
2403 pll2f_code.m_bp,
2404 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2405 pll2f_code.n_code, pll2f_code.k_code);
2406
2407 ret = rl6231_pll_calc(freq_in: pll2_fout1, freq_out, pll_code: &pll2b_code);
2408 if (ret < 0) {
2409 dev_err(component->dev, "Unsupported input clock %d\n",
2410 pll2_fout1);
2411 return ret;
2412 }
2413 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2414 pll2_fout1, freq_out,
2415 pll2b_code.m_bp,
2416 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2417 pll2b_code.n_code, pll2b_code.k_code);
2418
2419 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2420 val: pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2421 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2422 pll2b_code.m_code);
2423 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2424 val: pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2425 pll2b_code.n_code);
2426 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2427 val: pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2428
2429 if (freq_out == 22579200)
2430 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2431 else
2432 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2433 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2434 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2435 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2436 val: pll2_ps_val |
2437 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2438 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2439 0xf);
2440 } else {
2441 switch (source) {
2442 case RT5682_PLL1_S_MCLK:
2443 snd_soc_component_update_bits(component,
2444 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2445 RT5682_PLL1_SRC_MCLK);
2446 break;
2447 case RT5682_PLL1_S_BCLK1:
2448 snd_soc_component_update_bits(component,
2449 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2450 RT5682_PLL1_SRC_BCLK1);
2451 break;
2452 default:
2453 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2454 source);
2455 return -EINVAL;
2456 }
2457
2458 ret = rl6231_pll_calc(freq_in, freq_out, pll_code: &pll_code);
2459 if (ret < 0) {
2460 dev_err(component->dev, "Unsupported input clock %d\n",
2461 freq_in);
2462 return ret;
2463 }
2464
2465 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2466 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2467 pll_code.n_code, pll_code.k_code);
2468
2469 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2470 val: (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2471 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2472 val: ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2473 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2474 }
2475
2476 rt5682->pll_in[pll_id] = freq_in;
2477 rt5682->pll_out[pll_id] = freq_out;
2478 rt5682->pll_src[pll_id] = source;
2479
2480 return 0;
2481}
2482
2483static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2484{
2485 struct snd_soc_component *component = dai->component;
2486 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2487
2488 rt5682->bclk[dai->id] = ratio;
2489
2490 switch (ratio) {
2491 case 256:
2492 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2493 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2494 break;
2495 case 128:
2496 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2497 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2498 break;
2499 case 64:
2500 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2501 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2502 break;
2503 case 32:
2504 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2505 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2506 break;
2507 default:
2508 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2509 return -EINVAL;
2510 }
2511
2512 return 0;
2513}
2514
2515static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2516{
2517 struct snd_soc_component *component = dai->component;
2518 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2519
2520 rt5682->bclk[dai->id] = ratio;
2521
2522 switch (ratio) {
2523 case 64:
2524 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2525 RT5682_I2S2_BCLK_MS2_MASK,
2526 RT5682_I2S2_BCLK_MS2_64);
2527 break;
2528 case 32:
2529 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2530 RT5682_I2S2_BCLK_MS2_MASK,
2531 RT5682_I2S2_BCLK_MS2_32);
2532 break;
2533 default:
2534 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2535 return -EINVAL;
2536 }
2537
2538 return 0;
2539}
2540
2541static int rt5682_set_bias_level(struct snd_soc_component *component,
2542 enum snd_soc_bias_level level)
2543{
2544 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2545
2546 switch (level) {
2547 case SND_SOC_BIAS_PREPARE:
2548 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_ANLG_1,
2549 RT5682_PWR_BG, RT5682_PWR_BG);
2550 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_DIG_1,
2551 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2552 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2553 break;
2554
2555 case SND_SOC_BIAS_STANDBY:
2556 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_DIG_1,
2557 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2558 break;
2559 case SND_SOC_BIAS_OFF:
2560 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_DIG_1,
2561 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, val: 0);
2562 regmap_update_bits(map: rt5682->regmap, RT5682_PWR_ANLG_1,
2563 RT5682_PWR_BG, val: 0);
2564 break;
2565 case SND_SOC_BIAS_ON:
2566 break;
2567 }
2568
2569 return 0;
2570}
2571
2572#ifdef CONFIG_COMMON_CLK
2573#define CLK_PLL2_FIN 48000000
2574#define CLK_48 48000
2575#define CLK_44 44100
2576
2577static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2578{
2579 if (!rt5682->master[RT5682_AIF1]) {
2580 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2581 return false;
2582 }
2583 return true;
2584}
2585
2586static int rt5682_wclk_prepare(struct clk_hw *hw)
2587{
2588 struct rt5682_priv *rt5682 =
2589 container_of(hw, struct rt5682_priv,
2590 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2591 struct snd_soc_component *component;
2592 struct snd_soc_dapm_context *dapm;
2593
2594 if (!rt5682_clk_check(rt5682))
2595 return -EINVAL;
2596
2597 component = rt5682->component;
2598 dapm = snd_soc_component_get_dapm(component);
2599
2600 snd_soc_dapm_mutex_lock(dapm);
2601
2602 snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "MICBIAS");
2603 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2604 RT5682_PWR_MB, RT5682_PWR_MB);
2605
2606 snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "Vref2");
2607 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2608 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2609 RT5682_PWR_VREF2);
2610 usleep_range(min: 55000, max: 60000);
2611 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2612 RT5682_PWR_FV2, RT5682_PWR_FV2);
2613
2614 snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "I2S1");
2615 snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "PLL2F");
2616 snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "PLL2B");
2617 snd_soc_dapm_sync_unlocked(dapm);
2618
2619 snd_soc_dapm_mutex_unlock(dapm);
2620
2621 return 0;
2622}
2623
2624static void rt5682_wclk_unprepare(struct clk_hw *hw)
2625{
2626 struct rt5682_priv *rt5682 =
2627 container_of(hw, struct rt5682_priv,
2628 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2629 struct snd_soc_component *component;
2630 struct snd_soc_dapm_context *dapm;
2631
2632 if (!rt5682_clk_check(rt5682))
2633 return;
2634
2635 component = rt5682->component;
2636 dapm = snd_soc_component_get_dapm(component);
2637
2638 snd_soc_dapm_mutex_lock(dapm);
2639
2640 snd_soc_dapm_disable_pin_unlocked(dapm, pin: "MICBIAS");
2641 snd_soc_dapm_disable_pin_unlocked(dapm, pin: "Vref2");
2642 if (!rt5682->jack_type)
2643 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2644 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2645 RT5682_PWR_MB, val: 0);
2646
2647 snd_soc_dapm_disable_pin_unlocked(dapm, pin: "I2S1");
2648 snd_soc_dapm_disable_pin_unlocked(dapm, pin: "PLL2F");
2649 snd_soc_dapm_disable_pin_unlocked(dapm, pin: "PLL2B");
2650 snd_soc_dapm_sync_unlocked(dapm);
2651
2652 snd_soc_dapm_mutex_unlock(dapm);
2653}
2654
2655static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2656 unsigned long parent_rate)
2657{
2658 struct rt5682_priv *rt5682 =
2659 container_of(hw, struct rt5682_priv,
2660 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2661 const char * const clk_name = clk_hw_get_name(hw);
2662
2663 if (!rt5682_clk_check(rt5682))
2664 return 0;
2665 /*
2666 * Only accept to set wclk rate to 44.1k or 48kHz.
2667 */
2668 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2669 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2670 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2671 __func__, clk_name, CLK_44, CLK_48);
2672 return 0;
2673 }
2674
2675 return rt5682->lrck[RT5682_AIF1];
2676}
2677
2678static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2679 unsigned long *parent_rate)
2680{
2681 struct rt5682_priv *rt5682 =
2682 container_of(hw, struct rt5682_priv,
2683 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2684 const char * const clk_name = clk_hw_get_name(hw);
2685
2686 if (!rt5682_clk_check(rt5682))
2687 return -EINVAL;
2688 /*
2689 * Only accept to set wclk rate to 44.1k or 48kHz.
2690 * It will force to 48kHz if not both.
2691 */
2692 if (rate != CLK_48 && rate != CLK_44) {
2693 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2694 __func__, clk_name, CLK_44, CLK_48);
2695 rate = CLK_48;
2696 }
2697
2698 return rate;
2699}
2700
2701static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2702 unsigned long parent_rate)
2703{
2704 struct rt5682_priv *rt5682 =
2705 container_of(hw, struct rt5682_priv,
2706 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2707 struct snd_soc_component *component;
2708 struct clk_hw *parent_hw;
2709 const char * const clk_name = clk_hw_get_name(hw);
2710 int pre_div;
2711 unsigned int clk_pll2_out;
2712
2713 if (!rt5682_clk_check(rt5682))
2714 return -EINVAL;
2715
2716 component = rt5682->component;
2717
2718 /*
2719 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2720 * it is fixed or set to 48MHz before setting wclk rate. It's a
2721 * temporary limitation. Only accept 48MHz clk as the clk provider.
2722 *
2723 * It will set the codec anyway by assuming mclk is 48MHz.
2724 */
2725 parent_hw = clk_hw_get_parent(hw);
2726 if (!parent_hw)
2727 dev_warn(rt5682->i2c_dev,
2728 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2729 CLK_PLL2_FIN);
2730
2731 if (parent_rate != CLK_PLL2_FIN)
2732 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2733 clk_name, CLK_PLL2_FIN);
2734
2735 /*
2736 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2737 * PLL2 is needed.
2738 */
2739 clk_pll2_out = rate * 512;
2740 rt5682_set_component_pll(component, pll_id: RT5682_PLL2, source: RT5682_PLL2_S_MCLK,
2741 CLK_PLL2_FIN, freq_out: clk_pll2_out);
2742
2743 rt5682_set_component_sysclk(component, clk_id: RT5682_SCLK_S_PLL2, source: 0,
2744 freq: clk_pll2_out, SND_SOC_CLOCK_IN);
2745
2746 rt5682->lrck[RT5682_AIF1] = rate;
2747
2748 pre_div = rl6231_get_clk_info(sclk: rt5682->sysclk, rate);
2749
2750 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2751 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2752 val: pre_div << RT5682_I2S_M_DIV_SFT |
2753 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2754
2755 return 0;
2756}
2757
2758static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2759 unsigned long parent_rate)
2760{
2761 struct rt5682_priv *rt5682 =
2762 container_of(hw, struct rt5682_priv,
2763 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2764 unsigned int bclks_per_wclk;
2765
2766 regmap_read(map: rt5682->regmap, RT5682_TDM_TCON_CTRL, val: &bclks_per_wclk);
2767
2768 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2769 case RT5682_TDM_BCLK_MS1_256:
2770 return parent_rate * 256;
2771 case RT5682_TDM_BCLK_MS1_128:
2772 return parent_rate * 128;
2773 case RT5682_TDM_BCLK_MS1_64:
2774 return parent_rate * 64;
2775 case RT5682_TDM_BCLK_MS1_32:
2776 return parent_rate * 32;
2777 default:
2778 return 0;
2779 }
2780}
2781
2782static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2783 unsigned long parent_rate)
2784{
2785 unsigned long factor;
2786
2787 factor = rate / parent_rate;
2788 if (factor < 64)
2789 return 32;
2790 else if (factor < 128)
2791 return 64;
2792 else if (factor < 256)
2793 return 128;
2794 else
2795 return 256;
2796}
2797
2798static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2799 unsigned long *parent_rate)
2800{
2801 struct rt5682_priv *rt5682 =
2802 container_of(hw, struct rt5682_priv,
2803 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2804 unsigned long factor;
2805
2806 if (!*parent_rate || !rt5682_clk_check(rt5682))
2807 return -EINVAL;
2808
2809 /*
2810 * BCLK rates are set as a multiplier of WCLK in HW.
2811 * We don't allow changing the parent WCLK. We just do
2812 * some rounding down based on the parent WCLK rate
2813 * and find the appropriate multiplier of BCLK to
2814 * get the rounded down BCLK value.
2815 */
2816 factor = rt5682_bclk_get_factor(rate, parent_rate: *parent_rate);
2817
2818 return *parent_rate * factor;
2819}
2820
2821static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2822 unsigned long parent_rate)
2823{
2824 struct rt5682_priv *rt5682 =
2825 container_of(hw, struct rt5682_priv,
2826 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2827 struct snd_soc_component *component;
2828 struct snd_soc_dai *dai;
2829 unsigned long factor;
2830
2831 if (!rt5682_clk_check(rt5682))
2832 return -EINVAL;
2833
2834 component = rt5682->component;
2835
2836 factor = rt5682_bclk_get_factor(rate, parent_rate);
2837
2838 for_each_component_dais(component, dai)
2839 if (dai->id == RT5682_AIF1)
2840 return rt5682_set_bclk1_ratio(dai, ratio: factor);
2841
2842 dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2843 RT5682_AIF1);
2844 return -ENODEV;
2845}
2846
2847static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2848 [RT5682_DAI_WCLK_IDX] = {
2849 .prepare = rt5682_wclk_prepare,
2850 .unprepare = rt5682_wclk_unprepare,
2851 .recalc_rate = rt5682_wclk_recalc_rate,
2852 .round_rate = rt5682_wclk_round_rate,
2853 .set_rate = rt5682_wclk_set_rate,
2854 },
2855 [RT5682_DAI_BCLK_IDX] = {
2856 .recalc_rate = rt5682_bclk_recalc_rate,
2857 .round_rate = rt5682_bclk_round_rate,
2858 .set_rate = rt5682_bclk_set_rate,
2859 },
2860};
2861
2862int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2863{
2864 struct device *dev = rt5682->i2c_dev;
2865 struct rt5682_platform_data *pdata = &rt5682->pdata;
2866 struct clk_hw *dai_clk_hw;
2867 int i, ret;
2868
2869 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2870 struct clk_init_data init = { };
2871 const struct clk_hw *parent;
2872
2873 dai_clk_hw = &rt5682->dai_clks_hw[i];
2874
2875 switch (i) {
2876 case RT5682_DAI_WCLK_IDX:
2877 /* Make MCLK the parent of WCLK */
2878 if (rt5682->mclk) {
2879 parent = __clk_get_hw(clk: rt5682->mclk);
2880 init.parent_hws = &parent;
2881 init.num_parents = 1;
2882 }
2883 break;
2884 case RT5682_DAI_BCLK_IDX:
2885 /* Make WCLK the parent of BCLK */
2886 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2887 init.parent_hws = &parent;
2888 init.num_parents = 1;
2889 break;
2890 default:
2891 dev_err(dev, "Invalid clock index\n");
2892 return -EINVAL;
2893 }
2894
2895 init.name = pdata->dai_clk_names[i];
2896 init.ops = &rt5682_dai_clk_ops[i];
2897 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2898 dai_clk_hw->init = &init;
2899
2900 ret = devm_clk_hw_register(dev, hw: dai_clk_hw);
2901 if (ret) {
2902 dev_warn(dev, "Failed to register %s: %d\n",
2903 init.name, ret);
2904 return ret;
2905 }
2906
2907 if (dev->of_node) {
2908 ret = devm_of_clk_add_hw_provider(dev, get: of_clk_hw_simple_get,
2909 data: dai_clk_hw);
2910 if (ret)
2911 return ret;
2912 } else {
2913 ret = devm_clk_hw_register_clkdev(dev, hw: dai_clk_hw,
2914 con_id: init.name,
2915 dev_id: dev_name(dev));
2916 if (ret)
2917 return ret;
2918 }
2919 }
2920
2921 return 0;
2922}
2923EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2924#endif /* CONFIG_COMMON_CLK */
2925
2926static int rt5682_probe(struct snd_soc_component *component)
2927{
2928 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2929 struct sdw_slave *slave;
2930 unsigned long time;
2931 struct snd_soc_dapm_context *dapm = &component->dapm;
2932
2933 rt5682->component = component;
2934
2935 if (rt5682->is_sdw) {
2936 slave = rt5682->slave;
2937 time = wait_for_completion_timeout(
2938 x: &slave->initialization_complete,
2939 timeout: msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2940 if (!time) {
2941 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2942 return -ETIMEDOUT;
2943 }
2944 }
2945
2946 snd_soc_dapm_disable_pin(dapm, pin: "MICBIAS");
2947 snd_soc_dapm_disable_pin(dapm, pin: "Vref2");
2948 snd_soc_dapm_sync(dapm);
2949 return 0;
2950}
2951
2952static void rt5682_remove(struct snd_soc_component *component)
2953{
2954 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2955
2956 rt5682_reset(rt5682);
2957}
2958
2959#ifdef CONFIG_PM
2960static int rt5682_suspend(struct snd_soc_component *component)
2961{
2962 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
2963 unsigned int val;
2964
2965 if (rt5682->is_sdw)
2966 return 0;
2967
2968 if (rt5682->irq)
2969 disable_irq(irq: rt5682->irq);
2970
2971 cancel_delayed_work_sync(dwork: &rt5682->jack_detect_work);
2972 cancel_delayed_work_sync(dwork: &rt5682->jd_check_work);
2973 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2974 val = snd_soc_component_read(component,
2975 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2976
2977 switch (val) {
2978 case 0x1:
2979 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2980 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2981 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2982 break;
2983 case 0x2:
2984 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2985 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2986 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2987 break;
2988 default:
2989 break;
2990 }
2991
2992 /* enter SAR ADC power saving mode */
2993 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2994 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2995 RT5682_SAR_SEL_MB1_MB2_MASK, val: 0);
2996 usleep_range(min: 5000, max: 6000);
2997 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2998 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2999 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
3000 usleep_range(min: 10000, max: 12000);
3001 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3002 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
3003 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
3004 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
3005 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, val: 0);
3006 }
3007
3008 regcache_cache_only(map: rt5682->regmap, enable: true);
3009 regcache_mark_dirty(map: rt5682->regmap);
3010 return 0;
3011}
3012
3013static int rt5682_resume(struct snd_soc_component *component)
3014{
3015 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(c: component);
3016
3017 if (rt5682->is_sdw)
3018 return 0;
3019
3020 regcache_cache_only(map: rt5682->regmap, enable: false);
3021 regcache_sync(map: rt5682->regmap);
3022
3023 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3024 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3025 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3026 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3027 usleep_range(min: 5000, max: 6000);
3028 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3029 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3030 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3031 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3032 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3033 }
3034
3035 rt5682->jack_type = 0;
3036 mod_delayed_work(wq: system_power_efficient_wq,
3037 dwork: &rt5682->jack_detect_work, delay: msecs_to_jiffies(m: 0));
3038
3039 if (rt5682->irq)
3040 enable_irq(irq: rt5682->irq);
3041
3042 return 0;
3043}
3044#else
3045#define rt5682_suspend NULL
3046#define rt5682_resume NULL
3047#endif
3048
3049const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3050 .hw_params = rt5682_hw_params,
3051 .set_fmt = rt5682_set_dai_fmt,
3052 .set_tdm_slot = rt5682_set_tdm_slot,
3053 .set_bclk_ratio = rt5682_set_bclk1_ratio,
3054};
3055EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3056
3057const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3058 .hw_params = rt5682_hw_params,
3059 .set_fmt = rt5682_set_dai_fmt,
3060 .set_bclk_ratio = rt5682_set_bclk2_ratio,
3061};
3062EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3063
3064const struct snd_soc_component_driver rt5682_soc_component_dev = {
3065 .probe = rt5682_probe,
3066 .remove = rt5682_remove,
3067 .suspend = rt5682_suspend,
3068 .resume = rt5682_resume,
3069 .set_bias_level = rt5682_set_bias_level,
3070 .controls = rt5682_snd_controls,
3071 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3072 .dapm_widgets = rt5682_dapm_widgets,
3073 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3074 .dapm_routes = rt5682_dapm_routes,
3075 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3076 .set_sysclk = rt5682_set_component_sysclk,
3077 .set_pll = rt5682_set_component_pll,
3078 .set_jack = rt5682_set_jack_detect,
3079 .use_pmdown_time = 1,
3080 .endianness = 1,
3081};
3082EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3083
3084int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3085{
3086
3087 device_property_read_u32(dev, propname: "realtek,dmic1-data-pin",
3088 val: &rt5682->pdata.dmic1_data_pin);
3089 device_property_read_u32(dev, propname: "realtek,dmic1-clk-pin",
3090 val: &rt5682->pdata.dmic1_clk_pin);
3091 device_property_read_u32(dev, propname: "realtek,jd-src",
3092 val: &rt5682->pdata.jd_src);
3093 device_property_read_u32(dev, propname: "realtek,btndet-delay",
3094 val: &rt5682->pdata.btndet_delay);
3095 device_property_read_u32(dev, propname: "realtek,dmic-clk-rate-hz",
3096 val: &rt5682->pdata.dmic_clk_rate);
3097 device_property_read_u32(dev, propname: "realtek,dmic-delay-ms",
3098 val: &rt5682->pdata.dmic_delay);
3099
3100 if (device_property_read_string_array(dev, propname: "clock-output-names",
3101 val: rt5682->pdata.dai_clk_names,
3102 nval: RT5682_DAI_NUM_CLKS) < 0)
3103 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3104 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3105 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3106
3107 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3108 propname: "realtek,dmic-clk-driving-high");
3109
3110 return 0;
3111}
3112EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3113
3114int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev)
3115{
3116 rt5682->ldo1_en = devm_gpiod_get_optional(dev,
3117 con_id: "realtek,ldo1-en",
3118 flags: GPIOD_OUT_HIGH);
3119 if (IS_ERR(ptr: rt5682->ldo1_en)) {
3120 dev_err(dev, "Fail gpio request ldo1_en\n");
3121 return PTR_ERR(ptr: rt5682->ldo1_en);
3122 }
3123
3124 return 0;
3125}
3126EXPORT_SYMBOL_GPL(rt5682_get_ldo1);
3127
3128void rt5682_calibrate(struct rt5682_priv *rt5682)
3129{
3130 int value, count;
3131
3132 mutex_lock(&rt5682->calibrate_mutex);
3133
3134 rt5682_reset(rt5682);
3135 regmap_write(map: rt5682->regmap, RT5682_I2C_CTRL, val: 0x000f);
3136 regmap_write(map: rt5682->regmap, RT5682_PWR_ANLG_1, val: 0xa2af);
3137 usleep_range(min: 15000, max: 20000);
3138 regmap_write(map: rt5682->regmap, RT5682_PWR_ANLG_1, val: 0xf2af);
3139 regmap_write(map: rt5682->regmap, RT5682_MICBIAS_2, val: 0x0300);
3140 regmap_write(map: rt5682->regmap, RT5682_GLB_CLK, val: 0x8000);
3141 regmap_write(map: rt5682->regmap, RT5682_PWR_DIG_1, val: 0x0100);
3142 regmap_write(map: rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, val: 0x3800);
3143 regmap_write(map: rt5682->regmap, RT5682_CHOP_DAC, val: 0x3000);
3144 if (rt5682->ve_ic)
3145 regmap_write(map: rt5682->regmap, RT5682_CHOP_ADC, val: 0x7005);
3146 else
3147 regmap_write(map: rt5682->regmap, RT5682_CALIB_ADC_CTRL, val: 0x7005);
3148 regmap_write(map: rt5682->regmap, RT5682_STO1_ADC_MIXER, val: 0x686c);
3149 regmap_write(map: rt5682->regmap, RT5682_CAL_REC, val: 0x0d0d);
3150 regmap_write(map: rt5682->regmap, RT5682_HP_CALIB_CTRL_2, val: 0x0321);
3151 regmap_write(map: rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, val: 0x0004);
3152 regmap_write(map: rt5682->regmap, RT5682_HP_CALIB_CTRL_1, val: 0x7c00);
3153 regmap_write(map: rt5682->regmap, RT5682_HP_CALIB_CTRL_3, val: 0x06a1);
3154 regmap_write(map: rt5682->regmap, RT5682_A_DAC1_MUX, val: 0x0311);
3155 regmap_write(map: rt5682->regmap, RT5682_HP_CALIB_CTRL_1, val: 0x7c00);
3156
3157 regmap_write(map: rt5682->regmap, RT5682_HP_CALIB_CTRL_1, val: 0xfc00);
3158
3159 for (count = 0; count < 60; count++) {
3160 regmap_read(map: rt5682->regmap, RT5682_HP_CALIB_STA_1, val: &value);
3161 if (!(value & 0x8000))
3162 break;
3163
3164 usleep_range(min: 10000, max: 10005);
3165 }
3166
3167 if (count >= 60)
3168 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3169
3170 /* restore settings */
3171 regmap_write(map: rt5682->regmap, RT5682_PWR_ANLG_1, val: 0x002f);
3172 regmap_write(map: rt5682->regmap, RT5682_MICBIAS_2, val: 0x0080);
3173 regmap_write(map: rt5682->regmap, RT5682_GLB_CLK, val: 0x0000);
3174 regmap_write(map: rt5682->regmap, RT5682_PWR_DIG_1, val: 0x0000);
3175 regmap_write(map: rt5682->regmap, RT5682_CHOP_DAC, val: 0x2000);
3176 if (rt5682->ve_ic)
3177 regmap_write(map: rt5682->regmap, RT5682_CHOP_ADC, val: 0x2005);
3178 else
3179 regmap_write(map: rt5682->regmap, RT5682_CALIB_ADC_CTRL, val: 0x2005);
3180 regmap_write(map: rt5682->regmap, RT5682_STO1_ADC_MIXER, val: 0xc0c4);
3181 regmap_write(map: rt5682->regmap, RT5682_CAL_REC, val: 0x0c0c);
3182
3183 mutex_unlock(lock: &rt5682->calibrate_mutex);
3184}
3185EXPORT_SYMBOL_GPL(rt5682_calibrate);
3186
3187MODULE_DESCRIPTION("ASoC RT5682 driver");
3188MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3189MODULE_LICENSE("GPL v2");
3190

source code of linux/sound/soc/codecs/rt5682.c