1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved. |
4 | * |
5 | * lpass.h - Definitions for the QTi LPASS |
6 | */ |
7 | |
8 | #ifndef __LPASS_H__ |
9 | #define __LPASS_H__ |
10 | |
11 | #include <linux/clk.h> |
12 | #include <linux/compiler.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/regmap.h> |
15 | #include <dt-bindings/sound/qcom,lpass.h> |
16 | #include "lpass-hdmi.h" |
17 | |
18 | #define LPASS_AHBIX_CLOCK_FREQUENCY 131072000 |
19 | #define LPASS_MAX_PORTS (LPASS_CDC_DMA_VA_TX8 + 1) |
20 | #define LPASS_MAX_MI2S_PORTS (8) |
21 | #define LPASS_MAX_DMA_CHANNELS (8) |
22 | #define LPASS_MAX_HDMI_DMA_CHANNELS (4) |
23 | #define LPASS_MAX_CDC_DMA_CHANNELS (8) |
24 | #define LPASS_MAX_VA_CDC_DMA_CHANNELS (8) |
25 | #define LPASS_CDC_DMA_INTF_ONE_CHANNEL (0x01) |
26 | #define LPASS_CDC_DMA_INTF_TWO_CHANNEL (0x03) |
27 | #define LPASS_CDC_DMA_INTF_FOUR_CHANNEL (0x0F) |
28 | #define LPASS_CDC_DMA_INTF_SIX_CHANNEL (0x3F) |
29 | #define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL (0xFF) |
30 | |
31 | #define LPASS_ACTIVE_PDS (4) |
32 | #define LPASS_PROXY_PDS (8) |
33 | |
34 | #define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf) \ |
35 | do { \ |
36 | mf = devm_regmap_field_alloc(d, m, f); \ |
37 | if (IS_ERR(mf)) \ |
38 | return -EINVAL; \ |
39 | } while (0) |
40 | |
41 | static inline bool is_cdc_dma_port(int dai_id) |
42 | { |
43 | switch (dai_id) { |
44 | case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: |
45 | case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: |
46 | case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8: |
47 | return true; |
48 | } |
49 | return false; |
50 | } |
51 | |
52 | static inline bool is_rxtx_cdc_dma_port(int dai_id) |
53 | { |
54 | switch (dai_id) { |
55 | case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9: |
56 | case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8: |
57 | return true; |
58 | } |
59 | return false; |
60 | } |
61 | |
62 | struct lpaif_i2sctl { |
63 | struct regmap_field *loopback; |
64 | struct regmap_field *spken; |
65 | struct regmap_field *spkmode; |
66 | struct regmap_field *spkmono; |
67 | struct regmap_field *micen; |
68 | struct regmap_field *micmode; |
69 | struct regmap_field *micmono; |
70 | struct regmap_field *wssrc; |
71 | struct regmap_field *bitwidth; |
72 | }; |
73 | |
74 | |
75 | struct lpaif_dmactl { |
76 | struct regmap_field *intf; |
77 | struct regmap_field *bursten; |
78 | struct regmap_field *wpscnt; |
79 | struct regmap_field *fifowm; |
80 | struct regmap_field *enable; |
81 | struct regmap_field *dyncclk; |
82 | struct regmap_field *burst8; |
83 | struct regmap_field *burst16; |
84 | struct regmap_field *dynburst; |
85 | struct regmap_field *codec_enable; |
86 | struct regmap_field *codec_pack; |
87 | struct regmap_field *codec_intf; |
88 | struct regmap_field *codec_fs_sel; |
89 | struct regmap_field *codec_channel; |
90 | struct regmap_field *codec_fs_delay; |
91 | }; |
92 | |
93 | /* Both the CPU DAI and platform drivers will access this data */ |
94 | struct lpass_data { |
95 | |
96 | /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */ |
97 | struct clk *ahbix_clk; |
98 | |
99 | /* MI2S system clock */ |
100 | struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS]; |
101 | |
102 | /* MI2S bit clock (derived from system clock by a divider */ |
103 | struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS]; |
104 | |
105 | struct clk *codec_mem0; |
106 | struct clk *codec_mem1; |
107 | struct clk *codec_mem2; |
108 | struct clk *va_mem0; |
109 | |
110 | /* MI2S SD lines to use for playback/capture */ |
111 | unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS]; |
112 | unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS]; |
113 | |
114 | /* The state of MI2S prepare dai_ops was called */ |
115 | bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS]; |
116 | |
117 | int hdmi_port_enable; |
118 | int codec_dma_enable; |
119 | |
120 | /* low-power audio interface (LPAIF) registers */ |
121 | void __iomem *lpaif; |
122 | void __iomem *hdmiif; |
123 | void __iomem *rxtx_lpaif; |
124 | void __iomem *va_lpaif; |
125 | |
126 | u32 rxtx_cdc_dma_lpm_buf; |
127 | u32 va_cdc_dma_lpm_buf; |
128 | |
129 | /* regmap backed by the low-power audio interface (LPAIF) registers */ |
130 | struct regmap *lpaif_map; |
131 | struct regmap *hdmiif_map; |
132 | struct regmap *rxtx_lpaif_map; |
133 | struct regmap *va_lpaif_map; |
134 | |
135 | /* interrupts from the low-power audio interface (LPAIF) */ |
136 | int lpaif_irq; |
137 | int hdmiif_irq; |
138 | int rxtxif_irq; |
139 | int vaif_irq; |
140 | |
141 | /* SOC specific variations in the LPASS IP integration */ |
142 | const struct lpass_variant *variant; |
143 | |
144 | /* bit map to keep track of static channel allocations */ |
145 | unsigned long dma_ch_bit_map; |
146 | unsigned long hdmi_dma_ch_bit_map; |
147 | unsigned long rxtx_dma_ch_bit_map; |
148 | unsigned long va_dma_ch_bit_map; |
149 | |
150 | /* used it for handling interrupt per dma channel */ |
151 | struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS]; |
152 | struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS]; |
153 | struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS]; |
154 | struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS]; |
155 | |
156 | /* SOC specific clock list */ |
157 | struct clk_bulk_data *clks; |
158 | int num_clks; |
159 | |
160 | /* Regmap fields of I2SCTL & DMACTL registers bitfields */ |
161 | struct lpaif_i2sctl *i2sctl; |
162 | struct lpaif_dmactl *rd_dmactl; |
163 | struct lpaif_dmactl *wr_dmactl; |
164 | struct lpaif_dmactl *hdmi_rd_dmactl; |
165 | |
166 | /* Regmap fields of CODEC DMA CTRL registers */ |
167 | struct lpaif_dmactl *rxtx_rd_dmactl; |
168 | struct lpaif_dmactl *rxtx_wr_dmactl; |
169 | struct lpaif_dmactl *va_wr_dmactl; |
170 | |
171 | /* Regmap fields of HDMI_CTRL registers*/ |
172 | struct regmap_field *hdmitx_legacy_en; |
173 | struct regmap_field *hdmitx_parity_calc_en; |
174 | struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS]; |
175 | struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS]; |
176 | struct lpass_hdmi_tx_ctl *tx_ctl; |
177 | struct lpass_vbit_ctrl *vbit_ctl; |
178 | struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS]; |
179 | struct lpass_dp_metadata_ctl *meta_ctl; |
180 | struct lpass_sstream_ctl *sstream_ctl; |
181 | }; |
182 | |
183 | /* Vairant data per each SOC */ |
184 | struct lpass_variant { |
185 | u32 irq_reg_base; |
186 | u32 irq_reg_stride; |
187 | u32 irq_ports; |
188 | u32 rdma_reg_base; |
189 | u32 rdma_reg_stride; |
190 | u32 rdma_channels; |
191 | u32 hdmi_rdma_reg_base; |
192 | u32 hdmi_rdma_reg_stride; |
193 | u32 hdmi_rdma_channels; |
194 | u32 wrdma_reg_base; |
195 | u32 wrdma_reg_stride; |
196 | u32 wrdma_channels; |
197 | u32 rxtx_irq_reg_base; |
198 | u32 rxtx_irq_reg_stride; |
199 | u32 rxtx_irq_ports; |
200 | u32 rxtx_rdma_reg_base; |
201 | u32 rxtx_rdma_reg_stride; |
202 | u32 rxtx_rdma_channels; |
203 | u32 rxtx_wrdma_reg_base; |
204 | u32 rxtx_wrdma_reg_stride; |
205 | u32 rxtx_wrdma_channels; |
206 | u32 va_irq_reg_base; |
207 | u32 va_irq_reg_stride; |
208 | u32 va_irq_ports; |
209 | u32 va_rdma_reg_base; |
210 | u32 va_rdma_reg_stride; |
211 | u32 va_rdma_channels; |
212 | u32 va_wrdma_reg_base; |
213 | u32 va_wrdma_reg_stride; |
214 | u32 va_wrdma_channels; |
215 | u32 i2sctrl_reg_base; |
216 | u32 i2sctrl_reg_stride; |
217 | u32 i2s_ports; |
218 | |
219 | /* I2SCTL Register fields */ |
220 | struct reg_field loopback; |
221 | struct reg_field spken; |
222 | struct reg_field spkmode; |
223 | struct reg_field spkmono; |
224 | struct reg_field micen; |
225 | struct reg_field micmode; |
226 | struct reg_field micmono; |
227 | struct reg_field wssrc; |
228 | struct reg_field bitwidth; |
229 | |
230 | u32 hdmi_irq_reg_base; |
231 | u32 hdmi_irq_reg_stride; |
232 | u32 hdmi_irq_ports; |
233 | |
234 | /* HDMI specific controls */ |
235 | u32 hdmi_tx_ctl_addr; |
236 | u32 hdmi_legacy_addr; |
237 | u32 hdmi_vbit_addr; |
238 | u32 hdmi_ch_lsb_addr; |
239 | u32 hdmi_ch_msb_addr; |
240 | u32 ch_stride; |
241 | u32 hdmi_parity_addr; |
242 | u32 hdmi_dmactl_addr; |
243 | u32 hdmi_dma_stride; |
244 | u32 hdmi_DP_addr; |
245 | u32 hdmi_sstream_addr; |
246 | |
247 | /* HDMI SSTREAM CTRL fields */ |
248 | struct reg_field sstream_en; |
249 | struct reg_field dma_sel; |
250 | struct reg_field auto_bbit_en; |
251 | struct reg_field layout; |
252 | struct reg_field layout_sp; |
253 | struct reg_field set_sp_on_en; |
254 | struct reg_field dp_audio; |
255 | struct reg_field dp_staffing_en; |
256 | struct reg_field dp_sp_b_hw_en; |
257 | |
258 | /* HDMI DP METADATA CTL fields */ |
259 | struct reg_field mute; |
260 | struct reg_field as_sdp_cc; |
261 | struct reg_field as_sdp_ct; |
262 | struct reg_field aif_db4; |
263 | struct reg_field frequency; |
264 | struct reg_field mst_index; |
265 | struct reg_field dptx_index; |
266 | |
267 | /* HDMI TX CTRL fields */ |
268 | struct reg_field soft_reset; |
269 | struct reg_field force_reset; |
270 | |
271 | /* HDMI TX DMA CTRL */ |
272 | struct reg_field use_hw_chs; |
273 | struct reg_field use_hw_usr; |
274 | struct reg_field hw_chs_sel; |
275 | struct reg_field hw_usr_sel; |
276 | |
277 | /* HDMI VBIT CTRL */ |
278 | struct reg_field replace_vbit; |
279 | struct reg_field vbit_stream; |
280 | |
281 | /* HDMI TX LEGACY */ |
282 | struct reg_field legacy_en; |
283 | |
284 | /* HDMI TX PARITY */ |
285 | struct reg_field calc_en; |
286 | |
287 | /* HDMI CH LSB */ |
288 | struct reg_field lsb_bits; |
289 | |
290 | /* HDMI CH MSB */ |
291 | struct reg_field msb_bits; |
292 | |
293 | struct reg_field hdmi_rdma_bursten; |
294 | struct reg_field hdmi_rdma_wpscnt; |
295 | struct reg_field hdmi_rdma_fifowm; |
296 | struct reg_field hdmi_rdma_enable; |
297 | struct reg_field hdmi_rdma_dyncclk; |
298 | struct reg_field hdmi_rdma_burst8; |
299 | struct reg_field hdmi_rdma_burst16; |
300 | struct reg_field hdmi_rdma_dynburst; |
301 | |
302 | /* RD_DMA Register fields */ |
303 | struct reg_field rdma_intf; |
304 | struct reg_field rdma_bursten; |
305 | struct reg_field rdma_wpscnt; |
306 | struct reg_field rdma_fifowm; |
307 | struct reg_field rdma_enable; |
308 | struct reg_field rdma_dyncclk; |
309 | |
310 | /* WR_DMA Register fields */ |
311 | struct reg_field wrdma_intf; |
312 | struct reg_field wrdma_bursten; |
313 | struct reg_field wrdma_wpscnt; |
314 | struct reg_field wrdma_fifowm; |
315 | struct reg_field wrdma_enable; |
316 | struct reg_field wrdma_dyncclk; |
317 | |
318 | /* CDC RXTX RD_DMA */ |
319 | struct reg_field rxtx_rdma_intf; |
320 | struct reg_field rxtx_rdma_bursten; |
321 | struct reg_field rxtx_rdma_wpscnt; |
322 | struct reg_field rxtx_rdma_fifowm; |
323 | struct reg_field rxtx_rdma_enable; |
324 | struct reg_field rxtx_rdma_dyncclk; |
325 | struct reg_field rxtx_rdma_burst8; |
326 | struct reg_field rxtx_rdma_burst16; |
327 | struct reg_field rxtx_rdma_dynburst; |
328 | struct reg_field rxtx_rdma_codec_enable; |
329 | struct reg_field rxtx_rdma_codec_pack; |
330 | struct reg_field rxtx_rdma_codec_intf; |
331 | struct reg_field rxtx_rdma_codec_fs_sel; |
332 | struct reg_field rxtx_rdma_codec_ch; |
333 | struct reg_field rxtx_rdma_codec_fs_delay; |
334 | |
335 | /* CDC RXTX WR_DMA */ |
336 | struct reg_field rxtx_wrdma_intf; |
337 | struct reg_field rxtx_wrdma_bursten; |
338 | struct reg_field rxtx_wrdma_wpscnt; |
339 | struct reg_field rxtx_wrdma_fifowm; |
340 | struct reg_field rxtx_wrdma_enable; |
341 | struct reg_field rxtx_wrdma_dyncclk; |
342 | struct reg_field rxtx_wrdma_burst8; |
343 | struct reg_field rxtx_wrdma_burst16; |
344 | struct reg_field rxtx_wrdma_dynburst; |
345 | struct reg_field rxtx_wrdma_codec_enable; |
346 | struct reg_field rxtx_wrdma_codec_pack; |
347 | struct reg_field rxtx_wrdma_codec_intf; |
348 | struct reg_field rxtx_wrdma_codec_fs_sel; |
349 | struct reg_field rxtx_wrdma_codec_ch; |
350 | struct reg_field rxtx_wrdma_codec_fs_delay; |
351 | |
352 | /* CDC VA WR_DMA */ |
353 | struct reg_field va_wrdma_intf; |
354 | struct reg_field va_wrdma_bursten; |
355 | struct reg_field va_wrdma_wpscnt; |
356 | struct reg_field va_wrdma_fifowm; |
357 | struct reg_field va_wrdma_enable; |
358 | struct reg_field va_wrdma_dyncclk; |
359 | struct reg_field va_wrdma_burst8; |
360 | struct reg_field va_wrdma_burst16; |
361 | struct reg_field va_wrdma_dynburst; |
362 | struct reg_field va_wrdma_codec_enable; |
363 | struct reg_field va_wrdma_codec_pack; |
364 | struct reg_field va_wrdma_codec_intf; |
365 | struct reg_field va_wrdma_codec_fs_sel; |
366 | struct reg_field va_wrdma_codec_ch; |
367 | struct reg_field va_wrdma_codec_fs_delay; |
368 | |
369 | /** |
370 | * on SOCs like APQ8016 the channel control bits start |
371 | * at different offset to ipq806x |
372 | **/ |
373 | u32 dmactl_audif_start; |
374 | u32 wrdma_channel_start; |
375 | u32 rxtx_wrdma_channel_start; |
376 | u32 va_wrdma_channel_start; |
377 | |
378 | /* SOC specific initialization like clocks */ |
379 | int (*init)(struct platform_device *pdev); |
380 | int (*exit)(struct platform_device *pdev); |
381 | int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id); |
382 | int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id); |
383 | |
384 | /* SOC specific dais */ |
385 | struct snd_soc_dai_driver *dai_driver; |
386 | int num_dai; |
387 | const char * const *dai_osr_clk_names; |
388 | const char * const *dai_bit_clk_names; |
389 | |
390 | /* SOC specific clocks configuration */ |
391 | const char **clk_name; |
392 | int num_clks; |
393 | }; |
394 | |
395 | struct lpass_pcm_data { |
396 | int dma_ch; |
397 | int i2s_port; |
398 | }; |
399 | |
400 | /* register the platform driver from the CPU DAI driver */ |
401 | int asoc_qcom_lpass_platform_register(struct platform_device *pdev); |
402 | void asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev); |
403 | void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev); |
404 | int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev); |
405 | extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops; |
406 | extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops2; |
407 | extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops; |
408 | |
409 | #endif /* __LPASS_H__ */ |
410 | |