1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright 2020-2025 NXP
4//
5// Common helpers for the audio DSP on i.MX8
6
7#include <linux/firmware/imx/dsp.h>
8#include <linux/module.h>
9#include <linux/of_address.h>
10#include <linux/of_reserved_mem.h>
11#include <linux/pm_domain.h>
12#include <sound/sof/xtensa.h>
13
14#include "../ops.h"
15
16#include "imx-common.h"
17
18/**
19 * imx8_get_registers() - This function is called in case of DSP oops
20 * in order to gather information about the registers, filename and
21 * linenumber and stack.
22 * @sdev: SOF device
23 * @xoops: Stores information about registers.
24 * @panic_info: Stores information about filename and line number.
25 * @stack: Stores the stack dump.
26 * @stack_words: Size of the stack dump.
27 */
28void imx8_get_registers(struct snd_sof_dev *sdev,
29 struct sof_ipc_dsp_oops_xtensa *xoops,
30 struct sof_ipc_panic_info *panic_info,
31 u32 *stack, size_t stack_words)
32{
33 u32 offset = sdev->dsp_oops_offset;
34
35 /* first read registers */
36 sof_mailbox_read(sdev, offset, message: xoops, bytes: sizeof(*xoops));
37
38 /* then get panic info */
39 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
40 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
41 xoops->arch_hdr.totalsize);
42 return;
43 }
44 offset += xoops->arch_hdr.totalsize;
45 sof_mailbox_read(sdev, offset, message: panic_info, bytes: sizeof(*panic_info));
46
47 /* then get the stack */
48 offset += sizeof(*panic_info);
49 sof_mailbox_read(sdev, offset, message: stack, bytes: stack_words * sizeof(u32));
50}
51
52/**
53 * imx8_dump() - This function is called when a panic message is
54 * received from the firmware.
55 * @sdev: SOF device
56 * @flags: parameter not used but required by ops prototype
57 */
58void imx8_dump(struct snd_sof_dev *sdev, u32 flags)
59{
60 struct sof_ipc_dsp_oops_xtensa xoops;
61 struct sof_ipc_panic_info panic_info;
62 u32 stack[IMX8_STACK_DUMP_SIZE];
63 u32 status;
64
65 /* Get information about the panic status from the debug box area.
66 * Compute the trace point based on the status.
67 */
68 sof_mailbox_read(sdev, offset: sdev->debug_box.offset + 0x4, message: &status, bytes: 4);
69
70 /* Get information about the registers, the filename and line
71 * number and the stack.
72 */
73 imx8_get_registers(sdev, xoops: &xoops, panic_info: &panic_info, stack,
74 IMX8_STACK_DUMP_SIZE);
75
76 /* Print the information to the console */
77 sof_print_oops_and_stack(sdev, KERN_ERR, panic_code: status, tracep_code: status, oops: &xoops,
78 panic_info: &panic_info, stack, IMX8_STACK_DUMP_SIZE);
79}
80EXPORT_SYMBOL(imx8_dump);
81
82static void imx_handle_reply(struct imx_dsp_ipc *ipc)
83{
84 struct snd_sof_dev *sdev;
85 unsigned long flags;
86
87 sdev = imx_dsp_get_data(ipc);
88
89 spin_lock_irqsave(&sdev->ipc_lock, flags);
90 snd_sof_ipc_process_reply(sdev, msg_id: 0);
91 spin_unlock_irqrestore(lock: &sdev->ipc_lock, flags);
92}
93
94static void imx_handle_request(struct imx_dsp_ipc *ipc)
95{
96 struct snd_sof_dev *sdev;
97 u32 panic_code;
98
99 sdev = imx_dsp_get_data(ipc);
100
101 if (get_chip_info(sdev)->ipc_info.has_panic_code) {
102 sof_mailbox_read(sdev, offset: sdev->debug_box.offset + 0x4,
103 message: &panic_code,
104 bytes: sizeof(panic_code));
105
106 if ((panic_code & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
107 snd_sof_dsp_panic(sdev, offset: panic_code, non_recoverable: true);
108 return;
109 }
110 }
111
112 snd_sof_ipc_msgs_rx(sdev);
113}
114
115static struct imx_dsp_ops imx_ipc_ops = {
116 .handle_reply = imx_handle_reply,
117 .handle_request = imx_handle_request,
118};
119
120static int imx_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
121{
122 struct imx_common_data *common = sdev->pdata->hw_pdata;
123
124 sof_mailbox_write(sdev, offset: sdev->host_box.offset, message: msg->msg_data, bytes: msg->msg_size);
125 imx_dsp_ring_doorbell(dsp: common->ipc_handle, chan_idx: 0x0);
126
127 return 0;
128}
129
130static int imx_get_bar_index(struct snd_sof_dev *sdev, u32 type)
131{
132 switch (type) {
133 case SOF_FW_BLK_TYPE_IRAM:
134 case SOF_FW_BLK_TYPE_SRAM:
135 return type;
136 default:
137 return -EINVAL;
138 }
139}
140
141static int imx_get_mailbox_offset(struct snd_sof_dev *sdev)
142{
143 return get_chip_info(sdev)->ipc_info.boot_mbox_offset;
144}
145
146static int imx_get_window_offset(struct snd_sof_dev *sdev, u32 id)
147{
148 return get_chip_info(sdev)->ipc_info.window_offset;
149}
150
151static int imx_set_power_state(struct snd_sof_dev *sdev,
152 const struct sof_dsp_power_state *target)
153{
154 sdev->dsp_power_state = *target;
155
156 return 0;
157}
158
159static int imx_common_resume(struct snd_sof_dev *sdev)
160{
161 struct imx_common_data *common;
162 int ret, i;
163
164 common = sdev->pdata->hw_pdata;
165
166 ret = clk_bulk_prepare_enable(num_clks: common->clk_num, clks: common->clks);
167 if (ret)
168 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
169
170 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
171 imx_dsp_request_channel(ipc: common->ipc_handle, idx: i);
172
173 /* done. If need be, core will be started by SOF core immediately after */
174 return 0;
175}
176
177static int imx_common_suspend(struct snd_sof_dev *sdev)
178{
179 struct imx_common_data *common;
180 int i, ret;
181
182 common = sdev->pdata->hw_pdata;
183
184 ret = imx_chip_core_shutdown(sdev);
185 if (ret < 0) {
186 dev_err(sdev->dev, "failed to shutdown core: %d\n", ret);
187 return ret;
188 }
189
190 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
191 imx_dsp_free_channel(ipc: common->ipc_handle, idx: i);
192
193 clk_bulk_disable_unprepare(num_clks: common->clk_num, clks: common->clks);
194
195 return 0;
196}
197
198static int imx_runtime_resume(struct snd_sof_dev *sdev)
199{
200 const struct sof_dsp_power_state target_state = {
201 .state = SOF_DSP_PM_D0,
202 };
203 int ret;
204
205 ret = imx_common_resume(sdev);
206 if (ret < 0) {
207 dev_err(sdev->dev, "failed to runtime common resume: %d\n", ret);
208 return ret;
209 }
210
211 return snd_sof_dsp_set_power_state(sdev, target_state: &target_state);
212}
213
214static int imx_resume(struct snd_sof_dev *sdev)
215{
216 const struct sof_dsp_power_state target_state = {
217 .state = SOF_DSP_PM_D0,
218 };
219 int ret;
220
221 ret = imx_common_resume(sdev);
222 if (ret < 0) {
223 dev_err(sdev->dev, "failed to common resume: %d\n", ret);
224 return ret;
225 }
226
227 if (pm_runtime_suspended(dev: sdev->dev)) {
228 pm_runtime_disable(dev: sdev->dev);
229 pm_runtime_set_active(dev: sdev->dev);
230 pm_runtime_mark_last_busy(dev: sdev->dev);
231 pm_runtime_enable(dev: sdev->dev);
232 pm_runtime_idle(dev: sdev->dev);
233 }
234
235 return snd_sof_dsp_set_power_state(sdev, target_state: &target_state);
236}
237
238static int imx_runtime_suspend(struct snd_sof_dev *sdev)
239{
240 const struct sof_dsp_power_state target_state = {
241 .state = SOF_DSP_PM_D3,
242 };
243 int ret;
244
245 ret = imx_common_suspend(sdev);
246 if (ret < 0)
247 dev_err(sdev->dev, "failed to runtime common suspend: %d\n", ret);
248
249 return snd_sof_dsp_set_power_state(sdev, target_state: &target_state);
250}
251
252static int imx_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
253{
254 const struct sof_dsp_power_state target_power_state = {
255 .state = target_state,
256 };
257 int ret;
258
259 if (!pm_runtime_suspended(dev: sdev->dev)) {
260 ret = imx_common_suspend(sdev);
261 if (ret < 0) {
262 dev_err(sdev->dev, "failed to common suspend: %d\n", ret);
263 return ret;
264 }
265 }
266
267 return snd_sof_dsp_set_power_state(sdev, target_state: &target_power_state);
268}
269
270static int imx_region_name_to_blk_type(const char *region_name)
271{
272 if (!strcmp(region_name, "iram"))
273 return SOF_FW_BLK_TYPE_IRAM;
274 else if (!strcmp(region_name, "dram"))
275 return SOF_FW_BLK_TYPE_DRAM;
276 else if (!strcmp(region_name, "sram"))
277 return SOF_FW_BLK_TYPE_SRAM;
278 else
279 return -EINVAL;
280}
281
282static int imx_parse_ioremap_memory(struct snd_sof_dev *sdev)
283{
284 const struct imx_chip_info *chip_info;
285 struct platform_device *pdev;
286 struct resource *res, _res;
287 int i, blk_type, ret;
288
289 pdev = to_platform_device(sdev->dev);
290 chip_info = get_chip_info(sdev);
291
292 for (i = 0; chip_info->memory[i].name; i++) {
293 blk_type = imx_region_name_to_blk_type(region_name: chip_info->memory[i].name);
294 if (blk_type < 0)
295 return dev_err_probe(dev: sdev->dev, err: blk_type,
296 fmt: "no blk type for region %s\n",
297 chip_info->memory[i].name);
298
299 if (!chip_info->memory[i].reserved) {
300 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
301 chip_info->memory[i].name);
302 if (!res)
303 return dev_err_probe(dev: sdev->dev, err: -ENODEV,
304 fmt: "failed to fetch %s resource\n",
305 chip_info->memory[i].name);
306
307 } else {
308 ret = of_reserved_mem_region_to_resource_byname(np: pdev->dev.of_node,
309 name: chip_info->memory[i].name,
310 res: &_res);
311 if (ret < 0)
312 return dev_err_probe(dev: sdev->dev, err: ret,
313 fmt: "no valid entry for %s\n",
314 chip_info->memory[i].name);
315 res = &_res;
316 }
317
318 sdev->bar[blk_type] = devm_ioremap_resource(dev: sdev->dev, res);
319 if (IS_ERR(ptr: sdev->bar[blk_type]))
320 return dev_err_probe(dev: sdev->dev,
321 err: PTR_ERR(ptr: sdev->bar[blk_type]),
322 fmt: "failed to ioremap %s region\n",
323 chip_info->memory[i].name);
324 }
325
326 return 0;
327}
328
329static void imx_unregister_action(void *data)
330{
331 struct imx_common_data *common;
332 struct snd_sof_dev *sdev;
333
334 sdev = data;
335 common = sdev->pdata->hw_pdata;
336
337 if (get_chip_info(sdev)->has_dma_reserved)
338 of_reserved_mem_device_release(dev: sdev->dev);
339
340 platform_device_unregister(common->ipc_dev);
341}
342
343static int imx_probe(struct snd_sof_dev *sdev)
344{
345 struct dev_pm_domain_attach_data domain_data = {
346 .pd_names = NULL, /* no filtering */
347 .pd_flags = PD_FLAG_DEV_LINK_ON,
348 };
349 struct imx_common_data *common;
350 struct platform_device *pdev;
351 int ret;
352
353 pdev = to_platform_device(sdev->dev);
354
355 common = devm_kzalloc(dev: sdev->dev, size: sizeof(*common), GFP_KERNEL);
356 if (!common)
357 return -ENOMEM;
358
359 sdev->pdata->hw_pdata = common;
360
361 common->ipc_dev = platform_device_register_data(parent: sdev->dev, name: "imx-dsp",
362 PLATFORM_DEVID_NONE,
363 data: pdev, size: sizeof(*pdev));
364 if (IS_ERR(ptr: common->ipc_dev))
365 return dev_err_probe(dev: sdev->dev, err: PTR_ERR(ptr: common->ipc_dev),
366 fmt: "failed to create IPC device\n");
367
368 if (get_chip_info(sdev)->has_dma_reserved) {
369 ret = of_reserved_mem_device_init_by_name(dev: sdev->dev,
370 np: pdev->dev.of_node,
371 name: "dma");
372 if (ret) {
373 platform_device_unregister(common->ipc_dev);
374
375 return dev_err_probe(dev: sdev->dev, err: ret,
376 fmt: "failed to bind DMA region\n");
377 }
378 }
379
380 /* let the devres API take care of the cleanup */
381 ret = devm_add_action_or_reset(sdev->dev,
382 imx_unregister_action,
383 sdev);
384 if (ret)
385 return ret;
386
387 common->ipc_handle = dev_get_drvdata(dev: &common->ipc_dev->dev);
388 if (!common->ipc_handle)
389 return dev_err_probe(dev: sdev->dev, err: -EPROBE_DEFER,
390 fmt: "failed to fetch IPC handle\n");
391
392 ret = imx_parse_ioremap_memory(sdev);
393 if (ret < 0)
394 return dev_err_probe(dev: sdev->dev, err: ret,
395 fmt: "failed to parse/ioremap memory regions\n");
396
397 if (!sdev->dev->pm_domain) {
398 ret = devm_pm_domain_attach_list(dev: sdev->dev,
399 data: &domain_data, list: &common->pd_list);
400 if (ret < 0)
401 return dev_err_probe(dev: sdev->dev, err: ret, fmt: "failed to attach PDs\n");
402 }
403
404 ret = devm_clk_bulk_get_all(dev: sdev->dev, clks: &common->clks);
405 if (ret < 0)
406 return dev_err_probe(dev: sdev->dev, err: ret, fmt: "failed to fetch clocks\n");
407 common->clk_num = ret;
408
409 ret = clk_bulk_prepare_enable(num_clks: common->clk_num, clks: common->clks);
410 if (ret < 0)
411 return dev_err_probe(dev: sdev->dev, err: ret, fmt: "failed to enable clocks\n");
412
413 common->ipc_handle->ops = &imx_ipc_ops;
414 imx_dsp_set_data(ipc: common->ipc_handle, data: sdev);
415
416 sdev->num_cores = 1;
417 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
418 sdev->dsp_box.offset = get_chip_info(sdev)->ipc_info.boot_mbox_offset;
419
420 return imx_chip_probe(sdev);
421}
422
423static void imx_remove(struct snd_sof_dev *sdev)
424{
425 struct imx_common_data *common;
426 int ret;
427
428 common = sdev->pdata->hw_pdata;
429
430 if (!pm_runtime_suspended(dev: sdev->dev)) {
431 ret = imx_chip_core_shutdown(sdev);
432 if (ret < 0)
433 dev_err(sdev->dev, "failed to shutdown core: %d\n", ret);
434
435 clk_bulk_disable_unprepare(num_clks: common->clk_num, clks: common->clks);
436 }
437}
438
439const struct snd_sof_dsp_ops sof_imx_ops = {
440 .probe = imx_probe,
441 .remove = imx_remove,
442
443 .run = imx_chip_core_kick,
444 .reset = imx_chip_core_reset,
445
446 .block_read = sof_block_read,
447 .block_write = sof_block_write,
448
449 .mailbox_read = sof_mailbox_read,
450 .mailbox_write = sof_mailbox_write,
451
452 .send_msg = imx_send_msg,
453 .get_mailbox_offset = imx_get_mailbox_offset,
454 .get_window_offset = imx_get_window_offset,
455
456 .ipc_msg_data = sof_ipc_msg_data,
457 .set_stream_data_offset = sof_set_stream_data_offset,
458
459 .get_bar_index = imx_get_bar_index,
460 .load_firmware = snd_sof_load_firmware_memcpy,
461
462 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
463
464 .pcm_open = sof_stream_pcm_open,
465 .pcm_close = sof_stream_pcm_close,
466
467 .runtime_suspend = imx_runtime_suspend,
468 .runtime_resume = imx_runtime_resume,
469 .suspend = imx_suspend,
470 .resume = imx_resume,
471
472 .set_power_state = imx_set_power_state,
473
474 .hw_info = SNDRV_PCM_INFO_MMAP |
475 SNDRV_PCM_INFO_MMAP_VALID |
476 SNDRV_PCM_INFO_INTERLEAVED |
477 SNDRV_PCM_INFO_PAUSE |
478 SNDRV_PCM_INFO_BATCH |
479 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
480};
481EXPORT_SYMBOL(sof_imx_ops);
482
483MODULE_LICENSE("Dual BSD/GPL");
484MODULE_DESCRIPTION("SOF helpers for IMX platforms");
485

source code of linux/sound/soc/sof/imx/imx-common.c