| 1 | //===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | /// \file This file contains the AMDGPU implementation of the DAG scheduling |
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| 10 | /// mutation to pair instructions back to back. |
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| 11 | // |
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| 12 | //===----------------------------------------------------------------------===// |
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| 13 | |
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| 14 | #include "AMDGPUMacroFusion.h" |
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| 15 | #include "MCTargetDesc/AMDGPUMCTargetDesc.h" |
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| 16 | #include "SIInstrInfo.h" |
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| 17 | #include "llvm/CodeGen/MacroFusion.h" |
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| 18 | |
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| 19 | using namespace llvm; |
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| 20 | |
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| 21 | namespace { |
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| 22 | |
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| 23 | /// Check if the instr pair, FirstMI and SecondMI, should be fused |
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| 24 | /// together. Given SecondMI, when FirstMI is unspecified, then check if |
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| 25 | /// SecondMI may be part of a fused pair at all. |
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| 26 | static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_, |
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| 27 | const TargetSubtargetInfo &TSI, |
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| 28 | const MachineInstr *FirstMI, |
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| 29 | const MachineInstr &SecondMI) { |
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| 30 | const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); |
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| 31 | |
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| 32 | switch (SecondMI.getOpcode()) { |
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| 33 | case AMDGPU::V_ADDC_U32_e64: |
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| 34 | case AMDGPU::V_SUBB_U32_e64: |
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| 35 | case AMDGPU::V_SUBBREV_U32_e64: |
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| 36 | case AMDGPU::V_CNDMASK_B32_e64: { |
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| 37 | // Try to cluster defs of condition registers to their uses. This improves |
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| 38 | // the chance VCC will be available which will allow shrinking to VOP2 |
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| 39 | // encodings. |
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| 40 | if (!FirstMI) |
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| 41 | return true; |
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| 42 | |
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| 43 | const MachineBasicBlock &MBB = *FirstMI->getParent(); |
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| 44 | const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); |
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| 45 | const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); |
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| 46 | const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, |
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| 47 | AMDGPU::OpName::src2); |
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| 48 | return FirstMI->definesRegister(Reg: Src2->getReg(), TRI); |
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| 49 | } |
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| 50 | default: |
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| 51 | return false; |
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| 52 | } |
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| 53 | |
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| 54 | return false; |
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| 55 | } |
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| 56 | |
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| 57 | } // end namespace |
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| 58 | |
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| 59 | |
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| 60 | namespace llvm { |
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| 61 | |
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| 62 | std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation() { |
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| 63 | return createMacroFusionDAGMutation(Predicates: shouldScheduleAdjacent); |
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| 64 | } |
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| 65 | |
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| 66 | } // end namespace llvm |
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| 67 | |
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