1//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for ARM.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "ARMLegalizerInfo.h"
14#include "ARMCallLowering.h"
15#include "ARMSubtarget.h"
16#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18#include "llvm/CodeGen/LowLevelTypeUtils.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetOpcodes.h"
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/IR/Type.h"
24
25using namespace llvm;
26using namespace LegalizeActions;
27
28static bool AEABI(const ARMSubtarget &ST) {
29 return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
30}
31
32ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
33 using namespace TargetOpcode;
34
35 const LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: 32);
36
37 const LLT s1 = LLT::scalar(SizeInBits: 1);
38 const LLT s8 = LLT::scalar(SizeInBits: 8);
39 const LLT s16 = LLT::scalar(SizeInBits: 16);
40 const LLT s32 = LLT::scalar(SizeInBits: 32);
41 const LLT s64 = LLT::scalar(SizeInBits: 64);
42
43 auto &LegacyInfo = getLegacyLegalizerInfo();
44 if (ST.isThumb1Only()) {
45 // Thumb1 is not supported yet.
46 LegacyInfo.computeTables();
47 verify(*ST.getInstrInfo());
48 return;
49 }
50
51 getActionDefinitionsBuilder(Opcodes: {G_SEXT, G_ZEXT, G_ANYEXT})
52 .legalForCartesianProduct(Types0: {s8, s16, s32}, Types1: {s1, s8, s16});
53
54 getActionDefinitionsBuilder(Opcode: G_SEXT_INREG).lower();
55
56 getActionDefinitionsBuilder(Opcodes: {G_MUL, G_AND, G_OR, G_XOR})
57 .legalFor(Types: {s32})
58 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
59
60 if (ST.hasNEON())
61 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
62 .legalFor(Types: {s32, s64})
63 .minScalar(TypeIdx: 0, Ty: s32);
64 else
65 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
66 .legalFor(Types: {s32})
67 .minScalar(TypeIdx: 0, Ty: s32);
68
69 getActionDefinitionsBuilder(Opcodes: {G_ASHR, G_LSHR, G_SHL})
70 .legalFor(Types: {{s32, s32}})
71 .minScalar(TypeIdx: 0, Ty: s32)
72 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32);
73
74 bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
75 (ST.isThumb() && ST.hasDivideInThumbMode());
76 if (HasHWDivide)
77 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
78 .legalFor(Types: {s32})
79 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
80 else
81 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_UDIV})
82 .libcallFor(Types: {s32})
83 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
84
85 auto &REMBuilder =
86 getActionDefinitionsBuilder(Opcodes: {G_SREM, G_UREM}).minScalar(TypeIdx: 0, Ty: s32);
87 if (HasHWDivide)
88 REMBuilder.lowerFor(Types: {s32});
89 else if (AEABI(ST))
90 REMBuilder.customFor(Types: {s32});
91 else
92 REMBuilder.libcallFor(Types: {s32});
93
94 getActionDefinitionsBuilder(Opcode: G_INTTOPTR)
95 .legalFor(Types: {{p0, s32}})
96 .minScalar(TypeIdx: 1, Ty: s32);
97 getActionDefinitionsBuilder(Opcode: G_PTRTOINT)
98 .legalFor(Types: {{s32, p0}})
99 .minScalar(TypeIdx: 0, Ty: s32);
100
101 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
102 .legalFor(Types: {s32, p0})
103 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
104
105 getActionDefinitionsBuilder(Opcode: G_ICMP)
106 .legalForCartesianProduct(Types0: {s1}, Types1: {s32, p0})
107 .minScalar(TypeIdx: 1, Ty: s32);
108
109 getActionDefinitionsBuilder(Opcode: G_SELECT)
110 .legalForCartesianProduct(Types0: {s32, p0}, Types1: {s1})
111 .minScalar(TypeIdx: 0, Ty: s32);
112
113 // We're keeping these builders around because we'll want to add support for
114 // floating point to them.
115 auto &LoadStoreBuilder = getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
116 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s8, .Type1: p0, .MemTy: s8, .Align: 8},
117 {.Type0: s16, .Type1: p0, .MemTy: s16, .Align: 8},
118 {.Type0: s32, .Type1: p0, .MemTy: s32, .Align: 8},
119 {.Type0: p0, .Type1: p0, .MemTy: p0, .Align: 8}})
120 .unsupportedIfMemSizeNotPow2();
121
122 getActionDefinitionsBuilder(Opcode: G_FRAME_INDEX).legalFor(Types: {p0});
123 getActionDefinitionsBuilder(Opcode: G_GLOBAL_VALUE).legalFor(Types: {p0});
124
125 auto &PhiBuilder =
126 getActionDefinitionsBuilder(Opcode: G_PHI)
127 .legalFor(Types: {s32, p0})
128 .minScalar(TypeIdx: 0, Ty: s32);
129
130 getActionDefinitionsBuilder(Opcode: G_PTR_ADD)
131 .legalFor(Types: {{p0, s32}})
132 .minScalar(TypeIdx: 1, Ty: s32);
133
134 getActionDefinitionsBuilder(Opcode: G_BRCOND).legalFor(Types: {s1});
135
136 if (!ST.useSoftFloat() && ST.hasVFP2Base()) {
137 getActionDefinitionsBuilder(
138 Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
139 .legalFor(Types: {s32, s64});
140
141 LoadStoreBuilder
142 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s64, .Type1: p0, .MemTy: s64, .Align: 32}})
143 .maxScalar(TypeIdx: 0, Ty: s32);
144 PhiBuilder.legalFor(Types: {s64});
145
146 getActionDefinitionsBuilder(Opcode: G_FCMP).legalForCartesianProduct(Types0: {s1},
147 Types1: {s32, s64});
148
149 getActionDefinitionsBuilder(Opcode: G_MERGE_VALUES).legalFor(Types: {{s64, s32}});
150 getActionDefinitionsBuilder(Opcode: G_UNMERGE_VALUES).legalFor(Types: {{s32, s64}});
151
152 getActionDefinitionsBuilder(Opcode: G_FPEXT).legalFor(Types: {{s64, s32}});
153 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).legalFor(Types: {{s32, s64}});
154
155 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
156 .legalForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
157 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
158 .legalForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
159
160 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV}).legalFor(Types: {s32});
161 getActionDefinitionsBuilder(Opcode: G_RESET_FPENV).alwaysLegal();
162 } else {
163 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV})
164 .libcallFor(Types: {s32, s64});
165
166 LoadStoreBuilder.maxScalar(TypeIdx: 0, Ty: s32);
167
168 getActionDefinitionsBuilder(Opcode: G_FNEG).lowerFor(Types: {s32, s64});
169
170 getActionDefinitionsBuilder(Opcode: G_FCONSTANT).customFor(Types: {s32, s64});
171
172 getActionDefinitionsBuilder(Opcode: G_FCMP).customForCartesianProduct(Types0: {s1},
173 Types1: {s32, s64});
174
175 if (AEABI(ST))
176 setFCmpLibcallsAEABI();
177 else
178 setFCmpLibcallsGNU();
179
180 getActionDefinitionsBuilder(Opcode: G_FPEXT).libcallFor(Types: {{s64, s32}});
181 getActionDefinitionsBuilder(Opcode: G_FPTRUNC).libcallFor(Types: {{s32, s64}});
182
183 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
184 .libcallForCartesianProduct(Types0: {s32}, Types1: {s32, s64});
185 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
186 .libcallForCartesianProduct(Types0: {s32, s64}, Types1: {s32});
187
188 getActionDefinitionsBuilder(Opcodes: {G_GET_FPENV, G_SET_FPENV, G_RESET_FPENV})
189 .libcall();
190 }
191
192 // Just expand whatever loads and stores are left.
193 LoadStoreBuilder.lower();
194
195 if (!ST.useSoftFloat() && ST.hasVFP4Base())
196 getActionDefinitionsBuilder(Opcode: G_FMA).legalFor(Types: {s32, s64});
197 else
198 getActionDefinitionsBuilder(Opcode: G_FMA).libcallFor(Types: {s32, s64});
199
200 getActionDefinitionsBuilder(Opcodes: {G_FREM, G_FPOW}).libcallFor(Types: {s32, s64});
201
202 if (ST.hasV5TOps()) {
203 getActionDefinitionsBuilder(Opcode: G_CTLZ)
204 .legalFor(Types: {s32, s32})
205 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
206 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
207 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_UNDEF)
208 .lowerFor(Types: {s32, s32})
209 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
210 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
211 } else {
212 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_UNDEF)
213 .libcallFor(Types: {s32, s32})
214 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
215 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
216 getActionDefinitionsBuilder(Opcode: G_CTLZ)
217 .lowerFor(Types: {s32, s32})
218 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
219 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
220 }
221
222 LegacyInfo.computeTables();
223 verify(*ST.getInstrInfo());
224}
225
226void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
227 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
228 // default-initialized.
229 FCmp32Libcalls.resize(s: CmpInst::LAST_FCMP_PREDICATE + 1);
230 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
231 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
232 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
233 {.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
234 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
235 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
236 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
237 {.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
238 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
239 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
240 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
241 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_EQ}};
242 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_EQ}};
243 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_EQ}};
244 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_EQ}};
245 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_EQ}};
246 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
247 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
248 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
249 {.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
250 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
251 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
252 {.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
253 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
254
255 FCmp64Libcalls.resize(s: CmpInst::LAST_FCMP_PREDICATE + 1);
256 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
257 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
258 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
259 {.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
260 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
261 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
262 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
263 {.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
264 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
265 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
266 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
267 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_EQ}};
268 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_EQ}};
269 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_EQ}};
270 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_EQ}};
271 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_EQ}};
272 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
273 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
274 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
275 {.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
276 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
277 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
278 {.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE},
279 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::BAD_ICMP_PREDICATE}};
280}
281
282void ARMLegalizerInfo::setFCmpLibcallsGNU() {
283 // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
284 // default-initialized.
285 FCmp32Libcalls.resize(s: CmpInst::LAST_FCMP_PREDICATE + 1);
286 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ}};
287 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SGE}};
288 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT}};
289 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SLE}};
290 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
291 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_EQ}};
292 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SGE}};
293 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F32, .Predicate: CmpInst::ICMP_SGT}};
294 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SLE}};
295 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F32, .Predicate: CmpInst::ICMP_SLT}};
296 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F32, .Predicate: CmpInst::ICMP_NE}};
297 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
298 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F32, .Predicate: CmpInst::ICMP_SGT},
299 {.LibcallID: RTLIB::OLT_F32, .Predicate: CmpInst::ICMP_SLT}};
300 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F32, .Predicate: CmpInst::ICMP_EQ},
301 {.LibcallID: RTLIB::UO_F32, .Predicate: CmpInst::ICMP_NE}};
302
303 FCmp64Libcalls.resize(s: CmpInst::LAST_FCMP_PREDICATE + 1);
304 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ}};
305 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SGE}};
306 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT}};
307 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SLE}};
308 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
309 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_EQ}};
310 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SGE}};
311 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{.LibcallID: RTLIB::OLE_F64, .Predicate: CmpInst::ICMP_SGT}};
312 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SLE}};
313 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{.LibcallID: RTLIB::OGE_F64, .Predicate: CmpInst::ICMP_SLT}};
314 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{.LibcallID: RTLIB::UNE_F64, .Predicate: CmpInst::ICMP_NE}};
315 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
316 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{.LibcallID: RTLIB::OGT_F64, .Predicate: CmpInst::ICMP_SGT},
317 {.LibcallID: RTLIB::OLT_F64, .Predicate: CmpInst::ICMP_SLT}};
318 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{.LibcallID: RTLIB::OEQ_F64, .Predicate: CmpInst::ICMP_EQ},
319 {.LibcallID: RTLIB::UO_F64, .Predicate: CmpInst::ICMP_NE}};
320}
321
322ARMLegalizerInfo::FCmpLibcallsList
323ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
324 unsigned Size) const {
325 assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
326 if (Size == 32)
327 return FCmp32Libcalls[Predicate];
328 if (Size == 64)
329 return FCmp64Libcalls[Predicate];
330 llvm_unreachable("Unsupported size for FCmp predicate");
331}
332
333bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
334 LostDebugLocObserver &LocObserver) const {
335 using namespace TargetOpcode;
336
337 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
338 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
339 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
340
341 switch (MI.getOpcode()) {
342 default:
343 return false;
344 case G_SREM:
345 case G_UREM: {
346 Register OriginalResult = MI.getOperand(i: 0).getReg();
347 auto Size = MRI.getType(Reg: OriginalResult).getSizeInBits();
348 if (Size != 32)
349 return false;
350
351 auto Libcall =
352 MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
353
354 // Our divmod libcalls return a struct containing the quotient and the
355 // remainder. Create a new, unused register for the quotient and use the
356 // destination of the original instruction for the remainder.
357 Type *ArgTy = Type::getInt32Ty(C&: Ctx);
358 StructType *RetTy = StructType::get(Context&: Ctx, Elements: {ArgTy, ArgTy}, /* Packed */ isPacked: true);
359 Register RetRegs[] = {MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32)),
360 OriginalResult};
361 auto Status = createLibcall(MIRBuilder, Libcall, Result: {RetRegs, RetTy, 0},
362 Args: {{MI.getOperand(i: 1).getReg(), ArgTy, 0},
363 {MI.getOperand(i: 2).getReg(), ArgTy, 0}},
364 LocObserver, MI: &MI);
365 if (Status != LegalizerHelper::Legalized)
366 return false;
367 break;
368 }
369 case G_FCMP: {
370 assert(MRI.getType(MI.getOperand(2).getReg()) ==
371 MRI.getType(MI.getOperand(3).getReg()) &&
372 "Mismatched operands for G_FCMP");
373 auto OpSize = MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getSizeInBits();
374
375 auto OriginalResult = MI.getOperand(i: 0).getReg();
376 auto Predicate =
377 static_cast<CmpInst::Predicate>(MI.getOperand(i: 1).getPredicate());
378 auto Libcalls = getFCmpLibcalls(Predicate, Size: OpSize);
379
380 if (Libcalls.empty()) {
381 assert((Predicate == CmpInst::FCMP_TRUE ||
382 Predicate == CmpInst::FCMP_FALSE) &&
383 "Predicate needs libcalls, but none specified");
384 MIRBuilder.buildConstant(Res: OriginalResult,
385 Val: Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
386 MI.eraseFromParent();
387 return true;
388 }
389
390 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
391 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(C&: Ctx) : Type::getDoubleTy(C&: Ctx);
392 auto *RetTy = Type::getInt32Ty(C&: Ctx);
393
394 SmallVector<Register, 2> Results;
395 for (auto Libcall : Libcalls) {
396 auto LibcallResult = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 32));
397 auto Status = createLibcall(MIRBuilder, Libcall: Libcall.LibcallID,
398 Result: {LibcallResult, RetTy, 0},
399 Args: {{MI.getOperand(i: 2).getReg(), ArgTy, 0},
400 {MI.getOperand(i: 3).getReg(), ArgTy, 0}},
401 LocObserver, MI: &MI);
402
403 if (Status != LegalizerHelper::Legalized)
404 return false;
405
406 auto ProcessedResult =
407 Libcalls.size() == 1
408 ? OriginalResult
409 : MRI.createGenericVirtualRegister(Ty: MRI.getType(Reg: OriginalResult));
410
411 // We have a result, but we need to transform it into a proper 1-bit 0 or
412 // 1, taking into account the different peculiarities of the values
413 // returned by the comparison functions.
414 CmpInst::Predicate ResultPred = Libcall.Predicate;
415 if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
416 // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
417 // to keep the types consistent.
418 MIRBuilder.buildTrunc(Res: ProcessedResult, Op: LibcallResult);
419 } else {
420 // We need to compare against 0.
421 assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
422 auto Zero = MIRBuilder.buildConstant(Res: LLT::scalar(SizeInBits: 32), Val: 0);
423 MIRBuilder.buildICmp(Pred: ResultPred, Res: ProcessedResult, Op0: LibcallResult, Op1: Zero);
424 }
425 Results.push_back(Elt: ProcessedResult);
426 }
427
428 if (Results.size() != 1) {
429 assert(Results.size() == 2 && "Unexpected number of results");
430 MIRBuilder.buildOr(Dst: OriginalResult, Src0: Results[0], Src1: Results[1]);
431 }
432 break;
433 }
434 case G_FCONSTANT: {
435 // Convert to integer constants, while preserving the binary representation.
436 auto AsInteger =
437 MI.getOperand(i: 1).getFPImm()->getValueAPF().bitcastToAPInt();
438 MIRBuilder.buildConstant(Res: MI.getOperand(i: 0),
439 Val: *ConstantInt::get(Context&: Ctx, V: AsInteger));
440 break;
441 }
442 }
443
444 MI.eraseFromParent();
445 return true;
446}
447

source code of llvm/lib/Target/ARM/ARMLegalizerInfo.cpp