1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
16#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetLowering.h"
21#include "llvm/CodeGen/TargetOpcodes.h"
22#include "llvm/IR/DebugLoc.h"
23#include "llvm/IR/Module.h"
24
25namespace llvm {
26
27// Forward declarations.
28class APInt;
29class BlockAddress;
30class Constant;
31class ConstantFP;
32class ConstantInt;
33class DataLayout;
34class GISelCSEInfo;
35class GlobalValue;
36class TargetRegisterClass;
37class MachineFunction;
38class MachineInstr;
39class TargetInstrInfo;
40class GISelChangeObserver;
41
42/// Class which stores all the state required in a MachineIRBuilder.
43/// Since MachineIRBuilders will only store state in this object, it allows
44/// to transfer BuilderState between different kinds of MachineIRBuilders.
45struct MachineIRBuilderState {
46 /// MachineFunction under construction.
47 MachineFunction *MF = nullptr;
48 /// Information used to access the description of the opcodes.
49 const TargetInstrInfo *TII = nullptr;
50 /// Information used to verify types are consistent and to create virtual registers.
51 MachineRegisterInfo *MRI = nullptr;
52 /// Debug location to be set to any instruction we create.
53 DebugLoc DL;
54 /// PC sections metadata to be set to any instruction we create.
55 MDNode *PCSections = nullptr;
56 /// MMRA Metadata to be set on any instruction we create.
57 MDNode *MMRA = nullptr;
58
59 /// \name Fields describing the insertion point.
60 /// @{
61 MachineBasicBlock *MBB = nullptr;
62 MachineBasicBlock::iterator II;
63 /// @}
64
65 GISelChangeObserver *Observer = nullptr;
66
67 GISelCSEInfo *CSEInfo = nullptr;
68};
69
70class DstOp {
71 union {
72 LLT LLTTy;
73 Register Reg;
74 const TargetRegisterClass *RC;
75 };
76
77public:
78 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
79 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
80 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
81 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
82 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
83 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
84
85 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
86 switch (Ty) {
87 case DstType::Ty_Reg:
88 MIB.addDef(RegNo: Reg);
89 break;
90 case DstType::Ty_LLT:
91 MIB.addDef(RegNo: MRI.createGenericVirtualRegister(Ty: LLTTy));
92 break;
93 case DstType::Ty_RC:
94 MIB.addDef(RegNo: MRI.createVirtualRegister(RegClass: RC));
95 break;
96 }
97 }
98
99 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
100 switch (Ty) {
101 case DstType::Ty_RC:
102 return LLT{};
103 case DstType::Ty_LLT:
104 return LLTTy;
105 case DstType::Ty_Reg:
106 return MRI.getType(Reg: Reg);
107 }
108 llvm_unreachable("Unrecognised DstOp::DstType enum");
109 }
110
111 Register getReg() const {
112 assert(Ty == DstType::Ty_Reg && "Not a register");
113 return Reg;
114 }
115
116 const TargetRegisterClass *getRegClass() const {
117 switch (Ty) {
118 case DstType::Ty_RC:
119 return RC;
120 default:
121 llvm_unreachable("Not a RC Operand");
122 }
123 }
124
125 DstType getDstOpKind() const { return Ty; }
126
127private:
128 DstType Ty;
129};
130
131class SrcOp {
132 union {
133 MachineInstrBuilder SrcMIB;
134 Register Reg;
135 CmpInst::Predicate Pred;
136 int64_t Imm;
137 };
138
139public:
140 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
141 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
142 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
143 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
144 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
145 /// Use of registers held in unsigned integer variables (or more rarely signed
146 /// integers) is no longer permitted to avoid ambiguity with upcoming support
147 /// for immediates.
148 SrcOp(unsigned) = delete;
149 SrcOp(int) = delete;
150 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
151 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
152
153 void addSrcToMIB(MachineInstrBuilder &MIB) const {
154 switch (Ty) {
155 case SrcType::Ty_Predicate:
156 MIB.addPredicate(Pred: Pred);
157 break;
158 case SrcType::Ty_Reg:
159 MIB.addUse(RegNo: Reg);
160 break;
161 case SrcType::Ty_MIB:
162 MIB.addUse(RegNo: SrcMIB->getOperand(i: 0).getReg());
163 break;
164 case SrcType::Ty_Imm:
165 MIB.addImm(Val: Imm);
166 break;
167 }
168 }
169
170 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
171 switch (Ty) {
172 case SrcType::Ty_Predicate:
173 case SrcType::Ty_Imm:
174 llvm_unreachable("Not a register operand");
175 case SrcType::Ty_Reg:
176 return MRI.getType(Reg: Reg);
177 case SrcType::Ty_MIB:
178 return MRI.getType(Reg: SrcMIB->getOperand(i: 0).getReg());
179 }
180 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
181 }
182
183 Register getReg() const {
184 switch (Ty) {
185 case SrcType::Ty_Predicate:
186 case SrcType::Ty_Imm:
187 llvm_unreachable("Not a register operand");
188 case SrcType::Ty_Reg:
189 return Reg;
190 case SrcType::Ty_MIB:
191 return SrcMIB->getOperand(i: 0).getReg();
192 }
193 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
194 }
195
196 CmpInst::Predicate getPredicate() const {
197 switch (Ty) {
198 case SrcType::Ty_Predicate:
199 return Pred;
200 default:
201 llvm_unreachable("Not a register operand");
202 }
203 }
204
205 int64_t getImm() const {
206 switch (Ty) {
207 case SrcType::Ty_Imm:
208 return Imm;
209 default:
210 llvm_unreachable("Not an immediate");
211 }
212 }
213
214 SrcType getSrcOpKind() const { return Ty; }
215
216private:
217 SrcType Ty;
218};
219
220/// Helper class to build MachineInstr.
221/// It keeps internally the insertion point and debug location for all
222/// the new instructions we want to create.
223/// This information can be modified via the related setters.
224class MachineIRBuilder {
225
226 MachineIRBuilderState State;
227
228 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
229
230protected:
231 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
232
233 void validateUnaryOp(const LLT Res, const LLT Op0);
234 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
235 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
236
237 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
238 const LLT Op1Ty);
239
240 void recordInsertion(MachineInstr *InsertedInstr) const {
241 if (State.Observer)
242 State.Observer->createdInstr(MI&: *InsertedInstr);
243 }
244
245public:
246 /// Some constructors for easy use.
247 MachineIRBuilder() = default;
248 MachineIRBuilder(MachineFunction &MF) { setMF(MF); }
249
250 MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) {
251 setMF(*MBB.getParent());
252 setInsertPt(MBB, II: InsPt);
253 }
254
255 MachineIRBuilder(MachineInstr &MI) :
256 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
257 setInstr(MI);
258 setDebugLoc(MI.getDebugLoc());
259 }
260
261 MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) :
262 MachineIRBuilder(MI) {
263 setChangeObserver(Observer);
264 }
265
266 virtual ~MachineIRBuilder() = default;
267
268 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
269
270 const TargetInstrInfo &getTII() {
271 assert(State.TII && "TargetInstrInfo is not set");
272 return *State.TII;
273 }
274
275 /// Getter for the function we currently build.
276 MachineFunction &getMF() {
277 assert(State.MF && "MachineFunction is not set");
278 return *State.MF;
279 }
280
281 const MachineFunction &getMF() const {
282 assert(State.MF && "MachineFunction is not set");
283 return *State.MF;
284 }
285
286 const DataLayout &getDataLayout() const {
287 return getMF().getFunction().getParent()->getDataLayout();
288 }
289
290 LLVMContext &getContext() const {
291 return getMF().getFunction().getContext();
292 }
293
294 /// Getter for DebugLoc
295 const DebugLoc &getDL() { return State.DL; }
296
297 /// Getter for MRI
298 MachineRegisterInfo *getMRI() { return State.MRI; }
299 const MachineRegisterInfo *getMRI() const { return State.MRI; }
300
301 /// Getter for the State
302 MachineIRBuilderState &getState() { return State; }
303
304 /// Setter for the State
305 void setState(const MachineIRBuilderState &NewState) { State = NewState; }
306
307 /// Getter for the basic block we currently build.
308 const MachineBasicBlock &getMBB() const {
309 assert(State.MBB && "MachineBasicBlock is not set");
310 return *State.MBB;
311 }
312
313 MachineBasicBlock &getMBB() {
314 return const_cast<MachineBasicBlock &>(
315 const_cast<const MachineIRBuilder *>(this)->getMBB());
316 }
317
318 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
319 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
320
321 /// Current insertion point for new instructions.
322 MachineBasicBlock::iterator getInsertPt() { return State.II; }
323
324 /// Set the insertion point before the specified position.
325 /// \pre MBB must be in getMF().
326 /// \pre II must be a valid iterator in MBB.
327 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) {
328 assert(MBB.getParent() == &getMF() &&
329 "Basic block is in a different function");
330 State.MBB = &MBB;
331 State.II = II;
332 }
333
334 /// @}
335
336 void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
337
338 /// \name Setters for the insertion point.
339 /// @{
340 /// Set the MachineFunction where to build instructions.
341 void setMF(MachineFunction &MF);
342
343 /// Set the insertion point to the end of \p MBB.
344 /// \pre \p MBB must be contained by getMF().
345 void setMBB(MachineBasicBlock &MBB) {
346 State.MBB = &MBB;
347 State.II = MBB.end();
348 assert(&getMF() == MBB.getParent() &&
349 "Basic block is in a different function");
350 }
351
352 /// Set the insertion point to before MI.
353 /// \pre MI must be in getMF().
354 void setInstr(MachineInstr &MI) {
355 assert(MI.getParent() && "Instruction is not part of a basic block");
356 setMBB(*MI.getParent());
357 State.II = MI.getIterator();
358 setPCSections(MI.getPCSections());
359 setMMRAMetadata(MI.getMMRAMetadata());
360 }
361 /// @}
362
363 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
364 /// \pre MI must be in getMF().
365 void setInstrAndDebugLoc(MachineInstr &MI) {
366 setInstr(MI);
367 setDebugLoc(MI.getDebugLoc());
368 }
369
370 void setChangeObserver(GISelChangeObserver &Observer) {
371 State.Observer = &Observer;
372 }
373
374 GISelChangeObserver *getObserver() { return State.Observer; }
375
376 void stopObservingChanges() { State.Observer = nullptr; }
377
378 bool isObservingChanges() const { return State.Observer != nullptr; }
379 /// @}
380
381 /// Set the debug location to \p DL for all the next build instructions.
382 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
383
384 /// Get the current instruction's debug location.
385 const DebugLoc &getDebugLoc() { return State.DL; }
386
387 /// Set the PC sections metadata to \p MD for all the next build instructions.
388 void setPCSections(MDNode *MD) { State.PCSections = MD; }
389
390 /// Get the current instruction's PC sections metadata.
391 MDNode *getPCSections() { return State.PCSections; }
392
393 /// Set the PC sections metadata to \p MD for all the next build instructions.
394 void setMMRAMetadata(MDNode *MMRA) { State.MMRA = MMRA; }
395
396 /// Get the current instruction's MMRA metadata.
397 MDNode *getMMRAMetadata() { return State.MMRA; }
398
399 /// Build and insert <empty> = \p Opcode <empty>.
400 /// The insertion point is the one set by the last call of either
401 /// setBasicBlock or setMI.
402 ///
403 /// \pre setBasicBlock or setMI must have been called.
404 ///
405 /// \return a MachineInstrBuilder for the newly created instruction.
406 MachineInstrBuilder buildInstr(unsigned Opcode) {
407 return insertInstr(MIB: buildInstrNoInsert(Opcode));
408 }
409
410 /// Build but don't insert <empty> = \p Opcode <empty>.
411 ///
412 /// \pre setMF, setBasicBlock or setMI must have been called.
413 ///
414 /// \return a MachineInstrBuilder for the newly created instruction.
415 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
416
417 /// Insert an existing instruction at the insertion point.
418 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
419
420 /// Build and insert a DBG_VALUE instruction expressing the fact that the
421 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
422 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
423 const MDNode *Expr);
424
425 /// Build and insert a DBG_VALUE instruction expressing the fact that the
426 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
427 /// Expr).
428 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
429 const MDNode *Variable,
430 const MDNode *Expr);
431
432 /// Build and insert a DBG_VALUE instruction expressing the fact that the
433 /// associated \p Variable lives in the stack slot specified by \p FI
434 /// (suitably modified by \p Expr).
435 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
436 const MDNode *Expr);
437
438 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
439 /// given by \p C (suitably modified by \p Expr).
440 MachineInstrBuilder buildConstDbgValue(const Constant &C,
441 const MDNode *Variable,
442 const MDNode *Expr);
443
444 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
445 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
446 MachineInstrBuilder buildDbgLabel(const MDNode *Label);
447
448 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
449 ///
450 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
451 /// the allocated memory into \p Res.
452 /// \pre setBasicBlock or setMI must have been called.
453 /// \pre \p Res must be a generic virtual register with pointer type.
454 ///
455 /// \return a MachineInstrBuilder for the newly created instruction.
456 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
457 Align Alignment);
458
459 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
460 ///
461 /// G_FRAME_INDEX materializes the address of an alloca value or other
462 /// stack-based object.
463 ///
464 /// \pre setBasicBlock or setMI must have been called.
465 /// \pre \p Res must be a generic virtual register with pointer type.
466 ///
467 /// \return a MachineInstrBuilder for the newly created instruction.
468 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
469
470 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
471 ///
472 /// G_GLOBAL_VALUE materializes the address of the specified global
473 /// into \p Res.
474 ///
475 /// \pre setBasicBlock or setMI must have been called.
476 /// \pre \p Res must be a generic virtual register with pointer type
477 /// in the same address space as \p GV.
478 ///
479 /// \return a MachineInstrBuilder for the newly created instruction.
480 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
481
482 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
483 ///
484 /// G_CONSTANT_POOL materializes the address of an object in the constant
485 /// pool.
486 ///
487 /// \pre setBasicBlock or setMI must have been called.
488 /// \pre \p Res must be a generic virtual register with pointer type.
489 ///
490 /// \return a MachineInstrBuilder for the newly created instruction.
491 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
492
493 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
494 ///
495 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
496 /// storing the resulting pointer in \p Res. Addressible units are typically
497 /// bytes but this can vary between targets.
498 ///
499 /// \pre setBasicBlock or setMI must have been called.
500 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
501 /// type.
502 /// \pre \p Op1 must be a generic virtual register with scalar type.
503 ///
504 /// \return a MachineInstrBuilder for the newly created instruction.
505 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
506 const SrcOp &Op1,
507 std::optional<unsigned> Flags = std::nullopt);
508
509 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
510 ///
511 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
512 /// storing the resulting pointer in \p Res. If \p Value is zero then no
513 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
514 /// \p Res.
515 ///
516 /// \pre setBasicBlock or setMI must have been called.
517 /// \pre \p Op0 must be a generic virtual register with pointer type.
518 /// \pre \p ValueTy must be a scalar type.
519 /// \pre \p Res must be 0. This is to detect confusion between
520 /// materializePtrAdd() and buildPtrAdd().
521 /// \post \p Res will either be a new generic virtual register of the same
522 /// type as \p Op0 or \p Op0 itself.
523 ///
524 /// \return a MachineInstrBuilder for the newly created instruction.
525 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
526 Register Op0,
527 const LLT ValueTy,
528 uint64_t Value);
529
530 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
531 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
532 const SrcOp &Op1) {
533 return buildInstr(Opc: TargetOpcode::G_PTRMASK, DstOps: {Res}, SrcOps: {Op0, Op1});
534 }
535
536 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
537 ///
538 /// This clears the low bits of a pointer operand without destroying its
539 /// pointer properties. This has the effect of rounding the address *down* to
540 /// a specified alignment in bits.
541 ///
542 /// \pre setBasicBlock or setMI must have been called.
543 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
544 /// type.
545 /// \pre \p NumBits must be an integer representing the number of low bits to
546 /// be cleared in \p Op0.
547 ///
548 /// \return a MachineInstrBuilder for the newly created instruction.
549 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
550 uint32_t NumBits);
551
552 /// Build and insert
553 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
554 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
555 ///
556 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
557 ///
558 /// \pre setBasicBlock or setMI must have been called.
559 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
560 /// same vector element type and Op0 must have fewer elements then Res.
561 ///
562 /// \return a MachineInstrBuilder for the newly created build vector instr.
563 MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res,
564 const SrcOp &Op0);
565
566 /// Build and insert
567 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
568 /// \p Res = G_BUILD_VECTOR a, b, ..., x
569 ///
570 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
571 ///
572 /// \pre setBasicBlock or setMI must have been called.
573 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
574 /// same vector element type and Op0 must have more elements then Res.
575 ///
576 /// \return a MachineInstrBuilder for the newly created build vector instr.
577 MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res,
578 const SrcOp &Op0);
579
580 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
581 ///
582 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
583 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
584 ///
585 /// \pre setBasicBlock or setMI must have been called.
586 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
587 /// same scalar type.
588 ////\pre \p CarryOut must be generic virtual register with scalar type
589 ///(typically s1)
590 ///
591 /// \return The newly created instruction.
592 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
593 const SrcOp &Op0, const SrcOp &Op1) {
594 return buildInstr(Opc: TargetOpcode::G_UADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
595 }
596
597 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
598 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
599 const SrcOp &Op0, const SrcOp &Op1) {
600 return buildInstr(Opc: TargetOpcode::G_USUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
601 }
602
603 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
604 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
605 const SrcOp &Op0, const SrcOp &Op1) {
606 return buildInstr(Opc: TargetOpcode::G_SADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
607 }
608
609 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
610 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
611 const SrcOp &Op0, const SrcOp &Op1) {
612 return buildInstr(Opc: TargetOpcode::G_SSUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
613 }
614
615 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
616 /// \p Op1, \p CarryIn
617 ///
618 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
619 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
620 /// arithmetic.
621 ///
622 /// \pre setBasicBlock or setMI must have been called.
623 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
624 /// with the same scalar type.
625 /// \pre \p CarryOut and \p CarryIn must be generic virtual
626 /// registers with the same scalar type (typically s1)
627 ///
628 /// \return The newly created instruction.
629 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
630 const SrcOp &Op0, const SrcOp &Op1,
631 const SrcOp &CarryIn) {
632 return buildInstr(Opc: TargetOpcode::G_UADDE, DstOps: {Res, CarryOut},
633 SrcOps: {Op0, Op1, CarryIn});
634 }
635
636 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
637 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
638 const SrcOp &Op0, const SrcOp &Op1,
639 const SrcOp &CarryIn) {
640 return buildInstr(Opc: TargetOpcode::G_USUBE, DstOps: {Res, CarryOut},
641 SrcOps: {Op0, Op1, CarryIn});
642 }
643
644 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
645 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
646 const SrcOp &Op0, const SrcOp &Op1,
647 const SrcOp &CarryIn) {
648 return buildInstr(Opc: TargetOpcode::G_SADDE, DstOps: {Res, CarryOut},
649 SrcOps: {Op0, Op1, CarryIn});
650 }
651
652 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
653 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
654 const SrcOp &Op0, const SrcOp &Op1,
655 const SrcOp &CarryIn) {
656 return buildInstr(Opc: TargetOpcode::G_SSUBE, DstOps: {Res, CarryOut},
657 SrcOps: {Op0, Op1, CarryIn});
658 }
659
660 /// Build and insert \p Res = G_ANYEXT \p Op0
661 ///
662 /// G_ANYEXT produces a register of the specified width, with bits 0 to
663 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
664 /// (i.e. this is neither zero nor sign-extension). For a vector register,
665 /// each element is extended individually.
666 ///
667 /// \pre setBasicBlock or setMI must have been called.
668 /// \pre \p Res must be a generic virtual register with scalar or vector type.
669 /// \pre \p Op must be a generic virtual register with scalar or vector type.
670 /// \pre \p Op must be smaller than \p Res
671 ///
672 /// \return The newly created instruction.
673
674 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
675
676 /// Build and insert \p Res = G_SEXT \p Op
677 ///
678 /// G_SEXT produces a register of the specified width, with bits 0 to
679 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
680 /// high bit of \p Op (i.e. 2s-complement sign extended).
681 ///
682 /// \pre setBasicBlock or setMI must have been called.
683 /// \pre \p Res must be a generic virtual register with scalar or vector type.
684 /// \pre \p Op must be a generic virtual register with scalar or vector type.
685 /// \pre \p Op must be smaller than \p Res
686 ///
687 /// \return The newly created instruction.
688 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
689
690 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
691 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
692 return buildInstr(Opc: TargetOpcode::G_SEXT_INREG, DstOps: {Res}, SrcOps: {Op, SrcOp(ImmOp)});
693 }
694
695 /// Build and insert \p Res = G_FPEXT \p Op
696 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op,
697 std::optional<unsigned> Flags = std::nullopt) {
698 return buildInstr(Opc: TargetOpcode::G_FPEXT, DstOps: {Res}, SrcOps: {Op}, Flags);
699 }
700
701 /// Build and insert a G_PTRTOINT instruction.
702 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
703 return buildInstr(Opc: TargetOpcode::G_PTRTOINT, DstOps: {Dst}, SrcOps: {Src});
704 }
705
706 /// Build and insert a G_INTTOPTR instruction.
707 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
708 return buildInstr(Opc: TargetOpcode::G_INTTOPTR, DstOps: {Dst}, SrcOps: {Src});
709 }
710
711 /// Build and insert \p Dst = G_BITCAST \p Src
712 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
713 return buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {Dst}, SrcOps: {Src});
714 }
715
716 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
717 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {
718 return buildInstr(Opc: TargetOpcode::G_ADDRSPACE_CAST, DstOps: {Dst}, SrcOps: {Src});
719 }
720
721 /// \return The opcode of the extension the target wants to use for boolean
722 /// values.
723 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
724
725 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
726 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
727 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
728 bool IsFP);
729
730 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
731 // or COPY depending on how the target wants to extend boolean values, using
732 // the original register size.
733 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,
734 bool IsVector,
735 bool IsFP);
736
737 /// Build and insert \p Res = G_ZEXT \p Op
738 ///
739 /// G_ZEXT produces a register of the specified width, with bits 0 to
740 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
741 /// register, each element is extended individually.
742 ///
743 /// \pre setBasicBlock or setMI must have been called.
744 /// \pre \p Res must be a generic virtual register with scalar or vector type.
745 /// \pre \p Op must be a generic virtual register with scalar or vector type.
746 /// \pre \p Op must be smaller than \p Res
747 ///
748 /// \return The newly created instruction.
749 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
750
751 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
752 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
753 /// ///
754 /// \pre setBasicBlock or setMI must have been called.
755 /// \pre \p Res must be a generic virtual register with scalar or vector type.
756 /// \pre \p Op must be a generic virtual register with scalar or vector type.
757 ///
758 /// \return The newly created instruction.
759 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
760
761 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
762 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
763 /// ///
764 /// \pre setBasicBlock or setMI must have been called.
765 /// \pre \p Res must be a generic virtual register with scalar or vector type.
766 /// \pre \p Op must be a generic virtual register with scalar or vector type.
767 ///
768 /// \return The newly created instruction.
769 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
770
771 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
772 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
773 /// ///
774 /// \pre setBasicBlock or setMI must have been called.
775 /// \pre \p Res must be a generic virtual register with scalar or vector type.
776 /// \pre \p Op must be a generic virtual register with scalar or vector type.
777 ///
778 /// \return The newly created instruction.
779 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
780
781 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
782 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
783 /// \p Op.
784 /// ///
785 /// \pre setBasicBlock or setMI must have been called.
786 /// \pre \p Res must be a generic virtual register with scalar or vector type.
787 /// \pre \p Op must be a generic virtual register with scalar or vector type.
788 ///
789 /// \return The newly created instruction.
790 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
791 const SrcOp &Op);
792
793 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
794 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
795 /// emulated using G_AND.
796 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
797 int64_t ImmOp);
798
799 /// Build and insert an appropriate cast between two registers of equal size.
800 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
801
802 /// Build and insert G_BR \p Dest
803 ///
804 /// G_BR is an unconditional branch to \p Dest.
805 ///
806 /// \pre setBasicBlock or setMI must have been called.
807 ///
808 /// \return a MachineInstrBuilder for the newly created instruction.
809 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
810
811 /// Build and insert G_BRCOND \p Tst, \p Dest
812 ///
813 /// G_BRCOND is a conditional branch to \p Dest.
814 ///
815 /// \pre setBasicBlock or setMI must have been called.
816 /// \pre \p Tst must be a generic virtual register with scalar
817 /// type. At the beginning of legalization, this will be a single
818 /// bit (s1). Targets with interesting flags registers may change
819 /// this. For a wider type, whether the branch is taken must only
820 /// depend on bit 0 (for now).
821 ///
822 /// \return The newly created instruction.
823 MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest);
824
825 /// Build and insert G_BRINDIRECT \p Tgt
826 ///
827 /// G_BRINDIRECT is an indirect branch to \p Tgt.
828 ///
829 /// \pre setBasicBlock or setMI must have been called.
830 /// \pre \p Tgt must be a generic virtual register with pointer type.
831 ///
832 /// \return a MachineInstrBuilder for the newly created instruction.
833 MachineInstrBuilder buildBrIndirect(Register Tgt);
834
835 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
836 ///
837 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
838 /// jump table index \p JTI and index \p IndexReg
839 ///
840 /// \pre setBasicBlock or setMI must have been called.
841 /// \pre \p TablePtr must be a generic virtual register with pointer type.
842 /// \pre \p JTI must be a jump table index.
843 /// \pre \p IndexReg must be a generic virtual register with pointer type.
844 ///
845 /// \return a MachineInstrBuilder for the newly created instruction.
846 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
847 Register IndexReg);
848
849 /// Build and insert \p Res = G_CONSTANT \p Val
850 ///
851 /// G_CONSTANT is an integer constant with the specified size and value. \p
852 /// Val will be extended or truncated to the size of \p Reg.
853 ///
854 /// \pre setBasicBlock or setMI must have been called.
855 /// \pre \p Res must be a generic virtual register with scalar or pointer
856 /// type.
857 ///
858 /// \return The newly created instruction.
859 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
860 const ConstantInt &Val);
861
862 /// Build and insert \p Res = G_CONSTANT \p Val
863 ///
864 /// G_CONSTANT is an integer constant with the specified size and value.
865 ///
866 /// \pre setBasicBlock or setMI must have been called.
867 /// \pre \p Res must be a generic virtual register with scalar type.
868 ///
869 /// \return The newly created instruction.
870 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
871 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
872
873 /// Build and insert \p Res = G_FCONSTANT \p Val
874 ///
875 /// G_FCONSTANT is a floating-point constant with the specified size and
876 /// value.
877 ///
878 /// \pre setBasicBlock or setMI must have been called.
879 /// \pre \p Res must be a generic virtual register with scalar type.
880 ///
881 /// \return The newly created instruction.
882 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
883 const ConstantFP &Val);
884
885 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
886 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
887
888 /// Build and insert \p Res = COPY Op
889 ///
890 /// Register-to-register COPY sets \p Res to \p Op.
891 ///
892 /// \pre setBasicBlock or setMI must have been called.
893 ///
894 /// \return a MachineInstrBuilder for the newly created instruction.
895 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
896
897
898 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
899 ///
900 /// \return a MachineInstrBuilder for the newly created instruction.
901 MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res,
902 const SrcOp &Op, unsigned Val) {
903 return buildInstr(Opc, DstOps: Res, SrcOps: Op).addImm(Val);
904 }
905
906 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
907 ///
908 /// \return a MachineInstrBuilder for the newly created instruction.
909 MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
910 unsigned Size) {
911 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ZEXT, Res, Op, Val: Size);
912 }
913
914 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
915 ///
916 /// \return a MachineInstrBuilder for the newly created instruction.
917 MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
918 unsigned Size) {
919 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_SEXT, Res, Op, Val: Size);
920 }
921
922 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
923 ///
924 /// \return a MachineInstrBuilder for the newly created instruction.
925 MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op,
926 Align AlignVal) {
927 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ALIGN, Res, Op,
928 Val: AlignVal.value());
929 }
930
931 /// Build and insert `Res = G_LOAD Addr, MMO`.
932 ///
933 /// Loads the value stored at \p Addr. Puts the result in \p Res.
934 ///
935 /// \pre setBasicBlock or setMI must have been called.
936 /// \pre \p Res must be a generic virtual register.
937 /// \pre \p Addr must be a generic virtual register with pointer type.
938 ///
939 /// \return a MachineInstrBuilder for the newly created instruction.
940 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
941 MachineMemOperand &MMO) {
942 return buildLoadInstr(Opcode: TargetOpcode::G_LOAD, Res, Addr, MMO);
943 }
944
945 /// Build and insert a G_LOAD instruction, while constructing the
946 /// MachineMemOperand.
947 MachineInstrBuilder
948 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
949 Align Alignment,
950 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
951 const AAMDNodes &AAInfo = AAMDNodes());
952
953 /// Build and insert `Res = <opcode> Addr, MMO`.
954 ///
955 /// Loads the value stored at \p Addr. Puts the result in \p Res.
956 ///
957 /// \pre setBasicBlock or setMI must have been called.
958 /// \pre \p Res must be a generic virtual register.
959 /// \pre \p Addr must be a generic virtual register with pointer type.
960 ///
961 /// \return a MachineInstrBuilder for the newly created instruction.
962 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
963 const SrcOp &Addr, MachineMemOperand &MMO);
964
965 /// Helper to create a load from a constant offset given a base address. Load
966 /// the type of \p Dst from \p Offset from the given base address and memory
967 /// operand.
968 MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst,
969 const SrcOp &BasePtr,
970 MachineMemOperand &BaseMMO,
971 int64_t Offset);
972
973 /// Build and insert `G_STORE Val, Addr, MMO`.
974 ///
975 /// Stores the value \p Val to \p Addr.
976 ///
977 /// \pre setBasicBlock or setMI must have been called.
978 /// \pre \p Val must be a generic virtual register.
979 /// \pre \p Addr must be a generic virtual register with pointer type.
980 ///
981 /// \return a MachineInstrBuilder for the newly created instruction.
982 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
983 MachineMemOperand &MMO);
984
985 /// Build and insert a G_STORE instruction, while constructing the
986 /// MachineMemOperand.
987 MachineInstrBuilder
988 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
989 Align Alignment,
990 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
991 const AAMDNodes &AAInfo = AAMDNodes());
992
993 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
994 ///
995 /// \pre setBasicBlock or setMI must have been called.
996 /// \pre \p Res and \p Src must be generic virtual registers.
997 ///
998 /// \return a MachineInstrBuilder for the newly created instruction.
999 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
1000
1001 /// Build and insert \p Res = IMPLICIT_DEF.
1002 MachineInstrBuilder buildUndef(const DstOp &Res);
1003
1004 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1005 ///
1006 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1007 /// register. It should only be used when the destination register is not a
1008 /// vector.
1009 ///
1010 /// \pre setBasicBlock or setMI must have been called.
1011 /// \pre The entire register \p Res (and no more) must be covered by the input
1012 /// registers.
1013 /// \pre The type of all \p Ops registers must be identical.
1014 ///
1015 /// \return a MachineInstrBuilder for the newly created instruction.
1016 MachineInstrBuilder buildMergeValues(const DstOp &Res,
1017 ArrayRef<Register> Ops);
1018
1019 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1020 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1021 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1022 ///
1023 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1024 /// register. It is used when the destination register is not a vector.
1025 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1026 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1027 ///
1028 /// \pre setBasicBlock or setMI must have been called.
1029 /// \pre The entire register \p Res (and no more) must be covered by the input
1030 /// registers.
1031 /// \pre The type of all \p Ops registers must be identical.
1032 ///
1033 /// \return a MachineInstrBuilder for the newly created instruction. The
1034 /// opcode of the new instruction will depend on the types of both
1035 /// the destination and the sources.
1036 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res,
1037 ArrayRef<Register> Ops);
1038 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res,
1039 std::initializer_list<SrcOp> Ops);
1040
1041 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1042 ///
1043 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1044 ///
1045 /// \pre setBasicBlock or setMI must have been called.
1046 /// \pre The entire register \p Res (and no more) must be covered by the input
1047 /// registers.
1048 /// \pre The type of all \p Res registers must be identical.
1049 ///
1050 /// \return a MachineInstrBuilder for the newly created instruction.
1051 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
1052 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
1053
1054 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1055 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
1056
1057 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1058 ///
1059 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1060 /// \pre setBasicBlock or setMI must have been called.
1061 /// \pre The entire register \p Res (and no more) must be covered by the
1062 /// input scalar registers.
1063 /// \pre The type of all \p Ops registers must be identical.
1064 ///
1065 /// \return a MachineInstrBuilder for the newly created instruction.
1066 MachineInstrBuilder buildBuildVector(const DstOp &Res,
1067 ArrayRef<Register> Ops);
1068
1069 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1070 /// built with G_CONSTANT.
1071 MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res,
1072 ArrayRef<APInt> Ops);
1073
1074 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1075 /// the number of elements
1076 MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src);
1077
1078 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1079 ///
1080 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1081 /// which have types larger than the destination vector element type, and
1082 /// truncates the values to fit.
1083 ///
1084 /// If the operands given are already the same size as the vector elt type,
1085 /// then this method will instead create a G_BUILD_VECTOR instruction.
1086 ///
1087 /// \pre setBasicBlock or setMI must have been called.
1088 /// \pre The type of all \p Ops registers must be identical.
1089 ///
1090 /// \return a MachineInstrBuilder for the newly created instruction.
1091 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
1092 ArrayRef<Register> Ops);
1093
1094 /// Build and insert a vector splat of a scalar \p Src using a
1095 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1096 ///
1097 /// \pre setBasicBlock or setMI must have been called.
1098 /// \pre \p Src must have the same type as the element type of \p Dst
1099 ///
1100 /// \return a MachineInstrBuilder for the newly created instruction.
1101 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1102
1103 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1104 ///
1105 /// \pre setBasicBlock or setMI must have been called.
1106 ///
1107 /// \return a MachineInstrBuilder for the newly created instruction.
1108 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1109 const SrcOp &Src2, ArrayRef<int> Mask);
1110
1111 /// Build and insert \p Res = G_SPLAT_VECTOR \p Val
1112 ///
1113 /// \pre setBasicBlock or setMI must have been called.
1114 /// \pre \p Res must be a generic virtual register with vector type.
1115 /// \pre \p Val must be a generic virtual register with scalar type.
1116 ///
1117 /// \return a MachineInstrBuilder for the newly created instruction.
1118 MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val);
1119
1120 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1121 ///
1122 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1123 /// vectors.
1124 ///
1125 /// \pre setBasicBlock or setMI must have been called.
1126 /// \pre The entire register \p Res (and no more) must be covered by the input
1127 /// registers.
1128 /// \pre The type of all source operands must be identical.
1129 ///
1130 /// \return a MachineInstrBuilder for the newly created instruction.
1131 MachineInstrBuilder buildConcatVectors(const DstOp &Res,
1132 ArrayRef<Register> Ops);
1133
1134 /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
1135 ///
1136 /// \pre setBasicBlock or setMI must have been called.
1137 /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
1138 /// vector type.
1139 ///
1140 /// \return a MachineInstrBuilder for the newly created instruction.
1141 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1142 const SrcOp &Src1, unsigned Index);
1143
1144 /// Build and insert `Res = G_EXTRACT_SUBVECTOR Src, Idx0`.
1145 ///
1146 /// \pre setBasicBlock or setMI must have been called.
1147 /// \pre \p Res and \p Src must be generic virtual registers with vector type.
1148 ///
1149 /// \return a MachineInstrBuilder for the newly created instruction.
1150 MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src,
1151 unsigned Index);
1152
1153 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1154 const SrcOp &Op, unsigned Index);
1155
1156 /// Build and insert \p Res = G_VSCALE \p MinElts
1157 ///
1158 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1159 /// into \p Res.
1160 ///
1161 /// \pre setBasicBlock or setMI must have been called.
1162 /// \pre \p Res must be a generic virtual register with scalar type.
1163 ///
1164 /// \return a MachineInstrBuilder for the newly created instruction.
1165 MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts);
1166
1167 /// Build and insert \p Res = G_VSCALE \p MinElts
1168 ///
1169 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1170 /// into \p Res.
1171 ///
1172 /// \pre setBasicBlock or setMI must have been called.
1173 /// \pre \p Res must be a generic virtual register with scalar type.
1174 ///
1175 /// \return a MachineInstrBuilder for the newly created instruction.
1176 MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
1177
1178 /// Build and insert \p Res = G_VSCALE \p MinElts
1179 ///
1180 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1181 /// into \p Res.
1182 ///
1183 /// \pre setBasicBlock or setMI must have been called.
1184 /// \pre \p Res must be a generic virtual register with scalar type.
1185 ///
1186 /// \return a MachineInstrBuilder for the newly created instruction.
1187 MachineInstrBuilder buildVScale(const DstOp &Res, const APInt &MinElts);
1188
1189 /// Build and insert a G_INTRINSIC instruction.
1190 ///
1191 /// There are four different opcodes based on combinations of whether the
1192 /// intrinsic has side effects and whether it is convergent. These properties
1193 /// can be specified as explicit parameters, or else they are retrieved from
1194 /// the MCID for the intrinsic.
1195 ///
1196 /// The parameter \p Res provides the Registers or MOs that will be defined by
1197 /// this instruction.
1198 ///
1199 /// \pre setBasicBlock or setMI must have been called.
1200 ///
1201 /// \return a MachineInstrBuilder for the newly created instruction.
1202 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res,
1203 bool HasSideEffects, bool isConvergent);
1204 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res);
1205 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
1206 bool HasSideEffects, bool isConvergent);
1207 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res);
1208
1209 /// Build and insert \p Res = G_FPTRUNC \p Op
1210 ///
1211 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1212 ///
1213 /// \pre setBasicBlock or setMI must have been called.
1214 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1215 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1216 /// \pre \p Res must be smaller than \p Op
1217 ///
1218 /// \return The newly created instruction.
1219 MachineInstrBuilder
1220 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1221 std::optional<unsigned> Flags = std::nullopt);
1222
1223 /// Build and insert \p Res = G_TRUNC \p Op
1224 ///
1225 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1226 /// truncated independently before being packed into the destination.
1227 ///
1228 /// \pre setBasicBlock or setMI must have been called.
1229 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1230 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1231 /// \pre \p Res must be smaller than \p Op
1232 ///
1233 /// \return The newly created instruction.
1234 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1235
1236 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1237 ///
1238 /// \pre setBasicBlock or setMI must have been called.
1239
1240 /// \pre \p Res must be a generic virtual register with scalar or
1241 /// vector type. Typically this starts as s1 or <N x s1>.
1242 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1243 /// same number of elements as \p Res. If \p Res is a scalar,
1244 /// \p Op0 must be either a scalar or pointer.
1245 /// \pre \p Pred must be an integer predicate.
1246 ///
1247 /// \return a MachineInstrBuilder for the newly created instruction.
1248 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
1249 const SrcOp &Op0, const SrcOp &Op1);
1250
1251 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1252 ///
1253 /// \pre setBasicBlock or setMI must have been called.
1254
1255 /// \pre \p Res must be a generic virtual register with scalar or
1256 /// vector type. Typically this starts as s1 or <N x s1>.
1257 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1258 /// same number of elements as \p Res (or scalar, if \p Res is
1259 /// scalar).
1260 /// \pre \p Pred must be a floating-point predicate.
1261 ///
1262 /// \return a MachineInstrBuilder for the newly created instruction.
1263 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
1264 const SrcOp &Op0, const SrcOp &Op1,
1265 std::optional<unsigned> Flags = std::nullopt);
1266
1267 /// Build and insert a \p Res = G_IS_FPCLASS \p Src, \p Mask
1268 MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src,
1269 unsigned Mask) {
1270 return buildInstr(Opc: TargetOpcode::G_IS_FPCLASS, DstOps: {Res},
1271 SrcOps: {Src, SrcOp(static_cast<int64_t>(Mask))});
1272 }
1273
1274 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1275 ///
1276 /// \pre setBasicBlock or setMI must have been called.
1277 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1278 /// with the same type.
1279 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1280 /// vector type. If vector then it must have the same number of
1281 /// elements as the other parameters.
1282 ///
1283 /// \return a MachineInstrBuilder for the newly created instruction.
1284 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1285 const SrcOp &Op0, const SrcOp &Op1,
1286 std::optional<unsigned> Flags = std::nullopt);
1287
1288 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1289 /// \p Elt, \p Idx
1290 ///
1291 /// \pre setBasicBlock or setMI must have been called.
1292 /// \pre \p Res and \p Val must be a generic virtual register
1293 // with the same vector type.
1294 /// \pre \p Elt and \p Idx must be a generic virtual register
1295 /// with scalar type.
1296 ///
1297 /// \return The newly created instruction.
1298 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
1299 const SrcOp &Val,
1300 const SrcOp &Elt,
1301 const SrcOp &Idx);
1302
1303 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1304 ///
1305 /// \pre setBasicBlock or setMI must have been called.
1306 /// \pre \p Res must be a generic virtual register with scalar type.
1307 /// \pre \p Val must be a generic virtual register with vector type.
1308 ///
1309 /// \return The newly created instruction.
1310 MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res,
1311 const SrcOp &Val,
1312 const int Idx) {
1313 auto TLI = getMF().getSubtarget().getTargetLowering();
1314 unsigned VecIdxWidth = TLI->getVectorIdxTy(DL: getDataLayout()).getSizeInBits();
1315 return buildExtractVectorElement(
1316 Res, Val, Idx: buildConstant(Res: LLT::scalar(SizeInBits: VecIdxWidth), Val: Idx));
1317 }
1318
1319 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1320 ///
1321 /// \pre setBasicBlock or setMI must have been called.
1322 /// \pre \p Res must be a generic virtual register with scalar type.
1323 /// \pre \p Val must be a generic virtual register with vector type.
1324 /// \pre \p Idx must be a generic virtual register with scalar type.
1325 ///
1326 /// \return The newly created instruction.
1327 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
1328 const SrcOp &Val,
1329 const SrcOp &Idx);
1330
1331 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1332 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1333 ///
1334 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1335 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1336 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1337 ///
1338 /// \pre setBasicBlock or setMI must have been called.
1339 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1340 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1341 /// will be assigned 0 on failure and 1 on success.
1342 /// \pre \p Addr must be a generic virtual register with pointer type.
1343 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1344 /// registers of the same type.
1345 ///
1346 /// \return a MachineInstrBuilder for the newly created instruction.
1347 MachineInstrBuilder
1348 buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes,
1349 const SrcOp &Addr, const SrcOp &CmpVal,
1350 const SrcOp &NewVal, MachineMemOperand &MMO);
1351
1352 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1353 /// MMO`.
1354 ///
1355 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1356 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1357 /// Addr in \p Res.
1358 ///
1359 /// \pre setBasicBlock or setMI must have been called.
1360 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1361 /// \pre \p Addr must be a generic virtual register with pointer type.
1362 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1363 /// registers of the same type.
1364 ///
1365 /// \return a MachineInstrBuilder for the newly created instruction.
1366 MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes,
1367 const SrcOp &Addr, const SrcOp &CmpVal,
1368 const SrcOp &NewVal,
1369 MachineMemOperand &MMO);
1370
1371 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1372 ///
1373 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1374 /// original value from \p Addr in \p OldValRes. The modification is
1375 /// determined by the opcode.
1376 ///
1377 /// \pre setBasicBlock or setMI must have been called.
1378 /// \pre \p OldValRes must be a generic virtual register.
1379 /// \pre \p Addr must be a generic virtual register with pointer type.
1380 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1381 /// same type.
1382 ///
1383 /// \return a MachineInstrBuilder for the newly created instruction.
1384 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1385 const SrcOp &Addr, const SrcOp &Val,
1386 MachineMemOperand &MMO);
1387
1388 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1389 ///
1390 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1391 /// value from \p Addr in \p OldValRes.
1392 ///
1393 /// \pre setBasicBlock or setMI must have been called.
1394 /// \pre \p OldValRes must be a generic virtual register.
1395 /// \pre \p Addr must be a generic virtual register with pointer type.
1396 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1397 /// same type.
1398 ///
1399 /// \return a MachineInstrBuilder for the newly created instruction.
1400 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1401 Register Val, MachineMemOperand &MMO);
1402
1403 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1404 ///
1405 /// Atomically replace the value at \p Addr with the addition of \p Val and
1406 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1407 ///
1408 /// \pre setBasicBlock or setMI must have been called.
1409 /// \pre \p OldValRes must be a generic virtual register.
1410 /// \pre \p Addr must be a generic virtual register with pointer type.
1411 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1412 /// same type.
1413 ///
1414 /// \return a MachineInstrBuilder for the newly created instruction.
1415 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1416 Register Val, MachineMemOperand &MMO);
1417
1418 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1419 ///
1420 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1421 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1422 ///
1423 /// \pre setBasicBlock or setMI must have been called.
1424 /// \pre \p OldValRes must be a generic virtual register.
1425 /// \pre \p Addr must be a generic virtual register with pointer type.
1426 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1427 /// same type.
1428 ///
1429 /// \return a MachineInstrBuilder for the newly created instruction.
1430 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1431 Register Val, MachineMemOperand &MMO);
1432
1433 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1434 ///
1435 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1436 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1437 ///
1438 /// \pre setBasicBlock or setMI must have been called.
1439 /// \pre \p OldValRes must be a generic virtual register.
1440 /// \pre \p Addr must be a generic virtual register with pointer type.
1441 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1442 /// same type.
1443 ///
1444 /// \return a MachineInstrBuilder for the newly created instruction.
1445 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1446 Register Val, MachineMemOperand &MMO);
1447
1448 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1449 ///
1450 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1451 /// and the original value. Puts the original value from \p Addr in \p
1452 /// OldValRes.
1453 ///
1454 /// \pre setBasicBlock or setMI must have been called.
1455 /// \pre \p OldValRes must be a generic virtual register.
1456 /// \pre \p Addr must be a generic virtual register with pointer type.
1457 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1458 /// same type.
1459 ///
1460 /// \return a MachineInstrBuilder for the newly created instruction.
1461 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1462 Register Val, MachineMemOperand &MMO);
1463
1464 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1465 ///
1466 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1467 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1468 ///
1469 /// \pre setBasicBlock or setMI must have been called.
1470 /// \pre \p OldValRes must be a generic virtual register.
1471 /// \pre \p Addr must be a generic virtual register with pointer type.
1472 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1473 /// same type.
1474 ///
1475 /// \return a MachineInstrBuilder for the newly created instruction.
1476 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1477 Register Val, MachineMemOperand &MMO);
1478
1479 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1480 ///
1481 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1482 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1483 ///
1484 /// \pre setBasicBlock or setMI must have been called.
1485 /// \pre \p OldValRes must be a generic virtual register.
1486 /// \pre \p Addr must be a generic virtual register with pointer type.
1487 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1488 /// same type.
1489 ///
1490 /// \return a MachineInstrBuilder for the newly created instruction.
1491 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1492 Register Val, MachineMemOperand &MMO);
1493
1494 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1495 ///
1496 /// Atomically replace the value at \p Addr with the signed maximum of \p
1497 /// Val and the original value. Puts the original value from \p Addr in \p
1498 /// OldValRes.
1499 ///
1500 /// \pre setBasicBlock or setMI must have been called.
1501 /// \pre \p OldValRes must be a generic virtual register.
1502 /// \pre \p Addr must be a generic virtual register with pointer type.
1503 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1504 /// same type.
1505 ///
1506 /// \return a MachineInstrBuilder for the newly created instruction.
1507 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1508 Register Val, MachineMemOperand &MMO);
1509
1510 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1511 ///
1512 /// Atomically replace the value at \p Addr with the signed minimum of \p
1513 /// Val and the original value. Puts the original value from \p Addr in \p
1514 /// OldValRes.
1515 ///
1516 /// \pre setBasicBlock or setMI must have been called.
1517 /// \pre \p OldValRes must be a generic virtual register.
1518 /// \pre \p Addr must be a generic virtual register with pointer type.
1519 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1520 /// same type.
1521 ///
1522 /// \return a MachineInstrBuilder for the newly created instruction.
1523 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1524 Register Val, MachineMemOperand &MMO);
1525
1526 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1527 ///
1528 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1529 /// Val and the original value. Puts the original value from \p Addr in \p
1530 /// OldValRes.
1531 ///
1532 /// \pre setBasicBlock or setMI must have been called.
1533 /// \pre \p OldValRes must be a generic virtual register.
1534 /// \pre \p Addr must be a generic virtual register with pointer type.
1535 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1536 /// same type.
1537 ///
1538 /// \return a MachineInstrBuilder for the newly created instruction.
1539 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1540 Register Val, MachineMemOperand &MMO);
1541
1542 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1543 ///
1544 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1545 /// Val and the original value. Puts the original value from \p Addr in \p
1546 /// OldValRes.
1547 ///
1548 /// \pre setBasicBlock or setMI must have been called.
1549 /// \pre \p OldValRes must be a generic virtual register.
1550 /// \pre \p Addr must be a generic virtual register with pointer type.
1551 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1552 /// same type.
1553 ///
1554 /// \return a MachineInstrBuilder for the newly created instruction.
1555 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1556 Register Val, MachineMemOperand &MMO);
1557
1558 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1559 MachineInstrBuilder buildAtomicRMWFAdd(
1560 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1561 MachineMemOperand &MMO);
1562
1563 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1564 MachineInstrBuilder buildAtomicRMWFSub(
1565 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1566 MachineMemOperand &MMO);
1567
1568 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1569 ///
1570 /// Atomically replace the value at \p Addr with the floating point maximum of
1571 /// \p Val and the original value. Puts the original value from \p Addr in \p
1572 /// OldValRes.
1573 ///
1574 /// \pre setBasicBlock or setMI must have been called.
1575 /// \pre \p OldValRes must be a generic virtual register.
1576 /// \pre \p Addr must be a generic virtual register with pointer type.
1577 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1578 /// same type.
1579 ///
1580 /// \return a MachineInstrBuilder for the newly created instruction.
1581 MachineInstrBuilder buildAtomicRMWFMax(
1582 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1583 MachineMemOperand &MMO);
1584
1585 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1586 ///
1587 /// Atomically replace the value at \p Addr with the floating point minimum of
1588 /// \p Val and the original value. Puts the original value from \p Addr in \p
1589 /// OldValRes.
1590 ///
1591 /// \pre setBasicBlock or setMI must have been called.
1592 /// \pre \p OldValRes must be a generic virtual register.
1593 /// \pre \p Addr must be a generic virtual register with pointer type.
1594 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1595 /// same type.
1596 ///
1597 /// \return a MachineInstrBuilder for the newly created instruction.
1598 MachineInstrBuilder buildAtomicRMWFMin(
1599 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1600 MachineMemOperand &MMO);
1601
1602 /// Build and insert `G_FENCE Ordering, Scope`.
1603 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1604
1605 /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType
1606 MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW,
1607 unsigned Locality, unsigned CacheType,
1608 MachineMemOperand &MMO);
1609
1610 /// Build and insert \p Dst = G_FREEZE \p Src
1611 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1612 return buildInstr(Opc: TargetOpcode::G_FREEZE, DstOps: {Dst}, SrcOps: {Src});
1613 }
1614
1615 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1616 ///
1617 /// G_BLOCK_ADDR computes the address of a basic block.
1618 ///
1619 /// \pre setBasicBlock or setMI must have been called.
1620 /// \pre \p Res must be a generic virtual register of a pointer type.
1621 ///
1622 /// \return The newly created instruction.
1623 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1624
1625 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1626 ///
1627 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1628 /// truncated to their width.
1629 ///
1630 /// \pre setBasicBlock or setMI must have been called.
1631 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1632 /// with the same (scalar or vector) type).
1633 ///
1634 /// \return a MachineInstrBuilder for the newly created instruction.
1635
1636 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1637 const SrcOp &Src1,
1638 std::optional<unsigned> Flags = std::nullopt) {
1639 return buildInstr(Opc: TargetOpcode::G_ADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1640 }
1641
1642 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1643 ///
1644 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1645 /// \p Op1, truncated to their width.
1646 ///
1647 /// \pre setBasicBlock or setMI must have been called.
1648 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1649 /// with the same (scalar or vector) type).
1650 ///
1651 /// \return a MachineInstrBuilder for the newly created instruction.
1652
1653 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1654 const SrcOp &Src1,
1655 std::optional<unsigned> Flags = std::nullopt) {
1656 return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1657 }
1658
1659 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1660 ///
1661 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1662 /// truncated to their width.
1663 ///
1664 /// \pre setBasicBlock or setMI must have been called.
1665 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1666 /// with the same (scalar or vector) type).
1667 ///
1668 /// \return a MachineInstrBuilder for the newly created instruction.
1669 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1670 const SrcOp &Src1,
1671 std::optional<unsigned> Flags = std::nullopt) {
1672 return buildInstr(Opc: TargetOpcode::G_MUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1673 }
1674
1675 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1676 const SrcOp &Src1,
1677 std::optional<unsigned> Flags = std::nullopt) {
1678 return buildInstr(Opc: TargetOpcode::G_UMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1679 }
1680
1681 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1682 const SrcOp &Src1,
1683 std::optional<unsigned> Flags = std::nullopt) {
1684 return buildInstr(Opc: TargetOpcode::G_SMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1685 }
1686
1687 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1688 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1689 const SrcOp &Src1,
1690 std::optional<unsigned> Flags = std::nullopt) {
1691 return buildInstr(Opc: TargetOpcode::G_UREM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1692 }
1693
1694 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1695 const SrcOp &Src1,
1696 std::optional<unsigned> Flags = std::nullopt) {
1697 return buildInstr(Opc: TargetOpcode::G_FMUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1698 }
1699
1700 MachineInstrBuilder
1701 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1702 std::optional<unsigned> Flags = std::nullopt) {
1703 return buildInstr(Opc: TargetOpcode::G_FMINNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1704 }
1705
1706 MachineInstrBuilder
1707 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1708 std::optional<unsigned> Flags = std::nullopt) {
1709 return buildInstr(Opc: TargetOpcode::G_FMAXNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1710 }
1711
1712 MachineInstrBuilder
1713 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1714 std::optional<unsigned> Flags = std::nullopt) {
1715 return buildInstr(Opc: TargetOpcode::G_FMINNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1716 }
1717
1718 MachineInstrBuilder
1719 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1720 std::optional<unsigned> Flags = std::nullopt) {
1721 return buildInstr(Opc: TargetOpcode::G_FMAXNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1722 }
1723
1724 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1725 const SrcOp &Src1,
1726 std::optional<unsigned> Flags = std::nullopt) {
1727 return buildInstr(Opc: TargetOpcode::G_SHL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1728 }
1729
1730 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1731 const SrcOp &Src1,
1732 std::optional<unsigned> Flags = std::nullopt) {
1733 return buildInstr(Opc: TargetOpcode::G_LSHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1734 }
1735
1736 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1737 const SrcOp &Src1,
1738 std::optional<unsigned> Flags = std::nullopt) {
1739 return buildInstr(Opc: TargetOpcode::G_ASHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1740 }
1741
1742 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1743 ///
1744 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1745 /// Op1.
1746 ///
1747 /// \pre setBasicBlock or setMI must have been called.
1748 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1749 /// with the same (scalar or vector) type).
1750 ///
1751 /// \return a MachineInstrBuilder for the newly created instruction.
1752
1753 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1754 const SrcOp &Src1) {
1755 return buildInstr(Opc: TargetOpcode::G_AND, DstOps: {Dst}, SrcOps: {Src0, Src1});
1756 }
1757
1758 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1759 ///
1760 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1761 /// Op1.
1762 ///
1763 /// \pre setBasicBlock or setMI must have been called.
1764 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1765 /// with the same (scalar or vector) type).
1766 ///
1767 /// \return a MachineInstrBuilder for the newly created instruction.
1768 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1769 const SrcOp &Src1,
1770 std::optional<unsigned> Flags = std::nullopt) {
1771 return buildInstr(Opc: TargetOpcode::G_OR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1772 }
1773
1774 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1775 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1776 const SrcOp &Src1) {
1777 return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, Src1});
1778 }
1779
1780 /// Build and insert a bitwise not,
1781 /// \p NegOne = G_CONSTANT -1
1782 /// \p Res = G_OR \p Op0, NegOne
1783 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1784 auto NegOne = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: -1);
1785 return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, NegOne});
1786 }
1787
1788 /// Build and insert integer negation
1789 /// \p Zero = G_CONSTANT 0
1790 /// \p Res = G_SUB Zero, \p Op0
1791 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1792 auto Zero = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: 0);
1793 return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Zero, Src0});
1794 }
1795
1796 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1797 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1798 return buildInstr(Opc: TargetOpcode::G_CTPOP, DstOps: {Dst}, SrcOps: {Src0});
1799 }
1800
1801 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1802 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1803 return buildInstr(Opc: TargetOpcode::G_CTLZ, DstOps: {Dst}, SrcOps: {Src0});
1804 }
1805
1806 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1807 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1808 return buildInstr(Opc: TargetOpcode::G_CTLZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0});
1809 }
1810
1811 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1812 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1813 return buildInstr(Opc: TargetOpcode::G_CTTZ, DstOps: {Dst}, SrcOps: {Src0});
1814 }
1815
1816 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1817 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1818 return buildInstr(Opc: TargetOpcode::G_CTTZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0});
1819 }
1820
1821 /// Build and insert \p Dst = G_BSWAP \p Src0
1822 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1823 return buildInstr(Opc: TargetOpcode::G_BSWAP, DstOps: {Dst}, SrcOps: {Src0});
1824 }
1825
1826 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1827 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1828 const SrcOp &Src1,
1829 std::optional<unsigned> Flags = std::nullopt) {
1830 return buildInstr(Opc: TargetOpcode::G_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1831 }
1832
1833 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1834 MachineInstrBuilder
1835 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1836 std::optional<unsigned> Flags = std::nullopt) {
1837 return buildInstr(Opc: TargetOpcode::G_STRICT_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1838 }
1839
1840 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1841 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1842 const SrcOp &Src1,
1843 std::optional<unsigned> Flags = std::nullopt) {
1844 return buildInstr(Opc: TargetOpcode::G_FSUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1845 }
1846
1847 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1848 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1849 const SrcOp &Src1,
1850 std::optional<unsigned> Flags = std::nullopt) {
1851 return buildInstr(Opc: TargetOpcode::G_FDIV, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1852 }
1853
1854 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1855 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1856 const SrcOp &Src1, const SrcOp &Src2,
1857 std::optional<unsigned> Flags = std::nullopt) {
1858 return buildInstr(Opc: TargetOpcode::G_FMA, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags);
1859 }
1860
1861 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1862 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1863 const SrcOp &Src1, const SrcOp &Src2,
1864 std::optional<unsigned> Flags = std::nullopt) {
1865 return buildInstr(Opc: TargetOpcode::G_FMAD, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags);
1866 }
1867
1868 /// Build and insert \p Res = G_FNEG \p Op0
1869 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1870 std::optional<unsigned> Flags = std::nullopt) {
1871 return buildInstr(Opc: TargetOpcode::G_FNEG, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1872 }
1873
1874 /// Build and insert \p Res = G_FABS \p Op0
1875 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1876 std::optional<unsigned> Flags = std::nullopt) {
1877 return buildInstr(Opc: TargetOpcode::G_FABS, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1878 }
1879
1880 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1881 MachineInstrBuilder
1882 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1883 std::optional<unsigned> Flags = std::nullopt) {
1884 return buildInstr(Opc: TargetOpcode::G_FCANONICALIZE, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1885 }
1886
1887 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1888 MachineInstrBuilder
1889 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1890 std::optional<unsigned> Flags = std::nullopt) {
1891 return buildInstr(Opc: TargetOpcode::G_INTRINSIC_TRUNC, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1892 }
1893
1894 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1895 MachineInstrBuilder
1896 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1897 std::optional<unsigned> Flags = std::nullopt) {
1898 return buildInstr(Opc: TargetOpcode::G_FFLOOR, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1899 }
1900
1901 /// Build and insert \p Dst = G_FLOG \p Src
1902 MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1903 std::optional<unsigned> Flags = std::nullopt) {
1904 return buildInstr(Opc: TargetOpcode::G_FLOG, DstOps: {Dst}, SrcOps: {Src}, Flags);
1905 }
1906
1907 /// Build and insert \p Dst = G_FLOG2 \p Src
1908 MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1909 std::optional<unsigned> Flags = std::nullopt) {
1910 return buildInstr(Opc: TargetOpcode::G_FLOG2, DstOps: {Dst}, SrcOps: {Src}, Flags);
1911 }
1912
1913 /// Build and insert \p Dst = G_FEXP2 \p Src
1914 MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1915 std::optional<unsigned> Flags = std::nullopt) {
1916 return buildInstr(Opc: TargetOpcode::G_FEXP2, DstOps: {Dst}, SrcOps: {Src}, Flags);
1917 }
1918
1919 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1920 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1921 const SrcOp &Src1,
1922 std::optional<unsigned> Flags = std::nullopt) {
1923 return buildInstr(Opc: TargetOpcode::G_FPOW, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1924 }
1925
1926 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
1927 MachineInstrBuilder
1928 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1929 std::optional<unsigned> Flags = std::nullopt) {
1930 return buildInstr(Opc: TargetOpcode::G_FLDEXP, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1931 }
1932
1933 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src
1934 MachineInstrBuilder
1935 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src,
1936 std::optional<unsigned> Flags = std::nullopt) {
1937 return buildInstr(Opc: TargetOpcode::G_FFREXP, DstOps: {Fract, Exp}, SrcOps: {Src}, Flags);
1938 }
1939
1940 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1941 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0,
1942 const SrcOp &Src1) {
1943 return buildInstr(Opc: TargetOpcode::G_FCOPYSIGN, DstOps: {Dst}, SrcOps: {Src0, Src1});
1944 }
1945
1946 /// Build and insert \p Res = G_UITOFP \p Src0
1947 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1948 return buildInstr(Opc: TargetOpcode::G_UITOFP, DstOps: {Dst}, SrcOps: {Src0});
1949 }
1950
1951 /// Build and insert \p Res = G_SITOFP \p Src0
1952 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1953 return buildInstr(Opc: TargetOpcode::G_SITOFP, DstOps: {Dst}, SrcOps: {Src0});
1954 }
1955
1956 /// Build and insert \p Res = G_FPTOUI \p Src0
1957 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1958 return buildInstr(Opc: TargetOpcode::G_FPTOUI, DstOps: {Dst}, SrcOps: {Src0});
1959 }
1960
1961 /// Build and insert \p Res = G_FPTOSI \p Src0
1962 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1963 return buildInstr(Opc: TargetOpcode::G_FPTOSI, DstOps: {Dst}, SrcOps: {Src0});
1964 }
1965
1966 /// Build and insert \p Dst = G_INTRINSIC_ROUNDEVEN \p Src0, \p Src1
1967 MachineInstrBuilder
1968 buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0,
1969 std::optional<unsigned> Flags = std::nullopt) {
1970 return buildInstr(Opc: TargetOpcode::G_INTRINSIC_ROUNDEVEN, DstOps: {Dst}, SrcOps: {Src0},
1971 Flags);
1972 }
1973
1974 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1975 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1976 const SrcOp &Src1) {
1977 return buildInstr(Opc: TargetOpcode::G_SMIN, DstOps: {Dst}, SrcOps: {Src0, Src1});
1978 }
1979
1980 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1981 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1982 const SrcOp &Src1) {
1983 return buildInstr(Opc: TargetOpcode::G_SMAX, DstOps: {Dst}, SrcOps: {Src0, Src1});
1984 }
1985
1986 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1987 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1988 const SrcOp &Src1) {
1989 return buildInstr(Opc: TargetOpcode::G_UMIN, DstOps: {Dst}, SrcOps: {Src0, Src1});
1990 }
1991
1992 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1993 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1994 const SrcOp &Src1) {
1995 return buildInstr(Opc: TargetOpcode::G_UMAX, DstOps: {Dst}, SrcOps: {Src0, Src1});
1996 }
1997
1998 /// Build and insert \p Dst = G_ABS \p Src
1999 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
2000 return buildInstr(Opc: TargetOpcode::G_ABS, DstOps: {Dst}, SrcOps: {Src});
2001 }
2002
2003 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
2004 ///
2005 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
2006 /// the jump table index \p JTI.
2007 ///
2008 /// \return a MachineInstrBuilder for the newly created instruction.
2009 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
2010
2011 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
2012 ///
2013 /// \p ScalarIn is the scalar accumulator input to start the sequential
2014 /// reduction operation of \p VecIn.
2015 MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst,
2016 const SrcOp &ScalarIn,
2017 const SrcOp &VecIn) {
2018 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FADD, DstOps: {Dst},
2019 SrcOps: {ScalarIn, {VecIn}});
2020 }
2021
2022 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
2023 ///
2024 /// \p ScalarIn is the scalar accumulator input to start the sequential
2025 /// reduction operation of \p VecIn.
2026 MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst,
2027 const SrcOp &ScalarIn,
2028 const SrcOp &VecIn) {
2029 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FMUL, DstOps: {Dst},
2030 SrcOps: {ScalarIn, {VecIn}});
2031 }
2032
2033 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
2034 ///
2035 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2036 /// \p VecIn.
2037 MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst,
2038 const SrcOp &ScalarIn,
2039 const SrcOp &VecIn) {
2040 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FADD, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn});
2041 }
2042
2043 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
2044 ///
2045 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2046 /// \p VecIn.
2047 MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst,
2048 const SrcOp &ScalarIn,
2049 const SrcOp &VecIn) {
2050 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMUL, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn});
2051 }
2052
2053 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
2054 MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) {
2055 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAX, DstOps: {Dst}, SrcOps: {Src});
2056 }
2057
2058 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
2059 MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) {
2060 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMIN, DstOps: {Dst}, SrcOps: {Src});
2061 }
2062
2063 /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
2064 MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst,
2065 const SrcOp &Src) {
2066 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAXIMUM, DstOps: {Dst}, SrcOps: {Src});
2067 }
2068
2069 /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
2070 MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst,
2071 const SrcOp &Src) {
2072 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMINIMUM, DstOps: {Dst}, SrcOps: {Src});
2073 }
2074
2075 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
2076 MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) {
2077 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_ADD, DstOps: {Dst}, SrcOps: {Src});
2078 }
2079
2080 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
2081 MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) {
2082 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_MUL, DstOps: {Dst}, SrcOps: {Src});
2083 }
2084
2085 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
2086 MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) {
2087 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_AND, DstOps: {Dst}, SrcOps: {Src});
2088 }
2089
2090 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
2091 MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) {
2092 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_OR, DstOps: {Dst}, SrcOps: {Src});
2093 }
2094
2095 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
2096 MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) {
2097 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_XOR, DstOps: {Dst}, SrcOps: {Src});
2098 }
2099
2100 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
2101 MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) {
2102 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMAX, DstOps: {Dst}, SrcOps: {Src});
2103 }
2104
2105 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
2106 MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) {
2107 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMIN, DstOps: {Dst}, SrcOps: {Src});
2108 }
2109
2110 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
2111 MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) {
2112 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMAX, DstOps: {Dst}, SrcOps: {Src});
2113 }
2114
2115 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
2116 MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) {
2117 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMIN, DstOps: {Dst}, SrcOps: {Src});
2118 }
2119
2120 /// Build and insert G_MEMCPY or G_MEMMOVE
2121 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
2122 const SrcOp &SrcPtr,
2123 const SrcOp &Size,
2124 MachineMemOperand &DstMMO,
2125 MachineMemOperand &SrcMMO) {
2126 auto MIB = buildInstr(
2127 Opc: Opcode, DstOps: {}, SrcOps: {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2128 MIB.addMemOperand(MMO: &DstMMO);
2129 MIB.addMemOperand(MMO: &SrcMMO);
2130 return MIB;
2131 }
2132
2133 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2134 const SrcOp &Size, MachineMemOperand &DstMMO,
2135 MachineMemOperand &SrcMMO) {
2136 return buildMemTransferInst(Opcode: TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2137 DstMMO, SrcMMO);
2138 }
2139
2140 /// Build and insert G_TRAP or G_DEBUGTRAP
2141 MachineInstrBuilder buildTrap(bool Debug = false) {
2142 return buildInstr(Opcode: Debug ? TargetOpcode::G_DEBUGTRAP : TargetOpcode::G_TRAP);
2143 }
2144
2145 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2146 MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
2147 const SrcOp &LSB, const SrcOp &Width) {
2148 return buildInstr(Opc: TargetOpcode::G_SBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width});
2149 }
2150
2151 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2152 MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
2153 const SrcOp &LSB, const SrcOp &Width) {
2154 return buildInstr(Opc: TargetOpcode::G_UBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width});
2155 }
2156
2157 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2158 MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src,
2159 const SrcOp &Amt) {
2160 return buildInstr(Opc: TargetOpcode::G_ROTR, DstOps: {Dst}, SrcOps: {Src, Amt});
2161 }
2162
2163 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2164 MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src,
2165 const SrcOp &Amt) {
2166 return buildInstr(Opc: TargetOpcode::G_ROTL, DstOps: {Dst}, SrcOps: {Src, Amt});
2167 }
2168
2169 /// Build and insert \p Dst = G_BITREVERSE \p Src
2170 MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) {
2171 return buildInstr(Opc: TargetOpcode::G_BITREVERSE, DstOps: {Dst}, SrcOps: {Src});
2172 }
2173
2174 virtual MachineInstrBuilder
2175 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2176 std::optional<unsigned> Flags = std::nullopt);
2177};
2178
2179} // End namespace llvm.
2180#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
2181

source code of llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h