1 | //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the interfaces that Hexagon uses to lower LLVM code into a |
10 | // selection DAG. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H |
15 | #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H |
16 | |
17 | #include "Hexagon.h" |
18 | #include "MCTargetDesc/HexagonMCTargetDesc.h" |
19 | #include "llvm/ADT/StringRef.h" |
20 | #include "llvm/CodeGen/ISDOpcodes.h" |
21 | #include "llvm/CodeGen/SelectionDAGNodes.h" |
22 | #include "llvm/CodeGen/TargetLowering.h" |
23 | #include "llvm/CodeGen/ValueTypes.h" |
24 | #include "llvm/CodeGenTypes/MachineValueType.h" |
25 | #include "llvm/IR/CallingConv.h" |
26 | #include "llvm/IR/InlineAsm.h" |
27 | #include <cstdint> |
28 | #include <utility> |
29 | |
30 | namespace llvm { |
31 | |
32 | namespace HexagonISD { |
33 | |
34 | enum NodeType : unsigned { |
35 | OP_BEGIN = ISD::BUILTIN_OP_END, |
36 | |
37 | CONST32 = OP_BEGIN, |
38 | CONST32_GP, // For marking data present in GP. |
39 | ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). |
40 | SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). |
41 | ALLOCA, |
42 | |
43 | AT_GOT, // Index in GOT. |
44 | AT_PCREL, // Offset relative to PC. |
45 | |
46 | CALL, // Function call. |
47 | CALLnr, // Function call that does not return. |
48 | CALLR, |
49 | |
50 | RET_GLUE, // Return with a glue operand. |
51 | BARRIER, // Memory barrier. |
52 | JT, // Jump table. |
53 | CP, // Constant pool. |
54 | |
55 | COMBINE, |
56 | VASL, // Vector shifts by a scalar value |
57 | VASR, |
58 | VLSR, |
59 | MFSHL, // Funnel shifts with the shift amount guaranteed to be |
60 | MFSHR, // within the range of the bit width of the element. |
61 | |
62 | SSAT, // Signed saturate. |
63 | USAT, // Unsigned saturate. |
64 | SMUL_LOHI, // Same as ISD::SMUL_LOHI, but opaque to the combiner. |
65 | UMUL_LOHI, // Same as ISD::UMUL_LOHI, but opaque to the combiner. |
66 | // We want to legalize MULH[SU] to [SU]MUL_LOHI, but the |
67 | // combiner will keep rewriting it back to MULH[SU]. |
68 | USMUL_LOHI, // Like SMUL_LOHI, but unsigned*signed. |
69 | |
70 | TSTBIT, |
71 | INSERT, |
72 | , |
73 | , |
74 | VINSERTW0, |
75 | VROR, |
76 | TC_RETURN, |
77 | EH_RETURN, |
78 | DCFETCH, |
79 | READCYCLE, |
80 | PTRUE, |
81 | PFALSE, |
82 | D2P, // Convert 8-byte value to 8-bit predicate register. [*] |
83 | P2D, // Convert 8-bit predicate register to 8-byte value. [*] |
84 | V2Q, // Convert HVX vector to a vector predicate reg. [*] |
85 | Q2V, // Convert vector predicate to an HVX vector. [*] |
86 | // [*] The equivalence is defined as "Q <=> (V != 0)", |
87 | // where the != operation compares bytes. |
88 | // Note: V != 0 is implemented as V >u 0. |
89 | QCAT, |
90 | QTRUE, |
91 | QFALSE, |
92 | |
93 | TL_EXTEND, // Wrappers for ISD::*_EXTEND and ISD::TRUNCATE to prevent DAG |
94 | TL_TRUNCATE, // from auto-folding operations, e.g. |
95 | // (i32 ext (i16 ext i8)) would be folded to (i32 ext i8). |
96 | // To simplify the type legalization, we want to keep these |
97 | // single steps separate during type legalization. |
98 | // TL_[EXTEND|TRUNCATE] Inp, i128 _, i32 Opc |
99 | // * Inp is the original input to extend/truncate, |
100 | // * _ is a dummy operand with an illegal type (can be undef), |
101 | // * Opc is the original opcode. |
102 | // The legalization process (in Hexagon lowering code) will |
103 | // first deal with the "real" types (i.e. Inp and the result), |
104 | // and once all of them are processed, the wrapper node will |
105 | // be replaced with the original ISD node. The dummy illegal |
106 | // operand is there to make sure that the legalization hooks |
107 | // are called again after everything else is legal, giving |
108 | // us the opportunity to undo the wrapping. |
109 | |
110 | TYPECAST, // No-op that's used to convert between different legal |
111 | // types in a register. |
112 | VALIGN, // Align two vectors (in Op0, Op1) to one that would have |
113 | // been loaded from address in Op2. |
114 | VALIGNADDR, // Align vector address: Op0 & -Op1, except when it is |
115 | // an address in a vector load, then it's a no-op. |
116 | ISEL, // Marker for nodes that were created during ISel, and |
117 | // which need explicit selection (would have been left |
118 | // unselected otherwise). |
119 | OP_END |
120 | }; |
121 | |
122 | } // end namespace HexagonISD |
123 | |
124 | class HexagonSubtarget; |
125 | |
126 | class HexagonTargetLowering : public TargetLowering { |
127 | int VarArgsFrameOffset; // Frame offset to start of varargs area. |
128 | const HexagonTargetMachine &HTM; |
129 | const HexagonSubtarget &Subtarget; |
130 | |
131 | public: |
132 | explicit HexagonTargetLowering(const TargetMachine &TM, |
133 | const HexagonSubtarget &ST); |
134 | |
135 | /// IsEligibleForTailCallOptimization - Check whether the call is eligible |
136 | /// for tail call optimization. Targets which want to do tail call |
137 | /// optimization should implement this function. |
138 | bool IsEligibleForTailCallOptimization(SDValue Callee, |
139 | CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, |
140 | bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, |
141 | const SmallVectorImpl<SDValue> &OutVals, |
142 | const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; |
143 | |
144 | bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, |
145 | MachineFunction &MF, |
146 | unsigned Intrinsic) const override; |
147 | |
148 | bool isTruncateFree(Type *Ty1, Type *Ty2) const override; |
149 | bool isTruncateFree(EVT VT1, EVT VT2) const override; |
150 | |
151 | bool isCheapToSpeculateCttz(Type *) const override { return true; } |
152 | bool isCheapToSpeculateCtlz(Type *) const override { return true; } |
153 | bool isCtlzFast() const override { return true; } |
154 | |
155 | bool hasBitTest(SDValue X, SDValue Y) const override; |
156 | |
157 | bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; |
158 | |
159 | /// Return true if an FMA operation is faster than a pair of mul and add |
160 | /// instructions. fmuladd intrinsics will be expanded to FMAs when this |
161 | /// method returns true (and FMAs are legal), otherwise fmuladd is |
162 | /// expanded to mul + add. |
163 | bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, |
164 | EVT) const override; |
165 | |
166 | // Should we expand the build vector with shuffles? |
167 | bool shouldExpandBuildVectorWithShuffles(EVT VT, |
168 | unsigned DefinedValues) const override; |
169 | bool (EVT ResVT, EVT SrcVT, |
170 | unsigned Index) const override; |
171 | |
172 | bool isTargetCanonicalConstantNode(SDValue Op) const override; |
173 | |
174 | bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override; |
175 | LegalizeTypeAction getPreferredVectorAction(MVT VT) const override; |
176 | LegalizeAction getCustomOperationAction(SDNode &Op) const override; |
177 | |
178 | SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |
179 | void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, |
180 | SelectionDAG &DAG) const override; |
181 | void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, |
182 | SelectionDAG &DAG) const override; |
183 | |
184 | const char *getTargetNodeName(unsigned Opcode) const override; |
185 | |
186 | SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; |
187 | SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; |
188 | SDValue (SDValue Op, SelectionDAG &DAG) const; |
189 | SDValue (SDValue Op, SelectionDAG &DAG) const; |
190 | SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; |
191 | SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; |
192 | SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; |
193 | SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const; |
194 | SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; |
195 | SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; |
196 | SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const; |
197 | SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; |
198 | SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const; |
199 | SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const; |
200 | SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const; |
201 | SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const; |
202 | SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const; |
203 | SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const; |
204 | |
205 | SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; |
206 | SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; |
207 | SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; |
208 | SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; |
209 | SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; |
210 | SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; |
211 | SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; |
212 | SDValue |
213 | LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
214 | const SmallVectorImpl<ISD::InputArg> &Ins, |
215 | const SDLoc &dl, SelectionDAG &DAG, |
216 | SmallVectorImpl<SDValue> &InVals) const override; |
217 | SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; |
218 | SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; |
219 | SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; |
220 | SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, |
221 | SelectionDAG &DAG) const; |
222 | SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, |
223 | SelectionDAG &DAG) const; |
224 | SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, |
225 | SelectionDAG &DAG) const; |
226 | SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, |
227 | GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, |
228 | unsigned ReturnReg, unsigned char OperandGlues) const; |
229 | SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; |
230 | |
231 | SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, |
232 | SmallVectorImpl<SDValue> &InVals) const override; |
233 | SDValue LowerCallResult(SDValue Chain, SDValue InGlue, |
234 | CallingConv::ID CallConv, bool isVarArg, |
235 | const SmallVectorImpl<ISD::InputArg> &Ins, |
236 | const SDLoc &dl, SelectionDAG &DAG, |
237 | SmallVectorImpl<SDValue> &InVals, |
238 | const SmallVectorImpl<SDValue> &OutVals, |
239 | SDValue Callee) const; |
240 | |
241 | SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; |
242 | SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; |
243 | SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; |
244 | SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; |
245 | SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; |
246 | |
247 | bool CanLowerReturn(CallingConv::ID CallConv, |
248 | MachineFunction &MF, bool isVarArg, |
249 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
250 | LLVMContext &Context) const override; |
251 | |
252 | SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, |
253 | const SmallVectorImpl<ISD::OutputArg> &Outs, |
254 | const SmallVectorImpl<SDValue> &OutVals, |
255 | const SDLoc &dl, SelectionDAG &DAG) const override; |
256 | |
257 | SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; |
258 | |
259 | bool mayBeEmittedAsTailCall(const CallInst *CI) const override; |
260 | |
261 | Register getRegisterByName(const char* RegName, LLT VT, |
262 | const MachineFunction &MF) const override; |
263 | |
264 | /// If a physical register, this returns the register that receives the |
265 | /// exception address on entry to an EH pad. |
266 | Register |
267 | getExceptionPointerRegister(const Constant *PersonalityFn) const override { |
268 | return Hexagon::R0; |
269 | } |
270 | |
271 | /// If a physical register, this returns the register that receives the |
272 | /// exception typeid on entry to a landing pad. |
273 | Register |
274 | getExceptionSelectorRegister(const Constant *PersonalityFn) const override { |
275 | return Hexagon::R1; |
276 | } |
277 | |
278 | SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; |
279 | SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; |
280 | SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; |
281 | SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; |
282 | |
283 | EVT getSetCCResultType(const DataLayout &, LLVMContext &C, |
284 | EVT VT) const override { |
285 | if (!VT.isVector()) |
286 | return MVT::i1; |
287 | else |
288 | return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); |
289 | } |
290 | |
291 | bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, |
292 | SDValue &Base, SDValue &Offset, |
293 | ISD::MemIndexedMode &AM, |
294 | SelectionDAG &DAG) const override; |
295 | |
296 | ConstraintType getConstraintType(StringRef Constraint) const override; |
297 | |
298 | std::pair<unsigned, const TargetRegisterClass *> |
299 | getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, |
300 | StringRef Constraint, MVT VT) const override; |
301 | |
302 | // Intrinsics |
303 | SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; |
304 | SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; |
305 | /// isLegalAddressingMode - Return true if the addressing mode represented |
306 | /// by AM is legal for this target, for a load/store of the specified type. |
307 | /// The type may be VoidTy, in which case only return true if the addressing |
308 | /// mode is legal for a load/store of any legal type. |
309 | /// TODO: Handle pre/postinc as well. |
310 | bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, |
311 | Type *Ty, unsigned AS, |
312 | Instruction *I = nullptr) const override; |
313 | /// Return true if folding a constant offset with the given GlobalAddress |
314 | /// is legal. It is frequently not legal in PIC relocation models. |
315 | bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; |
316 | |
317 | bool isFPImmLegal(const APFloat &Imm, EVT VT, |
318 | bool ForCodeSize) const override; |
319 | |
320 | /// isLegalICmpImmediate - Return true if the specified immediate is legal |
321 | /// icmp immediate, that is the target has icmp instructions which can |
322 | /// compare a register against the immediate without having to materialize |
323 | /// the immediate into a register. |
324 | bool isLegalICmpImmediate(int64_t Imm) const override; |
325 | |
326 | EVT getOptimalMemOpType(const MemOp &Op, |
327 | const AttributeList &FuncAttributes) const override; |
328 | |
329 | bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, |
330 | unsigned AddrSpace, Align Alignment, |
331 | MachineMemOperand::Flags Flags, |
332 | unsigned *Fast) const override; |
333 | |
334 | bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, |
335 | Align Alignment, |
336 | MachineMemOperand::Flags Flags, |
337 | unsigned *Fast) const override; |
338 | |
339 | /// Returns relocation base for the given PIC jumptable. |
340 | SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) |
341 | const override; |
342 | |
343 | bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, |
344 | EVT NewVT) const override; |
345 | |
346 | void AdjustInstrPostInstrSelection(MachineInstr &MI, |
347 | SDNode *Node) const override; |
348 | |
349 | // Handling of atomic RMW instructions. |
350 | Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, |
351 | AtomicOrdering Ord) const override; |
352 | Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, |
353 | AtomicOrdering Ord) const override; |
354 | AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; |
355 | AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; |
356 | AtomicExpansionKind |
357 | shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; |
358 | |
359 | AtomicExpansionKind |
360 | shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override { |
361 | return AtomicExpansionKind::LLSC; |
362 | } |
363 | |
364 | private: |
365 | void initializeHVXLowering(); |
366 | unsigned getPreferredHvxVectorAction(MVT VecTy) const; |
367 | unsigned getCustomHvxOperationAction(SDNode &Op) const; |
368 | |
369 | bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl, |
370 | SelectionDAG &DAG) const; |
371 | SDValue replaceMemWithUndef(SDValue Op, SelectionDAG &DAG) const; |
372 | |
373 | std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const; |
374 | |
375 | bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy, |
376 | SelectionDAG &DAG, |
377 | MutableArrayRef<ConstantInt*> Consts) const; |
378 | SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, |
379 | SelectionDAG &DAG) const; |
380 | SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, |
381 | SelectionDAG &DAG) const; |
382 | SDValue (SDValue VecV, SDValue IdxV, const SDLoc &dl, |
383 | MVT ValTy, MVT ResTy, SelectionDAG &DAG) const; |
384 | SDValue (SDValue VecV, SDValue IdxV, const SDLoc &dl, |
385 | MVT ValTy, MVT ResTy, SelectionDAG &DAG) const; |
386 | SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV, |
387 | const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const; |
388 | SDValue insertVectorPred(SDValue VecV, SDValue ValV, SDValue IdxV, |
389 | const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const; |
390 | SDValue expandPredicate(SDValue Vec32, const SDLoc &dl, |
391 | SelectionDAG &DAG) const; |
392 | SDValue contractPredicate(SDValue Vec64, const SDLoc &dl, |
393 | SelectionDAG &DAG) const; |
394 | SDValue getSplatValue(SDValue Op, SelectionDAG &DAG) const; |
395 | SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const; |
396 | SDValue appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) const; |
397 | SDValue getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl, MVT ResTy, |
398 | SelectionDAG &DAG) const; |
399 | |
400 | bool isUndef(SDValue Op) const { |
401 | if (Op.isMachineOpcode()) |
402 | return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF; |
403 | return Op.getOpcode() == ISD::UNDEF; |
404 | } |
405 | SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty, |
406 | ArrayRef<SDValue> Ops, SelectionDAG &DAG) const { |
407 | SDNode *N = DAG.getMachineNode(Opcode: MachineOpc, dl, VT: Ty, Ops); |
408 | return SDValue(N, 0); |
409 | } |
410 | SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const; |
411 | |
412 | using VectorPair = std::pair<SDValue, SDValue>; |
413 | using TypePair = std::pair<MVT, MVT>; |
414 | |
415 | SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops, |
416 | const SDLoc &dl, SelectionDAG &DAG) const; |
417 | |
418 | MVT ty(SDValue Op) const { |
419 | return Op.getValueType().getSimpleVT(); |
420 | } |
421 | TypePair ty(const VectorPair &Ops) const { |
422 | return { Ops.first.getValueType().getSimpleVT(), |
423 | Ops.second.getValueType().getSimpleVT() }; |
424 | } |
425 | MVT tyScalar(MVT Ty) const { |
426 | if (!Ty.isVector()) |
427 | return Ty; |
428 | return MVT::getIntegerVT(BitWidth: Ty.getSizeInBits()); |
429 | } |
430 | MVT tyVector(MVT Ty, MVT ElemTy) const { |
431 | if (Ty.isVector() && Ty.getVectorElementType() == ElemTy) |
432 | return Ty; |
433 | unsigned TyWidth = Ty.getSizeInBits(); |
434 | unsigned ElemWidth = ElemTy.getSizeInBits(); |
435 | assert((TyWidth % ElemWidth) == 0); |
436 | return MVT::getVectorVT(VT: ElemTy, NumElements: TyWidth/ElemWidth); |
437 | } |
438 | |
439 | MVT typeJoin(const TypePair &Tys) const; |
440 | TypePair typeSplit(MVT Ty) const; |
441 | MVT typeExtElem(MVT VecTy, unsigned Factor) const; |
442 | MVT typeTruncElem(MVT VecTy, unsigned Factor) const; |
443 | TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const; |
444 | TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const; |
445 | MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const; |
446 | MVT typeWidenToHvx(MVT Ty) const; |
447 | |
448 | SDValue opJoin(const VectorPair &Ops, const SDLoc &dl, |
449 | SelectionDAG &DAG) const; |
450 | VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const; |
451 | SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const; |
452 | |
453 | SDValue LoHalf(SDValue V, SelectionDAG &DAG) const { |
454 | MVT Ty = ty(Op: V); |
455 | const SDLoc &dl(V); |
456 | if (!Ty.isVector()) { |
457 | assert(Ty.getSizeInBits() == 64); |
458 | return DAG.getTargetExtractSubreg(Hexagon::SRIdx: isub_lo, DL: dl, MVT::VT: i32, Operand: V); |
459 | } |
460 | MVT HalfTy = typeSplit(Ty).first; |
461 | SDValue Idx = getZero(dl, MVT::Ty: i32, DAG); |
462 | return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx); |
463 | } |
464 | SDValue HiHalf(SDValue V, SelectionDAG &DAG) const { |
465 | MVT Ty = ty(Op: V); |
466 | const SDLoc &dl(V); |
467 | if (!Ty.isVector()) { |
468 | assert(Ty.getSizeInBits() == 64); |
469 | return DAG.getTargetExtractSubreg(Hexagon::SRIdx: isub_hi, DL: dl, MVT::VT: i32, Operand: V); |
470 | } |
471 | MVT HalfTy = typeSplit(Ty).first; |
472 | SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32); |
473 | return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx); |
474 | } |
475 | |
476 | bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags, |
477 | unsigned *Fast) const; |
478 | bool allowsHvxMisalignedMemoryAccesses(MVT VecTy, |
479 | MachineMemOperand::Flags Flags, |
480 | unsigned *Fast) const; |
481 | void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const; |
482 | |
483 | bool isHvxSingleTy(MVT Ty) const; |
484 | bool isHvxPairTy(MVT Ty) const; |
485 | bool isHvxBoolTy(MVT Ty) const; |
486 | SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy, |
487 | SelectionDAG &DAG) const; |
488 | SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const; |
489 | SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1, |
490 | ArrayRef<int> Mask, SelectionDAG &DAG) const; |
491 | |
492 | SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl, |
493 | MVT VecTy, SelectionDAG &DAG) const; |
494 | SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl, |
495 | MVT VecTy, SelectionDAG &DAG) const; |
496 | SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl, |
497 | unsigned BitBytes, bool ZeroFill, |
498 | SelectionDAG &DAG) const; |
499 | SDValue (SDValue VecV, SDValue IdxV, const SDLoc &dl, |
500 | MVT ResTy, SelectionDAG &DAG) const; |
501 | SDValue (SDValue VecV, SDValue IdxV, const SDLoc &dl, |
502 | MVT ResTy, SelectionDAG &DAG) const; |
503 | SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV, |
504 | const SDLoc &dl, SelectionDAG &DAG) const; |
505 | SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV, |
506 | const SDLoc &dl, SelectionDAG &DAG) const; |
507 | SDValue (SDValue OrigOp, SDValue VecV, SDValue IdxV, |
508 | const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) |
509 | const; |
510 | SDValue (SDValue VecV, SDValue IdxV, const SDLoc &dl, |
511 | MVT ResTy, SelectionDAG &DAG) const; |
512 | SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV, |
513 | const SDLoc &dl, SelectionDAG &DAG) const; |
514 | SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV, |
515 | const SDLoc &dl, SelectionDAG &DAG) const; |
516 | SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy, |
517 | bool ZeroExt, SelectionDAG &DAG) const; |
518 | SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy, |
519 | SelectionDAG &DAG) const; |
520 | SDValue resizeToWidth(SDValue VecV, MVT ResTy, bool Signed, const SDLoc &dl, |
521 | SelectionDAG &DAG) const; |
522 | SDValue (SDValue Vec, MVT SubTy, unsigned SubIdx, |
523 | SelectionDAG &DAG) const; |
524 | VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl, |
525 | bool Signed, SelectionDAG &DAG) const; |
526 | VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed, |
527 | SelectionDAG &DAG) const; |
528 | SDValue emitHvxMulHsV60(SDValue A, SDValue B, const SDLoc &dl, |
529 | SelectionDAG &DAG) const; |
530 | SDValue emitHvxMulLoHiV60(SDValue A, bool SignedA, SDValue B, bool SignedB, |
531 | const SDLoc &dl, SelectionDAG &DAG) const; |
532 | SDValue emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, bool SignedB, |
533 | const SDLoc &dl, SelectionDAG &DAG) const; |
534 | |
535 | SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const; |
536 | SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const; |
537 | SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const; |
538 | SDValue (SDValue Op, SelectionDAG &DAG) const; |
539 | SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const; |
540 | SDValue (SDValue Op, SelectionDAG &DAG) const; |
541 | SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const; |
542 | SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const; |
543 | SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const; |
544 | SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const; |
545 | SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const; |
546 | SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const; |
547 | SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const; |
548 | SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const; |
549 | SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const; |
550 | SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const; |
551 | SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const; |
552 | SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const; |
553 | SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const; |
554 | SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const; |
555 | SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const; |
556 | SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const; |
557 | SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const; |
558 | SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const; |
559 | SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const; |
560 | |
561 | VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const; |
562 | |
563 | SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const; |
564 | SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const; |
565 | SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const; |
566 | SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const; |
567 | SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const; |
568 | SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const; |
569 | SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const; |
570 | |
571 | SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const; |
572 | SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const; |
573 | |
574 | std::pair<const TargetRegisterClass*, uint8_t> |
575 | findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) |
576 | const override; |
577 | |
578 | bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const; |
579 | bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const; |
580 | bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const; |
581 | SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const; |
582 | void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results, |
583 | SelectionDAG &DAG) const; |
584 | void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, |
585 | SelectionDAG &DAG) const; |
586 | |
587 | SDValue combineTruncateBeforeLegal(SDValue Op, DAGCombinerInfo &DCI) const; |
588 | SDValue combineConcatVectorsBeforeLegal(SDValue Op, DAGCombinerInfo & DCI) |
589 | const; |
590 | SDValue combineVectorShuffleBeforeLegal(SDValue Op, DAGCombinerInfo & DCI) |
591 | const; |
592 | |
593 | SDValue PerformHvxDAGCombine(SDNode * N, DAGCombinerInfo & DCI) const; |
594 | }; |
595 | |
596 | } // end namespace llvm |
597 | |
598 | #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H |
599 | |