1use crate::{
2 arch::asm,
3 core_arch::{simd::*, x86::*},
4 intrinsics::simd::*,
5 mem, ptr,
6};
7
8#[cfg(test)]
9use stdarch_test::assert_instr;
10
11use super::avx512f::{vpl, vps};
12
13/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst.
14///
15/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi16&expand=30)
16#[inline]
17#[target_feature(enable = "avx512bw")]
18#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
19#[cfg_attr(test, assert_instr(vpabsw))]
20pub unsafe fn _mm512_abs_epi16(a: __m512i) -> __m512i {
21 let a: i16x32 = a.as_i16x32();
22 // all-0 is a properly initialized i16x32
23 let zero: i16x32 = mem::zeroed();
24 let sub: i16x32 = simd_sub(lhs:zero, rhs:a);
25 let cmp: i16x32 = simd_gt(x:a, y:zero);
26 transmute(src:simd_select(mask:cmp, if_true:a, if_false:sub))
27}
28
29/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
30///
31/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi16&expand=31)
32#[inline]
33#[target_feature(enable = "avx512bw")]
34#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
35#[cfg_attr(test, assert_instr(vpabsw))]
36pub unsafe fn _mm512_mask_abs_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
37 let abs: i16x32 = _mm512_abs_epi16(a).as_i16x32();
38 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i16x32()))
39}
40
41/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
42///
43/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi16&expand=32)
44#[inline]
45#[target_feature(enable = "avx512bw")]
46#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
47#[cfg_attr(test, assert_instr(vpabsw))]
48pub unsafe fn _mm512_maskz_abs_epi16(k: __mmask32, a: __m512i) -> __m512i {
49 let abs: i16x32 = _mm512_abs_epi16(a).as_i16x32();
50 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
51 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
52}
53
54/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
55///
56/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi16&expand=28)
57#[inline]
58#[target_feature(enable = "avx512bw,avx512vl")]
59#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
60#[cfg_attr(test, assert_instr(vpabsw))]
61pub unsafe fn _mm256_mask_abs_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
62 let abs: i16x16 = _mm256_abs_epi16(a).as_i16x16();
63 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i16x16()))
64}
65
66/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
67///
68/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi16&expand=29)
69#[inline]
70#[target_feature(enable = "avx512bw,avx512vl")]
71#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
72#[cfg_attr(test, assert_instr(vpabsw))]
73pub unsafe fn _mm256_maskz_abs_epi16(k: __mmask16, a: __m256i) -> __m256i {
74 let abs: i16x16 = _mm256_abs_epi16(a).as_i16x16();
75 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
76 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
77}
78
79/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
80///
81/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi16&expand=25)
82#[inline]
83#[target_feature(enable = "avx512bw,avx512vl")]
84#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
85#[cfg_attr(test, assert_instr(vpabsw))]
86pub unsafe fn _mm_mask_abs_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
87 let abs: i16x8 = _mm_abs_epi16(a).as_i16x8();
88 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i16x8()))
89}
90
91/// Compute the absolute value of packed signed 16-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
92///
93/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi16&expand=26)
94#[inline]
95#[target_feature(enable = "avx512bw,avx512vl")]
96#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
97#[cfg_attr(test, assert_instr(vpabsw))]
98pub unsafe fn _mm_maskz_abs_epi16(k: __mmask8, a: __m128i) -> __m128i {
99 let abs: i16x8 = _mm_abs_epi16(a).as_i16x8();
100 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
101 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
102}
103
104/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst.
105///
106/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_abs_epi8&expand=57)
107#[inline]
108#[target_feature(enable = "avx512bw")]
109#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
110#[cfg_attr(test, assert_instr(vpabsb))]
111pub unsafe fn _mm512_abs_epi8(a: __m512i) -> __m512i {
112 let a: i8x64 = a.as_i8x64();
113 // all-0 is a properly initialized i8x64
114 let zero: i8x64 = mem::zeroed();
115 let sub: i8x64 = simd_sub(lhs:zero, rhs:a);
116 let cmp: i8x64 = simd_gt(x:a, y:zero);
117 transmute(src:simd_select(mask:cmp, if_true:a, if_false:sub))
118}
119
120/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
121///
122/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_abs_epi8&expand=58)
123#[inline]
124#[target_feature(enable = "avx512bw")]
125#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
126#[cfg_attr(test, assert_instr(vpabsb))]
127pub unsafe fn _mm512_mask_abs_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
128 let abs: i8x64 = _mm512_abs_epi8(a).as_i8x64();
129 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i8x64()))
130}
131
132/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
133///
134/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_abs_epi8&expand=59)
135#[inline]
136#[target_feature(enable = "avx512bw")]
137#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
138#[cfg_attr(test, assert_instr(vpabsb))]
139pub unsafe fn _mm512_maskz_abs_epi8(k: __mmask64, a: __m512i) -> __m512i {
140 let abs: i8x64 = _mm512_abs_epi8(a).as_i8x64();
141 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
142 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
143}
144
145/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
146///
147/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_abs_epi8&expand=55)
148#[inline]
149#[target_feature(enable = "avx512bw,avx512vl")]
150#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
151#[cfg_attr(test, assert_instr(vpabsb))]
152pub unsafe fn _mm256_mask_abs_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
153 let abs: i8x32 = _mm256_abs_epi8(a).as_i8x32();
154 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i8x32()))
155}
156
157/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
158///
159/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_abs_epi8&expand=56)
160#[inline]
161#[target_feature(enable = "avx512bw,avx512vl")]
162#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
163#[cfg_attr(test, assert_instr(vpabsb))]
164pub unsafe fn _mm256_maskz_abs_epi8(k: __mmask32, a: __m256i) -> __m256i {
165 let abs: i8x32 = _mm256_abs_epi8(a).as_i8x32();
166 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
167 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
168}
169
170/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set)
171///
172/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_abs_epi8&expand=52)
173#[inline]
174#[target_feature(enable = "avx512bw,avx512vl")]
175#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
176#[cfg_attr(test, assert_instr(vpabsb))]
177pub unsafe fn _mm_mask_abs_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
178 let abs: i8x16 = _mm_abs_epi8(a).as_i8x16();
179 transmute(src:simd_select_bitmask(m:k, yes:abs, no:src.as_i8x16()))
180}
181
182/// Compute the absolute value of packed signed 8-bit integers in a, and store the unsigned results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
183///
184/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_abs_epi8&expand=53)
185#[inline]
186#[target_feature(enable = "avx512bw,avx512vl")]
187#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
188#[cfg_attr(test, assert_instr(vpabsb))]
189pub unsafe fn _mm_maskz_abs_epi8(k: __mmask16, a: __m128i) -> __m128i {
190 let abs: i8x16 = _mm_abs_epi8(a).as_i8x16();
191 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
192 transmute(src:simd_select_bitmask(m:k, yes:abs, no:zero))
193}
194
195/// Add packed 16-bit integers in a and b, and store the results in dst.
196///
197/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi16&expand=91)
198#[inline]
199#[target_feature(enable = "avx512bw")]
200#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
201#[cfg_attr(test, assert_instr(vpaddw))]
202pub unsafe fn _mm512_add_epi16(a: __m512i, b: __m512i) -> __m512i {
203 transmute(src:simd_add(x:a.as_i16x32(), y:b.as_i16x32()))
204}
205
206/// Add packed 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
207///
208/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi16&expand=92)
209#[inline]
210#[target_feature(enable = "avx512bw")]
211#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
212#[cfg_attr(test, assert_instr(vpaddw))]
213pub unsafe fn _mm512_mask_add_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
214 let add: i16x32 = _mm512_add_epi16(a, b).as_i16x32();
215 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i16x32()))
216}
217
218/// Add packed 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
219///
220/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi16&expand=93)
221#[inline]
222#[target_feature(enable = "avx512bw")]
223#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
224#[cfg_attr(test, assert_instr(vpaddw))]
225pub unsafe fn _mm512_maskz_add_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
226 let add: i16x32 = _mm512_add_epi16(a, b).as_i16x32();
227 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
228 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
229}
230
231/// Add packed 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
232///
233/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi&expand=89)
234#[inline]
235#[target_feature(enable = "avx512bw,avx512vl")]
236#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
237#[cfg_attr(test, assert_instr(vpaddw))]
238pub unsafe fn _mm256_mask_add_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
239 let add: i16x16 = _mm256_add_epi16(a, b).as_i16x16();
240 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i16x16()))
241}
242
243/// Add packed 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
244///
245/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi16&expand=90)
246#[inline]
247#[target_feature(enable = "avx512bw,avx512vl")]
248#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
249#[cfg_attr(test, assert_instr(vpaddw))]
250pub unsafe fn _mm256_maskz_add_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
251 let add: i16x16 = _mm256_add_epi16(a, b).as_i16x16();
252 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
253 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
254}
255
256/// Add packed 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
257///
258/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi16&expand=86)
259#[inline]
260#[target_feature(enable = "avx512bw,avx512vl")]
261#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
262#[cfg_attr(test, assert_instr(vpaddw))]
263pub unsafe fn _mm_mask_add_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
264 let add: i16x8 = _mm_add_epi16(a, b).as_i16x8();
265 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i16x8()))
266}
267
268/// Add packed 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
269///
270/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi16&expand=87)
271#[inline]
272#[target_feature(enable = "avx512bw,avx512vl")]
273#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
274#[cfg_attr(test, assert_instr(vpaddw))]
275pub unsafe fn _mm_maskz_add_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
276 let add: i16x8 = _mm_add_epi16(a, b).as_i16x8();
277 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
278 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
279}
280
281/// Add packed 8-bit integers in a and b, and store the results in dst.
282///
283/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_add_epi8&expand=118)
284#[inline]
285#[target_feature(enable = "avx512bw")]
286#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
287#[cfg_attr(test, assert_instr(vpaddb))]
288pub unsafe fn _mm512_add_epi8(a: __m512i, b: __m512i) -> __m512i {
289 transmute(src:simd_add(x:a.as_i8x64(), y:b.as_i8x64()))
290}
291
292/// Add packed 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
293///
294/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_add_epi8&expand=119)
295#[inline]
296#[target_feature(enable = "avx512bw")]
297#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
298#[cfg_attr(test, assert_instr(vpaddb))]
299pub unsafe fn _mm512_mask_add_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
300 let add: i8x64 = _mm512_add_epi8(a, b).as_i8x64();
301 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i8x64()))
302}
303
304/// Add packed 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
305///
306/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_add_epi8&expand=120)
307#[inline]
308#[target_feature(enable = "avx512bw")]
309#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
310#[cfg_attr(test, assert_instr(vpaddb))]
311pub unsafe fn _mm512_maskz_add_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
312 let add: i8x64 = _mm512_add_epi8(a, b).as_i8x64();
313 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
314 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
315}
316
317/// Add packed 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
318///
319/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_add_epi8&expand=116)
320#[inline]
321#[target_feature(enable = "avx512bw,avx512vl")]
322#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
323#[cfg_attr(test, assert_instr(vpaddb))]
324pub unsafe fn _mm256_mask_add_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
325 let add: i8x32 = _mm256_add_epi8(a, b).as_i8x32();
326 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i8x32()))
327}
328
329/// Add packed 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
330///
331/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_add_epi8&expand=117)
332#[inline]
333#[target_feature(enable = "avx512bw,avx512vl")]
334#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
335#[cfg_attr(test, assert_instr(vpaddb))]
336pub unsafe fn _mm256_maskz_add_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
337 let add: i8x32 = _mm256_add_epi8(a, b).as_i8x32();
338 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
339 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
340}
341
342/// Add packed 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
343///
344/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_add_epi8&expand=113)
345#[inline]
346#[target_feature(enable = "avx512bw,avx512vl")]
347#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
348#[cfg_attr(test, assert_instr(vpaddb))]
349pub unsafe fn _mm_mask_add_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
350 let add: i8x16 = _mm_add_epi8(a, b).as_i8x16();
351 transmute(src:simd_select_bitmask(m:k, yes:add, no:src.as_i8x16()))
352}
353
354/// Add packed 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
355///
356/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_add_epi8&expand=114)
357#[inline]
358#[target_feature(enable = "avx512bw,avx512vl")]
359#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
360#[cfg_attr(test, assert_instr(vpaddb))]
361pub unsafe fn _mm_maskz_add_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
362 let add: i8x16 = _mm_add_epi8(a, b).as_i8x16();
363 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
364 transmute(src:simd_select_bitmask(m:k, yes:add, no:zero))
365}
366
367/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst.
368///
369/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epu16&expand=197)
370#[inline]
371#[target_feature(enable = "avx512bw")]
372#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
373#[cfg_attr(test, assert_instr(vpaddusw))]
374pub unsafe fn _mm512_adds_epu16(a: __m512i, b: __m512i) -> __m512i {
375 transmute(src:vpaddusw(
376 a:a.as_u16x32(),
377 b:b.as_u16x32(),
378 src:_mm512_setzero_si512().as_u16x32(),
379 mask:0b11111111_11111111_11111111_11111111,
380 ))
381}
382
383/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
384///
385/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epu16&expand=198)
386#[inline]
387#[target_feature(enable = "avx512bw")]
388#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
389#[cfg_attr(test, assert_instr(vpaddusw))]
390pub unsafe fn _mm512_mask_adds_epu16(
391 src: __m512i,
392 k: __mmask32,
393 a: __m512i,
394 b: __m512i,
395) -> __m512i {
396 transmute(src:vpaddusw(a:a.as_u16x32(), b:b.as_u16x32(), src:src.as_u16x32(), mask:k))
397}
398
399/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
400///
401/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epu16&expand=199)
402#[inline]
403#[target_feature(enable = "avx512bw")]
404#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
405#[cfg_attr(test, assert_instr(vpaddusw))]
406pub unsafe fn _mm512_maskz_adds_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
407 transmute(src:vpaddusw(
408 a:a.as_u16x32(),
409 b:b.as_u16x32(),
410 src:_mm512_setzero_si512().as_u16x32(),
411 mask:k,
412 ))
413}
414
415/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
416///
417/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epu16&expand=195)
418#[inline]
419#[target_feature(enable = "avx512bw,avx512vl")]
420#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
421#[cfg_attr(test, assert_instr(vpaddusw))]
422pub unsafe fn _mm256_mask_adds_epu16(
423 src: __m256i,
424 k: __mmask16,
425 a: __m256i,
426 b: __m256i,
427) -> __m256i {
428 transmute(src:vpaddusw256(
429 a:a.as_u16x16(),
430 b:b.as_u16x16(),
431 src:src.as_u16x16(),
432 mask:k,
433 ))
434}
435
436/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
437///
438/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epu16&expand=196)
439#[inline]
440#[target_feature(enable = "avx512bw,avx512vl")]
441#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
442#[cfg_attr(test, assert_instr(vpaddusw))]
443pub unsafe fn _mm256_maskz_adds_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
444 transmute(src:vpaddusw256(
445 a:a.as_u16x16(),
446 b:b.as_u16x16(),
447 src:_mm256_setzero_si256().as_u16x16(),
448 mask:k,
449 ))
450}
451
452/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
453///
454/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epu16&expand=192)
455#[inline]
456#[target_feature(enable = "avx512bw,avx512vl")]
457#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
458#[cfg_attr(test, assert_instr(vpaddusw))]
459pub unsafe fn _mm_mask_adds_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
460 transmute(src:vpaddusw128(a:a.as_u16x8(), b:b.as_u16x8(), src:src.as_u16x8(), mask:k))
461}
462
463/// Add packed unsigned 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
464///
465/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epu16&expand=193)
466#[inline]
467#[target_feature(enable = "avx512bw,avx512vl")]
468#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
469#[cfg_attr(test, assert_instr(vpaddusw))]
470pub unsafe fn _mm_maskz_adds_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
471 transmute(src:vpaddusw128(
472 a:a.as_u16x8(),
473 b:b.as_u16x8(),
474 src:_mm_setzero_si128().as_u16x8(),
475 mask:k,
476 ))
477}
478
479/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst.
480///
481/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epu8&expand=206)
482#[inline]
483#[target_feature(enable = "avx512bw")]
484#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
485#[cfg_attr(test, assert_instr(vpaddusb))]
486pub unsafe fn _mm512_adds_epu8(a: __m512i, b: __m512i) -> __m512i {
487 transmute(src:vpaddusb(
488 a:a.as_u8x64(),
489 b:b.as_u8x64(),
490 src:_mm512_setzero_si512().as_u8x64(),
491 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
492 ))
493}
494
495/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
496///
497/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epu8&expand=207)
498#[inline]
499#[target_feature(enable = "avx512bw")]
500#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
501#[cfg_attr(test, assert_instr(vpaddusb))]
502pub unsafe fn _mm512_mask_adds_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
503 transmute(src:vpaddusb(a:a.as_u8x64(), b:b.as_u8x64(), src:src.as_u8x64(), mask:k))
504}
505
506/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
507///
508/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epu8&expand=208)
509#[inline]
510#[target_feature(enable = "avx512bw")]
511#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
512#[cfg_attr(test, assert_instr(vpaddusb))]
513pub unsafe fn _mm512_maskz_adds_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
514 transmute(src:vpaddusb(
515 a:a.as_u8x64(),
516 b:b.as_u8x64(),
517 src:_mm512_setzero_si512().as_u8x64(),
518 mask:k,
519 ))
520}
521
522/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
523///
524/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epu8&expand=204)
525#[inline]
526#[target_feature(enable = "avx512bw,avx512vl")]
527#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
528#[cfg_attr(test, assert_instr(vpaddusb))]
529pub unsafe fn _mm256_mask_adds_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
530 transmute(src:vpaddusb256(a:a.as_u8x32(), b:b.as_u8x32(), src:src.as_u8x32(), mask:k))
531}
532
533/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
534///
535/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epu8&expand=205)
536#[inline]
537#[target_feature(enable = "avx512bw,avx512vl")]
538#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
539#[cfg_attr(test, assert_instr(vpaddusb))]
540pub unsafe fn _mm256_maskz_adds_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
541 transmute(src:vpaddusb256(
542 a:a.as_u8x32(),
543 b:b.as_u8x32(),
544 src:_mm256_setzero_si256().as_u8x32(),
545 mask:k,
546 ))
547}
548
549/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
550///
551/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epu8&expand=201)
552#[inline]
553#[target_feature(enable = "avx512bw,avx512vl")]
554#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
555#[cfg_attr(test, assert_instr(vpaddusb))]
556pub unsafe fn _mm_mask_adds_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
557 transmute(src:vpaddusb128(a:a.as_u8x16(), b:b.as_u8x16(), src:src.as_u8x16(), mask:k))
558}
559
560/// Add packed unsigned 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
561///
562/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epu8&expand=202)
563#[inline]
564#[target_feature(enable = "avx512bw,avx512vl")]
565#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
566#[cfg_attr(test, assert_instr(vpaddusb))]
567pub unsafe fn _mm_maskz_adds_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
568 transmute(src:vpaddusb128(
569 a:a.as_u8x16(),
570 b:b.as_u8x16(),
571 src:_mm_setzero_si128().as_u8x16(),
572 mask:k,
573 ))
574}
575
576/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst.
577///
578/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epi16&expand=179)
579#[inline]
580#[target_feature(enable = "avx512bw")]
581#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
582#[cfg_attr(test, assert_instr(vpaddsw))]
583pub unsafe fn _mm512_adds_epi16(a: __m512i, b: __m512i) -> __m512i {
584 transmute(src:vpaddsw(
585 a:a.as_i16x32(),
586 b:b.as_i16x32(),
587 src:_mm512_setzero_si512().as_i16x32(),
588 mask:0b11111111_11111111_11111111_11111111,
589 ))
590}
591
592/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
593///
594/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epi16&expand=180)
595#[inline]
596#[target_feature(enable = "avx512bw")]
597#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
598#[cfg_attr(test, assert_instr(vpaddsw))]
599pub unsafe fn _mm512_mask_adds_epi16(
600 src: __m512i,
601 k: __mmask32,
602 a: __m512i,
603 b: __m512i,
604) -> __m512i {
605 transmute(src:vpaddsw(a:a.as_i16x32(), b:b.as_i16x32(), src:src.as_i16x32(), mask:k))
606}
607
608/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
609///
610/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epi16&expand=181)
611#[inline]
612#[target_feature(enable = "avx512bw")]
613#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
614#[cfg_attr(test, assert_instr(vpaddsw))]
615pub unsafe fn _mm512_maskz_adds_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
616 transmute(src:vpaddsw(
617 a:a.as_i16x32(),
618 b:b.as_i16x32(),
619 src:_mm512_setzero_si512().as_i16x32(),
620 mask:k,
621 ))
622}
623
624/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
625///
626/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epi16&expand=177)
627#[inline]
628#[target_feature(enable = "avx512bw,avx512vl")]
629#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
630#[cfg_attr(test, assert_instr(vpaddsw))]
631pub unsafe fn _mm256_mask_adds_epi16(
632 src: __m256i,
633 k: __mmask16,
634 a: __m256i,
635 b: __m256i,
636) -> __m256i {
637 transmute(src:vpaddsw256(a:a.as_i16x16(), b:b.as_i16x16(), src:src.as_i16x16(), mask:k))
638}
639
640/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
641///
642/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epi16&expand=178)
643#[inline]
644#[target_feature(enable = "avx512bw,avx512vl")]
645#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
646#[cfg_attr(test, assert_instr(vpaddsw))]
647pub unsafe fn _mm256_maskz_adds_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
648 transmute(src:vpaddsw256(
649 a:a.as_i16x16(),
650 b:b.as_i16x16(),
651 src:_mm256_setzero_si256().as_i16x16(),
652 mask:k,
653 ))
654}
655
656/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
657///
658/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epi16&expand=174)
659#[inline]
660#[target_feature(enable = "avx512bw,avx512vl")]
661#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
662#[cfg_attr(test, assert_instr(vpaddsw))]
663pub unsafe fn _mm_mask_adds_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
664 transmute(src:vpaddsw128(a:a.as_i16x8(), b:b.as_i16x8(), src:src.as_i16x8(), mask:k))
665}
666
667/// Add packed signed 16-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
668///
669/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epi16&expand=175)
670#[inline]
671#[target_feature(enable = "avx512bw,avx512vl")]
672#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
673#[cfg_attr(test, assert_instr(vpaddsw))]
674pub unsafe fn _mm_maskz_adds_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
675 transmute(src:vpaddsw128(
676 a:a.as_i16x8(),
677 b:b.as_i16x8(),
678 src:_mm_setzero_si128().as_i16x8(),
679 mask:k,
680 ))
681}
682
683/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst.
684///
685/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_adds_epi8&expand=188)
686#[inline]
687#[target_feature(enable = "avx512bw")]
688#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
689#[cfg_attr(test, assert_instr(vpaddsb))]
690pub unsafe fn _mm512_adds_epi8(a: __m512i, b: __m512i) -> __m512i {
691 transmute(src:vpaddsb(
692 a:a.as_i8x64(),
693 b:b.as_i8x64(),
694 src:_mm512_setzero_si512().as_i8x64(),
695 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
696 ))
697}
698
699/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
700///
701/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_adds_epi8&expand=189)
702#[inline]
703#[target_feature(enable = "avx512bw")]
704#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
705#[cfg_attr(test, assert_instr(vpaddsb))]
706pub unsafe fn _mm512_mask_adds_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
707 transmute(src:vpaddsb(a:a.as_i8x64(), b:b.as_i8x64(), src:src.as_i8x64(), mask:k))
708}
709
710/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
711///
712/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_adds_epi8&expand=190)
713#[inline]
714#[target_feature(enable = "avx512bw")]
715#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
716#[cfg_attr(test, assert_instr(vpaddsb))]
717pub unsafe fn _mm512_maskz_adds_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
718 transmute(src:vpaddsb(
719 a:a.as_i8x64(),
720 b:b.as_i8x64(),
721 src:_mm512_setzero_si512().as_i8x64(),
722 mask:k,
723 ))
724}
725
726/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
727///
728/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_adds_epi8&expand=186)
729#[inline]
730#[target_feature(enable = "avx512bw,avx512vl")]
731#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
732#[cfg_attr(test, assert_instr(vpaddsb))]
733pub unsafe fn _mm256_mask_adds_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
734 transmute(src:vpaddsb256(a:a.as_i8x32(), b:b.as_i8x32(), src:src.as_i8x32(), mask:k))
735}
736
737/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
738///
739/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_adds_epi8&expand=187)
740#[inline]
741#[target_feature(enable = "avx512bw,avx512vl")]
742#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
743#[cfg_attr(test, assert_instr(vpaddsb))]
744pub unsafe fn _mm256_maskz_adds_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
745 transmute(src:vpaddsb256(
746 a:a.as_i8x32(),
747 b:b.as_i8x32(),
748 src:_mm256_setzero_si256().as_i8x32(),
749 mask:k,
750 ))
751}
752
753/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
754///
755/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_adds_epi8&expand=183)
756#[inline]
757#[target_feature(enable = "avx512bw,avx512vl")]
758#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
759#[cfg_attr(test, assert_instr(vpaddsb))]
760pub unsafe fn _mm_mask_adds_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
761 transmute(src:vpaddsb128(a:a.as_i8x16(), b:b.as_i8x16(), src:src.as_i8x16(), mask:k))
762}
763
764/// Add packed signed 8-bit integers in a and b using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
765///
766/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_adds_epi8&expand=184)
767#[inline]
768#[target_feature(enable = "avx512bw,avx512vl")]
769#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
770#[cfg_attr(test, assert_instr(vpaddsb))]
771pub unsafe fn _mm_maskz_adds_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
772 transmute(src:vpaddsb128(
773 a:a.as_i8x16(),
774 b:b.as_i8x16(),
775 src:_mm_setzero_si128().as_i8x16(),
776 mask:k,
777 ))
778}
779
780/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst.
781///
782/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi16&expand=5685)
783#[inline]
784#[target_feature(enable = "avx512bw")]
785#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
786#[cfg_attr(test, assert_instr(vpsubw))]
787pub unsafe fn _mm512_sub_epi16(a: __m512i, b: __m512i) -> __m512i {
788 transmute(src:simd_sub(lhs:a.as_i16x32(), rhs:b.as_i16x32()))
789}
790
791/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
792///
793/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi16&expand=5683)
794#[inline]
795#[target_feature(enable = "avx512bw")]
796#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
797#[cfg_attr(test, assert_instr(vpsubw))]
798pub unsafe fn _mm512_mask_sub_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
799 let sub: i16x32 = _mm512_sub_epi16(a, b).as_i16x32();
800 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i16x32()))
801}
802
803/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
804///
805/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi16&expand=5684)
806#[inline]
807#[target_feature(enable = "avx512bw")]
808#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
809#[cfg_attr(test, assert_instr(vpsubw))]
810pub unsafe fn _mm512_maskz_sub_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
811 let sub: i16x32 = _mm512_sub_epi16(a, b).as_i16x32();
812 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
813 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
814}
815
816/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
817///
818/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi16&expand=5680)
819#[inline]
820#[target_feature(enable = "avx512bw,avx512vl")]
821#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
822#[cfg_attr(test, assert_instr(vpsubw))]
823pub unsafe fn _mm256_mask_sub_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
824 let sub: i16x16 = _mm256_sub_epi16(a, b).as_i16x16();
825 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i16x16()))
826}
827
828/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
829///
830/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi16&expand=5681)
831#[inline]
832#[target_feature(enable = "avx512bw,avx512vl")]
833#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
834#[cfg_attr(test, assert_instr(vpsubw))]
835pub unsafe fn _mm256_maskz_sub_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
836 let sub: i16x16 = _mm256_sub_epi16(a, b).as_i16x16();
837 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
838 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
839}
840
841/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
842///
843/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi16&expand=5677)
844#[inline]
845#[target_feature(enable = "avx512bw,avx512vl")]
846#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
847#[cfg_attr(test, assert_instr(vpsubw))]
848pub unsafe fn _mm_mask_sub_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
849 let sub: i16x8 = _mm_sub_epi16(a, b).as_i16x8();
850 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i16x8()))
851}
852
853/// Subtract packed 16-bit integers in b from packed 16-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
854///
855/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi16&expand=5678)
856#[inline]
857#[target_feature(enable = "avx512bw,avx512vl")]
858#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
859#[cfg_attr(test, assert_instr(vpsubw))]
860pub unsafe fn _mm_maskz_sub_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
861 let sub: i16x8 = _mm_sub_epi16(a, b).as_i16x8();
862 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
863 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
864}
865
866/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst.
867///
868/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sub_epi8&expand=5712)
869#[inline]
870#[target_feature(enable = "avx512bw")]
871#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
872#[cfg_attr(test, assert_instr(vpsubb))]
873pub unsafe fn _mm512_sub_epi8(a: __m512i, b: __m512i) -> __m512i {
874 transmute(src:simd_sub(lhs:a.as_i8x64(), rhs:b.as_i8x64()))
875}
876
877/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
878///
879/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sub_epi8&expand=5710)
880#[inline]
881#[target_feature(enable = "avx512bw")]
882#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
883#[cfg_attr(test, assert_instr(vpsubb))]
884pub unsafe fn _mm512_mask_sub_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
885 let sub: i8x64 = _mm512_sub_epi8(a, b).as_i8x64();
886 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i8x64()))
887}
888
889/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
890///
891/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sub_epi8&expand=5711)
892#[inline]
893#[target_feature(enable = "avx512bw")]
894#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
895#[cfg_attr(test, assert_instr(vpsubb))]
896pub unsafe fn _mm512_maskz_sub_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
897 let sub: i8x64 = _mm512_sub_epi8(a, b).as_i8x64();
898 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
899 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
900}
901
902/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
903///
904/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sub_epi8&expand=5707)
905#[inline]
906#[target_feature(enable = "avx512bw,avx512vl")]
907#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
908#[cfg_attr(test, assert_instr(vpsubb))]
909pub unsafe fn _mm256_mask_sub_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
910 let sub: i8x32 = _mm256_sub_epi8(a, b).as_i8x32();
911 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i8x32()))
912}
913
914/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
915///
916/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sub_epi8&expand=5708)
917#[inline]
918#[target_feature(enable = "avx512bw,avx512vl")]
919#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
920#[cfg_attr(test, assert_instr(vpsubb))]
921pub unsafe fn _mm256_maskz_sub_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
922 let sub: i8x32 = _mm256_sub_epi8(a, b).as_i8x32();
923 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
924 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
925}
926
927/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
928///
929/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sub_epi8&expand=5704)
930#[inline]
931#[target_feature(enable = "avx512bw,avx512vl")]
932#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
933#[cfg_attr(test, assert_instr(vpsubb))]
934pub unsafe fn _mm_mask_sub_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
935 let sub: i8x16 = _mm_sub_epi8(a, b).as_i8x16();
936 transmute(src:simd_select_bitmask(m:k, yes:sub, no:src.as_i8x16()))
937}
938
939/// Subtract packed 8-bit integers in b from packed 8-bit integers in a, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
940///
941/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sub_epi8&expand=5705)
942#[inline]
943#[target_feature(enable = "avx512bw,avx512vl")]
944#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
945#[cfg_attr(test, assert_instr(vpsubb))]
946pub unsafe fn _mm_maskz_sub_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
947 let sub: i8x16 = _mm_sub_epi8(a, b).as_i8x16();
948 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
949 transmute(src:simd_select_bitmask(m:k, yes:sub, no:zero))
950}
951
952/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst.
953///
954/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epu16&expand=5793)
955#[inline]
956#[target_feature(enable = "avx512bw")]
957#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
958#[cfg_attr(test, assert_instr(vpsubusw))]
959pub unsafe fn _mm512_subs_epu16(a: __m512i, b: __m512i) -> __m512i {
960 transmute(src:vpsubusw(
961 a:a.as_u16x32(),
962 b:b.as_u16x32(),
963 src:_mm512_setzero_si512().as_u16x32(),
964 mask:0b11111111_11111111_11111111_11111111,
965 ))
966}
967
968/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
969///
970/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epu16&expand=5791)
971#[inline]
972#[target_feature(enable = "avx512bw")]
973#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
974#[cfg_attr(test, assert_instr(vpsubusw))]
975pub unsafe fn _mm512_mask_subs_epu16(
976 src: __m512i,
977 k: __mmask32,
978 a: __m512i,
979 b: __m512i,
980) -> __m512i {
981 transmute(src:vpsubusw(a:a.as_u16x32(), b:b.as_u16x32(), src:src.as_u16x32(), mask:k))
982}
983
984/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
985///
986/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epu16&expand=5792)
987#[inline]
988#[target_feature(enable = "avx512bw")]
989#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
990#[cfg_attr(test, assert_instr(vpsubusw))]
991pub unsafe fn _mm512_maskz_subs_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
992 transmute(src:vpsubusw(
993 a:a.as_u16x32(),
994 b:b.as_u16x32(),
995 src:_mm512_setzero_si512().as_u16x32(),
996 mask:k,
997 ))
998}
999
1000/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1001///
1002/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epu16&expand=5788)
1003#[inline]
1004#[target_feature(enable = "avx512bw,avx512vl")]
1005#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1006#[cfg_attr(test, assert_instr(vpsubusw))]
1007pub unsafe fn _mm256_mask_subs_epu16(
1008 src: __m256i,
1009 k: __mmask16,
1010 a: __m256i,
1011 b: __m256i,
1012) -> __m256i {
1013 transmute(src:vpsubusw256(
1014 a:a.as_u16x16(),
1015 b:b.as_u16x16(),
1016 src:src.as_u16x16(),
1017 mask:k,
1018 ))
1019}
1020
1021/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1022///
1023/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epu16&expand=5789)
1024#[inline]
1025#[target_feature(enable = "avx512bw,avx512vl")]
1026#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1027#[cfg_attr(test, assert_instr(vpsubusw))]
1028pub unsafe fn _mm256_maskz_subs_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1029 transmute(src:vpsubusw256(
1030 a:a.as_u16x16(),
1031 b:b.as_u16x16(),
1032 src:_mm256_setzero_si256().as_u16x16(),
1033 mask:k,
1034 ))
1035}
1036
1037/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1038///
1039/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epu16&expand=5785)
1040#[inline]
1041#[target_feature(enable = "avx512bw,avx512vl")]
1042#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1043#[cfg_attr(test, assert_instr(vpsubusw))]
1044pub unsafe fn _mm_mask_subs_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1045 transmute(src:vpsubusw128(a:a.as_u16x8(), b:b.as_u16x8(), src:src.as_u16x8(), mask:k))
1046}
1047
1048/// Subtract packed unsigned 16-bit integers in b from packed unsigned 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1049///
1050/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epu16&expand=5786)
1051#[inline]
1052#[target_feature(enable = "avx512bw,avx512vl")]
1053#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1054#[cfg_attr(test, assert_instr(vpsubusw))]
1055pub unsafe fn _mm_maskz_subs_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1056 transmute(src:vpsubusw128(
1057 a:a.as_u16x8(),
1058 b:b.as_u16x8(),
1059 src:_mm_setzero_si128().as_u16x8(),
1060 mask:k,
1061 ))
1062}
1063
1064/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst.
1065///
1066/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epu8&expand=5802)
1067#[inline]
1068#[target_feature(enable = "avx512bw")]
1069#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1070#[cfg_attr(test, assert_instr(vpsubusb))]
1071pub unsafe fn _mm512_subs_epu8(a: __m512i, b: __m512i) -> __m512i {
1072 transmute(src:vpsubusb(
1073 a:a.as_u8x64(),
1074 b:b.as_u8x64(),
1075 src:_mm512_setzero_si512().as_u8x64(),
1076 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
1077 ))
1078}
1079
1080/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1081///
1082/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epu8&expand=5800)
1083#[inline]
1084#[target_feature(enable = "avx512bw")]
1085#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1086#[cfg_attr(test, assert_instr(vpsubusb))]
1087pub unsafe fn _mm512_mask_subs_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1088 transmute(src:vpsubusb(a:a.as_u8x64(), b:b.as_u8x64(), src:src.as_u8x64(), mask:k))
1089}
1090
1091/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1092///
1093/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epu8&expand=5801)
1094#[inline]
1095#[target_feature(enable = "avx512bw")]
1096#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1097#[cfg_attr(test, assert_instr(vpsubusb))]
1098pub unsafe fn _mm512_maskz_subs_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1099 transmute(src:vpsubusb(
1100 a:a.as_u8x64(),
1101 b:b.as_u8x64(),
1102 src:_mm512_setzero_si512().as_u8x64(),
1103 mask:k,
1104 ))
1105}
1106
1107/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1108///
1109/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epu8&expand=5797)
1110#[inline]
1111#[target_feature(enable = "avx512bw,avx512vl")]
1112#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1113#[cfg_attr(test, assert_instr(vpsubusb))]
1114pub unsafe fn _mm256_mask_subs_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1115 transmute(src:vpsubusb256(a:a.as_u8x32(), b:b.as_u8x32(), src:src.as_u8x32(), mask:k))
1116}
1117
1118/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1119///
1120/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epu8&expand=5798)
1121#[inline]
1122#[target_feature(enable = "avx512bw,avx512vl")]
1123#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1124#[cfg_attr(test, assert_instr(vpsubusb))]
1125pub unsafe fn _mm256_maskz_subs_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1126 transmute(src:vpsubusb256(
1127 a:a.as_u8x32(),
1128 b:b.as_u8x32(),
1129 src:_mm256_setzero_si256().as_u8x32(),
1130 mask:k,
1131 ))
1132}
1133
1134/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1135///
1136/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epu8&expand=5794)
1137#[inline]
1138#[target_feature(enable = "avx512bw,avx512vl")]
1139#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1140#[cfg_attr(test, assert_instr(vpsubusb))]
1141pub unsafe fn _mm_mask_subs_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1142 transmute(src:vpsubusb128(a:a.as_u8x16(), b:b.as_u8x16(), src:src.as_u8x16(), mask:k))
1143}
1144
1145/// Subtract packed unsigned 8-bit integers in b from packed unsigned 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1146///
1147/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epu8&expand=5795)
1148#[inline]
1149#[target_feature(enable = "avx512bw,avx512vl")]
1150#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1151#[cfg_attr(test, assert_instr(vpsubusb))]
1152pub unsafe fn _mm_maskz_subs_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1153 transmute(src:vpsubusb128(
1154 a:a.as_u8x16(),
1155 b:b.as_u8x16(),
1156 src:_mm_setzero_si128().as_u8x16(),
1157 mask:k,
1158 ))
1159}
1160
1161/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst.
1162///
1163/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epi16&expand=5775)
1164#[inline]
1165#[target_feature(enable = "avx512bw")]
1166#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1167#[cfg_attr(test, assert_instr(vpsubsw))]
1168pub unsafe fn _mm512_subs_epi16(a: __m512i, b: __m512i) -> __m512i {
1169 transmute(src:vpsubsw(
1170 a:a.as_i16x32(),
1171 b:b.as_i16x32(),
1172 src:_mm512_setzero_si512().as_i16x32(),
1173 mask:0b11111111_11111111_11111111_11111111,
1174 ))
1175}
1176
1177/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1178///
1179/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epi16&expand=5773)
1180#[inline]
1181#[target_feature(enable = "avx512bw")]
1182#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1183#[cfg_attr(test, assert_instr(vpsubsw))]
1184pub unsafe fn _mm512_mask_subs_epi16(
1185 src: __m512i,
1186 k: __mmask32,
1187 a: __m512i,
1188 b: __m512i,
1189) -> __m512i {
1190 transmute(src:vpsubsw(a:a.as_i16x32(), b:b.as_i16x32(), src:src.as_i16x32(), mask:k))
1191}
1192
1193/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1194///
1195/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epi16&expand=5774)
1196#[inline]
1197#[target_feature(enable = "avx512bw")]
1198#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1199#[cfg_attr(test, assert_instr(vpsubsw))]
1200pub unsafe fn _mm512_maskz_subs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1201 transmute(src:vpsubsw(
1202 a:a.as_i16x32(),
1203 b:b.as_i16x32(),
1204 src:_mm512_setzero_si512().as_i16x32(),
1205 mask:k,
1206 ))
1207}
1208
1209/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1210///
1211/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epi16&expand=5770)
1212#[inline]
1213#[target_feature(enable = "avx512bw,avx512vl")]
1214#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1215#[cfg_attr(test, assert_instr(vpsubsw))]
1216pub unsafe fn _mm256_mask_subs_epi16(
1217 src: __m256i,
1218 k: __mmask16,
1219 a: __m256i,
1220 b: __m256i,
1221) -> __m256i {
1222 transmute(src:vpsubsw256(a:a.as_i16x16(), b:b.as_i16x16(), src:src.as_i16x16(), mask:k))
1223}
1224
1225/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1226///
1227/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epi16&expand=5771)
1228#[inline]
1229#[target_feature(enable = "avx512bw,avx512vl")]
1230#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1231#[cfg_attr(test, assert_instr(vpsubsw))]
1232pub unsafe fn _mm256_maskz_subs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1233 transmute(src:vpsubsw256(
1234 a:a.as_i16x16(),
1235 b:b.as_i16x16(),
1236 src:_mm256_setzero_si256().as_i16x16(),
1237 mask:k,
1238 ))
1239}
1240
1241/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1242///
1243/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epi16&expand=5767)
1244#[inline]
1245#[target_feature(enable = "avx512bw,avx512vl")]
1246#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1247#[cfg_attr(test, assert_instr(vpsubsw))]
1248pub unsafe fn _mm_mask_subs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1249 transmute(src:vpsubsw128(a:a.as_i16x8(), b:b.as_i16x8(), src:src.as_i16x8(), mask:k))
1250}
1251
1252/// Subtract packed signed 16-bit integers in b from packed 16-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1253///
1254/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epi16&expand=5768)
1255#[inline]
1256#[target_feature(enable = "avx512bw,avx512vl")]
1257#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1258#[cfg_attr(test, assert_instr(vpsubsw))]
1259pub unsafe fn _mm_maskz_subs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1260 transmute(src:vpsubsw128(
1261 a:a.as_i16x8(),
1262 b:b.as_i16x8(),
1263 src:_mm_setzero_si128().as_i16x8(),
1264 mask:k,
1265 ))
1266}
1267
1268/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst.
1269///
1270/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_subs_epi8&expand=5784)
1271#[inline]
1272#[target_feature(enable = "avx512bw")]
1273#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1274#[cfg_attr(test, assert_instr(vpsubsb))]
1275pub unsafe fn _mm512_subs_epi8(a: __m512i, b: __m512i) -> __m512i {
1276 transmute(src:vpsubsb(
1277 a:a.as_i8x64(),
1278 b:b.as_i8x64(),
1279 src:_mm512_setzero_si512().as_i8x64(),
1280 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
1281 ))
1282}
1283
1284/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1285///
1286/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_subs_epi8&expand=5782)
1287#[inline]
1288#[target_feature(enable = "avx512bw")]
1289#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1290#[cfg_attr(test, assert_instr(vpsubsb))]
1291pub unsafe fn _mm512_mask_subs_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1292 transmute(src:vpsubsb(a:a.as_i8x64(), b:b.as_i8x64(), src:src.as_i8x64(), mask:k))
1293}
1294
1295/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1296///
1297/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_subs_epi8&expand=5783)
1298#[inline]
1299#[target_feature(enable = "avx512bw")]
1300#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1301#[cfg_attr(test, assert_instr(vpsubsb))]
1302pub unsafe fn _mm512_maskz_subs_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1303 transmute(src:vpsubsb(
1304 a:a.as_i8x64(),
1305 b:b.as_i8x64(),
1306 src:_mm512_setzero_si512().as_i8x64(),
1307 mask:k,
1308 ))
1309}
1310
1311/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1312///
1313/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_subs_epi8&expand=5779)
1314#[inline]
1315#[target_feature(enable = "avx512bw,avx512vl")]
1316#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1317#[cfg_attr(test, assert_instr(vpsubsb))]
1318pub unsafe fn _mm256_mask_subs_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1319 transmute(src:vpsubsb256(a:a.as_i8x32(), b:b.as_i8x32(), src:src.as_i8x32(), mask:k))
1320}
1321
1322/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1323///
1324/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_subs_epi8&expand=5780)
1325#[inline]
1326#[target_feature(enable = "avx512bw,avx512vl")]
1327#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1328#[cfg_attr(test, assert_instr(vpsubsb))]
1329pub unsafe fn _mm256_maskz_subs_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1330 transmute(src:vpsubsb256(
1331 a:a.as_i8x32(),
1332 b:b.as_i8x32(),
1333 src:_mm256_setzero_si256().as_i8x32(),
1334 mask:k,
1335 ))
1336}
1337
1338/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1339///
1340/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_subs_epi8&expand=5776)
1341#[inline]
1342#[target_feature(enable = "avx512bw,avx512vl")]
1343#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1344#[cfg_attr(test, assert_instr(vpsubsb))]
1345pub unsafe fn _mm_mask_subs_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1346 transmute(src:vpsubsb128(a:a.as_i8x16(), b:b.as_i8x16(), src:src.as_i8x16(), mask:k))
1347}
1348
1349/// Subtract packed signed 8-bit integers in b from packed 8-bit integers in a using saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1350///
1351/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_subs_epi8&expand=5777)
1352#[inline]
1353#[target_feature(enable = "avx512bw,avx512vl")]
1354#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1355#[cfg_attr(test, assert_instr(vpsubsb))]
1356pub unsafe fn _mm_maskz_subs_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1357 transmute(src:vpsubsb128(
1358 a:a.as_i8x16(),
1359 b:b.as_i8x16(),
1360 src:_mm_setzero_si128().as_i8x16(),
1361 mask:k,
1362 ))
1363}
1364
1365/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst.
1366///
1367/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhi_epu16&expand=3973)
1368#[inline]
1369#[target_feature(enable = "avx512bw")]
1370#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1371#[cfg_attr(test, assert_instr(vpmulhuw))]
1372pub unsafe fn _mm512_mulhi_epu16(a: __m512i, b: __m512i) -> __m512i {
1373 transmute(src:vpmulhuw(a:a.as_u16x32(), b:b.as_u16x32()))
1374}
1375
1376/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1377///
1378/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhi_epu16&expand=3971)
1379#[inline]
1380#[target_feature(enable = "avx512bw")]
1381#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1382#[cfg_attr(test, assert_instr(vpmulhuw))]
1383pub unsafe fn _mm512_mask_mulhi_epu16(
1384 src: __m512i,
1385 k: __mmask32,
1386 a: __m512i,
1387 b: __m512i,
1388) -> __m512i {
1389 let mul: u16x32 = _mm512_mulhi_epu16(a, b).as_u16x32();
1390 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_u16x32()))
1391}
1392
1393/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1394///
1395/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhi_epu16&expand=3972)
1396#[inline]
1397#[target_feature(enable = "avx512bw")]
1398#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1399#[cfg_attr(test, assert_instr(vpmulhuw))]
1400pub unsafe fn _mm512_maskz_mulhi_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1401 let mul: u16x32 = _mm512_mulhi_epu16(a, b).as_u16x32();
1402 let zero: u16x32 = _mm512_setzero_si512().as_u16x32();
1403 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1404}
1405
1406/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1407///
1408/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhi_epu16&expand=3968)
1409#[inline]
1410#[target_feature(enable = "avx512bw,avx512vl")]
1411#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1412#[cfg_attr(test, assert_instr(vpmulhuw))]
1413pub unsafe fn _mm256_mask_mulhi_epu16(
1414 src: __m256i,
1415 k: __mmask16,
1416 a: __m256i,
1417 b: __m256i,
1418) -> __m256i {
1419 let mul: u16x16 = _mm256_mulhi_epu16(a, b).as_u16x16();
1420 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_u16x16()))
1421}
1422
1423/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1424///
1425/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhi_epu16&expand=3969)
1426#[inline]
1427#[target_feature(enable = "avx512bw,avx512vl")]
1428#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1429#[cfg_attr(test, assert_instr(vpmulhuw))]
1430pub unsafe fn _mm256_maskz_mulhi_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1431 let mul: u16x16 = _mm256_mulhi_epu16(a, b).as_u16x16();
1432 let zero: u16x16 = _mm256_setzero_si256().as_u16x16();
1433 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1434}
1435
1436/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1437///
1438/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhi_epu16&expand=3965)
1439#[inline]
1440#[target_feature(enable = "avx512bw,avx512vl")]
1441#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1442#[cfg_attr(test, assert_instr(vpmulhuw))]
1443pub unsafe fn _mm_mask_mulhi_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1444 let mul: u16x8 = _mm_mulhi_epu16(a, b).as_u16x8();
1445 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_u16x8()))
1446}
1447
1448/// Multiply the packed unsigned 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1449///
1450/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhi_epu16&expand=3966)
1451#[inline]
1452#[target_feature(enable = "avx512bw,avx512vl")]
1453#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1454#[cfg_attr(test, assert_instr(vpmulhuw))]
1455pub unsafe fn _mm_maskz_mulhi_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1456 let mul: u16x8 = _mm_mulhi_epu16(a, b).as_u16x8();
1457 let zero: u16x8 = _mm_setzero_si128().as_u16x8();
1458 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1459}
1460
1461/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst.
1462///
1463/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhi_epi16&expand=3962)
1464#[inline]
1465#[target_feature(enable = "avx512bw")]
1466#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1467#[cfg_attr(test, assert_instr(vpmulhw))]
1468pub unsafe fn _mm512_mulhi_epi16(a: __m512i, b: __m512i) -> __m512i {
1469 transmute(src:vpmulhw(a:a.as_i16x32(), b:b.as_i16x32()))
1470}
1471
1472/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1473///
1474/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhi_epi16&expand=3960)
1475#[inline]
1476#[target_feature(enable = "avx512bw")]
1477#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1478#[cfg_attr(test, assert_instr(vpmulhw))]
1479pub unsafe fn _mm512_mask_mulhi_epi16(
1480 src: __m512i,
1481 k: __mmask32,
1482 a: __m512i,
1483 b: __m512i,
1484) -> __m512i {
1485 let mul: i16x32 = _mm512_mulhi_epi16(a, b).as_i16x32();
1486 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x32()))
1487}
1488
1489/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1490///
1491/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhi_epi16&expand=3961)
1492#[inline]
1493#[target_feature(enable = "avx512bw")]
1494#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1495#[cfg_attr(test, assert_instr(vpmulhw))]
1496pub unsafe fn _mm512_maskz_mulhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1497 let mul: i16x32 = _mm512_mulhi_epi16(a, b).as_i16x32();
1498 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
1499 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1500}
1501
1502/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1503///
1504/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhi_epi16&expand=3957)
1505#[inline]
1506#[target_feature(enable = "avx512bw,avx512vl")]
1507#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1508#[cfg_attr(test, assert_instr(vpmulhw))]
1509pub unsafe fn _mm256_mask_mulhi_epi16(
1510 src: __m256i,
1511 k: __mmask16,
1512 a: __m256i,
1513 b: __m256i,
1514) -> __m256i {
1515 let mul: i16x16 = _mm256_mulhi_epi16(a, b).as_i16x16();
1516 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x16()))
1517}
1518
1519/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1520///
1521/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhi_epi16&expand=3958)
1522#[inline]
1523#[target_feature(enable = "avx512bw,avx512vl")]
1524#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1525#[cfg_attr(test, assert_instr(vpmulhw))]
1526pub unsafe fn _mm256_maskz_mulhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1527 let mul: i16x16 = _mm256_mulhi_epi16(a, b).as_i16x16();
1528 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
1529 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1530}
1531
1532/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1533///
1534/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhi_epi16&expand=3954)
1535#[inline]
1536#[target_feature(enable = "avx512bw,avx512vl")]
1537#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1538#[cfg_attr(test, assert_instr(vpmulhw))]
1539pub unsafe fn _mm_mask_mulhi_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1540 let mul: i16x8 = _mm_mulhi_epi16(a, b).as_i16x8();
1541 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x8()))
1542}
1543
1544/// Multiply the packed signed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1545///
1546/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhi_epi16&expand=3955)
1547#[inline]
1548#[target_feature(enable = "avx512bw,avx512vl")]
1549#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1550#[cfg_attr(test, assert_instr(vpmulhw))]
1551pub unsafe fn _mm_maskz_mulhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1552 let mul: i16x8 = _mm_mulhi_epi16(a, b).as_i16x8();
1553 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
1554 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1555}
1556
1557/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst.
1558///
1559/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mulhrs_epi16&expand=3986)
1560#[inline]
1561#[target_feature(enable = "avx512bw")]
1562#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1563#[cfg_attr(test, assert_instr(vpmulhrsw))]
1564pub unsafe fn _mm512_mulhrs_epi16(a: __m512i, b: __m512i) -> __m512i {
1565 transmute(src:vpmulhrsw(a:a.as_i16x32(), b:b.as_i16x32()))
1566}
1567
1568/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1569///
1570/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mulhrs_epi16&expand=3984)
1571#[inline]
1572#[target_feature(enable = "avx512bw")]
1573#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1574#[cfg_attr(test, assert_instr(vpmulhrsw))]
1575pub unsafe fn _mm512_mask_mulhrs_epi16(
1576 src: __m512i,
1577 k: __mmask32,
1578 a: __m512i,
1579 b: __m512i,
1580) -> __m512i {
1581 let mul: i16x32 = _mm512_mulhrs_epi16(a, b).as_i16x32();
1582 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x32()))
1583}
1584
1585/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1586///
1587/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mulhrs_epi16&expand=3985)
1588#[inline]
1589#[target_feature(enable = "avx512bw")]
1590#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1591#[cfg_attr(test, assert_instr(vpmulhrsw))]
1592pub unsafe fn _mm512_maskz_mulhrs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1593 let mul: i16x32 = _mm512_mulhrs_epi16(a, b).as_i16x32();
1594 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
1595 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1596}
1597
1598/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1599///
1600/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mulhrs_epi16&expand=3981)
1601#[inline]
1602#[target_feature(enable = "avx512bw,avx512vl")]
1603#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1604#[cfg_attr(test, assert_instr(vpmulhrsw))]
1605pub unsafe fn _mm256_mask_mulhrs_epi16(
1606 src: __m256i,
1607 k: __mmask16,
1608 a: __m256i,
1609 b: __m256i,
1610) -> __m256i {
1611 let mul: i16x16 = _mm256_mulhrs_epi16(a, b).as_i16x16();
1612 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x16()))
1613}
1614
1615/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1616///
1617/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mulhrs_epi16&expand=3982)
1618#[inline]
1619#[target_feature(enable = "avx512bw,avx512vl")]
1620#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1621#[cfg_attr(test, assert_instr(vpmulhrsw))]
1622pub unsafe fn _mm256_maskz_mulhrs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1623 let mul: i16x16 = _mm256_mulhrs_epi16(a, b).as_i16x16();
1624 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
1625 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1626}
1627
1628/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1629///
1630/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mulhrs_epi16&expand=3978)
1631#[inline]
1632#[target_feature(enable = "avx512bw,avx512vl")]
1633#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1634#[cfg_attr(test, assert_instr(vpmulhrsw))]
1635pub unsafe fn _mm_mask_mulhrs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1636 let mul: i16x8 = _mm_mulhrs_epi16(a, b).as_i16x8();
1637 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x8()))
1638}
1639
1640/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits \[16:1\] to dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1641///
1642/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mulhrs_epi16&expand=3979)
1643#[inline]
1644#[target_feature(enable = "avx512bw,avx512vl")]
1645#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1646#[cfg_attr(test, assert_instr(vpmulhrsw))]
1647pub unsafe fn _mm_maskz_mulhrs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1648 let mul: i16x8 = _mm_mulhrs_epi16(a, b).as_i16x8();
1649 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
1650 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1651}
1652
1653/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst.
1654///
1655/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mullo_epi16&expand=3996)
1656#[inline]
1657#[target_feature(enable = "avx512bw")]
1658#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1659#[cfg_attr(test, assert_instr(vpmullw))]
1660pub unsafe fn _mm512_mullo_epi16(a: __m512i, b: __m512i) -> __m512i {
1661 transmute(src:simd_mul(x:a.as_i16x32(), y:b.as_i16x32()))
1662}
1663
1664/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1665///
1666/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mullo_epi16&expand=3994)
1667#[inline]
1668#[target_feature(enable = "avx512bw")]
1669#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1670#[cfg_attr(test, assert_instr(vpmullw))]
1671pub unsafe fn _mm512_mask_mullo_epi16(
1672 src: __m512i,
1673 k: __mmask32,
1674 a: __m512i,
1675 b: __m512i,
1676) -> __m512i {
1677 let mul: i16x32 = _mm512_mullo_epi16(a, b).as_i16x32();
1678 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x32()))
1679}
1680
1681/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1682///
1683/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mullo_epi16&expand=3995)
1684#[inline]
1685#[target_feature(enable = "avx512bw")]
1686#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1687#[cfg_attr(test, assert_instr(vpmullw))]
1688pub unsafe fn _mm512_maskz_mullo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1689 let mul: i16x32 = _mm512_mullo_epi16(a, b).as_i16x32();
1690 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
1691 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1692}
1693
1694/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1695///
1696/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mullo_epi16&expand=3991)
1697#[inline]
1698#[target_feature(enable = "avx512bw,avx512vl")]
1699#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1700#[cfg_attr(test, assert_instr(vpmullw))]
1701pub unsafe fn _mm256_mask_mullo_epi16(
1702 src: __m256i,
1703 k: __mmask16,
1704 a: __m256i,
1705 b: __m256i,
1706) -> __m256i {
1707 let mul: i16x16 = _mm256_mullo_epi16(a, b).as_i16x16();
1708 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x16()))
1709}
1710
1711/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1712///
1713/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mullo_epi16&expand=3992)
1714#[inline]
1715#[target_feature(enable = "avx512bw,avx512vl")]
1716#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1717#[cfg_attr(test, assert_instr(vpmullw))]
1718pub unsafe fn _mm256_maskz_mullo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1719 let mul: i16x16 = _mm256_mullo_epi16(a, b).as_i16x16();
1720 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
1721 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1722}
1723
1724/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1725///
1726/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mullo_epi16&expand=3988)
1727#[inline]
1728#[target_feature(enable = "avx512bw,avx512vl")]
1729#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1730#[cfg_attr(test, assert_instr(vpmullw))]
1731pub unsafe fn _mm_mask_mullo_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1732 let mul: i16x8 = _mm_mullo_epi16(a, b).as_i16x8();
1733 transmute(src:simd_select_bitmask(m:k, yes:mul, no:src.as_i16x8()))
1734}
1735
1736/// Multiply the packed 16-bit integers in a and b, producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1737///
1738/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mullo_epi16&expand=3989)
1739#[inline]
1740#[target_feature(enable = "avx512bw,avx512vl")]
1741#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1742#[cfg_attr(test, assert_instr(vpmullw))]
1743pub unsafe fn _mm_maskz_mullo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1744 let mul: i16x8 = _mm_mullo_epi16(a, b).as_i16x8();
1745 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
1746 transmute(src:simd_select_bitmask(m:k, yes:mul, no:zero))
1747}
1748
1749/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst.
1750///
1751/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu16&expand=3609)
1752#[inline]
1753#[target_feature(enable = "avx512bw")]
1754#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1755#[cfg_attr(test, assert_instr(vpmaxuw))]
1756pub unsafe fn _mm512_max_epu16(a: __m512i, b: __m512i) -> __m512i {
1757 transmute(src:vpmaxuw(a:a.as_u16x32(), b:b.as_u16x32()))
1758}
1759
1760/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1761///
1762/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu16&expand=3607)
1763#[inline]
1764#[target_feature(enable = "avx512bw")]
1765#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1766#[cfg_attr(test, assert_instr(vpmaxuw))]
1767pub unsafe fn _mm512_mask_max_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1768 let max: u16x32 = _mm512_max_epu16(a, b).as_u16x32();
1769 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u16x32()))
1770}
1771
1772/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1773///
1774/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu16&expand=3608)
1775#[inline]
1776#[target_feature(enable = "avx512bw")]
1777#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1778#[cfg_attr(test, assert_instr(vpmaxuw))]
1779pub unsafe fn _mm512_maskz_max_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1780 let max: u16x32 = _mm512_max_epu16(a, b).as_u16x32();
1781 let zero: u16x32 = _mm512_setzero_si512().as_u16x32();
1782 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1783}
1784
1785/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1786///
1787/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu16&expand=3604)
1788#[inline]
1789#[target_feature(enable = "avx512bw,avx512vl")]
1790#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1791#[cfg_attr(test, assert_instr(vpmaxuw))]
1792pub unsafe fn _mm256_mask_max_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1793 let max: u16x16 = _mm256_max_epu16(a, b).as_u16x16();
1794 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u16x16()))
1795}
1796
1797/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1798///
1799/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu16&expand=3605)
1800#[inline]
1801#[target_feature(enable = "avx512bw,avx512vl")]
1802#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1803#[cfg_attr(test, assert_instr(vpmaxuw))]
1804pub unsafe fn _mm256_maskz_max_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1805 let max: u16x16 = _mm256_max_epu16(a, b).as_u16x16();
1806 let zero: u16x16 = _mm256_setzero_si256().as_u16x16();
1807 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1808}
1809
1810/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1811///
1812/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu16&expand=3601)
1813#[inline]
1814#[target_feature(enable = "avx512bw,avx512vl")]
1815#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1816#[cfg_attr(test, assert_instr(vpmaxuw))]
1817pub unsafe fn _mm_mask_max_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1818 let max: u16x8 = _mm_max_epu16(a, b).as_u16x8();
1819 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u16x8()))
1820}
1821
1822/// Compare packed unsigned 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1823///
1824/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu16&expand=3602)
1825#[inline]
1826#[target_feature(enable = "avx512bw,avx512vl")]
1827#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1828#[cfg_attr(test, assert_instr(vpmaxuw))]
1829pub unsafe fn _mm_maskz_max_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1830 let max: u16x8 = _mm_max_epu16(a, b).as_u16x8();
1831 let zero: u16x8 = _mm_setzero_si128().as_u16x8();
1832 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1833}
1834
1835/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst.
1836///
1837/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epu8&expand=3636)
1838#[inline]
1839#[target_feature(enable = "avx512bw")]
1840#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1841#[cfg_attr(test, assert_instr(vpmaxub))]
1842pub unsafe fn _mm512_max_epu8(a: __m512i, b: __m512i) -> __m512i {
1843 transmute(src:vpmaxub(a:a.as_u8x64(), b:b.as_u8x64()))
1844}
1845
1846/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1847///
1848/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epu8&expand=3634)
1849#[inline]
1850#[target_feature(enable = "avx512bw")]
1851#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1852#[cfg_attr(test, assert_instr(vpmaxub))]
1853pub unsafe fn _mm512_mask_max_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1854 let max: u8x64 = _mm512_max_epu8(a, b).as_u8x64();
1855 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u8x64()))
1856}
1857
1858/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1859///
1860/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epu8&expand=3635)
1861#[inline]
1862#[target_feature(enable = "avx512bw")]
1863#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1864#[cfg_attr(test, assert_instr(vpmaxub))]
1865pub unsafe fn _mm512_maskz_max_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
1866 let max: u8x64 = _mm512_max_epu8(a, b).as_u8x64();
1867 let zero: u8x64 = _mm512_setzero_si512().as_u8x64();
1868 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1869}
1870
1871/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1872///
1873/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epu8&expand=3631)
1874#[inline]
1875#[target_feature(enable = "avx512bw,avx512vl")]
1876#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1877#[cfg_attr(test, assert_instr(vpmaxub))]
1878pub unsafe fn _mm256_mask_max_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1879 let max: u8x32 = _mm256_max_epu8(a, b).as_u8x32();
1880 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u8x32()))
1881}
1882
1883/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1884///
1885/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epu8&expand=3632)
1886#[inline]
1887#[target_feature(enable = "avx512bw,avx512vl")]
1888#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1889#[cfg_attr(test, assert_instr(vpmaxub))]
1890pub unsafe fn _mm256_maskz_max_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
1891 let max: u8x32 = _mm256_max_epu8(a, b).as_u8x32();
1892 let zero: u8x32 = _mm256_setzero_si256().as_u8x32();
1893 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1894}
1895
1896/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1897///
1898/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epu8&expand=3628)
1899#[inline]
1900#[target_feature(enable = "avx512bw,avx512vl")]
1901#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1902#[cfg_attr(test, assert_instr(vpmaxub))]
1903pub unsafe fn _mm_mask_max_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1904 let max: u8x16 = _mm_max_epu8(a, b).as_u8x16();
1905 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_u8x16()))
1906}
1907
1908/// Compare packed unsigned 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1909///
1910/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epu8&expand=3629)
1911#[inline]
1912#[target_feature(enable = "avx512bw,avx512vl")]
1913#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1914#[cfg_attr(test, assert_instr(vpmaxub))]
1915pub unsafe fn _mm_maskz_max_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
1916 let max: u8x16 = _mm_max_epu8(a, b).as_u8x16();
1917 let zero: u8x16 = _mm_setzero_si128().as_u8x16();
1918 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1919}
1920
1921/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst.
1922///
1923/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi16&expand=3573)
1924#[inline]
1925#[target_feature(enable = "avx512bw")]
1926#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1927#[cfg_attr(test, assert_instr(vpmaxsw))]
1928pub unsafe fn _mm512_max_epi16(a: __m512i, b: __m512i) -> __m512i {
1929 transmute(src:vpmaxsw(a:a.as_i16x32(), b:b.as_i16x32()))
1930}
1931
1932/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1933///
1934/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi16&expand=3571)
1935#[inline]
1936#[target_feature(enable = "avx512bw")]
1937#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1938#[cfg_attr(test, assert_instr(vpmaxsw))]
1939pub unsafe fn _mm512_mask_max_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1940 let max: i16x32 = _mm512_max_epi16(a, b).as_i16x32();
1941 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i16x32()))
1942}
1943
1944/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1945///
1946/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi16&expand=3572)
1947#[inline]
1948#[target_feature(enable = "avx512bw")]
1949#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1950#[cfg_attr(test, assert_instr(vpmaxsw))]
1951pub unsafe fn _mm512_maskz_max_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
1952 let max: i16x32 = _mm512_max_epi16(a, b).as_i16x32();
1953 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
1954 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1955}
1956
1957/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1958///
1959/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi16&expand=3568)
1960#[inline]
1961#[target_feature(enable = "avx512bw,avx512vl")]
1962#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1963#[cfg_attr(test, assert_instr(vpmaxsw))]
1964pub unsafe fn _mm256_mask_max_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1965 let max: i16x16 = _mm256_max_epi16(a, b).as_i16x16();
1966 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i16x16()))
1967}
1968
1969/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1970///
1971/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi16&expand=3569)
1972#[inline]
1973#[target_feature(enable = "avx512bw,avx512vl")]
1974#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1975#[cfg_attr(test, assert_instr(vpmaxsw))]
1976pub unsafe fn _mm256_maskz_max_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
1977 let max: i16x16 = _mm256_max_epi16(a, b).as_i16x16();
1978 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
1979 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
1980}
1981
1982/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
1983///
1984/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi16&expand=3565)
1985#[inline]
1986#[target_feature(enable = "avx512bw,avx512vl")]
1987#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
1988#[cfg_attr(test, assert_instr(vpmaxsw))]
1989pub unsafe fn _mm_mask_max_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
1990 let max: i16x8 = _mm_max_epi16(a, b).as_i16x8();
1991 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i16x8()))
1992}
1993
1994/// Compare packed signed 16-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
1995///
1996/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi16&expand=3566)
1997#[inline]
1998#[target_feature(enable = "avx512bw,avx512vl")]
1999#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2000#[cfg_attr(test, assert_instr(vpmaxsw))]
2001pub unsafe fn _mm_maskz_max_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
2002 let max: i16x8 = _mm_max_epi16(a, b).as_i16x8();
2003 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
2004 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
2005}
2006
2007/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst.
2008///
2009/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_max_epi8&expand=3600)
2010#[inline]
2011#[target_feature(enable = "avx512bw")]
2012#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2013#[cfg_attr(test, assert_instr(vpmaxsb))]
2014pub unsafe fn _mm512_max_epi8(a: __m512i, b: __m512i) -> __m512i {
2015 transmute(src:vpmaxsb(a:a.as_i8x64(), b:b.as_i8x64()))
2016}
2017
2018/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2019///
2020/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_max_epi8&expand=3598)
2021#[inline]
2022#[target_feature(enable = "avx512bw")]
2023#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2024#[cfg_attr(test, assert_instr(vpmaxsb))]
2025pub unsafe fn _mm512_mask_max_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2026 let max: i8x64 = _mm512_max_epi8(a, b).as_i8x64();
2027 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i8x64()))
2028}
2029
2030/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2031///
2032/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_max_epi8&expand=3599)
2033#[inline]
2034#[target_feature(enable = "avx512bw")]
2035#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2036#[cfg_attr(test, assert_instr(vpmaxsb))]
2037pub unsafe fn _mm512_maskz_max_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2038 let max: i8x64 = _mm512_max_epi8(a, b).as_i8x64();
2039 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
2040 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
2041}
2042
2043/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2044///
2045/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_max_epi8&expand=3595)
2046#[inline]
2047#[target_feature(enable = "avx512bw,avx512vl")]
2048#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2049#[cfg_attr(test, assert_instr(vpmaxsb))]
2050pub unsafe fn _mm256_mask_max_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2051 let max: i8x32 = _mm256_max_epi8(a, b).as_i8x32();
2052 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i8x32()))
2053}
2054
2055/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2056///
2057/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_max_epi8&expand=3596)
2058#[inline]
2059#[target_feature(enable = "avx512bw,avx512vl")]
2060#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2061#[cfg_attr(test, assert_instr(vpmaxsb))]
2062pub unsafe fn _mm256_maskz_max_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2063 let max: i8x32 = _mm256_max_epi8(a, b).as_i8x32();
2064 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
2065 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
2066}
2067
2068/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2069///
2070/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_max_epi8&expand=3592)
2071#[inline]
2072#[target_feature(enable = "avx512bw,avx512vl")]
2073#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2074#[cfg_attr(test, assert_instr(vpmaxsb))]
2075pub unsafe fn _mm_mask_max_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2076 let max: i8x16 = _mm_max_epi8(a, b).as_i8x16();
2077 transmute(src:simd_select_bitmask(m:k, yes:max, no:src.as_i8x16()))
2078}
2079
2080/// Compare packed signed 8-bit integers in a and b, and store packed maximum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2081///
2082/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_max_epi8&expand=3593)
2083#[inline]
2084#[target_feature(enable = "avx512bw,avx512vl")]
2085#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2086#[cfg_attr(test, assert_instr(vpmaxsb))]
2087pub unsafe fn _mm_maskz_max_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2088 let max: i8x16 = _mm_max_epi8(a, b).as_i8x16();
2089 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
2090 transmute(src:simd_select_bitmask(m:k, yes:max, no:zero))
2091}
2092
2093/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst.
2094///
2095/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu16&expand=3723)
2096#[inline]
2097#[target_feature(enable = "avx512bw")]
2098#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2099#[cfg_attr(test, assert_instr(vpminuw))]
2100pub unsafe fn _mm512_min_epu16(a: __m512i, b: __m512i) -> __m512i {
2101 transmute(src:vpminuw(a:a.as_u16x32(), b:b.as_u16x32()))
2102}
2103
2104/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2105///
2106/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu16&expand=3721)
2107#[inline]
2108#[target_feature(enable = "avx512bw")]
2109#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2110#[cfg_attr(test, assert_instr(vpminuw))]
2111pub unsafe fn _mm512_mask_min_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
2112 let min: u16x32 = _mm512_min_epu16(a, b).as_u16x32();
2113 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u16x32()))
2114}
2115
2116/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2117///
2118/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu16&expand=3722)
2119#[inline]
2120#[target_feature(enable = "avx512bw")]
2121#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2122#[cfg_attr(test, assert_instr(vpminuw))]
2123pub unsafe fn _mm512_maskz_min_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
2124 let min: u16x32 = _mm512_min_epu16(a, b).as_u16x32();
2125 let zero: u16x32 = _mm512_setzero_si512().as_u16x32();
2126 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2127}
2128
2129/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2130///
2131/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu16&expand=3718)
2132#[inline]
2133#[target_feature(enable = "avx512bw,avx512vl")]
2134#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2135#[cfg_attr(test, assert_instr(vpminuw))]
2136pub unsafe fn _mm256_mask_min_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
2137 let min: u16x16 = _mm256_min_epu16(a, b).as_u16x16();
2138 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u16x16()))
2139}
2140
2141/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2142///
2143/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu16&expand=3719)
2144#[inline]
2145#[target_feature(enable = "avx512bw,avx512vl")]
2146#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2147#[cfg_attr(test, assert_instr(vpminuw))]
2148pub unsafe fn _mm256_maskz_min_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
2149 let min: u16x16 = _mm256_min_epu16(a, b).as_u16x16();
2150 let zero: u16x16 = _mm256_setzero_si256().as_u16x16();
2151 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2152}
2153
2154/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2155///
2156/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu16&expand=3715)
2157#[inline]
2158#[target_feature(enable = "avx512bw,avx512vl")]
2159#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2160#[cfg_attr(test, assert_instr(vpminuw))]
2161pub unsafe fn _mm_mask_min_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
2162 let min: u16x8 = _mm_min_epu16(a, b).as_u16x8();
2163 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u16x8()))
2164}
2165
2166/// Compare packed unsigned 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2167///
2168/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu16&expand=3716)
2169#[inline]
2170#[target_feature(enable = "avx512bw,avx512vl")]
2171#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2172#[cfg_attr(test, assert_instr(vpminuw))]
2173pub unsafe fn _mm_maskz_min_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
2174 let min: u16x8 = _mm_min_epu16(a, b).as_u16x8();
2175 let zero: u16x8 = _mm_setzero_si128().as_u16x8();
2176 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2177}
2178
2179/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst.
2180///
2181/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epu8&expand=3750)
2182#[inline]
2183#[target_feature(enable = "avx512bw")]
2184#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2185#[cfg_attr(test, assert_instr(vpminub))]
2186pub unsafe fn _mm512_min_epu8(a: __m512i, b: __m512i) -> __m512i {
2187 transmute(src:vpminub(a:a.as_u8x64(), b:b.as_u8x64()))
2188}
2189
2190/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2191///
2192/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epu8&expand=3748)
2193#[inline]
2194#[target_feature(enable = "avx512bw")]
2195#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2196#[cfg_attr(test, assert_instr(vpminub))]
2197pub unsafe fn _mm512_mask_min_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2198 let min: u8x64 = _mm512_min_epu8(a, b).as_u8x64();
2199 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u8x64()))
2200}
2201
2202/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2203///
2204/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epu8&expand=3749)
2205#[inline]
2206#[target_feature(enable = "avx512bw")]
2207#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2208#[cfg_attr(test, assert_instr(vpminub))]
2209pub unsafe fn _mm512_maskz_min_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2210 let min: u8x64 = _mm512_min_epu8(a, b).as_u8x64();
2211 let zero: u8x64 = _mm512_setzero_si512().as_u8x64();
2212 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2213}
2214
2215/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2216///
2217/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epu8&expand=3745)
2218#[inline]
2219#[target_feature(enable = "avx512bw,avx512vl")]
2220#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2221#[cfg_attr(test, assert_instr(vpminub))]
2222pub unsafe fn _mm256_mask_min_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2223 let min: u8x32 = _mm256_min_epu8(a, b).as_u8x32();
2224 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u8x32()))
2225}
2226
2227/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2228///
2229/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epu8&expand=3746)
2230#[inline]
2231#[target_feature(enable = "avx512bw,avx512vl")]
2232#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2233#[cfg_attr(test, assert_instr(vpminub))]
2234pub unsafe fn _mm256_maskz_min_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2235 let min: u8x32 = _mm256_min_epu8(a, b).as_u8x32();
2236 let zero: u8x32 = _mm256_setzero_si256().as_u8x32();
2237 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2238}
2239
2240/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2241///
2242/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epu8&expand=3742)
2243#[inline]
2244#[target_feature(enable = "avx512bw,avx512vl")]
2245#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2246#[cfg_attr(test, assert_instr(vpminub))]
2247pub unsafe fn _mm_mask_min_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2248 let min: u8x16 = _mm_min_epu8(a, b).as_u8x16();
2249 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_u8x16()))
2250}
2251
2252/// Compare packed unsigned 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2253///
2254/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epu8&expand=3743)
2255#[inline]
2256#[target_feature(enable = "avx512bw,avx512vl")]
2257#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2258#[cfg_attr(test, assert_instr(vpminub))]
2259pub unsafe fn _mm_maskz_min_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2260 let min: u8x16 = _mm_min_epu8(a, b).as_u8x16();
2261 let zero: u8x16 = _mm_setzero_si128().as_u8x16();
2262 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2263}
2264
2265/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst.
2266///
2267/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi16&expand=3687)
2268#[inline]
2269#[target_feature(enable = "avx512bw")]
2270#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2271#[cfg_attr(test, assert_instr(vpminsw))]
2272pub unsafe fn _mm512_min_epi16(a: __m512i, b: __m512i) -> __m512i {
2273 transmute(src:vpminsw(a:a.as_i16x32(), b:b.as_i16x32()))
2274}
2275
2276/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2277///
2278/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi16&expand=3685)
2279#[inline]
2280#[target_feature(enable = "avx512bw")]
2281#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2282#[cfg_attr(test, assert_instr(vpminsw))]
2283pub unsafe fn _mm512_mask_min_epi16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
2284 let min: i16x32 = _mm512_min_epi16(a, b).as_i16x32();
2285 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i16x32()))
2286}
2287
2288/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2289///
2290/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi16&expand=3686)
2291#[inline]
2292#[target_feature(enable = "avx512bw")]
2293#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2294#[cfg_attr(test, assert_instr(vpminsw))]
2295pub unsafe fn _mm512_maskz_min_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
2296 let min: i16x32 = _mm512_min_epi16(a, b).as_i16x32();
2297 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
2298 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2299}
2300
2301/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2302///
2303/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi16&expand=3682)
2304#[inline]
2305#[target_feature(enable = "avx512bw,avx512vl")]
2306#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2307#[cfg_attr(test, assert_instr(vpminsw))]
2308pub unsafe fn _mm256_mask_min_epi16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
2309 let min: i16x16 = _mm256_min_epi16(a, b).as_i16x16();
2310 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i16x16()))
2311}
2312
2313/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2314///
2315/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi16&expand=3683)
2316#[inline]
2317#[target_feature(enable = "avx512bw,avx512vl")]
2318#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2319#[cfg_attr(test, assert_instr(vpminsw))]
2320pub unsafe fn _mm256_maskz_min_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
2321 let min: i16x16 = _mm256_min_epi16(a, b).as_i16x16();
2322 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
2323 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2324}
2325
2326/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2327///
2328/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi16&expand=3679)
2329#[inline]
2330#[target_feature(enable = "avx512bw,avx512vl")]
2331#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2332#[cfg_attr(test, assert_instr(vpminsw))]
2333pub unsafe fn _mm_mask_min_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
2334 let min: i16x8 = _mm_min_epi16(a, b).as_i16x8();
2335 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i16x8()))
2336}
2337
2338/// Compare packed signed 16-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2339///
2340/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi16&expand=3680)
2341#[inline]
2342#[target_feature(enable = "avx512bw,avx512vl")]
2343#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2344#[cfg_attr(test, assert_instr(vpminsw))]
2345pub unsafe fn _mm_maskz_min_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
2346 let min: i16x8 = _mm_min_epi16(a, b).as_i16x8();
2347 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
2348 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2349}
2350
2351/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst.
2352///
2353/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_min_epi8&expand=3714)
2354#[inline]
2355#[target_feature(enable = "avx512bw")]
2356#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2357#[cfg_attr(test, assert_instr(vpminsb))]
2358pub unsafe fn _mm512_min_epi8(a: __m512i, b: __m512i) -> __m512i {
2359 transmute(src:vpminsb(a:a.as_i8x64(), b:b.as_i8x64()))
2360}
2361
2362/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2363///
2364/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_min_epi8&expand=3712)
2365#[inline]
2366#[target_feature(enable = "avx512bw")]
2367#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2368#[cfg_attr(test, assert_instr(vpminsb))]
2369pub unsafe fn _mm512_mask_min_epi8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2370 let min: i8x64 = _mm512_min_epi8(a, b).as_i8x64();
2371 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i8x64()))
2372}
2373
2374/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2375///
2376/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_min_epi8&expand=3713)
2377#[inline]
2378#[target_feature(enable = "avx512bw")]
2379#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2380#[cfg_attr(test, assert_instr(vpminsb))]
2381pub unsafe fn _mm512_maskz_min_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
2382 let min: i8x64 = _mm512_min_epi8(a, b).as_i8x64();
2383 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
2384 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2385}
2386
2387/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2388///
2389/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_min_epi8&expand=3709)
2390#[inline]
2391#[target_feature(enable = "avx512bw,avx512vl")]
2392#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2393#[cfg_attr(test, assert_instr(vpminsb))]
2394pub unsafe fn _mm256_mask_min_epi8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2395 let min: i8x32 = _mm256_min_epi8(a, b).as_i8x32();
2396 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i8x32()))
2397}
2398
2399/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2400///
2401/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_min_epi8&expand=3710)
2402#[inline]
2403#[target_feature(enable = "avx512bw,avx512vl")]
2404#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2405#[cfg_attr(test, assert_instr(vpminsb))]
2406pub unsafe fn _mm256_maskz_min_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
2407 let min: i8x32 = _mm256_min_epi8(a, b).as_i8x32();
2408 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
2409 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2410}
2411
2412/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
2413///
2414/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_min_epi8&expand=3706)
2415#[inline]
2416#[target_feature(enable = "avx512bw,avx512vl")]
2417#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2418#[cfg_attr(test, assert_instr(vpminsb))]
2419pub unsafe fn _mm_mask_min_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2420 let min: i8x16 = _mm_min_epi8(a, b).as_i8x16();
2421 transmute(src:simd_select_bitmask(m:k, yes:min, no:src.as_i8x16()))
2422}
2423
2424/// Compare packed signed 8-bit integers in a and b, and store packed minimum values in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
2425///
2426/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_min_epi8&expand=3707)
2427#[inline]
2428#[target_feature(enable = "avx512bw,avx512vl")]
2429#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2430#[cfg_attr(test, assert_instr(vpminsb))]
2431pub unsafe fn _mm_maskz_min_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
2432 let min: i8x16 = _mm_min_epi8(a, b).as_i8x16();
2433 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
2434 transmute(src:simd_select_bitmask(m:k, yes:min, no:zero))
2435}
2436
2437/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k.
2438///
2439/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=512_cmplt_epu16_mask&expand=1050)
2440#[inline]
2441#[target_feature(enable = "avx512bw")]
2442#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2443#[cfg_attr(test, assert_instr(vpcmp))]
2444pub unsafe fn _mm512_cmplt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
2445 simd_bitmask::<u16x32, _>(simd_lt(x:a.as_u16x32(), y:b.as_u16x32()))
2446}
2447
2448/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2449///
2450/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu16_mask&expand=1051)
2451#[inline]
2452#[target_feature(enable = "avx512bw")]
2453#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2454#[cfg_attr(test, assert_instr(vpcmp))]
2455pub unsafe fn _mm512_mask_cmplt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
2456 _mm512_cmplt_epu16_mask(a, b) & k1
2457}
2458
2459/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k.
2460///
2461/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=512_cmplt_epu16_mask&expand=1050)
2462#[inline]
2463#[target_feature(enable = "avx512bw,avx512vl")]
2464#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2465#[cfg_attr(test, assert_instr(vpcmp))]
2466pub unsafe fn _mm256_cmplt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
2467 simd_bitmask::<u16x16, _>(simd_lt(x:a.as_u16x16(), y:b.as_u16x16()))
2468}
2469
2470/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2471///
2472/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu16_mask&expand=1049)
2473#[inline]
2474#[target_feature(enable = "avx512bw,avx512vl")]
2475#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2476#[cfg_attr(test, assert_instr(vpcmp))]
2477pub unsafe fn _mm256_mask_cmplt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
2478 _mm256_cmplt_epu16_mask(a, b) & k1
2479}
2480
2481/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k.
2482///
2483/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi16_mask&expand=1018)
2484#[inline]
2485#[target_feature(enable = "avx512bw,avx512vl")]
2486#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2487#[cfg_attr(test, assert_instr(vpcmp))]
2488pub unsafe fn _mm_cmplt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
2489 simd_bitmask::<u16x8, _>(simd_lt(x:a.as_u16x8(), y:b.as_u16x8()))
2490}
2491
2492/// Compare packed unsigned 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2493///
2494/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi16_mask&expand=1019)
2495#[inline]
2496#[target_feature(enable = "avx512bw,avx512vl")]
2497#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2498#[cfg_attr(test, assert_instr(vpcmp))]
2499pub unsafe fn _mm_mask_cmplt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
2500 _mm_cmplt_epu16_mask(a, b) & k1
2501}
2502
2503/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k.
2504///
2505/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=mm512_cmplt_epu8_mask&expand=1068)
2506#[inline]
2507#[target_feature(enable = "avx512bw")]
2508#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2509#[cfg_attr(test, assert_instr(vpcmp))]
2510pub unsafe fn _mm512_cmplt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
2511 simd_bitmask::<u8x64, _>(simd_lt(x:a.as_u8x64(), y:b.as_u8x64()))
2512}
2513
2514/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2515///
2516/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epu8_mask&expand=1069)
2517#[inline]
2518#[target_feature(enable = "avx512bw")]
2519#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2520#[cfg_attr(test, assert_instr(vpcmp))]
2521pub unsafe fn _mm512_mask_cmplt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
2522 _mm512_cmplt_epu8_mask(a, b) & k1
2523}
2524
2525/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k.
2526///
2527/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epu8_mask&expand=1066)
2528#[inline]
2529#[target_feature(enable = "avx512bw,avx512vl")]
2530#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2531#[cfg_attr(test, assert_instr(vpcmp))]
2532pub unsafe fn _mm256_cmplt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
2533 simd_bitmask::<u8x32, _>(simd_lt(x:a.as_u8x32(), y:b.as_u8x32()))
2534}
2535
2536/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2537///
2538/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epu8_mask&expand=1067)
2539#[inline]
2540#[target_feature(enable = "avx512bw,avx512vl")]
2541#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2542#[cfg_attr(test, assert_instr(vpcmp))]
2543pub unsafe fn _mm256_mask_cmplt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
2544 _mm256_cmplt_epu8_mask(a, b) & k1
2545}
2546
2547/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k.
2548///
2549/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epu8_mask&expand=1064)
2550#[inline]
2551#[target_feature(enable = "avx512bw,avx512vl")]
2552#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2553#[cfg_attr(test, assert_instr(vpcmp))]
2554pub unsafe fn _mm_cmplt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
2555 simd_bitmask::<u8x16, _>(simd_lt(x:a.as_u8x16(), y:b.as_u8x16()))
2556}
2557
2558/// Compare packed unsigned 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2559///
2560/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epu8_mask&expand=1065)
2561#[inline]
2562#[target_feature(enable = "avx512bw,avx512vl")]
2563#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2564#[cfg_attr(test, assert_instr(vpcmp))]
2565pub unsafe fn _mm_mask_cmplt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
2566 _mm_cmplt_epu8_mask(a, b) & k1
2567}
2568
2569/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k.
2570///
2571/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi16_mask&expand=1022)
2572#[inline]
2573#[target_feature(enable = "avx512bw")]
2574#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2575#[cfg_attr(test, assert_instr(vpcmp))]
2576pub unsafe fn _mm512_cmplt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
2577 simd_bitmask::<i16x32, _>(simd_lt(x:a.as_i16x32(), y:b.as_i16x32()))
2578}
2579
2580/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2581///
2582/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi16_mask&expand=1023)
2583#[inline]
2584#[target_feature(enable = "avx512bw")]
2585#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2586#[cfg_attr(test, assert_instr(vpcmp))]
2587pub unsafe fn _mm512_mask_cmplt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
2588 _mm512_cmplt_epi16_mask(a, b) & k1
2589}
2590
2591/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k.
2592///
2593/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi16_mask&expand=1020)
2594#[inline]
2595#[target_feature(enable = "avx512bw,avx512vl")]
2596#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2597#[cfg_attr(test, assert_instr(vpcmp))]
2598pub unsafe fn _mm256_cmplt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
2599 simd_bitmask::<i16x16, _>(simd_lt(x:a.as_i16x16(), y:b.as_i16x16()))
2600}
2601
2602/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2603///
2604/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi16_mask&expand=1021)
2605#[inline]
2606#[target_feature(enable = "avx512bw,avx512vl")]
2607#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2608#[cfg_attr(test, assert_instr(vpcmp))]
2609pub unsafe fn _mm256_mask_cmplt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
2610 _mm256_cmplt_epi16_mask(a, b) & k1
2611}
2612
2613/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k.
2614///
2615/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi16_mask&expand=1018)
2616#[inline]
2617#[target_feature(enable = "avx512bw,avx512vl")]
2618#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2619#[cfg_attr(test, assert_instr(vpcmp))]
2620pub unsafe fn _mm_cmplt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
2621 simd_bitmask::<i16x8, _>(simd_lt(x:a.as_i16x8(), y:b.as_i16x8()))
2622}
2623
2624/// Compare packed signed 16-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2625///
2626/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi16_mask&expand=1019)
2627#[inline]
2628#[target_feature(enable = "avx512bw,avx512vl")]
2629#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2630#[cfg_attr(test, assert_instr(vpcmp))]
2631pub unsafe fn _mm_mask_cmplt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
2632 _mm_cmplt_epi16_mask(a, b) & k1
2633}
2634
2635/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k.
2636///
2637/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmplt_epi8_mask&expand=1044)
2638#[inline]
2639#[target_feature(enable = "avx512bw")]
2640#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2641#[cfg_attr(test, assert_instr(vpcmp))]
2642pub unsafe fn _mm512_cmplt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
2643 simd_bitmask::<i8x64, _>(simd_lt(x:a.as_i8x64(), y:b.as_i8x64()))
2644}
2645
2646/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2647///
2648/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmplt_epi8_mask&expand=1045)
2649#[inline]
2650#[target_feature(enable = "avx512bw")]
2651#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2652#[cfg_attr(test, assert_instr(vpcmp))]
2653pub unsafe fn _mm512_mask_cmplt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
2654 _mm512_cmplt_epi8_mask(a, b) & k1
2655}
2656
2657/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k.
2658///
2659/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmplt_epi8_mask&expand=1042)
2660#[inline]
2661#[target_feature(enable = "avx512bw,avx512vl")]
2662#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2663#[cfg_attr(test, assert_instr(vpcmp))]
2664pub unsafe fn _mm256_cmplt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
2665 simd_bitmask::<i8x32, _>(simd_lt(x:a.as_i8x32(), y:b.as_i8x32()))
2666}
2667
2668/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2669///
2670/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmplt_epi8_mask&expand=1043)
2671#[inline]
2672#[target_feature(enable = "avx512bw,avx512vl")]
2673#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2674#[cfg_attr(test, assert_instr(vpcmp))]
2675pub unsafe fn _mm256_mask_cmplt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
2676 _mm256_cmplt_epi8_mask(a, b) & k1
2677}
2678
2679/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k.
2680///
2681/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi8_mask&expand=1040)
2682#[inline]
2683#[target_feature(enable = "avx512bw,avx512vl")]
2684#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2685#[cfg_attr(test, assert_instr(vpcmp))]
2686pub unsafe fn _mm_cmplt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
2687 simd_bitmask::<i8x16, _>(simd_lt(x:a.as_i8x16(), y:b.as_i8x16()))
2688}
2689
2690/// Compare packed signed 8-bit integers in a and b for less-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2691///
2692/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmplt_epi8_mask&expand=1041)
2693#[inline]
2694#[target_feature(enable = "avx512bw,avx512vl")]
2695#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2696#[cfg_attr(test, assert_instr(vpcmp))]
2697pub unsafe fn _mm_mask_cmplt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
2698 _mm_cmplt_epi8_mask(a, b) & k1
2699}
2700
2701/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2702///
2703/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu16_mask&expand=927)
2704#[inline]
2705#[target_feature(enable = "avx512bw")]
2706#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2707#[cfg_attr(test, assert_instr(vpcmp))]
2708pub unsafe fn _mm512_cmpgt_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
2709 simd_bitmask::<u16x32, _>(simd_gt(x:a.as_u16x32(), y:b.as_u16x32()))
2710}
2711
2712/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2713///
2714/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu16_mask&expand=928)
2715#[inline]
2716#[target_feature(enable = "avx512bw")]
2717#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2718#[cfg_attr(test, assert_instr(vpcmp))]
2719pub unsafe fn _mm512_mask_cmpgt_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
2720 _mm512_cmpgt_epu16_mask(a, b) & k1
2721}
2722
2723/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2724///
2725/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu16_mask&expand=925)
2726#[inline]
2727#[target_feature(enable = "avx512bw,avx512vl")]
2728#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2729#[cfg_attr(test, assert_instr(vpcmp))]
2730pub unsafe fn _mm256_cmpgt_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
2731 simd_bitmask::<u16x16, _>(simd_gt(x:a.as_u16x16(), y:b.as_u16x16()))
2732}
2733
2734/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2735///
2736/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu16_mask&expand=926)
2737#[inline]
2738#[target_feature(enable = "avx512bw,avx512vl")]
2739#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2740#[cfg_attr(test, assert_instr(vpcmp))]
2741pub unsafe fn _mm256_mask_cmpgt_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
2742 _mm256_cmpgt_epu16_mask(a, b) & k1
2743}
2744
2745/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2746///
2747/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu16_mask&expand=923)
2748#[inline]
2749#[target_feature(enable = "avx512bw,avx512vl")]
2750#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2751#[cfg_attr(test, assert_instr(vpcmp))]
2752pub unsafe fn _mm_cmpgt_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
2753 simd_bitmask::<u16x8, _>(simd_gt(x:a.as_u16x8(), y:b.as_u16x8()))
2754}
2755
2756/// Compare packed unsigned 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2757///
2758/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu16_mask&expand=924)
2759#[inline]
2760#[target_feature(enable = "avx512bw,avx512vl")]
2761#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2762#[cfg_attr(test, assert_instr(vpcmp))]
2763pub unsafe fn _mm_mask_cmpgt_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
2764 _mm_cmpgt_epu16_mask(a, b) & k1
2765}
2766
2767/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2768///
2769/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epu8_mask&expand=945)
2770#[inline]
2771#[target_feature(enable = "avx512bw")]
2772#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2773#[cfg_attr(test, assert_instr(vpcmp))]
2774pub unsafe fn _mm512_cmpgt_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
2775 simd_bitmask::<u8x64, _>(simd_gt(x:a.as_u8x64(), y:b.as_u8x64()))
2776}
2777
2778/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2779///
2780/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epu8_mask&expand=946)
2781#[inline]
2782#[target_feature(enable = "avx512bw")]
2783#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2784#[cfg_attr(test, assert_instr(vpcmp))]
2785pub unsafe fn _mm512_mask_cmpgt_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
2786 _mm512_cmpgt_epu8_mask(a, b) & k1
2787}
2788
2789/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2790///
2791/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epu8_mask&expand=943)
2792#[inline]
2793#[target_feature(enable = "avx512bw,avx512vl")]
2794#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2795#[cfg_attr(test, assert_instr(vpcmp))]
2796pub unsafe fn _mm256_cmpgt_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
2797 simd_bitmask::<u8x32, _>(simd_gt(x:a.as_u8x32(), y:b.as_u8x32()))
2798}
2799
2800/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2801///
2802/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epu8_mask&expand=944)
2803#[inline]
2804#[target_feature(enable = "avx512bw,avx512vl")]
2805#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2806#[cfg_attr(test, assert_instr(vpcmp))]
2807pub unsafe fn _mm256_mask_cmpgt_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
2808 _mm256_cmpgt_epu8_mask(a, b) & k1
2809}
2810
2811/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2812///
2813/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epu8_mask&expand=941)
2814#[inline]
2815#[target_feature(enable = "avx512bw,avx512vl")]
2816#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2817#[cfg_attr(test, assert_instr(vpcmp))]
2818pub unsafe fn _mm_cmpgt_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
2819 simd_bitmask::<u8x16, _>(simd_gt(x:a.as_u8x16(), y:b.as_u8x16()))
2820}
2821
2822/// Compare packed unsigned 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2823///
2824/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epu8_mask&expand=942)
2825#[inline]
2826#[target_feature(enable = "avx512bw,avx512vl")]
2827#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2828#[cfg_attr(test, assert_instr(vpcmp))]
2829pub unsafe fn _mm_mask_cmpgt_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
2830 _mm_cmpgt_epu8_mask(a, b) & k1
2831}
2832
2833/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2834///
2835/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi16_mask&expand=897)
2836#[inline]
2837#[target_feature(enable = "avx512bw")]
2838#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2839#[cfg_attr(test, assert_instr(vpcmp))]
2840pub unsafe fn _mm512_cmpgt_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
2841 simd_bitmask::<i16x32, _>(simd_gt(x:a.as_i16x32(), y:b.as_i16x32()))
2842}
2843
2844/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2845///
2846/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi16_mask&expand=898)
2847#[inline]
2848#[target_feature(enable = "avx512bw")]
2849#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2850#[cfg_attr(test, assert_instr(vpcmp))]
2851pub unsafe fn _mm512_mask_cmpgt_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
2852 _mm512_cmpgt_epi16_mask(a, b) & k1
2853}
2854
2855/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2856///
2857/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi16_mask&expand=895)
2858#[inline]
2859#[target_feature(enable = "avx512bw,avx512vl")]
2860#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2861#[cfg_attr(test, assert_instr(vpcmp))]
2862pub unsafe fn _mm256_cmpgt_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
2863 simd_bitmask::<i16x16, _>(simd_gt(x:a.as_i16x16(), y:b.as_i16x16()))
2864}
2865
2866/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2867///
2868/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi16_mask&expand=896)
2869#[inline]
2870#[target_feature(enable = "avx512bw,avx512vl")]
2871#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2872#[cfg_attr(test, assert_instr(vpcmp))]
2873pub unsafe fn _mm256_mask_cmpgt_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
2874 _mm256_cmpgt_epi16_mask(a, b) & k1
2875}
2876
2877/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k.
2878///
2879/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi16_mask&expand=893)
2880#[inline]
2881#[target_feature(enable = "avx512bw,avx512vl")]
2882#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2883#[cfg_attr(test, assert_instr(vpcmp))]
2884pub unsafe fn _mm_cmpgt_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
2885 simd_bitmask::<i16x8, _>(simd_gt(x:a.as_i16x8(), y:b.as_i16x8()))
2886}
2887
2888/// Compare packed signed 16-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2889///
2890/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi16_mask&expand=894)
2891#[inline]
2892#[target_feature(enable = "avx512bw,avx512vl")]
2893#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2894#[cfg_attr(test, assert_instr(vpcmp))]
2895pub unsafe fn _mm_mask_cmpgt_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
2896 _mm_cmpgt_epi16_mask(a, b) & k1
2897}
2898
2899/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2900///
2901/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpgt_epi8_mask&expand=921)
2902#[inline]
2903#[target_feature(enable = "avx512bw")]
2904#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2905#[cfg_attr(test, assert_instr(vpcmp))]
2906pub unsafe fn _mm512_cmpgt_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
2907 simd_bitmask::<i8x64, _>(simd_gt(x:a.as_i8x64(), y:b.as_i8x64()))
2908}
2909
2910/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2911///
2912/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpgt_epi8_mask&expand=922)
2913#[inline]
2914#[target_feature(enable = "avx512bw")]
2915#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2916#[cfg_attr(test, assert_instr(vpcmp))]
2917pub unsafe fn _mm512_mask_cmpgt_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
2918 _mm512_cmpgt_epi8_mask(a, b) & k1
2919}
2920
2921/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2922///
2923/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpgt_epi8_mask&expand=919)
2924#[inline]
2925#[target_feature(enable = "avx512bw,avx512vl")]
2926#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2927#[cfg_attr(test, assert_instr(vpcmp))]
2928pub unsafe fn _mm256_cmpgt_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
2929 simd_bitmask::<i8x32, _>(simd_gt(x:a.as_i8x32(), y:b.as_i8x32()))
2930}
2931
2932/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2933///
2934/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpgt_epi8_mask&expand=920)
2935#[inline]
2936#[target_feature(enable = "avx512bw,avx512vl")]
2937#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2938#[cfg_attr(test, assert_instr(vpcmp))]
2939pub unsafe fn _mm256_mask_cmpgt_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
2940 _mm256_cmpgt_epi8_mask(a, b) & k1
2941}
2942
2943/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k.
2944///
2945/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi8_mask&expand=917)
2946#[inline]
2947#[target_feature(enable = "avx512bw,avx512vl")]
2948#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2949#[cfg_attr(test, assert_instr(vpcmp))]
2950pub unsafe fn _mm_cmpgt_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
2951 simd_bitmask::<i8x16, _>(simd_gt(x:a.as_i8x16(), y:b.as_i8x16()))
2952}
2953
2954/// Compare packed signed 8-bit integers in a and b for greater-than, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2955///
2956/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpgt_epi8_mask&expand=918)
2957#[inline]
2958#[target_feature(enable = "avx512bw,avx512vl")]
2959#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2960#[cfg_attr(test, assert_instr(vpcmp))]
2961pub unsafe fn _mm_mask_cmpgt_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
2962 _mm_cmpgt_epi8_mask(a, b) & k1
2963}
2964
2965/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
2966///
2967/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu16_mask&expand=989)
2968#[inline]
2969#[target_feature(enable = "avx512bw")]
2970#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2971#[cfg_attr(test, assert_instr(vpcmp))]
2972pub unsafe fn _mm512_cmple_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
2973 simd_bitmask::<u16x32, _>(simd_le(x:a.as_u16x32(), y:b.as_u16x32()))
2974}
2975
2976/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2977///
2978/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu16_mask&expand=990)
2979#[inline]
2980#[target_feature(enable = "avx512bw")]
2981#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2982#[cfg_attr(test, assert_instr(vpcmp))]
2983pub unsafe fn _mm512_mask_cmple_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
2984 _mm512_cmple_epu16_mask(a, b) & k1
2985}
2986
2987/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
2988///
2989/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu16_mask&expand=987)
2990#[inline]
2991#[target_feature(enable = "avx512bw,avx512vl")]
2992#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
2993#[cfg_attr(test, assert_instr(vpcmp))]
2994pub unsafe fn _mm256_cmple_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
2995 simd_bitmask::<u16x16, _>(simd_le(x:a.as_u16x16(), y:b.as_u16x16()))
2996}
2997
2998/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
2999///
3000/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu16_mask&expand=988)
3001#[inline]
3002#[target_feature(enable = "avx512bw,avx512vl")]
3003#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3004#[cfg_attr(test, assert_instr(vpcmp))]
3005pub unsafe fn _mm256_mask_cmple_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3006 _mm256_cmple_epu16_mask(a, b) & k1
3007}
3008
3009/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3010///
3011/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu16_mask&expand=985)
3012#[inline]
3013#[target_feature(enable = "avx512bw,avx512vl")]
3014#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3015#[cfg_attr(test, assert_instr(vpcmp))]
3016pub unsafe fn _mm_cmple_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3017 simd_bitmask::<u16x8, _>(simd_le(x:a.as_u16x8(), y:b.as_u16x8()))
3018}
3019
3020/// Compare packed unsigned 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3021///
3022/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu16_mask&expand=986)
3023#[inline]
3024#[target_feature(enable = "avx512bw,avx512vl")]
3025#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3026#[cfg_attr(test, assert_instr(vpcmp))]
3027pub unsafe fn _mm_mask_cmple_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3028 _mm_cmple_epu16_mask(a, b) & k1
3029}
3030
3031/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3032///
3033/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epu8_mask&expand=1007)
3034#[inline]
3035#[target_feature(enable = "avx512bw")]
3036#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3037#[cfg_attr(test, assert_instr(vpcmp))]
3038pub unsafe fn _mm512_cmple_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3039 simd_bitmask::<u8x64, _>(simd_le(x:a.as_u8x64(), y:b.as_u8x64()))
3040}
3041
3042/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3043///
3044/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epu8_mask&expand=1008)
3045#[inline]
3046#[target_feature(enable = "avx512bw")]
3047#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3048#[cfg_attr(test, assert_instr(vpcmp))]
3049pub unsafe fn _mm512_mask_cmple_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3050 _mm512_cmple_epu8_mask(a, b) & k1
3051}
3052
3053/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3054///
3055/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epu8_mask&expand=1005)
3056#[inline]
3057#[target_feature(enable = "avx512bw,avx512vl")]
3058#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3059#[cfg_attr(test, assert_instr(vpcmp))]
3060pub unsafe fn _mm256_cmple_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3061 simd_bitmask::<u8x32, _>(simd_le(x:a.as_u8x32(), y:b.as_u8x32()))
3062}
3063
3064/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3065///
3066/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epu8_mask&expand=1006)
3067#[inline]
3068#[target_feature(enable = "avx512bw,avx512vl")]
3069#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3070#[cfg_attr(test, assert_instr(vpcmp))]
3071pub unsafe fn _mm256_mask_cmple_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3072 _mm256_cmple_epu8_mask(a, b) & k1
3073}
3074
3075/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3076///
3077/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epu8_mask&expand=1003)
3078#[inline]
3079#[target_feature(enable = "avx512bw,avx512vl")]
3080#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3081#[cfg_attr(test, assert_instr(vpcmp))]
3082pub unsafe fn _mm_cmple_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3083 simd_bitmask::<u8x16, _>(simd_le(x:a.as_u8x16(), y:b.as_u8x16()))
3084}
3085
3086/// Compare packed unsigned 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3087///
3088/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epu8_mask&expand=1004)
3089#[inline]
3090#[target_feature(enable = "avx512bw,avx512vl")]
3091#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3092#[cfg_attr(test, assert_instr(vpcmp))]
3093pub unsafe fn _mm_mask_cmple_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3094 _mm_cmple_epu8_mask(a, b) & k1
3095}
3096
3097/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3098///
3099/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi16_mask&expand=965)
3100#[inline]
3101#[target_feature(enable = "avx512bw")]
3102#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3103#[cfg_attr(test, assert_instr(vpcmp))]
3104pub unsafe fn _mm512_cmple_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3105 simd_bitmask::<i16x32, _>(simd_le(x:a.as_i16x32(), y:b.as_i16x32()))
3106}
3107
3108/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3109///
3110/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi16_mask&expand=966)
3111#[inline]
3112#[target_feature(enable = "avx512bw")]
3113#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3114#[cfg_attr(test, assert_instr(vpcmp))]
3115pub unsafe fn _mm512_mask_cmple_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3116 _mm512_cmple_epi16_mask(a, b) & k1
3117}
3118
3119/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3120///
3121/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi16_mask&expand=963)
3122#[inline]
3123#[target_feature(enable = "avx512bw,avx512vl")]
3124#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3125#[cfg_attr(test, assert_instr(vpcmp))]
3126pub unsafe fn _mm256_cmple_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3127 simd_bitmask::<i16x16, _>(simd_le(x:a.as_i16x16(), y:b.as_i16x16()))
3128}
3129
3130/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3131///
3132/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi16_mask&expand=964)
3133#[inline]
3134#[target_feature(enable = "avx512bw,avx512vl")]
3135#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3136#[cfg_attr(test, assert_instr(vpcmp))]
3137pub unsafe fn _mm256_mask_cmple_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3138 _mm256_cmple_epi16_mask(a, b) & k1
3139}
3140
3141/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3142///
3143/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi16_mask&expand=961)
3144#[inline]
3145#[target_feature(enable = "avx512bw,avx512vl")]
3146#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3147#[cfg_attr(test, assert_instr(vpcmp))]
3148pub unsafe fn _mm_cmple_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3149 simd_bitmask::<i16x8, _>(simd_le(x:a.as_i16x8(), y:b.as_i16x8()))
3150}
3151
3152/// Compare packed signed 16-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3153///
3154/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi16_mask&expand=962)
3155#[inline]
3156#[target_feature(enable = "avx512bw,avx512vl")]
3157#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3158#[cfg_attr(test, assert_instr(vpcmp))]
3159pub unsafe fn _mm_mask_cmple_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3160 _mm_cmple_epi16_mask(a, b) & k1
3161}
3162
3163/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3164///
3165/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmple_epi8_mask&expand=983)
3166#[inline]
3167#[target_feature(enable = "avx512bw")]
3168#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3169#[cfg_attr(test, assert_instr(vpcmp))]
3170pub unsafe fn _mm512_cmple_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3171 simd_bitmask::<i8x64, _>(simd_le(x:a.as_i8x64(), y:b.as_i8x64()))
3172}
3173
3174/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3175///
3176/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmple_epi8_mask&expand=984)
3177#[inline]
3178#[target_feature(enable = "avx512bw")]
3179#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3180#[cfg_attr(test, assert_instr(vpcmp))]
3181pub unsafe fn _mm512_mask_cmple_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3182 _mm512_cmple_epi8_mask(a, b) & k1
3183}
3184
3185/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3186///
3187/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmple_epi8_mask&expand=981)
3188#[inline]
3189#[target_feature(enable = "avx512bw,avx512vl")]
3190#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3191#[cfg_attr(test, assert_instr(vpcmp))]
3192pub unsafe fn _mm256_cmple_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3193 simd_bitmask::<i8x32, _>(simd_le(x:a.as_i8x32(), y:b.as_i8x32()))
3194}
3195
3196/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3197///
3198/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmple_epi8_mask&expand=982)
3199#[inline]
3200#[target_feature(enable = "avx512bw,avx512vl")]
3201#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3202#[cfg_attr(test, assert_instr(vpcmp))]
3203pub unsafe fn _mm256_mask_cmple_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3204 _mm256_cmple_epi8_mask(a, b) & k1
3205}
3206
3207/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k.
3208///
3209/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_epi8_mask&expand=979)
3210#[inline]
3211#[target_feature(enable = "avx512bw,avx512vl")]
3212#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3213#[cfg_attr(test, assert_instr(vpcmp))]
3214pub unsafe fn _mm_cmple_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3215 simd_bitmask::<i8x16, _>(simd_le(x:a.as_i8x16(), y:b.as_i8x16()))
3216}
3217
3218/// Compare packed signed 8-bit integers in a and b for less-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3219///
3220/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmple_epi8_mask&expand=980)
3221#[inline]
3222#[target_feature(enable = "avx512bw,avx512vl")]
3223#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3224#[cfg_attr(test, assert_instr(vpcmp))]
3225pub unsafe fn _mm_mask_cmple_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3226 _mm_cmple_epi8_mask(a, b) & k1
3227}
3228
3229/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3230///
3231/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu16_mask&expand=867)
3232#[inline]
3233#[target_feature(enable = "avx512bw")]
3234#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3235#[cfg_attr(test, assert_instr(vpcmp))]
3236pub unsafe fn _mm512_cmpge_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3237 simd_bitmask::<u16x32, _>(simd_ge(x:a.as_u16x32(), y:b.as_u16x32()))
3238}
3239
3240/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3241///
3242/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu16_mask&expand=868)
3243#[inline]
3244#[target_feature(enable = "avx512bw")]
3245#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3246#[cfg_attr(test, assert_instr(vpcmp))]
3247pub unsafe fn _mm512_mask_cmpge_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3248 _mm512_cmpge_epu16_mask(a, b) & k1
3249}
3250
3251/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3252///
3253/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu16_mask&expand=865)
3254#[inline]
3255#[target_feature(enable = "avx512bw,avx512vl")]
3256#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3257#[cfg_attr(test, assert_instr(vpcmp))]
3258pub unsafe fn _mm256_cmpge_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3259 simd_bitmask::<u16x16, _>(simd_ge(x:a.as_u16x16(), y:b.as_u16x16()))
3260}
3261
3262/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3263///
3264/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu16_mask&expand=866)
3265#[inline]
3266#[target_feature(enable = "avx512bw,avx512vl")]
3267#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3268#[cfg_attr(test, assert_instr(vpcmp))]
3269pub unsafe fn _mm256_mask_cmpge_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3270 _mm256_cmpge_epu16_mask(a, b) & k1
3271}
3272
3273/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3274///
3275/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu16_mask&expand=863)
3276#[inline]
3277#[target_feature(enable = "avx512bw,avx512vl")]
3278#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3279#[cfg_attr(test, assert_instr(vpcmp))]
3280pub unsafe fn _mm_cmpge_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3281 simd_bitmask::<u16x8, _>(simd_ge(x:a.as_u16x8(), y:b.as_u16x8()))
3282}
3283
3284/// Compare packed unsigned 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3285///
3286/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu16_mask&expand=864)
3287#[inline]
3288#[target_feature(enable = "avx512bw,avx512vl")]
3289#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3290#[cfg_attr(test, assert_instr(vpcmp))]
3291pub unsafe fn _mm_mask_cmpge_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3292 _mm_cmpge_epu16_mask(a, b) & k1
3293}
3294
3295/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3296///
3297/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epu8_mask&expand=885)
3298#[inline]
3299#[target_feature(enable = "avx512bw")]
3300#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3301#[cfg_attr(test, assert_instr(vpcmp))]
3302pub unsafe fn _mm512_cmpge_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3303 simd_bitmask::<u8x64, _>(simd_ge(x:a.as_u8x64(), y:b.as_u8x64()))
3304}
3305
3306/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3307///
3308/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epu8_mask&expand=886)
3309#[inline]
3310#[target_feature(enable = "avx512bw")]
3311#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3312#[cfg_attr(test, assert_instr(vpcmp))]
3313pub unsafe fn _mm512_mask_cmpge_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3314 _mm512_cmpge_epu8_mask(a, b) & k1
3315}
3316
3317/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3318///
3319/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epu8_mask&expand=883)
3320#[inline]
3321#[target_feature(enable = "avx512bw,avx512vl")]
3322#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3323#[cfg_attr(test, assert_instr(vpcmp))]
3324pub unsafe fn _mm256_cmpge_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3325 simd_bitmask::<u8x32, _>(simd_ge(x:a.as_u8x32(), y:b.as_u8x32()))
3326}
3327
3328/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3329///
3330/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epu8_mask&expand=884)
3331#[inline]
3332#[target_feature(enable = "avx512bw,avx512vl")]
3333#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3334#[cfg_attr(test, assert_instr(vpcmp))]
3335pub unsafe fn _mm256_mask_cmpge_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3336 _mm256_cmpge_epu8_mask(a, b) & k1
3337}
3338
3339/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3340///
3341/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epu8_mask&expand=881)
3342#[inline]
3343#[target_feature(enable = "avx512bw,avx512vl")]
3344#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3345#[cfg_attr(test, assert_instr(vpcmp))]
3346pub unsafe fn _mm_cmpge_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3347 simd_bitmask::<u8x16, _>(simd_ge(x:a.as_u8x16(), y:b.as_u8x16()))
3348}
3349
3350/// Compare packed unsigned 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3351///
3352/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epu8_mask&expand=882)
3353#[inline]
3354#[target_feature(enable = "avx512bw,avx512vl")]
3355#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3356#[cfg_attr(test, assert_instr(vpcmp))]
3357pub unsafe fn _mm_mask_cmpge_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3358 _mm_cmpge_epu8_mask(a, b) & k1
3359}
3360
3361/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3362///
3363/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi16_mask&expand=843)
3364#[inline]
3365#[target_feature(enable = "avx512bw")]
3366#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3367#[cfg_attr(test, assert_instr(vpcmp))]
3368pub unsafe fn _mm512_cmpge_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3369 simd_bitmask::<i16x32, _>(simd_ge(x:a.as_i16x32(), y:b.as_i16x32()))
3370}
3371
3372/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3373///
3374/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi16_mask&expand=844)
3375#[inline]
3376#[target_feature(enable = "avx512bw")]
3377#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3378#[cfg_attr(test, assert_instr(vpcmp))]
3379pub unsafe fn _mm512_mask_cmpge_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3380 _mm512_cmpge_epi16_mask(a, b) & k1
3381}
3382
3383/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3384///
3385/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi16_mask&expand=841)
3386#[inline]
3387#[target_feature(enable = "avx512bw,avx512vl")]
3388#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3389#[cfg_attr(test, assert_instr(vpcmp))]
3390pub unsafe fn _mm256_cmpge_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3391 simd_bitmask::<i16x16, _>(simd_ge(x:a.as_i16x16(), y:b.as_i16x16()))
3392}
3393
3394/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3395///
3396/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi16_mask&expand=842)
3397#[inline]
3398#[target_feature(enable = "avx512bw,avx512vl")]
3399#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3400#[cfg_attr(test, assert_instr(vpcmp))]
3401pub unsafe fn _mm256_mask_cmpge_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3402 _mm256_cmpge_epi16_mask(a, b) & k1
3403}
3404
3405/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3406///
3407/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi16_mask&expand=839)
3408#[inline]
3409#[target_feature(enable = "avx512bw,avx512vl")]
3410#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3411#[cfg_attr(test, assert_instr(vpcmp))]
3412pub unsafe fn _mm_cmpge_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3413 simd_bitmask::<i16x8, _>(simd_ge(x:a.as_i16x8(), y:b.as_i16x8()))
3414}
3415
3416/// Compare packed signed 16-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3417///
3418/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi16_mask&expand=840)
3419#[inline]
3420#[target_feature(enable = "avx512bw,avx512vl")]
3421#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3422#[cfg_attr(test, assert_instr(vpcmp))]
3423pub unsafe fn _mm_mask_cmpge_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3424 _mm_cmpge_epi16_mask(a, b) & k1
3425}
3426
3427/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3428///
3429/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpge_epi8_mask&expand=861)
3430#[inline]
3431#[target_feature(enable = "avx512bw")]
3432#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3433#[cfg_attr(test, assert_instr(vpcmp))]
3434pub unsafe fn _mm512_cmpge_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3435 simd_bitmask::<i8x64, _>(simd_ge(x:a.as_i8x64(), y:b.as_i8x64()))
3436}
3437
3438/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3439///
3440/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpge_epi8_mask&expand=862)
3441#[inline]
3442#[target_feature(enable = "avx512bw")]
3443#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3444#[cfg_attr(test, assert_instr(vpcmp))]
3445pub unsafe fn _mm512_mask_cmpge_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3446 _mm512_cmpge_epi8_mask(a, b) & k1
3447}
3448
3449/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3450///
3451/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpge_epi8_mask&expand=859)
3452#[inline]
3453#[target_feature(enable = "avx512bw,avx512vl")]
3454#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3455#[cfg_attr(test, assert_instr(vpcmp))]
3456pub unsafe fn _mm256_cmpge_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3457 simd_bitmask::<i8x32, _>(simd_ge(x:a.as_i8x32(), y:b.as_i8x32()))
3458}
3459
3460/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3461///
3462/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpge_epi8_mask&expand=860)
3463#[inline]
3464#[target_feature(enable = "avx512bw,avx512vl")]
3465#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3466#[cfg_attr(test, assert_instr(vpcmp))]
3467pub unsafe fn _mm256_mask_cmpge_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3468 _mm256_cmpge_epi8_mask(a, b) & k1
3469}
3470
3471/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k.
3472///
3473/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_epi8_mask&expand=857)
3474#[inline]
3475#[target_feature(enable = "avx512bw,avx512vl")]
3476#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3477#[cfg_attr(test, assert_instr(vpcmp))]
3478pub unsafe fn _mm_cmpge_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3479 simd_bitmask::<i8x16, _>(simd_ge(x:a.as_i8x16(), y:b.as_i8x16()))
3480}
3481
3482/// Compare packed signed 8-bit integers in a and b for greater-than-or-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3483///
3484/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpge_epi8_mask&expand=858)
3485#[inline]
3486#[target_feature(enable = "avx512bw,avx512vl")]
3487#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3488#[cfg_attr(test, assert_instr(vpcmp))]
3489pub unsafe fn _mm_mask_cmpge_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3490 _mm_cmpge_epi8_mask(a, b) & k1
3491}
3492
3493/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k.
3494///
3495/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu16_mask&expand=801)
3496#[inline]
3497#[target_feature(enable = "avx512bw")]
3498#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3499#[cfg_attr(test, assert_instr(vpcmp))]
3500pub unsafe fn _mm512_cmpeq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3501 simd_bitmask::<u16x32, _>(simd_eq(x:a.as_u16x32(), y:b.as_u16x32()))
3502}
3503
3504/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3505///
3506/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu16_mask&expand=802)
3507#[inline]
3508#[target_feature(enable = "avx512bw")]
3509#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3510#[cfg_attr(test, assert_instr(vpcmp))]
3511pub unsafe fn _mm512_mask_cmpeq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3512 _mm512_cmpeq_epu16_mask(a, b) & k1
3513}
3514
3515/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k.
3516///
3517/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu16_mask&expand=799)
3518#[inline]
3519#[target_feature(enable = "avx512bw,avx512vl")]
3520#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3521#[cfg_attr(test, assert_instr(vpcmp))]
3522pub unsafe fn _mm256_cmpeq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3523 simd_bitmask::<u16x16, _>(simd_eq(x:a.as_u16x16(), y:b.as_u16x16()))
3524}
3525
3526/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3527///
3528/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu16_mask&expand=800)
3529#[inline]
3530#[target_feature(enable = "avx512bw,avx512vl")]
3531#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3532#[cfg_attr(test, assert_instr(vpcmp))]
3533pub unsafe fn _mm256_mask_cmpeq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3534 _mm256_cmpeq_epu16_mask(a, b) & k1
3535}
3536
3537/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k.
3538///
3539/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu16_mask&expand=797)
3540#[inline]
3541#[target_feature(enable = "avx512bw,avx512vl")]
3542#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3543#[cfg_attr(test, assert_instr(vpcmp))]
3544pub unsafe fn _mm_cmpeq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3545 simd_bitmask::<u16x8, _>(simd_eq(x:a.as_u16x8(), y:b.as_u16x8()))
3546}
3547
3548/// Compare packed unsigned 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3549///
3550/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu16_mask&expand=798)
3551#[inline]
3552#[target_feature(enable = "avx512bw,avx512vl")]
3553#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3554#[cfg_attr(test, assert_instr(vpcmp))]
3555pub unsafe fn _mm_mask_cmpeq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3556 _mm_cmpeq_epu16_mask(a, b) & k1
3557}
3558
3559/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k.
3560///
3561/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epu8_mask&expand=819)
3562#[inline]
3563#[target_feature(enable = "avx512bw")]
3564#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3565#[cfg_attr(test, assert_instr(vpcmp))]
3566pub unsafe fn _mm512_cmpeq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3567 simd_bitmask::<u8x64, _>(simd_eq(x:a.as_u8x64(), y:b.as_u8x64()))
3568}
3569
3570/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3571///
3572/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epu8_mask&expand=820)
3573#[inline]
3574#[target_feature(enable = "avx512bw")]
3575#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3576#[cfg_attr(test, assert_instr(vpcmp))]
3577pub unsafe fn _mm512_mask_cmpeq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3578 _mm512_cmpeq_epu8_mask(a, b) & k1
3579}
3580
3581/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k.
3582///
3583/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epu8_mask&expand=817)
3584#[inline]
3585#[target_feature(enable = "avx512bw,avx512vl")]
3586#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3587#[cfg_attr(test, assert_instr(vpcmp))]
3588pub unsafe fn _mm256_cmpeq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3589 simd_bitmask::<u8x32, _>(simd_eq(x:a.as_u8x32(), y:b.as_u8x32()))
3590}
3591
3592/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3593///
3594/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epu8_mask&expand=818)
3595#[inline]
3596#[target_feature(enable = "avx512bw,avx512vl")]
3597#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3598#[cfg_attr(test, assert_instr(vpcmp))]
3599pub unsafe fn _mm256_mask_cmpeq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3600 _mm256_cmpeq_epu8_mask(a, b) & k1
3601}
3602
3603/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k.
3604///
3605/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epu8_mask&expand=815)
3606#[inline]
3607#[target_feature(enable = "avx512bw,avx512vl")]
3608#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3609#[cfg_attr(test, assert_instr(vpcmp))]
3610pub unsafe fn _mm_cmpeq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3611 simd_bitmask::<u8x16, _>(simd_eq(x:a.as_u8x16(), y:b.as_u8x16()))
3612}
3613
3614/// Compare packed unsigned 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3615///
3616/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epu8_mask&expand=816)
3617#[inline]
3618#[target_feature(enable = "avx512bw,avx512vl")]
3619#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3620#[cfg_attr(test, assert_instr(vpcmp))]
3621pub unsafe fn _mm_mask_cmpeq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3622 _mm_cmpeq_epu8_mask(a, b) & k1
3623}
3624
3625/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k.
3626///
3627/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi16_mask&expand=771)
3628#[inline]
3629#[target_feature(enable = "avx512bw")]
3630#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3631#[cfg_attr(test, assert_instr(vpcmp))]
3632pub unsafe fn _mm512_cmpeq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3633 simd_bitmask::<i16x32, _>(simd_eq(x:a.as_i16x32(), y:b.as_i16x32()))
3634}
3635
3636/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3637///
3638/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi16_mask&expand=772)
3639#[inline]
3640#[target_feature(enable = "avx512bw")]
3641#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3642#[cfg_attr(test, assert_instr(vpcmp))]
3643pub unsafe fn _mm512_mask_cmpeq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3644 _mm512_cmpeq_epi16_mask(a, b) & k1
3645}
3646
3647/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k.
3648///
3649/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi16_mask&expand=769)
3650#[inline]
3651#[target_feature(enable = "avx512bw,avx512vl")]
3652#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3653#[cfg_attr(test, assert_instr(vpcmp))]
3654pub unsafe fn _mm256_cmpeq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3655 simd_bitmask::<i16x16, _>(simd_eq(x:a.as_i16x16(), y:b.as_i16x16()))
3656}
3657
3658/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3659///
3660/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi16_mask&expand=770)
3661#[inline]
3662#[target_feature(enable = "avx512bw,avx512vl")]
3663#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3664#[cfg_attr(test, assert_instr(vpcmp))]
3665pub unsafe fn _mm256_mask_cmpeq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3666 _mm256_cmpeq_epi16_mask(a, b) & k1
3667}
3668
3669/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k.
3670///
3671/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi16_mask&expand=767)
3672#[inline]
3673#[target_feature(enable = "avx512bw,avx512vl")]
3674#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3675#[cfg_attr(test, assert_instr(vpcmp))]
3676pub unsafe fn _mm_cmpeq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3677 simd_bitmask::<i16x8, _>(simd_eq(x:a.as_i16x8(), y:b.as_i16x8()))
3678}
3679
3680/// Compare packed signed 16-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3681///
3682/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi16_mask&expand=768)
3683#[inline]
3684#[target_feature(enable = "avx512bw,avx512vl")]
3685#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3686#[cfg_attr(test, assert_instr(vpcmp))]
3687pub unsafe fn _mm_mask_cmpeq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3688 _mm_cmpeq_epi16_mask(a, b) & k1
3689}
3690
3691/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k.
3692///
3693/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpeq_epi8_mask&expand=795)
3694#[inline]
3695#[target_feature(enable = "avx512bw")]
3696#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3697#[cfg_attr(test, assert_instr(vpcmp))]
3698pub unsafe fn _mm512_cmpeq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3699 simd_bitmask::<i8x64, _>(simd_eq(x:a.as_i8x64(), y:b.as_i8x64()))
3700}
3701
3702/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3703///
3704/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpeq_epi8_mask&expand=796)
3705#[inline]
3706#[target_feature(enable = "avx512bw")]
3707#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3708#[cfg_attr(test, assert_instr(vpcmp))]
3709pub unsafe fn _mm512_mask_cmpeq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3710 _mm512_cmpeq_epi8_mask(a, b) & k1
3711}
3712
3713/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k.
3714///
3715/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpeq_epi8_mask&expand=793)
3716#[inline]
3717#[target_feature(enable = "avx512bw,avx512vl")]
3718#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3719#[cfg_attr(test, assert_instr(vpcmp))]
3720pub unsafe fn _mm256_cmpeq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3721 simd_bitmask::<i8x32, _>(simd_eq(x:a.as_i8x32(), y:b.as_i8x32()))
3722}
3723
3724/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3725///
3726/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpeq_epi8_mask&expand=794)
3727#[inline]
3728#[target_feature(enable = "avx512bw,avx512vl")]
3729#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3730#[cfg_attr(test, assert_instr(vpcmp))]
3731pub unsafe fn _mm256_mask_cmpeq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3732 _mm256_cmpeq_epi8_mask(a, b) & k1
3733}
3734
3735/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k.
3736///
3737/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi8_mask&expand=791)
3738#[inline]
3739#[target_feature(enable = "avx512bw,avx512vl")]
3740#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3741#[cfg_attr(test, assert_instr(vpcmp))]
3742pub unsafe fn _mm_cmpeq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3743 simd_bitmask::<i8x16, _>(simd_eq(x:a.as_i8x16(), y:b.as_i8x16()))
3744}
3745
3746/// Compare packed signed 8-bit integers in a and b for equality, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3747///
3748/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpeq_epi8_mask&expand=792)
3749#[inline]
3750#[target_feature(enable = "avx512bw,avx512vl")]
3751#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3752#[cfg_attr(test, assert_instr(vpcmp))]
3753pub unsafe fn _mm_mask_cmpeq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3754 _mm_cmpeq_epi8_mask(a, b) & k1
3755}
3756
3757/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3758///
3759/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu16_mask&expand=1106)
3760#[inline]
3761#[target_feature(enable = "avx512bw")]
3762#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3763#[cfg_attr(test, assert_instr(vpcmp))]
3764pub unsafe fn _mm512_cmpneq_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3765 simd_bitmask::<u16x32, _>(simd_ne(x:a.as_u16x32(), y:b.as_u16x32()))
3766}
3767
3768/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3769///
3770/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu16_mask&expand=1107)
3771#[inline]
3772#[target_feature(enable = "avx512bw")]
3773#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3774#[cfg_attr(test, assert_instr(vpcmp))]
3775pub unsafe fn _mm512_mask_cmpneq_epu16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3776 _mm512_cmpneq_epu16_mask(a, b) & k1
3777}
3778
3779/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3780///
3781/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu16_mask&expand=1104)
3782#[inline]
3783#[target_feature(enable = "avx512bw,avx512vl")]
3784#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3785#[cfg_attr(test, assert_instr(vpcmp))]
3786pub unsafe fn _mm256_cmpneq_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3787 simd_bitmask::<u16x16, _>(simd_ne(x:a.as_u16x16(), y:b.as_u16x16()))
3788}
3789
3790/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3791///
3792/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu16_mask&expand=1105)
3793#[inline]
3794#[target_feature(enable = "avx512bw,avx512vl")]
3795#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3796#[cfg_attr(test, assert_instr(vpcmp))]
3797pub unsafe fn _mm256_mask_cmpneq_epu16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3798 _mm256_cmpneq_epu16_mask(a, b) & k1
3799}
3800
3801/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3802///
3803/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu16_mask&expand=1102)
3804#[inline]
3805#[target_feature(enable = "avx512bw,avx512vl")]
3806#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3807#[cfg_attr(test, assert_instr(vpcmp))]
3808pub unsafe fn _mm_cmpneq_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3809 simd_bitmask::<u16x8, _>(simd_ne(x:a.as_u16x8(), y:b.as_u16x8()))
3810}
3811
3812/// Compare packed unsigned 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3813///
3814/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu16_mask&expand=1103)
3815#[inline]
3816#[target_feature(enable = "avx512bw,avx512vl")]
3817#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3818#[cfg_attr(test, assert_instr(vpcmp))]
3819pub unsafe fn _mm_mask_cmpneq_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3820 _mm_cmpneq_epu16_mask(a, b) & k1
3821}
3822
3823/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k.
3824///
3825/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epu8_mask&expand=1124)
3826#[inline]
3827#[target_feature(enable = "avx512bw")]
3828#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3829#[cfg_attr(test, assert_instr(vpcmp))]
3830pub unsafe fn _mm512_cmpneq_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3831 simd_bitmask::<u8x64, _>(simd_ne(x:a.as_u8x64(), y:b.as_u8x64()))
3832}
3833
3834/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3835///
3836/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epu8_mask&expand=1125)
3837#[inline]
3838#[target_feature(enable = "avx512bw")]
3839#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3840#[cfg_attr(test, assert_instr(vpcmp))]
3841pub unsafe fn _mm512_mask_cmpneq_epu8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3842 _mm512_cmpneq_epu8_mask(a, b) & k1
3843}
3844
3845/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k.
3846///
3847/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epu8_mask&expand=1122)
3848#[inline]
3849#[target_feature(enable = "avx512bw,avx512vl")]
3850#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3851#[cfg_attr(test, assert_instr(vpcmp))]
3852pub unsafe fn _mm256_cmpneq_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3853 simd_bitmask::<u8x32, _>(simd_ne(x:a.as_u8x32(), y:b.as_u8x32()))
3854}
3855
3856/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3857///
3858/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epu8_mask&expand=1123)
3859#[inline]
3860#[target_feature(enable = "avx512bw,avx512vl")]
3861#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3862#[cfg_attr(test, assert_instr(vpcmp))]
3863pub unsafe fn _mm256_mask_cmpneq_epu8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3864 _mm256_cmpneq_epu8_mask(a, b) & k1
3865}
3866
3867/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k.
3868///
3869/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epu8_mask&expand=1120)
3870#[inline]
3871#[target_feature(enable = "avx512bw,avx512vl")]
3872#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3873#[cfg_attr(test, assert_instr(vpcmp))]
3874pub unsafe fn _mm_cmpneq_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 {
3875 simd_bitmask::<u8x16, _>(simd_ne(x:a.as_u8x16(), y:b.as_u8x16()))
3876}
3877
3878/// Compare packed unsigned 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3879///
3880/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epu8_mask&expand=1121)
3881#[inline]
3882#[target_feature(enable = "avx512bw,avx512vl")]
3883#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3884#[cfg_attr(test, assert_instr(vpcmp))]
3885pub unsafe fn _mm_mask_cmpneq_epu8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
3886 _mm_cmpneq_epu8_mask(a, b) & k1
3887}
3888
3889/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3890///
3891/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi16_mask&expand=1082)
3892#[inline]
3893#[target_feature(enable = "avx512bw")]
3894#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3895#[cfg_attr(test, assert_instr(vpcmp))]
3896pub unsafe fn _mm512_cmpneq_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
3897 simd_bitmask::<i16x32, _>(simd_ne(x:a.as_i16x32(), y:b.as_i16x32()))
3898}
3899
3900/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3901///
3902/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi16_mask&expand=1083)
3903#[inline]
3904#[target_feature(enable = "avx512bw")]
3905#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3906#[cfg_attr(test, assert_instr(vpcmp))]
3907pub unsafe fn _mm512_mask_cmpneq_epi16_mask(k1: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
3908 _mm512_cmpneq_epi16_mask(a, b) & k1
3909}
3910
3911/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3912///
3913/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi16_mask&expand=1080)
3914#[inline]
3915#[target_feature(enable = "avx512bw,avx512vl")]
3916#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3917#[cfg_attr(test, assert_instr(vpcmp))]
3918pub unsafe fn _mm256_cmpneq_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
3919 simd_bitmask::<i16x16, _>(simd_ne(x:a.as_i16x16(), y:b.as_i16x16()))
3920}
3921
3922/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3923///
3924/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi16_mask&expand=1081)
3925#[inline]
3926#[target_feature(enable = "avx512bw,avx512vl")]
3927#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3928#[cfg_attr(test, assert_instr(vpcmp))]
3929pub unsafe fn _mm256_mask_cmpneq_epi16_mask(k1: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
3930 _mm256_cmpneq_epi16_mask(a, b) & k1
3931}
3932
3933/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k.
3934///
3935/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi16_mask&expand=1078)
3936#[inline]
3937#[target_feature(enable = "avx512bw,avx512vl")]
3938#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3939#[cfg_attr(test, assert_instr(vpcmp))]
3940pub unsafe fn _mm_cmpneq_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
3941 simd_bitmask::<i16x8, _>(simd_ne(x:a.as_i16x8(), y:b.as_i16x8()))
3942}
3943
3944/// Compare packed signed 16-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3945///
3946/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi16_mask&expand=1079)
3947#[inline]
3948#[target_feature(enable = "avx512bw,avx512vl")]
3949#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3950#[cfg_attr(test, assert_instr(vpcmp))]
3951pub unsafe fn _mm_mask_cmpneq_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
3952 _mm_cmpneq_epi16_mask(a, b) & k1
3953}
3954
3955/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k.
3956///
3957/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmpneq_epi8_mask&expand=1100)
3958#[inline]
3959#[target_feature(enable = "avx512bw")]
3960#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3961#[cfg_attr(test, assert_instr(vpcmp))]
3962pub unsafe fn _mm512_cmpneq_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
3963 simd_bitmask::<i8x64, _>(simd_ne(x:a.as_i8x64(), y:b.as_i8x64()))
3964}
3965
3966/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3967///
3968/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmpneq_epi8_mask&expand=1101)
3969#[inline]
3970#[target_feature(enable = "avx512bw")]
3971#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3972#[cfg_attr(test, assert_instr(vpcmp))]
3973pub unsafe fn _mm512_mask_cmpneq_epi8_mask(k1: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
3974 _mm512_cmpneq_epi8_mask(a, b) & k1
3975}
3976
3977/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k.
3978///
3979/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmpneq_epi8_mask&expand=1098)
3980#[inline]
3981#[target_feature(enable = "avx512bw,avx512vl")]
3982#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3983#[cfg_attr(test, assert_instr(vpcmp))]
3984pub unsafe fn _mm256_cmpneq_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
3985 simd_bitmask::<i8x32, _>(simd_ne(x:a.as_i8x32(), y:b.as_i8x32()))
3986}
3987
3988/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
3989///
3990/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmpneq_epi8_mask&expand=1099)
3991#[inline]
3992#[target_feature(enable = "avx512bw,avx512vl")]
3993#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
3994#[cfg_attr(test, assert_instr(vpcmp))]
3995pub unsafe fn _mm256_mask_cmpneq_epi8_mask(k1: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
3996 _mm256_cmpneq_epi8_mask(a, b) & k1
3997}
3998
3999/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k.
4000///
4001/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_epi8_mask&expand=1096)
4002#[inline]
4003#[target_feature(enable = "avx512bw,avx512vl")]
4004#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4005#[cfg_attr(test, assert_instr(vpcmp))]
4006pub unsafe fn _mm_cmpneq_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
4007 simd_bitmask::<i8x16, _>(simd_ne(x:a.as_i8x16(), y:b.as_i8x16()))
4008}
4009
4010/// Compare packed signed 8-bit integers in a and b for not-equal, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4011///
4012/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmpneq_epi8_mask&expand=1097)
4013#[inline]
4014#[target_feature(enable = "avx512bw,avx512vl")]
4015#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4016#[cfg_attr(test, assert_instr(vpcmp))]
4017pub unsafe fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
4018 _mm_cmpneq_epi8_mask(a, b) & k1
4019}
4020
4021/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by `IMM8`, and store the results in mask vector k.
4022///
4023/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu16_mask&expand=715)
4024#[inline]
4025#[target_feature(enable = "avx512bw")]
4026#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4027#[rustc_legacy_const_generics(2)]
4028#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4029pub unsafe fn _mm512_cmp_epu16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
4030 static_assert_uimm_bits!(IMM8, 3);
4031 let a: u16x32 = a.as_u16x32();
4032 let b: u16x32 = b.as_u16x32();
4033 vpcmpuw(a, b, IMM8, mask:0b11111111_11111111_11111111_11111111)
4034}
4035
4036/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4037///
4038/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu16_mask&expand=716)
4039#[inline]
4040#[target_feature(enable = "avx512bw")]
4041#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4042#[rustc_legacy_const_generics(3)]
4043#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4044pub unsafe fn _mm512_mask_cmp_epu16_mask<const IMM8: i32>(
4045 k1: __mmask32,
4046 a: __m512i,
4047 b: __m512i,
4048) -> __mmask32 {
4049 static_assert_uimm_bits!(IMM8, 3);
4050 let a: u16x32 = a.as_u16x32();
4051 let b: u16x32 = b.as_u16x32();
4052 vpcmpuw(a, b, IMM8, mask:k1)
4053}
4054
4055/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4056///
4057/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu16_mask&expand=713)
4058#[inline]
4059#[target_feature(enable = "avx512bw,avx512vl")]
4060#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4061#[rustc_legacy_const_generics(2)]
4062#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4063pub unsafe fn _mm256_cmp_epu16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
4064 static_assert_uimm_bits!(IMM8, 3);
4065 let a: u16x16 = a.as_u16x16();
4066 let b: u16x16 = b.as_u16x16();
4067 vpcmpuw256(a, b, IMM8, mask:0b11111111_11111111)
4068}
4069
4070/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4071///
4072/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu16_mask&expand=714)
4073#[inline]
4074#[target_feature(enable = "avx512bw,avx512vl")]
4075#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4076#[rustc_legacy_const_generics(3)]
4077#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4078pub unsafe fn _mm256_mask_cmp_epu16_mask<const IMM8: i32>(
4079 k1: __mmask16,
4080 a: __m256i,
4081 b: __m256i,
4082) -> __mmask16 {
4083 static_assert_uimm_bits!(IMM8, 3);
4084 let a: u16x16 = a.as_u16x16();
4085 let b: u16x16 = b.as_u16x16();
4086 vpcmpuw256(a, b, IMM8, mask:k1)
4087}
4088
4089/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4090///
4091/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu16_mask&expand=711)
4092#[inline]
4093#[target_feature(enable = "avx512bw,avx512vl")]
4094#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4095#[rustc_legacy_const_generics(2)]
4096#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4097pub unsafe fn _mm_cmp_epu16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
4098 static_assert_uimm_bits!(IMM8, 3);
4099 let a: u16x8 = a.as_u16x8();
4100 let b: u16x8 = b.as_u16x8();
4101 vpcmpuw128(a, b, IMM8, mask:0b11111111)
4102}
4103
4104/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4105///
4106/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu16_mask&expand=712)
4107#[inline]
4108#[target_feature(enable = "avx512bw,avx512vl")]
4109#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4110#[rustc_legacy_const_generics(3)]
4111#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4112pub unsafe fn _mm_mask_cmp_epu16_mask<const IMM8: i32>(
4113 k1: __mmask8,
4114 a: __m128i,
4115 b: __m128i,
4116) -> __mmask8 {
4117 static_assert_uimm_bits!(IMM8, 3);
4118 let a: u16x8 = a.as_u16x8();
4119 let b: u16x8 = b.as_u16x8();
4120 vpcmpuw128(a, b, IMM8, mask:k1)
4121}
4122
4123/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4124///
4125/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epu8_mask&expand=733)
4126#[inline]
4127#[target_feature(enable = "avx512bw")]
4128#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4129#[rustc_legacy_const_generics(2)]
4130#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4131pub unsafe fn _mm512_cmp_epu8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
4132 static_assert_uimm_bits!(IMM8, 3);
4133 let a: u8x64 = a.as_u8x64();
4134 let b: u8x64 = b.as_u8x64();
4135 vpcmpub(
4136 a,
4137 b,
4138 IMM8,
4139 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
4140 )
4141}
4142
4143/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4144///
4145/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epu8_mask&expand=734)
4146#[inline]
4147#[target_feature(enable = "avx512bw")]
4148#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4149#[rustc_legacy_const_generics(3)]
4150#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4151pub unsafe fn _mm512_mask_cmp_epu8_mask<const IMM8: i32>(
4152 k1: __mmask64,
4153 a: __m512i,
4154 b: __m512i,
4155) -> __mmask64 {
4156 static_assert_uimm_bits!(IMM8, 3);
4157 let a: u8x64 = a.as_u8x64();
4158 let b: u8x64 = b.as_u8x64();
4159 vpcmpub(a, b, IMM8, mask:k1)
4160}
4161
4162/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4163///
4164/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epu8_mask&expand=731)
4165#[inline]
4166#[target_feature(enable = "avx512bw,avx512vl")]
4167#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4168#[rustc_legacy_const_generics(2)]
4169#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4170pub unsafe fn _mm256_cmp_epu8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
4171 static_assert_uimm_bits!(IMM8, 3);
4172 let a: u8x32 = a.as_u8x32();
4173 let b: u8x32 = b.as_u8x32();
4174 vpcmpub256(a, b, IMM8, mask:0b11111111_11111111_11111111_11111111)
4175}
4176
4177/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4178///
4179/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epu8_mask&expand=732)
4180#[inline]
4181#[target_feature(enable = "avx512bw,avx512vl")]
4182#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4183#[rustc_legacy_const_generics(3)]
4184#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4185pub unsafe fn _mm256_mask_cmp_epu8_mask<const IMM8: i32>(
4186 k1: __mmask32,
4187 a: __m256i,
4188 b: __m256i,
4189) -> __mmask32 {
4190 static_assert_uimm_bits!(IMM8, 3);
4191 let a: u8x32 = a.as_u8x32();
4192 let b: u8x32 = b.as_u8x32();
4193 vpcmpub256(a, b, IMM8, mask:k1)
4194}
4195
4196/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4197///
4198/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epu8_mask&expand=729)
4199#[inline]
4200#[target_feature(enable = "avx512bw,avx512vl")]
4201#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4202#[rustc_legacy_const_generics(2)]
4203#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4204pub unsafe fn _mm_cmp_epu8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
4205 static_assert_uimm_bits!(IMM8, 3);
4206 let a: u8x16 = a.as_u8x16();
4207 let b: u8x16 = b.as_u8x16();
4208 vpcmpub128(a, b, IMM8, mask:0b11111111_11111111)
4209}
4210
4211/// Compare packed unsigned 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4212///
4213/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epu8_mask&expand=730)
4214#[inline]
4215#[target_feature(enable = "avx512bw,avx512vl")]
4216#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4217#[rustc_legacy_const_generics(3)]
4218#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4219pub unsafe fn _mm_mask_cmp_epu8_mask<const IMM8: i32>(
4220 k1: __mmask16,
4221 a: __m128i,
4222 b: __m128i,
4223) -> __mmask16 {
4224 static_assert_uimm_bits!(IMM8, 3);
4225 let a: u8x16 = a.as_u8x16();
4226 let b: u8x16 = b.as_u8x16();
4227 vpcmpub128(a, b, IMM8, mask:k1)
4228}
4229
4230/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4231///
4232/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi16_mask&expand=691)
4233#[inline]
4234#[target_feature(enable = "avx512bw")]
4235#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4236#[rustc_legacy_const_generics(2)]
4237#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4238pub unsafe fn _mm512_cmp_epi16_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask32 {
4239 static_assert_uimm_bits!(IMM8, 3);
4240 let a: i16x32 = a.as_i16x32();
4241 let b: i16x32 = b.as_i16x32();
4242 vpcmpw(a, b, IMM8, mask:0b11111111_11111111_11111111_11111111)
4243}
4244
4245/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4246///
4247/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi16_mask&expand=692)
4248#[inline]
4249#[target_feature(enable = "avx512bw")]
4250#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4251#[rustc_legacy_const_generics(3)]
4252#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4253pub unsafe fn _mm512_mask_cmp_epi16_mask<const IMM8: i32>(
4254 k1: __mmask32,
4255 a: __m512i,
4256 b: __m512i,
4257) -> __mmask32 {
4258 static_assert_uimm_bits!(IMM8, 3);
4259 let a: i16x32 = a.as_i16x32();
4260 let b: i16x32 = b.as_i16x32();
4261 vpcmpw(a, b, IMM8, mask:k1)
4262}
4263
4264/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4265///
4266/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epi16_mask&expand=689)
4267#[inline]
4268#[target_feature(enable = "avx512bw,avx512vl")]
4269#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4270#[rustc_legacy_const_generics(2)]
4271#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4272pub unsafe fn _mm256_cmp_epi16_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask16 {
4273 static_assert_uimm_bits!(IMM8, 3);
4274 let a: i16x16 = a.as_i16x16();
4275 let b: i16x16 = b.as_i16x16();
4276 vpcmpw256(a, b, IMM8, mask:0b11111111_11111111)
4277}
4278
4279/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4280///
4281/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi16_mask&expand=690)
4282#[inline]
4283#[target_feature(enable = "avx512bw,avx512vl")]
4284#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4285#[rustc_legacy_const_generics(3)]
4286#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4287pub unsafe fn _mm256_mask_cmp_epi16_mask<const IMM8: i32>(
4288 k1: __mmask16,
4289 a: __m256i,
4290 b: __m256i,
4291) -> __mmask16 {
4292 static_assert_uimm_bits!(IMM8, 3);
4293 let a: i16x16 = a.as_i16x16();
4294 let b: i16x16 = b.as_i16x16();
4295 vpcmpw256(a, b, IMM8, mask:k1)
4296}
4297
4298/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4299///
4300/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi16_mask&expand=687)
4301#[inline]
4302#[target_feature(enable = "avx512bw,avx512vl")]
4303#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4304#[rustc_legacy_const_generics(2)]
4305#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4306pub unsafe fn _mm_cmp_epi16_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask8 {
4307 static_assert_uimm_bits!(IMM8, 3);
4308 let a: i16x8 = a.as_i16x8();
4309 let b: i16x8 = b.as_i16x8();
4310 vpcmpw128(a, b, IMM8, mask:0b11111111)
4311}
4312
4313/// Compare packed signed 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4314///
4315/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi16_mask&expand=688)
4316#[inline]
4317#[target_feature(enable = "avx512bw,avx512vl")]
4318#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4319#[rustc_legacy_const_generics(3)]
4320#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4321pub unsafe fn _mm_mask_cmp_epi16_mask<const IMM8: i32>(
4322 k1: __mmask8,
4323 a: __m128i,
4324 b: __m128i,
4325) -> __mmask8 {
4326 static_assert_uimm_bits!(IMM8, 3);
4327 let a: i16x8 = a.as_i16x8();
4328 let b: i16x8 = b.as_i16x8();
4329 vpcmpw128(a, b, IMM8, mask:k1)
4330}
4331
4332/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4333///
4334/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cmp_epi8_mask&expand=709)
4335#[inline]
4336#[target_feature(enable = "avx512bw")]
4337#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4338#[rustc_legacy_const_generics(2)]
4339#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4340pub unsafe fn _mm512_cmp_epi8_mask<const IMM8: i32>(a: __m512i, b: __m512i) -> __mmask64 {
4341 static_assert_uimm_bits!(IMM8, 3);
4342 let a: i8x64 = a.as_i8x64();
4343 let b: i8x64 = b.as_i8x64();
4344 vpcmpb(
4345 a,
4346 b,
4347 IMM8,
4348 mask:0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
4349 )
4350}
4351
4352/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4353///
4354/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cmp_epi8_mask&expand=710)
4355#[inline]
4356#[target_feature(enable = "avx512bw")]
4357#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4358#[rustc_legacy_const_generics(3)]
4359#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4360pub unsafe fn _mm512_mask_cmp_epi8_mask<const IMM8: i32>(
4361 k1: __mmask64,
4362 a: __m512i,
4363 b: __m512i,
4364) -> __mmask64 {
4365 static_assert_uimm_bits!(IMM8, 3);
4366 let a: i8x64 = a.as_i8x64();
4367 let b: i8x64 = b.as_i8x64();
4368 vpcmpb(a, b, IMM8, mask:k1)
4369}
4370
4371/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4372///
4373/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cmp_epi8_mask&expand=707)
4374#[inline]
4375#[target_feature(enable = "avx512bw,avx512vl")]
4376#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4377#[rustc_legacy_const_generics(2)]
4378#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4379pub unsafe fn _mm256_cmp_epi8_mask<const IMM8: i32>(a: __m256i, b: __m256i) -> __mmask32 {
4380 static_assert_uimm_bits!(IMM8, 3);
4381 let a: i8x32 = a.as_i8x32();
4382 let b: i8x32 = b.as_i8x32();
4383 vpcmpb256(a, b, IMM8, mask:0b11111111_11111111_11111111_11111111)
4384}
4385
4386/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4387///
4388/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cmp_epi8_mask&expand=708)
4389#[inline]
4390#[target_feature(enable = "avx512bw,avx512vl")]
4391#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4392#[rustc_legacy_const_generics(3)]
4393#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4394pub unsafe fn _mm256_mask_cmp_epi8_mask<const IMM8: i32>(
4395 k1: __mmask32,
4396 a: __m256i,
4397 b: __m256i,
4398) -> __mmask32 {
4399 static_assert_uimm_bits!(IMM8, 3);
4400 let a: i8x32 = a.as_i8x32();
4401 let b: i8x32 = b.as_i8x32();
4402 vpcmpb256(a, b, IMM8, mask:k1)
4403}
4404
4405/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k.
4406///
4407/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmp_epi8_mask&expand=705)
4408#[inline]
4409#[target_feature(enable = "avx512bw,avx512vl")]
4410#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4411#[rustc_legacy_const_generics(2)]
4412#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4413pub unsafe fn _mm_cmp_epi8_mask<const IMM8: i32>(a: __m128i, b: __m128i) -> __mmask16 {
4414 static_assert_uimm_bits!(IMM8, 3);
4415 let a: i8x16 = a.as_i8x16();
4416 let b: i8x16 = b.as_i8x16();
4417 vpcmpb128(a, b, IMM8, mask:0b11111111_11111111)
4418}
4419
4420/// Compare packed signed 8-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k using zeromask k1 (elements are zeroed out when the corresponding mask bit is not set).
4421///
4422/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cmp_epi8_mask&expand=706)
4423#[inline]
4424#[target_feature(enable = "avx512bw,avx512vl")]
4425#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4426#[rustc_legacy_const_generics(3)]
4427#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))]
4428pub unsafe fn _mm_mask_cmp_epi8_mask<const IMM8: i32>(
4429 k1: __mmask16,
4430 a: __m128i,
4431 b: __m128i,
4432) -> __mmask16 {
4433 static_assert_uimm_bits!(IMM8, 3);
4434 let a: i8x16 = a.as_i8x16();
4435 let b: i8x16 = b.as_i8x16();
4436 vpcmpb128(a, b, IMM8, mask:k1)
4437}
4438
4439/// Load 512-bits (composed of 32 packed 16-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4440///
4441/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi16&expand=3368)
4442#[inline]
4443#[target_feature(enable = "avx512bw")]
4444#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4445#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4446pub unsafe fn _mm512_loadu_epi16(mem_addr: *const i16) -> __m512i {
4447 ptr::read_unaligned(src:mem_addr as *const __m512i)
4448}
4449
4450/// Load 256-bits (composed of 16 packed 16-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4451///
4452/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi16&expand=3365)
4453#[inline]
4454#[target_feature(enable = "avx512bw,avx512vl")]
4455#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4456#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4457pub unsafe fn _mm256_loadu_epi16(mem_addr: *const i16) -> __m256i {
4458 ptr::read_unaligned(src:mem_addr as *const __m256i)
4459}
4460
4461/// Load 128-bits (composed of 8 packed 16-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4462///
4463/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi16&expand=3362)
4464#[inline]
4465#[target_feature(enable = "avx512bw,avx512vl")]
4466#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4467#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4468pub unsafe fn _mm_loadu_epi16(mem_addr: *const i16) -> __m128i {
4469 ptr::read_unaligned(src:mem_addr as *const __m128i)
4470}
4471
4472/// Load 512-bits (composed of 64 packed 8-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4473///
4474/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_loadu_epi8&expand=3395)
4475#[inline]
4476#[target_feature(enable = "avx512bw")]
4477#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4478#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4479pub unsafe fn _mm512_loadu_epi8(mem_addr: *const i8) -> __m512i {
4480 ptr::read_unaligned(src:mem_addr as *const __m512i)
4481}
4482
4483/// Load 256-bits (composed of 32 packed 8-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4484///
4485/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_loadu_epi8&expand=3392)
4486#[inline]
4487#[target_feature(enable = "avx512bw,avx512vl")]
4488#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4489#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4490pub unsafe fn _mm256_loadu_epi8(mem_addr: *const i8) -> __m256i {
4491 ptr::read_unaligned(src:mem_addr as *const __m256i)
4492}
4493
4494/// Load 128-bits (composed of 16 packed 8-bit integers) from memory into dst. mem_addr does not need to be aligned on any particular boundary.
4495///
4496/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_epi8&expand=3389)
4497#[inline]
4498#[target_feature(enable = "avx512bw,avx512vl")]
4499#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4500#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4501pub unsafe fn _mm_loadu_epi8(mem_addr: *const i8) -> __m128i {
4502 ptr::read_unaligned(src:mem_addr as *const __m128i)
4503}
4504
4505/// Store 512-bits (composed of 32 packed 16-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4506///
4507/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi16&expand=5622)
4508#[inline]
4509#[target_feature(enable = "avx512bw")]
4510#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4511#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4512pub unsafe fn _mm512_storeu_epi16(mem_addr: *mut i16, a: __m512i) {
4513 ptr::write_unaligned(dst:mem_addr as *mut __m512i, src:a);
4514}
4515
4516/// Store 256-bits (composed of 16 packed 16-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4517///
4518/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi16&expand=5620)
4519#[inline]
4520#[target_feature(enable = "avx512bw,avx512vl")]
4521#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4522#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4523pub unsafe fn _mm256_storeu_epi16(mem_addr: *mut i16, a: __m256i) {
4524 ptr::write_unaligned(dst:mem_addr as *mut __m256i, src:a);
4525}
4526
4527/// Store 128-bits (composed of 8 packed 16-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4528///
4529/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi16&expand=5618)
4530#[inline]
4531#[target_feature(enable = "avx512bw,avx512vl")]
4532#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4533#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu16
4534pub unsafe fn _mm_storeu_epi16(mem_addr: *mut i16, a: __m128i) {
4535 ptr::write_unaligned(dst:mem_addr as *mut __m128i, src:a);
4536}
4537
4538/// Store 512-bits (composed of 64 packed 8-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4539///
4540/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_storeu_epi8&expand=5640)
4541#[inline]
4542#[target_feature(enable = "avx512bw")]
4543#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4544#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4545pub unsafe fn _mm512_storeu_epi8(mem_addr: *mut i8, a: __m512i) {
4546 ptr::write_unaligned(dst:mem_addr as *mut __m512i, src:a);
4547}
4548
4549/// Store 256-bits (composed of 32 packed 8-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4550///
4551/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_storeu_epi8&expand=5638)
4552#[inline]
4553#[target_feature(enable = "avx512bw,avx512vl")]
4554#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4555#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4556pub unsafe fn _mm256_storeu_epi8(mem_addr: *mut i8, a: __m256i) {
4557 ptr::write_unaligned(dst:mem_addr as *mut __m256i, src:a);
4558}
4559
4560/// Store 128-bits (composed of 16 packed 8-bit integers) from a into memory. mem_addr does not need to be aligned on any particular boundary.
4561///
4562/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_epi8&expand=5636)
4563#[inline]
4564#[target_feature(enable = "avx512bw,avx512vl")]
4565#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4566#[cfg_attr(test, assert_instr(vmovups))] //should be vmovdqu8
4567pub unsafe fn _mm_storeu_epi8(mem_addr: *mut i8, a: __m128i) {
4568 ptr::write_unaligned(dst:mem_addr as *mut __m128i, src:a);
4569}
4570
4571/// Load packed 16-bit integers from memory into dst using writemask k
4572/// (elements are copied from src when the corresponding mask bit is not set).
4573/// mem_addr does not need to be aligned on any particular boundary.
4574///
4575/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_loadu_epi16)
4576#[inline]
4577#[target_feature(enable = "avx512f,avx512bw")]
4578#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4579pub unsafe fn _mm512_mask_loadu_epi16(src: __m512i, k: __mmask32, mem_addr: *const i16) -> __m512i {
4580 let mut dst: __m512i = src;
4581 asm!(
4582 vpl!("vmovdqu16 {dst}{{{k}}}"),
4583 p = in(reg) mem_addr,
4584 k = in(kreg) k,
4585 dst = inout(zmm_reg) dst,
4586 options(pure, readonly, nostack)
4587 );
4588 dst
4589}
4590
4591/// Load packed 16-bit integers from memory into dst using zeromask k
4592/// (elements are zeroed out when the corresponding mask bit is not set).
4593/// mem_addr does not need to be aligned on any particular boundary.
4594///
4595/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_loadu_epi16)
4596#[inline]
4597#[target_feature(enable = "avx512f,avx512bw")]
4598#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4599pub unsafe fn _mm512_maskz_loadu_epi16(k: __mmask32, mem_addr: *const i16) -> __m512i {
4600 let mut dst: __m512i;
4601 asm!(
4602 vpl!("vmovdqu16 {dst}{{{k}}} {{z}}"),
4603 p = in(reg) mem_addr,
4604 k = in(kreg) k,
4605 dst = out(zmm_reg) dst,
4606 options(pure, readonly, nostack)
4607 );
4608 dst
4609}
4610
4611/// Load packed 8-bit integers from memory into dst using writemask k
4612/// (elements are copied from src when the corresponding mask bit is not set).
4613/// mem_addr does not need to be aligned on any particular boundary.
4614///
4615/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_loadu_epi8)
4616#[inline]
4617#[target_feature(enable = "avx512f,avx512bw")]
4618#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4619pub unsafe fn _mm512_mask_loadu_epi8(src: __m512i, k: __mmask64, mem_addr: *const i8) -> __m512i {
4620 let mut dst: __m512i = src;
4621 asm!(
4622 vpl!("vmovdqu8 {dst}{{{k}}}"),
4623 p = in(reg) mem_addr,
4624 k = in(kreg) k,
4625 dst = inout(zmm_reg) dst,
4626 options(pure, readonly, nostack)
4627 );
4628 dst
4629}
4630
4631/// Load packed 8-bit integers from memory into dst using zeromask k
4632/// (elements are zeroed out when the corresponding mask bit is not set).
4633/// mem_addr does not need to be aligned on any particular boundary.
4634///
4635/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_loadu_epi8)
4636#[inline]
4637#[target_feature(enable = "avx512f,avx512bw")]
4638#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4639pub unsafe fn _mm512_maskz_loadu_epi8(k: __mmask64, mem_addr: *const i8) -> __m512i {
4640 let mut dst: __m512i;
4641 asm!(
4642 vpl!("vmovdqu8 {dst}{{{k}}} {{z}}"),
4643 p = in(reg) mem_addr,
4644 k = in(kreg) k,
4645 dst = out(zmm_reg) dst,
4646 options(pure, readonly, nostack)
4647 );
4648 dst
4649}
4650
4651/// Load packed 16-bit integers from memory into dst using writemask k
4652/// (elements are copied from src when the corresponding mask bit is not set).
4653/// mem_addr does not need to be aligned on any particular boundary.
4654///
4655/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_loadu_epi16)
4656#[inline]
4657#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4658#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4659pub unsafe fn _mm256_mask_loadu_epi16(src: __m256i, k: __mmask16, mem_addr: *const i16) -> __m256i {
4660 let mut dst: __m256i = src;
4661 asm!(
4662 vpl!("vmovdqu16 {dst}{{{k}}}"),
4663 p = in(reg) mem_addr,
4664 k = in(kreg) k,
4665 dst = inout(ymm_reg) dst,
4666 options(pure, readonly, nostack)
4667 );
4668 dst
4669}
4670
4671/// Load packed 16-bit integers from memory into dst using zeromask k
4672/// (elements are zeroed out when the corresponding mask bit is not set).
4673/// mem_addr does not need to be aligned on any particular boundary.
4674///
4675/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_loadu_epi16)
4676#[inline]
4677#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4678#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4679pub unsafe fn _mm256_maskz_loadu_epi16(k: __mmask16, mem_addr: *const i16) -> __m256i {
4680 let mut dst: __m256i;
4681 asm!(
4682 vpl!("vmovdqu16 {dst}{{{k}}} {{z}}"),
4683 p = in(reg) mem_addr,
4684 k = in(kreg) k,
4685 dst = out(ymm_reg) dst,
4686 options(pure, readonly, nostack)
4687 );
4688 dst
4689}
4690
4691/// Load packed 8-bit integers from memory into dst using writemask k
4692/// (elements are copied from src when the corresponding mask bit is not set).
4693/// mem_addr does not need to be aligned on any particular boundary.
4694///
4695/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_loadu_epi8)
4696#[inline]
4697#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4698#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4699pub unsafe fn _mm256_mask_loadu_epi8(src: __m256i, k: __mmask32, mem_addr: *const i8) -> __m256i {
4700 let mut dst: __m256i = src;
4701 asm!(
4702 vpl!("vmovdqu8 {dst}{{{k}}}"),
4703 p = in(reg) mem_addr,
4704 k = in(kreg) k,
4705 dst = inout(ymm_reg) dst,
4706 options(pure, readonly, nostack)
4707 );
4708 dst
4709}
4710
4711/// Load packed 8-bit integers from memory into dst using zeromask k
4712/// (elements are zeroed out when the corresponding mask bit is not set).
4713/// mem_addr does not need to be aligned on any particular boundary.
4714///
4715/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_loadu_epi8)
4716#[inline]
4717#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4718#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4719pub unsafe fn _mm256_maskz_loadu_epi8(k: __mmask32, mem_addr: *const i8) -> __m256i {
4720 let mut dst: __m256i;
4721 asm!(
4722 vpl!("vmovdqu8 {dst}{{{k}}} {{z}}"),
4723 p = in(reg) mem_addr,
4724 k = in(kreg) k,
4725 dst = out(ymm_reg) dst,
4726 options(pure, readonly, nostack)
4727 );
4728 dst
4729}
4730
4731/// Load packed 16-bit integers from memory into dst using writemask k
4732/// (elements are copied from src when the corresponding mask bit is not set).
4733/// mem_addr does not need to be aligned on any particular boundary.
4734///
4735/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_loadu_epi16)
4736#[inline]
4737#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4738#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4739pub unsafe fn _mm_mask_loadu_epi16(src: __m128i, k: __mmask8, mem_addr: *const i16) -> __m128i {
4740 let mut dst: __m128i = src;
4741 asm!(
4742 vpl!("vmovdqu16 {dst}{{{k}}}"),
4743 p = in(reg) mem_addr,
4744 k = in(kreg) k,
4745 dst = inout(xmm_reg) dst,
4746 options(pure, readonly, nostack)
4747 );
4748 dst
4749}
4750
4751/// Load packed 16-bit integers from memory into dst using zeromask k
4752/// (elements are zeroed out when the corresponding mask bit is not set).
4753/// mem_addr does not need to be aligned on any particular boundary.
4754///
4755/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_loadu_epi16)
4756#[inline]
4757#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4758#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4759pub unsafe fn _mm_maskz_loadu_epi16(k: __mmask8, mem_addr: *const i16) -> __m128i {
4760 let mut dst: __m128i;
4761 asm!(
4762 vpl!("vmovdqu16 {dst}{{{k}}} {{z}}"),
4763 p = in(reg) mem_addr,
4764 k = in(kreg) k,
4765 dst = out(xmm_reg) dst,
4766 options(pure, readonly, nostack)
4767 );
4768 dst
4769}
4770
4771/// Load packed 8-bit integers from memory into dst using writemask k
4772/// (elements are copied from src when the corresponding mask bit is not set).
4773/// mem_addr does not need to be aligned on any particular boundary.
4774///
4775/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_loadu_epi8)
4776#[inline]
4777#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4778#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4779pub unsafe fn _mm_mask_loadu_epi8(src: __m128i, k: __mmask16, mem_addr: *const i8) -> __m128i {
4780 let mut dst: __m128i = src;
4781 asm!(
4782 vpl!("vmovdqu8 {dst}{{{k}}}"),
4783 p = in(reg) mem_addr,
4784 k = in(kreg) k,
4785 dst = inout(xmm_reg) dst,
4786 options(pure, readonly, nostack)
4787 );
4788 dst
4789}
4790
4791/// Load packed 8-bit integers from memory into dst using zeromask k
4792/// (elements are zeroed out when the corresponding mask bit is not set).
4793/// mem_addr does not need to be aligned on any particular boundary.
4794///
4795/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_loadu_epi8)
4796#[inline]
4797#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4798#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4799pub unsafe fn _mm_maskz_loadu_epi8(k: __mmask16, mem_addr: *const i8) -> __m128i {
4800 let mut dst: __m128i;
4801 asm!(
4802 vpl!("vmovdqu8 {dst}{{{k}}} {{z}}"),
4803 p = in(reg) mem_addr,
4804 k = in(kreg) k,
4805 dst = out(xmm_reg) dst,
4806 options(pure, readonly, nostack)
4807 );
4808 dst
4809}
4810
4811/// Store packed 16-bit integers from a into memory using writemask k.
4812/// mem_addr does not need to be aligned on any particular boundary.
4813///
4814/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_storeu_epi16)
4815#[inline]
4816#[target_feature(enable = "avx512f,avx512bw")]
4817#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4818pub unsafe fn _mm512_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask32, a: __m512i) {
4819 asm!(
4820 vps!("vmovdqu16", "{{{mask}}}, {a}"),
4821 p = in(reg) mem_addr,
4822 mask = in(kreg) mask,
4823 a = in(zmm_reg) a,
4824 options(nostack)
4825 );
4826}
4827
4828/// Store packed 8-bit integers from a into memory using writemask k.
4829/// mem_addr does not need to be aligned on any particular boundary.
4830///
4831/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_storeu_epi8)
4832#[inline]
4833#[target_feature(enable = "avx512f,avx512bw")]
4834#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4835pub unsafe fn _mm512_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask64, a: __m512i) {
4836 asm!(
4837 vps!("vmovdqu8", "{{{mask}}}, {a}"),
4838 p = in(reg) mem_addr,
4839 mask = in(kreg) mask,
4840 a = in(zmm_reg) a,
4841 options(nostack)
4842 );
4843}
4844
4845/// Store packed 16-bit integers from a into memory using writemask k.
4846/// mem_addr does not need to be aligned on any particular boundary.
4847///
4848/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_storeu_epi16)
4849#[inline]
4850#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4851#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4852pub unsafe fn _mm256_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask16, a: __m256i) {
4853 asm!(
4854 vps!("vmovdqu16", "{{{mask}}}, {a}"),
4855 p = in(reg) mem_addr,
4856 mask = in(kreg) mask,
4857 a = in(ymm_reg) a,
4858 options(nostack)
4859 );
4860}
4861
4862/// Store packed 8-bit integers from a into memory using writemask k.
4863/// mem_addr does not need to be aligned on any particular boundary.
4864///
4865/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_storeu_epi8)
4866#[inline]
4867#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx")]
4868#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4869pub unsafe fn _mm256_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask32, a: __m256i) {
4870 asm!(
4871 vps!("vmovdqu8", "{{{mask}}}, {a}"),
4872 p = in(reg) mem_addr,
4873 mask = in(kreg) mask,
4874 a = in(ymm_reg) a,
4875 options(nostack)
4876 );
4877}
4878
4879/// Store packed 16-bit integers from a into memory using writemask k.
4880/// mem_addr does not need to be aligned on any particular boundary.
4881///
4882/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_storeu_epi16)
4883#[inline]
4884#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4885#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4886pub unsafe fn _mm_mask_storeu_epi16(mem_addr: *mut i16, mask: __mmask8, a: __m128i) {
4887 asm!(
4888 vps!("vmovdqu16", "{{{mask}}}, {a}"),
4889 p = in(reg) mem_addr,
4890 mask = in(kreg) mask,
4891 a = in(xmm_reg) a,
4892 options(nostack)
4893 );
4894}
4895
4896/// Store packed 8-bit integers from a into memory using writemask k.
4897/// mem_addr does not need to be aligned on any particular boundary.
4898///
4899/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_storeu_epi8)
4900#[inline]
4901#[target_feature(enable = "avx512f,avx512bw,avx512vl,avx,sse")]
4902#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4903pub unsafe fn _mm_mask_storeu_epi8(mem_addr: *mut i8, mask: __mmask16, a: __m128i) {
4904 asm!(
4905 vps!("vmovdqu8", "{{{mask}}}, {a}"),
4906 p = in(reg) mem_addr,
4907 mask = in(kreg) mask,
4908 a = in(xmm_reg) a,
4909 options(nostack)
4910 );
4911}
4912
4913/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst.
4914///
4915/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_madd_epi16&expand=3511)
4916#[inline]
4917#[target_feature(enable = "avx512bw")]
4918#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4919#[cfg_attr(test, assert_instr(vpmaddwd))]
4920pub unsafe fn _mm512_madd_epi16(a: __m512i, b: __m512i) -> __m512i {
4921 transmute(src:vpmaddwd(a:a.as_i16x32(), b:b.as_i16x32()))
4922}
4923
4924/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
4925///
4926/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_madd_epi16&expand=3512)
4927#[inline]
4928#[target_feature(enable = "avx512bw")]
4929#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4930#[cfg_attr(test, assert_instr(vpmaddwd))]
4931pub unsafe fn _mm512_mask_madd_epi16(
4932 src: __m512i,
4933 k: __mmask16,
4934 a: __m512i,
4935 b: __m512i,
4936) -> __m512i {
4937 let madd: i32x16 = _mm512_madd_epi16(a, b).as_i32x16();
4938 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i32x16()))
4939}
4940
4941/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
4942///
4943/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_madd_epi16&expand=3513)
4944#[inline]
4945#[target_feature(enable = "avx512bw")]
4946#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4947#[cfg_attr(test, assert_instr(vpmaddwd))]
4948pub unsafe fn _mm512_maskz_madd_epi16(k: __mmask16, a: __m512i, b: __m512i) -> __m512i {
4949 let madd: i32x16 = _mm512_madd_epi16(a, b).as_i32x16();
4950 let zero: i32x16 = _mm512_setzero_si512().as_i32x16();
4951 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
4952}
4953
4954/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
4955///
4956/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_madd_epi16&expand=3509)
4957#[inline]
4958#[target_feature(enable = "avx512bw,avx512vl")]
4959#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4960#[cfg_attr(test, assert_instr(vpmaddwd))]
4961pub unsafe fn _mm256_mask_madd_epi16(src: __m256i, k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
4962 let madd: i32x8 = _mm256_madd_epi16(a, b).as_i32x8();
4963 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i32x8()))
4964}
4965
4966/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
4967///
4968/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_madd_epi16&expand=3510)
4969#[inline]
4970#[target_feature(enable = "avx512bw,avx512vl")]
4971#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4972#[cfg_attr(test, assert_instr(vpmaddwd))]
4973pub unsafe fn _mm256_maskz_madd_epi16(k: __mmask8, a: __m256i, b: __m256i) -> __m256i {
4974 let madd: i32x8 = _mm256_madd_epi16(a, b).as_i32x8();
4975 let zero: i32x8 = _mm256_setzero_si256().as_i32x8();
4976 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
4977}
4978
4979/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
4980///
4981/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_madd_epi16&expand=3506)
4982#[inline]
4983#[target_feature(enable = "avx512bw,avx512vl")]
4984#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4985#[cfg_attr(test, assert_instr(vpmaddwd))]
4986pub unsafe fn _mm_mask_madd_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
4987 let madd: i32x4 = _mm_madd_epi16(a, b).as_i32x4();
4988 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i32x4()))
4989}
4990
4991/// Multiply packed signed 16-bit integers in a and b, producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
4992///
4993/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_madd_epi16&expand=3507)
4994#[inline]
4995#[target_feature(enable = "avx512bw,avx512vl")]
4996#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
4997#[cfg_attr(test, assert_instr(vpmaddwd))]
4998pub unsafe fn _mm_maskz_madd_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
4999 let madd: i32x4 = _mm_madd_epi16(a, b).as_i32x4();
5000 let zero: i32x4 = _mm_setzero_si128().as_i32x4();
5001 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
5002}
5003
5004/// Vertically multiply each unsigned 8-bit integer from a with the corresponding signed 8-bit integer from b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst.
5005///
5006/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maddubs_epi16&expand=3539)
5007#[inline]
5008#[target_feature(enable = "avx512bw")]
5009#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5010#[cfg_attr(test, assert_instr(vpmaddubsw))]
5011pub unsafe fn _mm512_maddubs_epi16(a: __m512i, b: __m512i) -> __m512i {
5012 transmute(src:vpmaddubsw(a:a.as_i8x64(), b:b.as_i8x64()))
5013}
5014
5015/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5016///
5017/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_maddubs_epi16&expand=3540)
5018#[inline]
5019#[target_feature(enable = "avx512bw")]
5020#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5021#[cfg_attr(test, assert_instr(vpmaddubsw))]
5022pub unsafe fn _mm512_mask_maddubs_epi16(
5023 src: __m512i,
5024 k: __mmask32,
5025 a: __m512i,
5026 b: __m512i,
5027) -> __m512i {
5028 let madd: i16x32 = _mm512_maddubs_epi16(a, b).as_i16x32();
5029 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i16x32()))
5030}
5031
5032/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5033///
5034/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_maddubs_epi16&expand=3541)
5035#[inline]
5036#[target_feature(enable = "avx512bw")]
5037#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5038#[cfg_attr(test, assert_instr(vpmaddubsw))]
5039pub unsafe fn _mm512_maskz_maddubs_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
5040 let madd: i16x32 = _mm512_maddubs_epi16(a, b).as_i16x32();
5041 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
5042 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
5043}
5044
5045/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5046///
5047/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_maddubs_epi16&expand=3537)
5048#[inline]
5049#[target_feature(enable = "avx512bw,avx512vl")]
5050#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5051#[cfg_attr(test, assert_instr(vpmaddubsw))]
5052pub unsafe fn _mm256_mask_maddubs_epi16(
5053 src: __m256i,
5054 k: __mmask16,
5055 a: __m256i,
5056 b: __m256i,
5057) -> __m256i {
5058 let madd: i16x16 = _mm256_maddubs_epi16(a, b).as_i16x16();
5059 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i16x16()))
5060}
5061
5062/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5063///
5064/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_maddubs_epi16&expand=3538)
5065#[inline]
5066#[target_feature(enable = "avx512bw,avx512vl")]
5067#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5068#[cfg_attr(test, assert_instr(vpmaddubsw))]
5069pub unsafe fn _mm256_maskz_maddubs_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
5070 let madd: i16x16 = _mm256_maddubs_epi16(a, b).as_i16x16();
5071 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
5072 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
5073}
5074
5075/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5076///
5077/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_maddubs_epi16&expand=3534)
5078#[inline]
5079#[target_feature(enable = "avx512bw,avx512vl")]
5080#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5081#[cfg_attr(test, assert_instr(vpmaddubsw))]
5082pub unsafe fn _mm_mask_maddubs_epi16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5083 let madd: i16x8 = _mm_maddubs_epi16(a, b).as_i16x8();
5084 transmute(src:simd_select_bitmask(m:k, yes:madd, no:src.as_i16x8()))
5085}
5086
5087/// Multiply packed unsigned 8-bit integers in a by packed signed 8-bit integers in b, producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5088///
5089/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_maddubs_epi16&expand=3535)
5090#[inline]
5091#[target_feature(enable = "avx512bw,avx512vl")]
5092#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5093#[cfg_attr(test, assert_instr(vpmaddubsw))]
5094pub unsafe fn _mm_maskz_maddubs_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5095 let madd: i16x8 = _mm_maddubs_epi16(a, b).as_i16x8();
5096 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
5097 transmute(src:simd_select_bitmask(m:k, yes:madd, no:zero))
5098}
5099
5100/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst.
5101///
5102/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packs_epi32&expand=4091)
5103#[inline]
5104#[target_feature(enable = "avx512bw")]
5105#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5106#[cfg_attr(test, assert_instr(vpackssdw))]
5107pub unsafe fn _mm512_packs_epi32(a: __m512i, b: __m512i) -> __m512i {
5108 transmute(src:vpackssdw(a:a.as_i32x16(), b:b.as_i32x16()))
5109}
5110
5111/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5112///
5113/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packs_epi32&expand=4089)
5114#[inline]
5115#[target_feature(enable = "avx512bw")]
5116#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5117#[cfg_attr(test, assert_instr(vpackssdw))]
5118pub unsafe fn _mm512_mask_packs_epi32(
5119 src: __m512i,
5120 k: __mmask32,
5121 a: __m512i,
5122 b: __m512i,
5123) -> __m512i {
5124 let pack: i16x32 = _mm512_packs_epi32(a, b).as_i16x32();
5125 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x32()))
5126}
5127
5128/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5129///
5130/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packs_epi32&expand=4090)
5131#[inline]
5132#[target_feature(enable = "avx512bw")]
5133#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5134#[cfg_attr(test, assert_instr(vpackssdw))]
5135pub unsafe fn _mm512_maskz_packs_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
5136 let pack: i16x32 = _mm512_packs_epi32(a, b).as_i16x32();
5137 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
5138 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5139}
5140
5141/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5142///
5143/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packs_epi32&expand=4086)
5144#[inline]
5145#[target_feature(enable = "avx512bw,avx512vl")]
5146#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5147#[cfg_attr(test, assert_instr(vpackssdw))]
5148pub unsafe fn _mm256_mask_packs_epi32(
5149 src: __m256i,
5150 k: __mmask16,
5151 a: __m256i,
5152 b: __m256i,
5153) -> __m256i {
5154 let pack: i16x16 = _mm256_packs_epi32(a, b).as_i16x16();
5155 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x16()))
5156}
5157
5158/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5159///
5160/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packs_epi32&expand=4087)
5161#[inline]
5162#[target_feature(enable = "avx512bw,avx512vl")]
5163#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5164#[cfg_attr(test, assert_instr(vpackssdw))]
5165pub unsafe fn _mm256_maskz_packs_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
5166 let pack: i16x16 = _mm256_packs_epi32(a, b).as_i16x16();
5167 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
5168 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5169}
5170
5171/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5172///
5173/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packs_epi32&expand=4083)
5174#[inline]
5175#[target_feature(enable = "avx512bw,avx512vl")]
5176#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5177#[cfg_attr(test, assert_instr(vpackssdw))]
5178pub unsafe fn _mm_mask_packs_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5179 let pack: i16x8 = _mm_packs_epi32(a, b).as_i16x8();
5180 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x8()))
5181}
5182
5183/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5184///
5185/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packs_epi32&expand=4084)
5186#[inline]
5187#[target_feature(enable = "avx512bw,avx512vl")]
5188#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5189#[cfg_attr(test, assert_instr(vpackssdw))]
5190pub unsafe fn _mm_maskz_packs_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5191 let pack: i16x8 = _mm_packs_epi32(a, b).as_i16x8();
5192 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
5193 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5194}
5195
5196/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst.
5197///
5198/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packs_epi16&expand=4082)
5199#[inline]
5200#[target_feature(enable = "avx512bw")]
5201#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5202#[cfg_attr(test, assert_instr(vpacksswb))]
5203pub unsafe fn _mm512_packs_epi16(a: __m512i, b: __m512i) -> __m512i {
5204 transmute(src:vpacksswb(a:a.as_i16x32(), b:b.as_i16x32()))
5205}
5206
5207/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5208///
5209/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packs_epi16&expand=4080)
5210#[inline]
5211#[target_feature(enable = "avx512bw")]
5212#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5213#[cfg_attr(test, assert_instr(vpacksswb))]
5214pub unsafe fn _mm512_mask_packs_epi16(
5215 src: __m512i,
5216 k: __mmask64,
5217 a: __m512i,
5218 b: __m512i,
5219) -> __m512i {
5220 let pack: i8x64 = _mm512_packs_epi16(a, b).as_i8x64();
5221 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x64()))
5222}
5223
5224/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5225///
5226/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packs_epi16&expand=4081)
5227#[inline]
5228#[target_feature(enable = "avx512bw")]
5229#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5230#[cfg_attr(test, assert_instr(vpacksswb))]
5231pub unsafe fn _mm512_maskz_packs_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
5232 let pack: i8x64 = _mm512_packs_epi16(a, b).as_i8x64();
5233 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
5234 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5235}
5236
5237/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5238///
5239/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packs_epi16&expand=4077)
5240#[inline]
5241#[target_feature(enable = "avx512bw,avx512vl")]
5242#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5243#[cfg_attr(test, assert_instr(vpacksswb))]
5244pub unsafe fn _mm256_mask_packs_epi16(
5245 src: __m256i,
5246 k: __mmask32,
5247 a: __m256i,
5248 b: __m256i,
5249) -> __m256i {
5250 let pack: i8x32 = _mm256_packs_epi16(a, b).as_i8x32();
5251 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x32()))
5252}
5253
5254/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5255///
5256/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=#text=_mm256_maskz_packs_epi16&expand=4078)
5257#[inline]
5258#[target_feature(enable = "avx512bw,avx512vl")]
5259#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5260#[cfg_attr(test, assert_instr(vpacksswb))]
5261pub unsafe fn _mm256_maskz_packs_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
5262 let pack: i8x32 = _mm256_packs_epi16(a, b).as_i8x32();
5263 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
5264 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5265}
5266
5267/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5268///
5269/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packs_epi16&expand=4074)
5270#[inline]
5271#[target_feature(enable = "avx512bw,avx512vl")]
5272#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5273#[cfg_attr(test, assert_instr(vpacksswb))]
5274pub unsafe fn _mm_mask_packs_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5275 let pack: i8x16 = _mm_packs_epi16(a, b).as_i8x16();
5276 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x16()))
5277}
5278
5279/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5280///
5281/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packs_epi16&expand=4075)
5282#[inline]
5283#[target_feature(enable = "avx512bw,avx512vl")]
5284#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5285#[cfg_attr(test, assert_instr(vpacksswb))]
5286pub unsafe fn _mm_maskz_packs_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5287 let pack: i8x16 = _mm_packs_epi16(a, b).as_i8x16();
5288 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
5289 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5290}
5291
5292/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst.
5293///
5294/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packus_epi32&expand=4130)
5295#[inline]
5296#[target_feature(enable = "avx512bw")]
5297#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5298#[cfg_attr(test, assert_instr(vpackusdw))]
5299pub unsafe fn _mm512_packus_epi32(a: __m512i, b: __m512i) -> __m512i {
5300 transmute(src:vpackusdw(a:a.as_i32x16(), b:b.as_i32x16()))
5301}
5302
5303/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5304///
5305/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packus_epi32&expand=4128)
5306#[inline]
5307#[target_feature(enable = "avx512bw")]
5308#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5309#[cfg_attr(test, assert_instr(vpackusdw))]
5310pub unsafe fn _mm512_mask_packus_epi32(
5311 src: __m512i,
5312 k: __mmask32,
5313 a: __m512i,
5314 b: __m512i,
5315) -> __m512i {
5316 let pack: i16x32 = _mm512_packus_epi32(a, b).as_i16x32();
5317 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x32()))
5318}
5319
5320/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5321///
5322/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packus_epi32&expand=4129)
5323#[inline]
5324#[target_feature(enable = "avx512bw")]
5325#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5326#[cfg_attr(test, assert_instr(vpackusdw))]
5327pub unsafe fn _mm512_maskz_packus_epi32(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
5328 let pack: i16x32 = _mm512_packus_epi32(a, b).as_i16x32();
5329 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
5330 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5331}
5332
5333/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5334///
5335/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packus_epi32&expand=4125)
5336#[inline]
5337#[target_feature(enable = "avx512bw,avx512vl")]
5338#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5339#[cfg_attr(test, assert_instr(vpackusdw))]
5340pub unsafe fn _mm256_mask_packus_epi32(
5341 src: __m256i,
5342 k: __mmask16,
5343 a: __m256i,
5344 b: __m256i,
5345) -> __m256i {
5346 let pack: i16x16 = _mm256_packus_epi32(a, b).as_i16x16();
5347 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x16()))
5348}
5349
5350/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5351///
5352/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packus_epi32&expand=4126)
5353#[inline]
5354#[target_feature(enable = "avx512bw,avx512vl")]
5355#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5356#[cfg_attr(test, assert_instr(vpackusdw))]
5357pub unsafe fn _mm256_maskz_packus_epi32(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
5358 let pack: i16x16 = _mm256_packus_epi32(a, b).as_i16x16();
5359 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
5360 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5361}
5362
5363/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5364///
5365/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packus_epi32&expand=4122)
5366#[inline]
5367#[target_feature(enable = "avx512bw,avx512vl")]
5368#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5369#[cfg_attr(test, assert_instr(vpackusdw))]
5370pub unsafe fn _mm_mask_packus_epi32(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5371 let pack: i16x8 = _mm_packus_epi32(a, b).as_i16x8();
5372 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i16x8()))
5373}
5374
5375/// Convert packed signed 32-bit integers from a and b to packed 16-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5376///
5377/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packus_epi32&expand=4123)
5378#[inline]
5379#[target_feature(enable = "avx512bw,avx512vl")]
5380#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5381#[cfg_attr(test, assert_instr(vpackusdw))]
5382pub unsafe fn _mm_maskz_packus_epi32(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5383 let pack: i16x8 = _mm_packus_epi32(a, b).as_i16x8();
5384 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
5385 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5386}
5387
5388/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst.
5389///
5390/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_packus_epi16&expand=4121)
5391#[inline]
5392#[target_feature(enable = "avx512bw")]
5393#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5394#[cfg_attr(test, assert_instr(vpackuswb))]
5395pub unsafe fn _mm512_packus_epi16(a: __m512i, b: __m512i) -> __m512i {
5396 transmute(src:vpackuswb(a:a.as_i16x32(), b:b.as_i16x32()))
5397}
5398
5399/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5400///
5401/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_packus_epi16&expand=4119)
5402#[inline]
5403#[target_feature(enable = "avx512bw")]
5404#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5405#[cfg_attr(test, assert_instr(vpackuswb))]
5406pub unsafe fn _mm512_mask_packus_epi16(
5407 src: __m512i,
5408 k: __mmask64,
5409 a: __m512i,
5410 b: __m512i,
5411) -> __m512i {
5412 let pack: i8x64 = _mm512_packus_epi16(a, b).as_i8x64();
5413 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x64()))
5414}
5415
5416/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5417///
5418/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_packus_epi16&expand=4120)
5419#[inline]
5420#[target_feature(enable = "avx512bw")]
5421#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5422#[cfg_attr(test, assert_instr(vpackuswb))]
5423pub unsafe fn _mm512_maskz_packus_epi16(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
5424 let pack: i8x64 = _mm512_packus_epi16(a, b).as_i8x64();
5425 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
5426 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5427}
5428
5429/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5430///
5431/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_packus_epi16&expand=4116)
5432#[inline]
5433#[target_feature(enable = "avx512bw,avx512vl")]
5434#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5435#[cfg_attr(test, assert_instr(vpackuswb))]
5436pub unsafe fn _mm256_mask_packus_epi16(
5437 src: __m256i,
5438 k: __mmask32,
5439 a: __m256i,
5440 b: __m256i,
5441) -> __m256i {
5442 let pack: i8x32 = _mm256_packus_epi16(a, b).as_i8x32();
5443 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x32()))
5444}
5445
5446/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5447///
5448/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_packus_epi16&expand=4117)
5449#[inline]
5450#[target_feature(enable = "avx512bw,avx512vl")]
5451#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5452#[cfg_attr(test, assert_instr(vpackuswb))]
5453pub unsafe fn _mm256_maskz_packus_epi16(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
5454 let pack: i8x32 = _mm256_packus_epi16(a, b).as_i8x32();
5455 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
5456 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5457}
5458
5459/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5460///
5461/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_packus_epi16&expand=4113)
5462#[inline]
5463#[target_feature(enable = "avx512bw,avx512vl")]
5464#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5465#[cfg_attr(test, assert_instr(vpackuswb))]
5466pub unsafe fn _mm_mask_packus_epi16(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5467 let pack: i8x16 = _mm_packus_epi16(a, b).as_i8x16();
5468 transmute(src:simd_select_bitmask(m:k, yes:pack, no:src.as_i8x16()))
5469}
5470
5471/// Convert packed signed 16-bit integers from a and b to packed 8-bit integers using unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5472///
5473/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_packus_epi16&expand=4114)
5474#[inline]
5475#[target_feature(enable = "avx512bw,avx512vl")]
5476#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5477#[cfg_attr(test, assert_instr(vpackuswb))]
5478pub unsafe fn _mm_maskz_packus_epi16(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5479 let pack: i8x16 = _mm_packus_epi16(a, b).as_i8x16();
5480 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
5481 transmute(src:simd_select_bitmask(m:k, yes:pack, no:zero))
5482}
5483
5484/// Average packed unsigned 16-bit integers in a and b, and store the results in dst.
5485///
5486/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_avg_epu16&expand=388)
5487#[inline]
5488#[target_feature(enable = "avx512bw")]
5489#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5490#[cfg_attr(test, assert_instr(vpavgw))]
5491pub unsafe fn _mm512_avg_epu16(a: __m512i, b: __m512i) -> __m512i {
5492 transmute(src:vpavgw(a:a.as_u16x32(), b:b.as_u16x32()))
5493}
5494
5495/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5496///
5497/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_avg_epu16&expand=389)
5498#[inline]
5499#[target_feature(enable = "avx512bw")]
5500#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5501#[cfg_attr(test, assert_instr(vpavgw))]
5502pub unsafe fn _mm512_mask_avg_epu16(src: __m512i, k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
5503 let avg: u16x32 = _mm512_avg_epu16(a, b).as_u16x32();
5504 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u16x32()))
5505}
5506
5507/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5508///
5509/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_avg_epu16&expand=390)
5510#[inline]
5511#[target_feature(enable = "avx512bw")]
5512#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5513#[cfg_attr(test, assert_instr(vpavgw))]
5514pub unsafe fn _mm512_maskz_avg_epu16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
5515 let avg: u16x32 = _mm512_avg_epu16(a, b).as_u16x32();
5516 let zero: u16x32 = _mm512_setzero_si512().as_u16x32();
5517 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5518}
5519
5520/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5521///
5522/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_avg_epu16&expand=386)
5523#[inline]
5524#[target_feature(enable = "avx512bw,avx512vl")]
5525#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5526#[cfg_attr(test, assert_instr(vpavgw))]
5527pub unsafe fn _mm256_mask_avg_epu16(src: __m256i, k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
5528 let avg: u16x16 = _mm256_avg_epu16(a, b).as_u16x16();
5529 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u16x16()))
5530}
5531
5532/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5533///
5534/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_avg_epu16&expand=387)
5535#[inline]
5536#[target_feature(enable = "avx512bw,avx512vl")]
5537#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5538#[cfg_attr(test, assert_instr(vpavgw))]
5539pub unsafe fn _mm256_maskz_avg_epu16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
5540 let avg: u16x16 = _mm256_avg_epu16(a, b).as_u16x16();
5541 let zero: u16x16 = _mm256_setzero_si256().as_u16x16();
5542 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5543}
5544
5545/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5546///
5547/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_avg_epu16&expand=383)
5548#[inline]
5549#[target_feature(enable = "avx512bw,avx512vl")]
5550#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5551#[cfg_attr(test, assert_instr(vpavgw))]
5552pub unsafe fn _mm_mask_avg_epu16(src: __m128i, k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5553 let avg: u16x8 = _mm_avg_epu16(a, b).as_u16x8();
5554 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u16x8()))
5555}
5556
5557/// Average packed unsigned 16-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5558///
5559/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_avg_epu16&expand=384)
5560#[inline]
5561#[target_feature(enable = "avx512bw,avx512vl")]
5562#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5563#[cfg_attr(test, assert_instr(vpavgw))]
5564pub unsafe fn _mm_maskz_avg_epu16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
5565 let avg: u16x8 = _mm_avg_epu16(a, b).as_u16x8();
5566 let zero: u16x8 = _mm_setzero_si128().as_u16x8();
5567 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5568}
5569
5570/// Average packed unsigned 8-bit integers in a and b, and store the results in dst.
5571///
5572/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_avg_epu8&expand=397)
5573#[inline]
5574#[target_feature(enable = "avx512bw")]
5575#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5576#[cfg_attr(test, assert_instr(vpavgb))]
5577pub unsafe fn _mm512_avg_epu8(a: __m512i, b: __m512i) -> __m512i {
5578 transmute(src:vpavgb(a:a.as_u8x64(), b:b.as_u8x64()))
5579}
5580
5581/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5582///
5583/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_avg_epu8&expand=398)
5584#[inline]
5585#[target_feature(enable = "avx512bw")]
5586#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5587#[cfg_attr(test, assert_instr(vpavgb))]
5588pub unsafe fn _mm512_mask_avg_epu8(src: __m512i, k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
5589 let avg: u8x64 = _mm512_avg_epu8(a, b).as_u8x64();
5590 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u8x64()))
5591}
5592
5593/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5594///
5595/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_avg_epu8&expand=399)
5596#[inline]
5597#[target_feature(enable = "avx512bw")]
5598#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5599#[cfg_attr(test, assert_instr(vpavgb))]
5600pub unsafe fn _mm512_maskz_avg_epu8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
5601 let avg: u8x64 = _mm512_avg_epu8(a, b).as_u8x64();
5602 let zero: u8x64 = _mm512_setzero_si512().as_u8x64();
5603 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5604}
5605
5606/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5607///
5608/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_avg_epu8&expand=395)
5609#[inline]
5610#[target_feature(enable = "avx512bw,avx512vl")]
5611#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5612#[cfg_attr(test, assert_instr(vpavgb))]
5613pub unsafe fn _mm256_mask_avg_epu8(src: __m256i, k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
5614 let avg: u8x32 = _mm256_avg_epu8(a, b).as_u8x32();
5615 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u8x32()))
5616}
5617
5618/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5619///
5620/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_avg_epu8&expand=396)
5621#[inline]
5622#[target_feature(enable = "avx512bw,avx512vl")]
5623#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5624#[cfg_attr(test, assert_instr(vpavgb))]
5625pub unsafe fn _mm256_maskz_avg_epu8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
5626 let avg: u8x32 = _mm256_avg_epu8(a, b).as_u8x32();
5627 let zero: u8x32 = _mm256_setzero_si256().as_u8x32();
5628 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5629}
5630
5631/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5632///
5633/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_avg_epu8&expand=392)
5634#[inline]
5635#[target_feature(enable = "avx512bw,avx512vl")]
5636#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5637#[cfg_attr(test, assert_instr(vpavgb))]
5638pub unsafe fn _mm_mask_avg_epu8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5639 let avg: u8x16 = _mm_avg_epu8(a, b).as_u8x16();
5640 transmute(src:simd_select_bitmask(m:k, yes:avg, no:src.as_u8x16()))
5641}
5642
5643/// Average packed unsigned 8-bit integers in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5644///
5645/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_avg_epu8&expand=393)
5646#[inline]
5647#[target_feature(enable = "avx512bw,avx512vl")]
5648#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5649#[cfg_attr(test, assert_instr(vpavgb))]
5650pub unsafe fn _mm_maskz_avg_epu8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
5651 let avg: u8x16 = _mm_avg_epu8(a, b).as_u8x16();
5652 let zero: u8x16 = _mm_setzero_si128().as_u8x16();
5653 transmute(src:simd_select_bitmask(m:k, yes:avg, no:zero))
5654}
5655
5656/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst.
5657///
5658/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sll_epi16&expand=5271)
5659#[inline]
5660#[target_feature(enable = "avx512bw")]
5661#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5662#[cfg_attr(test, assert_instr(vpsllw))]
5663pub unsafe fn _mm512_sll_epi16(a: __m512i, count: __m128i) -> __m512i {
5664 transmute(src:vpsllw(a:a.as_i16x32(), count:count.as_i16x8()))
5665}
5666
5667/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5668///
5669/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sll_epi16&expand=5269)
5670#[inline]
5671#[target_feature(enable = "avx512bw")]
5672#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5673#[cfg_attr(test, assert_instr(vpsllw))]
5674pub unsafe fn _mm512_mask_sll_epi16(
5675 src: __m512i,
5676 k: __mmask32,
5677 a: __m512i,
5678 count: __m128i,
5679) -> __m512i {
5680 let shf: i16x32 = _mm512_sll_epi16(a, count).as_i16x32();
5681 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
5682}
5683
5684/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5685///
5686/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sll_epi16&expand=5270)
5687#[inline]
5688#[target_feature(enable = "avx512bw")]
5689#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5690#[cfg_attr(test, assert_instr(vpsllw))]
5691pub unsafe fn _mm512_maskz_sll_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i {
5692 let shf: i16x32 = _mm512_sll_epi16(a, count).as_i16x32();
5693 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
5694 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5695}
5696
5697/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5698///
5699/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sll_epi16&expand=5266)
5700#[inline]
5701#[target_feature(enable = "avx512bw,avx512vl")]
5702#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5703#[cfg_attr(test, assert_instr(vpsllw))]
5704pub unsafe fn _mm256_mask_sll_epi16(
5705 src: __m256i,
5706 k: __mmask16,
5707 a: __m256i,
5708 count: __m128i,
5709) -> __m256i {
5710 let shf: i16x16 = _mm256_sll_epi16(a, count).as_i16x16();
5711 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
5712}
5713
5714/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5715///
5716/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sll_epi16&expand=5267)
5717#[inline]
5718#[target_feature(enable = "avx512bw,avx512vl")]
5719#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5720#[cfg_attr(test, assert_instr(vpsllw))]
5721pub unsafe fn _mm256_maskz_sll_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i {
5722 let shf: i16x16 = _mm256_sll_epi16(a, count).as_i16x16();
5723 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
5724 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5725}
5726
5727/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5728///
5729/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sll_epi16&expand=5263)
5730#[inline]
5731#[target_feature(enable = "avx512bw,avx512vl")]
5732#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5733#[cfg_attr(test, assert_instr(vpsllw))]
5734pub unsafe fn _mm_mask_sll_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
5735 let shf: i16x8 = _mm_sll_epi16(a, count).as_i16x8();
5736 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
5737}
5738
5739/// Shift packed 16-bit integers in a left by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5740///
5741/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sll_epi16&expand=5264)
5742#[inline]
5743#[target_feature(enable = "avx512bw,avx512vl")]
5744#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5745#[cfg_attr(test, assert_instr(vpsllw))]
5746pub unsafe fn _mm_maskz_sll_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
5747 let shf: i16x8 = _mm_sll_epi16(a, count).as_i16x8();
5748 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
5749 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5750}
5751
5752/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst.
5753///
5754/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_slli_epi16&expand=5301)
5755#[inline]
5756#[target_feature(enable = "avx512bw")]
5757#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5758#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5759#[rustc_legacy_const_generics(1)]
5760pub unsafe fn _mm512_slli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
5761 static_assert_uimm_bits!(IMM8, 8);
5762 if IMM8 >= 16 {
5763 _mm512_setzero_si512()
5764 } else {
5765 transmute(src:simd_shl(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16)))
5766 }
5767}
5768
5769/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5770///
5771/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_slli_epi16&expand=5299)
5772#[inline]
5773#[target_feature(enable = "avx512bw")]
5774#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5775#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5776#[rustc_legacy_const_generics(3)]
5777pub unsafe fn _mm512_mask_slli_epi16<const IMM8: u32>(
5778 src: __m512i,
5779 k: __mmask32,
5780 a: __m512i,
5781) -> __m512i {
5782 static_assert_uimm_bits!(IMM8, 8);
5783 let shf: u16x32 = if IMM8 >= 16 {
5784 u16x32::splat(0)
5785 } else {
5786 simd_shl(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16))
5787 };
5788 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_u16x32()))
5789}
5790
5791/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5792///
5793/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_slli_epi16&expand=5300)
5794#[inline]
5795#[target_feature(enable = "avx512bw")]
5796#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5797#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5798#[rustc_legacy_const_generics(2)]
5799pub unsafe fn _mm512_maskz_slli_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
5800 static_assert_uimm_bits!(IMM8, 8);
5801 if IMM8 >= 16 {
5802 _mm512_setzero_si512()
5803 } else {
5804 let shf: u16x32 = simd_shl(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16));
5805 let zero: u16x32 = u16x32::splat(0);
5806 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5807 }
5808}
5809
5810/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5811///
5812/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_slli_epi16&expand=5296)
5813#[inline]
5814#[target_feature(enable = "avx512bw,avx512vl")]
5815#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5816#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5817#[rustc_legacy_const_generics(3)]
5818pub unsafe fn _mm256_mask_slli_epi16<const IMM8: u32>(
5819 src: __m256i,
5820 k: __mmask16,
5821 a: __m256i,
5822) -> __m256i {
5823 static_assert_uimm_bits!(IMM8, 8);
5824 let shf: u16x16 = if IMM8 >= 16 {
5825 u16x16::splat(0)
5826 } else {
5827 simd_shl(lhs:a.as_u16x16(), rhs:u16x16::splat(IMM8 as u16))
5828 };
5829 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_u16x16()))
5830}
5831
5832/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5833///
5834/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_slli_epi16&expand=5297)
5835#[inline]
5836#[target_feature(enable = "avx512bw,avx512vl")]
5837#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5838#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5839#[rustc_legacy_const_generics(2)]
5840pub unsafe fn _mm256_maskz_slli_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
5841 static_assert_uimm_bits!(IMM8, 8);
5842 if IMM8 >= 16 {
5843 _mm256_setzero_si256()
5844 } else {
5845 let shf: u16x16 = simd_shl(lhs:a.as_u16x16(), rhs:u16x16::splat(IMM8 as u16));
5846 let zero: u16x16 = u16x16::splat(0);
5847 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5848 }
5849}
5850
5851/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5852///
5853/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_slli_epi16&expand=5293)
5854#[inline]
5855#[target_feature(enable = "avx512bw,avx512vl")]
5856#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5857#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5858#[rustc_legacy_const_generics(3)]
5859pub unsafe fn _mm_mask_slli_epi16<const IMM8: u32>(
5860 src: __m128i,
5861 k: __mmask8,
5862 a: __m128i,
5863) -> __m128i {
5864 static_assert_uimm_bits!(IMM8, 8);
5865 let shf: u16x8 = if IMM8 >= 16 {
5866 u16x8::splat(0)
5867 } else {
5868 simd_shl(lhs:a.as_u16x8(), rhs:u16x8::splat(IMM8 as u16))
5869 };
5870 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_u16x8()))
5871}
5872
5873/// Shift packed 16-bit integers in a left by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5874///
5875/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_slli_epi16&expand=5294)
5876#[inline]
5877#[target_feature(enable = "avx512bw,avx512vl")]
5878#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5879#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))]
5880#[rustc_legacy_const_generics(2)]
5881pub unsafe fn _mm_maskz_slli_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
5882 static_assert_uimm_bits!(IMM8, 8);
5883 if IMM8 >= 16 {
5884 _mm_setzero_si128()
5885 } else {
5886 let shf: u16x8 = simd_shl(lhs:a.as_u16x8(), rhs:u16x8::splat(IMM8 as u16));
5887 let zero: u16x8 = u16x8::splat(0);
5888 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5889 }
5890}
5891
5892/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
5893///
5894/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sllv_epi16&expand=5333)
5895#[inline]
5896#[target_feature(enable = "avx512bw")]
5897#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5898#[cfg_attr(test, assert_instr(vpsllvw))]
5899pub unsafe fn _mm512_sllv_epi16(a: __m512i, count: __m512i) -> __m512i {
5900 transmute(src:vpsllvw(a:a.as_i16x32(), b:count.as_i16x32()))
5901}
5902
5903/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5904///
5905/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sllv_epi16&expand=5331)
5906#[inline]
5907#[target_feature(enable = "avx512bw")]
5908#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5909#[cfg_attr(test, assert_instr(vpsllvw))]
5910pub unsafe fn _mm512_mask_sllv_epi16(
5911 src: __m512i,
5912 k: __mmask32,
5913 a: __m512i,
5914 count: __m512i,
5915) -> __m512i {
5916 let shf: i16x32 = _mm512_sllv_epi16(a, count).as_i16x32();
5917 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
5918}
5919
5920/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5921///
5922/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sllv_epi16&expand=5332)
5923#[inline]
5924#[target_feature(enable = "avx512bw")]
5925#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5926#[cfg_attr(test, assert_instr(vpsllvw))]
5927pub unsafe fn _mm512_maskz_sllv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
5928 let shf: i16x32 = _mm512_sllv_epi16(a, count).as_i16x32();
5929 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
5930 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5931}
5932
5933/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
5934///
5935/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_sllv_epi16&expand=5330)
5936#[inline]
5937#[target_feature(enable = "avx512bw,avx512vl")]
5938#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5939#[cfg_attr(test, assert_instr(vpsllvw))]
5940pub unsafe fn _mm256_sllv_epi16(a: __m256i, count: __m256i) -> __m256i {
5941 transmute(src:vpsllvw256(a:a.as_i16x16(), b:count.as_i16x16()))
5942}
5943
5944/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5945///
5946/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sllv_epi16&expand=5328)
5947#[inline]
5948#[target_feature(enable = "avx512bw,avx512vl")]
5949#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5950#[cfg_attr(test, assert_instr(vpsllvw))]
5951pub unsafe fn _mm256_mask_sllv_epi16(
5952 src: __m256i,
5953 k: __mmask16,
5954 a: __m256i,
5955 count: __m256i,
5956) -> __m256i {
5957 let shf: i16x16 = _mm256_sllv_epi16(a, count).as_i16x16();
5958 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
5959}
5960
5961/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
5962///
5963/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sllv_epi16&expand=5329)
5964#[inline]
5965#[target_feature(enable = "avx512bw,avx512vl")]
5966#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5967#[cfg_attr(test, assert_instr(vpsllvw))]
5968pub unsafe fn _mm256_maskz_sllv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
5969 let shf: i16x16 = _mm256_sllv_epi16(a, count).as_i16x16();
5970 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
5971 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
5972}
5973
5974/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
5975///
5976/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sllv_epi16&expand=5327)
5977#[inline]
5978#[target_feature(enable = "avx512bw,avx512vl")]
5979#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5980#[cfg_attr(test, assert_instr(vpsllvw))]
5981pub unsafe fn _mm_sllv_epi16(a: __m128i, count: __m128i) -> __m128i {
5982 transmute(src:vpsllvw128(a:a.as_i16x8(), b:count.as_i16x8()))
5983}
5984
5985/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
5986///
5987/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sllv_epi16&expand=5325)
5988#[inline]
5989#[target_feature(enable = "avx512bw,avx512vl")]
5990#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
5991#[cfg_attr(test, assert_instr(vpsllvw))]
5992pub unsafe fn _mm_mask_sllv_epi16(
5993 src: __m128i,
5994 k: __mmask8,
5995 a: __m128i,
5996 count: __m128i,
5997) -> __m128i {
5998 let shf: i16x8 = _mm_sllv_epi16(a, count).as_i16x8();
5999 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
6000}
6001
6002/// Shift packed 16-bit integers in a left by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6003///
6004/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sllv_epi16&expand=5326)
6005#[inline]
6006#[target_feature(enable = "avx512bw,avx512vl")]
6007#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6008#[cfg_attr(test, assert_instr(vpsllvw))]
6009pub unsafe fn _mm_maskz_sllv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6010 let shf: i16x8 = _mm_sllv_epi16(a, count).as_i16x8();
6011 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6012 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6013}
6014
6015/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst.
6016///
6017/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srl_epi16&expand=5483)
6018#[inline]
6019#[target_feature(enable = "avx512bw")]
6020#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6021#[cfg_attr(test, assert_instr(vpsrlw))]
6022pub unsafe fn _mm512_srl_epi16(a: __m512i, count: __m128i) -> __m512i {
6023 transmute(src:vpsrlw(a:a.as_i16x32(), count:count.as_i16x8()))
6024}
6025
6026/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6027///
6028/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srl_epi16&expand=5481)
6029#[inline]
6030#[target_feature(enable = "avx512bw")]
6031#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6032#[cfg_attr(test, assert_instr(vpsrlw))]
6033pub unsafe fn _mm512_mask_srl_epi16(
6034 src: __m512i,
6035 k: __mmask32,
6036 a: __m512i,
6037 count: __m128i,
6038) -> __m512i {
6039 let shf: i16x32 = _mm512_srl_epi16(a, count).as_i16x32();
6040 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
6041}
6042
6043/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6044///
6045/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srl_epi16&expand=5482)
6046#[inline]
6047#[target_feature(enable = "avx512bw")]
6048#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6049#[cfg_attr(test, assert_instr(vpsrlw))]
6050pub unsafe fn _mm512_maskz_srl_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i {
6051 let shf: i16x32 = _mm512_srl_epi16(a, count).as_i16x32();
6052 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6053 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6054}
6055
6056/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6057///
6058/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srl_epi16&expand=5478)
6059#[inline]
6060#[target_feature(enable = "avx512bw,avx512vl")]
6061#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6062#[cfg_attr(test, assert_instr(vpsrlw))]
6063pub unsafe fn _mm256_mask_srl_epi16(
6064 src: __m256i,
6065 k: __mmask16,
6066 a: __m256i,
6067 count: __m128i,
6068) -> __m256i {
6069 let shf: i16x16 = _mm256_srl_epi16(a, count).as_i16x16();
6070 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
6071}
6072
6073/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6074///
6075/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srl_epi16&expand=5479)
6076#[inline]
6077#[target_feature(enable = "avx512bw,avx512vl")]
6078#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6079#[cfg_attr(test, assert_instr(vpsrlw))]
6080pub unsafe fn _mm256_maskz_srl_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i {
6081 let shf: i16x16 = _mm256_srl_epi16(a, count).as_i16x16();
6082 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6083 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6084}
6085
6086/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6087///
6088/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srl_epi16&expand=5475)
6089#[inline]
6090#[target_feature(enable = "avx512bw,avx512vl")]
6091#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6092#[cfg_attr(test, assert_instr(vpsrlw))]
6093pub unsafe fn _mm_mask_srl_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6094 let shf: i16x8 = _mm_srl_epi16(a, count).as_i16x8();
6095 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
6096}
6097
6098/// Shift packed 16-bit integers in a right by count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6099///
6100/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srl_epi16&expand=5476)
6101#[inline]
6102#[target_feature(enable = "avx512bw,avx512vl")]
6103#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6104#[cfg_attr(test, assert_instr(vpsrlw))]
6105pub unsafe fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6106 let shf: i16x8 = _mm_srl_epi16(a, count).as_i16x8();
6107 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6108 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6109}
6110
6111/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst.
6112///
6113/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srli_epi16&expand=5513)
6114#[inline]
6115#[target_feature(enable = "avx512bw")]
6116#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6117#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6118#[rustc_legacy_const_generics(1)]
6119pub unsafe fn _mm512_srli_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
6120 static_assert_uimm_bits!(IMM8, 8);
6121 if IMM8 >= 16 {
6122 _mm512_setzero_si512()
6123 } else {
6124 transmute(src:simd_shr(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16)))
6125 }
6126}
6127
6128/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6129///
6130/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srli_epi16&expand=5511)
6131#[inline]
6132#[target_feature(enable = "avx512bw")]
6133#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6134#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6135#[rustc_legacy_const_generics(3)]
6136pub unsafe fn _mm512_mask_srli_epi16<const IMM8: u32>(
6137 src: __m512i,
6138 k: __mmask32,
6139 a: __m512i,
6140) -> __m512i {
6141 static_assert_uimm_bits!(IMM8, 8);
6142 let shf: u16x32 = if IMM8 >= 16 {
6143 u16x32::splat(0)
6144 } else {
6145 simd_shr(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16))
6146 };
6147 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_u16x32()))
6148}
6149
6150/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6151///
6152/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srli_epi16&expand=5512)
6153#[inline]
6154#[target_feature(enable = "avx512bw")]
6155#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6156#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6157#[rustc_legacy_const_generics(2)]
6158pub unsafe fn _mm512_maskz_srli_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
6159 static_assert_uimm_bits!(IMM8, 8);
6160 //imm8 should be u32, it seems the document to verify is incorrect
6161 if IMM8 >= 16 {
6162 _mm512_setzero_si512()
6163 } else {
6164 let shf: u16x32 = simd_shr(lhs:a.as_u16x32(), rhs:u16x32::splat(IMM8 as u16));
6165 let zero: u16x32 = u16x32::splat(0);
6166 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6167 }
6168}
6169
6170/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6171///
6172/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srli_epi16&expand=5508)
6173#[inline]
6174#[target_feature(enable = "avx512bw,avx512vl")]
6175#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6176#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6177#[rustc_legacy_const_generics(3)]
6178pub unsafe fn _mm256_mask_srli_epi16<const IMM8: i32>(
6179 src: __m256i,
6180 k: __mmask16,
6181 a: __m256i,
6182) -> __m256i {
6183 static_assert_uimm_bits!(IMM8, 8);
6184 let shf: __m256i = _mm256_srli_epi16::<IMM8>(a);
6185 transmute(src:simd_select_bitmask(m:k, yes:shf.as_i16x16(), no:src.as_i16x16()))
6186}
6187
6188/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6189///
6190/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srli_epi16&expand=5509)
6191#[inline]
6192#[target_feature(enable = "avx512bw,avx512vl")]
6193#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6194#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6195#[rustc_legacy_const_generics(2)]
6196pub unsafe fn _mm256_maskz_srli_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
6197 static_assert_uimm_bits!(IMM8, 8);
6198 let shf: __m256i = _mm256_srli_epi16::<IMM8>(a);
6199 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6200 transmute(src:simd_select_bitmask(m:k, yes:shf.as_i16x16(), no:zero))
6201}
6202
6203/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6204///
6205/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srli_epi16&expand=5505)
6206#[inline]
6207#[target_feature(enable = "avx512bw,avx512vl")]
6208#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6209#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6210#[rustc_legacy_const_generics(3)]
6211pub unsafe fn _mm_mask_srli_epi16<const IMM8: i32>(
6212 src: __m128i,
6213 k: __mmask8,
6214 a: __m128i,
6215) -> __m128i {
6216 static_assert_uimm_bits!(IMM8, 8);
6217 let shf: __m128i = _mm_srli_epi16::<IMM8>(a);
6218 transmute(src:simd_select_bitmask(m:k, yes:shf.as_i16x8(), no:src.as_i16x8()))
6219}
6220
6221/// Shift packed 16-bit integers in a right by imm8 while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6222///
6223/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srli_epi16&expand=5506)
6224#[inline]
6225#[target_feature(enable = "avx512bw,avx512vl")]
6226#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6227#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
6228#[rustc_legacy_const_generics(2)]
6229pub unsafe fn _mm_maskz_srli_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
6230 static_assert_uimm_bits!(IMM8, 8);
6231 let shf: __m128i = _mm_srli_epi16::<IMM8>(a);
6232 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6233 transmute(src:simd_select_bitmask(m:k, yes:shf.as_i16x8(), no:zero))
6234}
6235
6236/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
6237///
6238/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srlv_epi16&expand=5545)
6239#[inline]
6240#[target_feature(enable = "avx512bw")]
6241#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6242#[cfg_attr(test, assert_instr(vpsrlvw))]
6243pub unsafe fn _mm512_srlv_epi16(a: __m512i, count: __m512i) -> __m512i {
6244 transmute(src:vpsrlvw(a:a.as_i16x32(), b:count.as_i16x32()))
6245}
6246
6247/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6248///
6249/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srlv_epi16&expand=5543)
6250#[inline]
6251#[target_feature(enable = "avx512bw")]
6252#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6253#[cfg_attr(test, assert_instr(vpsrlvw))]
6254pub unsafe fn _mm512_mask_srlv_epi16(
6255 src: __m512i,
6256 k: __mmask32,
6257 a: __m512i,
6258 count: __m512i,
6259) -> __m512i {
6260 let shf: i16x32 = _mm512_srlv_epi16(a, count).as_i16x32();
6261 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
6262}
6263
6264/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6265///
6266/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srlv_epi16&expand=5544)
6267#[inline]
6268#[target_feature(enable = "avx512bw")]
6269#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6270#[cfg_attr(test, assert_instr(vpsrlvw))]
6271pub unsafe fn _mm512_maskz_srlv_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
6272 let shf: i16x32 = _mm512_srlv_epi16(a, count).as_i16x32();
6273 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6274 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6275}
6276
6277/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
6278///
6279/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srlv_epi16&expand=5542)
6280#[inline]
6281#[target_feature(enable = "avx512bw,avx512vl")]
6282#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6283#[cfg_attr(test, assert_instr(vpsrlvw))]
6284pub unsafe fn _mm256_srlv_epi16(a: __m256i, count: __m256i) -> __m256i {
6285 transmute(src:vpsrlvw256(a:a.as_i16x16(), b:count.as_i16x16()))
6286}
6287
6288/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6289///
6290/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srlv_epi16&expand=5540)
6291#[inline]
6292#[target_feature(enable = "avx512bw,avx512vl")]
6293#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6294#[cfg_attr(test, assert_instr(vpsrlvw))]
6295pub unsafe fn _mm256_mask_srlv_epi16(
6296 src: __m256i,
6297 k: __mmask16,
6298 a: __m256i,
6299 count: __m256i,
6300) -> __m256i {
6301 let shf: i16x16 = _mm256_srlv_epi16(a, count).as_i16x16();
6302 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
6303}
6304
6305/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6306///
6307/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srlv_epi16&expand=5541)
6308#[inline]
6309#[target_feature(enable = "avx512bw,avx512vl")]
6310#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6311#[cfg_attr(test, assert_instr(vpsrlvw))]
6312pub unsafe fn _mm256_maskz_srlv_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
6313 let shf: i16x16 = _mm256_srlv_epi16(a, count).as_i16x16();
6314 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6315 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6316}
6317
6318/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst.
6319///
6320/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srlv_epi16&expand=5539)
6321#[inline]
6322#[target_feature(enable = "avx512bw,avx512vl")]
6323#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6324#[cfg_attr(test, assert_instr(vpsrlvw))]
6325pub unsafe fn _mm_srlv_epi16(a: __m128i, count: __m128i) -> __m128i {
6326 transmute(src:vpsrlvw128(a:a.as_i16x8(), b:count.as_i16x8()))
6327}
6328
6329/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6330///
6331/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srlv_epi16&expand=5537)
6332#[inline]
6333#[target_feature(enable = "avx512bw,avx512vl")]
6334#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6335#[cfg_attr(test, assert_instr(vpsrlvw))]
6336pub unsafe fn _mm_mask_srlv_epi16(
6337 src: __m128i,
6338 k: __mmask8,
6339 a: __m128i,
6340 count: __m128i,
6341) -> __m128i {
6342 let shf: i16x8 = _mm_srlv_epi16(a, count).as_i16x8();
6343 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
6344}
6345
6346/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in zeros, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6347///
6348/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srlv_epi16&expand=5538)
6349#[inline]
6350#[target_feature(enable = "avx512bw,avx512vl")]
6351#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6352#[cfg_attr(test, assert_instr(vpsrlvw))]
6353pub unsafe fn _mm_maskz_srlv_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6354 let shf: i16x8 = _mm_srlv_epi16(a, count).as_i16x8();
6355 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6356 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6357}
6358
6359/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst.
6360///
6361/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sra_epi16&expand=5398)
6362#[inline]
6363#[target_feature(enable = "avx512bw")]
6364#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6365#[cfg_attr(test, assert_instr(vpsraw))]
6366pub unsafe fn _mm512_sra_epi16(a: __m512i, count: __m128i) -> __m512i {
6367 transmute(src:vpsraw(a:a.as_i16x32(), count:count.as_i16x8()))
6368}
6369
6370/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6371///
6372/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_sra_epi16&expand=5396)
6373#[inline]
6374#[target_feature(enable = "avx512bw")]
6375#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6376#[cfg_attr(test, assert_instr(vpsraw))]
6377pub unsafe fn _mm512_mask_sra_epi16(
6378 src: __m512i,
6379 k: __mmask32,
6380 a: __m512i,
6381 count: __m128i,
6382) -> __m512i {
6383 let shf: i16x32 = _mm512_sra_epi16(a, count).as_i16x32();
6384 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
6385}
6386
6387/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6388///
6389/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_sra_epi16&expand=5397)
6390#[inline]
6391#[target_feature(enable = "avx512bw")]
6392#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6393#[cfg_attr(test, assert_instr(vpsraw))]
6394pub unsafe fn _mm512_maskz_sra_epi16(k: __mmask32, a: __m512i, count: __m128i) -> __m512i {
6395 let shf: i16x32 = _mm512_sra_epi16(a, count).as_i16x32();
6396 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6397 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6398}
6399
6400/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6401///
6402/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_sra_epi16&expand=5393)
6403#[inline]
6404#[target_feature(enable = "avx512bw,avx512vl")]
6405#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6406#[cfg_attr(test, assert_instr(vpsraw))]
6407pub unsafe fn _mm256_mask_sra_epi16(
6408 src: __m256i,
6409 k: __mmask16,
6410 a: __m256i,
6411 count: __m128i,
6412) -> __m256i {
6413 let shf: i16x16 = _mm256_sra_epi16(a, count).as_i16x16();
6414 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
6415}
6416
6417/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6418///
6419/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_sra_epi16&expand=5394)
6420#[inline]
6421#[target_feature(enable = "avx512bw,avx512vl")]
6422#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6423#[cfg_attr(test, assert_instr(vpsraw))]
6424pub unsafe fn _mm256_maskz_sra_epi16(k: __mmask16, a: __m256i, count: __m128i) -> __m256i {
6425 let shf: i16x16 = _mm256_sra_epi16(a, count).as_i16x16();
6426 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6427 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6428}
6429
6430/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6431///
6432/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_sra_epi16&expand=5390)
6433#[inline]
6434#[target_feature(enable = "avx512bw,avx512vl")]
6435#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6436#[cfg_attr(test, assert_instr(vpsraw))]
6437pub unsafe fn _mm_mask_sra_epi16(src: __m128i, k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6438 let shf: i16x8 = _mm_sra_epi16(a, count).as_i16x8();
6439 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
6440}
6441
6442/// Shift packed 16-bit integers in a right by count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6443///
6444/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_sra_epi16&expand=5391)
6445#[inline]
6446#[target_feature(enable = "avx512bw,avx512vl")]
6447#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6448#[cfg_attr(test, assert_instr(vpsraw))]
6449pub unsafe fn _mm_maskz_sra_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6450 let shf: i16x8 = _mm_sra_epi16(a, count).as_i16x8();
6451 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6452 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6453}
6454
6455/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst.
6456///
6457/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srai_epi16&expand=5427)
6458#[inline]
6459#[target_feature(enable = "avx512bw")]
6460#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6461#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6462#[rustc_legacy_const_generics(1)]
6463pub unsafe fn _mm512_srai_epi16<const IMM8: u32>(a: __m512i) -> __m512i {
6464 static_assert_uimm_bits!(IMM8, 8);
6465 transmute(src:simd_shr(lhs:a.as_i16x32(), rhs:i16x32::splat(IMM8.min(15) as i16)))
6466}
6467
6468/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6469///
6470/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srai_epi16&expand=5425)
6471#[inline]
6472#[target_feature(enable = "avx512bw")]
6473#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6474#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6475#[rustc_legacy_const_generics(3)]
6476pub unsafe fn _mm512_mask_srai_epi16<const IMM8: u32>(
6477 src: __m512i,
6478 k: __mmask32,
6479 a: __m512i,
6480) -> __m512i {
6481 static_assert_uimm_bits!(IMM8, 8);
6482 let shf: i16x32 = simd_shr(lhs:a.as_i16x32(), rhs:i16x32::splat(IMM8.min(15) as i16));
6483 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
6484}
6485
6486/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6487///
6488/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srai_epi16&expand=5426)
6489#[inline]
6490#[target_feature(enable = "avx512bw")]
6491#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6492#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6493#[rustc_legacy_const_generics(2)]
6494pub unsafe fn _mm512_maskz_srai_epi16<const IMM8: u32>(k: __mmask32, a: __m512i) -> __m512i {
6495 static_assert_uimm_bits!(IMM8, 8);
6496 let shf: i16x32 = simd_shr(lhs:a.as_i16x32(), rhs:i16x32::splat(IMM8.min(15) as i16));
6497 let zero: i16x32 = i16x32::splat(0);
6498 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6499}
6500
6501/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6502///
6503/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srai_epi16&expand=5422)
6504#[inline]
6505#[target_feature(enable = "avx512bw,avx512vl")]
6506#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6507#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6508#[rustc_legacy_const_generics(3)]
6509pub unsafe fn _mm256_mask_srai_epi16<const IMM8: u32>(
6510 src: __m256i,
6511 k: __mmask16,
6512 a: __m256i,
6513) -> __m256i {
6514 static_assert_uimm_bits!(IMM8, 8);
6515 let r: i16x16 = simd_shr(lhs:a.as_i16x16(), rhs:i16x16::splat(IMM8.min(15) as i16));
6516 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i16x16()))
6517}
6518
6519/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6520///
6521/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srai_epi16&expand=5423)
6522#[inline]
6523#[target_feature(enable = "avx512bw,avx512vl")]
6524#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6525#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6526#[rustc_legacy_const_generics(2)]
6527pub unsafe fn _mm256_maskz_srai_epi16<const IMM8: u32>(k: __mmask16, a: __m256i) -> __m256i {
6528 static_assert_uimm_bits!(IMM8, 8);
6529 let r: i16x16 = simd_shr(lhs:a.as_i16x16(), rhs:i16x16::splat(IMM8.min(15) as i16));
6530 let zero: i16x16 = i16x16::splat(0);
6531 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
6532}
6533
6534/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6535///
6536/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srai_epi16&expand=5419)
6537#[inline]
6538#[target_feature(enable = "avx512bw,avx512vl")]
6539#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6540#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6541#[rustc_legacy_const_generics(3)]
6542pub unsafe fn _mm_mask_srai_epi16<const IMM8: u32>(
6543 src: __m128i,
6544 k: __mmask8,
6545 a: __m128i,
6546) -> __m128i {
6547 static_assert_uimm_bits!(IMM8, 8);
6548 let r: i16x8 = simd_shr(lhs:a.as_i16x8(), rhs:i16x8::splat(IMM8.min(15) as i16));
6549 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i16x8()))
6550}
6551
6552/// Shift packed 16-bit integers in a right by imm8 while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6553///
6554/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srai_epi16&expand=5420)
6555#[inline]
6556#[target_feature(enable = "avx512bw,avx512vl")]
6557#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6558#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))]
6559#[rustc_legacy_const_generics(2)]
6560pub unsafe fn _mm_maskz_srai_epi16<const IMM8: u32>(k: __mmask8, a: __m128i) -> __m128i {
6561 static_assert_uimm_bits!(IMM8, 8);
6562 let r: i16x8 = simd_shr(lhs:a.as_i16x8(), rhs:i16x8::splat(IMM8.min(15) as i16));
6563 let zero: i16x8 = i16x8::splat(0);
6564 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
6565}
6566
6567/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst.
6568///
6569/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_srav_epi16&expand=5456)
6570#[inline]
6571#[target_feature(enable = "avx512bw")]
6572#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6573#[cfg_attr(test, assert_instr(vpsravw))]
6574pub unsafe fn _mm512_srav_epi16(a: __m512i, count: __m512i) -> __m512i {
6575 transmute(src:vpsravw(a:a.as_i16x32(), count:count.as_i16x32()))
6576}
6577
6578/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6579///
6580/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_srav_epi16&expand=5454)
6581#[inline]
6582#[target_feature(enable = "avx512bw")]
6583#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6584#[cfg_attr(test, assert_instr(vpsravw))]
6585pub unsafe fn _mm512_mask_srav_epi16(
6586 src: __m512i,
6587 k: __mmask32,
6588 a: __m512i,
6589 count: __m512i,
6590) -> __m512i {
6591 let shf: i16x32 = _mm512_srav_epi16(a, count).as_i16x32();
6592 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x32()))
6593}
6594
6595/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6596///
6597/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_srav_epi16&expand=5455)
6598#[inline]
6599#[target_feature(enable = "avx512bw")]
6600#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6601#[cfg_attr(test, assert_instr(vpsravw))]
6602pub unsafe fn _mm512_maskz_srav_epi16(k: __mmask32, a: __m512i, count: __m512i) -> __m512i {
6603 let shf: i16x32 = _mm512_srav_epi16(a, count).as_i16x32();
6604 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6605 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6606}
6607
6608/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst.
6609///
6610/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_srav_epi16&expand=5453)
6611#[inline]
6612#[target_feature(enable = "avx512bw,avx512vl")]
6613#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6614#[cfg_attr(test, assert_instr(vpsravw))]
6615pub unsafe fn _mm256_srav_epi16(a: __m256i, count: __m256i) -> __m256i {
6616 transmute(src:vpsravw256(a:a.as_i16x16(), count:count.as_i16x16()))
6617}
6618
6619/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6620///
6621/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_srav_epi16&expand=5451)
6622#[inline]
6623#[target_feature(enable = "avx512bw,avx512vl")]
6624#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6625#[cfg_attr(test, assert_instr(vpsravw))]
6626pub unsafe fn _mm256_mask_srav_epi16(
6627 src: __m256i,
6628 k: __mmask16,
6629 a: __m256i,
6630 count: __m256i,
6631) -> __m256i {
6632 let shf: i16x16 = _mm256_srav_epi16(a, count).as_i16x16();
6633 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x16()))
6634}
6635
6636/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6637///
6638/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_srav_epi16&expand=5452)
6639#[inline]
6640#[target_feature(enable = "avx512bw,avx512vl")]
6641#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6642#[cfg_attr(test, assert_instr(vpsravw))]
6643pub unsafe fn _mm256_maskz_srav_epi16(k: __mmask16, a: __m256i, count: __m256i) -> __m256i {
6644 let shf: i16x16 = _mm256_srav_epi16(a, count).as_i16x16();
6645 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6646 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6647}
6648
6649/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst.
6650///
6651/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srav_epi16&expand=5450)
6652#[inline]
6653#[target_feature(enable = "avx512bw,avx512vl")]
6654#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6655#[cfg_attr(test, assert_instr(vpsravw))]
6656pub unsafe fn _mm_srav_epi16(a: __m128i, count: __m128i) -> __m128i {
6657 transmute(src:vpsravw128(a:a.as_i16x8(), count:count.as_i16x8()))
6658}
6659
6660/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6661///
6662/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_srav_epi16&expand=5448)
6663#[inline]
6664#[target_feature(enable = "avx512bw,avx512vl")]
6665#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6666#[cfg_attr(test, assert_instr(vpsravw))]
6667pub unsafe fn _mm_mask_srav_epi16(
6668 src: __m128i,
6669 k: __mmask8,
6670 a: __m128i,
6671 count: __m128i,
6672) -> __m128i {
6673 let shf: i16x8 = _mm_srav_epi16(a, count).as_i16x8();
6674 transmute(src:simd_select_bitmask(m:k, yes:shf, no:src.as_i16x8()))
6675}
6676
6677/// Shift packed 16-bit integers in a right by the amount specified by the corresponding element in count while shifting in sign bits, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6678///
6679/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_srav_epi16&expand=5449)
6680#[inline]
6681#[target_feature(enable = "avx512bw,avx512vl")]
6682#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6683#[cfg_attr(test, assert_instr(vpsravw))]
6684pub unsafe fn _mm_maskz_srav_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __m128i {
6685 let shf: i16x8 = _mm_srav_epi16(a, count).as_i16x8();
6686 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6687 transmute(src:simd_select_bitmask(m:k, yes:shf, no:zero))
6688}
6689
6690/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
6691///
6692/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutex2var_epi16&expand=4226)
6693#[inline]
6694#[target_feature(enable = "avx512bw")]
6695#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6696#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6697pub unsafe fn _mm512_permutex2var_epi16(a: __m512i, idx: __m512i, b: __m512i) -> __m512i {
6698 transmute(src:vpermi2w(a:a.as_i16x32(), idx:idx.as_i16x32(), b:b.as_i16x32()))
6699}
6700
6701/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
6702///
6703/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutex2var_epi16&expand=4223)
6704#[inline]
6705#[target_feature(enable = "avx512bw")]
6706#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6707#[cfg_attr(test, assert_instr(vpermt2w))]
6708pub unsafe fn _mm512_mask_permutex2var_epi16(
6709 a: __m512i,
6710 k: __mmask32,
6711 idx: __m512i,
6712 b: __m512i,
6713) -> __m512i {
6714 let permute: i16x32 = _mm512_permutex2var_epi16(a, idx, b).as_i16x32();
6715 transmute(src:simd_select_bitmask(m:k, yes:permute, no:a.as_i16x32()))
6716}
6717
6718/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6719///
6720/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutex2var_epi16&expand=4225)
6721#[inline]
6722#[target_feature(enable = "avx512bw")]
6723#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6724#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6725pub unsafe fn _mm512_maskz_permutex2var_epi16(
6726 k: __mmask32,
6727 a: __m512i,
6728 idx: __m512i,
6729 b: __m512i,
6730) -> __m512i {
6731 let permute: i16x32 = _mm512_permutex2var_epi16(a, idx, b).as_i16x32();
6732 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6733 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
6734}
6735
6736/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
6737///
6738/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask2_permutex2var_epi16&expand=4224)
6739#[inline]
6740#[target_feature(enable = "avx512bw")]
6741#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6742#[cfg_attr(test, assert_instr(vpermi2w))]
6743pub unsafe fn _mm512_mask2_permutex2var_epi16(
6744 a: __m512i,
6745 idx: __m512i,
6746 k: __mmask32,
6747 b: __m512i,
6748) -> __m512i {
6749 let permute: i16x32 = _mm512_permutex2var_epi16(a, idx, b).as_i16x32();
6750 transmute(src:simd_select_bitmask(m:k, yes:permute, no:idx.as_i16x32()))
6751}
6752
6753/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
6754///
6755/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutex2var_epi16&expand=4222)
6756#[inline]
6757#[target_feature(enable = "avx512bw,avx512vl")]
6758#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6759#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6760pub unsafe fn _mm256_permutex2var_epi16(a: __m256i, idx: __m256i, b: __m256i) -> __m256i {
6761 transmute(src:vpermi2w256(a:a.as_i16x16(), idx:idx.as_i16x16(), b:b.as_i16x16()))
6762}
6763
6764/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
6765///
6766/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutex2var_epi16&expand=4219)
6767#[inline]
6768#[target_feature(enable = "avx512bw,avx512vl")]
6769#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6770#[cfg_attr(test, assert_instr(vpermt2w))]
6771pub unsafe fn _mm256_mask_permutex2var_epi16(
6772 a: __m256i,
6773 k: __mmask16,
6774 idx: __m256i,
6775 b: __m256i,
6776) -> __m256i {
6777 let permute: i16x16 = _mm256_permutex2var_epi16(a, idx, b).as_i16x16();
6778 transmute(src:simd_select_bitmask(m:k, yes:permute, no:a.as_i16x16()))
6779}
6780
6781/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6782///
6783/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutex2var_epi16&expand=4221)
6784#[inline]
6785#[target_feature(enable = "avx512bw,avx512vl")]
6786#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6787#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6788pub unsafe fn _mm256_maskz_permutex2var_epi16(
6789 k: __mmask16,
6790 a: __m256i,
6791 idx: __m256i,
6792 b: __m256i,
6793) -> __m256i {
6794 let permute: i16x16 = _mm256_permutex2var_epi16(a, idx, b).as_i16x16();
6795 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6796 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
6797}
6798
6799/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
6800///
6801/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask2_permutex2var_epi16&expand=4220)
6802#[inline]
6803#[target_feature(enable = "avx512bw,avx512vl")]
6804#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6805#[cfg_attr(test, assert_instr(vpermi2w))]
6806pub unsafe fn _mm256_mask2_permutex2var_epi16(
6807 a: __m256i,
6808 idx: __m256i,
6809 k: __mmask16,
6810 b: __m256i,
6811) -> __m256i {
6812 let permute: i16x16 = _mm256_permutex2var_epi16(a, idx, b).as_i16x16();
6813 transmute(src:simd_select_bitmask(m:k, yes:permute, no:idx.as_i16x16()))
6814}
6815
6816/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst.
6817///
6818/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutex2var_epi16&expand=4218)
6819#[inline]
6820#[target_feature(enable = "avx512bw,avx512vl")]
6821#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6822#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6823pub unsafe fn _mm_permutex2var_epi16(a: __m128i, idx: __m128i, b: __m128i) -> __m128i {
6824 transmute(src:vpermi2w128(a:a.as_i16x8(), idx:idx.as_i16x8(), b:b.as_i16x8()))
6825}
6826
6827/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from a when the corresponding mask bit is not set).
6828///
6829/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutex2var_epi16&expand=4215)
6830#[inline]
6831#[target_feature(enable = "avx512bw,avx512vl")]
6832#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6833#[cfg_attr(test, assert_instr(vpermt2w))]
6834pub unsafe fn _mm_mask_permutex2var_epi16(
6835 a: __m128i,
6836 k: __mmask8,
6837 idx: __m128i,
6838 b: __m128i,
6839) -> __m128i {
6840 let permute: i16x8 = _mm_permutex2var_epi16(a, idx, b).as_i16x8();
6841 transmute(src:simd_select_bitmask(m:k, yes:permute, no:a.as_i16x8()))
6842}
6843
6844/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6845///
6846/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutex2var_epi16&expand=4217)
6847#[inline]
6848#[target_feature(enable = "avx512bw,avx512vl")]
6849#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6850#[cfg_attr(test, assert_instr(vperm))] //vpermi2w or vpermt2w
6851pub unsafe fn _mm_maskz_permutex2var_epi16(
6852 k: __mmask8,
6853 a: __m128i,
6854 idx: __m128i,
6855 b: __m128i,
6856) -> __m128i {
6857 let permute: i16x8 = _mm_permutex2var_epi16(a, idx, b).as_i16x8();
6858 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6859 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
6860}
6861
6862/// Shuffle 16-bit integers in a and b across lanes using the corresponding selector and index in idx, and store the results in dst using writemask k (elements are copied from idx when the corresponding mask bit is not set).
6863///
6864/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask2_permutex2var_epi16&expand=4216)
6865#[inline]
6866#[target_feature(enable = "avx512bw,avx512vl")]
6867#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6868#[cfg_attr(test, assert_instr(vpermi2w))]
6869pub unsafe fn _mm_mask2_permutex2var_epi16(
6870 a: __m128i,
6871 idx: __m128i,
6872 k: __mmask8,
6873 b: __m128i,
6874) -> __m128i {
6875 let permute: i16x8 = _mm_permutex2var_epi16(a, idx, b).as_i16x8();
6876 transmute(src:simd_select_bitmask(m:k, yes:permute, no:idx.as_i16x8()))
6877}
6878
6879/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
6880///
6881/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_permutexvar_epi16&expand=4295)
6882#[inline]
6883#[target_feature(enable = "avx512bw")]
6884#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6885#[cfg_attr(test, assert_instr(vpermw))]
6886pub unsafe fn _mm512_permutexvar_epi16(idx: __m512i, a: __m512i) -> __m512i {
6887 transmute(src:vpermw(a:a.as_i16x32(), idx:idx.as_i16x32()))
6888}
6889
6890/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6891///
6892/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_permutexvar_epi16&expand=4293)
6893#[inline]
6894#[target_feature(enable = "avx512bw")]
6895#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6896#[cfg_attr(test, assert_instr(vpermw))]
6897pub unsafe fn _mm512_mask_permutexvar_epi16(
6898 src: __m512i,
6899 k: __mmask32,
6900 idx: __m512i,
6901 a: __m512i,
6902) -> __m512i {
6903 let permute: i16x32 = _mm512_permutexvar_epi16(idx, a).as_i16x32();
6904 transmute(src:simd_select_bitmask(m:k, yes:permute, no:src.as_i16x32()))
6905}
6906
6907/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6908///
6909/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_permutexvar_epi16&expand=4294)
6910#[inline]
6911#[target_feature(enable = "avx512bw")]
6912#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6913#[cfg_attr(test, assert_instr(vpermw))]
6914pub unsafe fn _mm512_maskz_permutexvar_epi16(k: __mmask32, idx: __m512i, a: __m512i) -> __m512i {
6915 let permute: i16x32 = _mm512_permutexvar_epi16(idx, a).as_i16x32();
6916 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
6917 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
6918}
6919
6920/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
6921///
6922/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permutexvar_epi16&expand=4292)
6923#[inline]
6924#[target_feature(enable = "avx512bw,avx512vl")]
6925#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6926#[cfg_attr(test, assert_instr(vpermw))]
6927pub unsafe fn _mm256_permutexvar_epi16(idx: __m256i, a: __m256i) -> __m256i {
6928 transmute(src:vpermw256(a:a.as_i16x16(), idx:idx.as_i16x16()))
6929}
6930
6931/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6932///
6933/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_permutexvar_epi16&expand=4290)
6934#[inline]
6935#[target_feature(enable = "avx512bw,avx512vl")]
6936#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6937#[cfg_attr(test, assert_instr(vpermw))]
6938pub unsafe fn _mm256_mask_permutexvar_epi16(
6939 src: __m256i,
6940 k: __mmask16,
6941 idx: __m256i,
6942 a: __m256i,
6943) -> __m256i {
6944 let permute: i16x16 = _mm256_permutexvar_epi16(idx, a).as_i16x16();
6945 transmute(src:simd_select_bitmask(m:k, yes:permute, no:src.as_i16x16()))
6946}
6947
6948/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6949///
6950/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_permutexvar_epi16&expand=4291)
6951#[inline]
6952#[target_feature(enable = "avx512bw,avx512vl")]
6953#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6954#[cfg_attr(test, assert_instr(vpermw))]
6955pub unsafe fn _mm256_maskz_permutexvar_epi16(k: __mmask16, idx: __m256i, a: __m256i) -> __m256i {
6956 let permute: i16x16 = _mm256_permutexvar_epi16(idx, a).as_i16x16();
6957 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
6958 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
6959}
6960
6961/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst.
6962///
6963/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_permutexvar_epi16&expand=4289)
6964#[inline]
6965#[target_feature(enable = "avx512bw,avx512vl")]
6966#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6967#[cfg_attr(test, assert_instr(vpermw))]
6968pub unsafe fn _mm_permutexvar_epi16(idx: __m128i, a: __m128i) -> __m128i {
6969 transmute(src:vpermw128(a:a.as_i16x8(), idx:idx.as_i16x8()))
6970}
6971
6972/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
6973///
6974/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_permutexvar_epi16&expand=4287)
6975#[inline]
6976#[target_feature(enable = "avx512bw,avx512vl")]
6977#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6978#[cfg_attr(test, assert_instr(vpermw))]
6979pub unsafe fn _mm_mask_permutexvar_epi16(
6980 src: __m128i,
6981 k: __mmask8,
6982 idx: __m128i,
6983 a: __m128i,
6984) -> __m128i {
6985 let permute: i16x8 = _mm_permutexvar_epi16(idx, a).as_i16x8();
6986 transmute(src:simd_select_bitmask(m:k, yes:permute, no:src.as_i16x8()))
6987}
6988
6989/// Shuffle 16-bit integers in a across lanes using the corresponding index in idx, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
6990///
6991/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_permutexvar_epi16&expand=4288)
6992#[inline]
6993#[target_feature(enable = "avx512bw,avx512vl")]
6994#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
6995#[cfg_attr(test, assert_instr(vpermw))]
6996pub unsafe fn _mm_maskz_permutexvar_epi16(k: __mmask8, idx: __m128i, a: __m128i) -> __m128i {
6997 let permute: i16x8 = _mm_permutexvar_epi16(idx, a).as_i16x8();
6998 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
6999 transmute(src:simd_select_bitmask(m:k, yes:permute, no:zero))
7000}
7001
7002/// Blend packed 16-bit integers from a and b using control mask k, and store the results in dst.
7003///
7004/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi16&expand=430)
7005#[inline]
7006#[target_feature(enable = "avx512bw")]
7007#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7008#[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
7009pub unsafe fn _mm512_mask_blend_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
7010 transmute(src:simd_select_bitmask(m:k, yes:b.as_i16x32(), no:a.as_i16x32()))
7011}
7012
7013/// Blend packed 16-bit integers from a and b using control mask k, and store the results in dst.
7014///
7015/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi16&expand=429)
7016#[inline]
7017#[target_feature(enable = "avx512bw,avx512vl")]
7018#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7019#[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
7020pub unsafe fn _mm256_mask_blend_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
7021 transmute(src:simd_select_bitmask(m:k, yes:b.as_i16x16(), no:a.as_i16x16()))
7022}
7023
7024/// Blend packed 16-bit integers from a and b using control mask k, and store the results in dst.
7025///
7026/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi16&expand=427)
7027#[inline]
7028#[target_feature(enable = "avx512bw,avx512vl")]
7029#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7030#[cfg_attr(test, assert_instr(vmovdqu16))] //should be vpblendmw
7031pub unsafe fn _mm_mask_blend_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
7032 transmute(src:simd_select_bitmask(m:k, yes:b.as_i16x8(), no:a.as_i16x8()))
7033}
7034
7035/// Blend packed 8-bit integers from a and b using control mask k, and store the results in dst.
7036///
7037/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_blend_epi8&expand=441)
7038#[inline]
7039#[target_feature(enable = "avx512bw")]
7040#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7041#[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
7042pub unsafe fn _mm512_mask_blend_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
7043 transmute(src:simd_select_bitmask(m:k, yes:b.as_i8x64(), no:a.as_i8x64()))
7044}
7045
7046/// Blend packed 8-bit integers from a and b using control mask k, and store the results in dst.
7047///
7048/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_blend_epi8&expand=440)
7049#[inline]
7050#[target_feature(enable = "avx512bw,avx512vl")]
7051#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7052#[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
7053pub unsafe fn _mm256_mask_blend_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
7054 transmute(src:simd_select_bitmask(m:k, yes:b.as_i8x32(), no:a.as_i8x32()))
7055}
7056
7057/// Blend packed 8-bit integers from a and b using control mask k, and store the results in dst.
7058///
7059/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_blend_epi8&expand=439)
7060#[inline]
7061#[target_feature(enable = "avx512bw,avx512vl")]
7062#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7063#[cfg_attr(test, assert_instr(vmovdqu8))] //should be vpblendmb
7064pub unsafe fn _mm_mask_blend_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
7065 transmute(src:simd_select_bitmask(m:k, yes:b.as_i8x16(), no:a.as_i8x16()))
7066}
7067
7068/// Broadcast the low packed 16-bit integer from a to all elements of dst.
7069///
7070/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastw_epi16&expand=587)
7071#[inline]
7072#[target_feature(enable = "avx512bw")]
7073#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7074#[cfg_attr(test, assert_instr(vpbroadcastw))]
7075pub unsafe fn _mm512_broadcastw_epi16(a: __m128i) -> __m512i {
7076 let a: i16x32 = _mm512_castsi128_si512(a).as_i16x32();
7077 let ret: i16x32 = simd_shuffle!(
7078 a,
7079 a,
7080 [
7081 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7082 0, 0, 0,
7083 ],
7084 );
7085 transmute(src:ret)
7086}
7087
7088/// Broadcast the low packed 16-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7089///
7090/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastw_epi16&expand=588)
7091#[inline]
7092#[target_feature(enable = "avx512bw")]
7093#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7094#[cfg_attr(test, assert_instr(vpbroadcastw))]
7095pub unsafe fn _mm512_mask_broadcastw_epi16(src: __m512i, k: __mmask32, a: __m128i) -> __m512i {
7096 let broadcast: i16x32 = _mm512_broadcastw_epi16(a).as_i16x32();
7097 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i16x32()))
7098}
7099
7100/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7101///
7102/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastw_epi16&expand=589)
7103#[inline]
7104#[target_feature(enable = "avx512bw")]
7105#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7106#[cfg_attr(test, assert_instr(vpbroadcastw))]
7107pub unsafe fn _mm512_maskz_broadcastw_epi16(k: __mmask32, a: __m128i) -> __m512i {
7108 let broadcast: i16x32 = _mm512_broadcastw_epi16(a).as_i16x32();
7109 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
7110 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7111}
7112
7113/// Broadcast the low packed 16-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7114///
7115/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastw_epi16&expand=585)
7116#[inline]
7117#[target_feature(enable = "avx512bw,avx512vl")]
7118#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7119#[cfg_attr(test, assert_instr(vpbroadcastw))]
7120pub unsafe fn _mm256_mask_broadcastw_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
7121 let broadcast: i16x16 = _mm256_broadcastw_epi16(a).as_i16x16();
7122 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i16x16()))
7123}
7124
7125/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7126///
7127/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastw_epi16&expand=586)
7128#[inline]
7129#[target_feature(enable = "avx512bw,avx512vl")]
7130#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7131#[cfg_attr(test, assert_instr(vpbroadcastw))]
7132pub unsafe fn _mm256_maskz_broadcastw_epi16(k: __mmask16, a: __m128i) -> __m256i {
7133 let broadcast: i16x16 = _mm256_broadcastw_epi16(a).as_i16x16();
7134 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
7135 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7136}
7137
7138/// Broadcast the low packed 16-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7139///
7140/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastw_epi16&expand=582)
7141#[inline]
7142#[target_feature(enable = "avx512bw,avx512vl")]
7143#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7144#[cfg_attr(test, assert_instr(vpbroadcastw))]
7145pub unsafe fn _mm_mask_broadcastw_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
7146 let broadcast: i16x8 = _mm_broadcastw_epi16(a).as_i16x8();
7147 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i16x8()))
7148}
7149
7150/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7151///
7152/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastw_epi16&expand=583)
7153#[inline]
7154#[target_feature(enable = "avx512bw,avx512vl")]
7155#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7156#[cfg_attr(test, assert_instr(vpbroadcastw))]
7157pub unsafe fn _mm_maskz_broadcastw_epi16(k: __mmask8, a: __m128i) -> __m128i {
7158 let broadcast: i16x8 = _mm_broadcastw_epi16(a).as_i16x8();
7159 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
7160 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7161}
7162
7163/// Broadcast the low packed 8-bit integer from a to all elements of dst.
7164///
7165/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_broadcastb_epi8&expand=536)
7166#[inline]
7167#[target_feature(enable = "avx512bw")]
7168#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7169#[cfg_attr(test, assert_instr(vpbroadcastb))]
7170pub unsafe fn _mm512_broadcastb_epi8(a: __m128i) -> __m512i {
7171 let a: i8x64 = _mm512_castsi128_si512(a).as_i8x64();
7172 let ret: i8x64 = simd_shuffle!(
7173 a,
7174 a,
7175 [
7176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7177 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7178 0, 0, 0, 0, 0, 0,
7179 ],
7180 );
7181 transmute(src:ret)
7182}
7183
7184/// Broadcast the low packed 8-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7185///
7186/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_broadcastb_epi8&expand=537)
7187#[inline]
7188#[target_feature(enable = "avx512bw")]
7189#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7190#[cfg_attr(test, assert_instr(vpbroadcastb))]
7191pub unsafe fn _mm512_mask_broadcastb_epi8(src: __m512i, k: __mmask64, a: __m128i) -> __m512i {
7192 let broadcast: i8x64 = _mm512_broadcastb_epi8(a).as_i8x64();
7193 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i8x64()))
7194}
7195
7196/// Broadcast the low packed 8-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7197///
7198/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_broadcastb_epi8&expand=538)
7199#[inline]
7200#[target_feature(enable = "avx512bw")]
7201#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7202#[cfg_attr(test, assert_instr(vpbroadcastb))]
7203pub unsafe fn _mm512_maskz_broadcastb_epi8(k: __mmask64, a: __m128i) -> __m512i {
7204 let broadcast: i8x64 = _mm512_broadcastb_epi8(a).as_i8x64();
7205 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
7206 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7207}
7208
7209/// Broadcast the low packed 8-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7210///
7211/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_broadcastb_epi8&expand=534)
7212#[inline]
7213#[target_feature(enable = "avx512bw,avx512vl")]
7214#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7215#[cfg_attr(test, assert_instr(vpbroadcastb))]
7216pub unsafe fn _mm256_mask_broadcastb_epi8(src: __m256i, k: __mmask32, a: __m128i) -> __m256i {
7217 let broadcast: i8x32 = _mm256_broadcastb_epi8(a).as_i8x32();
7218 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i8x32()))
7219}
7220
7221/// Broadcast the low packed 8-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7222///
7223/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_broadcastb_epi8&expand=535)
7224#[inline]
7225#[target_feature(enable = "avx512bw,avx512vl")]
7226#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7227#[cfg_attr(test, assert_instr(vpbroadcastb))]
7228pub unsafe fn _mm256_maskz_broadcastb_epi8(k: __mmask32, a: __m128i) -> __m256i {
7229 let broadcast: i8x32 = _mm256_broadcastb_epi8(a).as_i8x32();
7230 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
7231 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7232}
7233
7234/// Broadcast the low packed 8-bit integer from a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7235///
7236/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_broadcastb_epi8&expand=531)
7237#[inline]
7238#[target_feature(enable = "avx512bw,avx512vl")]
7239#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7240#[cfg_attr(test, assert_instr(vpbroadcastb))]
7241pub unsafe fn _mm_mask_broadcastb_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
7242 let broadcast: i8x16 = _mm_broadcastb_epi8(a).as_i8x16();
7243 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:src.as_i8x16()))
7244}
7245
7246/// Broadcast the low packed 8-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7247///
7248/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_broadcastb_epi8&expand=532)
7249#[inline]
7250#[target_feature(enable = "avx512bw,avx512vl")]
7251#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7252#[cfg_attr(test, assert_instr(vpbroadcastb))]
7253pub unsafe fn _mm_maskz_broadcastb_epi8(k: __mmask16, a: __m128i) -> __m128i {
7254 let broadcast: i8x16 = _mm_broadcastb_epi8(a).as_i8x16();
7255 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
7256 transmute(src:simd_select_bitmask(m:k, yes:broadcast, no:zero))
7257}
7258
7259/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst.
7260///
7261/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi16&expand=6012)
7262#[inline]
7263#[target_feature(enable = "avx512bw")]
7264#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7265#[cfg_attr(test, assert_instr(vpunpckhwd))]
7266pub unsafe fn _mm512_unpackhi_epi16(a: __m512i, b: __m512i) -> __m512i {
7267 let a: i16x32 = a.as_i16x32();
7268 let b: i16x32 = b.as_i16x32();
7269 #[rustfmt::skip]
7270 let r: i16x32 = simd_shuffle!(
7271 a,
7272 b,
7273 [
7274 4, 32 + 4, 5, 32 + 5,
7275 6, 32 + 6, 7, 32 + 7,
7276 12, 32 + 12, 13, 32 + 13,
7277 14, 32 + 14, 15, 32 + 15,
7278 20, 32 + 20, 21, 32 + 21,
7279 22, 32 + 22, 23, 32 + 23,
7280 28, 32 + 28, 29, 32 + 29,
7281 30, 32 + 30, 31, 32 + 31,
7282 ],
7283 );
7284 transmute(src:r)
7285}
7286
7287/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7288///
7289/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi16&expand=6010)
7290#[inline]
7291#[target_feature(enable = "avx512bw")]
7292#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7293#[cfg_attr(test, assert_instr(vpunpckhwd))]
7294pub unsafe fn _mm512_mask_unpackhi_epi16(
7295 src: __m512i,
7296 k: __mmask32,
7297 a: __m512i,
7298 b: __m512i,
7299) -> __m512i {
7300 let unpackhi: i16x32 = _mm512_unpackhi_epi16(a, b).as_i16x32();
7301 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i16x32()))
7302}
7303
7304/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7305///
7306/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi16&expand=6011)
7307#[inline]
7308#[target_feature(enable = "avx512bw")]
7309#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7310#[cfg_attr(test, assert_instr(vpunpckhwd))]
7311pub unsafe fn _mm512_maskz_unpackhi_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
7312 let unpackhi: i16x32 = _mm512_unpackhi_epi16(a, b).as_i16x32();
7313 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
7314 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7315}
7316
7317/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7318///
7319/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi16&expand=6007)
7320#[inline]
7321#[target_feature(enable = "avx512bw,avx512vl")]
7322#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7323#[cfg_attr(test, assert_instr(vpunpckhwd))]
7324pub unsafe fn _mm256_mask_unpackhi_epi16(
7325 src: __m256i,
7326 k: __mmask16,
7327 a: __m256i,
7328 b: __m256i,
7329) -> __m256i {
7330 let unpackhi: i16x16 = _mm256_unpackhi_epi16(a, b).as_i16x16();
7331 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i16x16()))
7332}
7333
7334/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7335///
7336/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi16&expand=6008)
7337#[inline]
7338#[target_feature(enable = "avx512bw,avx512vl")]
7339#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7340#[cfg_attr(test, assert_instr(vpunpckhwd))]
7341pub unsafe fn _mm256_maskz_unpackhi_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
7342 let unpackhi: i16x16 = _mm256_unpackhi_epi16(a, b).as_i16x16();
7343 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
7344 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7345}
7346
7347/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7348///
7349/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi16&expand=6004)
7350#[inline]
7351#[target_feature(enable = "avx512bw,avx512vl")]
7352#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7353#[cfg_attr(test, assert_instr(vpunpckhwd))]
7354pub unsafe fn _mm_mask_unpackhi_epi16(
7355 src: __m128i,
7356 k: __mmask8,
7357 a: __m128i,
7358 b: __m128i,
7359) -> __m128i {
7360 let unpackhi: i16x8 = _mm_unpackhi_epi16(a, b).as_i16x8();
7361 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i16x8()))
7362}
7363
7364/// Unpack and interleave 16-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7365///
7366/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi16&expand=6005)
7367#[inline]
7368#[target_feature(enable = "avx512bw,avx512vl")]
7369#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7370#[cfg_attr(test, assert_instr(vpunpckhwd))]
7371pub unsafe fn _mm_maskz_unpackhi_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
7372 let unpackhi: i16x8 = _mm_unpackhi_epi16(a, b).as_i16x8();
7373 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
7374 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7375}
7376
7377/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst.
7378///
7379/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpackhi_epi8&expand=6039)
7380#[inline]
7381#[target_feature(enable = "avx512bw")]
7382#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7383#[cfg_attr(test, assert_instr(vpunpckhbw))]
7384pub unsafe fn _mm512_unpackhi_epi8(a: __m512i, b: __m512i) -> __m512i {
7385 let a = a.as_i8x64();
7386 let b = b.as_i8x64();
7387 #[rustfmt::skip]
7388 let r: i8x64 = simd_shuffle!(
7389 a,
7390 b,
7391 [
7392 8, 64+8, 9, 64+9,
7393 10, 64+10, 11, 64+11,
7394 12, 64+12, 13, 64+13,
7395 14, 64+14, 15, 64+15,
7396 24, 64+24, 25, 64+25,
7397 26, 64+26, 27, 64+27,
7398 28, 64+28, 29, 64+29,
7399 30, 64+30, 31, 64+31,
7400 40, 64+40, 41, 64+41,
7401 42, 64+42, 43, 64+43,
7402 44, 64+44, 45, 64+45,
7403 46, 64+46, 47, 64+47,
7404 56, 64+56, 57, 64+57,
7405 58, 64+58, 59, 64+59,
7406 60, 64+60, 61, 64+61,
7407 62, 64+62, 63, 64+63,
7408 ],
7409 );
7410 transmute(r)
7411}
7412
7413/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7414///
7415/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpackhi_epi8&expand=6037)
7416#[inline]
7417#[target_feature(enable = "avx512bw")]
7418#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7419#[cfg_attr(test, assert_instr(vpunpckhbw))]
7420pub unsafe fn _mm512_mask_unpackhi_epi8(
7421 src: __m512i,
7422 k: __mmask64,
7423 a: __m512i,
7424 b: __m512i,
7425) -> __m512i {
7426 let unpackhi: i8x64 = _mm512_unpackhi_epi8(a, b).as_i8x64();
7427 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i8x64()))
7428}
7429
7430/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7431///
7432/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpackhi_epi8&expand=6038)
7433#[inline]
7434#[target_feature(enable = "avx512bw")]
7435#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7436#[cfg_attr(test, assert_instr(vpunpckhbw))]
7437pub unsafe fn _mm512_maskz_unpackhi_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
7438 let unpackhi: i8x64 = _mm512_unpackhi_epi8(a, b).as_i8x64();
7439 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
7440 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7441}
7442
7443/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7444///
7445/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpackhi_epi8&expand=6034)
7446#[inline]
7447#[target_feature(enable = "avx512bw,avx512vl")]
7448#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7449#[cfg_attr(test, assert_instr(vpunpckhbw))]
7450pub unsafe fn _mm256_mask_unpackhi_epi8(
7451 src: __m256i,
7452 k: __mmask32,
7453 a: __m256i,
7454 b: __m256i,
7455) -> __m256i {
7456 let unpackhi: i8x32 = _mm256_unpackhi_epi8(a, b).as_i8x32();
7457 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i8x32()))
7458}
7459
7460/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7461///
7462/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpackhi_epi8&expand=6035)
7463#[inline]
7464#[target_feature(enable = "avx512bw,avx512vl")]
7465#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7466#[cfg_attr(test, assert_instr(vpunpckhbw))]
7467pub unsafe fn _mm256_maskz_unpackhi_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
7468 let unpackhi: i8x32 = _mm256_unpackhi_epi8(a, b).as_i8x32();
7469 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
7470 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7471}
7472
7473/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7474///
7475/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpackhi_epi8&expand=6031)
7476#[inline]
7477#[target_feature(enable = "avx512bw,avx512vl")]
7478#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7479#[cfg_attr(test, assert_instr(vpunpckhbw))]
7480pub unsafe fn _mm_mask_unpackhi_epi8(
7481 src: __m128i,
7482 k: __mmask16,
7483 a: __m128i,
7484 b: __m128i,
7485) -> __m128i {
7486 let unpackhi: i8x16 = _mm_unpackhi_epi8(a, b).as_i8x16();
7487 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:src.as_i8x16()))
7488}
7489
7490/// Unpack and interleave 8-bit integers from the high half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7491///
7492/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpackhi_epi8&expand=6032)
7493#[inline]
7494#[target_feature(enable = "avx512bw,avx512vl")]
7495#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7496#[cfg_attr(test, assert_instr(vpunpckhbw))]
7497pub unsafe fn _mm_maskz_unpackhi_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
7498 let unpackhi: i8x16 = _mm_unpackhi_epi8(a, b).as_i8x16();
7499 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
7500 transmute(src:simd_select_bitmask(m:k, yes:unpackhi, no:zero))
7501}
7502
7503/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst.
7504///
7505/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi16&expand=6069)
7506#[inline]
7507#[target_feature(enable = "avx512bw")]
7508#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7509#[cfg_attr(test, assert_instr(vpunpcklwd))]
7510pub unsafe fn _mm512_unpacklo_epi16(a: __m512i, b: __m512i) -> __m512i {
7511 let a: i16x32 = a.as_i16x32();
7512 let b: i16x32 = b.as_i16x32();
7513 #[rustfmt::skip]
7514 let r: i16x32 = simd_shuffle!(
7515 a,
7516 b,
7517 [
7518 0, 32+0, 1, 32+1,
7519 2, 32+2, 3, 32+3,
7520 8, 32+8, 9, 32+9,
7521 10, 32+10, 11, 32+11,
7522 16, 32+16, 17, 32+17,
7523 18, 32+18, 19, 32+19,
7524 24, 32+24, 25, 32+25,
7525 26, 32+26, 27, 32+27
7526 ],
7527 );
7528 transmute(src:r)
7529}
7530
7531/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7532///
7533/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi16&expand=6067)
7534#[inline]
7535#[target_feature(enable = "avx512bw")]
7536#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7537#[cfg_attr(test, assert_instr(vpunpcklwd))]
7538pub unsafe fn _mm512_mask_unpacklo_epi16(
7539 src: __m512i,
7540 k: __mmask32,
7541 a: __m512i,
7542 b: __m512i,
7543) -> __m512i {
7544 let unpacklo: i16x32 = _mm512_unpacklo_epi16(a, b).as_i16x32();
7545 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i16x32()))
7546}
7547
7548/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7549///
7550/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi16&expand=6068)
7551#[inline]
7552#[target_feature(enable = "avx512bw")]
7553#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7554#[cfg_attr(test, assert_instr(vpunpcklwd))]
7555pub unsafe fn _mm512_maskz_unpacklo_epi16(k: __mmask32, a: __m512i, b: __m512i) -> __m512i {
7556 let unpacklo: i16x32 = _mm512_unpacklo_epi16(a, b).as_i16x32();
7557 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
7558 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7559}
7560
7561/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7562///
7563/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi16&expand=6064)
7564#[inline]
7565#[target_feature(enable = "avx512bw,avx512vl")]
7566#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7567#[cfg_attr(test, assert_instr(vpunpcklwd))]
7568pub unsafe fn _mm256_mask_unpacklo_epi16(
7569 src: __m256i,
7570 k: __mmask16,
7571 a: __m256i,
7572 b: __m256i,
7573) -> __m256i {
7574 let unpacklo: i16x16 = _mm256_unpacklo_epi16(a, b).as_i16x16();
7575 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i16x16()))
7576}
7577
7578/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7579///
7580/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi16&expand=6065)
7581#[inline]
7582#[target_feature(enable = "avx512bw,avx512vl")]
7583#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7584#[cfg_attr(test, assert_instr(vpunpcklwd))]
7585pub unsafe fn _mm256_maskz_unpacklo_epi16(k: __mmask16, a: __m256i, b: __m256i) -> __m256i {
7586 let unpacklo: i16x16 = _mm256_unpacklo_epi16(a, b).as_i16x16();
7587 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
7588 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7589}
7590
7591/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7592///
7593/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi16&expand=6061)
7594#[inline]
7595#[target_feature(enable = "avx512bw,avx512vl")]
7596#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7597#[cfg_attr(test, assert_instr(vpunpcklwd))]
7598pub unsafe fn _mm_mask_unpacklo_epi16(
7599 src: __m128i,
7600 k: __mmask8,
7601 a: __m128i,
7602 b: __m128i,
7603) -> __m128i {
7604 let unpacklo: i16x8 = _mm_unpacklo_epi16(a, b).as_i16x8();
7605 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i16x8()))
7606}
7607
7608/// Unpack and interleave 16-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7609///
7610/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi16&expand=6062)
7611#[inline]
7612#[target_feature(enable = "avx512bw,avx512vl")]
7613#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7614#[cfg_attr(test, assert_instr(vpunpcklwd))]
7615pub unsafe fn _mm_maskz_unpacklo_epi16(k: __mmask8, a: __m128i, b: __m128i) -> __m128i {
7616 let unpacklo: i16x8 = _mm_unpacklo_epi16(a, b).as_i16x8();
7617 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
7618 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7619}
7620
7621/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst.
7622///
7623/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_unpacklo_epi8&expand=6096)
7624#[inline]
7625#[target_feature(enable = "avx512bw")]
7626#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7627#[cfg_attr(test, assert_instr(vpunpcklbw))]
7628pub unsafe fn _mm512_unpacklo_epi8(a: __m512i, b: __m512i) -> __m512i {
7629 let a = a.as_i8x64();
7630 let b = b.as_i8x64();
7631 #[rustfmt::skip]
7632 let r: i8x64 = simd_shuffle!(
7633 a,
7634 b,
7635 [
7636 0, 64+0, 1, 64+1,
7637 2, 64+2, 3, 64+3,
7638 4, 64+4, 5, 64+5,
7639 6, 64+6, 7, 64+7,
7640 16, 64+16, 17, 64+17,
7641 18, 64+18, 19, 64+19,
7642 20, 64+20, 21, 64+21,
7643 22, 64+22, 23, 64+23,
7644 32, 64+32, 33, 64+33,
7645 34, 64+34, 35, 64+35,
7646 36, 64+36, 37, 64+37,
7647 38, 64+38, 39, 64+39,
7648 48, 64+48, 49, 64+49,
7649 50, 64+50, 51, 64+51,
7650 52, 64+52, 53, 64+53,
7651 54, 64+54, 55, 64+55,
7652 ],
7653 );
7654 transmute(r)
7655}
7656
7657/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7658///
7659/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_unpacklo_epi8&expand=6094)
7660#[inline]
7661#[target_feature(enable = "avx512bw")]
7662#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7663#[cfg_attr(test, assert_instr(vpunpcklbw))]
7664pub unsafe fn _mm512_mask_unpacklo_epi8(
7665 src: __m512i,
7666 k: __mmask64,
7667 a: __m512i,
7668 b: __m512i,
7669) -> __m512i {
7670 let unpacklo: i8x64 = _mm512_unpacklo_epi8(a, b).as_i8x64();
7671 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i8x64()))
7672}
7673
7674/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7675///
7676/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_unpacklo_epi8&expand=6095)
7677#[inline]
7678#[target_feature(enable = "avx512bw")]
7679#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7680#[cfg_attr(test, assert_instr(vpunpcklbw))]
7681pub unsafe fn _mm512_maskz_unpacklo_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
7682 let unpacklo: i8x64 = _mm512_unpacklo_epi8(a, b).as_i8x64();
7683 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
7684 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7685}
7686
7687/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7688///
7689/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_unpacklo_epi8&expand=6091)
7690#[inline]
7691#[target_feature(enable = "avx512bw,avx512vl")]
7692#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7693#[cfg_attr(test, assert_instr(vpunpcklbw))]
7694pub unsafe fn _mm256_mask_unpacklo_epi8(
7695 src: __m256i,
7696 k: __mmask32,
7697 a: __m256i,
7698 b: __m256i,
7699) -> __m256i {
7700 let unpacklo: i8x32 = _mm256_unpacklo_epi8(a, b).as_i8x32();
7701 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i8x32()))
7702}
7703
7704/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7705///
7706/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_unpacklo_epi8&expand=6092)
7707#[inline]
7708#[target_feature(enable = "avx512bw,avx512vl")]
7709#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7710#[cfg_attr(test, assert_instr(vpunpcklbw))]
7711pub unsafe fn _mm256_maskz_unpacklo_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
7712 let unpacklo: i8x32 = _mm256_unpacklo_epi8(a, b).as_i8x32();
7713 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
7714 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7715}
7716
7717/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7718///
7719/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_unpacklo_epi8&expand=6088)
7720#[inline]
7721#[target_feature(enable = "avx512bw,avx512vl")]
7722#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7723#[cfg_attr(test, assert_instr(vpunpcklbw))]
7724pub unsafe fn _mm_mask_unpacklo_epi8(
7725 src: __m128i,
7726 k: __mmask16,
7727 a: __m128i,
7728 b: __m128i,
7729) -> __m128i {
7730 let unpacklo: i8x16 = _mm_unpacklo_epi8(a, b).as_i8x16();
7731 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:src.as_i8x16()))
7732}
7733
7734/// Unpack and interleave 8-bit integers from the low half of each 128-bit lane in a and b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7735///
7736/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_unpacklo_epi8&expand=6089)
7737#[inline]
7738#[target_feature(enable = "avx512bw,avx512vl")]
7739#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7740#[cfg_attr(test, assert_instr(vpunpcklbw))]
7741pub unsafe fn _mm_maskz_unpacklo_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
7742 let unpacklo: i8x16 = _mm_unpacklo_epi8(a, b).as_i8x16();
7743 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
7744 transmute(src:simd_select_bitmask(m:k, yes:unpacklo, no:zero))
7745}
7746
7747/// Move packed 16-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7748///
7749/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi16&expand=3795)
7750#[inline]
7751#[target_feature(enable = "avx512bw")]
7752#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7753#[cfg_attr(test, assert_instr(vmovdqu16))]
7754pub unsafe fn _mm512_mask_mov_epi16(src: __m512i, k: __mmask32, a: __m512i) -> __m512i {
7755 let mov: i16x32 = a.as_i16x32();
7756 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i16x32()))
7757}
7758
7759/// Move packed 16-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7760///
7761/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi16&expand=3796)
7762#[inline]
7763#[target_feature(enable = "avx512bw")]
7764#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7765#[cfg_attr(test, assert_instr(vmovdqu16))]
7766pub unsafe fn _mm512_maskz_mov_epi16(k: __mmask32, a: __m512i) -> __m512i {
7767 let mov: i16x32 = a.as_i16x32();
7768 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
7769 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7770}
7771
7772/// Move packed 16-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7773///
7774/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi16&expand=3793)
7775#[inline]
7776#[target_feature(enable = "avx512bw,avx512vl")]
7777#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7778#[cfg_attr(test, assert_instr(vmovdqu16))]
7779pub unsafe fn _mm256_mask_mov_epi16(src: __m256i, k: __mmask16, a: __m256i) -> __m256i {
7780 let mov: i16x16 = a.as_i16x16();
7781 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i16x16()))
7782}
7783
7784/// Move packed 16-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7785///
7786/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi16&expand=3794)
7787#[inline]
7788#[target_feature(enable = "avx512bw,avx512vl")]
7789#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7790#[cfg_attr(test, assert_instr(vmovdqu16))]
7791pub unsafe fn _mm256_maskz_mov_epi16(k: __mmask16, a: __m256i) -> __m256i {
7792 let mov: i16x16 = a.as_i16x16();
7793 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
7794 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7795}
7796
7797/// Move packed 16-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7798///
7799/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi16&expand=3791)
7800#[inline]
7801#[target_feature(enable = "avx512bw,avx512vl")]
7802#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7803#[cfg_attr(test, assert_instr(vmovdqu16))]
7804pub unsafe fn _mm_mask_mov_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
7805 let mov: i16x8 = a.as_i16x8();
7806 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i16x8()))
7807}
7808
7809/// Move packed 16-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7810///
7811/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi16&expand=3792)
7812#[inline]
7813#[target_feature(enable = "avx512bw,avx512vl")]
7814#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7815#[cfg_attr(test, assert_instr(vmovdqu16))]
7816pub unsafe fn _mm_maskz_mov_epi16(k: __mmask8, a: __m128i) -> __m128i {
7817 let mov: i16x8 = a.as_i16x8();
7818 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
7819 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7820}
7821
7822/// Move packed 8-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7823///
7824/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_mov_epi8&expand=3813)
7825#[inline]
7826#[target_feature(enable = "avx512bw")]
7827#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7828#[cfg_attr(test, assert_instr(vmovdqu8))]
7829pub unsafe fn _mm512_mask_mov_epi8(src: __m512i, k: __mmask64, a: __m512i) -> __m512i {
7830 let mov: i8x64 = a.as_i8x64();
7831 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i8x64()))
7832}
7833
7834/// Move packed 8-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7835///
7836/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_mov_epi8&expand=3814)
7837#[inline]
7838#[target_feature(enable = "avx512bw")]
7839#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7840#[cfg_attr(test, assert_instr(vmovdqu8))]
7841pub unsafe fn _mm512_maskz_mov_epi8(k: __mmask64, a: __m512i) -> __m512i {
7842 let mov: i8x64 = a.as_i8x64();
7843 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
7844 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7845}
7846
7847/// Move packed 8-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7848///
7849/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_mov_epi8&expand=3811)
7850#[inline]
7851#[target_feature(enable = "avx512bw,avx512vl")]
7852#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7853#[cfg_attr(test, assert_instr(vmovdqu8))]
7854pub unsafe fn _mm256_mask_mov_epi8(src: __m256i, k: __mmask32, a: __m256i) -> __m256i {
7855 let mov: i8x32 = a.as_i8x32();
7856 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i8x32()))
7857}
7858
7859/// Move packed 8-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7860///
7861/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_mov_epi8&expand=3812)
7862#[inline]
7863#[target_feature(enable = "avx512bw,avx512vl")]
7864#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7865#[cfg_attr(test, assert_instr(vmovdqu8))]
7866pub unsafe fn _mm256_maskz_mov_epi8(k: __mmask32, a: __m256i) -> __m256i {
7867 let mov: i8x32 = a.as_i8x32();
7868 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
7869 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7870}
7871
7872/// Move packed 8-bit integers from a into dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7873///
7874/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_mov_epi8&expand=3809)
7875#[inline]
7876#[target_feature(enable = "avx512bw,avx512vl")]
7877#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7878#[cfg_attr(test, assert_instr(vmovdqu8))]
7879pub unsafe fn _mm_mask_mov_epi8(src: __m128i, k: __mmask16, a: __m128i) -> __m128i {
7880 let mov: i8x16 = a.as_i8x16();
7881 transmute(src:simd_select_bitmask(m:k, yes:mov, no:src.as_i8x16()))
7882}
7883
7884/// Move packed 8-bit integers from a into dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7885///
7886/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_mov_epi8&expand=3810)
7887#[inline]
7888#[target_feature(enable = "avx512bw,avx512vl")]
7889#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7890#[cfg_attr(test, assert_instr(vmovdqu8))]
7891pub unsafe fn _mm_maskz_mov_epi8(k: __mmask16, a: __m128i) -> __m128i {
7892 let mov: i8x16 = a.as_i8x16();
7893 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
7894 transmute(src:simd_select_bitmask(m:k, yes:mov, no:zero))
7895}
7896
7897/// Broadcast 16-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7898///
7899/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi16&expand=4942)
7900#[inline]
7901#[target_feature(enable = "avx512bw")]
7902#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7903#[cfg_attr(test, assert_instr(vpbroadcastw))]
7904pub unsafe fn _mm512_mask_set1_epi16(src: __m512i, k: __mmask32, a: i16) -> __m512i {
7905 let r: i16x32 = _mm512_set1_epi16(a).as_i16x32();
7906 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i16x32()))
7907}
7908
7909/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7910///
7911/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi16&expand=4943)
7912#[inline]
7913#[target_feature(enable = "avx512bw")]
7914#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7915#[cfg_attr(test, assert_instr(vpbroadcastw))]
7916pub unsafe fn _mm512_maskz_set1_epi16(k: __mmask32, a: i16) -> __m512i {
7917 let r: i16x32 = _mm512_set1_epi16(a).as_i16x32();
7918 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
7919 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
7920}
7921
7922/// Broadcast 16-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7923///
7924/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi16&expand=4939)
7925#[inline]
7926#[target_feature(enable = "avx512bw,avx512vl")]
7927#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7928#[cfg_attr(test, assert_instr(vpbroadcastw))]
7929pub unsafe fn _mm256_mask_set1_epi16(src: __m256i, k: __mmask16, a: i16) -> __m256i {
7930 let r: i16x16 = _mm256_set1_epi16(a).as_i16x16();
7931 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i16x16()))
7932}
7933
7934/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7935///
7936/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi16&expand=4940)
7937#[inline]
7938#[target_feature(enable = "avx512bw,avx512vl")]
7939#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7940#[cfg_attr(test, assert_instr(vpbroadcastw))]
7941pub unsafe fn _mm256_maskz_set1_epi16(k: __mmask16, a: i16) -> __m256i {
7942 let r: i16x16 = _mm256_set1_epi16(a).as_i16x16();
7943 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
7944 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
7945}
7946
7947/// Broadcast 16-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7948///
7949/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi16&expand=4936)
7950#[inline]
7951#[target_feature(enable = "avx512bw,avx512vl")]
7952#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7953#[cfg_attr(test, assert_instr(vpbroadcastw))]
7954pub unsafe fn _mm_mask_set1_epi16(src: __m128i, k: __mmask8, a: i16) -> __m128i {
7955 let r: i16x8 = _mm_set1_epi16(a).as_i16x8();
7956 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i16x8()))
7957}
7958
7959/// Broadcast the low packed 16-bit integer from a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7960///
7961/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi16&expand=4937)
7962#[inline]
7963#[target_feature(enable = "avx512bw,avx512vl")]
7964#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7965#[cfg_attr(test, assert_instr(vpbroadcastw))]
7966pub unsafe fn _mm_maskz_set1_epi16(k: __mmask8, a: i16) -> __m128i {
7967 let r: i16x8 = _mm_set1_epi16(a).as_i16x8();
7968 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
7969 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
7970}
7971
7972/// Broadcast 8-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7973///
7974/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_set1_epi8&expand=4970)
7975#[inline]
7976#[target_feature(enable = "avx512bw")]
7977#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7978#[cfg_attr(test, assert_instr(vpbroadcast))]
7979pub unsafe fn _mm512_mask_set1_epi8(src: __m512i, k: __mmask64, a: i8) -> __m512i {
7980 let r: i8x64 = _mm512_set1_epi8(a).as_i8x64();
7981 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i8x64()))
7982}
7983
7984/// Broadcast 8-bit integer a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
7985///
7986/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_set1_epi8&expand=4971)
7987#[inline]
7988#[target_feature(enable = "avx512bw")]
7989#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
7990#[cfg_attr(test, assert_instr(vpbroadcast))]
7991pub unsafe fn _mm512_maskz_set1_epi8(k: __mmask64, a: i8) -> __m512i {
7992 let r: i8x64 = _mm512_set1_epi8(a).as_i8x64();
7993 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
7994 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
7995}
7996
7997/// Broadcast 8-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
7998///
7999/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_set1_epi8&expand=4967)
8000#[inline]
8001#[target_feature(enable = "avx512bw,avx512vl")]
8002#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8003#[cfg_attr(test, assert_instr(vpbroadcast))]
8004pub unsafe fn _mm256_mask_set1_epi8(src: __m256i, k: __mmask32, a: i8) -> __m256i {
8005 let r: i8x32 = _mm256_set1_epi8(a).as_i8x32();
8006 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i8x32()))
8007}
8008
8009/// Broadcast 8-bit integer a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8010///
8011/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_set1_epi8&expand=4968)
8012#[inline]
8013#[target_feature(enable = "avx512bw,avx512vl")]
8014#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8015#[cfg_attr(test, assert_instr(vpbroadcast))]
8016pub unsafe fn _mm256_maskz_set1_epi8(k: __mmask32, a: i8) -> __m256i {
8017 let r: i8x32 = _mm256_set1_epi8(a).as_i8x32();
8018 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
8019 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
8020}
8021
8022/// Broadcast 8-bit integer a to all elements of dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8023///
8024/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_set1_epi8&expand=4964)
8025#[inline]
8026#[target_feature(enable = "avx512bw,avx512vl")]
8027#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8028#[cfg_attr(test, assert_instr(vpbroadcast))]
8029pub unsafe fn _mm_mask_set1_epi8(src: __m128i, k: __mmask16, a: i8) -> __m128i {
8030 let r: i8x16 = _mm_set1_epi8(a).as_i8x16();
8031 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_i8x16()))
8032}
8033
8034/// Broadcast 8-bit integer a to all elements of dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8035///
8036/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_set1_epi8&expand=4965)
8037#[inline]
8038#[target_feature(enable = "avx512bw,avx512vl")]
8039#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8040#[cfg_attr(test, assert_instr(vpbroadcast))]
8041pub unsafe fn _mm_maskz_set1_epi8(k: __mmask16, a: i8) -> __m128i {
8042 let r: i8x16 = _mm_set1_epi8(a).as_i8x16();
8043 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
8044 transmute(src:simd_select_bitmask(m:k, yes:r, no:zero))
8045}
8046
8047/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst.
8048///
8049/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shufflelo_epi16&expand=5221)
8050#[inline]
8051#[target_feature(enable = "avx512bw")]
8052#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8053#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
8054#[rustc_legacy_const_generics(1)]
8055pub unsafe fn _mm512_shufflelo_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
8056 static_assert_uimm_bits!(IMM8, 8);
8057 let a = a.as_i16x32();
8058 let r: i16x32 = simd_shuffle!(
8059 a,
8060 a,
8061 [
8062 IMM8 as u32 & 0b11,
8063 (IMM8 as u32 >> 2) & 0b11,
8064 (IMM8 as u32 >> 4) & 0b11,
8065 (IMM8 as u32 >> 6) & 0b11,
8066 4,
8067 5,
8068 6,
8069 7,
8070 (IMM8 as u32 & 0b11) + 8,
8071 ((IMM8 as u32 >> 2) & 0b11) + 8,
8072 ((IMM8 as u32 >> 4) & 0b11) + 8,
8073 ((IMM8 as u32 >> 6) & 0b11) + 8,
8074 12,
8075 13,
8076 14,
8077 15,
8078 (IMM8 as u32 & 0b11) + 16,
8079 ((IMM8 as u32 >> 2) & 0b11) + 16,
8080 ((IMM8 as u32 >> 4) & 0b11) + 16,
8081 ((IMM8 as u32 >> 6) & 0b11) + 16,
8082 20,
8083 21,
8084 22,
8085 23,
8086 (IMM8 as u32 & 0b11) + 24,
8087 ((IMM8 as u32 >> 2) & 0b11) + 24,
8088 ((IMM8 as u32 >> 4) & 0b11) + 24,
8089 ((IMM8 as u32 >> 6) & 0b11) + 24,
8090 28,
8091 29,
8092 30,
8093 31,
8094 ],
8095 );
8096 transmute(r)
8097}
8098
8099/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8100///
8101/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shufflelo_epi16&expand=5219)
8102#[inline]
8103#[target_feature(enable = "avx512bw")]
8104#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8105#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
8106#[rustc_legacy_const_generics(3)]
8107pub unsafe fn _mm512_mask_shufflelo_epi16<const IMM8: i32>(
8108 src: __m512i,
8109 k: __mmask32,
8110 a: __m512i,
8111) -> __m512i {
8112 static_assert_uimm_bits!(IMM8, 8);
8113 let r: __m512i = _mm512_shufflelo_epi16::<IMM8>(a);
8114 transmute(src:simd_select_bitmask(m:k, yes:r.as_i16x32(), no:src.as_i16x32()))
8115}
8116
8117/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8118///
8119/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shufflelo_epi16&expand=5220)
8120#[inline]
8121#[target_feature(enable = "avx512bw")]
8122#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8123#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))]
8124#[rustc_legacy_const_generics(2)]
8125pub unsafe fn _mm512_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
8126 static_assert_uimm_bits!(IMM8, 8);
8127 let r: __m512i = _mm512_shufflelo_epi16::<IMM8>(a);
8128 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
8129 transmute(src:simd_select_bitmask(m:k, yes:r.as_i16x32(), no:zero))
8130}
8131
8132/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8133///
8134/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shufflelo_epi16&expand=5216)
8135#[inline]
8136#[target_feature(enable = "avx512bw,avx512vl")]
8137#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8138#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
8139#[rustc_legacy_const_generics(3)]
8140pub unsafe fn _mm256_mask_shufflelo_epi16<const IMM8: i32>(
8141 src: __m256i,
8142 k: __mmask16,
8143 a: __m256i,
8144) -> __m256i {
8145 static_assert_uimm_bits!(IMM8, 8);
8146 let shuffle: __m256i = _mm256_shufflelo_epi16::<IMM8>(a);
8147 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x16(), no:src.as_i16x16()))
8148}
8149
8150/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8151///
8152/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shufflelo_epi16&expand=5217)
8153#[inline]
8154#[target_feature(enable = "avx512bw,avx512vl")]
8155#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8156#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
8157#[rustc_legacy_const_generics(2)]
8158pub unsafe fn _mm256_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
8159 static_assert_uimm_bits!(IMM8, 8);
8160 let shuffle: __m256i = _mm256_shufflelo_epi16::<IMM8>(a);
8161 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
8162 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x16(), no:zero))
8163}
8164
8165/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8166///
8167/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shufflelo_epi16&expand=5213)
8168#[inline]
8169#[target_feature(enable = "avx512bw,avx512vl")]
8170#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8171#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
8172#[rustc_legacy_const_generics(3)]
8173pub unsafe fn _mm_mask_shufflelo_epi16<const IMM8: i32>(
8174 src: __m128i,
8175 k: __mmask8,
8176 a: __m128i,
8177) -> __m128i {
8178 static_assert_uimm_bits!(IMM8, 8);
8179 let shuffle: __m128i = _mm_shufflelo_epi16::<IMM8>(a);
8180 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x8(), no:src.as_i16x8()))
8181}
8182
8183/// Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the low 64 bits of 128-bit lanes of dst, with the high 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8184///
8185/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shufflelo_epi16&expand=5214)
8186#[inline]
8187#[target_feature(enable = "avx512bw,avx512vl")]
8188#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8189#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))]
8190#[rustc_legacy_const_generics(2)]
8191pub unsafe fn _mm_maskz_shufflelo_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
8192 static_assert_uimm_bits!(IMM8, 8);
8193 let shuffle: __m128i = _mm_shufflelo_epi16::<IMM8>(a);
8194 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
8195 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x8(), no:zero))
8196}
8197
8198/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst.
8199///
8200/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shufflehi_epi16&expand=5212)
8201#[inline]
8202#[target_feature(enable = "avx512bw")]
8203#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8204#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
8205#[rustc_legacy_const_generics(1)]
8206pub unsafe fn _mm512_shufflehi_epi16<const IMM8: i32>(a: __m512i) -> __m512i {
8207 static_assert_uimm_bits!(IMM8, 8);
8208 let a = a.as_i16x32();
8209 let r: i16x32 = simd_shuffle!(
8210 a,
8211 a,
8212 [
8213 0,
8214 1,
8215 2,
8216 3,
8217 (IMM8 as u32 & 0b11) + 4,
8218 ((IMM8 as u32 >> 2) & 0b11) + 4,
8219 ((IMM8 as u32 >> 4) & 0b11) + 4,
8220 ((IMM8 as u32 >> 6) & 0b11) + 4,
8221 8,
8222 9,
8223 10,
8224 11,
8225 (IMM8 as u32 & 0b11) + 12,
8226 ((IMM8 as u32 >> 2) & 0b11) + 12,
8227 ((IMM8 as u32 >> 4) & 0b11) + 12,
8228 ((IMM8 as u32 >> 6) & 0b11) + 12,
8229 16,
8230 17,
8231 18,
8232 19,
8233 (IMM8 as u32 & 0b11) + 20,
8234 ((IMM8 as u32 >> 2) & 0b11) + 20,
8235 ((IMM8 as u32 >> 4) & 0b11) + 20,
8236 ((IMM8 as u32 >> 6) & 0b11) + 20,
8237 24,
8238 25,
8239 26,
8240 27,
8241 (IMM8 as u32 & 0b11) + 28,
8242 ((IMM8 as u32 >> 2) & 0b11) + 28,
8243 ((IMM8 as u32 >> 4) & 0b11) + 28,
8244 ((IMM8 as u32 >> 6) & 0b11) + 28,
8245 ],
8246 );
8247 transmute(r)
8248}
8249
8250/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8251///
8252/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shufflehi_epi16&expand=5210)
8253#[inline]
8254#[target_feature(enable = "avx512bw")]
8255#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8256#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
8257#[rustc_legacy_const_generics(3)]
8258pub unsafe fn _mm512_mask_shufflehi_epi16<const IMM8: i32>(
8259 src: __m512i,
8260 k: __mmask32,
8261 a: __m512i,
8262) -> __m512i {
8263 static_assert_uimm_bits!(IMM8, 8);
8264 let r: __m512i = _mm512_shufflehi_epi16::<IMM8>(a);
8265 transmute(src:simd_select_bitmask(m:k, yes:r.as_i16x32(), no:src.as_i16x32()))
8266}
8267
8268/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8269///
8270/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shufflehi_epi16&expand=5211)
8271#[inline]
8272#[target_feature(enable = "avx512bw")]
8273#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8274#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))]
8275#[rustc_legacy_const_generics(2)]
8276pub unsafe fn _mm512_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask32, a: __m512i) -> __m512i {
8277 static_assert_uimm_bits!(IMM8, 8);
8278 let r: __m512i = _mm512_shufflehi_epi16::<IMM8>(a);
8279 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
8280 transmute(src:simd_select_bitmask(m:k, yes:r.as_i16x32(), no:zero))
8281}
8282
8283/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8284///
8285/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shufflehi_epi16&expand=5207)
8286#[inline]
8287#[target_feature(enable = "avx512bw,avx512vl")]
8288#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8289#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
8290#[rustc_legacy_const_generics(3)]
8291pub unsafe fn _mm256_mask_shufflehi_epi16<const IMM8: i32>(
8292 src: __m256i,
8293 k: __mmask16,
8294 a: __m256i,
8295) -> __m256i {
8296 static_assert_uimm_bits!(IMM8, 8);
8297 let shuffle: __m256i = _mm256_shufflehi_epi16::<IMM8>(a);
8298 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x16(), no:src.as_i16x16()))
8299}
8300
8301/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8302///
8303/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shufflehi_epi16&expand=5208)
8304#[inline]
8305#[target_feature(enable = "avx512bw,avx512vl")]
8306#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8307#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
8308#[rustc_legacy_const_generics(2)]
8309pub unsafe fn _mm256_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
8310 static_assert_uimm_bits!(IMM8, 8);
8311 let shuffle: __m256i = _mm256_shufflehi_epi16::<IMM8>(a);
8312 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
8313 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x16(), no:zero))
8314}
8315
8316/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using writemask k (elements are copied from src when the corresponding mask bit is not set).
8317///
8318/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shufflehi_epi16&expand=5204)
8319#[inline]
8320#[target_feature(enable = "avx512bw,avx512vl")]
8321#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8322#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
8323#[rustc_legacy_const_generics(3)]
8324pub unsafe fn _mm_mask_shufflehi_epi16<const IMM8: i32>(
8325 src: __m128i,
8326 k: __mmask8,
8327 a: __m128i,
8328) -> __m128i {
8329 static_assert_uimm_bits!(IMM8, 8);
8330 let shuffle: __m128i = _mm_shufflehi_epi16::<IMM8>(a);
8331 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x8(), no:src.as_i16x8()))
8332}
8333
8334/// Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of a using the control in imm8. Store the results in the high 64 bits of 128-bit lanes of dst, with the low 64 bits of 128-bit lanes being copied from a to dst, using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8335///
8336/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shufflehi_epi16&expand=5205)
8337#[inline]
8338#[target_feature(enable = "avx512bw,avx512vl")]
8339#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8340#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))]
8341#[rustc_legacy_const_generics(2)]
8342pub unsafe fn _mm_maskz_shufflehi_epi16<const IMM8: i32>(k: __mmask8, a: __m128i) -> __m128i {
8343 static_assert_uimm_bits!(IMM8, 8);
8344 let shuffle: __m128i = _mm_shufflehi_epi16::<IMM8>(a);
8345 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
8346 transmute(src:simd_select_bitmask(m:k, yes:shuffle.as_i16x8(), no:zero))
8347}
8348
8349/// Shuffle packed 8-bit integers in a according to shuffle control mask in the corresponding 8-bit element of b, and store the results in dst.
8350///
8351/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_shuffle_epi8&expand=5159)
8352#[inline]
8353#[target_feature(enable = "avx512bw")]
8354#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8355#[cfg_attr(test, assert_instr(vpshufb))]
8356pub unsafe fn _mm512_shuffle_epi8(a: __m512i, b: __m512i) -> __m512i {
8357 transmute(src:vpshufb(a:a.as_i8x64(), b:b.as_i8x64()))
8358}
8359
8360/// Shuffle 8-bit integers in a within 128-bit lanes using the control in the corresponding 8-bit element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8361///
8362/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_shuffle_epi8&expand=5157)
8363#[inline]
8364#[target_feature(enable = "avx512bw")]
8365#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8366#[cfg_attr(test, assert_instr(vpshufb))]
8367pub unsafe fn _mm512_mask_shuffle_epi8(
8368 src: __m512i,
8369 k: __mmask64,
8370 a: __m512i,
8371 b: __m512i,
8372) -> __m512i {
8373 let shuffle: i8x64 = _mm512_shuffle_epi8(a, b).as_i8x64();
8374 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:src.as_i8x64()))
8375}
8376
8377/// Shuffle packed 8-bit integers in a according to shuffle control mask in the corresponding 8-bit element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8378///
8379/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_shuffle_epi8&expand=5158)
8380#[inline]
8381#[target_feature(enable = "avx512bw")]
8382#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8383#[cfg_attr(test, assert_instr(vpshufb))]
8384pub unsafe fn _mm512_maskz_shuffle_epi8(k: __mmask64, a: __m512i, b: __m512i) -> __m512i {
8385 let shuffle: i8x64 = _mm512_shuffle_epi8(a, b).as_i8x64();
8386 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
8387 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:zero))
8388}
8389
8390/// Shuffle 8-bit integers in a within 128-bit lanes using the control in the corresponding 8-bit element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8391///
8392/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_shuffle_epi8&expand=5154)
8393#[inline]
8394#[target_feature(enable = "avx512bw,avx512vl")]
8395#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8396#[cfg_attr(test, assert_instr(vpshufb))]
8397pub unsafe fn _mm256_mask_shuffle_epi8(
8398 src: __m256i,
8399 k: __mmask32,
8400 a: __m256i,
8401 b: __m256i,
8402) -> __m256i {
8403 let shuffle: i8x32 = _mm256_shuffle_epi8(a, b).as_i8x32();
8404 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:src.as_i8x32()))
8405}
8406
8407/// Shuffle packed 8-bit integers in a according to shuffle control mask in the corresponding 8-bit element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8408///
8409/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_shuffle_epi8&expand=5155)
8410#[inline]
8411#[target_feature(enable = "avx512bw,avx512vl")]
8412#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8413#[cfg_attr(test, assert_instr(vpshufb))]
8414pub unsafe fn _mm256_maskz_shuffle_epi8(k: __mmask32, a: __m256i, b: __m256i) -> __m256i {
8415 let shuffle: i8x32 = _mm256_shuffle_epi8(a, b).as_i8x32();
8416 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
8417 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:zero))
8418}
8419
8420/// Shuffle 8-bit integers in a within 128-bit lanes using the control in the corresponding 8-bit element of b, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
8421///
8422/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_shuffle_epi8&expand=5151)
8423#[inline]
8424#[target_feature(enable = "avx512bw,avx512vl")]
8425#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8426#[cfg_attr(test, assert_instr(vpshufb))]
8427pub unsafe fn _mm_mask_shuffle_epi8(src: __m128i, k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
8428 let shuffle: i8x16 = _mm_shuffle_epi8(a, b).as_i8x16();
8429 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:src.as_i8x16()))
8430}
8431
8432/// Shuffle packed 8-bit integers in a according to shuffle control mask in the corresponding 8-bit element of b, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
8433///
8434/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_shuffle_epi8&expand=5152)
8435#[inline]
8436#[target_feature(enable = "avx512bw,avx512vl")]
8437#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8438#[cfg_attr(test, assert_instr(vpshufb))]
8439pub unsafe fn _mm_maskz_shuffle_epi8(k: __mmask16, a: __m128i, b: __m128i) -> __m128i {
8440 let shuffle: i8x16 = _mm_shuffle_epi8(a, b).as_i8x16();
8441 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
8442 transmute(src:simd_select_bitmask(m:k, yes:shuffle, no:zero))
8443}
8444
8445/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8446///
8447/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi16_mask&expand=5884)
8448#[inline]
8449#[target_feature(enable = "avx512bw")]
8450#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8451#[cfg_attr(test, assert_instr(vptestmw))]
8452pub unsafe fn _mm512_test_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
8453 let and: __m512i = _mm512_and_si512(a, b);
8454 let zero: __m512i = _mm512_setzero_si512();
8455 _mm512_cmpneq_epi16_mask(a:and, b:zero)
8456}
8457
8458/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8459///
8460/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi16_mask&expand=5883)
8461#[inline]
8462#[target_feature(enable = "avx512bw")]
8463#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8464#[cfg_attr(test, assert_instr(vptestmw))]
8465pub unsafe fn _mm512_mask_test_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
8466 let and: __m512i = _mm512_and_si512(a, b);
8467 let zero: __m512i = _mm512_setzero_si512();
8468 _mm512_mask_cmpneq_epi16_mask(k1:k, a:and, b:zero)
8469}
8470
8471/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8472///
8473// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi16_mask&expand=5882)
8474#[inline]
8475#[target_feature(enable = "avx512bw,avx512vl")]
8476#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8477#[cfg_attr(test, assert_instr(vptestmw))]
8478pub unsafe fn _mm256_test_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
8479 let and: __m256i = _mm256_and_si256(a, b);
8480 let zero: __m256i = _mm256_setzero_si256();
8481 _mm256_cmpneq_epi16_mask(a:and, b:zero)
8482}
8483
8484/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8485///
8486/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi16_mask&expand=5881)
8487#[inline]
8488#[target_feature(enable = "avx512bw,avx512vl")]
8489#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8490#[cfg_attr(test, assert_instr(vptestmw))]
8491pub unsafe fn _mm256_mask_test_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
8492 let and: __m256i = _mm256_and_si256(a, b);
8493 let zero: __m256i = _mm256_setzero_si256();
8494 _mm256_mask_cmpneq_epi16_mask(k1:k, a:and, b:zero)
8495}
8496
8497/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8498///
8499// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi16_mask&expand=5880)
8500#[inline]
8501#[target_feature(enable = "avx512bw,avx512vl")]
8502#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8503#[cfg_attr(test, assert_instr(vptestmw))]
8504pub unsafe fn _mm_test_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
8505 let and: __m128i = _mm_and_si128(a, b);
8506 let zero: __m128i = _mm_setzero_si128();
8507 _mm_cmpneq_epi16_mask(a:and, b:zero)
8508}
8509
8510/// Compute the bitwise AND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8511///
8512/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi16_mask&expand=5879)
8513#[inline]
8514#[target_feature(enable = "avx512bw,avx512vl")]
8515#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8516#[cfg_attr(test, assert_instr(vptestmw))]
8517pub unsafe fn _mm_mask_test_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
8518 let and: __m128i = _mm_and_si128(a, b);
8519 let zero: __m128i = _mm_setzero_si128();
8520 _mm_mask_cmpneq_epi16_mask(k1:k, a:and, b:zero)
8521}
8522
8523/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8524///
8525/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_test_epi8_mask&expand=5902)
8526#[inline]
8527#[target_feature(enable = "avx512bw")]
8528#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8529#[cfg_attr(test, assert_instr(vptestmb))]
8530pub unsafe fn _mm512_test_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
8531 let and: __m512i = _mm512_and_si512(a, b);
8532 let zero: __m512i = _mm512_setzero_si512();
8533 _mm512_cmpneq_epi8_mask(a:and, b:zero)
8534}
8535
8536/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8537///
8538/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_test_epi8_mask&expand=5901)
8539#[inline]
8540#[target_feature(enable = "avx512bw")]
8541#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8542#[cfg_attr(test, assert_instr(vptestmb))]
8543pub unsafe fn _mm512_mask_test_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
8544 let and: __m512i = _mm512_and_si512(a, b);
8545 let zero: __m512i = _mm512_setzero_si512();
8546 _mm512_mask_cmpneq_epi8_mask(k1:k, a:and, b:zero)
8547}
8548
8549/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8550///
8551/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_test_epi8_mask&expand=5900)
8552#[inline]
8553#[target_feature(enable = "avx512bw,avx512vl")]
8554#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8555#[cfg_attr(test, assert_instr(vptestmb))]
8556pub unsafe fn _mm256_test_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
8557 let and: __m256i = _mm256_and_si256(a, b);
8558 let zero: __m256i = _mm256_setzero_si256();
8559 _mm256_cmpneq_epi8_mask(a:and, b:zero)
8560}
8561
8562/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8563///
8564/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_test_epi8_mask&expand=5899)
8565#[inline]
8566#[target_feature(enable = "avx512bw,avx512vl")]
8567#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8568#[cfg_attr(test, assert_instr(vptestmb))]
8569pub unsafe fn _mm256_mask_test_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
8570 let and: __m256i = _mm256_and_si256(a, b);
8571 let zero: __m256i = _mm256_setzero_si256();
8572 _mm256_mask_cmpneq_epi8_mask(k1:k, a:and, b:zero)
8573}
8574
8575/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is non-zero.
8576///
8577/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_test_epi8_mask&expand=5898)
8578#[inline]
8579#[target_feature(enable = "avx512bw,avx512vl")]
8580#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8581#[cfg_attr(test, assert_instr(vptestmb))]
8582pub unsafe fn _mm_test_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
8583 let and: __m128i = _mm_and_si128(a, b);
8584 let zero: __m128i = _mm_setzero_si128();
8585 _mm_cmpneq_epi8_mask(a:and, b:zero)
8586}
8587
8588/// Compute the bitwise AND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is non-zero.
8589///
8590/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_test_epi8_mask&expand=5897)
8591#[inline]
8592#[target_feature(enable = "avx512bw,avx512vl")]
8593#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8594#[cfg_attr(test, assert_instr(vptestmb))]
8595pub unsafe fn _mm_mask_test_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
8596 let and: __m128i = _mm_and_si128(a, b);
8597 let zero: __m128i = _mm_setzero_si128();
8598 _mm_mask_cmpneq_epi8_mask(k1:k, a:and, b:zero)
8599}
8600
8601/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8602///
8603/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi16_mask&expand=5915)
8604#[inline]
8605#[target_feature(enable = "avx512bw")]
8606#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8607#[cfg_attr(test, assert_instr(vptestnmw))]
8608pub unsafe fn _mm512_testn_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 {
8609 let and: __m512i = _mm512_and_si512(a, b);
8610 let zero: __m512i = _mm512_setzero_si512();
8611 _mm512_cmpeq_epi16_mask(a:and, b:zero)
8612}
8613
8614/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8615///
8616/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi16&expand=5914)
8617#[inline]
8618#[target_feature(enable = "avx512bw")]
8619#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8620#[cfg_attr(test, assert_instr(vptestnmw))]
8621pub unsafe fn _mm512_mask_testn_epi16_mask(k: __mmask32, a: __m512i, b: __m512i) -> __mmask32 {
8622 let and: __m512i = _mm512_and_si512(a, b);
8623 let zero: __m512i = _mm512_setzero_si512();
8624 _mm512_mask_cmpeq_epi16_mask(k1:k, a:and, b:zero)
8625}
8626
8627/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8628///
8629/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi16_mask&expand=5913)
8630#[inline]
8631#[target_feature(enable = "avx512bw,avx512vl")]
8632#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8633#[cfg_attr(test, assert_instr(vptestnmw))]
8634pub unsafe fn _mm256_testn_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 {
8635 let and: __m256i = _mm256_and_si256(a, b);
8636 let zero: __m256i = _mm256_setzero_si256();
8637 _mm256_cmpeq_epi16_mask(a:and, b:zero)
8638}
8639
8640/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8641///
8642/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi16_mask&expand=5912)
8643#[inline]
8644#[target_feature(enable = "avx512bw,avx512vl")]
8645#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8646#[cfg_attr(test, assert_instr(vptestnmw))]
8647pub unsafe fn _mm256_mask_testn_epi16_mask(k: __mmask16, a: __m256i, b: __m256i) -> __mmask16 {
8648 let and: __m256i = _mm256_and_si256(a, b);
8649 let zero: __m256i = _mm256_setzero_si256();
8650 _mm256_mask_cmpeq_epi16_mask(k1:k, a:and, b:zero)
8651}
8652
8653/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8654///
8655/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi16_mask&expand=5911)
8656#[inline]
8657#[target_feature(enable = "avx512bw,avx512vl")]
8658#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8659#[cfg_attr(test, assert_instr(vptestnmw))]
8660pub unsafe fn _mm_testn_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 {
8661 let and: __m128i = _mm_and_si128(a, b);
8662 let zero: __m128i = _mm_setzero_si128();
8663 _mm_cmpeq_epi16_mask(a:and, b:zero)
8664}
8665
8666/// Compute the bitwise NAND of packed 16-bit integers in a and b, producing intermediate 16-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8667///
8668/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi16_mask&expand=5910)
8669#[inline]
8670#[target_feature(enable = "avx512bw,avx512vl")]
8671#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8672#[cfg_attr(test, assert_instr(vptestnmw))]
8673pub unsafe fn _mm_mask_testn_epi16_mask(k: __mmask8, a: __m128i, b: __m128i) -> __mmask8 {
8674 let and: __m128i = _mm_and_si128(a, b);
8675 let zero: __m128i = _mm_setzero_si128();
8676 _mm_mask_cmpeq_epi16_mask(k1:k, a:and, b:zero)
8677}
8678
8679/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8680///
8681/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_testn_epi8_mask&expand=5933)
8682#[inline]
8683#[target_feature(enable = "avx512bw")]
8684#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8685#[cfg_attr(test, assert_instr(vptestnmb))]
8686pub unsafe fn _mm512_testn_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 {
8687 let and: __m512i = _mm512_and_si512(a, b);
8688 let zero: __m512i = _mm512_setzero_si512();
8689 _mm512_cmpeq_epi8_mask(a:and, b:zero)
8690}
8691
8692/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8693///
8694/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_testn_epi8_mask&expand=5932)
8695#[inline]
8696#[target_feature(enable = "avx512bw")]
8697#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8698#[cfg_attr(test, assert_instr(vptestnmb))]
8699pub unsafe fn _mm512_mask_testn_epi8_mask(k: __mmask64, a: __m512i, b: __m512i) -> __mmask64 {
8700 let and: __m512i = _mm512_and_si512(a, b);
8701 let zero: __m512i = _mm512_setzero_si512();
8702 _mm512_mask_cmpeq_epi8_mask(k1:k, a:and, b:zero)
8703}
8704
8705/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8706///
8707/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testn_epi8_mask&expand=5931)
8708#[inline]
8709#[target_feature(enable = "avx512bw,avx512vl")]
8710#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8711#[cfg_attr(test, assert_instr(vptestnmb))]
8712pub unsafe fn _mm256_testn_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 {
8713 let and: __m256i = _mm256_and_si256(a, b);
8714 let zero: __m256i = _mm256_setzero_si256();
8715 _mm256_cmpeq_epi8_mask(a:and, b:zero)
8716}
8717
8718/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8719///
8720/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_testn_epi8_mask&expand=5930)
8721#[inline]
8722#[target_feature(enable = "avx512bw,avx512vl")]
8723#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8724#[cfg_attr(test, assert_instr(vptestnmb))]
8725pub unsafe fn _mm256_mask_testn_epi8_mask(k: __mmask32, a: __m256i, b: __m256i) -> __mmask32 {
8726 let and: __m256i = _mm256_and_si256(a, b);
8727 let zero: __m256i = _mm256_setzero_si256();
8728 _mm256_mask_cmpeq_epi8_mask(k1:k, a:and, b:zero)
8729}
8730
8731/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k if the intermediate value is zero.
8732///
8733/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_testn_epi8_mask&expand=5929)
8734#[inline]
8735#[target_feature(enable = "avx512bw,avx512vl")]
8736#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8737#[cfg_attr(test, assert_instr(vptestnmb))]
8738pub unsafe fn _mm_testn_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 {
8739 let and: __m128i = _mm_and_si128(a, b);
8740 let zero: __m128i = _mm_setzero_si128();
8741 _mm_cmpeq_epi8_mask(a:and, b:zero)
8742}
8743
8744/// Compute the bitwise NAND of packed 8-bit integers in a and b, producing intermediate 8-bit values, and set the corresponding bit in result mask k (subject to writemask k) if the intermediate value is zero.
8745///
8746/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_testn_epi8_mask&expand=5928)
8747#[inline]
8748#[target_feature(enable = "avx512bw,avx512vl")]
8749#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8750#[cfg_attr(test, assert_instr(vptestnmb))]
8751pub unsafe fn _mm_mask_testn_epi8_mask(k: __mmask16, a: __m128i, b: __m128i) -> __mmask16 {
8752 let and: __m128i = _mm_and_si128(a, b);
8753 let zero: __m128i = _mm_setzero_si128();
8754 _mm_mask_cmpeq_epi8_mask(k1:k, a:and, b:zero)
8755}
8756
8757/// Store 64-bit mask from a into memory.
8758///
8759/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask64&expand=5578)
8760#[inline]
8761#[target_feature(enable = "avx512bw")]
8762#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8763#[cfg_attr(test, assert_instr(mov))] //should be kmovq
8764pub unsafe fn _store_mask64(mem_addr: *mut u64, a: __mmask64) {
8765 ptr::write(dst:mem_addr as *mut __mmask64, src:a);
8766}
8767
8768/// Store 32-bit mask from a into memory.
8769///
8770/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_store_mask32&expand=5577)
8771#[inline]
8772#[target_feature(enable = "avx512bw")]
8773#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8774#[cfg_attr(test, assert_instr(mov))] //should be kmovd
8775pub unsafe fn _store_mask32(mem_addr: *mut u32, a: __mmask32) {
8776 ptr::write(dst:mem_addr as *mut __mmask32, src:a);
8777}
8778
8779/// Load 64-bit mask from memory into k.
8780///
8781/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask64&expand=3318)
8782#[inline]
8783#[target_feature(enable = "avx512bw")]
8784#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8785#[cfg_attr(test, assert_instr(mov))] //should be kmovq
8786pub unsafe fn _load_mask64(mem_addr: *const u64) -> __mmask64 {
8787 ptr::read(src:mem_addr as *const __mmask64)
8788}
8789
8790/// Load 32-bit mask from memory into k.
8791///
8792/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_load_mask32&expand=3317)
8793#[inline]
8794#[target_feature(enable = "avx512bw")]
8795#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8796#[cfg_attr(test, assert_instr(mov))] //should be kmovd
8797pub unsafe fn _load_mask32(mem_addr: *const u32) -> __mmask32 {
8798 ptr::read(src:mem_addr as *const __mmask32)
8799}
8800
8801/// Compute the absolute differences of packed unsigned 8-bit integers in a and b, then horizontally sum each consecutive 8 differences to produce eight unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in dst.
8802///
8803/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_sad_epu8&expand=4855)
8804#[inline]
8805#[target_feature(enable = "avx512bw")]
8806#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8807#[cfg_attr(test, assert_instr(vpsadbw))]
8808pub unsafe fn _mm512_sad_epu8(a: __m512i, b: __m512i) -> __m512i {
8809 transmute(src:vpsadbw(a:a.as_u8x64(), b:b.as_u8x64()))
8810}
8811
8812/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst. Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8813///
8814/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_dbsad_epu8&expand=2114)
8815#[inline]
8816#[target_feature(enable = "avx512bw")]
8817#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8818#[rustc_legacy_const_generics(2)]
8819#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8820pub unsafe fn _mm512_dbsad_epu8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
8821 static_assert_uimm_bits!(IMM8, 8);
8822 let a: u8x64 = a.as_u8x64();
8823 let b: u8x64 = b.as_u8x64();
8824 let r: u16x32 = vdbpsadbw(a, b, IMM8);
8825 transmute(src:r)
8826}
8827
8828/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8829///
8830/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_dbsad_epu8&expand=2115)
8831#[inline]
8832#[target_feature(enable = "avx512bw")]
8833#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8834#[rustc_legacy_const_generics(4)]
8835#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8836pub unsafe fn _mm512_mask_dbsad_epu8<const IMM8: i32>(
8837 src: __m512i,
8838 k: __mmask32,
8839 a: __m512i,
8840 b: __m512i,
8841) -> __m512i {
8842 static_assert_uimm_bits!(IMM8, 8);
8843 let a: u8x64 = a.as_u8x64();
8844 let b: u8x64 = b.as_u8x64();
8845 let r: u16x32 = vdbpsadbw(a, b, IMM8);
8846 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_u16x32()))
8847}
8848
8849/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8850///
8851/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_dbsad_epu8&expand=2116)
8852#[inline]
8853#[target_feature(enable = "avx512bw")]
8854#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8855#[rustc_legacy_const_generics(3)]
8856#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8857pub unsafe fn _mm512_maskz_dbsad_epu8<const IMM8: i32>(
8858 k: __mmask32,
8859 a: __m512i,
8860 b: __m512i,
8861) -> __m512i {
8862 static_assert_uimm_bits!(IMM8, 8);
8863 let a: u8x64 = a.as_u8x64();
8864 let b: u8x64 = b.as_u8x64();
8865 let r: u16x32 = vdbpsadbw(a, b, IMM8);
8866 transmute(src:simd_select_bitmask(
8867 m:k,
8868 yes:r,
8869 no:_mm512_setzero_si512().as_u16x32(),
8870 ))
8871}
8872
8873/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst. Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8874///
8875/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_dbsad_epu8&expand=2111)
8876#[inline]
8877#[target_feature(enable = "avx512bw,avx512vl")]
8878#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8879#[rustc_legacy_const_generics(2)]
8880#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8881pub unsafe fn _mm256_dbsad_epu8<const IMM8: i32>(a: __m256i, b: __m256i) -> __m256i {
8882 static_assert_uimm_bits!(IMM8, 8);
8883 let a: u8x32 = a.as_u8x32();
8884 let b: u8x32 = b.as_u8x32();
8885 let r: u16x16 = vdbpsadbw256(a, b, IMM8);
8886 transmute(src:r)
8887}
8888
8889/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8890///
8891/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_dbsad_epu8&expand=2112)
8892#[inline]
8893#[target_feature(enable = "avx512bw,avx512vl")]
8894#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8895#[rustc_legacy_const_generics(4)]
8896#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8897pub unsafe fn _mm256_mask_dbsad_epu8<const IMM8: i32>(
8898 src: __m256i,
8899 k: __mmask16,
8900 a: __m256i,
8901 b: __m256i,
8902) -> __m256i {
8903 static_assert_uimm_bits!(IMM8, 8);
8904 let a: u8x32 = a.as_u8x32();
8905 let b: u8x32 = b.as_u8x32();
8906 let r: u16x16 = vdbpsadbw256(a, b, IMM8);
8907 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_u16x16()))
8908}
8909
8910/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8911///
8912/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_dbsad_epu8&expand=2113)
8913#[inline]
8914#[target_feature(enable = "avx512bw,avx512vl")]
8915#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8916#[rustc_legacy_const_generics(3)]
8917#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8918pub unsafe fn _mm256_maskz_dbsad_epu8<const IMM8: i32>(
8919 k: __mmask16,
8920 a: __m256i,
8921 b: __m256i,
8922) -> __m256i {
8923 static_assert_uimm_bits!(IMM8, 8);
8924 let a: u8x32 = a.as_u8x32();
8925 let b: u8x32 = b.as_u8x32();
8926 let r: u16x16 = vdbpsadbw256(a, b, IMM8);
8927 transmute(src:simd_select_bitmask(
8928 m:k,
8929 yes:r,
8930 no:_mm256_setzero_si256().as_u16x16(),
8931 ))
8932}
8933
8934/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst. Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8935///
8936/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_dbsad_epu8&expand=2108)
8937#[inline]
8938#[target_feature(enable = "avx512bw,avx512vl")]
8939#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8940#[rustc_legacy_const_generics(2)]
8941#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8942pub unsafe fn _mm_dbsad_epu8<const IMM8: i32>(a: __m128i, b: __m128i) -> __m128i {
8943 static_assert_uimm_bits!(IMM8, 8);
8944 let a: u8x16 = a.as_u8x16();
8945 let b: u8x16 = b.as_u8x16();
8946 let r: u16x8 = vdbpsadbw128(a, b, IMM8);
8947 transmute(src:r)
8948}
8949
8950/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8951///
8952/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_dbsad_epu8&expand=2109)
8953#[inline]
8954#[target_feature(enable = "avx512bw,avx512vl")]
8955#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8956#[rustc_legacy_const_generics(4)]
8957#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8958pub unsafe fn _mm_mask_dbsad_epu8<const IMM8: i32>(
8959 src: __m128i,
8960 k: __mmask8,
8961 a: __m128i,
8962 b: __m128i,
8963) -> __m128i {
8964 static_assert_uimm_bits!(IMM8, 8);
8965 let a: u8x16 = a.as_u8x16();
8966 let b: u8x16 = b.as_u8x16();
8967 let r: u16x8 = vdbpsadbw128(a, b, IMM8);
8968 transmute(src:simd_select_bitmask(m:k, yes:r, no:src.as_u16x8()))
8969}
8970
8971/// Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in a compared to those in b, and store the 16-bit results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set). Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from a, and the last two SADs use the uppper 8-bit quadruplet of the lane from a. Quadruplets from b are selected from within 128-bit lanes according to the control in imm8, and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets.
8972///
8973/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_dbsad_epu8&expand=2110)
8974#[inline]
8975#[target_feature(enable = "avx512bw,avx512vl")]
8976#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8977#[rustc_legacy_const_generics(3)]
8978#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))]
8979pub unsafe fn _mm_maskz_dbsad_epu8<const IMM8: i32>(
8980 k: __mmask8,
8981 a: __m128i,
8982 b: __m128i,
8983) -> __m128i {
8984 static_assert_uimm_bits!(IMM8, 8);
8985 let a: u8x16 = a.as_u8x16();
8986 let b: u8x16 = b.as_u8x16();
8987 let r: u16x8 = vdbpsadbw128(a, b, IMM8);
8988 transmute(src:simd_select_bitmask(m:k, yes:r, no:_mm_setzero_si128().as_u16x8()))
8989}
8990
8991/// Set each bit of mask register k based on the most significant bit of the corresponding packed 16-bit integer in a.
8992///
8993/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi16_mask&expand=3873)
8994#[inline]
8995#[target_feature(enable = "avx512bw")]
8996#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
8997#[cfg_attr(test, assert_instr(vpmovw2m))]
8998pub unsafe fn _mm512_movepi16_mask(a: __m512i) -> __mmask32 {
8999 let filter: __m512i = _mm512_set1_epi16(1 << 15);
9000 let a: __m512i = _mm512_and_si512(a, b:filter);
9001 _mm512_cmpeq_epi16_mask(a, b:filter)
9002}
9003
9004/// Set each bit of mask register k based on the most significant bit of the corresponding packed 16-bit integer in a.
9005///
9006/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi16_mask&expand=3872)
9007#[inline]
9008#[target_feature(enable = "avx512bw,avx512vl")]
9009#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9010#[cfg_attr(test, assert_instr(vpmovw2m))]
9011pub unsafe fn _mm256_movepi16_mask(a: __m256i) -> __mmask16 {
9012 let filter: __m256i = _mm256_set1_epi16(1 << 15);
9013 let a: __m256i = _mm256_and_si256(a, b:filter);
9014 _mm256_cmpeq_epi16_mask(a, b:filter)
9015}
9016
9017/// Set each bit of mask register k based on the most significant bit of the corresponding packed 16-bit integer in a.
9018///
9019/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi16_mask&expand=3871)
9020#[inline]
9021#[target_feature(enable = "avx512bw,avx512vl")]
9022#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9023#[cfg_attr(test, assert_instr(vpmovw2m))]
9024pub unsafe fn _mm_movepi16_mask(a: __m128i) -> __mmask8 {
9025 let filter: __m128i = _mm_set1_epi16(1 << 15);
9026 let a: __m128i = _mm_and_si128(a, b:filter);
9027 _mm_cmpeq_epi16_mask(a, b:filter)
9028}
9029
9030/// Set each bit of mask register k based on the most significant bit of the corresponding packed 8-bit integer in a.
9031///
9032/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movepi8_mask&expand=3883)
9033#[inline]
9034#[target_feature(enable = "avx512bw")]
9035#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9036#[cfg_attr(test, assert_instr(vpmovb2m))]
9037pub unsafe fn _mm512_movepi8_mask(a: __m512i) -> __mmask64 {
9038 let filter: __m512i = _mm512_set1_epi8(1 << 7);
9039 let a: __m512i = _mm512_and_si512(a, b:filter);
9040 _mm512_cmpeq_epi8_mask(a, b:filter)
9041}
9042
9043/// Set each bit of mask register k based on the most significant bit of the corresponding packed 8-bit integer in a.
9044///
9045/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movepi8_mask&expand=3882)
9046#[inline]
9047#[target_feature(enable = "avx512bw,avx512vl")]
9048#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9049#[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
9050 // using vpmovb2m plus converting the mask register to a standard register.
9051pub unsafe fn _mm256_movepi8_mask(a: __m256i) -> __mmask32 {
9052 let filter: __m256i = _mm256_set1_epi8(1 << 7);
9053 let a: __m256i = _mm256_and_si256(a, b:filter);
9054 _mm256_cmpeq_epi8_mask(a, b:filter)
9055}
9056
9057/// Set each bit of mask register k based on the most significant bit of the corresponding packed 8-bit integer in a.
9058///
9059/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movepi8_mask&expand=3881)
9060#[inline]
9061#[target_feature(enable = "avx512bw,avx512vl")]
9062#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9063#[cfg_attr(test, assert_instr(vpmovmskb))] // should be vpmovb2m but compiled to vpmovmskb in the test shim because that takes less cycles than
9064 // using vpmovb2m plus converting the mask register to a standard register.
9065pub unsafe fn _mm_movepi8_mask(a: __m128i) -> __mmask16 {
9066 let filter: __m128i = _mm_set1_epi8(1 << 7);
9067 let a: __m128i = _mm_and_si128(a, b:filter);
9068 _mm_cmpeq_epi8_mask(a, b:filter)
9069}
9070
9071/// Set each packed 16-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9072///
9073/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movm_epi16&expand=3886)
9074#[inline]
9075#[target_feature(enable = "avx512bw")]
9076#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9077#[cfg_attr(test, assert_instr(vpmovm2w))]
9078pub unsafe fn _mm512_movm_epi16(k: __mmask32) -> __m512i {
9079 let one: i16x32 = _mm512_set1_epi16__m512i(
9080 1 << 15
9081 | 1 << 14
9082 | 1 << 13
9083 | 1 << 12
9084 | 1 << 11
9085 | 1 << 10
9086 | 1 << 9
9087 | 1 << 8
9088 | 1 << 7
9089 | 1 << 6
9090 | 1 << 5
9091 | 1 << 4
9092 | 1 << 3
9093 | 1 << 2
9094 | 1 << 1
9095 | 1 << 0,
9096 )
9097 .as_i16x32();
9098 let zero: i16x32 = _mm512_setzero_si512().as_i16x32();
9099 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9100}
9101
9102/// Set each packed 16-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9103///
9104/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movm_epi16&expand=3885)
9105#[inline]
9106#[target_feature(enable = "avx512bw,avx512vl")]
9107#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9108#[cfg_attr(test, assert_instr(vpmovm2w))]
9109pub unsafe fn _mm256_movm_epi16(k: __mmask16) -> __m256i {
9110 let one: i16x16 = _mm256_set1_epi16__m256i(
9111 1 << 15
9112 | 1 << 14
9113 | 1 << 13
9114 | 1 << 12
9115 | 1 << 11
9116 | 1 << 10
9117 | 1 << 9
9118 | 1 << 8
9119 | 1 << 7
9120 | 1 << 6
9121 | 1 << 5
9122 | 1 << 4
9123 | 1 << 3
9124 | 1 << 2
9125 | 1 << 1
9126 | 1 << 0,
9127 )
9128 .as_i16x16();
9129 let zero: i16x16 = _mm256_setzero_si256().as_i16x16();
9130 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9131}
9132
9133/// Set each packed 16-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9134///
9135/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movm_epi16&expand=3884)
9136#[inline]
9137#[target_feature(enable = "avx512bw,avx512vl")]
9138#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9139#[cfg_attr(test, assert_instr(vpmovm2w))]
9140pub unsafe fn _mm_movm_epi16(k: __mmask8) -> __m128i {
9141 let one: i16x8 = _mm_set1_epi16__m128i(
9142 1 << 15
9143 | 1 << 14
9144 | 1 << 13
9145 | 1 << 12
9146 | 1 << 11
9147 | 1 << 10
9148 | 1 << 9
9149 | 1 << 8
9150 | 1 << 7
9151 | 1 << 6
9152 | 1 << 5
9153 | 1 << 4
9154 | 1 << 3
9155 | 1 << 2
9156 | 1 << 1
9157 | 1 << 0,
9158 )
9159 .as_i16x8();
9160 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
9161 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9162}
9163
9164/// Set each packed 8-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9165///
9166/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_movm_epi8&expand=3895)
9167#[inline]
9168#[target_feature(enable = "avx512bw")]
9169#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9170#[cfg_attr(test, assert_instr(vpmovm2b))]
9171pub unsafe fn _mm512_movm_epi8(k: __mmask64) -> __m512i {
9172 let one: i8x64 =
9173 _mm512_set1_epi8__m512i(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
9174 .as_i8x64();
9175 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
9176 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9177}
9178
9179/// Set each packed 8-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9180///
9181/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_movm_epi8&expand=3894)
9182#[inline]
9183#[target_feature(enable = "avx512bw,avx512vl")]
9184#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9185#[cfg_attr(test, assert_instr(vpmovm2b))]
9186pub unsafe fn _mm256_movm_epi8(k: __mmask32) -> __m256i {
9187 let one: i8x32 =
9188 _mm256_set1_epi8__m256i(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
9189 .as_i8x32();
9190 let zero: i8x32 = _mm256_setzero_si256().as_i8x32();
9191 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9192}
9193
9194/// Set each packed 8-bit integer in dst to all ones or all zeros based on the value of the corresponding bit in k.
9195///
9196/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movm_epi8&expand=3893)
9197#[inline]
9198#[target_feature(enable = "avx512bw,avx512vl")]
9199#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9200#[cfg_attr(test, assert_instr(vpmovm2b))]
9201pub unsafe fn _mm_movm_epi8(k: __mmask16) -> __m128i {
9202 let one: i8x16 = _mm_set1_epi8__m128i(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0)
9203 .as_i8x16();
9204 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
9205 transmute(src:simd_select_bitmask(m:k, yes:one, no:zero))
9206}
9207
9208/// Add 32-bit masks in a and b, and store the result in k.
9209///
9210/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask32&expand=3207)
9211#[inline]
9212#[target_feature(enable = "avx512bw")]
9213#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9214pub unsafe fn _kadd_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9215 a + b
9216}
9217
9218/// Add 64-bit masks in a and b, and store the result in k.
9219///
9220/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kadd_mask64&expand=3208)
9221#[inline]
9222#[target_feature(enable = "avx512bw")]
9223#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9224pub unsafe fn _kadd_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9225 a + b
9226}
9227
9228/// Compute the bitwise AND of 32-bit masks a and b, and store the result in k.
9229///
9230/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kand_mask32&expand=3213)
9231#[inline]
9232#[target_feature(enable = "avx512bw")]
9233#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9234pub unsafe fn _kand_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9235 a & b
9236}
9237
9238/// Compute the bitwise AND of 64-bit masks a and b, and store the result in k.
9239///
9240/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kand_mask64&expand=3214)
9241#[inline]
9242#[target_feature(enable = "avx512bw")]
9243#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9244pub unsafe fn _kand_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9245 a & b
9246}
9247
9248/// Compute the bitwise NOT of 32-bit mask a, and store the result in k.
9249///
9250/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_knot_mask32&expand=3234)
9251#[inline]
9252#[target_feature(enable = "avx512bw")]
9253#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9254pub unsafe fn _knot_mask32(a: __mmask32) -> __mmask32 {
9255 a ^ 0b11111111_11111111_11111111_11111111
9256}
9257
9258/// Compute the bitwise NOT of 64-bit mask a, and store the result in k.
9259///
9260/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_knot_mask64&expand=3235)
9261#[inline]
9262#[target_feature(enable = "avx512bw")]
9263#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9264pub unsafe fn _knot_mask64(a: __mmask64) -> __mmask64 {
9265 a ^ 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
9266}
9267
9268/// Compute the bitwise NOT of 32-bit masks a and then AND with b, and store the result in k.
9269///
9270/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kandn_mask32&expand=3219)
9271#[inline]
9272#[target_feature(enable = "avx512bw")]
9273#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9274pub unsafe fn _kandn_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9275 _knot_mask32(a) & b
9276}
9277
9278/// Compute the bitwise NOT of 64-bit masks a and then AND with b, and store the result in k.
9279///
9280/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kandn_mask64&expand=3220)
9281#[inline]
9282#[target_feature(enable = "avx512bw")]
9283#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9284pub unsafe fn _kandn_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9285 _knot_mask64(a) & b
9286}
9287
9288/// Compute the bitwise OR of 32-bit masks a and b, and store the result in k.
9289///
9290/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kor_mask32&expand=3240)
9291#[inline]
9292#[target_feature(enable = "avx512bw")]
9293#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9294pub unsafe fn _kor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9295 a | b
9296}
9297
9298/// Compute the bitwise OR of 64-bit masks a and b, and store the result in k.
9299///
9300/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kor_mask64&expand=3241)
9301#[inline]
9302#[target_feature(enable = "avx512bw")]
9303#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9304pub unsafe fn _kor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9305 a | b
9306}
9307
9308/// Compute the bitwise XOR of 32-bit masks a and b, and store the result in k.
9309///
9310/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxor_mask32&expand=3292)
9311#[inline]
9312#[target_feature(enable = "avx512bw")]
9313#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9314pub unsafe fn _kxor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9315 a ^ b
9316}
9317
9318/// Compute the bitwise XOR of 64-bit masks a and b, and store the result in k.
9319///
9320/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxor_mask64&expand=3293)
9321#[inline]
9322#[target_feature(enable = "avx512bw")]
9323#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9324pub unsafe fn _kxor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9325 a ^ b
9326}
9327
9328/// Compute the bitwise XNOR of 32-bit masks a and b, and store the result in k.
9329///
9330/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxnor_mask32&expand=3286)
9331#[inline]
9332#[target_feature(enable = "avx512bw")]
9333#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9334pub unsafe fn _kxnor_mask32(a: __mmask32, b: __mmask32) -> __mmask32 {
9335 _knot_mask32(a ^ b)
9336}
9337
9338/// Compute the bitwise XNOR of 64-bit masks a and b, and store the result in k.
9339///
9340/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_kxnor_mask64&expand=3287)
9341#[inline]
9342#[target_feature(enable = "avx512bw")]
9343#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9344pub unsafe fn _kxnor_mask64(a: __mmask64, b: __mmask64) -> __mmask64 {
9345 _knot_mask64(a ^ b)
9346}
9347
9348/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst.
9349///
9350/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi16_epi8&expand=1407)
9351#[inline]
9352#[target_feature(enable = "avx512bw")]
9353#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9354#[cfg_attr(test, assert_instr(vpmovwb))]
9355pub unsafe fn _mm512_cvtepi16_epi8(a: __m512i) -> __m256i {
9356 let a: i16x32 = a.as_i16x32();
9357 transmute::<i8x32, _>(src:simd_cast(a))
9358}
9359
9360/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9361///
9362/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_epi8&expand=1408)
9363#[inline]
9364#[target_feature(enable = "avx512bw")]
9365#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9366#[cfg_attr(test, assert_instr(vpmovwb))]
9367pub unsafe fn _mm512_mask_cvtepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
9368 let convert: i8x32 = _mm512_cvtepi16_epi8(a).as_i8x32();
9369 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i8x32()))
9370}
9371
9372/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9373///
9374/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi16_epi8&expand=1409)
9375#[inline]
9376#[target_feature(enable = "avx512bw")]
9377#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9378#[cfg_attr(test, assert_instr(vpmovwb))]
9379pub unsafe fn _mm512_maskz_cvtepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
9380 let convert: i8x32 = _mm512_cvtepi16_epi8(a).as_i8x32();
9381 transmute(src:simd_select_bitmask(
9382 m:k,
9383 yes:convert,
9384 no:_mm256_setzero_si256().as_i8x32(),
9385 ))
9386}
9387
9388/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst.
9389///
9390/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtepi16_epi8&expand=1404)
9391#[inline]
9392#[target_feature(enable = "avx512bw,avx512vl")]
9393#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9394#[cfg_attr(test, assert_instr(vpmovwb))]
9395pub unsafe fn _mm256_cvtepi16_epi8(a: __m256i) -> __m128i {
9396 let a: i16x16 = a.as_i16x16();
9397 transmute::<i8x16, _>(src:simd_cast(a))
9398}
9399
9400/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9401///
9402/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_epi8&expand=1405)
9403#[inline]
9404#[target_feature(enable = "avx512bw,avx512vl")]
9405#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9406#[cfg_attr(test, assert_instr(vpmovwb))]
9407pub unsafe fn _mm256_mask_cvtepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
9408 let convert: i8x16 = _mm256_cvtepi16_epi8(a).as_i8x16();
9409 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i8x16()))
9410}
9411
9412/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9413///
9414/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi16_epi8&expand=1406)
9415#[inline]
9416#[target_feature(enable = "avx512bw,avx512vl")]
9417#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9418#[cfg_attr(test, assert_instr(vpmovwb))]
9419pub unsafe fn _mm256_maskz_cvtepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
9420 let convert: i8x16 = _mm256_cvtepi16_epi8(a).as_i8x16();
9421 transmute(src:simd_select_bitmask(
9422 m:k,
9423 yes:convert,
9424 no:_mm_setzero_si128().as_i8x16(),
9425 ))
9426}
9427
9428/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst.
9429///
9430/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi16_epi8&expand=1401)
9431#[inline]
9432#[target_feature(enable = "avx512bw,avx512vl")]
9433#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9434#[cfg_attr(test, assert_instr(vpmovwb))]
9435pub unsafe fn _mm_cvtepi16_epi8(a: __m128i) -> __m128i {
9436 let a: i16x8 = a.as_i16x8();
9437 let zero: i16x8 = _mm_setzero_si128().as_i16x8();
9438 let v256: i16x16 = simd_shuffle!(a, zero, [0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 8, 8, 8, 8, 8, 8]);
9439 transmute::<i8x16, _>(src:simd_cast(v256))
9440}
9441
9442/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9443///
9444/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_epi8&expand=1402)
9445#[inline]
9446#[target_feature(enable = "avx512bw,avx512vl")]
9447#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9448#[cfg_attr(test, assert_instr(vpmovwb))]
9449pub unsafe fn _mm_mask_cvtepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
9450 let convert: i8x16 = _mm_cvtepi16_epi8(a).as_i8x16();
9451 let k: __mmask16 = 0b11111111_11111111 & k as __mmask16;
9452 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i8x16()))
9453}
9454
9455/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9456///
9457/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi16_epi8&expand=1403)
9458#[inline]
9459#[target_feature(enable = "avx512bw,avx512vl")]
9460#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9461#[cfg_attr(test, assert_instr(vpmovwb))]
9462pub unsafe fn _mm_maskz_cvtepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
9463 let convert: i8x16 = _mm_cvtepi16_epi8(a).as_i8x16();
9464 let k: __mmask16 = 0b11111111_11111111 & k as __mmask16;
9465 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
9466 transmute(src:simd_select_bitmask(m:k, yes:convert, no:zero))
9467}
9468
9469/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
9470///
9471/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtsepi16_epi8&expand=1807)
9472#[inline]
9473#[target_feature(enable = "avx512bw")]
9474#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9475#[cfg_attr(test, assert_instr(vpmovswb))]
9476pub unsafe fn _mm512_cvtsepi16_epi8(a: __m512i) -> __m256i {
9477 transmute(src:vpmovswb(
9478 a:a.as_i16x32(),
9479 src:_mm256_setzero_si256().as_i8x32(),
9480 mask:0b11111111_11111111_11111111_11111111,
9481 ))
9482}
9483
9484/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9485///
9486/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi16_epi8&expand=1808)
9487#[inline]
9488#[target_feature(enable = "avx512bw")]
9489#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9490#[cfg_attr(test, assert_instr(vpmovswb))]
9491pub unsafe fn _mm512_mask_cvtsepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
9492 transmute(src:vpmovswb(a:a.as_i16x32(), src:src.as_i8x32(), mask:k))
9493}
9494
9495/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9496///
9497/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtsepi16_epi8&expand=1809)
9498#[inline]
9499#[target_feature(enable = "avx512bw")]
9500#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9501#[cfg_attr(test, assert_instr(vpmovswb))]
9502pub unsafe fn _mm512_maskz_cvtsepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
9503 transmute(src:vpmovswb(
9504 a:a.as_i16x32(),
9505 src:_mm256_setzero_si256().as_i8x32(),
9506 mask:k,
9507 ))
9508}
9509
9510/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
9511///
9512/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtsepi16_epi8&expand=1804)
9513#[inline]
9514#[target_feature(enable = "avx512bw,avx512vl")]
9515#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9516#[cfg_attr(test, assert_instr(vpmovswb))]
9517pub unsafe fn _mm256_cvtsepi16_epi8(a: __m256i) -> __m128i {
9518 transmute(src:vpmovswb256(
9519 a:a.as_i16x16(),
9520 src:_mm_setzero_si128().as_i8x16(),
9521 mask:0b11111111_11111111,
9522 ))
9523}
9524
9525/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9526///
9527/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi16_epi8&expand=1805)
9528#[inline]
9529#[target_feature(enable = "avx512bw,avx512vl")]
9530#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9531#[cfg_attr(test, assert_instr(vpmovswb))]
9532pub unsafe fn _mm256_mask_cvtsepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
9533 transmute(src:vpmovswb256(a:a.as_i16x16(), src:src.as_i8x16(), mask:k))
9534}
9535
9536/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9537///
9538/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtsepi16_epi8&expand=1806)
9539#[inline]
9540#[target_feature(enable = "avx512bw,avx512vl")]
9541#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9542#[cfg_attr(test, assert_instr(vpmovswb))]
9543pub unsafe fn _mm256_maskz_cvtsepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
9544 transmute(src:vpmovswb256(
9545 a:a.as_i16x16(),
9546 src:_mm_setzero_si128().as_i8x16(),
9547 mask:k,
9548 ))
9549}
9550
9551/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst.
9552///
9553/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsepi16_epi8&expand=1801)
9554#[inline]
9555#[target_feature(enable = "avx512bw,avx512vl")]
9556#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9557#[cfg_attr(test, assert_instr(vpmovswb))]
9558pub unsafe fn _mm_cvtsepi16_epi8(a: __m128i) -> __m128i {
9559 transmute(src:vpmovswb128(
9560 a:a.as_i16x8(),
9561 src:_mm_setzero_si128().as_i8x16(),
9562 mask:0b11111111,
9563 ))
9564}
9565
9566/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9567///
9568/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi16_epi8&expand=1802)
9569#[inline]
9570#[target_feature(enable = "avx512bw,avx512vl")]
9571#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9572#[cfg_attr(test, assert_instr(vpmovswb))]
9573pub unsafe fn _mm_mask_cvtsepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
9574 transmute(src:vpmovswb128(a:a.as_i16x8(), src:src.as_i8x16(), mask:k))
9575}
9576
9577/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9578///
9579/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtsepi16_epi8&expand=1803)
9580#[inline]
9581#[target_feature(enable = "avx512bw,avx512vl")]
9582#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9583#[cfg_attr(test, assert_instr(vpmovswb))]
9584pub unsafe fn _mm_maskz_cvtsepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
9585 transmute(src:vpmovswb128(a:a.as_i16x8(), src:_mm_setzero_si128().as_i8x16(), mask:k))
9586}
9587
9588/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst.
9589///
9590/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtusepi16_epi8&expand=2042)
9591#[inline]
9592#[target_feature(enable = "avx512bw")]
9593#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9594#[cfg_attr(test, assert_instr(vpmovuswb))]
9595pub unsafe fn _mm512_cvtusepi16_epi8(a: __m512i) -> __m256i {
9596 transmute(src:vpmovuswb(
9597 a:a.as_u16x32(),
9598 src:_mm256_setzero_si256().as_u8x32(),
9599 mask:0b11111111_11111111_11111111_11111111,
9600 ))
9601}
9602
9603/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9604///
9605/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi16_epi8&expand=2043)
9606#[inline]
9607#[target_feature(enable = "avx512bw")]
9608#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9609#[cfg_attr(test, assert_instr(vpmovuswb))]
9610pub unsafe fn _mm512_mask_cvtusepi16_epi8(src: __m256i, k: __mmask32, a: __m512i) -> __m256i {
9611 transmute(src:vpmovuswb(a:a.as_u16x32(), src:src.as_u8x32(), mask:k))
9612}
9613
9614/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9615///
9616/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtusepi16_epi8&expand=2044)
9617#[inline]
9618#[target_feature(enable = "avx512bw")]
9619#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9620#[cfg_attr(test, assert_instr(vpmovuswb))]
9621pub unsafe fn _mm512_maskz_cvtusepi16_epi8(k: __mmask32, a: __m512i) -> __m256i {
9622 transmute(src:vpmovuswb(
9623 a:a.as_u16x32(),
9624 src:_mm256_setzero_si256().as_u8x32(),
9625 mask:k,
9626 ))
9627}
9628
9629/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst.
9630///
9631/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_cvtusepi16_epi8&expand=2039)
9632#[inline]
9633#[target_feature(enable = "avx512bw,avx512vl")]
9634#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9635#[cfg_attr(test, assert_instr(vpmovuswb))]
9636pub unsafe fn _mm256_cvtusepi16_epi8(a: __m256i) -> __m128i {
9637 transmute(src:vpmovuswb256(
9638 a:a.as_u16x16(),
9639 src:_mm_setzero_si128().as_u8x16(),
9640 mask:0b11111111_11111111,
9641 ))
9642}
9643
9644/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9645///
9646/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi16_epi8&expand=2040)
9647#[inline]
9648#[target_feature(enable = "avx512bw,avx512vl")]
9649#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9650#[cfg_attr(test, assert_instr(vpmovuswb))]
9651pub unsafe fn _mm256_mask_cvtusepi16_epi8(src: __m128i, k: __mmask16, a: __m256i) -> __m128i {
9652 transmute(src:vpmovuswb256(a:a.as_u16x16(), src:src.as_u8x16(), mask:k))
9653}
9654
9655/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9656///
9657/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtusepi16_epi8&expand=2041)
9658#[inline]
9659#[target_feature(enable = "avx512bw,avx512vl")]
9660#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9661#[cfg_attr(test, assert_instr(vpmovuswb))]
9662pub unsafe fn _mm256_maskz_cvtusepi16_epi8(k: __mmask16, a: __m256i) -> __m128i {
9663 transmute(src:vpmovuswb256(
9664 a:a.as_u16x16(),
9665 src:_mm_setzero_si128().as_u8x16(),
9666 mask:k,
9667 ))
9668}
9669
9670/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst.
9671///
9672/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtusepi16_epi8&expand=2036)
9673#[inline]
9674#[target_feature(enable = "avx512bw,avx512vl")]
9675#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9676#[cfg_attr(test, assert_instr(vpmovuswb))]
9677pub unsafe fn _mm_cvtusepi16_epi8(a: __m128i) -> __m128i {
9678 transmute(src:vpmovuswb128(
9679 a:a.as_u16x8(),
9680 src:_mm_setzero_si128().as_u8x16(),
9681 mask:0b11111111,
9682 ))
9683}
9684
9685/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9686///
9687/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi16_epi8&expand=2037)
9688#[inline]
9689#[target_feature(enable = "avx512bw,avx512vl")]
9690#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9691#[cfg_attr(test, assert_instr(vpmovuswb))]
9692pub unsafe fn _mm_mask_cvtusepi16_epi8(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
9693 transmute(src:vpmovuswb128(a:a.as_u16x8(), src:src.as_u8x16(), mask:k))
9694}
9695
9696/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9697///
9698/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtusepi16_epi8&expand=2038)
9699#[inline]
9700#[target_feature(enable = "avx512bw,avx512vl")]
9701#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9702#[cfg_attr(test, assert_instr(vpmovuswb))]
9703pub unsafe fn _mm_maskz_cvtusepi16_epi8(k: __mmask8, a: __m128i) -> __m128i {
9704 transmute(src:vpmovuswb128(
9705 a:a.as_u16x8(),
9706 src:_mm_setzero_si128().as_u8x16(),
9707 mask:k,
9708 ))
9709}
9710
9711/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst.
9712///
9713/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepi8_epi16&expand=1526)
9714#[inline]
9715#[target_feature(enable = "avx512bw")]
9716#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9717#[cfg_attr(test, assert_instr(vpmovsxbw))]
9718pub unsafe fn _mm512_cvtepi8_epi16(a: __m256i) -> __m512i {
9719 let a: i8x32 = a.as_i8x32();
9720 transmute::<i16x32, _>(src:simd_cast(a))
9721}
9722
9723/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9724///
9725/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi8_epi16&expand=1527)
9726#[inline]
9727#[target_feature(enable = "avx512bw")]
9728#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9729#[cfg_attr(test, assert_instr(vpmovsxbw))]
9730pub unsafe fn _mm512_mask_cvtepi8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
9731 let convert: i16x32 = _mm512_cvtepi8_epi16(a).as_i16x32();
9732 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x32()))
9733}
9734
9735/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9736///
9737/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepi8_epi16&expand=1528)
9738#[inline]
9739#[target_feature(enable = "avx512bw")]
9740#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9741#[cfg_attr(test, assert_instr(vpmovsxbw))]
9742pub unsafe fn _mm512_maskz_cvtepi8_epi16(k: __mmask32, a: __m256i) -> __m512i {
9743 let convert: i16x32 = _mm512_cvtepi8_epi16(a).as_i16x32();
9744 transmute(src:simd_select_bitmask(
9745 m:k,
9746 yes:convert,
9747 no:_mm512_setzero_si512().as_i16x32(),
9748 ))
9749}
9750
9751/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9752///
9753/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi8_epi16&expand=1524)
9754#[inline]
9755#[target_feature(enable = "avx512bw,avx512vl")]
9756#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9757#[cfg_attr(test, assert_instr(vpmovsxbw))]
9758pub unsafe fn _mm256_mask_cvtepi8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
9759 let convert: i16x16 = _mm256_cvtepi8_epi16(a).as_i16x16();
9760 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x16()))
9761}
9762
9763/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9764///
9765/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepi8_epi16&expand=1525)
9766#[inline]
9767#[target_feature(enable = "avx512bw,avx512vl")]
9768#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9769#[cfg_attr(test, assert_instr(vpmovsxbw))]
9770pub unsafe fn _mm256_maskz_cvtepi8_epi16(k: __mmask16, a: __m128i) -> __m256i {
9771 let convert: i16x16 = _mm256_cvtepi8_epi16(a).as_i16x16();
9772 transmute(src:simd_select_bitmask(
9773 m:k,
9774 yes:convert,
9775 no:_mm256_setzero_si256().as_i16x16(),
9776 ))
9777}
9778
9779/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9780///
9781/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi8_epi16&expand=1521)
9782#[inline]
9783#[target_feature(enable = "avx512bw,avx512vl")]
9784#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9785#[cfg_attr(test, assert_instr(vpmovsxbw))]
9786pub unsafe fn _mm_mask_cvtepi8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
9787 let convert: i16x8 = _mm_cvtepi8_epi16(a).as_i16x8();
9788 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x8()))
9789}
9790
9791/// Sign extend packed 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9792///
9793/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepi8_epi16&expand=1522)
9794#[inline]
9795#[target_feature(enable = "avx512bw,avx512vl")]
9796#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9797#[cfg_attr(test, assert_instr(vpmovsxbw))]
9798pub unsafe fn _mm_maskz_cvtepi8_epi16(k: __mmask8, a: __m128i) -> __m128i {
9799 let convert: i16x8 = _mm_cvtepi8_epi16(a).as_i16x8();
9800 transmute(src:simd_select_bitmask(
9801 m:k,
9802 yes:convert,
9803 no:_mm_setzero_si128().as_i16x8(),
9804 ))
9805}
9806
9807/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst.
9808///
9809/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_cvtepu8_epi16&expand=1612)
9810#[inline]
9811#[target_feature(enable = "avx512bw")]
9812#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9813#[cfg_attr(test, assert_instr(vpmovzxbw))]
9814pub unsafe fn _mm512_cvtepu8_epi16(a: __m256i) -> __m512i {
9815 let a: u8x32 = a.as_u8x32();
9816 transmute::<i16x32, _>(src:simd_cast(a))
9817}
9818
9819/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9820///
9821/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepu8_epi16&expand=1613)
9822#[inline]
9823#[target_feature(enable = "avx512bw")]
9824#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9825#[cfg_attr(test, assert_instr(vpmovzxbw))]
9826pub unsafe fn _mm512_mask_cvtepu8_epi16(src: __m512i, k: __mmask32, a: __m256i) -> __m512i {
9827 let convert: i16x32 = _mm512_cvtepu8_epi16(a).as_i16x32();
9828 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x32()))
9829}
9830
9831/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9832///
9833/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_cvtepu8_epi16&expand=1614)
9834#[inline]
9835#[target_feature(enable = "avx512bw")]
9836#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9837#[cfg_attr(test, assert_instr(vpmovzxbw))]
9838pub unsafe fn _mm512_maskz_cvtepu8_epi16(k: __mmask32, a: __m256i) -> __m512i {
9839 let convert: i16x32 = _mm512_cvtepu8_epi16(a).as_i16x32();
9840 transmute(src:simd_select_bitmask(
9841 m:k,
9842 yes:convert,
9843 no:_mm512_setzero_si512().as_i16x32(),
9844 ))
9845}
9846
9847/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9848///
9849/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepu8_epi16&expand=1610)
9850#[inline]
9851#[target_feature(enable = "avx512bw,avx512vl")]
9852#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9853#[cfg_attr(test, assert_instr(vpmovzxbw))]
9854pub unsafe fn _mm256_mask_cvtepu8_epi16(src: __m256i, k: __mmask16, a: __m128i) -> __m256i {
9855 let convert: i16x16 = _mm256_cvtepu8_epi16(a).as_i16x16();
9856 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x16()))
9857}
9858
9859/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9860///
9861/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_cvtepu8_epi16&expand=1611)
9862#[inline]
9863#[target_feature(enable = "avx512bw,avx512vl")]
9864#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9865#[cfg_attr(test, assert_instr(vpmovzxbw))]
9866pub unsafe fn _mm256_maskz_cvtepu8_epi16(k: __mmask16, a: __m128i) -> __m256i {
9867 let convert: i16x16 = _mm256_cvtepu8_epi16(a).as_i16x16();
9868 transmute(src:simd_select_bitmask(
9869 m:k,
9870 yes:convert,
9871 no:_mm256_setzero_si256().as_i16x16(),
9872 ))
9873}
9874
9875/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
9876///
9877/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepu8_epi16&expand=1607)
9878#[inline]
9879#[target_feature(enable = "avx512bw,avx512vl")]
9880#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9881#[cfg_attr(test, assert_instr(vpmovzxbw))]
9882pub unsafe fn _mm_mask_cvtepu8_epi16(src: __m128i, k: __mmask8, a: __m128i) -> __m128i {
9883 let convert: i16x8 = _mm_cvtepu8_epi16(a).as_i16x8();
9884 transmute(src:simd_select_bitmask(m:k, yes:convert, no:src.as_i16x8()))
9885}
9886
9887/// Zero extend packed unsigned 8-bit integers in a to packed 16-bit integers, and store the results in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
9888///
9889/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_cvtepu8_epi16&expand=1608)
9890#[inline]
9891#[target_feature(enable = "avx512bw,avx512vl")]
9892#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9893#[cfg_attr(test, assert_instr(vpmovzxbw))]
9894pub unsafe fn _mm_maskz_cvtepu8_epi16(k: __mmask8, a: __m128i) -> __m128i {
9895 let convert: i16x8 = _mm_cvtepu8_epi16(a).as_i16x8();
9896 transmute(src:simd_select_bitmask(
9897 m:k,
9898 yes:convert,
9899 no:_mm_setzero_si128().as_i16x8(),
9900 ))
9901}
9902
9903/// Shift 128-bit lanes in a left by imm8 bytes while shifting in zeros, and store the results in dst.
9904///
9905/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_bslli_epi128&expand=591)
9906#[inline]
9907#[target_feature(enable = "avx512bw")]
9908#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
9909#[cfg_attr(test, assert_instr(vpslldq, IMM8 = 3))]
9910#[rustc_legacy_const_generics(1)]
9911pub unsafe fn _mm512_bslli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
9912 static_assert_uimm_bits!(IMM8, 8);
9913 const fn mask(shift: i32, i: u32) -> u32 {
9914 let shift = shift as u32 & 0xff;
9915 if shift > 15 || i % 16 < shift {
9916 0
9917 } else {
9918 64 + (i - shift)
9919 }
9920 }
9921 let a = a.as_i8x64();
9922 let zero = _mm512_setzero_si512().as_i8x64();
9923 let r: i8x64 = simd_shuffle!(
9924 zero,
9925 a,
9926 [
9927 mask(IMM8, 0),
9928 mask(IMM8, 1),
9929 mask(IMM8, 2),
9930 mask(IMM8, 3),
9931 mask(IMM8, 4),
9932 mask(IMM8, 5),
9933 mask(IMM8, 6),
9934 mask(IMM8, 7),
9935 mask(IMM8, 8),
9936 mask(IMM8, 9),
9937 mask(IMM8, 10),
9938 mask(IMM8, 11),
9939 mask(IMM8, 12),
9940 mask(IMM8, 13),
9941 mask(IMM8, 14),
9942 mask(IMM8, 15),
9943 mask(IMM8, 16),
9944 mask(IMM8, 17),
9945 mask(IMM8, 18),
9946 mask(IMM8, 19),
9947 mask(IMM8, 20),
9948 mask(IMM8, 21),
9949 mask(IMM8, 22),
9950 mask(IMM8, 23),
9951 mask(IMM8, 24),
9952 mask(IMM8, 25),
9953 mask(IMM8, 26),
9954 mask(IMM8, 27),
9955 mask(IMM8, 28),
9956 mask(IMM8, 29),
9957 mask(IMM8, 30),
9958 mask(IMM8, 31),
9959 mask(IMM8, 32),
9960 mask(IMM8, 33),
9961 mask(IMM8, 34),
9962 mask(IMM8, 35),
9963 mask(IMM8, 36),
9964 mask(IMM8, 37),
9965 mask(IMM8, 38),
9966 mask(IMM8, 39),
9967 mask(IMM8, 40),
9968 mask(IMM8, 41),
9969 mask(IMM8, 42),
9970 mask(IMM8, 43),
9971 mask(IMM8, 44),
9972 mask(IMM8, 45),
9973 mask(IMM8, 46),
9974 mask(IMM8, 47),
9975 mask(IMM8, 48),
9976 mask(IMM8, 49),
9977 mask(IMM8, 50),
9978 mask(IMM8, 51),
9979 mask(IMM8, 52),
9980 mask(IMM8, 53),
9981 mask(IMM8, 54),
9982 mask(IMM8, 55),
9983 mask(IMM8, 56),
9984 mask(IMM8, 57),
9985 mask(IMM8, 58),
9986 mask(IMM8, 59),
9987 mask(IMM8, 60),
9988 mask(IMM8, 61),
9989 mask(IMM8, 62),
9990 mask(IMM8, 63),
9991 ],
9992 );
9993 transmute(r)
9994}
9995
9996/// Shift 128-bit lanes in a right by imm8 bytes while shifting in zeros, and store the results in dst.
9997///
9998/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_bsrli_epi128&expand=594)
9999#[inline]
10000#[target_feature(enable = "avx512bw")]
10001#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10002#[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 3))]
10003#[rustc_legacy_const_generics(1)]
10004pub unsafe fn _mm512_bsrli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
10005 static_assert_uimm_bits!(IMM8, 8);
10006 let a = a.as_i8x64();
10007 let zero = _mm512_setzero_si512().as_i8x64();
10008 let r: i8x64 = match IMM8 % 16 {
10009 0 => simd_shuffle!(
10010 a,
10011 zero,
10012 [
10013 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
10014 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
10015 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
10016 ],
10017 ),
10018 1 => simd_shuffle!(
10019 a,
10020 zero,
10021 [
10022 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 17, 18, 19, 20, 21, 22, 23,
10023 24, 25, 26, 27, 28, 29, 30, 31, 80, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
10024 45, 46, 47, 96, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112,
10025 ],
10026 ),
10027 2 => simd_shuffle!(
10028 a,
10029 zero,
10030 [
10031 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 18, 19, 20, 21, 22, 23, 24,
10032 25, 26, 27, 28, 29, 30, 31, 80, 81, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10033 46, 47, 96, 97, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113,
10034 ],
10035 ),
10036 3 => simd_shuffle!(
10037 a,
10038 zero,
10039 [
10040 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 19, 20, 21, 22, 23, 24,
10041 25, 26, 27, 28, 29, 30, 31, 80, 81, 82, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10042 46, 47, 96, 97, 98, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113,
10043 114,
10044 ],
10045 ),
10046 4 => simd_shuffle!(
10047 a,
10048 zero,
10049 [
10050 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 20, 21, 22, 23, 24, 25,
10051 26, 27, 28, 29, 30, 31, 80, 81, 82, 83, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,
10052 47, 96, 97, 98, 99, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114,
10053 115,
10054 ],
10055 ),
10056 5 => simd_shuffle!(
10057 a,
10058 zero,
10059 [
10060 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 21, 22, 23, 24, 25, 26,
10061 27, 28, 29, 30, 31, 80, 81, 82, 83, 84, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
10062 96, 97, 98, 99, 100, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114,
10063 115, 116,
10064 ],
10065 ),
10066 6 => simd_shuffle!(
10067 a,
10068 zero,
10069 [
10070 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 22, 23, 24, 25, 26, 27,
10071 28, 29, 30, 31, 80, 81, 82, 83, 84, 85, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 96,
10072 97, 98, 99, 100, 101, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10073 116, 117,
10074 ],
10075 ),
10076 7 => simd_shuffle!(
10077 a,
10078 zero,
10079 [
10080 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 23, 24, 25, 26, 27,
10081 28, 29, 30, 31, 80, 81, 82, 83, 84, 85, 86, 39, 40, 41, 42, 43, 44, 45, 46, 47, 96,
10082 97, 98, 99, 100, 101, 102, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10083 116, 117, 118,
10084 ],
10085 ),
10086 8 => simd_shuffle!(
10087 a,
10088 zero,
10089 [
10090 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 24, 25, 26, 27, 28,
10091 29, 30, 31, 80, 81, 82, 83, 84, 85, 86, 87, 40, 41, 42, 43, 44, 45, 46, 47, 96, 97,
10092 98, 99, 100, 101, 102, 103, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10093 116, 117, 118, 119,
10094 ],
10095 ),
10096 9 => simd_shuffle!(
10097 a,
10098 zero,
10099 [
10100 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 25, 26, 27, 28, 29,
10101 30, 31, 80, 81, 82, 83, 84, 85, 86, 87, 88, 41, 42, 43, 44, 45, 46, 47, 96, 97, 98,
10102 99, 100, 101, 102, 103, 104, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116,
10103 117, 118, 119, 120,
10104 ],
10105 ),
10106 10 => simd_shuffle!(
10107 a,
10108 zero,
10109 [
10110 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 26, 27, 28, 29, 30,
10111 31, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 42, 43, 44, 45, 46, 47, 96, 97, 98, 99,
10112 100, 101, 102, 103, 104, 105, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116, 117,
10113 118, 119, 120, 121,
10114 ],
10115 ),
10116 11 => simd_shuffle!(
10117 a,
10118 zero,
10119 [
10120 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 27, 28, 29, 30, 31,
10121 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 43, 44, 45, 46, 47, 96, 97, 98, 99,
10122 100, 101, 102, 103, 104, 105, 106, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116,
10123 117, 118, 119, 120, 121, 122,
10124 ],
10125 ),
10126 12 => simd_shuffle!(
10127 a,
10128 zero,
10129 [
10130 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 28, 29, 30, 31, 80,
10131 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 44, 45, 46, 47, 96, 97, 98, 99, 100,
10132 101, 102, 103, 104, 105, 106, 107, 60, 61, 62, 63, 112, 113, 114, 115, 116, 117,
10133 118, 119, 120, 121, 122, 123,
10134 ],
10135 ),
10136 13 => simd_shuffle!(
10137 a,
10138 zero,
10139 [
10140 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 29, 30, 31, 80, 81,
10141 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 45, 46, 47, 96, 97, 98, 99, 100, 101,
10142 102, 103, 104, 105, 106, 107, 108, 61, 62, 63, 112, 113, 114, 115, 116, 117, 118,
10143 119, 120, 121, 122, 123, 124,
10144 ],
10145 ),
10146 14 => simd_shuffle!(
10147 a,
10148 zero,
10149 [
10150 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 30, 31, 80, 81, 82,
10151 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 46, 47, 96, 97, 98, 99, 100, 101, 102,
10152 103, 104, 105, 106, 107, 108, 109, 62, 63, 112, 113, 114, 115, 116, 117, 118, 119,
10153 120, 121, 122, 123, 124, 125,
10154 ],
10155 ),
10156 15 => simd_shuffle!(
10157 a,
10158 zero,
10159 [
10160 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 31, 80, 81, 82, 83,
10161 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 47, 96, 97, 98, 99, 100, 101, 102, 103,
10162 104, 105, 106, 107, 108, 109, 110, 63, 112, 113, 114, 115, 116, 117, 118, 119, 120,
10163 121, 122, 123, 124, 125, 126,
10164 ],
10165 ),
10166 _ => zero,
10167 };
10168 transmute(r)
10169}
10170
10171/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst.
10172///
10173/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_alignr_epi8&expand=263)
10174#[inline]
10175#[target_feature(enable = "avx512bw")]
10176#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10177#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
10178#[rustc_legacy_const_generics(2)]
10179pub unsafe fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
10180 // If palignr is shifting the pair of vectors more than the size of two
10181 // lanes, emit zero.
10182 if IMM8 > 32 {
10183 return _mm512_set1_epi8(0);
10184 }
10185 // If palignr is shifting the pair of input vectors more than one lane,
10186 // but less than two lanes, convert to shifting in zeroes.
10187 let (a, b) = if IMM8 > 16 {
10188 (_mm512_set1_epi8(0), a)
10189 } else {
10190 (a, b)
10191 };
10192 let a = a.as_i8x64();
10193 let b = b.as_i8x64();
10194
10195 let r: i8x64 = match IMM8 % 16 {
10196 0 => simd_shuffle!(
10197 b,
10198 a,
10199 [
10200 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,
10201 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
10202 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
10203 ],
10204 ),
10205 1 => simd_shuffle!(
10206 b,
10207 a,
10208 [
10209 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 17, 18, 19, 20, 21, 22, 23,
10210 24, 25, 26, 27, 28, 29, 30, 31, 80, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
10211 45, 46, 47, 96, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112,
10212 ],
10213 ),
10214 2 => simd_shuffle!(
10215 b,
10216 a,
10217 [
10218 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 18, 19, 20, 21, 22, 23, 24,
10219 25, 26, 27, 28, 29, 30, 31, 80, 81, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10220 46, 47, 96, 97, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113,
10221 ],
10222 ),
10223 3 => simd_shuffle!(
10224 b,
10225 a,
10226 [
10227 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 19, 20, 21, 22, 23, 24,
10228 25, 26, 27, 28, 29, 30, 31, 80, 81, 82, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
10229 46, 47, 96, 97, 98, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113,
10230 114,
10231 ],
10232 ),
10233 4 => simd_shuffle!(
10234 b,
10235 a,
10236 [
10237 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 20, 21, 22, 23, 24, 25,
10238 26, 27, 28, 29, 30, 31, 80, 81, 82, 83, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,
10239 47, 96, 97, 98, 99, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114,
10240 115,
10241 ],
10242 ),
10243 5 => simd_shuffle!(
10244 b,
10245 a,
10246 [
10247 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 21, 22, 23, 24, 25, 26,
10248 27, 28, 29, 30, 31, 80, 81, 82, 83, 84, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
10249 96, 97, 98, 99, 100, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114,
10250 115, 116,
10251 ],
10252 ),
10253 6 => simd_shuffle!(
10254 b,
10255 a,
10256 [
10257 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 22, 23, 24, 25, 26, 27,
10258 28, 29, 30, 31, 80, 81, 82, 83, 84, 85, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 96,
10259 97, 98, 99, 100, 101, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10260 116, 117,
10261 ],
10262 ),
10263 7 => simd_shuffle!(
10264 b,
10265 a,
10266 [
10267 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 23, 24, 25, 26, 27,
10268 28, 29, 30, 31, 80, 81, 82, 83, 84, 85, 86, 39, 40, 41, 42, 43, 44, 45, 46, 47, 96,
10269 97, 98, 99, 100, 101, 102, 55, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10270 116, 117, 118,
10271 ],
10272 ),
10273 8 => simd_shuffle!(
10274 b,
10275 a,
10276 [
10277 8, 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 24, 25, 26, 27, 28,
10278 29, 30, 31, 80, 81, 82, 83, 84, 85, 86, 87, 40, 41, 42, 43, 44, 45, 46, 47, 96, 97,
10279 98, 99, 100, 101, 102, 103, 56, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115,
10280 116, 117, 118, 119,
10281 ],
10282 ),
10283 9 => simd_shuffle!(
10284 b,
10285 a,
10286 [
10287 9, 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 25, 26, 27, 28, 29,
10288 30, 31, 80, 81, 82, 83, 84, 85, 86, 87, 88, 41, 42, 43, 44, 45, 46, 47, 96, 97, 98,
10289 99, 100, 101, 102, 103, 104, 57, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116,
10290 117, 118, 119, 120,
10291 ],
10292 ),
10293 10 => simd_shuffle!(
10294 b,
10295 a,
10296 [
10297 10, 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 26, 27, 28, 29, 30,
10298 31, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 42, 43, 44, 45, 46, 47, 96, 97, 98, 99,
10299 100, 101, 102, 103, 104, 105, 58, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116, 117,
10300 118, 119, 120, 121,
10301 ],
10302 ),
10303 11 => simd_shuffle!(
10304 b,
10305 a,
10306 [
10307 11, 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 27, 28, 29, 30, 31,
10308 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 43, 44, 45, 46, 47, 96, 97, 98, 99,
10309 100, 101, 102, 103, 104, 105, 106, 59, 60, 61, 62, 63, 112, 113, 114, 115, 116,
10310 117, 118, 119, 120, 121, 122,
10311 ],
10312 ),
10313 12 => simd_shuffle!(
10314 b,
10315 a,
10316 [
10317 12, 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 28, 29, 30, 31, 80,
10318 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 44, 45, 46, 47, 96, 97, 98, 99, 100,
10319 101, 102, 103, 104, 105, 106, 107, 60, 61, 62, 63, 112, 113, 114, 115, 116, 117,
10320 118, 119, 120, 121, 122, 123,
10321 ],
10322 ),
10323 13 => simd_shuffle!(
10324 b,
10325 a,
10326 [
10327 13, 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 29, 30, 31, 80, 81,
10328 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 45, 46, 47, 96, 97, 98, 99, 100, 101,
10329 102, 103, 104, 105, 106, 107, 108, 61, 62, 63, 112, 113, 114, 115, 116, 117, 118,
10330 119, 120, 121, 122, 123, 124,
10331 ],
10332 ),
10333 14 => simd_shuffle!(
10334 b,
10335 a,
10336 [
10337 14, 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 30, 31, 80, 81, 82,
10338 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 46, 47, 96, 97, 98, 99, 100, 101, 102,
10339 103, 104, 105, 106, 107, 108, 109, 62, 63, 112, 113, 114, 115, 116, 117, 118, 119,
10340 120, 121, 122, 123, 124, 125,
10341 ],
10342 ),
10343 15 => simd_shuffle!(
10344 b,
10345 a,
10346 [
10347 15, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 31, 80, 81, 82, 83,
10348 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 47, 96, 97, 98, 99, 100, 101, 102, 103,
10349 104, 105, 106, 107, 108, 109, 110, 63, 112, 113, 114, 115, 116, 117, 118, 119, 120,
10350 121, 122, 123, 124, 125, 126,
10351 ],
10352 ),
10353 _ => b,
10354 };
10355 transmute(r)
10356}
10357
10358/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10359///
10360/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_alignr_epi8&expand=264)
10361#[inline]
10362#[target_feature(enable = "avx512bw")]
10363#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10364#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
10365#[rustc_legacy_const_generics(4)]
10366pub unsafe fn _mm512_mask_alignr_epi8<const IMM8: i32>(
10367 src: __m512i,
10368 k: __mmask64,
10369 a: __m512i,
10370 b: __m512i,
10371) -> __m512i {
10372 static_assert_uimm_bits!(IMM8, 8);
10373 let r: __m512i = _mm512_alignr_epi8::<IMM8>(a, b);
10374 transmute(src:simd_select_bitmask(m:k, yes:r.as_i8x64(), no:src.as_i8x64()))
10375}
10376
10377/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10378///
10379/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_alignr_epi8&expand=265)
10380#[inline]
10381#[target_feature(enable = "avx512bw")]
10382#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10383#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))]
10384#[rustc_legacy_const_generics(3)]
10385pub unsafe fn _mm512_maskz_alignr_epi8<const IMM8: i32>(
10386 k: __mmask64,
10387 a: __m512i,
10388 b: __m512i,
10389) -> __m512i {
10390 static_assert_uimm_bits!(IMM8, 8);
10391 let r: __m512i = _mm512_alignr_epi8::<IMM8>(a, b);
10392 let zero: i8x64 = _mm512_setzero_si512().as_i8x64();
10393 transmute(src:simd_select_bitmask(m:k, yes:r.as_i8x64(), no:zero))
10394}
10395
10396/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10397///
10398/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_alignr_epi8&expand=261)
10399#[inline]
10400#[target_feature(enable = "avx512bw,avx512vl")]
10401#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10402#[rustc_legacy_const_generics(4)]
10403#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
10404pub unsafe fn _mm256_mask_alignr_epi8<const IMM8: i32>(
10405 src: __m256i,
10406 k: __mmask32,
10407 a: __m256i,
10408 b: __m256i,
10409) -> __m256i {
10410 static_assert_uimm_bits!(IMM8, 8);
10411 let r: __m256i = _mm256_alignr_epi8::<IMM8>(a, b);
10412 transmute(src:simd_select_bitmask(m:k, yes:r.as_i8x32(), no:src.as_i8x32()))
10413}
10414
10415/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10416///
10417/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_alignr_epi8&expand=262)
10418#[inline]
10419#[target_feature(enable = "avx512bw,avx512vl")]
10420#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10421#[rustc_legacy_const_generics(3)]
10422#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
10423pub unsafe fn _mm256_maskz_alignr_epi8<const IMM8: i32>(
10424 k: __mmask32,
10425 a: __m256i,
10426 b: __m256i,
10427) -> __m256i {
10428 static_assert_uimm_bits!(IMM8, 8);
10429 let r: __m256i = _mm256_alignr_epi8::<IMM8>(a, b);
10430 transmute(src:simd_select_bitmask(
10431 m:k,
10432 yes:r.as_i8x32(),
10433 no:_mm256_setzero_si256().as_i8x32(),
10434 ))
10435}
10436
10437/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using writemask k (elements are copied from src when the corresponding mask bit is not set).
10438///
10439/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_alignr_epi8&expand=258)
10440#[inline]
10441#[target_feature(enable = "avx512bw,avx512vl")]
10442#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10443#[rustc_legacy_const_generics(4)]
10444#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
10445pub unsafe fn _mm_mask_alignr_epi8<const IMM8: i32>(
10446 src: __m128i,
10447 k: __mmask16,
10448 a: __m128i,
10449 b: __m128i,
10450) -> __m128i {
10451 static_assert_uimm_bits!(IMM8, 8);
10452 let r: __m128i = _mm_alignr_epi8::<IMM8>(a, b);
10453 transmute(src:simd_select_bitmask(m:k, yes:r.as_i8x16(), no:src.as_i8x16()))
10454}
10455
10456/// Concatenate pairs of 16-byte blocks in a and b into a 32-byte temporary result, shift the result right by imm8 bytes, and store the low 16 bytes in dst using zeromask k (elements are zeroed out when the corresponding mask bit is not set).
10457///
10458/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_alignr_epi8&expand=259)
10459#[inline]
10460#[target_feature(enable = "avx512bw,avx512vl")]
10461#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10462#[rustc_legacy_const_generics(3)]
10463#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))]
10464pub unsafe fn _mm_maskz_alignr_epi8<const IMM8: i32>(
10465 k: __mmask16,
10466 a: __m128i,
10467 b: __m128i,
10468) -> __m128i {
10469 static_assert_uimm_bits!(IMM8, 8);
10470 let r: __m128i = _mm_alignr_epi8::<IMM8>(a, b);
10471 let zero: i8x16 = _mm_setzero_si128().as_i8x16();
10472 transmute(src:simd_select_bitmask(m:k, yes:r.as_i8x16(), no:zero))
10473}
10474
10475/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10476///
10477/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtsepi16_storeu_epi8&expand=1812)
10478#[inline]
10479#[target_feature(enable = "avx512bw")]
10480#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10481#[cfg_attr(test, assert_instr(vpmovswb))]
10482pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
10483 vpmovswbmem(mem_addr, a:a.as_i16x32(), mask:k);
10484}
10485
10486/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10487///
10488/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtsepi16_storeu_epi8&expand=1811)
10489#[inline]
10490#[target_feature(enable = "avx512bw,avx512vl")]
10491#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10492#[cfg_attr(test, assert_instr(vpmovswb))]
10493pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
10494 vpmovswbmem256(mem_addr, a:a.as_i16x16(), mask:k);
10495}
10496
10497/// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10498///
10499/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtsepi16_storeu_epi8&expand=1810)
10500#[inline]
10501#[target_feature(enable = "avx512bw,avx512vl")]
10502#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10503#[cfg_attr(test, assert_instr(vpmovswb))]
10504pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
10505 vpmovswbmem128(mem_addr, a:a.as_i16x8(), mask:k);
10506}
10507
10508/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10509///
10510/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtepi16_storeu_epi8&expand=1412)
10511#[inline]
10512#[target_feature(enable = "avx512bw")]
10513#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10514#[cfg_attr(test, assert_instr(vpmovwb))]
10515pub unsafe fn _mm512_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
10516 vpmovwbmem(mem_addr, a:a.as_i16x32(), mask:k);
10517}
10518
10519/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10520///
10521/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtepi16_storeu_epi8&expand=1411)
10522#[inline]
10523#[target_feature(enable = "avx512bw,avx512vl")]
10524#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10525#[cfg_attr(test, assert_instr(vpmovwb))]
10526pub unsafe fn _mm256_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
10527 vpmovwbmem256(mem_addr, a:a.as_i16x16(), mask:k);
10528}
10529
10530/// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10531///
10532/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtepi16_storeu_epi8&expand=1410)
10533#[inline]
10534#[target_feature(enable = "avx512bw,avx512vl")]
10535#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10536#[cfg_attr(test, assert_instr(vpmovwb))]
10537pub unsafe fn _mm_mask_cvtepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
10538 vpmovwbmem128(mem_addr, a:a.as_i16x8(), mask:k);
10539}
10540
10541/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10542///
10543/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_cvtusepi16_storeu_epi8&expand=2047)
10544#[inline]
10545#[target_feature(enable = "avx512bw")]
10546#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10547#[cfg_attr(test, assert_instr(vpmovuswb))]
10548pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, a: __m512i) {
10549 vpmovuswbmem(mem_addr, a:a.as_i16x32(), mask:k);
10550}
10551
10552/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10553///
10554/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_cvtusepi16_storeu_epi8&expand=2046)
10555#[inline]
10556#[target_feature(enable = "avx512bw,avx512vl")]
10557#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10558#[cfg_attr(test, assert_instr(vpmovuswb))]
10559pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) {
10560 vpmovuswbmem256(mem_addr, a:a.as_i16x16(), mask:k);
10561}
10562
10563/// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr.
10564///
10565/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_cvtusepi16_storeu_epi8&expand=2045)
10566#[inline]
10567#[target_feature(enable = "avx512bw,avx512vl")]
10568#[unstable(feature = "stdarch_x86_avx512", issue = "111137")]
10569#[cfg_attr(test, assert_instr(vpmovuswb))]
10570pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) {
10571 vpmovuswbmem128(mem_addr, a:a.as_i16x8(), mask:k);
10572}
10573
10574#[allow(improper_ctypes)]
10575extern "C" {
10576 #[link_name = "llvm.x86.avx512.mask.paddus.w.512"]
10577 fn vpaddusw(a: u16x32, b: u16x32, src: u16x32, mask: u32) -> u16x32;
10578 #[link_name = "llvm.x86.avx512.mask.paddus.w.256"]
10579 fn vpaddusw256(a: u16x16, b: u16x16, src: u16x16, mask: u16) -> u16x16;
10580 #[link_name = "llvm.x86.avx512.mask.paddus.w.128"]
10581 fn vpaddusw128(a: u16x8, b: u16x8, src: u16x8, mask: u8) -> u16x8;
10582
10583 #[link_name = "llvm.x86.avx512.mask.paddus.b.512"]
10584 fn vpaddusb(a: u8x64, b: u8x64, src: u8x64, mask: u64) -> u8x64;
10585 #[link_name = "llvm.x86.avx512.mask.paddus.b.256"]
10586 fn vpaddusb256(a: u8x32, b: u8x32, src: u8x32, mask: u32) -> u8x32;
10587 #[link_name = "llvm.x86.avx512.mask.paddus.b.128"]
10588 fn vpaddusb128(a: u8x16, b: u8x16, src: u8x16, mask: u16) -> u8x16;
10589
10590 #[link_name = "llvm.x86.avx512.mask.padds.w.512"]
10591 fn vpaddsw(a: i16x32, b: i16x32, src: i16x32, mask: u32) -> i16x32;
10592 #[link_name = "llvm.x86.avx512.mask.padds.w.256"]
10593 fn vpaddsw256(a: i16x16, b: i16x16, src: i16x16, mask: u16) -> i16x16;
10594 #[link_name = "llvm.x86.avx512.mask.padds.w.128"]
10595 fn vpaddsw128(a: i16x8, b: i16x8, src: i16x8, mask: u8) -> i16x8;
10596
10597 #[link_name = "llvm.x86.avx512.mask.padds.b.512"]
10598 fn vpaddsb(a: i8x64, b: i8x64, src: i8x64, mask: u64) -> i8x64;
10599 #[link_name = "llvm.x86.avx512.mask.padds.b.256"]
10600 fn vpaddsb256(a: i8x32, b: i8x32, src: i8x32, mask: u32) -> i8x32;
10601 #[link_name = "llvm.x86.avx512.mask.padds.b.128"]
10602 fn vpaddsb128(a: i8x16, b: i8x16, src: i8x16, mask: u16) -> i8x16;
10603
10604 #[link_name = "llvm.x86.avx512.mask.psubus.w.512"]
10605 fn vpsubusw(a: u16x32, b: u16x32, src: u16x32, mask: u32) -> u16x32;
10606 #[link_name = "llvm.x86.avx512.mask.psubus.w.256"]
10607 fn vpsubusw256(a: u16x16, b: u16x16, src: u16x16, mask: u16) -> u16x16;
10608 #[link_name = "llvm.x86.avx512.mask.psubus.w.128"]
10609 fn vpsubusw128(a: u16x8, b: u16x8, src: u16x8, mask: u8) -> u16x8;
10610
10611 #[link_name = "llvm.x86.avx512.mask.psubus.b.512"]
10612 fn vpsubusb(a: u8x64, b: u8x64, src: u8x64, mask: u64) -> u8x64;
10613 #[link_name = "llvm.x86.avx512.mask.psubus.b.256"]
10614 fn vpsubusb256(a: u8x32, b: u8x32, src: u8x32, mask: u32) -> u8x32;
10615 #[link_name = "llvm.x86.avx512.mask.psubus.b.128"]
10616 fn vpsubusb128(a: u8x16, b: u8x16, src: u8x16, mask: u16) -> u8x16;
10617
10618 #[link_name = "llvm.x86.avx512.mask.psubs.w.512"]
10619 fn vpsubsw(a: i16x32, b: i16x32, src: i16x32, mask: u32) -> i16x32;
10620 #[link_name = "llvm.x86.avx512.mask.psubs.w.256"]
10621 fn vpsubsw256(a: i16x16, b: i16x16, src: i16x16, mask: u16) -> i16x16;
10622 #[link_name = "llvm.x86.avx512.mask.psubs.w.128"]
10623 fn vpsubsw128(a: i16x8, b: i16x8, src: i16x8, mask: u8) -> i16x8;
10624
10625 #[link_name = "llvm.x86.avx512.mask.psubs.b.512"]
10626 fn vpsubsb(a: i8x64, b: i8x64, src: i8x64, mask: u64) -> i8x64;
10627 #[link_name = "llvm.x86.avx512.mask.psubs.b.256"]
10628 fn vpsubsb256(a: i8x32, b: i8x32, src: i8x32, mask: u32) -> i8x32;
10629 #[link_name = "llvm.x86.avx512.mask.psubs.b.128"]
10630 fn vpsubsb128(a: i8x16, b: i8x16, src: i8x16, mask: u16) -> i8x16;
10631
10632 #[link_name = "llvm.x86.avx512.pmulhu.w.512"]
10633 fn vpmulhuw(a: u16x32, b: u16x32) -> u16x32;
10634 #[link_name = "llvm.x86.avx512.pmulh.w.512"]
10635 fn vpmulhw(a: i16x32, b: i16x32) -> i16x32;
10636 #[link_name = "llvm.x86.avx512.pmul.hr.sw.512"]
10637 fn vpmulhrsw(a: i16x32, b: i16x32) -> i16x32;
10638
10639 #[link_name = "llvm.x86.avx512.mask.ucmp.w.512"]
10640 fn vpcmpuw(a: u16x32, b: u16x32, op: i32, mask: u32) -> u32;
10641 #[link_name = "llvm.x86.avx512.mask.ucmp.w.256"]
10642 fn vpcmpuw256(a: u16x16, b: u16x16, op: i32, mask: u16) -> u16;
10643 #[link_name = "llvm.x86.avx512.mask.ucmp.w.128"]
10644 fn vpcmpuw128(a: u16x8, b: u16x8, op: i32, mask: u8) -> u8;
10645
10646 #[link_name = "llvm.x86.avx512.mask.ucmp.b.512"]
10647 fn vpcmpub(a: u8x64, b: u8x64, op: i32, mask: u64) -> u64;
10648 #[link_name = "llvm.x86.avx512.mask.ucmp.b.256"]
10649 fn vpcmpub256(a: u8x32, b: u8x32, op: i32, mask: u32) -> u32;
10650 #[link_name = "llvm.x86.avx512.mask.ucmp.b.128"]
10651 fn vpcmpub128(a: u8x16, b: u8x16, op: i32, mask: u16) -> u16;
10652
10653 #[link_name = "llvm.x86.avx512.mask.cmp.w.512"]
10654 fn vpcmpw(a: i16x32, b: i16x32, op: i32, mask: u32) -> u32;
10655 #[link_name = "llvm.x86.avx512.mask.cmp.w.256"]
10656 fn vpcmpw256(a: i16x16, b: i16x16, op: i32, mask: u16) -> u16;
10657 #[link_name = "llvm.x86.avx512.mask.cmp.w.128"]
10658 fn vpcmpw128(a: i16x8, b: i16x8, op: i32, mask: u8) -> u8;
10659
10660 #[link_name = "llvm.x86.avx512.mask.cmp.b.512"]
10661 fn vpcmpb(a: i8x64, b: i8x64, op: i32, mask: u64) -> u64;
10662 #[link_name = "llvm.x86.avx512.mask.cmp.b.256"]
10663 fn vpcmpb256(a: i8x32, b: i8x32, op: i32, mask: u32) -> u32;
10664 #[link_name = "llvm.x86.avx512.mask.cmp.b.128"]
10665 fn vpcmpb128(a: i8x16, b: i8x16, op: i32, mask: u16) -> u16;
10666
10667 #[link_name = "llvm.x86.avx512.mask.pmaxu.w.512"]
10668 fn vpmaxuw(a: u16x32, b: u16x32) -> u16x32;
10669 #[link_name = "llvm.x86.avx512.mask.pmaxu.b.512"]
10670 fn vpmaxub(a: u8x64, b: u8x64) -> u8x64;
10671 #[link_name = "llvm.x86.avx512.mask.pmaxs.w.512"]
10672 fn vpmaxsw(a: i16x32, b: i16x32) -> i16x32;
10673 #[link_name = "llvm.x86.avx512.mask.pmaxs.b.512"]
10674 fn vpmaxsb(a: i8x64, b: i8x64) -> i8x64;
10675
10676 #[link_name = "llvm.x86.avx512.mask.pminu.w.512"]
10677 fn vpminuw(a: u16x32, b: u16x32) -> u16x32;
10678 #[link_name = "llvm.x86.avx512.mask.pminu.b.512"]
10679 fn vpminub(a: u8x64, b: u8x64) -> u8x64;
10680 #[link_name = "llvm.x86.avx512.mask.pmins.w.512"]
10681 fn vpminsw(a: i16x32, b: i16x32) -> i16x32;
10682 #[link_name = "llvm.x86.avx512.mask.pmins.b.512"]
10683 fn vpminsb(a: i8x64, b: i8x64) -> i8x64;
10684
10685 #[link_name = "llvm.x86.avx512.pmaddw.d.512"]
10686 fn vpmaddwd(a: i16x32, b: i16x32) -> i32x16;
10687 #[link_name = "llvm.x86.avx512.pmaddubs.w.512"]
10688 fn vpmaddubsw(a: i8x64, b: i8x64) -> i16x32;
10689
10690 #[link_name = "llvm.x86.avx512.packssdw.512"]
10691 fn vpackssdw(a: i32x16, b: i32x16) -> i16x32;
10692 #[link_name = "llvm.x86.avx512.packsswb.512"]
10693 fn vpacksswb(a: i16x32, b: i16x32) -> i8x64;
10694 #[link_name = "llvm.x86.avx512.packusdw.512"]
10695 fn vpackusdw(a: i32x16, b: i32x16) -> u16x32;
10696 #[link_name = "llvm.x86.avx512.packuswb.512"]
10697 fn vpackuswb(a: i16x32, b: i16x32) -> u8x64;
10698
10699 #[link_name = "llvm.x86.avx512.pavg.w.512"]
10700 fn vpavgw(a: u16x32, b: u16x32) -> u16x32;
10701 #[link_name = "llvm.x86.avx512.pavg.b.512"]
10702 fn vpavgb(a: u8x64, b: u8x64) -> u8x64;
10703
10704 #[link_name = "llvm.x86.avx512.psll.w.512"]
10705 fn vpsllw(a: i16x32, count: i16x8) -> i16x32;
10706
10707 #[link_name = "llvm.x86.avx512.psllv.w.512"]
10708 fn vpsllvw(a: i16x32, b: i16x32) -> i16x32;
10709 #[link_name = "llvm.x86.avx512.psllv.w.256"]
10710 fn vpsllvw256(a: i16x16, b: i16x16) -> i16x16;
10711 #[link_name = "llvm.x86.avx512.psllv.w.128"]
10712 fn vpsllvw128(a: i16x8, b: i16x8) -> i16x8;
10713
10714 #[link_name = "llvm.x86.avx512.psrl.w.512"]
10715 fn vpsrlw(a: i16x32, count: i16x8) -> i16x32;
10716
10717 #[link_name = "llvm.x86.avx512.psrlv.w.512"]
10718 fn vpsrlvw(a: i16x32, b: i16x32) -> i16x32;
10719 #[link_name = "llvm.x86.avx512.psrlv.w.256"]
10720 fn vpsrlvw256(a: i16x16, b: i16x16) -> i16x16;
10721 #[link_name = "llvm.x86.avx512.psrlv.w.128"]
10722 fn vpsrlvw128(a: i16x8, b: i16x8) -> i16x8;
10723
10724 #[link_name = "llvm.x86.avx512.psra.w.512"]
10725 fn vpsraw(a: i16x32, count: i16x8) -> i16x32;
10726
10727 #[link_name = "llvm.x86.avx512.psrav.w.512"]
10728 fn vpsravw(a: i16x32, count: i16x32) -> i16x32;
10729 #[link_name = "llvm.x86.avx512.psrav.w.256"]
10730 fn vpsravw256(a: i16x16, count: i16x16) -> i16x16;
10731 #[link_name = "llvm.x86.avx512.psrav.w.128"]
10732 fn vpsravw128(a: i16x8, count: i16x8) -> i16x8;
10733
10734 #[link_name = "llvm.x86.avx512.vpermi2var.hi.512"]
10735 fn vpermi2w(a: i16x32, idx: i16x32, b: i16x32) -> i16x32;
10736 #[link_name = "llvm.x86.avx512.vpermi2var.hi.256"]
10737 fn vpermi2w256(a: i16x16, idx: i16x16, b: i16x16) -> i16x16;
10738 #[link_name = "llvm.x86.avx512.vpermi2var.hi.128"]
10739 fn vpermi2w128(a: i16x8, idx: i16x8, b: i16x8) -> i16x8;
10740
10741 #[link_name = "llvm.x86.avx512.permvar.hi.512"]
10742 fn vpermw(a: i16x32, idx: i16x32) -> i16x32;
10743 #[link_name = "llvm.x86.avx512.permvar.hi.256"]
10744 fn vpermw256(a: i16x16, idx: i16x16) -> i16x16;
10745 #[link_name = "llvm.x86.avx512.permvar.hi.128"]
10746 fn vpermw128(a: i16x8, idx: i16x8) -> i16x8;
10747
10748 #[link_name = "llvm.x86.avx512.pshuf.b.512"]
10749 fn vpshufb(a: i8x64, b: i8x64) -> i8x64;
10750
10751 #[link_name = "llvm.x86.avx512.psad.bw.512"]
10752 fn vpsadbw(a: u8x64, b: u8x64) -> u64x8;
10753
10754 #[link_name = "llvm.x86.avx512.dbpsadbw.512"]
10755 fn vdbpsadbw(a: u8x64, b: u8x64, imm8: i32) -> u16x32;
10756 #[link_name = "llvm.x86.avx512.dbpsadbw.256"]
10757 fn vdbpsadbw256(a: u8x32, b: u8x32, imm8: i32) -> u16x16;
10758 #[link_name = "llvm.x86.avx512.dbpsadbw.128"]
10759 fn vdbpsadbw128(a: u8x16, b: u8x16, imm8: i32) -> u16x8;
10760
10761 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.512"]
10762 fn vpmovswb(a: i16x32, src: i8x32, mask: u32) -> i8x32;
10763 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.256"]
10764 fn vpmovswb256(a: i16x16, src: i8x16, mask: u16) -> i8x16;
10765 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.128"]
10766 fn vpmovswb128(a: i16x8, src: i8x16, mask: u8) -> i8x16;
10767
10768 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.512"]
10769 fn vpmovuswb(a: u16x32, src: u8x32, mask: u32) -> u8x32;
10770 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.256"]
10771 fn vpmovuswb256(a: u16x16, src: u8x16, mask: u16) -> u8x16;
10772 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.128"]
10773 fn vpmovuswb128(a: u16x8, src: u8x16, mask: u8) -> u8x16;
10774
10775 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.512"]
10776 fn vpmovswbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
10777 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.256"]
10778 fn vpmovswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
10779 #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"]
10780 fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
10781
10782 #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.512"]
10783 fn vpmovwbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
10784 #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.256"]
10785 fn vpmovwbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
10786 #[link_name = "llvm.x86.avx512.mask.pmov.wb.mem.128"]
10787 fn vpmovwbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
10788
10789 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"]
10790 fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32);
10791 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"]
10792 fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16);
10793 #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"]
10794 fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8);
10795}
10796
10797#[cfg(test)]
10798mod tests {
10799
10800 use stdarch_test::simd_test;
10801
10802 use crate::core_arch::x86::*;
10803 use crate::hint::black_box;
10804 use crate::mem::{self};
10805
10806 #[simd_test(enable = "avx512bw")]
10807 unsafe fn test_mm512_abs_epi16() {
10808 let a = _mm512_set1_epi16(-1);
10809 let r = _mm512_abs_epi16(a);
10810 let e = _mm512_set1_epi16(1);
10811 assert_eq_m512i(r, e);
10812 }
10813
10814 #[simd_test(enable = "avx512bw")]
10815 unsafe fn test_mm512_mask_abs_epi16() {
10816 let a = _mm512_set1_epi16(-1);
10817 let r = _mm512_mask_abs_epi16(a, 0, a);
10818 assert_eq_m512i(r, a);
10819 let r = _mm512_mask_abs_epi16(a, 0b00000000_11111111_00000000_11111111, a);
10820 #[rustfmt::skip]
10821 let e = _mm512_set_epi16(-1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1,
10822 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1);
10823 assert_eq_m512i(r, e);
10824 }
10825
10826 #[simd_test(enable = "avx512bw")]
10827 unsafe fn test_mm512_maskz_abs_epi16() {
10828 let a = _mm512_set1_epi16(-1);
10829 let r = _mm512_maskz_abs_epi16(0, a);
10830 assert_eq_m512i(r, _mm512_setzero_si512());
10831 let r = _mm512_maskz_abs_epi16(0b00000000_11111111_00000000_11111111, a);
10832 #[rustfmt::skip]
10833 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
10834 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
10835 assert_eq_m512i(r, e);
10836 }
10837
10838 #[simd_test(enable = "avx512bw,avx512vl")]
10839 unsafe fn test_mm256_mask_abs_epi16() {
10840 let a = _mm256_set1_epi16(-1);
10841 let r = _mm256_mask_abs_epi16(a, 0, a);
10842 assert_eq_m256i(r, a);
10843 let r = _mm256_mask_abs_epi16(a, 0b00000000_11111111, a);
10844 let e = _mm256_set_epi16(-1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1);
10845 assert_eq_m256i(r, e);
10846 }
10847
10848 #[simd_test(enable = "avx512bw,avx512vl")]
10849 unsafe fn test_mm256_maskz_abs_epi16() {
10850 let a = _mm256_set1_epi16(-1);
10851 let r = _mm256_maskz_abs_epi16(0, a);
10852 assert_eq_m256i(r, _mm256_setzero_si256());
10853 let r = _mm256_maskz_abs_epi16(0b00000000_11111111, a);
10854 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
10855 assert_eq_m256i(r, e);
10856 }
10857
10858 #[simd_test(enable = "avx512bw,avx512vl")]
10859 unsafe fn test_mm_mask_abs_epi16() {
10860 let a = _mm_set1_epi16(-1);
10861 let r = _mm_mask_abs_epi16(a, 0, a);
10862 assert_eq_m128i(r, a);
10863 let r = _mm_mask_abs_epi16(a, 0b00001111, a);
10864 let e = _mm_set_epi16(-1, -1, -1, -1, 1, 1, 1, 1);
10865 assert_eq_m128i(r, e);
10866 }
10867
10868 #[simd_test(enable = "avx512bw,avx512vl")]
10869 unsafe fn test_mm_maskz_abs_epi16() {
10870 let a = _mm_set1_epi16(-1);
10871 let r = _mm_maskz_abs_epi16(0, a);
10872 assert_eq_m128i(r, _mm_setzero_si128());
10873 let r = _mm_maskz_abs_epi16(0b00001111, a);
10874 let e = _mm_set_epi16(0, 0, 0, 0, 1, 1, 1, 1);
10875 assert_eq_m128i(r, e);
10876 }
10877
10878 #[simd_test(enable = "avx512bw")]
10879 unsafe fn test_mm512_abs_epi8() {
10880 let a = _mm512_set1_epi8(-1);
10881 let r = _mm512_abs_epi8(a);
10882 let e = _mm512_set1_epi8(1);
10883 assert_eq_m512i(r, e);
10884 }
10885
10886 #[simd_test(enable = "avx512bw")]
10887 unsafe fn test_mm512_mask_abs_epi8() {
10888 let a = _mm512_set1_epi8(-1);
10889 let r = _mm512_mask_abs_epi8(a, 0, a);
10890 assert_eq_m512i(r, a);
10891 let r = _mm512_mask_abs_epi8(
10892 a,
10893 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
10894 a,
10895 );
10896 #[rustfmt::skip]
10897 let e = _mm512_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1,
10898 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1,
10899 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1,
10900 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1);
10901 assert_eq_m512i(r, e);
10902 }
10903
10904 #[simd_test(enable = "avx512bw")]
10905 unsafe fn test_mm512_maskz_abs_epi8() {
10906 let a = _mm512_set1_epi8(-1);
10907 let r = _mm512_maskz_abs_epi8(0, a);
10908 assert_eq_m512i(r, _mm512_setzero_si512());
10909 let r = _mm512_maskz_abs_epi8(
10910 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
10911 a,
10912 );
10913 #[rustfmt::skip]
10914 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
10915 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
10916 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
10917 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
10918 assert_eq_m512i(r, e);
10919 }
10920
10921 #[simd_test(enable = "avx512bw,avx512vl")]
10922 unsafe fn test_mm256_mask_abs_epi8() {
10923 let a = _mm256_set1_epi8(-1);
10924 let r = _mm256_mask_abs_epi8(a, 0, a);
10925 assert_eq_m256i(r, a);
10926 let r = _mm256_mask_abs_epi8(a, 0b00000000_11111111_00000000_11111111, a);
10927 #[rustfmt::skip]
10928 let e = _mm256_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1,
10929 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1);
10930 assert_eq_m256i(r, e);
10931 }
10932
10933 #[simd_test(enable = "avx512bw,avx512vl")]
10934 unsafe fn test_mm256_maskz_abs_epi8() {
10935 let a = _mm256_set1_epi8(-1);
10936 let r = _mm256_maskz_abs_epi8(0, a);
10937 assert_eq_m256i(r, _mm256_setzero_si256());
10938 let r = _mm256_maskz_abs_epi8(0b00000000_11111111_00000000_11111111, a);
10939 #[rustfmt::skip]
10940 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
10941 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
10942 assert_eq_m256i(r, e);
10943 }
10944
10945 #[simd_test(enable = "avx512bw,avx512vl")]
10946 unsafe fn test_mm_mask_abs_epi8() {
10947 let a = _mm_set1_epi8(-1);
10948 let r = _mm_mask_abs_epi8(a, 0, a);
10949 assert_eq_m128i(r, a);
10950 let r = _mm_mask_abs_epi8(a, 0b00000000_11111111, a);
10951 let e = _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1);
10952 assert_eq_m128i(r, e);
10953 }
10954
10955 #[simd_test(enable = "avx512bw,avx512vl")]
10956 unsafe fn test_mm_maskz_abs_epi8() {
10957 let a = _mm_set1_epi8(-1);
10958 let r = _mm_maskz_abs_epi8(0, a);
10959 assert_eq_m128i(r, _mm_setzero_si128());
10960 let r = _mm_maskz_abs_epi8(0b00000000_11111111, a);
10961 #[rustfmt::skip]
10962 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
10963 assert_eq_m128i(r, e);
10964 }
10965
10966 #[simd_test(enable = "avx512bw")]
10967 unsafe fn test_mm512_add_epi16() {
10968 let a = _mm512_set1_epi16(1);
10969 let b = _mm512_set1_epi16(2);
10970 let r = _mm512_add_epi16(a, b);
10971 let e = _mm512_set1_epi16(3);
10972 assert_eq_m512i(r, e);
10973 }
10974
10975 #[simd_test(enable = "avx512bw")]
10976 unsafe fn test_mm512_mask_add_epi16() {
10977 let a = _mm512_set1_epi16(1);
10978 let b = _mm512_set1_epi16(2);
10979 let r = _mm512_mask_add_epi16(a, 0, a, b);
10980 assert_eq_m512i(r, a);
10981 let r = _mm512_mask_add_epi16(a, 0b00000000_11111111_00000000_11111111, a, b);
10982 #[rustfmt::skip]
10983 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3,
10984 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3);
10985 assert_eq_m512i(r, e);
10986 }
10987
10988 #[simd_test(enable = "avx512bw")]
10989 unsafe fn test_mm512_maskz_add_epi16() {
10990 let a = _mm512_set1_epi16(1);
10991 let b = _mm512_set1_epi16(2);
10992 let r = _mm512_maskz_add_epi16(0, a, b);
10993 assert_eq_m512i(r, _mm512_setzero_si512());
10994 let r = _mm512_maskz_add_epi16(0b00000000_11111111_00000000_11111111, a, b);
10995 #[rustfmt::skip]
10996 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3,
10997 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3);
10998 assert_eq_m512i(r, e);
10999 }
11000
11001 #[simd_test(enable = "avx512bw,avx512vl")]
11002 unsafe fn test_mm256_mask_add_epi16() {
11003 let a = _mm256_set1_epi16(1);
11004 let b = _mm256_set1_epi16(2);
11005 let r = _mm256_mask_add_epi16(a, 0, a, b);
11006 assert_eq_m256i(r, a);
11007 let r = _mm256_mask_add_epi16(a, 0b00000000_11111111, a, b);
11008 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3);
11009 assert_eq_m256i(r, e);
11010 }
11011
11012 #[simd_test(enable = "avx512bw,avx512vl")]
11013 unsafe fn test_mm256_maskz_add_epi16() {
11014 let a = _mm256_set1_epi16(1);
11015 let b = _mm256_set1_epi16(2);
11016 let r = _mm256_maskz_add_epi16(0, a, b);
11017 assert_eq_m256i(r, _mm256_setzero_si256());
11018 let r = _mm256_maskz_add_epi16(0b00000000_11111111, a, b);
11019 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3);
11020 assert_eq_m256i(r, e);
11021 }
11022
11023 #[simd_test(enable = "avx512bw,avx512vl")]
11024 unsafe fn test_mm_mask_add_epi16() {
11025 let a = _mm_set1_epi16(1);
11026 let b = _mm_set1_epi16(2);
11027 let r = _mm_mask_add_epi16(a, 0, a, b);
11028 assert_eq_m128i(r, a);
11029 let r = _mm_mask_add_epi16(a, 0b00001111, a, b);
11030 let e = _mm_set_epi16(1, 1, 1, 1, 3, 3, 3, 3);
11031 assert_eq_m128i(r, e);
11032 }
11033
11034 #[simd_test(enable = "avx512bw,avx512vl")]
11035 unsafe fn test_mm_maskz_add_epi16() {
11036 let a = _mm_set1_epi16(1);
11037 let b = _mm_set1_epi16(2);
11038 let r = _mm_maskz_add_epi16(0, a, b);
11039 assert_eq_m128i(r, _mm_setzero_si128());
11040 let r = _mm_maskz_add_epi16(0b00001111, a, b);
11041 let e = _mm_set_epi16(0, 0, 0, 0, 3, 3, 3, 3);
11042 assert_eq_m128i(r, e);
11043 }
11044
11045 #[simd_test(enable = "avx512bw")]
11046 unsafe fn test_mm512_add_epi8() {
11047 let a = _mm512_set1_epi8(1);
11048 let b = _mm512_set1_epi8(2);
11049 let r = _mm512_add_epi8(a, b);
11050 let e = _mm512_set1_epi8(3);
11051 assert_eq_m512i(r, e);
11052 }
11053
11054 #[simd_test(enable = "avx512bw")]
11055 unsafe fn test_mm512_mask_add_epi8() {
11056 let a = _mm512_set1_epi8(1);
11057 let b = _mm512_set1_epi8(2);
11058 let r = _mm512_mask_add_epi8(a, 0, a, b);
11059 assert_eq_m512i(r, a);
11060 let r = _mm512_mask_add_epi8(
11061 a,
11062 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
11063 a,
11064 b,
11065 );
11066 #[rustfmt::skip]
11067 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3,
11068 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3,
11069 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3,
11070 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3);
11071 assert_eq_m512i(r, e);
11072 }
11073
11074 #[simd_test(enable = "avx512bw")]
11075 unsafe fn test_mm512_maskz_add_epi8() {
11076 let a = _mm512_set1_epi8(1);
11077 let b = _mm512_set1_epi8(2);
11078 let r = _mm512_maskz_add_epi8(0, a, b);
11079 assert_eq_m512i(r, _mm512_setzero_si512());
11080 let r = _mm512_maskz_add_epi8(
11081 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
11082 a,
11083 b,
11084 );
11085 #[rustfmt::skip]
11086 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3,
11087 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3,
11088 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3,
11089 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3);
11090 assert_eq_m512i(r, e);
11091 }
11092
11093 #[simd_test(enable = "avx512bw,avx512vl")]
11094 unsafe fn test_mm256_mask_add_epi8() {
11095 let a = _mm256_set1_epi8(1);
11096 let b = _mm256_set1_epi8(2);
11097 let r = _mm256_mask_add_epi8(a, 0, a, b);
11098 assert_eq_m256i(r, a);
11099 let r = _mm256_mask_add_epi8(a, 0b00000000_11111111_00000000_11111111, a, b);
11100 #[rustfmt::skip]
11101 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3,
11102 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3);
11103 assert_eq_m256i(r, e);
11104 }
11105
11106 #[simd_test(enable = "avx512bw,avx512vl")]
11107 unsafe fn test_mm256_maskz_add_epi8() {
11108 let a = _mm256_set1_epi8(1);
11109 let b = _mm256_set1_epi8(2);
11110 let r = _mm256_maskz_add_epi8(0, a, b);
11111 assert_eq_m256i(r, _mm256_setzero_si256());
11112 let r = _mm256_maskz_add_epi8(0b00000000_11111111_00000000_11111111, a, b);
11113 #[rustfmt::skip]
11114 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3,
11115 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3);
11116 assert_eq_m256i(r, e);
11117 }
11118
11119 #[simd_test(enable = "avx512bw,avx512vl")]
11120 unsafe fn test_mm_mask_add_epi8() {
11121 let a = _mm_set1_epi8(1);
11122 let b = _mm_set1_epi8(2);
11123 let r = _mm_mask_add_epi8(a, 0, a, b);
11124 assert_eq_m128i(r, a);
11125 let r = _mm_mask_add_epi8(a, 0b00000000_11111111, a, b);
11126 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3);
11127 assert_eq_m128i(r, e);
11128 }
11129
11130 #[simd_test(enable = "avx512bw,avx512vl")]
11131 unsafe fn test_mm_maskz_add_epi8() {
11132 let a = _mm_set1_epi8(1);
11133 let b = _mm_set1_epi8(2);
11134 let r = _mm_maskz_add_epi8(0, a, b);
11135 assert_eq_m128i(r, _mm_setzero_si128());
11136 let r = _mm_maskz_add_epi8(0b00000000_11111111, a, b);
11137 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3);
11138 assert_eq_m128i(r, e);
11139 }
11140
11141 #[simd_test(enable = "avx512bw")]
11142 unsafe fn test_mm512_adds_epu16() {
11143 let a = _mm512_set1_epi16(1);
11144 let b = _mm512_set1_epi16(u16::MAX as i16);
11145 let r = _mm512_adds_epu16(a, b);
11146 let e = _mm512_set1_epi16(u16::MAX as i16);
11147 assert_eq_m512i(r, e);
11148 }
11149
11150 #[simd_test(enable = "avx512bw")]
11151 unsafe fn test_mm512_mask_adds_epu16() {
11152 let a = _mm512_set1_epi16(1);
11153 let b = _mm512_set1_epi16(u16::MAX as i16);
11154 let r = _mm512_mask_adds_epu16(a, 0, a, b);
11155 assert_eq_m512i(r, a);
11156 let r = _mm512_mask_adds_epu16(a, 0b00000000_00000000_00000000_00001111, a, b);
11157 #[rustfmt::skip]
11158 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11159 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11160 assert_eq_m512i(r, e);
11161 }
11162
11163 #[simd_test(enable = "avx512bw")]
11164 unsafe fn test_mm512_maskz_adds_epu16() {
11165 let a = _mm512_set1_epi16(1);
11166 let b = _mm512_set1_epi16(u16::MAX as i16);
11167 let r = _mm512_maskz_adds_epu16(0, a, b);
11168 assert_eq_m512i(r, _mm512_setzero_si512());
11169 let r = _mm512_maskz_adds_epu16(0b00000000_00000000_00000000_00001111, a, b);
11170 #[rustfmt::skip]
11171 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11172 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11173 assert_eq_m512i(r, e);
11174 }
11175
11176 #[simd_test(enable = "avx512bw,avx512vl")]
11177 unsafe fn test_mm256_mask_adds_epu16() {
11178 let a = _mm256_set1_epi16(1);
11179 let b = _mm256_set1_epi16(u16::MAX as i16);
11180 let r = _mm256_mask_adds_epu16(a, 0, a, b);
11181 assert_eq_m256i(r, a);
11182 let r = _mm256_mask_adds_epu16(a, 0b00000000_00001111, a, b);
11183 #[rustfmt::skip]
11184 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11185 assert_eq_m256i(r, e);
11186 }
11187
11188 #[simd_test(enable = "avx512bw,avx512vl")]
11189 unsafe fn test_mm256_maskz_adds_epu16() {
11190 let a = _mm256_set1_epi16(1);
11191 let b = _mm256_set1_epi16(u16::MAX as i16);
11192 let r = _mm256_maskz_adds_epu16(0, a, b);
11193 assert_eq_m256i(r, _mm256_setzero_si256());
11194 let r = _mm256_maskz_adds_epu16(0b00000000_00001111, a, b);
11195 #[rustfmt::skip]
11196 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11197 assert_eq_m256i(r, e);
11198 }
11199
11200 #[simd_test(enable = "avx512bw,avx512vl")]
11201 unsafe fn test_mm_mask_adds_epu16() {
11202 let a = _mm_set1_epi16(1);
11203 let b = _mm_set1_epi16(u16::MAX as i16);
11204 let r = _mm_mask_adds_epu16(a, 0, a, b);
11205 assert_eq_m128i(r, a);
11206 let r = _mm_mask_adds_epu16(a, 0b00001111, a, b);
11207 #[rustfmt::skip]
11208 let e = _mm_set_epi16(1, 1, 1, 1, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11209 assert_eq_m128i(r, e);
11210 }
11211
11212 #[simd_test(enable = "avx512bw,avx512vl")]
11213 unsafe fn test_mm_maskz_adds_epu16() {
11214 let a = _mm_set1_epi16(1);
11215 let b = _mm_set1_epi16(u16::MAX as i16);
11216 let r = _mm_maskz_adds_epu16(0, a, b);
11217 assert_eq_m128i(r, _mm_setzero_si128());
11218 let r = _mm_maskz_adds_epu16(0b00001111, a, b);
11219 #[rustfmt::skip]
11220 let e = _mm_set_epi16(0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16, u16::MAX as i16);
11221 assert_eq_m128i(r, e);
11222 }
11223
11224 #[simd_test(enable = "avx512bw")]
11225 unsafe fn test_mm512_adds_epu8() {
11226 let a = _mm512_set1_epi8(1);
11227 let b = _mm512_set1_epi8(u8::MAX as i8);
11228 let r = _mm512_adds_epu8(a, b);
11229 let e = _mm512_set1_epi8(u8::MAX as i8);
11230 assert_eq_m512i(r, e);
11231 }
11232
11233 #[simd_test(enable = "avx512bw")]
11234 unsafe fn test_mm512_mask_adds_epu8() {
11235 let a = _mm512_set1_epi8(1);
11236 let b = _mm512_set1_epi8(u8::MAX as i8);
11237 let r = _mm512_mask_adds_epu8(a, 0, a, b);
11238 assert_eq_m512i(r, a);
11239 let r = _mm512_mask_adds_epu8(
11240 a,
11241 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11242 a,
11243 b,
11244 );
11245 #[rustfmt::skip]
11246 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11247 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11248 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11249 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11250 assert_eq_m512i(r, e);
11251 }
11252
11253 #[simd_test(enable = "avx512bw")]
11254 unsafe fn test_mm512_maskz_adds_epu8() {
11255 let a = _mm512_set1_epi8(1);
11256 let b = _mm512_set1_epi8(u8::MAX as i8);
11257 let r = _mm512_maskz_adds_epu8(0, a, b);
11258 assert_eq_m512i(r, _mm512_setzero_si512());
11259 let r = _mm512_maskz_adds_epu8(
11260 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11261 a,
11262 b,
11263 );
11264 #[rustfmt::skip]
11265 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11267 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11268 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11269 assert_eq_m512i(r, e);
11270 }
11271
11272 #[simd_test(enable = "avx512bw,avx512vl")]
11273 unsafe fn test_mm256_mask_adds_epu8() {
11274 let a = _mm256_set1_epi8(1);
11275 let b = _mm256_set1_epi8(u8::MAX as i8);
11276 let r = _mm256_mask_adds_epu8(a, 0, a, b);
11277 assert_eq_m256i(r, a);
11278 let r = _mm256_mask_adds_epu8(a, 0b00000000_00000000_00000000_00001111, a, b);
11279 #[rustfmt::skip]
11280 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11281 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11282 assert_eq_m256i(r, e);
11283 }
11284
11285 #[simd_test(enable = "avx512bw,avx512vl")]
11286 unsafe fn test_mm256_maskz_adds_epu8() {
11287 let a = _mm256_set1_epi8(1);
11288 let b = _mm256_set1_epi8(u8::MAX as i8);
11289 let r = _mm256_maskz_adds_epu8(0, a, b);
11290 assert_eq_m256i(r, _mm256_setzero_si256());
11291 let r = _mm256_maskz_adds_epu8(0b00000000_00000000_00000000_00001111, a, b);
11292 #[rustfmt::skip]
11293 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11295 assert_eq_m256i(r, e);
11296 }
11297
11298 #[simd_test(enable = "avx512bw,avx512vl")]
11299 unsafe fn test_mm_mask_adds_epu8() {
11300 let a = _mm_set1_epi8(1);
11301 let b = _mm_set1_epi8(u8::MAX as i8);
11302 let r = _mm_mask_adds_epu8(a, 0, a, b);
11303 assert_eq_m128i(r, a);
11304 let r = _mm_mask_adds_epu8(a, 0b00000000_00001111, a, b);
11305 #[rustfmt::skip]
11306 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11307 assert_eq_m128i(r, e);
11308 }
11309
11310 #[simd_test(enable = "avx512bw,avx512vl")]
11311 unsafe fn test_mm_maskz_adds_epu8() {
11312 let a = _mm_set1_epi8(1);
11313 let b = _mm_set1_epi8(u8::MAX as i8);
11314 let r = _mm_maskz_adds_epu8(0, a, b);
11315 assert_eq_m128i(r, _mm_setzero_si128());
11316 let r = _mm_maskz_adds_epu8(0b00000000_00001111, a, b);
11317 #[rustfmt::skip]
11318 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8);
11319 assert_eq_m128i(r, e);
11320 }
11321
11322 #[simd_test(enable = "avx512bw")]
11323 unsafe fn test_mm512_adds_epi16() {
11324 let a = _mm512_set1_epi16(1);
11325 let b = _mm512_set1_epi16(i16::MAX);
11326 let r = _mm512_adds_epi16(a, b);
11327 let e = _mm512_set1_epi16(i16::MAX);
11328 assert_eq_m512i(r, e);
11329 }
11330
11331 #[simd_test(enable = "avx512bw")]
11332 unsafe fn test_mm512_mask_adds_epi16() {
11333 let a = _mm512_set1_epi16(1);
11334 let b = _mm512_set1_epi16(i16::MAX);
11335 let r = _mm512_mask_adds_epi16(a, 0, a, b);
11336 assert_eq_m512i(r, a);
11337 let r = _mm512_mask_adds_epi16(a, 0b00000000_00000000_00000000_00001111, a, b);
11338 #[rustfmt::skip]
11339 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11340 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11341 assert_eq_m512i(r, e);
11342 }
11343
11344 #[simd_test(enable = "avx512bw")]
11345 unsafe fn test_mm512_maskz_adds_epi16() {
11346 let a = _mm512_set1_epi16(1);
11347 let b = _mm512_set1_epi16(i16::MAX);
11348 let r = _mm512_maskz_adds_epi16(0, a, b);
11349 assert_eq_m512i(r, _mm512_setzero_si512());
11350 let r = _mm512_maskz_adds_epi16(0b00000000_00000000_00000000_00001111, a, b);
11351 #[rustfmt::skip]
11352 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11354 assert_eq_m512i(r, e);
11355 }
11356
11357 #[simd_test(enable = "avx512bw,avx512vl")]
11358 unsafe fn test_mm256_mask_adds_epi16() {
11359 let a = _mm256_set1_epi16(1);
11360 let b = _mm256_set1_epi16(i16::MAX);
11361 let r = _mm256_mask_adds_epi16(a, 0, a, b);
11362 assert_eq_m256i(r, a);
11363 let r = _mm256_mask_adds_epi16(a, 0b00000000_00001111, a, b);
11364 #[rustfmt::skip]
11365 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11366 assert_eq_m256i(r, e);
11367 }
11368
11369 #[simd_test(enable = "avx512bw,avx512vl")]
11370 unsafe fn test_mm256_maskz_adds_epi16() {
11371 let a = _mm256_set1_epi16(1);
11372 let b = _mm256_set1_epi16(i16::MAX);
11373 let r = _mm256_maskz_adds_epi16(0, a, b);
11374 assert_eq_m256i(r, _mm256_setzero_si256());
11375 let r = _mm256_maskz_adds_epi16(0b00000000_00001111, a, b);
11376 #[rustfmt::skip]
11377 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11378 assert_eq_m256i(r, e);
11379 }
11380
11381 #[simd_test(enable = "avx512bw,avx512vl")]
11382 unsafe fn test_mm_mask_adds_epi16() {
11383 let a = _mm_set1_epi16(1);
11384 let b = _mm_set1_epi16(i16::MAX);
11385 let r = _mm_mask_adds_epi16(a, 0, a, b);
11386 assert_eq_m128i(r, a);
11387 let r = _mm_mask_adds_epi16(a, 0b00001111, a, b);
11388 let e = _mm_set_epi16(1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11389 assert_eq_m128i(r, e);
11390 }
11391
11392 #[simd_test(enable = "avx512bw,avx512vl")]
11393 unsafe fn test_mm_maskz_adds_epi16() {
11394 let a = _mm_set1_epi16(1);
11395 let b = _mm_set1_epi16(i16::MAX);
11396 let r = _mm_maskz_adds_epi16(0, a, b);
11397 assert_eq_m128i(r, _mm_setzero_si128());
11398 let r = _mm_maskz_adds_epi16(0b00001111, a, b);
11399 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
11400 assert_eq_m128i(r, e);
11401 }
11402
11403 #[simd_test(enable = "avx512bw")]
11404 unsafe fn test_mm512_adds_epi8() {
11405 let a = _mm512_set1_epi8(1);
11406 let b = _mm512_set1_epi8(i8::MAX);
11407 let r = _mm512_adds_epi8(a, b);
11408 let e = _mm512_set1_epi8(i8::MAX);
11409 assert_eq_m512i(r, e);
11410 }
11411
11412 #[simd_test(enable = "avx512bw")]
11413 unsafe fn test_mm512_mask_adds_epi8() {
11414 let a = _mm512_set1_epi8(1);
11415 let b = _mm512_set1_epi8(i8::MAX);
11416 let r = _mm512_mask_adds_epi8(a, 0, a, b);
11417 assert_eq_m512i(r, a);
11418 let r = _mm512_mask_adds_epi8(
11419 a,
11420 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11421 a,
11422 b,
11423 );
11424 #[rustfmt::skip]
11425 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11426 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11427 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11429 assert_eq_m512i(r, e);
11430 }
11431
11432 #[simd_test(enable = "avx512bw")]
11433 unsafe fn test_mm512_maskz_adds_epi8() {
11434 let a = _mm512_set1_epi8(1);
11435 let b = _mm512_set1_epi8(i8::MAX);
11436 let r = _mm512_maskz_adds_epi8(0, a, b);
11437 assert_eq_m512i(r, _mm512_setzero_si512());
11438 let r = _mm512_maskz_adds_epi8(
11439 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11440 a,
11441 b,
11442 );
11443 #[rustfmt::skip]
11444 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11448 assert_eq_m512i(r, e);
11449 }
11450
11451 #[simd_test(enable = "avx512bw,avx512vl")]
11452 unsafe fn test_mm256_mask_adds_epi8() {
11453 let a = _mm256_set1_epi8(1);
11454 let b = _mm256_set1_epi8(i8::MAX);
11455 let r = _mm256_mask_adds_epi8(a, 0, a, b);
11456 assert_eq_m256i(r, a);
11457 let r = _mm256_mask_adds_epi8(a, 0b00000000_00000000_00000000_00001111, a, b);
11458 #[rustfmt::skip]
11459 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11461 assert_eq_m256i(r, e);
11462 }
11463
11464 #[simd_test(enable = "avx512bw,avx512vl")]
11465 unsafe fn test_mm256_maskz_adds_epi8() {
11466 let a = _mm256_set1_epi8(1);
11467 let b = _mm256_set1_epi8(i8::MAX);
11468 let r = _mm256_maskz_adds_epi8(0, a, b);
11469 assert_eq_m256i(r, _mm256_setzero_si256());
11470 let r = _mm256_maskz_adds_epi8(0b00000000_00000000_00000000_00001111, a, b);
11471 #[rustfmt::skip]
11472 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11474 assert_eq_m256i(r, e);
11475 }
11476
11477 #[simd_test(enable = "avx512bw,avx512vl")]
11478 unsafe fn test_mm_mask_adds_epi8() {
11479 let a = _mm_set1_epi8(1);
11480 let b = _mm_set1_epi8(i8::MAX);
11481 let r = _mm_mask_adds_epi8(a, 0, a, b);
11482 assert_eq_m128i(r, a);
11483 let r = _mm_mask_adds_epi8(a, 0b00000000_00001111, a, b);
11484 #[rustfmt::skip]
11485 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11486 assert_eq_m128i(r, e);
11487 }
11488
11489 #[simd_test(enable = "avx512bw,avx512vl")]
11490 unsafe fn test_mm_maskz_adds_epi8() {
11491 let a = _mm_set1_epi8(1);
11492 let b = _mm_set1_epi8(i8::MAX);
11493 let r = _mm_maskz_adds_epi8(0, a, b);
11494 assert_eq_m128i(r, _mm_setzero_si128());
11495 let r = _mm_maskz_adds_epi8(0b00000000_00001111, a, b);
11496 #[rustfmt::skip]
11497 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
11498 assert_eq_m128i(r, e);
11499 }
11500
11501 #[simd_test(enable = "avx512bw")]
11502 unsafe fn test_mm512_sub_epi16() {
11503 let a = _mm512_set1_epi16(1);
11504 let b = _mm512_set1_epi16(2);
11505 let r = _mm512_sub_epi16(a, b);
11506 let e = _mm512_set1_epi16(-1);
11507 assert_eq_m512i(r, e);
11508 }
11509
11510 #[simd_test(enable = "avx512bw")]
11511 unsafe fn test_mm512_mask_sub_epi16() {
11512 let a = _mm512_set1_epi16(1);
11513 let b = _mm512_set1_epi16(2);
11514 let r = _mm512_mask_sub_epi16(a, 0, a, b);
11515 assert_eq_m512i(r, a);
11516 let r = _mm512_mask_sub_epi16(a, 0b00000000_11111111_00000000_11111111, a, b);
11517 #[rustfmt::skip]
11518 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
11519 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1);
11520 assert_eq_m512i(r, e);
11521 }
11522
11523 #[simd_test(enable = "avx512bw")]
11524 unsafe fn test_mm512_maskz_sub_epi16() {
11525 let a = _mm512_set1_epi16(1);
11526 let b = _mm512_set1_epi16(2);
11527 let r = _mm512_maskz_sub_epi16(0, a, b);
11528 assert_eq_m512i(r, _mm512_setzero_si512());
11529 let r = _mm512_maskz_sub_epi16(0b00000000_11111111_00000000_11111111, a, b);
11530 #[rustfmt::skip]
11531 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1,
11532 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
11533 assert_eq_m512i(r, e);
11534 }
11535
11536 #[simd_test(enable = "avx512bw,avx512vl")]
11537 unsafe fn test_mm256_mask_sub_epi16() {
11538 let a = _mm256_set1_epi16(1);
11539 let b = _mm256_set1_epi16(2);
11540 let r = _mm256_mask_sub_epi16(a, 0, a, b);
11541 assert_eq_m256i(r, a);
11542 let r = _mm256_mask_sub_epi16(a, 0b00000000_11111111, a, b);
11543 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1);
11544 assert_eq_m256i(r, e);
11545 }
11546
11547 #[simd_test(enable = "avx512bw,avx512vl")]
11548 unsafe fn test_mm256_maskz_sub_epi16() {
11549 let a = _mm256_set1_epi16(1);
11550 let b = _mm256_set1_epi16(2);
11551 let r = _mm256_maskz_sub_epi16(0, a, b);
11552 assert_eq_m256i(r, _mm256_setzero_si256());
11553 let r = _mm256_maskz_sub_epi16(0b00000000_11111111, a, b);
11554 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
11555 assert_eq_m256i(r, e);
11556 }
11557
11558 #[simd_test(enable = "avx512bw,avx512vl")]
11559 unsafe fn test_mm_mask_sub_epi16() {
11560 let a = _mm_set1_epi16(1);
11561 let b = _mm_set1_epi16(2);
11562 let r = _mm_mask_sub_epi16(a, 0, a, b);
11563 assert_eq_m128i(r, a);
11564 let r = _mm_mask_sub_epi16(a, 0b00001111, a, b);
11565 let e = _mm_set_epi16(1, 1, 1, 1, -1, -1, -1, -1);
11566 assert_eq_m128i(r, e);
11567 }
11568
11569 #[simd_test(enable = "avx512bw,avx512vl")]
11570 unsafe fn test_mm_maskz_sub_epi16() {
11571 let a = _mm_set1_epi16(1);
11572 let b = _mm_set1_epi16(2);
11573 let r = _mm_maskz_sub_epi16(0, a, b);
11574 assert_eq_m128i(r, _mm_setzero_si128());
11575 let r = _mm_maskz_sub_epi16(0b00001111, a, b);
11576 let e = _mm_set_epi16(0, 0, 0, 0, -1, -1, -1, -1);
11577 assert_eq_m128i(r, e);
11578 }
11579
11580 #[simd_test(enable = "avx512bw")]
11581 unsafe fn test_mm512_sub_epi8() {
11582 let a = _mm512_set1_epi8(1);
11583 let b = _mm512_set1_epi8(2);
11584 let r = _mm512_sub_epi8(a, b);
11585 let e = _mm512_set1_epi8(-1);
11586 assert_eq_m512i(r, e);
11587 }
11588
11589 #[simd_test(enable = "avx512bw")]
11590 unsafe fn test_mm512_mask_sub_epi8() {
11591 let a = _mm512_set1_epi8(1);
11592 let b = _mm512_set1_epi8(2);
11593 let r = _mm512_mask_sub_epi8(a, 0, a, b);
11594 assert_eq_m512i(r, a);
11595 let r = _mm512_mask_sub_epi8(
11596 a,
11597 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
11598 a,
11599 b,
11600 );
11601 #[rustfmt::skip]
11602 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
11603 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
11604 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
11605 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1);
11606 assert_eq_m512i(r, e);
11607 }
11608
11609 #[simd_test(enable = "avx512bw")]
11610 unsafe fn test_mm512_maskz_sub_epi8() {
11611 let a = _mm512_set1_epi8(1);
11612 let b = _mm512_set1_epi8(2);
11613 let r = _mm512_maskz_sub_epi8(0, a, b);
11614 assert_eq_m512i(r, _mm512_setzero_si512());
11615 let r = _mm512_maskz_sub_epi8(
11616 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
11617 a,
11618 b,
11619 );
11620 #[rustfmt::skip]
11621 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1,
11622 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1,
11623 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1,
11624 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
11625 assert_eq_m512i(r, e);
11626 }
11627
11628 #[simd_test(enable = "avx512bw,avx512vl")]
11629 unsafe fn test_mm256_mask_sub_epi8() {
11630 let a = _mm256_set1_epi8(1);
11631 let b = _mm256_set1_epi8(2);
11632 let r = _mm256_mask_sub_epi8(a, 0, a, b);
11633 assert_eq_m256i(r, a);
11634 let r = _mm256_mask_sub_epi8(a, 0b00000000_11111111_00000000_11111111, a, b);
11635 #[rustfmt::skip]
11636 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1,
11637 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1);
11638 assert_eq_m256i(r, e);
11639 }
11640
11641 #[simd_test(enable = "avx512bw,avx512vl")]
11642 unsafe fn test_mm256_maskz_sub_epi8() {
11643 let a = _mm256_set1_epi8(1);
11644 let b = _mm256_set1_epi8(2);
11645 let r = _mm256_maskz_sub_epi8(0, a, b);
11646 assert_eq_m256i(r, _mm256_setzero_si256());
11647 let r = _mm256_maskz_sub_epi8(0b00000000_11111111_00000000_11111111, a, b);
11648 #[rustfmt::skip]
11649 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1,
11650 0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
11651 assert_eq_m256i(r, e);
11652 }
11653
11654 #[simd_test(enable = "avx512bw,avx512vl")]
11655 unsafe fn test_mm_mask_sub_epi8() {
11656 let a = _mm_set1_epi8(1);
11657 let b = _mm_set1_epi8(2);
11658 let r = _mm_mask_sub_epi8(a, 0, a, b);
11659 assert_eq_m128i(r, a);
11660 let r = _mm_mask_sub_epi8(a, 0b00000000_11111111, a, b);
11661 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1);
11662 assert_eq_m128i(r, e);
11663 }
11664
11665 #[simd_test(enable = "avx512bw,avx512vl")]
11666 unsafe fn test_mm_maskz_sub_epi8() {
11667 let a = _mm_set1_epi8(1);
11668 let b = _mm_set1_epi8(2);
11669 let r = _mm_maskz_sub_epi8(0, a, b);
11670 assert_eq_m128i(r, _mm_setzero_si128());
11671 let r = _mm_maskz_sub_epi8(0b00000000_11111111, a, b);
11672 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
11673 assert_eq_m128i(r, e);
11674 }
11675
11676 #[simd_test(enable = "avx512bw")]
11677 unsafe fn test_mm512_subs_epu16() {
11678 let a = _mm512_set1_epi16(1);
11679 let b = _mm512_set1_epi16(u16::MAX as i16);
11680 let r = _mm512_subs_epu16(a, b);
11681 let e = _mm512_set1_epi16(0);
11682 assert_eq_m512i(r, e);
11683 }
11684
11685 #[simd_test(enable = "avx512bw")]
11686 unsafe fn test_mm512_mask_subs_epu16() {
11687 let a = _mm512_set1_epi16(1);
11688 let b = _mm512_set1_epi16(u16::MAX as i16);
11689 let r = _mm512_mask_subs_epu16(a, 0, a, b);
11690 assert_eq_m512i(r, a);
11691 let r = _mm512_mask_subs_epu16(a, 0b00000000_00000000_00000000_00001111, a, b);
11692 #[rustfmt::skip]
11693 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
11695 assert_eq_m512i(r, e);
11696 }
11697
11698 #[simd_test(enable = "avx512bw")]
11699 unsafe fn test_mm512_maskz_subs_epu16() {
11700 let a = _mm512_set1_epi16(1);
11701 let b = _mm512_set1_epi16(u16::MAX as i16);
11702 let r = _mm512_maskz_subs_epu16(0, a, b);
11703 assert_eq_m512i(r, _mm512_setzero_si512());
11704 let r = _mm512_maskz_subs_epu16(0b00000000_00000000_00000000_00001111, a, b);
11705 #[rustfmt::skip]
11706 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
11708 assert_eq_m512i(r, e);
11709 }
11710
11711 #[simd_test(enable = "avx512bw,avx512vl")]
11712 unsafe fn test_mm256_mask_subs_epu16() {
11713 let a = _mm256_set1_epi16(1);
11714 let b = _mm256_set1_epi16(u16::MAX as i16);
11715 let r = _mm256_mask_subs_epu16(a, 0, a, b);
11716 assert_eq_m256i(r, a);
11717 let r = _mm256_mask_subs_epu16(a, 0b00000000_00001111, a, b);
11718 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
11719 assert_eq_m256i(r, e);
11720 }
11721
11722 #[simd_test(enable = "avx512bw,avx512vl")]
11723 unsafe fn test_mm256_maskz_subs_epu16() {
11724 let a = _mm256_set1_epi16(1);
11725 let b = _mm256_set1_epi16(u16::MAX as i16);
11726 let r = _mm256_maskz_subs_epu16(0, a, b);
11727 assert_eq_m256i(r, _mm256_setzero_si256());
11728 let r = _mm256_maskz_subs_epu16(0b00000000_00001111, a, b);
11729 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
11730 assert_eq_m256i(r, e);
11731 }
11732
11733 #[simd_test(enable = "avx512bw,avx512vl")]
11734 unsafe fn test_mm_mask_subs_epu16() {
11735 let a = _mm_set1_epi16(1);
11736 let b = _mm_set1_epi16(u16::MAX as i16);
11737 let r = _mm_mask_subs_epu16(a, 0, a, b);
11738 assert_eq_m128i(r, a);
11739 let r = _mm_mask_subs_epu16(a, 0b00001111, a, b);
11740 let e = _mm_set_epi16(1, 1, 1, 1, 0, 0, 0, 0);
11741 assert_eq_m128i(r, e);
11742 }
11743
11744 #[simd_test(enable = "avx512bw,avx512vl")]
11745 unsafe fn test_mm_maskz_subs_epu16() {
11746 let a = _mm_set1_epi16(1);
11747 let b = _mm_set1_epi16(u16::MAX as i16);
11748 let r = _mm_maskz_subs_epu16(0, a, b);
11749 assert_eq_m128i(r, _mm_setzero_si128());
11750 let r = _mm_maskz_subs_epu16(0b00001111, a, b);
11751 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 0, 0);
11752 assert_eq_m128i(r, e);
11753 }
11754
11755 #[simd_test(enable = "avx512bw")]
11756 unsafe fn test_mm512_subs_epu8() {
11757 let a = _mm512_set1_epi8(1);
11758 let b = _mm512_set1_epi8(u8::MAX as i8);
11759 let r = _mm512_subs_epu8(a, b);
11760 let e = _mm512_set1_epi8(0);
11761 assert_eq_m512i(r, e);
11762 }
11763
11764 #[simd_test(enable = "avx512bw")]
11765 unsafe fn test_mm512_mask_subs_epu8() {
11766 let a = _mm512_set1_epi8(1);
11767 let b = _mm512_set1_epi8(u8::MAX as i8);
11768 let r = _mm512_mask_subs_epu8(a, 0, a, b);
11769 assert_eq_m512i(r, a);
11770 let r = _mm512_mask_subs_epu8(
11771 a,
11772 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11773 a,
11774 b,
11775 );
11776 #[rustfmt::skip]
11777 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11778 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11779 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11780 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
11781 assert_eq_m512i(r, e);
11782 }
11783
11784 #[simd_test(enable = "avx512bw")]
11785 unsafe fn test_mm512_maskz_subs_epu8() {
11786 let a = _mm512_set1_epi8(1);
11787 let b = _mm512_set1_epi8(u8::MAX as i8);
11788 let r = _mm512_maskz_subs_epu8(0, a, b);
11789 assert_eq_m512i(r, _mm512_setzero_si512());
11790 let r = _mm512_maskz_subs_epu8(
11791 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11792 a,
11793 b,
11794 );
11795 #[rustfmt::skip]
11796 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11797 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11799 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
11800 assert_eq_m512i(r, e);
11801 }
11802
11803 #[simd_test(enable = "avx512bw,avx512vl")]
11804 unsafe fn test_mm256_mask_subs_epu8() {
11805 let a = _mm256_set1_epi8(1);
11806 let b = _mm256_set1_epi8(u8::MAX as i8);
11807 let r = _mm256_mask_subs_epu8(a, 0, a, b);
11808 assert_eq_m256i(r, a);
11809 let r = _mm256_mask_subs_epu8(a, 0b00000000_00000000_00000000_00001111, a, b);
11810 #[rustfmt::skip]
11811 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
11812 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
11813 assert_eq_m256i(r, e);
11814 }
11815
11816 #[simd_test(enable = "avx512bw,avx512vl")]
11817 unsafe fn test_mm256_maskz_subs_epu8() {
11818 let a = _mm256_set1_epi8(1);
11819 let b = _mm256_set1_epi8(u8::MAX as i8);
11820 let r = _mm256_maskz_subs_epu8(0, a, b);
11821 assert_eq_m256i(r, _mm256_setzero_si256());
11822 let r = _mm256_maskz_subs_epu8(0b00000000_00000000_00000000_00001111, a, b);
11823 #[rustfmt::skip]
11824 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11825 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
11826 assert_eq_m256i(r, e);
11827 }
11828
11829 #[simd_test(enable = "avx512bw,avx512vl")]
11830 unsafe fn test_mm_mask_subs_epu8() {
11831 let a = _mm_set1_epi8(1);
11832 let b = _mm_set1_epi8(u8::MAX as i8);
11833 let r = _mm_mask_subs_epu8(a, 0, a, b);
11834 assert_eq_m128i(r, a);
11835 let r = _mm_mask_subs_epu8(a, 0b00000000_00001111, a, b);
11836 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
11837 assert_eq_m128i(r, e);
11838 }
11839
11840 #[simd_test(enable = "avx512bw,avx512vl")]
11841 unsafe fn test_mm_maskz_subs_epu8() {
11842 let a = _mm_set1_epi8(1);
11843 let b = _mm_set1_epi8(u8::MAX as i8);
11844 let r = _mm_maskz_subs_epu8(0, a, b);
11845 assert_eq_m128i(r, _mm_setzero_si128());
11846 let r = _mm_maskz_subs_epu8(0b00000000_00001111, a, b);
11847 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
11848 assert_eq_m128i(r, e);
11849 }
11850
11851 #[simd_test(enable = "avx512bw")]
11852 unsafe fn test_mm512_subs_epi16() {
11853 let a = _mm512_set1_epi16(-1);
11854 let b = _mm512_set1_epi16(i16::MAX);
11855 let r = _mm512_subs_epi16(a, b);
11856 let e = _mm512_set1_epi16(i16::MIN);
11857 assert_eq_m512i(r, e);
11858 }
11859
11860 #[simd_test(enable = "avx512bw")]
11861 unsafe fn test_mm512_mask_subs_epi16() {
11862 let a = _mm512_set1_epi16(-1);
11863 let b = _mm512_set1_epi16(i16::MAX);
11864 let r = _mm512_mask_subs_epi16(a, 0, a, b);
11865 assert_eq_m512i(r, a);
11866 let r = _mm512_mask_subs_epi16(a, 0b00000000_00000000_00000000_00001111, a, b);
11867 #[rustfmt::skip]
11868 let e = _mm512_set_epi16(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
11869 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11870 assert_eq_m512i(r, e);
11871 }
11872
11873 #[simd_test(enable = "avx512bw")]
11874 unsafe fn test_mm512_maskz_subs_epi16() {
11875 let a = _mm512_set1_epi16(-1);
11876 let b = _mm512_set1_epi16(i16::MAX);
11877 let r = _mm512_maskz_subs_epi16(0, a, b);
11878 assert_eq_m512i(r, _mm512_setzero_si512());
11879 let r = _mm512_maskz_subs_epi16(0b00000000_00000000_00000000_00001111, a, b);
11880 #[rustfmt::skip]
11881 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11883 assert_eq_m512i(r, e);
11884 }
11885
11886 #[simd_test(enable = "avx512bw,avx512vl")]
11887 unsafe fn test_mm256_mask_subs_epi16() {
11888 let a = _mm256_set1_epi16(-1);
11889 let b = _mm256_set1_epi16(i16::MAX);
11890 let r = _mm256_mask_subs_epi16(a, 0, a, b);
11891 assert_eq_m256i(r, a);
11892 let r = _mm256_mask_subs_epi16(a, 0b00000000_00001111, a, b);
11893 #[rustfmt::skip]
11894 let e = _mm256_set_epi16(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11895 assert_eq_m256i(r, e);
11896 }
11897
11898 #[simd_test(enable = "avx512bw,avx512vl")]
11899 unsafe fn test_mm256_maskz_subs_epi16() {
11900 let a = _mm256_set1_epi16(-1);
11901 let b = _mm256_set1_epi16(i16::MAX);
11902 let r = _mm256_maskz_subs_epi16(0, a, b);
11903 assert_eq_m256i(r, _mm256_setzero_si256());
11904 let r = _mm256_maskz_subs_epi16(0b00000000_00001111, a, b);
11905 #[rustfmt::skip]
11906 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11907 assert_eq_m256i(r, e);
11908 }
11909
11910 #[simd_test(enable = "avx512bw,avx512vl")]
11911 unsafe fn test_mm_mask_subs_epi16() {
11912 let a = _mm_set1_epi16(-1);
11913 let b = _mm_set1_epi16(i16::MAX);
11914 let r = _mm_mask_subs_epi16(a, 0, a, b);
11915 assert_eq_m128i(r, a);
11916 let r = _mm_mask_subs_epi16(a, 0b00001111, a, b);
11917 let e = _mm_set_epi16(-1, -1, -1, -1, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11918 assert_eq_m128i(r, e);
11919 }
11920
11921 #[simd_test(enable = "avx512bw,avx512vl")]
11922 unsafe fn test_mm_maskz_subs_epi16() {
11923 let a = _mm_set1_epi16(-1);
11924 let b = _mm_set1_epi16(i16::MAX);
11925 let r = _mm_maskz_subs_epi16(0, a, b);
11926 assert_eq_m128i(r, _mm_setzero_si128());
11927 let r = _mm_maskz_subs_epi16(0b00001111, a, b);
11928 let e = _mm_set_epi16(0, 0, 0, 0, i16::MIN, i16::MIN, i16::MIN, i16::MIN);
11929 assert_eq_m128i(r, e);
11930 }
11931
11932 #[simd_test(enable = "avx512bw")]
11933 unsafe fn test_mm512_subs_epi8() {
11934 let a = _mm512_set1_epi8(-1);
11935 let b = _mm512_set1_epi8(i8::MAX);
11936 let r = _mm512_subs_epi8(a, b);
11937 let e = _mm512_set1_epi8(i8::MIN);
11938 assert_eq_m512i(r, e);
11939 }
11940
11941 #[simd_test(enable = "avx512bw")]
11942 unsafe fn test_mm512_mask_subs_epi8() {
11943 let a = _mm512_set1_epi8(-1);
11944 let b = _mm512_set1_epi8(i8::MAX);
11945 let r = _mm512_mask_subs_epi8(a, 0, a, b);
11946 assert_eq_m512i(r, a);
11947 let r = _mm512_mask_subs_epi8(
11948 a,
11949 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11950 a,
11951 b,
11952 );
11953 #[rustfmt::skip]
11954 let e = _mm512_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
11955 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
11956 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
11957 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
11958 assert_eq_m512i(r, e);
11959 }
11960
11961 #[simd_test(enable = "avx512bw")]
11962 unsafe fn test_mm512_maskz_subs_epi8() {
11963 let a = _mm512_set1_epi8(-1);
11964 let b = _mm512_set1_epi8(i8::MAX);
11965 let r = _mm512_maskz_subs_epi8(0, a, b);
11966 assert_eq_m512i(r, _mm512_setzero_si512());
11967 let r = _mm512_maskz_subs_epi8(
11968 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
11969 a,
11970 b,
11971 );
11972 #[rustfmt::skip]
11973 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11974 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11975 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
11976 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
11977 assert_eq_m512i(r, e);
11978 }
11979
11980 #[simd_test(enable = "avx512bw,avx512vl")]
11981 unsafe fn test_mm256_mask_subs_epi8() {
11982 let a = _mm256_set1_epi8(-1);
11983 let b = _mm256_set1_epi8(i8::MAX);
11984 let r = _mm256_mask_subs_epi8(a, 0, a, b);
11985 assert_eq_m256i(r, a);
11986 let r = _mm256_mask_subs_epi8(a, 0b00000000_00000000_00000000_00001111, a, b);
11987 #[rustfmt::skip]
11988 let e = _mm256_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
11989 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
11990 assert_eq_m256i(r, e);
11991 }
11992
11993 #[simd_test(enable = "avx512bw,avx512vl")]
11994 unsafe fn test_mm256_maskz_subs_epi8() {
11995 let a = _mm256_set1_epi8(-1);
11996 let b = _mm256_set1_epi8(i8::MAX);
11997 let r = _mm256_maskz_subs_epi8(0, a, b);
11998 assert_eq_m256i(r, _mm256_setzero_si256());
11999 let r = _mm256_maskz_subs_epi8(0b00000000_00000000_00000000_00001111, a, b);
12000 #[rustfmt::skip]
12001 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12002 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
12003 assert_eq_m256i(r, e);
12004 }
12005
12006 #[simd_test(enable = "avx512bw,avx512vl")]
12007 unsafe fn test_mm_mask_subs_epi8() {
12008 let a = _mm_set1_epi8(-1);
12009 let b = _mm_set1_epi8(i8::MAX);
12010 let r = _mm_mask_subs_epi8(a, 0, a, b);
12011 assert_eq_m128i(r, a);
12012 let r = _mm_mask_subs_epi8(a, 0b00000000_00001111, a, b);
12013 #[rustfmt::skip]
12014 let e = _mm_set_epi8(-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
12015 assert_eq_m128i(r, e);
12016 }
12017
12018 #[simd_test(enable = "avx512bw,avx512vl")]
12019 unsafe fn test_mm_maskz_subs_epi8() {
12020 let a = _mm_set1_epi8(-1);
12021 let b = _mm_set1_epi8(i8::MAX);
12022 let r = _mm_maskz_subs_epi8(0, a, b);
12023 assert_eq_m128i(r, _mm_setzero_si128());
12024 let r = _mm_maskz_subs_epi8(0b00000000_00001111, a, b);
12025 #[rustfmt::skip]
12026 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MIN, i8::MIN, i8::MIN, i8::MIN);
12027 assert_eq_m128i(r, e);
12028 }
12029
12030 #[simd_test(enable = "avx512bw")]
12031 unsafe fn test_mm512_mulhi_epu16() {
12032 let a = _mm512_set1_epi16(1);
12033 let b = _mm512_set1_epi16(1);
12034 let r = _mm512_mulhi_epu16(a, b);
12035 let e = _mm512_set1_epi16(0);
12036 assert_eq_m512i(r, e);
12037 }
12038
12039 #[simd_test(enable = "avx512bw")]
12040 unsafe fn test_mm512_mask_mulhi_epu16() {
12041 let a = _mm512_set1_epi16(1);
12042 let b = _mm512_set1_epi16(1);
12043 let r = _mm512_mask_mulhi_epu16(a, 0, a, b);
12044 assert_eq_m512i(r, a);
12045 let r = _mm512_mask_mulhi_epu16(a, 0b00000000_00000000_00000000_00001111, a, b);
12046 #[rustfmt::skip]
12047 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
12048 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12049 assert_eq_m512i(r, e);
12050 }
12051
12052 #[simd_test(enable = "avx512bw")]
12053 unsafe fn test_mm512_maskz_mulhi_epu16() {
12054 let a = _mm512_set1_epi16(1);
12055 let b = _mm512_set1_epi16(1);
12056 let r = _mm512_maskz_mulhi_epu16(0, a, b);
12057 assert_eq_m512i(r, _mm512_setzero_si512());
12058 let r = _mm512_maskz_mulhi_epu16(0b00000000_00000000_00000000_00001111, a, b);
12059 #[rustfmt::skip]
12060 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12061 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12062 assert_eq_m512i(r, e);
12063 }
12064
12065 #[simd_test(enable = "avx512bw,avx512vl")]
12066 unsafe fn test_mm256_mask_mulhi_epu16() {
12067 let a = _mm256_set1_epi16(1);
12068 let b = _mm256_set1_epi16(1);
12069 let r = _mm256_mask_mulhi_epu16(a, 0, a, b);
12070 assert_eq_m256i(r, a);
12071 let r = _mm256_mask_mulhi_epu16(a, 0b00000000_00001111, a, b);
12072 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12073 assert_eq_m256i(r, e);
12074 }
12075
12076 #[simd_test(enable = "avx512bw,avx512vl")]
12077 unsafe fn test_mm256_maskz_mulhi_epu16() {
12078 let a = _mm256_set1_epi16(1);
12079 let b = _mm256_set1_epi16(1);
12080 let r = _mm256_maskz_mulhi_epu16(0, a, b);
12081 assert_eq_m256i(r, _mm256_setzero_si256());
12082 let r = _mm256_maskz_mulhi_epu16(0b00000000_00001111, a, b);
12083 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12084 assert_eq_m256i(r, e);
12085 }
12086
12087 #[simd_test(enable = "avx512bw,avx512vl")]
12088 unsafe fn test_mm_mask_mulhi_epu16() {
12089 let a = _mm_set1_epi16(1);
12090 let b = _mm_set1_epi16(1);
12091 let r = _mm_mask_mulhi_epu16(a, 0, a, b);
12092 assert_eq_m128i(r, a);
12093 let r = _mm_mask_mulhi_epu16(a, 0b00001111, a, b);
12094 let e = _mm_set_epi16(1, 1, 1, 1, 0, 0, 0, 0);
12095 assert_eq_m128i(r, e);
12096 }
12097
12098 #[simd_test(enable = "avx512bw,avx512vl")]
12099 unsafe fn test_mm_maskz_mulhi_epu16() {
12100 let a = _mm_set1_epi16(1);
12101 let b = _mm_set1_epi16(1);
12102 let r = _mm_maskz_mulhi_epu16(0, a, b);
12103 assert_eq_m128i(r, _mm_setzero_si128());
12104 let r = _mm_maskz_mulhi_epu16(0b00001111, a, b);
12105 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 0, 0);
12106 assert_eq_m128i(r, e);
12107 }
12108
12109 #[simd_test(enable = "avx512bw")]
12110 unsafe fn test_mm512_mulhi_epi16() {
12111 let a = _mm512_set1_epi16(1);
12112 let b = _mm512_set1_epi16(1);
12113 let r = _mm512_mulhi_epi16(a, b);
12114 let e = _mm512_set1_epi16(0);
12115 assert_eq_m512i(r, e);
12116 }
12117
12118 #[simd_test(enable = "avx512bw")]
12119 unsafe fn test_mm512_mask_mulhi_epi16() {
12120 let a = _mm512_set1_epi16(1);
12121 let b = _mm512_set1_epi16(1);
12122 let r = _mm512_mask_mulhi_epi16(a, 0, a, b);
12123 assert_eq_m512i(r, a);
12124 let r = _mm512_mask_mulhi_epi16(a, 0b00000000_00000000_00000000_00001111, a, b);
12125 #[rustfmt::skip]
12126 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
12127 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12128 assert_eq_m512i(r, e);
12129 }
12130
12131 #[simd_test(enable = "avx512bw")]
12132 unsafe fn test_mm512_maskz_mulhi_epi16() {
12133 let a = _mm512_set1_epi16(1);
12134 let b = _mm512_set1_epi16(1);
12135 let r = _mm512_maskz_mulhi_epi16(0, a, b);
12136 assert_eq_m512i(r, _mm512_setzero_si512());
12137 let r = _mm512_maskz_mulhi_epi16(0b00000000_00000000_00000000_00001111, a, b);
12138 #[rustfmt::skip]
12139 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12141 assert_eq_m512i(r, e);
12142 }
12143
12144 #[simd_test(enable = "avx512bw,avx512vl")]
12145 unsafe fn test_mm256_mask_mulhi_epi16() {
12146 let a = _mm256_set1_epi16(1);
12147 let b = _mm256_set1_epi16(1);
12148 let r = _mm256_mask_mulhi_epi16(a, 0, a, b);
12149 assert_eq_m256i(r, a);
12150 let r = _mm256_mask_mulhi_epi16(a, 0b00000000_00001111, a, b);
12151 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12152 assert_eq_m256i(r, e);
12153 }
12154
12155 #[simd_test(enable = "avx512bw,avx512vl")]
12156 unsafe fn test_mm256_maskz_mulhi_epi16() {
12157 let a = _mm256_set1_epi16(1);
12158 let b = _mm256_set1_epi16(1);
12159 let r = _mm256_maskz_mulhi_epi16(0, a, b);
12160 assert_eq_m256i(r, _mm256_setzero_si256());
12161 let r = _mm256_maskz_mulhi_epi16(0b00000000_00001111, a, b);
12162 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12163 assert_eq_m256i(r, e);
12164 }
12165
12166 #[simd_test(enable = "avx512bw,avx512vl")]
12167 unsafe fn test_mm_mask_mulhi_epi16() {
12168 let a = _mm_set1_epi16(1);
12169 let b = _mm_set1_epi16(1);
12170 let r = _mm_mask_mulhi_epi16(a, 0, a, b);
12171 assert_eq_m128i(r, a);
12172 let r = _mm_mask_mulhi_epi16(a, 0b00001111, a, b);
12173 let e = _mm_set_epi16(1, 1, 1, 1, 0, 0, 0, 0);
12174 assert_eq_m128i(r, e);
12175 }
12176
12177 #[simd_test(enable = "avx512bw,avx512vl")]
12178 unsafe fn test_mm_maskz_mulhi_epi16() {
12179 let a = _mm_set1_epi16(1);
12180 let b = _mm_set1_epi16(1);
12181 let r = _mm_maskz_mulhi_epi16(0, a, b);
12182 assert_eq_m128i(r, _mm_setzero_si128());
12183 let r = _mm_maskz_mulhi_epi16(0b00001111, a, b);
12184 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 0, 0);
12185 assert_eq_m128i(r, e);
12186 }
12187
12188 #[simd_test(enable = "avx512bw")]
12189 unsafe fn test_mm512_mulhrs_epi16() {
12190 let a = _mm512_set1_epi16(1);
12191 let b = _mm512_set1_epi16(1);
12192 let r = _mm512_mulhrs_epi16(a, b);
12193 let e = _mm512_set1_epi16(0);
12194 assert_eq_m512i(r, e);
12195 }
12196
12197 #[simd_test(enable = "avx512bw")]
12198 unsafe fn test_mm512_mask_mulhrs_epi16() {
12199 let a = _mm512_set1_epi16(1);
12200 let b = _mm512_set1_epi16(1);
12201 let r = _mm512_mask_mulhrs_epi16(a, 0, a, b);
12202 assert_eq_m512i(r, a);
12203 let r = _mm512_mask_mulhrs_epi16(a, 0b00000000_00000000_00000000_00001111, a, b);
12204 #[rustfmt::skip]
12205 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
12206 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12207 assert_eq_m512i(r, e);
12208 }
12209
12210 #[simd_test(enable = "avx512bw")]
12211 unsafe fn test_mm512_maskz_mulhrs_epi16() {
12212 let a = _mm512_set1_epi16(1);
12213 let b = _mm512_set1_epi16(1);
12214 let r = _mm512_maskz_mulhrs_epi16(0, a, b);
12215 assert_eq_m512i(r, _mm512_setzero_si512());
12216 let r = _mm512_maskz_mulhrs_epi16(0b00000000_00000000_00000000_00001111, a, b);
12217 #[rustfmt::skip]
12218 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12220 assert_eq_m512i(r, e);
12221 }
12222
12223 #[simd_test(enable = "avx512bw,avx512vl")]
12224 unsafe fn test_mm256_mask_mulhrs_epi16() {
12225 let a = _mm256_set1_epi16(1);
12226 let b = _mm256_set1_epi16(1);
12227 let r = _mm256_mask_mulhrs_epi16(a, 0, a, b);
12228 assert_eq_m256i(r, a);
12229 let r = _mm256_mask_mulhrs_epi16(a, 0b00000000_00001111, a, b);
12230 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
12231 assert_eq_m256i(r, e);
12232 }
12233
12234 #[simd_test(enable = "avx512bw,avx512vl")]
12235 unsafe fn test_mm256_maskz_mulhrs_epi16() {
12236 let a = _mm256_set1_epi16(1);
12237 let b = _mm256_set1_epi16(1);
12238 let r = _mm256_maskz_mulhrs_epi16(0, a, b);
12239 assert_eq_m256i(r, _mm256_setzero_si256());
12240 let r = _mm256_maskz_mulhrs_epi16(0b00000000_00001111, a, b);
12241 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
12242 assert_eq_m256i(r, e);
12243 }
12244
12245 #[simd_test(enable = "avx512bw,avx512vl")]
12246 unsafe fn test_mm_mask_mulhrs_epi16() {
12247 let a = _mm_set1_epi16(1);
12248 let b = _mm_set1_epi16(1);
12249 let r = _mm_mask_mulhrs_epi16(a, 0, a, b);
12250 assert_eq_m128i(r, a);
12251 let r = _mm_mask_mulhrs_epi16(a, 0b00001111, a, b);
12252 let e = _mm_set_epi16(1, 1, 1, 1, 0, 0, 0, 0);
12253 assert_eq_m128i(r, e);
12254 }
12255
12256 #[simd_test(enable = "avx512bw,avx512vl")]
12257 unsafe fn test_mm_maskz_mulhrs_epi16() {
12258 let a = _mm_set1_epi16(1);
12259 let b = _mm_set1_epi16(1);
12260 let r = _mm_maskz_mulhrs_epi16(0, a, b);
12261 assert_eq_m128i(r, _mm_setzero_si128());
12262 let r = _mm_maskz_mulhrs_epi16(0b00001111, a, b);
12263 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 0, 0);
12264 assert_eq_m128i(r, e);
12265 }
12266
12267 #[simd_test(enable = "avx512bw")]
12268 unsafe fn test_mm512_mullo_epi16() {
12269 let a = _mm512_set1_epi16(1);
12270 let b = _mm512_set1_epi16(1);
12271 let r = _mm512_mullo_epi16(a, b);
12272 let e = _mm512_set1_epi16(1);
12273 assert_eq_m512i(r, e);
12274 }
12275
12276 #[simd_test(enable = "avx512bw")]
12277 unsafe fn test_mm512_mask_mullo_epi16() {
12278 let a = _mm512_set1_epi16(1);
12279 let b = _mm512_set1_epi16(1);
12280 let r = _mm512_mask_mullo_epi16(a, 0, a, b);
12281 assert_eq_m512i(r, a);
12282 let r = _mm512_mask_mullo_epi16(a, 0b00000000_00000000_00000000_00001111, a, b);
12283 #[rustfmt::skip]
12284 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
12285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
12286 assert_eq_m512i(r, e);
12287 }
12288
12289 #[simd_test(enable = "avx512bw")]
12290 unsafe fn test_mm512_maskz_mullo_epi16() {
12291 let a = _mm512_set1_epi16(1);
12292 let b = _mm512_set1_epi16(1);
12293 let r = _mm512_maskz_mullo_epi16(0, a, b);
12294 assert_eq_m512i(r, _mm512_setzero_si512());
12295 let r = _mm512_maskz_mullo_epi16(0b00000000_00000000_00000000_00001111, a, b);
12296 #[rustfmt::skip]
12297 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
12298 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
12299 assert_eq_m512i(r, e);
12300 }
12301
12302 #[simd_test(enable = "avx512bw,avx512vl")]
12303 unsafe fn test_mm256_mask_mullo_epi16() {
12304 let a = _mm256_set1_epi16(1);
12305 let b = _mm256_set1_epi16(1);
12306 let r = _mm256_mask_mullo_epi16(a, 0, a, b);
12307 assert_eq_m256i(r, a);
12308 let r = _mm256_mask_mullo_epi16(a, 0b00000000_00001111, a, b);
12309 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
12310 assert_eq_m256i(r, e);
12311 }
12312
12313 #[simd_test(enable = "avx512bw,avx512vl")]
12314 unsafe fn test_mm256_maskz_mullo_epi16() {
12315 let a = _mm256_set1_epi16(1);
12316 let b = _mm256_set1_epi16(1);
12317 let r = _mm256_maskz_mullo_epi16(0, a, b);
12318 assert_eq_m256i(r, _mm256_setzero_si256());
12319 let r = _mm256_maskz_mullo_epi16(0b00000000_00001111, a, b);
12320 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
12321 assert_eq_m256i(r, e);
12322 }
12323
12324 #[simd_test(enable = "avx512bw,avx512vl")]
12325 unsafe fn test_mm_mask_mullo_epi16() {
12326 let a = _mm_set1_epi16(1);
12327 let b = _mm_set1_epi16(1);
12328 let r = _mm_mask_mullo_epi16(a, 0, a, b);
12329 assert_eq_m128i(r, a);
12330 let r = _mm_mask_mullo_epi16(a, 0b00001111, a, b);
12331 let e = _mm_set_epi16(1, 1, 1, 1, 1, 1, 1, 1);
12332 assert_eq_m128i(r, e);
12333 }
12334
12335 #[simd_test(enable = "avx512bw,avx512vl")]
12336 unsafe fn test_mm_maskz_mullo_epi16() {
12337 let a = _mm_set1_epi16(1);
12338 let b = _mm_set1_epi16(1);
12339 let r = _mm_maskz_mullo_epi16(0, a, b);
12340 assert_eq_m128i(r, _mm_setzero_si128());
12341 let r = _mm_maskz_mullo_epi16(0b00001111, a, b);
12342 let e = _mm_set_epi16(0, 0, 0, 0, 1, 1, 1, 1);
12343 assert_eq_m128i(r, e);
12344 }
12345
12346 #[simd_test(enable = "avx512bw")]
12347 unsafe fn test_mm512_max_epu16() {
12348 #[rustfmt::skip]
12349 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12350 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12351 #[rustfmt::skip]
12352 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12353 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12354 let r = _mm512_max_epu16(a, b);
12355 #[rustfmt::skip]
12356 let e = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12357 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
12358 assert_eq_m512i(r, e);
12359 }
12360
12361 #[simd_test(enable = "avx512f")]
12362 unsafe fn test_mm512_mask_max_epu16() {
12363 #[rustfmt::skip]
12364 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12365 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12366 #[rustfmt::skip]
12367 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12368 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12369 let r = _mm512_mask_max_epu16(a, 0, a, b);
12370 assert_eq_m512i(r, a);
12371 let r = _mm512_mask_max_epu16(a, 0b00000000_11111111_00000000_11111111, a, b);
12372 #[rustfmt::skip]
12373 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12374 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12375 assert_eq_m512i(r, e);
12376 }
12377
12378 #[simd_test(enable = "avx512f")]
12379 unsafe fn test_mm512_maskz_max_epu16() {
12380 #[rustfmt::skip]
12381 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12382 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12383 #[rustfmt::skip]
12384 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12385 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12386 let r = _mm512_maskz_max_epu16(0, a, b);
12387 assert_eq_m512i(r, _mm512_setzero_si512());
12388 let r = _mm512_maskz_max_epu16(0b00000000_11111111_00000000_11111111, a, b);
12389 #[rustfmt::skip]
12390 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12391 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12392 assert_eq_m512i(r, e);
12393 }
12394
12395 #[simd_test(enable = "avx512f,avx512vl")]
12396 unsafe fn test_mm256_mask_max_epu16() {
12397 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12398 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12399 let r = _mm256_mask_max_epu16(a, 0, a, b);
12400 assert_eq_m256i(r, a);
12401 let r = _mm256_mask_max_epu16(a, 0b00000000_11111111, a, b);
12402 let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12403 assert_eq_m256i(r, e);
12404 }
12405
12406 #[simd_test(enable = "avx512f,avx512vl")]
12407 unsafe fn test_mm256_maskz_max_epu16() {
12408 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12409 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12410 let r = _mm256_maskz_max_epu16(0, a, b);
12411 assert_eq_m256i(r, _mm256_setzero_si256());
12412 let r = _mm256_maskz_max_epu16(0b00000000_11111111, a, b);
12413 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12414 assert_eq_m256i(r, e);
12415 }
12416
12417 #[simd_test(enable = "avx512f,avx512vl")]
12418 unsafe fn test_mm_mask_max_epu16() {
12419 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12420 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12421 let r = _mm_mask_max_epu16(a, 0, a, b);
12422 assert_eq_m128i(r, a);
12423 let r = _mm_mask_max_epu16(a, 0b00001111, a, b);
12424 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12425 assert_eq_m128i(r, e);
12426 }
12427
12428 #[simd_test(enable = "avx512f,avx512vl")]
12429 unsafe fn test_mm_maskz_max_epu16() {
12430 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12431 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12432 let r = _mm_maskz_max_epu16(0, a, b);
12433 assert_eq_m128i(r, _mm_setzero_si128());
12434 let r = _mm_maskz_max_epu16(0b00001111, a, b);
12435 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, 7);
12436 assert_eq_m128i(r, e);
12437 }
12438
12439 #[simd_test(enable = "avx512bw")]
12440 unsafe fn test_mm512_max_epu8() {
12441 #[rustfmt::skip]
12442 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12443 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12444 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12445 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12446 #[rustfmt::skip]
12447 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12448 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12449 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12450 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12451 let r = _mm512_max_epu8(a, b);
12452 #[rustfmt::skip]
12453 let e = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12454 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12455 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12456 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
12457 assert_eq_m512i(r, e);
12458 }
12459
12460 #[simd_test(enable = "avx512f")]
12461 unsafe fn test_mm512_mask_max_epu8() {
12462 #[rustfmt::skip]
12463 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12464 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12465 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12466 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12467 #[rustfmt::skip]
12468 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12469 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12470 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12471 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12472 let r = _mm512_mask_max_epu8(a, 0, a, b);
12473 assert_eq_m512i(r, a);
12474 let r = _mm512_mask_max_epu8(
12475 a,
12476 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12477 a,
12478 b,
12479 );
12480 #[rustfmt::skip]
12481 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12482 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12483 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12484 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12485 assert_eq_m512i(r, e);
12486 }
12487
12488 #[simd_test(enable = "avx512f")]
12489 unsafe fn test_mm512_maskz_max_epu8() {
12490 #[rustfmt::skip]
12491 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12492 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12493 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12494 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12495 #[rustfmt::skip]
12496 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12497 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12498 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12499 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12500 let r = _mm512_maskz_max_epu8(0, a, b);
12501 assert_eq_m512i(r, _mm512_setzero_si512());
12502 let r = _mm512_maskz_max_epu8(
12503 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12504 a,
12505 b,
12506 );
12507 #[rustfmt::skip]
12508 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12509 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12510 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12511 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12512 assert_eq_m512i(r, e);
12513 }
12514
12515 #[simd_test(enable = "avx512f,avx512vl")]
12516 unsafe fn test_mm256_mask_max_epu8() {
12517 #[rustfmt::skip]
12518 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12519 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12520 #[rustfmt::skip]
12521 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12522 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12523 let r = _mm256_mask_max_epu8(a, 0, a, b);
12524 assert_eq_m256i(r, a);
12525 let r = _mm256_mask_max_epu8(a, 0b00000000_11111111_00000000_11111111, a, b);
12526 #[rustfmt::skip]
12527 let e = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12528 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12529 assert_eq_m256i(r, e);
12530 }
12531
12532 #[simd_test(enable = "avx512f,avx512vl")]
12533 unsafe fn test_mm256_maskz_max_epu8() {
12534 #[rustfmt::skip]
12535 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12536 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12537 #[rustfmt::skip]
12538 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12539 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12540 let r = _mm256_maskz_max_epu8(0, a, b);
12541 assert_eq_m256i(r, _mm256_setzero_si256());
12542 let r = _mm256_maskz_max_epu8(0b00000000_11111111_00000000_11111111, a, b);
12543 #[rustfmt::skip]
12544 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12545 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12546 assert_eq_m256i(r, e);
12547 }
12548
12549 #[simd_test(enable = "avx512f,avx512vl")]
12550 unsafe fn test_mm_mask_max_epu8() {
12551 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12552 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12553 let r = _mm_mask_max_epu8(a, 0, a, b);
12554 assert_eq_m128i(r, a);
12555 let r = _mm_mask_max_epu8(a, 0b00000000_11111111, a, b);
12556 let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12557 assert_eq_m128i(r, e);
12558 }
12559
12560 #[simd_test(enable = "avx512f,avx512vl")]
12561 unsafe fn test_mm_maskz_max_epu8() {
12562 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12563 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12564 let r = _mm_maskz_max_epu8(0, a, b);
12565 assert_eq_m128i(r, _mm_setzero_si128());
12566 let r = _mm_maskz_max_epu8(0b00000000_11111111, a, b);
12567 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12568 assert_eq_m128i(r, e);
12569 }
12570
12571 #[simd_test(enable = "avx512bw")]
12572 unsafe fn test_mm512_max_epi16() {
12573 #[rustfmt::skip]
12574 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12575 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12576 #[rustfmt::skip]
12577 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12578 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12579 let r = _mm512_max_epi16(a, b);
12580 #[rustfmt::skip]
12581 let e = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12582 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
12583 assert_eq_m512i(r, e);
12584 }
12585
12586 #[simd_test(enable = "avx512f")]
12587 unsafe fn test_mm512_mask_max_epi16() {
12588 #[rustfmt::skip]
12589 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12590 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12591 #[rustfmt::skip]
12592 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12593 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12594 let r = _mm512_mask_max_epi16(a, 0, a, b);
12595 assert_eq_m512i(r, a);
12596 let r = _mm512_mask_max_epi16(a, 0b00000000_11111111_00000000_11111111, a, b);
12597 #[rustfmt::skip]
12598 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12599 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12600 assert_eq_m512i(r, e);
12601 }
12602
12603 #[simd_test(enable = "avx512f")]
12604 unsafe fn test_mm512_maskz_max_epi16() {
12605 #[rustfmt::skip]
12606 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12607 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12608 #[rustfmt::skip]
12609 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12610 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12611 let r = _mm512_maskz_max_epi16(0, a, b);
12612 assert_eq_m512i(r, _mm512_setzero_si512());
12613 let r = _mm512_maskz_max_epi16(0b00000000_11111111_00000000_11111111, a, b);
12614 #[rustfmt::skip]
12615 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12616 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12617 assert_eq_m512i(r, e);
12618 }
12619
12620 #[simd_test(enable = "avx512f,avx512vl")]
12621 unsafe fn test_mm256_mask_max_epi16() {
12622 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12623 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12624 let r = _mm256_mask_max_epi16(a, 0, a, b);
12625 assert_eq_m256i(r, a);
12626 let r = _mm256_mask_max_epi16(a, 0b00000000_11111111, a, b);
12627 let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12628 assert_eq_m256i(r, e);
12629 }
12630
12631 #[simd_test(enable = "avx512f,avx512vl")]
12632 unsafe fn test_mm256_maskz_max_epi16() {
12633 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12634 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12635 let r = _mm256_maskz_max_epi16(0, a, b);
12636 assert_eq_m256i(r, _mm256_setzero_si256());
12637 let r = _mm256_maskz_max_epi16(0b00000000_11111111, a, b);
12638 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12639 assert_eq_m256i(r, e);
12640 }
12641
12642 #[simd_test(enable = "avx512f,avx512vl")]
12643 unsafe fn test_mm_mask_max_epi16() {
12644 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12645 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12646 let r = _mm_mask_max_epi16(a, 0, a, b);
12647 assert_eq_m128i(r, a);
12648 let r = _mm_mask_max_epi16(a, 0b00001111, a, b);
12649 let e = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12650 assert_eq_m128i(r, e);
12651 }
12652
12653 #[simd_test(enable = "avx512f,avx512vl")]
12654 unsafe fn test_mm_maskz_max_epi16() {
12655 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12656 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12657 let r = _mm_maskz_max_epi16(0, a, b);
12658 assert_eq_m128i(r, _mm_setzero_si128());
12659 let r = _mm_maskz_max_epi16(0b00001111, a, b);
12660 let e = _mm_set_epi16(0, 0, 0, 0, 4, 5, 6, 7);
12661 assert_eq_m128i(r, e);
12662 }
12663
12664 #[simd_test(enable = "avx512bw")]
12665 unsafe fn test_mm512_max_epi8() {
12666 #[rustfmt::skip]
12667 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12668 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12669 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12670 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12671 #[rustfmt::skip]
12672 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12673 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12674 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12675 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12676 let r = _mm512_max_epi8(a, b);
12677 #[rustfmt::skip]
12678 let e = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12679 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12680 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15,
12681 15, 14, 13, 12, 11, 10, 9, 8, 8, 9, 10, 11, 12, 13, 14, 15);
12682 assert_eq_m512i(r, e);
12683 }
12684
12685 #[simd_test(enable = "avx512f")]
12686 unsafe fn test_mm512_mask_max_epi8() {
12687 #[rustfmt::skip]
12688 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12689 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12690 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12691 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12692 #[rustfmt::skip]
12693 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12694 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12695 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12696 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12697 let r = _mm512_mask_max_epi8(a, 0, a, b);
12698 assert_eq_m512i(r, a);
12699 let r = _mm512_mask_max_epi8(
12700 a,
12701 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12702 a,
12703 b,
12704 );
12705 #[rustfmt::skip]
12706 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12707 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12708 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12709 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12710 assert_eq_m512i(r, e);
12711 }
12712
12713 #[simd_test(enable = "avx512f")]
12714 unsafe fn test_mm512_maskz_max_epi8() {
12715 #[rustfmt::skip]
12716 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12717 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12718 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12719 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12720 #[rustfmt::skip]
12721 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12722 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12723 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12724 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12725 let r = _mm512_maskz_max_epi8(0, a, b);
12726 assert_eq_m512i(r, _mm512_setzero_si512());
12727 let r = _mm512_maskz_max_epi8(
12728 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12729 a,
12730 b,
12731 );
12732 #[rustfmt::skip]
12733 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12734 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12735 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12736 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12737 assert_eq_m512i(r, e);
12738 }
12739
12740 #[simd_test(enable = "avx512f,avx512vl")]
12741 unsafe fn test_mm256_mask_max_epi8() {
12742 #[rustfmt::skip]
12743 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12744 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12745 #[rustfmt::skip]
12746 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12747 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12748 let r = _mm256_mask_max_epi8(a, 0, a, b);
12749 assert_eq_m256i(r, a);
12750 let r = _mm256_mask_max_epi8(a, 0b00000000_11111111_00000000_11111111, a, b);
12751 #[rustfmt::skip]
12752 let e = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12753 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12754 assert_eq_m256i(r, e);
12755 }
12756
12757 #[simd_test(enable = "avx512f,avx512vl")]
12758 unsafe fn test_mm256_maskz_max_epi8() {
12759 #[rustfmt::skip]
12760 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12761 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12762 #[rustfmt::skip]
12763 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12764 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12765 let r = _mm256_maskz_max_epi8(0, a, b);
12766 assert_eq_m256i(r, _mm256_setzero_si256());
12767 let r = _mm256_maskz_max_epi8(0b00000000_11111111_00000000_11111111, a, b);
12768 #[rustfmt::skip]
12769 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15,
12770 0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12771 assert_eq_m256i(r, e);
12772 }
12773
12774 #[simd_test(enable = "avx512f,avx512vl")]
12775 unsafe fn test_mm_mask_max_epi8() {
12776 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12777 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12778 let r = _mm_mask_max_epi8(a, 0, a, b);
12779 assert_eq_m128i(r, a);
12780 let r = _mm_mask_max_epi8(a, 0b00000000_11111111, a, b);
12781 let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12782 assert_eq_m128i(r, e);
12783 }
12784
12785 #[simd_test(enable = "avx512f,avx512vl")]
12786 unsafe fn test_mm_maskz_max_epi8() {
12787 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12788 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12789 let r = _mm_maskz_max_epi8(0, a, b);
12790 assert_eq_m128i(r, _mm_setzero_si128());
12791 let r = _mm_maskz_max_epi8(0b00000000_11111111, a, b);
12792 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 9, 10, 11, 12, 13, 14, 15);
12793 assert_eq_m128i(r, e);
12794 }
12795
12796 #[simd_test(enable = "avx512bw")]
12797 unsafe fn test_mm512_min_epu16() {
12798 #[rustfmt::skip]
12799 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12800 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12801 #[rustfmt::skip]
12802 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12803 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12804 let r = _mm512_min_epu16(a, b);
12805 #[rustfmt::skip]
12806 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12807 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12808 assert_eq_m512i(r, e);
12809 }
12810
12811 #[simd_test(enable = "avx512f")]
12812 unsafe fn test_mm512_mask_min_epu16() {
12813 #[rustfmt::skip]
12814 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12815 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12816 #[rustfmt::skip]
12817 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12818 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12819 let r = _mm512_mask_min_epu16(a, 0, a, b);
12820 assert_eq_m512i(r, a);
12821 let r = _mm512_mask_min_epu16(a, 0b00000000_11111111_00000000_11111111, a, b);
12822 #[rustfmt::skip]
12823 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12824 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12825 assert_eq_m512i(r, e);
12826 }
12827
12828 #[simd_test(enable = "avx512f")]
12829 unsafe fn test_mm512_maskz_min_epu16() {
12830 #[rustfmt::skip]
12831 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12832 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12833 #[rustfmt::skip]
12834 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12835 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12836 let r = _mm512_maskz_min_epu16(0, a, b);
12837 assert_eq_m512i(r, _mm512_setzero_si512());
12838 let r = _mm512_maskz_min_epu16(0b00000000_11111111_00000000_11111111, a, b);
12839 #[rustfmt::skip]
12840 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
12841 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
12842 assert_eq_m512i(r, e);
12843 }
12844
12845 #[simd_test(enable = "avx512f,avx512vl")]
12846 unsafe fn test_mm256_mask_min_epu16() {
12847 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12848 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12849 let r = _mm256_mask_min_epu16(a, 0, a, b);
12850 assert_eq_m256i(r, a);
12851 let r = _mm256_mask_min_epu16(a, 0b00000000_11111111, a, b);
12852 let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12853 assert_eq_m256i(r, e);
12854 }
12855
12856 #[simd_test(enable = "avx512f,avx512vl")]
12857 unsafe fn test_mm256_maskz_min_epu16() {
12858 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12859 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12860 let r = _mm256_maskz_min_epu16(0, a, b);
12861 assert_eq_m256i(r, _mm256_setzero_si256());
12862 let r = _mm256_maskz_min_epu16(0b00000000_11111111, a, b);
12863 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
12864 assert_eq_m256i(r, e);
12865 }
12866
12867 #[simd_test(enable = "avx512f,avx512vl")]
12868 unsafe fn test_mm_mask_min_epu16() {
12869 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12870 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12871 let r = _mm_mask_min_epu16(a, 0, a, b);
12872 assert_eq_m128i(r, a);
12873 let r = _mm_mask_min_epu16(a, 0b00001111, a, b);
12874 let e = _mm_set_epi16(0, 1, 2, 3, 3, 2, 1, 0);
12875 assert_eq_m128i(r, e);
12876 }
12877
12878 #[simd_test(enable = "avx512f,avx512vl")]
12879 unsafe fn test_mm_maskz_min_epu16() {
12880 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
12881 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
12882 let r = _mm_maskz_min_epu16(0, a, b);
12883 assert_eq_m128i(r, _mm_setzero_si128());
12884 let r = _mm_maskz_min_epu16(0b00001111, a, b);
12885 let e = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
12886 assert_eq_m128i(r, e);
12887 }
12888
12889 #[simd_test(enable = "avx512bw")]
12890 unsafe fn test_mm512_min_epu8() {
12891 #[rustfmt::skip]
12892 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12893 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12894 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12895 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12896 #[rustfmt::skip]
12897 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12898 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12899 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12900 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12901 let r = _mm512_min_epu8(a, b);
12902 #[rustfmt::skip]
12903 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12904 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12905 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12906 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12907 assert_eq_m512i(r, e);
12908 }
12909
12910 #[simd_test(enable = "avx512f")]
12911 unsafe fn test_mm512_mask_min_epu8() {
12912 #[rustfmt::skip]
12913 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12914 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12915 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12916 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12917 #[rustfmt::skip]
12918 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12919 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12920 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12921 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12922 let r = _mm512_mask_min_epu8(a, 0, a, b);
12923 assert_eq_m512i(r, a);
12924 let r = _mm512_mask_min_epu8(
12925 a,
12926 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12927 a,
12928 b,
12929 );
12930 #[rustfmt::skip]
12931 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12932 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12933 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12934 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12935 assert_eq_m512i(r, e);
12936 }
12937
12938 #[simd_test(enable = "avx512f")]
12939 unsafe fn test_mm512_maskz_min_epu8() {
12940 #[rustfmt::skip]
12941 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12942 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12943 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12944 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12945 #[rustfmt::skip]
12946 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12947 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12948 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12949 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12950 let r = _mm512_maskz_min_epu8(0, a, b);
12951 assert_eq_m512i(r, _mm512_setzero_si512());
12952 let r = _mm512_maskz_min_epu8(
12953 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
12954 a,
12955 b,
12956 );
12957 #[rustfmt::skip]
12958 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
12959 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
12960 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
12961 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
12962 assert_eq_m512i(r, e);
12963 }
12964
12965 #[simd_test(enable = "avx512f,avx512vl")]
12966 unsafe fn test_mm256_mask_min_epu8() {
12967 #[rustfmt::skip]
12968 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12969 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12970 #[rustfmt::skip]
12971 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12972 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12973 let r = _mm256_mask_min_epu8(a, 0, a, b);
12974 assert_eq_m256i(r, a);
12975 let r = _mm256_mask_min_epu8(a, 0b00000000_11111111_00000000_11111111, a, b);
12976 #[rustfmt::skip]
12977 let e = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
12978 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
12979 assert_eq_m256i(r, e);
12980 }
12981
12982 #[simd_test(enable = "avx512f,avx512vl")]
12983 unsafe fn test_mm256_maskz_min_epu8() {
12984 #[rustfmt::skip]
12985 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
12986 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
12987 #[rustfmt::skip]
12988 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
12989 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
12990 let r = _mm256_maskz_min_epu8(0, a, b);
12991 assert_eq_m256i(r, _mm256_setzero_si256());
12992 let r = _mm256_maskz_min_epu8(0b00000000_11111111_00000000_11111111, a, b);
12993 #[rustfmt::skip]
12994 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
12995 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
12996 assert_eq_m256i(r, e);
12997 }
12998
12999 #[simd_test(enable = "avx512f,avx512vl")]
13000 unsafe fn test_mm_mask_min_epu8() {
13001 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13002 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13003 let r = _mm_mask_min_epu8(a, 0, a, b);
13004 assert_eq_m128i(r, a);
13005 let r = _mm_mask_min_epu8(a, 0b00000000_11111111, a, b);
13006 let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13007 assert_eq_m128i(r, e);
13008 }
13009
13010 #[simd_test(enable = "avx512f,avx512vl")]
13011 unsafe fn test_mm_maskz_min_epu8() {
13012 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13013 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13014 let r = _mm_maskz_min_epu8(0, a, b);
13015 assert_eq_m128i(r, _mm_setzero_si128());
13016 let r = _mm_maskz_min_epu8(0b00000000_11111111, a, b);
13017 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13018 assert_eq_m128i(r, e);
13019 }
13020
13021 #[simd_test(enable = "avx512bw")]
13022 unsafe fn test_mm512_min_epi16() {
13023 #[rustfmt::skip]
13024 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13025 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13026 #[rustfmt::skip]
13027 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13028 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13029 let r = _mm512_min_epi16(a, b);
13030 #[rustfmt::skip]
13031 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13032 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13033 assert_eq_m512i(r, e);
13034 }
13035
13036 #[simd_test(enable = "avx512f")]
13037 unsafe fn test_mm512_mask_min_epi16() {
13038 #[rustfmt::skip]
13039 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13040 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13041 #[rustfmt::skip]
13042 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13043 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13044 let r = _mm512_mask_min_epi16(a, 0, a, b);
13045 assert_eq_m512i(r, a);
13046 let r = _mm512_mask_min_epi16(a, 0b00000000_11111111_00000000_11111111, a, b);
13047 #[rustfmt::skip]
13048 let e = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13049 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13050 assert_eq_m512i(r, e);
13051 }
13052
13053 #[simd_test(enable = "avx512f")]
13054 unsafe fn test_mm512_maskz_min_epi16() {
13055 #[rustfmt::skip]
13056 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13057 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13058 #[rustfmt::skip]
13059 let b = _mm512_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13060 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13061 let r = _mm512_maskz_min_epi16(0, a, b);
13062 assert_eq_m512i(r, _mm512_setzero_si512());
13063 let r = _mm512_maskz_min_epi16(0b00000000_11111111_00000000_11111111, a, b);
13064 #[rustfmt::skip]
13065 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
13066 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13067 assert_eq_m512i(r, e);
13068 }
13069
13070 #[simd_test(enable = "avx512f,avx512vl")]
13071 unsafe fn test_mm256_mask_min_epi16() {
13072 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13073 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13074 let r = _mm256_mask_min_epi16(a, 0, a, b);
13075 assert_eq_m256i(r, a);
13076 let r = _mm256_mask_min_epi16(a, 0b00000000_11111111, a, b);
13077 let e = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13078 assert_eq_m256i(r, e);
13079 }
13080
13081 #[simd_test(enable = "avx512f,avx512vl")]
13082 unsafe fn test_mm256_maskz_min_epi16() {
13083 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13084 let b = _mm256_set_epi16(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13085 let r = _mm256_maskz_min_epi16(0, a, b);
13086 assert_eq_m256i(r, _mm256_setzero_si256());
13087 let r = _mm256_maskz_min_epi16(0b00000000_11111111, a, b);
13088 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13089 assert_eq_m256i(r, e);
13090 }
13091
13092 #[simd_test(enable = "avx512f,avx512vl")]
13093 unsafe fn test_mm_mask_min_epi16() {
13094 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
13095 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
13096 let r = _mm_mask_min_epi16(a, 0, a, b);
13097 assert_eq_m128i(r, a);
13098 let r = _mm_mask_min_epi16(a, 0b00001111, a, b);
13099 let e = _mm_set_epi16(0, 1, 2, 3, 3, 2, 1, 0);
13100 assert_eq_m128i(r, e);
13101 }
13102
13103 #[simd_test(enable = "avx512f,avx512vl")]
13104 unsafe fn test_mm_maskz_min_epi16() {
13105 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
13106 let b = _mm_set_epi16(7, 6, 5, 4, 3, 2, 1, 0);
13107 let r = _mm_maskz_min_epi16(0, a, b);
13108 assert_eq_m128i(r, _mm_setzero_si128());
13109 let r = _mm_maskz_min_epi16(0b00001111, a, b);
13110 let e = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
13111 assert_eq_m128i(r, e);
13112 }
13113
13114 #[simd_test(enable = "avx512bw")]
13115 unsafe fn test_mm512_min_epi8() {
13116 #[rustfmt::skip]
13117 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13118 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13119 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13120 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13121 #[rustfmt::skip]
13122 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13123 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13124 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13125 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13126 let r = _mm512_min_epi8(a, b);
13127 #[rustfmt::skip]
13128 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13129 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13130 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13131 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13132 assert_eq_m512i(r, e);
13133 }
13134
13135 #[simd_test(enable = "avx512f")]
13136 unsafe fn test_mm512_mask_min_epi8() {
13137 #[rustfmt::skip]
13138 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13139 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13140 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13141 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13142 #[rustfmt::skip]
13143 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13144 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13145 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13146 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13147 let r = _mm512_mask_min_epi8(a, 0, a, b);
13148 assert_eq_m512i(r, a);
13149 let r = _mm512_mask_min_epi8(
13150 a,
13151 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
13152 a,
13153 b,
13154 );
13155 #[rustfmt::skip]
13156 let e = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13157 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13158 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13159 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13160 assert_eq_m512i(r, e);
13161 }
13162
13163 #[simd_test(enable = "avx512f")]
13164 unsafe fn test_mm512_maskz_min_epi8() {
13165 #[rustfmt::skip]
13166 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13167 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13168 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13169 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13170 #[rustfmt::skip]
13171 let b = _mm512_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13172 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13173 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13174 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13175 let r = _mm512_maskz_min_epi8(0, a, b);
13176 assert_eq_m512i(r, _mm512_setzero_si512());
13177 let r = _mm512_maskz_min_epi8(
13178 0b00000000_11111111_00000000_11111111_00000000_11111111_00000000_11111111,
13179 a,
13180 b,
13181 );
13182 #[rustfmt::skip]
13183 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
13184 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
13185 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
13186 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13187 assert_eq_m512i(r, e);
13188 }
13189
13190 #[simd_test(enable = "avx512f,avx512vl")]
13191 unsafe fn test_mm256_mask_min_epi8() {
13192 #[rustfmt::skip]
13193 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13194 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13195 #[rustfmt::skip]
13196 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13197 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13198 let r = _mm256_mask_min_epi8(a, 0, a, b);
13199 assert_eq_m256i(r, a);
13200 let r = _mm256_mask_min_epi8(a, 0b00000000_11111111_00000000_11111111, a, b);
13201 #[rustfmt::skip]
13202 let e = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0,
13203 0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13204 assert_eq_m256i(r, e);
13205 }
13206
13207 #[simd_test(enable = "avx512f,avx512vl")]
13208 unsafe fn test_mm256_maskz_min_epi8() {
13209 #[rustfmt::skip]
13210 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
13211 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13212 #[rustfmt::skip]
13213 let b = _mm256_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0,
13214 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13215 let r = _mm256_maskz_min_epi8(0, a, b);
13216 assert_eq_m256i(r, _mm256_setzero_si256());
13217 let r = _mm256_maskz_min_epi8(0b00000000_11111111_00000000_11111111, a, b);
13218 #[rustfmt::skip]
13219 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0,
13220 0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13221 assert_eq_m256i(r, e);
13222 }
13223
13224 #[simd_test(enable = "avx512f,avx512vl")]
13225 unsafe fn test_mm_mask_min_epi8() {
13226 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13227 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13228 let r = _mm_mask_min_epi8(a, 0, a, b);
13229 assert_eq_m128i(r, a);
13230 let r = _mm_mask_min_epi8(a, 0b00000000_11111111, a, b);
13231 let e = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 7, 6, 5, 4, 3, 2, 1, 0);
13232 assert_eq_m128i(r, e);
13233 }
13234
13235 #[simd_test(enable = "avx512f,avx512vl")]
13236 unsafe fn test_mm_maskz_min_epi8() {
13237 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
13238 let b = _mm_set_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
13239 let r = _mm_maskz_min_epi8(0, a, b);
13240 assert_eq_m128i(r, _mm_setzero_si128());
13241 let r = _mm_maskz_min_epi8(0b00000000_11111111, a, b);
13242 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 7, 6, 5, 4, 3, 2, 1, 0);
13243 assert_eq_m128i(r, e);
13244 }
13245
13246 #[simd_test(enable = "avx512bw")]
13247 unsafe fn test_mm512_cmplt_epu16_mask() {
13248 let a = _mm512_set1_epi16(-2);
13249 let b = _mm512_set1_epi16(-1);
13250 let m = _mm512_cmplt_epu16_mask(a, b);
13251 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13252 }
13253
13254 #[simd_test(enable = "avx512bw")]
13255 unsafe fn test_mm512_mask_cmplt_epu16_mask() {
13256 let a = _mm512_set1_epi16(-2);
13257 let b = _mm512_set1_epi16(-1);
13258 let mask = 0b01010101_01010101_01010101_01010101;
13259 let r = _mm512_mask_cmplt_epu16_mask(mask, a, b);
13260 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13261 }
13262
13263 #[simd_test(enable = "avx512bw,avx512vl")]
13264 unsafe fn test_mm256_cmplt_epu16_mask() {
13265 let a = _mm256_set1_epi16(-2);
13266 let b = _mm256_set1_epi16(-1);
13267 let m = _mm256_cmplt_epu16_mask(a, b);
13268 assert_eq!(m, 0b11111111_11111111);
13269 }
13270
13271 #[simd_test(enable = "avx512bw,avx512vl")]
13272 unsafe fn test_mm256_mask_cmplt_epu16_mask() {
13273 let a = _mm256_set1_epi16(-2);
13274 let b = _mm256_set1_epi16(-1);
13275 let mask = 0b01010101_01010101;
13276 let r = _mm256_mask_cmplt_epu16_mask(mask, a, b);
13277 assert_eq!(r, 0b01010101_01010101);
13278 }
13279
13280 #[simd_test(enable = "avx512bw,avx512vl")]
13281 unsafe fn test_mm_cmplt_epu16_mask() {
13282 let a = _mm_set1_epi16(-2);
13283 let b = _mm_set1_epi16(-1);
13284 let m = _mm_cmplt_epu16_mask(a, b);
13285 assert_eq!(m, 0b11111111);
13286 }
13287
13288 #[simd_test(enable = "avx512bw,avx512vl")]
13289 unsafe fn test_mm_mask_cmplt_epu16_mask() {
13290 let a = _mm_set1_epi16(-2);
13291 let b = _mm_set1_epi16(-1);
13292 let mask = 0b01010101;
13293 let r = _mm_mask_cmplt_epu16_mask(mask, a, b);
13294 assert_eq!(r, 0b01010101);
13295 }
13296
13297 #[simd_test(enable = "avx512bw")]
13298 unsafe fn test_mm512_cmplt_epu8_mask() {
13299 let a = _mm512_set1_epi8(-2);
13300 let b = _mm512_set1_epi8(-1);
13301 let m = _mm512_cmplt_epu8_mask(a, b);
13302 assert_eq!(
13303 m,
13304 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13305 );
13306 }
13307
13308 #[simd_test(enable = "avx512bw")]
13309 unsafe fn test_mm512_mask_cmplt_epu8_mask() {
13310 let a = _mm512_set1_epi8(-2);
13311 let b = _mm512_set1_epi8(-1);
13312 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13313 let r = _mm512_mask_cmplt_epu8_mask(mask, a, b);
13314 assert_eq!(
13315 r,
13316 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13317 );
13318 }
13319
13320 #[simd_test(enable = "avx512bw,avx512vl")]
13321 unsafe fn test_mm256_cmplt_epu8_mask() {
13322 let a = _mm256_set1_epi8(-2);
13323 let b = _mm256_set1_epi8(-1);
13324 let m = _mm256_cmplt_epu8_mask(a, b);
13325 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13326 }
13327
13328 #[simd_test(enable = "avx512bw,avx512vl")]
13329 unsafe fn test_mm256_mask_cmplt_epu8_mask() {
13330 let a = _mm256_set1_epi8(-2);
13331 let b = _mm256_set1_epi8(-1);
13332 let mask = 0b01010101_01010101_01010101_01010101;
13333 let r = _mm256_mask_cmplt_epu8_mask(mask, a, b);
13334 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13335 }
13336
13337 #[simd_test(enable = "avx512bw,avx512vl")]
13338 unsafe fn test_mm_cmplt_epu8_mask() {
13339 let a = _mm_set1_epi8(-2);
13340 let b = _mm_set1_epi8(-1);
13341 let m = _mm_cmplt_epu8_mask(a, b);
13342 assert_eq!(m, 0b11111111_11111111);
13343 }
13344
13345 #[simd_test(enable = "avx512bw,avx512vl")]
13346 unsafe fn test_mm_mask_cmplt_epu8_mask() {
13347 let a = _mm_set1_epi8(-2);
13348 let b = _mm_set1_epi8(-1);
13349 let mask = 0b01010101_01010101;
13350 let r = _mm_mask_cmplt_epu8_mask(mask, a, b);
13351 assert_eq!(r, 0b01010101_01010101);
13352 }
13353
13354 #[simd_test(enable = "avx512bw")]
13355 unsafe fn test_mm512_cmplt_epi16_mask() {
13356 let a = _mm512_set1_epi16(-2);
13357 let b = _mm512_set1_epi16(-1);
13358 let m = _mm512_cmplt_epi16_mask(a, b);
13359 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13360 }
13361
13362 #[simd_test(enable = "avx512bw")]
13363 unsafe fn test_mm512_mask_cmplt_epi16_mask() {
13364 let a = _mm512_set1_epi16(-2);
13365 let b = _mm512_set1_epi16(-1);
13366 let mask = 0b01010101_01010101_01010101_01010101;
13367 let r = _mm512_mask_cmplt_epi16_mask(mask, a, b);
13368 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13369 }
13370
13371 #[simd_test(enable = "avx512bw,avx512vl")]
13372 unsafe fn test_mm256_cmplt_epi16_mask() {
13373 let a = _mm256_set1_epi16(-2);
13374 let b = _mm256_set1_epi16(-1);
13375 let m = _mm256_cmplt_epi16_mask(a, b);
13376 assert_eq!(m, 0b11111111_11111111);
13377 }
13378
13379 #[simd_test(enable = "avx512bw,avx512vl")]
13380 unsafe fn test_mm256_mask_cmplt_epi16_mask() {
13381 let a = _mm256_set1_epi16(-2);
13382 let b = _mm256_set1_epi16(-1);
13383 let mask = 0b01010101_01010101;
13384 let r = _mm256_mask_cmplt_epi16_mask(mask, a, b);
13385 assert_eq!(r, 0b01010101_01010101);
13386 }
13387
13388 #[simd_test(enable = "avx512bw,avx512vl")]
13389 unsafe fn test_mm_cmplt_epi16_mask() {
13390 let a = _mm_set1_epi16(-2);
13391 let b = _mm_set1_epi16(-1);
13392 let m = _mm_cmplt_epi16_mask(a, b);
13393 assert_eq!(m, 0b11111111);
13394 }
13395
13396 #[simd_test(enable = "avx512bw,avx512vl")]
13397 unsafe fn test_mm_mask_cmplt_epi16_mask() {
13398 let a = _mm_set1_epi16(-2);
13399 let b = _mm_set1_epi16(-1);
13400 let mask = 0b01010101;
13401 let r = _mm_mask_cmplt_epi16_mask(mask, a, b);
13402 assert_eq!(r, 0b01010101);
13403 }
13404
13405 #[simd_test(enable = "avx512bw")]
13406 unsafe fn test_mm512_cmplt_epi8_mask() {
13407 let a = _mm512_set1_epi8(-2);
13408 let b = _mm512_set1_epi8(-1);
13409 let m = _mm512_cmplt_epi8_mask(a, b);
13410 assert_eq!(
13411 m,
13412 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13413 );
13414 }
13415
13416 #[simd_test(enable = "avx512bw")]
13417 unsafe fn test_mm512_mask_cmplt_epi8_mask() {
13418 let a = _mm512_set1_epi8(-2);
13419 let b = _mm512_set1_epi8(-1);
13420 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13421 let r = _mm512_mask_cmplt_epi8_mask(mask, a, b);
13422 assert_eq!(
13423 r,
13424 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13425 );
13426 }
13427
13428 #[simd_test(enable = "avx512bw,avx512vl")]
13429 unsafe fn test_mm256_cmplt_epi8_mask() {
13430 let a = _mm256_set1_epi8(-2);
13431 let b = _mm256_set1_epi8(-1);
13432 let m = _mm256_cmplt_epi8_mask(a, b);
13433 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13434 }
13435
13436 #[simd_test(enable = "avx512bw,avx512vl")]
13437 unsafe fn test_mm256_mask_cmplt_epi8_mask() {
13438 let a = _mm256_set1_epi8(-2);
13439 let b = _mm256_set1_epi8(-1);
13440 let mask = 0b01010101_01010101_01010101_01010101;
13441 let r = _mm256_mask_cmplt_epi8_mask(mask, a, b);
13442 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13443 }
13444
13445 #[simd_test(enable = "avx512bw,avx512vl")]
13446 unsafe fn test_mm_cmplt_epi8_mask() {
13447 let a = _mm_set1_epi8(-2);
13448 let b = _mm_set1_epi8(-1);
13449 let m = _mm_cmplt_epi8_mask(a, b);
13450 assert_eq!(m, 0b11111111_11111111);
13451 }
13452
13453 #[simd_test(enable = "avx512bw,avx512vl")]
13454 unsafe fn test_mm_mask_cmplt_epi8_mask() {
13455 let a = _mm_set1_epi8(-2);
13456 let b = _mm_set1_epi8(-1);
13457 let mask = 0b01010101_01010101;
13458 let r = _mm_mask_cmplt_epi8_mask(mask, a, b);
13459 assert_eq!(r, 0b01010101_01010101);
13460 }
13461
13462 #[simd_test(enable = "avx512bw")]
13463 unsafe fn test_mm512_cmpgt_epu16_mask() {
13464 let a = _mm512_set1_epi16(2);
13465 let b = _mm512_set1_epi16(1);
13466 let m = _mm512_cmpgt_epu16_mask(a, b);
13467 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13468 }
13469
13470 #[simd_test(enable = "avx512bw")]
13471 unsafe fn test_mm512_mask_cmpgt_epu16_mask() {
13472 let a = _mm512_set1_epi16(2);
13473 let b = _mm512_set1_epi16(1);
13474 let mask = 0b01010101_01010101_01010101_01010101;
13475 let r = _mm512_mask_cmpgt_epu16_mask(mask, a, b);
13476 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13477 }
13478
13479 #[simd_test(enable = "avx512bw,avx512vl")]
13480 unsafe fn test_mm256_cmpgt_epu16_mask() {
13481 let a = _mm256_set1_epi16(2);
13482 let b = _mm256_set1_epi16(1);
13483 let m = _mm256_cmpgt_epu16_mask(a, b);
13484 assert_eq!(m, 0b11111111_11111111);
13485 }
13486
13487 #[simd_test(enable = "avx512bw,avx512vl")]
13488 unsafe fn test_mm256_mask_cmpgt_epu16_mask() {
13489 let a = _mm256_set1_epi16(2);
13490 let b = _mm256_set1_epi16(1);
13491 let mask = 0b01010101_01010101;
13492 let r = _mm256_mask_cmpgt_epu16_mask(mask, a, b);
13493 assert_eq!(r, 0b01010101_01010101);
13494 }
13495
13496 #[simd_test(enable = "avx512bw,avx512vl")]
13497 unsafe fn test_mm_cmpgt_epu16_mask() {
13498 let a = _mm_set1_epi16(2);
13499 let b = _mm_set1_epi16(1);
13500 let m = _mm_cmpgt_epu16_mask(a, b);
13501 assert_eq!(m, 0b11111111);
13502 }
13503
13504 #[simd_test(enable = "avx512bw,avx512vl")]
13505 unsafe fn test_mm_mask_cmpgt_epu16_mask() {
13506 let a = _mm_set1_epi16(2);
13507 let b = _mm_set1_epi16(1);
13508 let mask = 0b01010101;
13509 let r = _mm_mask_cmpgt_epu16_mask(mask, a, b);
13510 assert_eq!(r, 0b01010101);
13511 }
13512
13513 #[simd_test(enable = "avx512bw")]
13514 unsafe fn test_mm512_cmpgt_epu8_mask() {
13515 let a = _mm512_set1_epi8(2);
13516 let b = _mm512_set1_epi8(1);
13517 let m = _mm512_cmpgt_epu8_mask(a, b);
13518 assert_eq!(
13519 m,
13520 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13521 );
13522 }
13523
13524 #[simd_test(enable = "avx512bw")]
13525 unsafe fn test_mm512_mask_cmpgt_epu8_mask() {
13526 let a = _mm512_set1_epi8(2);
13527 let b = _mm512_set1_epi8(1);
13528 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13529 let r = _mm512_mask_cmpgt_epu8_mask(mask, a, b);
13530 assert_eq!(
13531 r,
13532 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13533 );
13534 }
13535
13536 #[simd_test(enable = "avx512bw,avx512vl")]
13537 unsafe fn test_mm256_cmpgt_epu8_mask() {
13538 let a = _mm256_set1_epi8(2);
13539 let b = _mm256_set1_epi8(1);
13540 let m = _mm256_cmpgt_epu8_mask(a, b);
13541 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13542 }
13543
13544 #[simd_test(enable = "avx512bw,avx512vl")]
13545 unsafe fn test_mm256_mask_cmpgt_epu8_mask() {
13546 let a = _mm256_set1_epi8(2);
13547 let b = _mm256_set1_epi8(1);
13548 let mask = 0b01010101_01010101_01010101_01010101;
13549 let r = _mm256_mask_cmpgt_epu8_mask(mask, a, b);
13550 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13551 }
13552
13553 #[simd_test(enable = "avx512bw,avx512vl")]
13554 unsafe fn test_mm_cmpgt_epu8_mask() {
13555 let a = _mm_set1_epi8(2);
13556 let b = _mm_set1_epi8(1);
13557 let m = _mm_cmpgt_epu8_mask(a, b);
13558 assert_eq!(m, 0b11111111_11111111);
13559 }
13560
13561 #[simd_test(enable = "avx512bw,avx512vl")]
13562 unsafe fn test_mm_mask_cmpgt_epu8_mask() {
13563 let a = _mm_set1_epi8(2);
13564 let b = _mm_set1_epi8(1);
13565 let mask = 0b01010101_01010101;
13566 let r = _mm_mask_cmpgt_epu8_mask(mask, a, b);
13567 assert_eq!(r, 0b01010101_01010101);
13568 }
13569
13570 #[simd_test(enable = "avx512bw")]
13571 unsafe fn test_mm512_cmpgt_epi16_mask() {
13572 let a = _mm512_set1_epi16(2);
13573 let b = _mm512_set1_epi16(-1);
13574 let m = _mm512_cmpgt_epi16_mask(a, b);
13575 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13576 }
13577
13578 #[simd_test(enable = "avx512bw")]
13579 unsafe fn test_mm512_mask_cmpgt_epi16_mask() {
13580 let a = _mm512_set1_epi16(2);
13581 let b = _mm512_set1_epi16(-1);
13582 let mask = 0b01010101_01010101_01010101_01010101;
13583 let r = _mm512_mask_cmpgt_epi16_mask(mask, a, b);
13584 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13585 }
13586
13587 #[simd_test(enable = "avx512bw,avx512vl")]
13588 unsafe fn test_mm256_cmpgt_epi16_mask() {
13589 let a = _mm256_set1_epi16(2);
13590 let b = _mm256_set1_epi16(-1);
13591 let m = _mm256_cmpgt_epi16_mask(a, b);
13592 assert_eq!(m, 0b11111111_11111111);
13593 }
13594
13595 #[simd_test(enable = "avx512bw,avx512vl")]
13596 unsafe fn test_mm256_mask_cmpgt_epi16_mask() {
13597 let a = _mm256_set1_epi16(2);
13598 let b = _mm256_set1_epi16(-1);
13599 let mask = 0b001010101_01010101;
13600 let r = _mm256_mask_cmpgt_epi16_mask(mask, a, b);
13601 assert_eq!(r, 0b01010101_01010101);
13602 }
13603
13604 #[simd_test(enable = "avx512bw,avx512vl")]
13605 unsafe fn test_mm_cmpgt_epi16_mask() {
13606 let a = _mm_set1_epi16(2);
13607 let b = _mm_set1_epi16(-1);
13608 let m = _mm_cmpgt_epi16_mask(a, b);
13609 assert_eq!(m, 0b11111111);
13610 }
13611
13612 #[simd_test(enable = "avx512bw,avx512vl")]
13613 unsafe fn test_mm_mask_cmpgt_epi16_mask() {
13614 let a = _mm_set1_epi16(2);
13615 let b = _mm_set1_epi16(-1);
13616 let mask = 0b01010101;
13617 let r = _mm_mask_cmpgt_epi16_mask(mask, a, b);
13618 assert_eq!(r, 0b01010101);
13619 }
13620
13621 #[simd_test(enable = "avx512bw")]
13622 unsafe fn test_mm512_cmpgt_epi8_mask() {
13623 let a = _mm512_set1_epi8(2);
13624 let b = _mm512_set1_epi8(-1);
13625 let m = _mm512_cmpgt_epi8_mask(a, b);
13626 assert_eq!(
13627 m,
13628 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13629 );
13630 }
13631
13632 #[simd_test(enable = "avx512bw")]
13633 unsafe fn test_mm512_mask_cmpgt_epi8_mask() {
13634 let a = _mm512_set1_epi8(2);
13635 let b = _mm512_set1_epi8(-1);
13636 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13637 let r = _mm512_mask_cmpgt_epi8_mask(mask, a, b);
13638 assert_eq!(
13639 r,
13640 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13641 );
13642 }
13643
13644 #[simd_test(enable = "avx512bw,avx512vl")]
13645 unsafe fn test_mm256_cmpgt_epi8_mask() {
13646 let a = _mm256_set1_epi8(2);
13647 let b = _mm256_set1_epi8(-1);
13648 let m = _mm256_cmpgt_epi8_mask(a, b);
13649 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13650 }
13651
13652 #[simd_test(enable = "avx512bw,avx512vl")]
13653 unsafe fn test_mm256_mask_cmpgt_epi8_mask() {
13654 let a = _mm256_set1_epi8(2);
13655 let b = _mm256_set1_epi8(-1);
13656 let mask = 0b01010101_01010101_01010101_01010101;
13657 let r = _mm256_mask_cmpgt_epi8_mask(mask, a, b);
13658 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13659 }
13660
13661 #[simd_test(enable = "avx512bw,avx512vl")]
13662 unsafe fn test_mm_cmpgt_epi8_mask() {
13663 let a = _mm_set1_epi8(2);
13664 let b = _mm_set1_epi8(-1);
13665 let m = _mm_cmpgt_epi8_mask(a, b);
13666 assert_eq!(m, 0b11111111_11111111);
13667 }
13668
13669 #[simd_test(enable = "avx512bw,avx512vl")]
13670 unsafe fn test_mm_mask_cmpgt_epi8_mask() {
13671 let a = _mm_set1_epi8(2);
13672 let b = _mm_set1_epi8(-1);
13673 let mask = 0b01010101_01010101;
13674 let r = _mm_mask_cmpgt_epi8_mask(mask, a, b);
13675 assert_eq!(r, 0b01010101_01010101);
13676 }
13677
13678 #[simd_test(enable = "avx512bw")]
13679 unsafe fn test_mm512_cmple_epu16_mask() {
13680 let a = _mm512_set1_epi16(-1);
13681 let b = _mm512_set1_epi16(-1);
13682 let m = _mm512_cmple_epu16_mask(a, b);
13683 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13684 }
13685
13686 #[simd_test(enable = "avx512bw")]
13687 unsafe fn test_mm512_mask_cmple_epu16_mask() {
13688 let a = _mm512_set1_epi16(-1);
13689 let b = _mm512_set1_epi16(-1);
13690 let mask = 0b01010101_01010101_01010101_01010101;
13691 let r = _mm512_mask_cmple_epu16_mask(mask, a, b);
13692 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13693 }
13694
13695 #[simd_test(enable = "avx512bw,avx512vl")]
13696 unsafe fn test_mm256_cmple_epu16_mask() {
13697 let a = _mm256_set1_epi16(-1);
13698 let b = _mm256_set1_epi16(-1);
13699 let m = _mm256_cmple_epu16_mask(a, b);
13700 assert_eq!(m, 0b11111111_11111111);
13701 }
13702
13703 #[simd_test(enable = "avx512bw,avx512vl")]
13704 unsafe fn test_mm256_mask_cmple_epu16_mask() {
13705 let a = _mm256_set1_epi16(-1);
13706 let b = _mm256_set1_epi16(-1);
13707 let mask = 0b01010101_01010101;
13708 let r = _mm256_mask_cmple_epu16_mask(mask, a, b);
13709 assert_eq!(r, 0b01010101_01010101);
13710 }
13711
13712 #[simd_test(enable = "avx512bw,avx512vl")]
13713 unsafe fn test_mm_cmple_epu16_mask() {
13714 let a = _mm_set1_epi16(-1);
13715 let b = _mm_set1_epi16(-1);
13716 let m = _mm_cmple_epu16_mask(a, b);
13717 assert_eq!(m, 0b11111111);
13718 }
13719
13720 #[simd_test(enable = "avx512bw,avx512vl")]
13721 unsafe fn test_mm_mask_cmple_epu16_mask() {
13722 let a = _mm_set1_epi16(-1);
13723 let b = _mm_set1_epi16(-1);
13724 let mask = 0b01010101;
13725 let r = _mm_mask_cmple_epu16_mask(mask, a, b);
13726 assert_eq!(r, 0b01010101);
13727 }
13728
13729 #[simd_test(enable = "avx512bw")]
13730 unsafe fn test_mm512_cmple_epu8_mask() {
13731 let a = _mm512_set1_epi8(-1);
13732 let b = _mm512_set1_epi8(-1);
13733 let m = _mm512_cmple_epu8_mask(a, b);
13734 assert_eq!(
13735 m,
13736 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13737 );
13738 }
13739
13740 #[simd_test(enable = "avx512bw")]
13741 unsafe fn test_mm512_mask_cmple_epu8_mask() {
13742 let a = _mm512_set1_epi8(-1);
13743 let b = _mm512_set1_epi8(-1);
13744 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13745 let r = _mm512_mask_cmple_epu8_mask(mask, a, b);
13746 assert_eq!(
13747 r,
13748 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13749 );
13750 }
13751
13752 #[simd_test(enable = "avx512bw,avx512vl")]
13753 unsafe fn test_mm256_cmple_epu8_mask() {
13754 let a = _mm256_set1_epi8(-1);
13755 let b = _mm256_set1_epi8(-1);
13756 let m = _mm256_cmple_epu8_mask(a, b);
13757 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13758 }
13759
13760 #[simd_test(enable = "avx512bw,avx512vl")]
13761 unsafe fn test_mm256_mask_cmple_epu8_mask() {
13762 let a = _mm256_set1_epi8(-1);
13763 let b = _mm256_set1_epi8(-1);
13764 let mask = 0b01010101_01010101_01010101_01010101;
13765 let r = _mm256_mask_cmple_epu8_mask(mask, a, b);
13766 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13767 }
13768
13769 #[simd_test(enable = "avx512bw,avx512vl")]
13770 unsafe fn test_mm_cmple_epu8_mask() {
13771 let a = _mm_set1_epi8(-1);
13772 let b = _mm_set1_epi8(-1);
13773 let m = _mm_cmple_epu8_mask(a, b);
13774 assert_eq!(m, 0b11111111_11111111);
13775 }
13776
13777 #[simd_test(enable = "avx512bw,avx512vl")]
13778 unsafe fn test_mm_mask_cmple_epu8_mask() {
13779 let a = _mm_set1_epi8(-1);
13780 let b = _mm_set1_epi8(-1);
13781 let mask = 0b01010101_01010101;
13782 let r = _mm_mask_cmple_epu8_mask(mask, a, b);
13783 assert_eq!(r, 0b01010101_01010101);
13784 }
13785
13786 #[simd_test(enable = "avx512bw")]
13787 unsafe fn test_mm512_cmple_epi16_mask() {
13788 let a = _mm512_set1_epi16(-1);
13789 let b = _mm512_set1_epi16(-1);
13790 let m = _mm512_cmple_epi16_mask(a, b);
13791 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13792 }
13793
13794 #[simd_test(enable = "avx512bw")]
13795 unsafe fn test_mm512_mask_cmple_epi16_mask() {
13796 let a = _mm512_set1_epi16(-1);
13797 let b = _mm512_set1_epi16(-1);
13798 let mask = 0b01010101_01010101_01010101_01010101;
13799 let r = _mm512_mask_cmple_epi16_mask(mask, a, b);
13800 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13801 }
13802
13803 #[simd_test(enable = "avx512bw,avx512vl")]
13804 unsafe fn test_mm256_cmple_epi16_mask() {
13805 let a = _mm256_set1_epi16(-1);
13806 let b = _mm256_set1_epi16(-1);
13807 let m = _mm256_cmple_epi16_mask(a, b);
13808 assert_eq!(m, 0b11111111_11111111);
13809 }
13810
13811 #[simd_test(enable = "avx512bw,avx512vl")]
13812 unsafe fn test_mm256_mask_cmple_epi16_mask() {
13813 let a = _mm256_set1_epi16(-1);
13814 let b = _mm256_set1_epi16(-1);
13815 let mask = 0b01010101_01010101;
13816 let r = _mm256_mask_cmple_epi16_mask(mask, a, b);
13817 assert_eq!(r, 0b01010101_01010101);
13818 }
13819
13820 #[simd_test(enable = "avx512bw,avx512vl")]
13821 unsafe fn test_mm_cmple_epi16_mask() {
13822 let a = _mm_set1_epi16(-1);
13823 let b = _mm_set1_epi16(-1);
13824 let m = _mm_cmple_epi16_mask(a, b);
13825 assert_eq!(m, 0b11111111);
13826 }
13827
13828 #[simd_test(enable = "avx512bw,avx512vl")]
13829 unsafe fn test_mm_mask_cmple_epi16_mask() {
13830 let a = _mm_set1_epi16(-1);
13831 let b = _mm_set1_epi16(-1);
13832 let mask = 0b01010101;
13833 let r = _mm_mask_cmple_epi16_mask(mask, a, b);
13834 assert_eq!(r, 0b01010101);
13835 }
13836
13837 #[simd_test(enable = "avx512bw")]
13838 unsafe fn test_mm512_cmple_epi8_mask() {
13839 let a = _mm512_set1_epi8(-1);
13840 let b = _mm512_set1_epi8(-1);
13841 let m = _mm512_cmple_epi8_mask(a, b);
13842 assert_eq!(
13843 m,
13844 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13845 );
13846 }
13847
13848 #[simd_test(enable = "avx512bw")]
13849 unsafe fn test_mm512_mask_cmple_epi8_mask() {
13850 let a = _mm512_set1_epi8(-1);
13851 let b = _mm512_set1_epi8(-1);
13852 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13853 let r = _mm512_mask_cmple_epi8_mask(mask, a, b);
13854 assert_eq!(
13855 r,
13856 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13857 );
13858 }
13859
13860 #[simd_test(enable = "avx512bw,avx512vl")]
13861 unsafe fn test_mm256_cmple_epi8_mask() {
13862 let a = _mm256_set1_epi8(-1);
13863 let b = _mm256_set1_epi8(-1);
13864 let m = _mm256_cmple_epi8_mask(a, b);
13865 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13866 }
13867
13868 #[simd_test(enable = "avx512bw,avx512vl")]
13869 unsafe fn test_mm256_mask_cmple_epi8_mask() {
13870 let a = _mm256_set1_epi8(-1);
13871 let b = _mm256_set1_epi8(-1);
13872 let mask = 0b01010101_01010101_01010101_01010101;
13873 let r = _mm256_mask_cmple_epi8_mask(mask, a, b);
13874 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13875 }
13876
13877 #[simd_test(enable = "avx512bw,avx512vl")]
13878 unsafe fn test_mm_cmple_epi8_mask() {
13879 let a = _mm_set1_epi8(-1);
13880 let b = _mm_set1_epi8(-1);
13881 let m = _mm_cmple_epi8_mask(a, b);
13882 assert_eq!(m, 0b11111111_11111111);
13883 }
13884
13885 #[simd_test(enable = "avx512bw,avx512vl")]
13886 unsafe fn test_mm_mask_cmple_epi8_mask() {
13887 let a = _mm_set1_epi8(-1);
13888 let b = _mm_set1_epi8(-1);
13889 let mask = 0b01010101_01010101;
13890 let r = _mm_mask_cmple_epi8_mask(mask, a, b);
13891 assert_eq!(r, 0b01010101_01010101);
13892 }
13893
13894 #[simd_test(enable = "avx512bw")]
13895 unsafe fn test_mm512_cmpge_epu16_mask() {
13896 let a = _mm512_set1_epi16(1);
13897 let b = _mm512_set1_epi16(1);
13898 let m = _mm512_cmpge_epu16_mask(a, b);
13899 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13900 }
13901
13902 #[simd_test(enable = "avx512bw")]
13903 unsafe fn test_mm512_mask_cmpge_epu16_mask() {
13904 let a = _mm512_set1_epi16(1);
13905 let b = _mm512_set1_epi16(1);
13906 let mask = 0b01010101_01010101_01010101_01010101;
13907 let r = _mm512_mask_cmpge_epu16_mask(mask, a, b);
13908 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13909 }
13910
13911 #[simd_test(enable = "avx512bw,avx512vl")]
13912 unsafe fn test_mm256_cmpge_epu16_mask() {
13913 let a = _mm256_set1_epi16(1);
13914 let b = _mm256_set1_epi16(1);
13915 let m = _mm256_cmpge_epu16_mask(a, b);
13916 assert_eq!(m, 0b11111111_11111111);
13917 }
13918
13919 #[simd_test(enable = "avx512bw,avx512vl")]
13920 unsafe fn test_mm256_mask_cmpge_epu16_mask() {
13921 let a = _mm256_set1_epi16(1);
13922 let b = _mm256_set1_epi16(1);
13923 let mask = 0b01010101_01010101;
13924 let r = _mm256_mask_cmpge_epu16_mask(mask, a, b);
13925 assert_eq!(r, 0b01010101_01010101);
13926 }
13927
13928 #[simd_test(enable = "avx512bw,avx512vl")]
13929 unsafe fn test_mm_cmpge_epu16_mask() {
13930 let a = _mm_set1_epi16(1);
13931 let b = _mm_set1_epi16(1);
13932 let m = _mm_cmpge_epu16_mask(a, b);
13933 assert_eq!(m, 0b11111111);
13934 }
13935
13936 #[simd_test(enable = "avx512bw,avx512vl")]
13937 unsafe fn test_mm_mask_cmpge_epu16_mask() {
13938 let a = _mm_set1_epi16(1);
13939 let b = _mm_set1_epi16(1);
13940 let mask = 0b01010101;
13941 let r = _mm_mask_cmpge_epu16_mask(mask, a, b);
13942 assert_eq!(r, 0b01010101);
13943 }
13944
13945 #[simd_test(enable = "avx512bw")]
13946 unsafe fn test_mm512_cmpge_epu8_mask() {
13947 let a = _mm512_set1_epi8(1);
13948 let b = _mm512_set1_epi8(1);
13949 let m = _mm512_cmpge_epu8_mask(a, b);
13950 assert_eq!(
13951 m,
13952 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
13953 );
13954 }
13955
13956 #[simd_test(enable = "avx512bw")]
13957 unsafe fn test_mm512_mask_cmpge_epu8_mask() {
13958 let a = _mm512_set1_epi8(1);
13959 let b = _mm512_set1_epi8(1);
13960 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
13961 let r = _mm512_mask_cmpge_epu8_mask(mask, a, b);
13962 assert_eq!(
13963 r,
13964 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
13965 );
13966 }
13967
13968 #[simd_test(enable = "avx512bw,avx512vl")]
13969 unsafe fn test_mm256_cmpge_epu8_mask() {
13970 let a = _mm256_set1_epi8(1);
13971 let b = _mm256_set1_epi8(1);
13972 let m = _mm256_cmpge_epu8_mask(a, b);
13973 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
13974 }
13975
13976 #[simd_test(enable = "avx512bw,avx512vl")]
13977 unsafe fn test_mm256_mask_cmpge_epu8_mask() {
13978 let a = _mm256_set1_epi8(1);
13979 let b = _mm256_set1_epi8(1);
13980 let mask = 0b01010101_01010101_01010101_01010101;
13981 let r = _mm256_mask_cmpge_epu8_mask(mask, a, b);
13982 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
13983 }
13984
13985 #[simd_test(enable = "avx512bw,avx512vl")]
13986 unsafe fn test_mm_cmpge_epu8_mask() {
13987 let a = _mm_set1_epi8(1);
13988 let b = _mm_set1_epi8(1);
13989 let m = _mm_cmpge_epu8_mask(a, b);
13990 assert_eq!(m, 0b11111111_11111111);
13991 }
13992
13993 #[simd_test(enable = "avx512bw,avx512vl")]
13994 unsafe fn test_mm_mask_cmpge_epu8_mask() {
13995 let a = _mm_set1_epi8(1);
13996 let b = _mm_set1_epi8(1);
13997 let mask = 0b01010101_01010101;
13998 let r = _mm_mask_cmpge_epu8_mask(mask, a, b);
13999 assert_eq!(r, 0b01010101_01010101);
14000 }
14001
14002 #[simd_test(enable = "avx512bw")]
14003 unsafe fn test_mm512_cmpge_epi16_mask() {
14004 let a = _mm512_set1_epi16(-1);
14005 let b = _mm512_set1_epi16(-1);
14006 let m = _mm512_cmpge_epi16_mask(a, b);
14007 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14008 }
14009
14010 #[simd_test(enable = "avx512bw")]
14011 unsafe fn test_mm512_mask_cmpge_epi16_mask() {
14012 let a = _mm512_set1_epi16(-1);
14013 let b = _mm512_set1_epi16(-1);
14014 let mask = 0b01010101_01010101_01010101_01010101;
14015 let r = _mm512_mask_cmpge_epi16_mask(mask, a, b);
14016 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14017 }
14018
14019 #[simd_test(enable = "avx512bw,avx512vl")]
14020 unsafe fn test_mm256_cmpge_epi16_mask() {
14021 let a = _mm256_set1_epi16(-1);
14022 let b = _mm256_set1_epi16(-1);
14023 let m = _mm256_cmpge_epi16_mask(a, b);
14024 assert_eq!(m, 0b11111111_11111111);
14025 }
14026
14027 #[simd_test(enable = "avx512bw,avx512vl")]
14028 unsafe fn test_mm256_mask_cmpge_epi16_mask() {
14029 let a = _mm256_set1_epi16(-1);
14030 let b = _mm256_set1_epi16(-1);
14031 let mask = 0b01010101_01010101;
14032 let r = _mm256_mask_cmpge_epi16_mask(mask, a, b);
14033 assert_eq!(r, 0b01010101_01010101);
14034 }
14035
14036 #[simd_test(enable = "avx512bw,avx512vl")]
14037 unsafe fn test_mm_cmpge_epi16_mask() {
14038 let a = _mm_set1_epi16(-1);
14039 let b = _mm_set1_epi16(-1);
14040 let m = _mm_cmpge_epi16_mask(a, b);
14041 assert_eq!(m, 0b11111111);
14042 }
14043
14044 #[simd_test(enable = "avx512bw,avx512vl")]
14045 unsafe fn test_mm_mask_cmpge_epi16_mask() {
14046 let a = _mm_set1_epi16(-1);
14047 let b = _mm_set1_epi16(-1);
14048 let mask = 0b01010101;
14049 let r = _mm_mask_cmpge_epi16_mask(mask, a, b);
14050 assert_eq!(r, 0b01010101);
14051 }
14052
14053 #[simd_test(enable = "avx512bw")]
14054 unsafe fn test_mm512_cmpge_epi8_mask() {
14055 let a = _mm512_set1_epi8(-1);
14056 let b = _mm512_set1_epi8(-1);
14057 let m = _mm512_cmpge_epi8_mask(a, b);
14058 assert_eq!(
14059 m,
14060 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14061 );
14062 }
14063
14064 #[simd_test(enable = "avx512bw")]
14065 unsafe fn test_mm512_mask_cmpge_epi8_mask() {
14066 let a = _mm512_set1_epi8(-1);
14067 let b = _mm512_set1_epi8(-1);
14068 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14069 let r = _mm512_mask_cmpge_epi8_mask(mask, a, b);
14070 assert_eq!(
14071 r,
14072 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14073 );
14074 }
14075
14076 #[simd_test(enable = "avx512bw,avx512vl")]
14077 unsafe fn test_mm256_cmpge_epi8_mask() {
14078 let a = _mm256_set1_epi8(-1);
14079 let b = _mm256_set1_epi8(-1);
14080 let m = _mm256_cmpge_epi8_mask(a, b);
14081 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14082 }
14083
14084 #[simd_test(enable = "avx512bw,avx512vl")]
14085 unsafe fn test_mm256_mask_cmpge_epi8_mask() {
14086 let a = _mm256_set1_epi8(-1);
14087 let b = _mm256_set1_epi8(-1);
14088 let mask = 0b01010101_01010101_01010101_01010101;
14089 let r = _mm256_mask_cmpge_epi8_mask(mask, a, b);
14090 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14091 }
14092
14093 #[simd_test(enable = "avx512bw,avx512vl")]
14094 unsafe fn test_mm_cmpge_epi8_mask() {
14095 let a = _mm_set1_epi8(-1);
14096 let b = _mm_set1_epi8(-1);
14097 let m = _mm_cmpge_epi8_mask(a, b);
14098 assert_eq!(m, 0b11111111_11111111);
14099 }
14100
14101 #[simd_test(enable = "avx512bw,avx512vl")]
14102 unsafe fn test_mm_mask_cmpge_epi8_mask() {
14103 let a = _mm_set1_epi8(-1);
14104 let b = _mm_set1_epi8(-1);
14105 let mask = 0b01010101_01010101;
14106 let r = _mm_mask_cmpge_epi8_mask(mask, a, b);
14107 assert_eq!(r, 0b01010101_01010101);
14108 }
14109
14110 #[simd_test(enable = "avx512bw")]
14111 unsafe fn test_mm512_cmpeq_epu16_mask() {
14112 let a = _mm512_set1_epi16(1);
14113 let b = _mm512_set1_epi16(1);
14114 let m = _mm512_cmpeq_epu16_mask(a, b);
14115 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14116 }
14117
14118 #[simd_test(enable = "avx512bw")]
14119 unsafe fn test_mm512_mask_cmpeq_epu16_mask() {
14120 let a = _mm512_set1_epi16(1);
14121 let b = _mm512_set1_epi16(1);
14122 let mask = 0b01010101_01010101_01010101_01010101;
14123 let r = _mm512_mask_cmpeq_epu16_mask(mask, a, b);
14124 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14125 }
14126
14127 #[simd_test(enable = "avx512bw,avx512vl")]
14128 unsafe fn test_mm256_cmpeq_epu16_mask() {
14129 let a = _mm256_set1_epi16(1);
14130 let b = _mm256_set1_epi16(1);
14131 let m = _mm256_cmpeq_epu16_mask(a, b);
14132 assert_eq!(m, 0b11111111_11111111);
14133 }
14134
14135 #[simd_test(enable = "avx512bw,avx512vl")]
14136 unsafe fn test_mm256_mask_cmpeq_epu16_mask() {
14137 let a = _mm256_set1_epi16(1);
14138 let b = _mm256_set1_epi16(1);
14139 let mask = 0b01010101_01010101;
14140 let r = _mm256_mask_cmpeq_epu16_mask(mask, a, b);
14141 assert_eq!(r, 0b01010101_01010101);
14142 }
14143
14144 #[simd_test(enable = "avx512bw,avx512vl")]
14145 unsafe fn test_mm_cmpeq_epu16_mask() {
14146 let a = _mm_set1_epi16(1);
14147 let b = _mm_set1_epi16(1);
14148 let m = _mm_cmpeq_epu16_mask(a, b);
14149 assert_eq!(m, 0b11111111);
14150 }
14151
14152 #[simd_test(enable = "avx512bw,avx512vl")]
14153 unsafe fn test_mm_mask_cmpeq_epu16_mask() {
14154 let a = _mm_set1_epi16(1);
14155 let b = _mm_set1_epi16(1);
14156 let mask = 0b01010101;
14157 let r = _mm_mask_cmpeq_epu16_mask(mask, a, b);
14158 assert_eq!(r, 0b01010101);
14159 }
14160
14161 #[simd_test(enable = "avx512bw")]
14162 unsafe fn test_mm512_cmpeq_epu8_mask() {
14163 let a = _mm512_set1_epi8(1);
14164 let b = _mm512_set1_epi8(1);
14165 let m = _mm512_cmpeq_epu8_mask(a, b);
14166 assert_eq!(
14167 m,
14168 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14169 );
14170 }
14171
14172 #[simd_test(enable = "avx512bw")]
14173 unsafe fn test_mm512_mask_cmpeq_epu8_mask() {
14174 let a = _mm512_set1_epi8(1);
14175 let b = _mm512_set1_epi8(1);
14176 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14177 let r = _mm512_mask_cmpeq_epu8_mask(mask, a, b);
14178 assert_eq!(
14179 r,
14180 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14181 );
14182 }
14183
14184 #[simd_test(enable = "avx512bw,avx512vl")]
14185 unsafe fn test_mm256_cmpeq_epu8_mask() {
14186 let a = _mm256_set1_epi8(1);
14187 let b = _mm256_set1_epi8(1);
14188 let m = _mm256_cmpeq_epu8_mask(a, b);
14189 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14190 }
14191
14192 #[simd_test(enable = "avx512bw,avx512vl")]
14193 unsafe fn test_mm256_mask_cmpeq_epu8_mask() {
14194 let a = _mm256_set1_epi8(1);
14195 let b = _mm256_set1_epi8(1);
14196 let mask = 0b01010101_01010101_01010101_01010101;
14197 let r = _mm256_mask_cmpeq_epu8_mask(mask, a, b);
14198 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14199 }
14200
14201 #[simd_test(enable = "avx512bw,avx512vl")]
14202 unsafe fn test_mm_cmpeq_epu8_mask() {
14203 let a = _mm_set1_epi8(1);
14204 let b = _mm_set1_epi8(1);
14205 let m = _mm_cmpeq_epu8_mask(a, b);
14206 assert_eq!(m, 0b11111111_11111111);
14207 }
14208
14209 #[simd_test(enable = "avx512bw,avx512vl")]
14210 unsafe fn test_mm_mask_cmpeq_epu8_mask() {
14211 let a = _mm_set1_epi8(1);
14212 let b = _mm_set1_epi8(1);
14213 let mask = 0b01010101_01010101;
14214 let r = _mm_mask_cmpeq_epu8_mask(mask, a, b);
14215 assert_eq!(r, 0b01010101_01010101);
14216 }
14217
14218 #[simd_test(enable = "avx512bw")]
14219 unsafe fn test_mm512_cmpeq_epi16_mask() {
14220 let a = _mm512_set1_epi16(-1);
14221 let b = _mm512_set1_epi16(-1);
14222 let m = _mm512_cmpeq_epi16_mask(a, b);
14223 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14224 }
14225
14226 #[simd_test(enable = "avx512bw")]
14227 unsafe fn test_mm512_mask_cmpeq_epi16_mask() {
14228 let a = _mm512_set1_epi16(-1);
14229 let b = _mm512_set1_epi16(-1);
14230 let mask = 0b01010101_01010101_01010101_01010101;
14231 let r = _mm512_mask_cmpeq_epi16_mask(mask, a, b);
14232 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14233 }
14234
14235 #[simd_test(enable = "avx512bw,avx512vl")]
14236 unsafe fn test_mm256_cmpeq_epi16_mask() {
14237 let a = _mm256_set1_epi16(-1);
14238 let b = _mm256_set1_epi16(-1);
14239 let m = _mm256_cmpeq_epi16_mask(a, b);
14240 assert_eq!(m, 0b11111111_11111111);
14241 }
14242
14243 #[simd_test(enable = "avx512bw,avx512vl")]
14244 unsafe fn test_mm256_mask_cmpeq_epi16_mask() {
14245 let a = _mm256_set1_epi16(-1);
14246 let b = _mm256_set1_epi16(-1);
14247 let mask = 0b01010101_01010101;
14248 let r = _mm256_mask_cmpeq_epi16_mask(mask, a, b);
14249 assert_eq!(r, 0b01010101_01010101);
14250 }
14251
14252 #[simd_test(enable = "avx512bw,avx512vl")]
14253 unsafe fn test_mm_cmpeq_epi16_mask() {
14254 let a = _mm_set1_epi16(-1);
14255 let b = _mm_set1_epi16(-1);
14256 let m = _mm_cmpeq_epi16_mask(a, b);
14257 assert_eq!(m, 0b11111111);
14258 }
14259
14260 #[simd_test(enable = "avx512bw,avx512vl")]
14261 unsafe fn test_mm_mask_cmpeq_epi16_mask() {
14262 let a = _mm_set1_epi16(-1);
14263 let b = _mm_set1_epi16(-1);
14264 let mask = 0b01010101;
14265 let r = _mm_mask_cmpeq_epi16_mask(mask, a, b);
14266 assert_eq!(r, 0b01010101);
14267 }
14268
14269 #[simd_test(enable = "avx512bw")]
14270 unsafe fn test_mm512_cmpeq_epi8_mask() {
14271 let a = _mm512_set1_epi8(-1);
14272 let b = _mm512_set1_epi8(-1);
14273 let m = _mm512_cmpeq_epi8_mask(a, b);
14274 assert_eq!(
14275 m,
14276 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14277 );
14278 }
14279
14280 #[simd_test(enable = "avx512bw")]
14281 unsafe fn test_mm512_mask_cmpeq_epi8_mask() {
14282 let a = _mm512_set1_epi8(-1);
14283 let b = _mm512_set1_epi8(-1);
14284 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14285 let r = _mm512_mask_cmpeq_epi8_mask(mask, a, b);
14286 assert_eq!(
14287 r,
14288 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14289 );
14290 }
14291
14292 #[simd_test(enable = "avx512bw,avx512vl")]
14293 unsafe fn test_mm256_cmpeq_epi8_mask() {
14294 let a = _mm256_set1_epi8(-1);
14295 let b = _mm256_set1_epi8(-1);
14296 let m = _mm256_cmpeq_epi8_mask(a, b);
14297 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14298 }
14299
14300 #[simd_test(enable = "avx512bw,avx512vl")]
14301 unsafe fn test_mm256_mask_cmpeq_epi8_mask() {
14302 let a = _mm256_set1_epi8(-1);
14303 let b = _mm256_set1_epi8(-1);
14304 let mask = 0b01010101_01010101_01010101_01010101;
14305 let r = _mm256_mask_cmpeq_epi8_mask(mask, a, b);
14306 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14307 }
14308
14309 #[simd_test(enable = "avx512bw,avx512vl")]
14310 unsafe fn test_mm_cmpeq_epi8_mask() {
14311 let a = _mm_set1_epi8(-1);
14312 let b = _mm_set1_epi8(-1);
14313 let m = _mm_cmpeq_epi8_mask(a, b);
14314 assert_eq!(m, 0b11111111_11111111);
14315 }
14316
14317 #[simd_test(enable = "avx512bw,avx512vl")]
14318 unsafe fn test_mm_mask_cmpeq_epi8_mask() {
14319 let a = _mm_set1_epi8(-1);
14320 let b = _mm_set1_epi8(-1);
14321 let mask = 0b01010101_01010101;
14322 let r = _mm_mask_cmpeq_epi8_mask(mask, a, b);
14323 assert_eq!(r, 0b01010101_01010101);
14324 }
14325
14326 #[simd_test(enable = "avx512bw")]
14327 unsafe fn test_mm512_cmpneq_epu16_mask() {
14328 let a = _mm512_set1_epi16(2);
14329 let b = _mm512_set1_epi16(1);
14330 let m = _mm512_cmpneq_epu16_mask(a, b);
14331 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14332 }
14333
14334 #[simd_test(enable = "avx512bw")]
14335 unsafe fn test_mm512_mask_cmpneq_epu16_mask() {
14336 let a = _mm512_set1_epi16(2);
14337 let b = _mm512_set1_epi16(1);
14338 let mask = 0b01010101_01010101_01010101_01010101;
14339 let r = _mm512_mask_cmpneq_epu16_mask(mask, a, b);
14340 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14341 }
14342
14343 #[simd_test(enable = "avx512bw,avx512vl")]
14344 unsafe fn test_mm256_cmpneq_epu16_mask() {
14345 let a = _mm256_set1_epi16(2);
14346 let b = _mm256_set1_epi16(1);
14347 let m = _mm256_cmpneq_epu16_mask(a, b);
14348 assert_eq!(m, 0b11111111_11111111);
14349 }
14350
14351 #[simd_test(enable = "avx512bw,avx512vl")]
14352 unsafe fn test_mm256_mask_cmpneq_epu16_mask() {
14353 let a = _mm256_set1_epi16(2);
14354 let b = _mm256_set1_epi16(1);
14355 let mask = 0b01010101_01010101;
14356 let r = _mm256_mask_cmpneq_epu16_mask(mask, a, b);
14357 assert_eq!(r, 0b01010101_01010101);
14358 }
14359
14360 #[simd_test(enable = "avx512bw,avx512vl")]
14361 unsafe fn test_mm_cmpneq_epu16_mask() {
14362 let a = _mm_set1_epi16(2);
14363 let b = _mm_set1_epi16(1);
14364 let m = _mm_cmpneq_epu16_mask(a, b);
14365 assert_eq!(m, 0b11111111);
14366 }
14367
14368 #[simd_test(enable = "avx512bw,avx512vl")]
14369 unsafe fn test_mm_mask_cmpneq_epu16_mask() {
14370 let a = _mm_set1_epi16(2);
14371 let b = _mm_set1_epi16(1);
14372 let mask = 0b01010101;
14373 let r = _mm_mask_cmpneq_epu16_mask(mask, a, b);
14374 assert_eq!(r, 0b01010101);
14375 }
14376
14377 #[simd_test(enable = "avx512bw")]
14378 unsafe fn test_mm512_cmpneq_epu8_mask() {
14379 let a = _mm512_set1_epi8(2);
14380 let b = _mm512_set1_epi8(1);
14381 let m = _mm512_cmpneq_epu8_mask(a, b);
14382 assert_eq!(
14383 m,
14384 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14385 );
14386 }
14387
14388 #[simd_test(enable = "avx512bw")]
14389 unsafe fn test_mm512_mask_cmpneq_epu8_mask() {
14390 let a = _mm512_set1_epi8(2);
14391 let b = _mm512_set1_epi8(1);
14392 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14393 let r = _mm512_mask_cmpneq_epu8_mask(mask, a, b);
14394 assert_eq!(
14395 r,
14396 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14397 );
14398 }
14399
14400 #[simd_test(enable = "avx512bw,avx512vl")]
14401 unsafe fn test_mm256_cmpneq_epu8_mask() {
14402 let a = _mm256_set1_epi8(2);
14403 let b = _mm256_set1_epi8(1);
14404 let m = _mm256_cmpneq_epu8_mask(a, b);
14405 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14406 }
14407
14408 #[simd_test(enable = "avx512bw,avx512vl")]
14409 unsafe fn test_mm256_mask_cmpneq_epu8_mask() {
14410 let a = _mm256_set1_epi8(2);
14411 let b = _mm256_set1_epi8(1);
14412 let mask = 0b01010101_01010101_01010101_01010101;
14413 let r = _mm256_mask_cmpneq_epu8_mask(mask, a, b);
14414 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14415 }
14416
14417 #[simd_test(enable = "avx512bw,avx512vl")]
14418 unsafe fn test_mm_cmpneq_epu8_mask() {
14419 let a = _mm_set1_epi8(2);
14420 let b = _mm_set1_epi8(1);
14421 let m = _mm_cmpneq_epu8_mask(a, b);
14422 assert_eq!(m, 0b11111111_11111111);
14423 }
14424
14425 #[simd_test(enable = "avx512bw,avx512vl")]
14426 unsafe fn test_mm_mask_cmpneq_epu8_mask() {
14427 let a = _mm_set1_epi8(2);
14428 let b = _mm_set1_epi8(1);
14429 let mask = 0b01010101_01010101;
14430 let r = _mm_mask_cmpneq_epu8_mask(mask, a, b);
14431 assert_eq!(r, 0b01010101_01010101);
14432 }
14433
14434 #[simd_test(enable = "avx512bw")]
14435 unsafe fn test_mm512_cmpneq_epi16_mask() {
14436 let a = _mm512_set1_epi16(1);
14437 let b = _mm512_set1_epi16(-1);
14438 let m = _mm512_cmpneq_epi16_mask(a, b);
14439 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14440 }
14441
14442 #[simd_test(enable = "avx512bw")]
14443 unsafe fn test_mm512_mask_cmpneq_epi16_mask() {
14444 let a = _mm512_set1_epi16(1);
14445 let b = _mm512_set1_epi16(-1);
14446 let mask = 0b01010101_01010101_01010101_01010101;
14447 let r = _mm512_mask_cmpneq_epi16_mask(mask, a, b);
14448 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14449 }
14450
14451 #[simd_test(enable = "avx512bw,avx512vl")]
14452 unsafe fn test_mm256_cmpneq_epi16_mask() {
14453 let a = _mm256_set1_epi16(1);
14454 let b = _mm256_set1_epi16(-1);
14455 let m = _mm256_cmpneq_epi16_mask(a, b);
14456 assert_eq!(m, 0b11111111_11111111);
14457 }
14458
14459 #[simd_test(enable = "avx512bw,avx512vl")]
14460 unsafe fn test_mm256_mask_cmpneq_epi16_mask() {
14461 let a = _mm256_set1_epi16(1);
14462 let b = _mm256_set1_epi16(-1);
14463 let mask = 0b01010101_01010101;
14464 let r = _mm256_mask_cmpneq_epi16_mask(mask, a, b);
14465 assert_eq!(r, 0b01010101_01010101);
14466 }
14467
14468 #[simd_test(enable = "avx512bw,avx512vl")]
14469 unsafe fn test_mm_cmpneq_epi16_mask() {
14470 let a = _mm_set1_epi16(1);
14471 let b = _mm_set1_epi16(-1);
14472 let m = _mm_cmpneq_epi16_mask(a, b);
14473 assert_eq!(m, 0b11111111);
14474 }
14475
14476 #[simd_test(enable = "avx512bw,avx512vl")]
14477 unsafe fn test_mm_mask_cmpneq_epi16_mask() {
14478 let a = _mm_set1_epi16(1);
14479 let b = _mm_set1_epi16(-1);
14480 let mask = 0b01010101;
14481 let r = _mm_mask_cmpneq_epi16_mask(mask, a, b);
14482 assert_eq!(r, 0b01010101);
14483 }
14484
14485 #[simd_test(enable = "avx512bw")]
14486 unsafe fn test_mm512_cmpneq_epi8_mask() {
14487 let a = _mm512_set1_epi8(1);
14488 let b = _mm512_set1_epi8(-1);
14489 let m = _mm512_cmpneq_epi8_mask(a, b);
14490 assert_eq!(
14491 m,
14492 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14493 );
14494 }
14495
14496 #[simd_test(enable = "avx512bw")]
14497 unsafe fn test_mm512_mask_cmpneq_epi8_mask() {
14498 let a = _mm512_set1_epi8(1);
14499 let b = _mm512_set1_epi8(-1);
14500 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14501 let r = _mm512_mask_cmpneq_epi8_mask(mask, a, b);
14502 assert_eq!(
14503 r,
14504 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14505 );
14506 }
14507
14508 #[simd_test(enable = "avx512bw,avx512vl")]
14509 unsafe fn test_mm256_cmpneq_epi8_mask() {
14510 let a = _mm256_set1_epi8(1);
14511 let b = _mm256_set1_epi8(-1);
14512 let m = _mm256_cmpneq_epi8_mask(a, b);
14513 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14514 }
14515
14516 #[simd_test(enable = "avx512bw,avx512vl")]
14517 unsafe fn test_mm256_mask_cmpneq_epi8_mask() {
14518 let a = _mm256_set1_epi8(1);
14519 let b = _mm256_set1_epi8(-1);
14520 let mask = 0b01010101_01010101_01010101_01010101;
14521 let r = _mm256_mask_cmpneq_epi8_mask(mask, a, b);
14522 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14523 }
14524
14525 #[simd_test(enable = "avx512bw,avx512vl")]
14526 unsafe fn test_mm_cmpneq_epi8_mask() {
14527 let a = _mm_set1_epi8(1);
14528 let b = _mm_set1_epi8(-1);
14529 let m = _mm_cmpneq_epi8_mask(a, b);
14530 assert_eq!(m, 0b11111111_11111111);
14531 }
14532
14533 #[simd_test(enable = "avx512bw,avx512vl")]
14534 unsafe fn test_mm_mask_cmpneq_epi8_mask() {
14535 let a = _mm_set1_epi8(1);
14536 let b = _mm_set1_epi8(-1);
14537 let mask = 0b01010101_01010101;
14538 let r = _mm_mask_cmpneq_epi8_mask(mask, a, b);
14539 assert_eq!(r, 0b01010101_01010101);
14540 }
14541
14542 #[simd_test(enable = "avx512bw")]
14543 unsafe fn test_mm512_cmp_epu16_mask() {
14544 let a = _mm512_set1_epi16(0);
14545 let b = _mm512_set1_epi16(1);
14546 let m = _mm512_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
14547 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14548 }
14549
14550 #[simd_test(enable = "avx512bw")]
14551 unsafe fn test_mm512_mask_cmp_epu16_mask() {
14552 let a = _mm512_set1_epi16(0);
14553 let b = _mm512_set1_epi16(1);
14554 let mask = 0b01010101_01010101_01010101_01010101;
14555 let r = _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b);
14556 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14557 }
14558
14559 #[simd_test(enable = "avx512bw,avx512vl")]
14560 unsafe fn test_mm256_cmp_epu16_mask() {
14561 let a = _mm256_set1_epi16(0);
14562 let b = _mm256_set1_epi16(1);
14563 let m = _mm256_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
14564 assert_eq!(m, 0b11111111_11111111);
14565 }
14566
14567 #[simd_test(enable = "avx512bw,avx512vl")]
14568 unsafe fn test_mm256_mask_cmp_epu16_mask() {
14569 let a = _mm256_set1_epi16(0);
14570 let b = _mm256_set1_epi16(1);
14571 let mask = 0b01010101_01010101;
14572 let r = _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b);
14573 assert_eq!(r, 0b01010101_01010101);
14574 }
14575
14576 #[simd_test(enable = "avx512bw,avx512vl")]
14577 unsafe fn test_mm_cmp_epu16_mask() {
14578 let a = _mm_set1_epi16(0);
14579 let b = _mm_set1_epi16(1);
14580 let m = _mm_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b);
14581 assert_eq!(m, 0b11111111);
14582 }
14583
14584 #[simd_test(enable = "avx512bw,avx512vl")]
14585 unsafe fn test_mm_mask_cmp_epu16_mask() {
14586 let a = _mm_set1_epi16(0);
14587 let b = _mm_set1_epi16(1);
14588 let mask = 0b01010101;
14589 let r = _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b);
14590 assert_eq!(r, 0b01010101);
14591 }
14592
14593 #[simd_test(enable = "avx512bw")]
14594 unsafe fn test_mm512_cmp_epu8_mask() {
14595 let a = _mm512_set1_epi8(0);
14596 let b = _mm512_set1_epi8(1);
14597 let m = _mm512_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
14598 assert_eq!(
14599 m,
14600 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14601 );
14602 }
14603
14604 #[simd_test(enable = "avx512bw")]
14605 unsafe fn test_mm512_mask_cmp_epu8_mask() {
14606 let a = _mm512_set1_epi8(0);
14607 let b = _mm512_set1_epi8(1);
14608 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14609 let r = _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b);
14610 assert_eq!(
14611 r,
14612 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14613 );
14614 }
14615
14616 #[simd_test(enable = "avx512bw,avx512vl")]
14617 unsafe fn test_mm256_cmp_epu8_mask() {
14618 let a = _mm256_set1_epi8(0);
14619 let b = _mm256_set1_epi8(1);
14620 let m = _mm256_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
14621 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14622 }
14623
14624 #[simd_test(enable = "avx512bw,avx512vl")]
14625 unsafe fn test_mm256_mask_cmp_epu8_mask() {
14626 let a = _mm256_set1_epi8(0);
14627 let b = _mm256_set1_epi8(1);
14628 let mask = 0b01010101_01010101_01010101_01010101;
14629 let r = _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b);
14630 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14631 }
14632
14633 #[simd_test(enable = "avx512bw,avx512vl")]
14634 unsafe fn test_mm_cmp_epu8_mask() {
14635 let a = _mm_set1_epi8(0);
14636 let b = _mm_set1_epi8(1);
14637 let m = _mm_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b);
14638 assert_eq!(m, 0b11111111_11111111);
14639 }
14640
14641 #[simd_test(enable = "avx512bw,avx512vl")]
14642 unsafe fn test_mm_mask_cmp_epu8_mask() {
14643 let a = _mm_set1_epi8(0);
14644 let b = _mm_set1_epi8(1);
14645 let mask = 0b01010101_01010101;
14646 let r = _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b);
14647 assert_eq!(r, 0b01010101_01010101);
14648 }
14649
14650 #[simd_test(enable = "avx512bw")]
14651 unsafe fn test_mm512_cmp_epi16_mask() {
14652 let a = _mm512_set1_epi16(0);
14653 let b = _mm512_set1_epi16(1);
14654 let m = _mm512_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
14655 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14656 }
14657
14658 #[simd_test(enable = "avx512bw")]
14659 unsafe fn test_mm512_mask_cmp_epi16_mask() {
14660 let a = _mm512_set1_epi16(0);
14661 let b = _mm512_set1_epi16(1);
14662 let mask = 0b01010101_01010101_01010101_01010101;
14663 let r = _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b);
14664 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14665 }
14666
14667 #[simd_test(enable = "avx512bw,avx512vl")]
14668 unsafe fn test_mm256_cmp_epi16_mask() {
14669 let a = _mm256_set1_epi16(0);
14670 let b = _mm256_set1_epi16(1);
14671 let m = _mm256_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
14672 assert_eq!(m, 0b11111111_11111111);
14673 }
14674
14675 #[simd_test(enable = "avx512bw,avx512vl")]
14676 unsafe fn test_mm256_mask_cmp_epi16_mask() {
14677 let a = _mm256_set1_epi16(0);
14678 let b = _mm256_set1_epi16(1);
14679 let mask = 0b01010101_01010101;
14680 let r = _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b);
14681 assert_eq!(r, 0b01010101_01010101);
14682 }
14683
14684 #[simd_test(enable = "avx512bw,avx512vl")]
14685 unsafe fn test_mm_cmp_epi16_mask() {
14686 let a = _mm_set1_epi16(0);
14687 let b = _mm_set1_epi16(1);
14688 let m = _mm_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b);
14689 assert_eq!(m, 0b11111111);
14690 }
14691
14692 #[simd_test(enable = "avx512bw,avx512vl")]
14693 unsafe fn test_mm_mask_cmp_epi16_mask() {
14694 let a = _mm_set1_epi16(0);
14695 let b = _mm_set1_epi16(1);
14696 let mask = 0b01010101;
14697 let r = _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b);
14698 assert_eq!(r, 0b01010101);
14699 }
14700
14701 #[simd_test(enable = "avx512bw")]
14702 unsafe fn test_mm512_cmp_epi8_mask() {
14703 let a = _mm512_set1_epi8(0);
14704 let b = _mm512_set1_epi8(1);
14705 let m = _mm512_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
14706 assert_eq!(
14707 m,
14708 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111
14709 );
14710 }
14711
14712 #[simd_test(enable = "avx512bw")]
14713 unsafe fn test_mm512_mask_cmp_epi8_mask() {
14714 let a = _mm512_set1_epi8(0);
14715 let b = _mm512_set1_epi8(1);
14716 let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101;
14717 let r = _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b);
14718 assert_eq!(
14719 r,
14720 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101
14721 );
14722 }
14723
14724 #[simd_test(enable = "avx512bw,avx512vl")]
14725 unsafe fn test_mm256_cmp_epi8_mask() {
14726 let a = _mm256_set1_epi8(0);
14727 let b = _mm256_set1_epi8(1);
14728 let m = _mm256_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
14729 assert_eq!(m, 0b11111111_11111111_11111111_11111111);
14730 }
14731
14732 #[simd_test(enable = "avx512bw,avx512vl")]
14733 unsafe fn test_mm256_mask_cmp_epi8_mask() {
14734 let a = _mm256_set1_epi8(0);
14735 let b = _mm256_set1_epi8(1);
14736 let mask = 0b01010101_01010101_01010101_01010101;
14737 let r = _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b);
14738 assert_eq!(r, 0b01010101_01010101_01010101_01010101);
14739 }
14740
14741 #[simd_test(enable = "avx512bw,avx512vl")]
14742 unsafe fn test_mm_cmp_epi8_mask() {
14743 let a = _mm_set1_epi8(0);
14744 let b = _mm_set1_epi8(1);
14745 let m = _mm_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b);
14746 assert_eq!(m, 0b11111111_11111111);
14747 }
14748
14749 #[simd_test(enable = "avx512bw,avx512vl")]
14750 unsafe fn test_mm_mask_cmp_epi8_mask() {
14751 let a = _mm_set1_epi8(0);
14752 let b = _mm_set1_epi8(1);
14753 let mask = 0b01010101_01010101;
14754 let r = _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b);
14755 assert_eq!(r, 0b01010101_01010101);
14756 }
14757
14758 #[simd_test(enable = "avx512bw")]
14759 unsafe fn test_mm512_loadu_epi16() {
14760 #[rustfmt::skip]
14761 let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
14762 let r = _mm512_loadu_epi16(&a[0]);
14763 #[rustfmt::skip]
14764 let e = _mm512_set_epi16(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
14765 assert_eq_m512i(r, e);
14766 }
14767
14768 #[simd_test(enable = "avx512bw,avx512vl")]
14769 unsafe fn test_mm256_loadu_epi16() {
14770 let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
14771 let r = _mm256_loadu_epi16(&a[0]);
14772 let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
14773 assert_eq_m256i(r, e);
14774 }
14775
14776 #[simd_test(enable = "avx512bw,avx512vl")]
14777 unsafe fn test_mm_loadu_epi16() {
14778 let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
14779 let r = _mm_loadu_epi16(&a[0]);
14780 let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
14781 assert_eq_m128i(r, e);
14782 }
14783
14784 #[simd_test(enable = "avx512bw")]
14785 unsafe fn test_mm512_loadu_epi8() {
14786 #[rustfmt::skip]
14787 let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
14788 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
14789 let r = _mm512_loadu_epi8(&a[0]);
14790 #[rustfmt::skip]
14791 let e = _mm512_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
14792 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
14793 assert_eq_m512i(r, e);
14794 }
14795
14796 #[simd_test(enable = "avx512bw,avx512vl")]
14797 unsafe fn test_mm256_loadu_epi8() {
14798 #[rustfmt::skip]
14799 let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
14800 let r = _mm256_loadu_epi8(&a[0]);
14801 #[rustfmt::skip]
14802 let e = _mm256_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
14803 assert_eq_m256i(r, e);
14804 }
14805
14806 #[simd_test(enable = "avx512bw,avx512vl")]
14807 unsafe fn test_mm_loadu_epi8() {
14808 let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
14809 let r = _mm_loadu_epi8(&a[0]);
14810 let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
14811 assert_eq_m128i(r, e);
14812 }
14813
14814 #[simd_test(enable = "avx512bw")]
14815 unsafe fn test_mm512_storeu_epi16() {
14816 let a = _mm512_set1_epi16(9);
14817 let mut r = _mm512_undefined_epi32();
14818 _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
14819 assert_eq_m512i(r, a);
14820 }
14821
14822 #[simd_test(enable = "avx512bw,avx512vl")]
14823 unsafe fn test_mm256_storeu_epi16() {
14824 let a = _mm256_set1_epi16(9);
14825 let mut r = _mm256_set1_epi32(0);
14826 _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
14827 assert_eq_m256i(r, a);
14828 }
14829
14830 #[simd_test(enable = "avx512bw,avx512vl")]
14831 unsafe fn test_mm_storeu_epi16() {
14832 let a = _mm_set1_epi16(9);
14833 let mut r = _mm_set1_epi32(0);
14834 _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
14835 assert_eq_m128i(r, a);
14836 }
14837
14838 #[simd_test(enable = "avx512bw")]
14839 unsafe fn test_mm512_storeu_epi8() {
14840 let a = _mm512_set1_epi8(9);
14841 let mut r = _mm512_undefined_epi32();
14842 _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
14843 assert_eq_m512i(r, a);
14844 }
14845
14846 #[simd_test(enable = "avx512bw,avx512vl")]
14847 unsafe fn test_mm256_storeu_epi8() {
14848 let a = _mm256_set1_epi8(9);
14849 let mut r = _mm256_set1_epi32(0);
14850 _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
14851 assert_eq_m256i(r, a);
14852 }
14853
14854 #[simd_test(enable = "avx512bw,avx512vl")]
14855 unsafe fn test_mm_storeu_epi8() {
14856 let a = _mm_set1_epi8(9);
14857 let mut r = _mm_set1_epi32(0);
14858 _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
14859 assert_eq_m128i(r, a);
14860 }
14861
14862 #[simd_test(enable = "avx512f,avx512bw")]
14863 unsafe fn test_mm512_mask_loadu_epi16() {
14864 let src = _mm512_set1_epi16(42);
14865 let a = &[
14866 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14867 24, 25, 26, 27, 28, 29, 30, 31, 32,
14868 ];
14869 let p = a.as_ptr();
14870 let m = 0b10101010_11001100_11101000_11001010;
14871 let r = _mm512_mask_loadu_epi16(src, m, black_box(p));
14872 let e = &[
14873 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
14874 23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
14875 ];
14876 let e = _mm512_loadu_epi16(e.as_ptr());
14877 assert_eq_m512i(r, e);
14878 }
14879
14880 #[simd_test(enable = "avx512f,avx512bw")]
14881 unsafe fn test_mm512_maskz_loadu_epi16() {
14882 let a = &[
14883 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14884 24, 25, 26, 27, 28, 29, 30, 31, 32,
14885 ];
14886 let p = a.as_ptr();
14887 let m = 0b10101010_11001100_11101000_11001010;
14888 let r = _mm512_maskz_loadu_epi16(m, black_box(p));
14889 let e = &[
14890 0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
14891 26, 0, 28, 0, 30, 0, 32,
14892 ];
14893 let e = _mm512_loadu_epi16(e.as_ptr());
14894 assert_eq_m512i(r, e);
14895 }
14896
14897 #[simd_test(enable = "avx512f,avx512bw")]
14898 unsafe fn test_mm512_mask_storeu_epi16() {
14899 let mut r = [42_i16; 32];
14900 let a = &[
14901 1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14902 24, 25, 26, 27, 28, 29, 30, 31, 32,
14903 ];
14904 let a = _mm512_loadu_epi16(a.as_ptr());
14905 let m = 0b10101010_11001100_11101000_11001010;
14906 _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a);
14907 let e = &[
14908 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
14909 23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
14910 ];
14911 let e = _mm512_loadu_epi16(e.as_ptr());
14912 assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e);
14913 }
14914
14915 #[simd_test(enable = "avx512f,avx512bw")]
14916 unsafe fn test_mm512_mask_loadu_epi8() {
14917 let src = _mm512_set1_epi8(42);
14918 let a = &[
14919 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14920 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
14921 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
14922 ];
14923 let p = a.as_ptr();
14924 let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
14925 let r = _mm512_mask_loadu_epi8(src, m, black_box(p));
14926 let e = &[
14927 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
14928 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
14929 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
14930 ];
14931 let e = _mm512_loadu_epi8(e.as_ptr());
14932 assert_eq_m512i(r, e);
14933 }
14934
14935 #[simd_test(enable = "avx512f,avx512bw")]
14936 unsafe fn test_mm512_maskz_loadu_epi8() {
14937 let a = &[
14938 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14939 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
14940 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
14941 ];
14942 let p = a.as_ptr();
14943 let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
14944 let r = _mm512_maskz_loadu_epi8(m, black_box(p));
14945 let e = &[
14946 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
14947 26, 0, 28, 0, 30, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 45, 46, 47, 48, 49,
14948 50, 51, 52, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0,
14949 ];
14950 let e = _mm512_loadu_epi8(e.as_ptr());
14951 assert_eq_m512i(r, e);
14952 }
14953
14954 #[simd_test(enable = "avx512f,avx512bw")]
14955 unsafe fn test_mm512_mask_storeu_epi8() {
14956 let mut r = [42_i8; 64];
14957 let a = &[
14958 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
14959 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
14960 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
14961 ];
14962 let a = _mm512_loadu_epi8(a.as_ptr());
14963 let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
14964 _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a);
14965 let e = &[
14966 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
14967 23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
14968 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
14969 ];
14970 let e = _mm512_loadu_epi8(e.as_ptr());
14971 assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e);
14972 }
14973
14974 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
14975 unsafe fn test_mm256_mask_loadu_epi16() {
14976 let src = _mm256_set1_epi16(42);
14977 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
14978 let p = a.as_ptr();
14979 let m = 0b11101000_11001010;
14980 let r = _mm256_mask_loadu_epi16(src, m, black_box(p));
14981 let e = &[
14982 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
14983 ];
14984 let e = _mm256_loadu_epi16(e.as_ptr());
14985 assert_eq_m256i(r, e);
14986 }
14987
14988 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
14989 unsafe fn test_mm256_maskz_loadu_epi16() {
14990 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
14991 let p = a.as_ptr();
14992 let m = 0b11101000_11001010;
14993 let r = _mm256_maskz_loadu_epi16(m, black_box(p));
14994 let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
14995 let e = _mm256_loadu_epi16(e.as_ptr());
14996 assert_eq_m256i(r, e);
14997 }
14998
14999 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15000 unsafe fn test_mm256_mask_storeu_epi16() {
15001 let mut r = [42_i16; 16];
15002 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
15003 let a = _mm256_loadu_epi16(a.as_ptr());
15004 let m = 0b11101000_11001010;
15005 _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a);
15006 let e = &[
15007 42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
15008 ];
15009 let e = _mm256_loadu_epi16(e.as_ptr());
15010 assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e);
15011 }
15012
15013 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15014 unsafe fn test_mm256_mask_loadu_epi8() {
15015 let src = _mm256_set1_epi8(42);
15016 let a = &[
15017 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
15018 24, 25, 26, 27, 28, 29, 30, 31, 32,
15019 ];
15020 let p = a.as_ptr();
15021 let m = 0b10101010_11001100_11101000_11001010;
15022 let r = _mm256_mask_loadu_epi8(src, m, black_box(p));
15023 let e = &[
15024 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
15025 23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
15026 ];
15027 let e = _mm256_loadu_epi8(e.as_ptr());
15028 assert_eq_m256i(r, e);
15029 }
15030
15031 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15032 unsafe fn test_mm256_maskz_loadu_epi8() {
15033 let a = &[
15034 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
15035 24, 25, 26, 27, 28, 29, 30, 31, 32,
15036 ];
15037 let p = a.as_ptr();
15038 let m = 0b10101010_11001100_11101000_11001010;
15039 let r = _mm256_maskz_loadu_epi8(m, black_box(p));
15040 let e = &[
15041 0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
15042 26, 0, 28, 0, 30, 0, 32,
15043 ];
15044 let e = _mm256_loadu_epi8(e.as_ptr());
15045 assert_eq_m256i(r, e);
15046 }
15047
15048 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15049 unsafe fn test_mm256_mask_storeu_epi8() {
15050 let mut r = [42_i8; 32];
15051 let a = &[
15052 1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
15053 24, 25, 26, 27, 28, 29, 30, 31, 32,
15054 ];
15055 let a = _mm256_loadu_epi8(a.as_ptr());
15056 let m = 0b10101010_11001100_11101000_11001010;
15057 _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a);
15058 let e = &[
15059 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
15060 23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
15061 ];
15062 let e = _mm256_loadu_epi8(e.as_ptr());
15063 assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e);
15064 }
15065
15066 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15067 unsafe fn test_mm_mask_loadu_epi16() {
15068 let src = _mm_set1_epi16(42);
15069 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
15070 let p = a.as_ptr();
15071 let m = 0b11001010;
15072 let r = _mm_mask_loadu_epi16(src, m, black_box(p));
15073 let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
15074 let e = _mm_loadu_epi16(e.as_ptr());
15075 assert_eq_m128i(r, e);
15076 }
15077
15078 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15079 unsafe fn test_mm_maskz_loadu_epi16() {
15080 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
15081 let p = a.as_ptr();
15082 let m = 0b11001010;
15083 let r = _mm_maskz_loadu_epi16(m, black_box(p));
15084 let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8];
15085 let e = _mm_loadu_epi16(e.as_ptr());
15086 assert_eq_m128i(r, e);
15087 }
15088
15089 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15090 unsafe fn test_mm_mask_storeu_epi16() {
15091 let mut r = [42_i16; 8];
15092 let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
15093 let a = _mm_loadu_epi16(a.as_ptr());
15094 let m = 0b11001010;
15095 _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a);
15096 let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
15097 let e = _mm_loadu_epi16(e.as_ptr());
15098 assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e);
15099 }
15100
15101 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15102 unsafe fn test_mm_mask_loadu_epi8() {
15103 let src = _mm_set1_epi8(42);
15104 let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
15105 let p = a.as_ptr();
15106 let m = 0b11101000_11001010;
15107 let r = _mm_mask_loadu_epi8(src, m, black_box(p));
15108 let e = &[
15109 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
15110 ];
15111 let e = _mm_loadu_epi8(e.as_ptr());
15112 assert_eq_m128i(r, e);
15113 }
15114
15115 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15116 unsafe fn test_mm_maskz_loadu_epi8() {
15117 let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
15118 let p = a.as_ptr();
15119 let m = 0b11101000_11001010;
15120 let r = _mm_maskz_loadu_epi8(m, black_box(p));
15121 let e = &[0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
15122 let e = _mm_loadu_epi8(e.as_ptr());
15123 assert_eq_m128i(r, e);
15124 }
15125
15126 #[simd_test(enable = "avx512f,avx512bw,avx512vl")]
15127 unsafe fn test_mm_mask_storeu_epi8() {
15128 let mut r = [42_i8; 16];
15129 let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
15130 let a = _mm_loadu_epi8(a.as_ptr());
15131 let m = 0b11101000_11001010;
15132 _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a);
15133 let e = &[
15134 42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
15135 ];
15136 let e = _mm_loadu_epi8(e.as_ptr());
15137 assert_eq_m128i(_mm_loadu_epi8(r.as_ptr()), e);
15138 }
15139
15140 #[simd_test(enable = "avx512bw")]
15141 unsafe fn test_mm512_madd_epi16() {
15142 let a = _mm512_set1_epi16(1);
15143 let b = _mm512_set1_epi16(1);
15144 let r = _mm512_madd_epi16(a, b);
15145 let e = _mm512_set1_epi32(2);
15146 assert_eq_m512i(r, e);
15147 }
15148
15149 #[simd_test(enable = "avx512bw")]
15150 unsafe fn test_mm512_mask_madd_epi16() {
15151 let a = _mm512_set1_epi16(1);
15152 let b = _mm512_set1_epi16(1);
15153 let r = _mm512_mask_madd_epi16(a, 0, a, b);
15154 assert_eq_m512i(r, a);
15155 let r = _mm512_mask_madd_epi16(a, 0b00000000_00001111, a, b);
15156 let e = _mm512_set_epi32(
15157 1 << 16 | 1,
15158 1 << 16 | 1,
15159 1 << 16 | 1,
15160 1 << 16 | 1,
15161 1 << 16 | 1,
15162 1 << 16 | 1,
15163 1 << 16 | 1,
15164 1 << 16 | 1,
15165 1 << 16 | 1,
15166 1 << 16 | 1,
15167 1 << 16 | 1,
15168 1 << 16 | 1,
15169 2,
15170 2,
15171 2,
15172 2,
15173 );
15174 assert_eq_m512i(r, e);
15175 }
15176
15177 #[simd_test(enable = "avx512bw")]
15178 unsafe fn test_mm512_maskz_madd_epi16() {
15179 let a = _mm512_set1_epi16(1);
15180 let b = _mm512_set1_epi16(1);
15181 let r = _mm512_maskz_madd_epi16(0, a, b);
15182 assert_eq_m512i(r, _mm512_setzero_si512());
15183 let r = _mm512_maskz_madd_epi16(0b00000000_00001111, a, b);
15184 let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2);
15185 assert_eq_m512i(r, e);
15186 }
15187
15188 #[simd_test(enable = "avx512bw,avx512vl")]
15189 unsafe fn test_mm256_mask_madd_epi16() {
15190 let a = _mm256_set1_epi16(1);
15191 let b = _mm256_set1_epi16(1);
15192 let r = _mm256_mask_madd_epi16(a, 0, a, b);
15193 assert_eq_m256i(r, a);
15194 let r = _mm256_mask_madd_epi16(a, 0b00001111, a, b);
15195 let e = _mm256_set_epi32(
15196 1 << 16 | 1,
15197 1 << 16 | 1,
15198 1 << 16 | 1,
15199 1 << 16 | 1,
15200 2,
15201 2,
15202 2,
15203 2,
15204 );
15205 assert_eq_m256i(r, e);
15206 }
15207
15208 #[simd_test(enable = "avx512bw,avx512vl")]
15209 unsafe fn test_mm256_maskz_madd_epi16() {
15210 let a = _mm256_set1_epi16(1);
15211 let b = _mm256_set1_epi16(1);
15212 let r = _mm256_maskz_madd_epi16(0, a, b);
15213 assert_eq_m256i(r, _mm256_setzero_si256());
15214 let r = _mm256_maskz_madd_epi16(0b00001111, a, b);
15215 let e = _mm256_set_epi32(0, 0, 0, 0, 2, 2, 2, 2);
15216 assert_eq_m256i(r, e);
15217 }
15218
15219 #[simd_test(enable = "avx512bw,avx512vl")]
15220 unsafe fn test_mm_mask_madd_epi16() {
15221 let a = _mm_set1_epi16(1);
15222 let b = _mm_set1_epi16(1);
15223 let r = _mm_mask_madd_epi16(a, 0, a, b);
15224 assert_eq_m128i(r, a);
15225 let r = _mm_mask_madd_epi16(a, 0b00001111, a, b);
15226 let e = _mm_set_epi32(2, 2, 2, 2);
15227 assert_eq_m128i(r, e);
15228 }
15229
15230 #[simd_test(enable = "avx512bw,avx512vl")]
15231 unsafe fn test_mm_maskz_madd_epi16() {
15232 let a = _mm_set1_epi16(1);
15233 let b = _mm_set1_epi16(1);
15234 let r = _mm_maskz_madd_epi16(0, a, b);
15235 assert_eq_m128i(r, _mm_setzero_si128());
15236 let r = _mm_maskz_madd_epi16(0b00001111, a, b);
15237 let e = _mm_set_epi32(2, 2, 2, 2);
15238 assert_eq_m128i(r, e);
15239 }
15240
15241 #[simd_test(enable = "avx512bw")]
15242 unsafe fn test_mm512_maddubs_epi16() {
15243 let a = _mm512_set1_epi8(1);
15244 let b = _mm512_set1_epi8(1);
15245 let r = _mm512_maddubs_epi16(a, b);
15246 let e = _mm512_set1_epi16(2);
15247 assert_eq_m512i(r, e);
15248 }
15249
15250 #[simd_test(enable = "avx512bw")]
15251 unsafe fn test_mm512_mask_maddubs_epi16() {
15252 let a = _mm512_set1_epi8(1);
15253 let b = _mm512_set1_epi8(1);
15254 let src = _mm512_set1_epi16(1);
15255 let r = _mm512_mask_maddubs_epi16(src, 0, a, b);
15256 assert_eq_m512i(r, src);
15257 let r = _mm512_mask_add_epi16(src, 0b00000000_00000000_00000000_00000001, a, b);
15258 #[rustfmt::skip]
15259 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1<<9|2);
15261 assert_eq_m512i(r, e);
15262 }
15263
15264 #[simd_test(enable = "avx512bw")]
15265 unsafe fn test_mm512_maskz_maddubs_epi16() {
15266 let a = _mm512_set1_epi8(1);
15267 let b = _mm512_set1_epi8(1);
15268 let r = _mm512_maskz_maddubs_epi16(0, a, b);
15269 assert_eq_m512i(r, _mm512_setzero_si512());
15270 let r = _mm512_maskz_maddubs_epi16(0b00000000_11111111_00000000_11111111, a, b);
15271 #[rustfmt::skip]
15272 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2,
15273 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
15274 assert_eq_m512i(r, e);
15275 }
15276
15277 #[simd_test(enable = "avx512bw,avx512vl")]
15278 unsafe fn test_mm256_mask_maddubs_epi16() {
15279 let a = _mm256_set1_epi8(1);
15280 let b = _mm256_set1_epi8(1);
15281 let src = _mm256_set1_epi16(1);
15282 let r = _mm256_mask_maddubs_epi16(src, 0, a, b);
15283 assert_eq_m256i(r, src);
15284 let r = _mm256_mask_add_epi16(src, 0b00000000_00000001, a, b);
15285 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 << 9 | 2);
15286 assert_eq_m256i(r, e);
15287 }
15288
15289 #[simd_test(enable = "avx512bw,avx512vl")]
15290 unsafe fn test_mm256_maskz_maddubs_epi16() {
15291 let a = _mm256_set1_epi8(1);
15292 let b = _mm256_set1_epi8(1);
15293 let r = _mm256_maskz_maddubs_epi16(0, a, b);
15294 assert_eq_m256i(r, _mm256_setzero_si256());
15295 let r = _mm256_maskz_maddubs_epi16(0b00000000_11111111, a, b);
15296 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
15297 assert_eq_m256i(r, e);
15298 }
15299
15300 #[simd_test(enable = "avx512bw,avx512vl")]
15301 unsafe fn test_mm_mask_maddubs_epi16() {
15302 let a = _mm_set1_epi8(1);
15303 let b = _mm_set1_epi8(1);
15304 let src = _mm_set1_epi16(1);
15305 let r = _mm_mask_maddubs_epi16(src, 0, a, b);
15306 assert_eq_m128i(r, src);
15307 let r = _mm_mask_add_epi16(src, 0b00000001, a, b);
15308 let e = _mm_set_epi16(1, 1, 1, 1, 1, 1, 1, 1 << 9 | 2);
15309 assert_eq_m128i(r, e);
15310 }
15311
15312 #[simd_test(enable = "avx512bw,avx512vl")]
15313 unsafe fn test_mm_maskz_maddubs_epi16() {
15314 let a = _mm_set1_epi8(1);
15315 let b = _mm_set1_epi8(1);
15316 let r = _mm_maskz_maddubs_epi16(0, a, b);
15317 assert_eq_m128i(r, _mm_setzero_si128());
15318 let r = _mm_maskz_maddubs_epi16(0b00001111, a, b);
15319 let e = _mm_set_epi16(0, 0, 0, 0, 2, 2, 2, 2);
15320 assert_eq_m128i(r, e);
15321 }
15322
15323 #[simd_test(enable = "avx512bw")]
15324 unsafe fn test_mm512_packs_epi32() {
15325 let a = _mm512_set1_epi32(i32::MAX);
15326 let b = _mm512_set1_epi32(1);
15327 let r = _mm512_packs_epi32(a, b);
15328 #[rustfmt::skip]
15329 let e = _mm512_set_epi16(1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX,
15330 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15331 assert_eq_m512i(r, e);
15332 }
15333
15334 #[simd_test(enable = "avx512bw")]
15335 unsafe fn test_mm512_mask_packs_epi32() {
15336 let a = _mm512_set1_epi32(i32::MAX);
15337 let b = _mm512_set1_epi32(1 << 16 | 1);
15338 let r = _mm512_mask_packs_epi32(a, 0, a, b);
15339 assert_eq_m512i(r, a);
15340 let r = _mm512_mask_packs_epi32(b, 0b00000000_00000000_00000000_00001111, a, b);
15341 #[rustfmt::skip]
15342 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15343 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15344 assert_eq_m512i(r, e);
15345 }
15346
15347 #[simd_test(enable = "avx512bw")]
15348 unsafe fn test_mm512_maskz_packs_epi32() {
15349 let a = _mm512_set1_epi32(i32::MAX);
15350 let b = _mm512_set1_epi32(1);
15351 let r = _mm512_maskz_packs_epi32(0, a, b);
15352 assert_eq_m512i(r, _mm512_setzero_si512());
15353 let r = _mm512_maskz_packs_epi32(0b00000000_00000000_00000000_00001111, a, b);
15354 #[rustfmt::skip]
15355 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15356 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15357 assert_eq_m512i(r, e);
15358 }
15359
15360 #[simd_test(enable = "avx512bw,avx512vl")]
15361 unsafe fn test_mm256_mask_packs_epi32() {
15362 let a = _mm256_set1_epi32(i32::MAX);
15363 let b = _mm256_set1_epi32(1 << 16 | 1);
15364 let r = _mm256_mask_packs_epi32(a, 0, a, b);
15365 assert_eq_m256i(r, a);
15366 let r = _mm256_mask_packs_epi32(b, 0b00000000_00001111, a, b);
15367 #[rustfmt::skip]
15368 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15369 assert_eq_m256i(r, e);
15370 }
15371
15372 #[simd_test(enable = "avx512bw,avx512vl")]
15373 unsafe fn test_mm256_maskz_packs_epi32() {
15374 let a = _mm256_set1_epi32(i32::MAX);
15375 let b = _mm256_set1_epi32(1);
15376 let r = _mm256_maskz_packs_epi32(0, a, b);
15377 assert_eq_m256i(r, _mm256_setzero_si256());
15378 let r = _mm256_maskz_packs_epi32(0b00000000_00001111, a, b);
15379 #[rustfmt::skip]
15380 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15381 assert_eq_m256i(r, e);
15382 }
15383
15384 #[simd_test(enable = "avx512bw,avx512vl")]
15385 unsafe fn test_mm_mask_packs_epi32() {
15386 let a = _mm_set1_epi32(i32::MAX);
15387 let b = _mm_set1_epi32(1 << 16 | 1);
15388 let r = _mm_mask_packs_epi32(a, 0, a, b);
15389 assert_eq_m128i(r, a);
15390 let r = _mm_mask_packs_epi32(b, 0b00001111, a, b);
15391 let e = _mm_set_epi16(1, 1, 1, 1, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15392 assert_eq_m128i(r, e);
15393 }
15394
15395 #[simd_test(enable = "avx512bw,avx512vl")]
15396 unsafe fn test_mm_maskz_packs_epi32() {
15397 let a = _mm_set1_epi32(i32::MAX);
15398 let b = _mm_set1_epi32(1);
15399 let r = _mm_maskz_packs_epi32(0, a, b);
15400 assert_eq_m128i(r, _mm_setzero_si128());
15401 let r = _mm_maskz_packs_epi32(0b00001111, a, b);
15402 let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
15403 assert_eq_m128i(r, e);
15404 }
15405
15406 #[simd_test(enable = "avx512bw")]
15407 unsafe fn test_mm512_packs_epi16() {
15408 let a = _mm512_set1_epi16(i16::MAX);
15409 let b = _mm512_set1_epi16(1);
15410 let r = _mm512_packs_epi16(a, b);
15411 #[rustfmt::skip]
15412 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX,
15413 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX,
15414 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX,
15415 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15416 assert_eq_m512i(r, e);
15417 }
15418
15419 #[simd_test(enable = "avx512bw")]
15420 unsafe fn test_mm512_mask_packs_epi16() {
15421 let a = _mm512_set1_epi16(i16::MAX);
15422 let b = _mm512_set1_epi16(1 << 8 | 1);
15423 let r = _mm512_mask_packs_epi16(a, 0, a, b);
15424 assert_eq_m512i(r, a);
15425 let r = _mm512_mask_packs_epi16(
15426 b,
15427 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
15428 a,
15429 b,
15430 );
15431 #[rustfmt::skip]
15432 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15434 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15436 assert_eq_m512i(r, e);
15437 }
15438
15439 #[simd_test(enable = "avx512bw")]
15440 unsafe fn test_mm512_maskz_packs_epi16() {
15441 let a = _mm512_set1_epi16(i16::MAX);
15442 let b = _mm512_set1_epi16(1);
15443 let r = _mm512_maskz_packs_epi16(0, a, b);
15444 assert_eq_m512i(r, _mm512_setzero_si512());
15445 let r = _mm512_maskz_packs_epi16(
15446 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
15447 a,
15448 b,
15449 );
15450 #[rustfmt::skip]
15451 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15455 assert_eq_m512i(r, e);
15456 }
15457
15458 #[simd_test(enable = "avx512bw,avx512vl")]
15459 unsafe fn test_mm256_mask_packs_epi16() {
15460 let a = _mm256_set1_epi16(i16::MAX);
15461 let b = _mm256_set1_epi16(1 << 8 | 1);
15462 let r = _mm256_mask_packs_epi16(a, 0, a, b);
15463 assert_eq_m256i(r, a);
15464 let r = _mm256_mask_packs_epi16(b, 0b00000000_00000000_00000000_00001111, a, b);
15465 #[rustfmt::skip]
15466 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15467 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15468 assert_eq_m256i(r, e);
15469 }
15470
15471 #[simd_test(enable = "avx512bw,avx512vl")]
15472 unsafe fn test_mm256_maskz_packs_epi16() {
15473 let a = _mm256_set1_epi16(i16::MAX);
15474 let b = _mm256_set1_epi16(1);
15475 let r = _mm256_maskz_packs_epi16(0, a, b);
15476 assert_eq_m256i(r, _mm256_setzero_si256());
15477 let r = _mm256_maskz_packs_epi16(0b00000000_00000000_00000000_00001111, a, b);
15478 #[rustfmt::skip]
15479 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15481 assert_eq_m256i(r, e);
15482 }
15483
15484 #[simd_test(enable = "avx512bw,avx512vl")]
15485 unsafe fn test_mm_mask_packs_epi16() {
15486 let a = _mm_set1_epi16(i16::MAX);
15487 let b = _mm_set1_epi16(1 << 8 | 1);
15488 let r = _mm_mask_packs_epi16(a, 0, a, b);
15489 assert_eq_m128i(r, a);
15490 let r = _mm_mask_packs_epi16(b, 0b00000000_00001111, a, b);
15491 #[rustfmt::skip]
15492 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15493 assert_eq_m128i(r, e);
15494 }
15495
15496 #[simd_test(enable = "avx512bw,avx512vl")]
15497 unsafe fn test_mm_maskz_packs_epi16() {
15498 let a = _mm_set1_epi16(i16::MAX);
15499 let b = _mm_set1_epi16(1);
15500 let r = _mm_maskz_packs_epi16(0, a, b);
15501 assert_eq_m128i(r, _mm_setzero_si128());
15502 let r = _mm_maskz_packs_epi16(0b00000000_00001111, a, b);
15503 #[rustfmt::skip]
15504 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
15505 assert_eq_m128i(r, e);
15506 }
15507
15508 #[simd_test(enable = "avx512bw")]
15509 unsafe fn test_mm512_packus_epi32() {
15510 let a = _mm512_set1_epi32(-1);
15511 let b = _mm512_set1_epi32(1);
15512 let r = _mm512_packus_epi32(a, b);
15513 #[rustfmt::skip]
15514 let e = _mm512_set_epi16(1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0,
15515 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0);
15516 assert_eq_m512i(r, e);
15517 }
15518
15519 #[simd_test(enable = "avx512bw")]
15520 unsafe fn test_mm512_mask_packus_epi32() {
15521 let a = _mm512_set1_epi32(-1);
15522 let b = _mm512_set1_epi32(1 << 16 | 1);
15523 let r = _mm512_mask_packus_epi32(a, 0, a, b);
15524 assert_eq_m512i(r, a);
15525 let r = _mm512_mask_packus_epi32(b, 0b00000000_00000000_00000000_00001111, a, b);
15526 #[rustfmt::skip]
15527 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
15529 assert_eq_m512i(r, e);
15530 }
15531
15532 #[simd_test(enable = "avx512bw")]
15533 unsafe fn test_mm512_maskz_packus_epi32() {
15534 let a = _mm512_set1_epi32(-1);
15535 let b = _mm512_set1_epi32(1);
15536 let r = _mm512_maskz_packus_epi32(0, a, b);
15537 assert_eq_m512i(r, _mm512_setzero_si512());
15538 let r = _mm512_maskz_packus_epi32(0b00000000_00000000_00000000_00001111, a, b);
15539 #[rustfmt::skip]
15540 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
15542 assert_eq_m512i(r, e);
15543 }
15544
15545 #[simd_test(enable = "avx512bw,avx512vl")]
15546 unsafe fn test_mm256_mask_packus_epi32() {
15547 let a = _mm256_set1_epi32(-1);
15548 let b = _mm256_set1_epi32(1 << 16 | 1);
15549 let r = _mm256_mask_packus_epi32(a, 0, a, b);
15550 assert_eq_m256i(r, a);
15551 let r = _mm256_mask_packus_epi32(b, 0b00000000_00001111, a, b);
15552 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
15553 assert_eq_m256i(r, e);
15554 }
15555
15556 #[simd_test(enable = "avx512bw,avx512vl")]
15557 unsafe fn test_mm256_maskz_packus_epi32() {
15558 let a = _mm256_set1_epi32(-1);
15559 let b = _mm256_set1_epi32(1);
15560 let r = _mm256_maskz_packus_epi32(0, a, b);
15561 assert_eq_m256i(r, _mm256_setzero_si256());
15562 let r = _mm256_maskz_packus_epi32(0b00000000_00001111, a, b);
15563 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
15564 assert_eq_m256i(r, e);
15565 }
15566
15567 #[simd_test(enable = "avx512bw,avx512vl")]
15568 unsafe fn test_mm_mask_packus_epi32() {
15569 let a = _mm_set1_epi32(-1);
15570 let b = _mm_set1_epi32(1 << 16 | 1);
15571 let r = _mm_mask_packus_epi32(a, 0, a, b);
15572 assert_eq_m128i(r, a);
15573 let r = _mm_mask_packus_epi32(b, 0b00001111, a, b);
15574 let e = _mm_set_epi16(1, 1, 1, 1, 0, 0, 0, 0);
15575 assert_eq_m128i(r, e);
15576 }
15577
15578 #[simd_test(enable = "avx512bw,avx512vl")]
15579 unsafe fn test_mm_maskz_packus_epi32() {
15580 let a = _mm_set1_epi32(-1);
15581 let b = _mm_set1_epi32(1);
15582 let r = _mm_maskz_packus_epi32(0, a, b);
15583 assert_eq_m128i(r, _mm_setzero_si128());
15584 let r = _mm_maskz_packus_epi32(0b00001111, a, b);
15585 let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 0, 0);
15586 assert_eq_m128i(r, e);
15587 }
15588
15589 #[simd_test(enable = "avx512bw")]
15590 unsafe fn test_mm512_packus_epi16() {
15591 let a = _mm512_set1_epi16(-1);
15592 let b = _mm512_set1_epi16(1);
15593 let r = _mm512_packus_epi16(a, b);
15594 #[rustfmt::skip]
15595 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
15596 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
15597 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
15598 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0);
15599 assert_eq_m512i(r, e);
15600 }
15601
15602 #[simd_test(enable = "avx512bw")]
15603 unsafe fn test_mm512_mask_packus_epi16() {
15604 let a = _mm512_set1_epi16(-1);
15605 let b = _mm512_set1_epi16(1 << 8 | 1);
15606 let r = _mm512_mask_packus_epi16(a, 0, a, b);
15607 assert_eq_m512i(r, a);
15608 let r = _mm512_mask_packus_epi16(
15609 b,
15610 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
15611 a,
15612 b,
15613 );
15614 #[rustfmt::skip]
15615 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15616 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15617 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15618 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
15619 assert_eq_m512i(r, e);
15620 }
15621
15622 #[simd_test(enable = "avx512bw")]
15623 unsafe fn test_mm512_maskz_packus_epi16() {
15624 let a = _mm512_set1_epi16(-1);
15625 let b = _mm512_set1_epi16(1);
15626 let r = _mm512_maskz_packus_epi16(0, a, b);
15627 assert_eq_m512i(r, _mm512_setzero_si512());
15628 let r = _mm512_maskz_packus_epi16(
15629 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
15630 a,
15631 b,
15632 );
15633 #[rustfmt::skip]
15634 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15635 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15636 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
15638 assert_eq_m512i(r, e);
15639 }
15640
15641 #[simd_test(enable = "avx512bw,avx512vl")]
15642 unsafe fn test_mm256_mask_packus_epi16() {
15643 let a = _mm256_set1_epi16(-1);
15644 let b = _mm256_set1_epi16(1 << 8 | 1);
15645 let r = _mm256_mask_packus_epi16(a, 0, a, b);
15646 assert_eq_m256i(r, a);
15647 let r = _mm256_mask_packus_epi16(b, 0b00000000_00000000_00000000_00001111, a, b);
15648 #[rustfmt::skip]
15649 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15650 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
15651 assert_eq_m256i(r, e);
15652 }
15653
15654 #[simd_test(enable = "avx512bw,avx512vl")]
15655 unsafe fn test_mm256_maskz_packus_epi16() {
15656 let a = _mm256_set1_epi16(-1);
15657 let b = _mm256_set1_epi16(1);
15658 let r = _mm256_maskz_packus_epi16(0, a, b);
15659 assert_eq_m256i(r, _mm256_setzero_si256());
15660 let r = _mm256_maskz_packus_epi16(0b00000000_00000000_00000000_00001111, a, b);
15661 #[rustfmt::skip]
15662 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15663 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
15664 assert_eq_m256i(r, e);
15665 }
15666
15667 #[simd_test(enable = "avx512bw,avx512vl")]
15668 unsafe fn test_mm_mask_packus_epi16() {
15669 let a = _mm_set1_epi16(-1);
15670 let b = _mm_set1_epi16(1 << 8 | 1);
15671 let r = _mm_mask_packus_epi16(a, 0, a, b);
15672 assert_eq_m128i(r, a);
15673 let r = _mm_mask_packus_epi16(b, 0b00000000_00001111, a, b);
15674 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0);
15675 assert_eq_m128i(r, e);
15676 }
15677
15678 #[simd_test(enable = "avx512bw,avx512vl")]
15679 unsafe fn test_mm_maskz_packus_epi16() {
15680 let a = _mm_set1_epi16(-1);
15681 let b = _mm_set1_epi16(1);
15682 let r = _mm_maskz_packus_epi16(0, a, b);
15683 assert_eq_m128i(r, _mm_setzero_si128());
15684 let r = _mm_maskz_packus_epi16(0b00000000_00001111, a, b);
15685 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
15686 assert_eq_m128i(r, e);
15687 }
15688
15689 #[simd_test(enable = "avx512bw")]
15690 unsafe fn test_mm512_avg_epu16() {
15691 let a = _mm512_set1_epi16(1);
15692 let b = _mm512_set1_epi16(1);
15693 let r = _mm512_avg_epu16(a, b);
15694 let e = _mm512_set1_epi16(1);
15695 assert_eq_m512i(r, e);
15696 }
15697
15698 #[simd_test(enable = "avx512bw")]
15699 unsafe fn test_mm512_mask_avg_epu16() {
15700 let a = _mm512_set1_epi16(1);
15701 let b = _mm512_set1_epi16(1);
15702 let r = _mm512_mask_avg_epu16(a, 0, a, b);
15703 assert_eq_m512i(r, a);
15704 let r = _mm512_mask_avg_epu16(a, 0b00000000_00000000_00000000_00001111, a, b);
15705 #[rustfmt::skip]
15706 let e = _mm512_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15707 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
15708 assert_eq_m512i(r, e);
15709 }
15710
15711 #[simd_test(enable = "avx512bw")]
15712 unsafe fn test_mm512_maskz_avg_epu16() {
15713 let a = _mm512_set1_epi16(1);
15714 let b = _mm512_set1_epi16(1);
15715 let r = _mm512_maskz_avg_epu16(0, a, b);
15716 assert_eq_m512i(r, _mm512_setzero_si512());
15717 let r = _mm512_maskz_avg_epu16(0b00000000_00000000_00000000_00001111, a, b);
15718 #[rustfmt::skip]
15719 let e = _mm512_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
15721 assert_eq_m512i(r, e);
15722 }
15723
15724 #[simd_test(enable = "avx512bw,avx512vl")]
15725 unsafe fn test_mm256_mask_avg_epu16() {
15726 let a = _mm256_set1_epi16(1);
15727 let b = _mm256_set1_epi16(1);
15728 let r = _mm256_mask_avg_epu16(a, 0, a, b);
15729 assert_eq_m256i(r, a);
15730 let r = _mm256_mask_avg_epu16(a, 0b00000000_00001111, a, b);
15731 let e = _mm256_set_epi16(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
15732 assert_eq_m256i(r, e);
15733 }
15734
15735 #[simd_test(enable = "avx512bw,avx512vl")]
15736 unsafe fn test_mm256_maskz_avg_epu16() {
15737 let a = _mm256_set1_epi16(1);
15738 let b = _mm256_set1_epi16(1);
15739 let r = _mm256_maskz_avg_epu16(0, a, b);
15740 assert_eq_m256i(r, _mm256_setzero_si256());
15741 let r = _mm256_maskz_avg_epu16(0b00000000_00001111, a, b);
15742 let e = _mm256_set_epi16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
15743 assert_eq_m256i(r, e);
15744 }
15745
15746 #[simd_test(enable = "avx512bw,avx512vl")]
15747 unsafe fn test_mm_mask_avg_epu16() {
15748 let a = _mm_set1_epi16(1);
15749 let b = _mm_set1_epi16(1);
15750 let r = _mm_mask_avg_epu16(a, 0, a, b);
15751 assert_eq_m128i(r, a);
15752 let r = _mm_mask_avg_epu16(a, 0b00001111, a, b);
15753 let e = _mm_set_epi16(1, 1, 1, 1, 1, 1, 1, 1);
15754 assert_eq_m128i(r, e);
15755 }
15756
15757 #[simd_test(enable = "avx512bw,avx512vl")]
15758 unsafe fn test_mm_maskz_avg_epu16() {
15759 let a = _mm_set1_epi16(1);
15760 let b = _mm_set1_epi16(1);
15761 let r = _mm_maskz_avg_epu16(0, a, b);
15762 assert_eq_m128i(r, _mm_setzero_si128());
15763 let r = _mm_maskz_avg_epu16(0b00001111, a, b);
15764 let e = _mm_set_epi16(0, 0, 0, 0, 1, 1, 1, 1);
15765 assert_eq_m128i(r, e);
15766 }
15767
15768 #[simd_test(enable = "avx512bw")]
15769 unsafe fn test_mm512_avg_epu8() {
15770 let a = _mm512_set1_epi8(1);
15771 let b = _mm512_set1_epi8(1);
15772 let r = _mm512_avg_epu8(a, b);
15773 let e = _mm512_set1_epi8(1);
15774 assert_eq_m512i(r, e);
15775 }
15776
15777 #[simd_test(enable = "avx512bw")]
15778 unsafe fn test_mm512_mask_avg_epu8() {
15779 let a = _mm512_set1_epi8(1);
15780 let b = _mm512_set1_epi8(1);
15781 let r = _mm512_mask_avg_epu8(a, 0, a, b);
15782 assert_eq_m512i(r, a);
15783 let r = _mm512_mask_avg_epu8(
15784 a,
15785 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00001111,
15786 a,
15787 b,
15788 );
15789 #[rustfmt::skip]
15790 let e = _mm512_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15791 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15792 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15793 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
15794 assert_eq_m512i(r, e);
15795 }
15796
15797 #[simd_test(enable = "avx512bw")]
15798 unsafe fn test_mm512_maskz_avg_epu8() {
15799 let a = _mm512_set1_epi8(1);
15800 let b = _mm512_set1_epi8(1);
15801 let r = _mm512_maskz_avg_epu8(0, a, b);
15802 assert_eq_m512i(r, _mm512_setzero_si512());
15803 let r = _mm512_maskz_avg_epu8(
15804 0b00000000_000000000_00000000_00000000_00000000_0000000_00000000_00001111,
15805 a,
15806 b,
15807 );
15808 #[rustfmt::skip]
15809 let e = _mm512_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15811 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
15813 assert_eq_m512i(r, e);
15814 }
15815
15816 #[simd_test(enable = "avx512bw,avx512vl")]
15817 unsafe fn test_mm256_mask_avg_epu8() {
15818 let a = _mm256_set1_epi8(1);
15819 let b = _mm256_set1_epi8(1);
15820 let r = _mm256_mask_avg_epu8(a, 0, a, b);
15821 assert_eq_m256i(r, a);
15822 let r = _mm256_mask_avg_epu8(a, 0b00000000_00000000_00000000_00001111, a, b);
15823 #[rustfmt::skip]
15824 let e = _mm256_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
15825 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
15826 assert_eq_m256i(r, e);
15827 }
15828
15829 #[simd_test(enable = "avx512bw,avx512vl")]
15830 unsafe fn test_mm256_maskz_avg_epu8() {
15831 let a = _mm256_set1_epi8(1);
15832 let b = _mm256_set1_epi8(1);
15833 let r = _mm256_maskz_avg_epu8(0, a, b);
15834 assert_eq_m256i(r, _mm256_setzero_si256());
15835 let r = _mm256_maskz_avg_epu8(0b00000000_0000000_00000000_00001111, a, b);
15836 #[rustfmt::skip]
15837 let e = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15838 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
15839 assert_eq_m256i(r, e);
15840 }
15841
15842 #[simd_test(enable = "avx512bw,avx512vl")]
15843 unsafe fn test_mm_mask_avg_epu8() {
15844 let a = _mm_set1_epi8(1);
15845 let b = _mm_set1_epi8(1);
15846 let r = _mm_mask_avg_epu8(a, 0, a, b);
15847 assert_eq_m128i(r, a);
15848 let r = _mm_mask_avg_epu8(a, 0b00000000_00001111, a, b);
15849 let e = _mm_set_epi8(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
15850 assert_eq_m128i(r, e);
15851 }
15852
15853 #[simd_test(enable = "avx512bw,avx512vl")]
15854 unsafe fn test_mm_maskz_avg_epu8() {
15855 let a = _mm_set1_epi8(1);
15856 let b = _mm_set1_epi8(1);
15857 let r = _mm_maskz_avg_epu8(0, a, b);
15858 assert_eq_m128i(r, _mm_setzero_si128());
15859 let r = _mm_maskz_avg_epu8(0b00000000_00001111, a, b);
15860 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1);
15861 assert_eq_m128i(r, e);
15862 }
15863
15864 #[simd_test(enable = "avx512bw")]
15865 unsafe fn test_mm512_sll_epi16() {
15866 let a = _mm512_set1_epi16(1 << 15);
15867 let count = _mm_set1_epi16(2);
15868 let r = _mm512_sll_epi16(a, count);
15869 let e = _mm512_set1_epi16(0);
15870 assert_eq_m512i(r, e);
15871 }
15872
15873 #[simd_test(enable = "avx512bw")]
15874 unsafe fn test_mm512_mask_sll_epi16() {
15875 let a = _mm512_set1_epi16(1 << 15);
15876 let count = _mm_set1_epi16(2);
15877 let r = _mm512_mask_sll_epi16(a, 0, a, count);
15878 assert_eq_m512i(r, a);
15879 let r = _mm512_mask_sll_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
15880 let e = _mm512_set1_epi16(0);
15881 assert_eq_m512i(r, e);
15882 }
15883
15884 #[simd_test(enable = "avx512bw")]
15885 unsafe fn test_mm512_maskz_sll_epi16() {
15886 let a = _mm512_set1_epi16(1 << 15);
15887 let count = _mm_set1_epi16(2);
15888 let r = _mm512_maskz_sll_epi16(0, a, count);
15889 assert_eq_m512i(r, _mm512_setzero_si512());
15890 let r = _mm512_maskz_sll_epi16(0b11111111_11111111_11111111_11111111, a, count);
15891 let e = _mm512_set1_epi16(0);
15892 assert_eq_m512i(r, e);
15893 }
15894
15895 #[simd_test(enable = "avx512bw,avx512vl")]
15896 unsafe fn test_mm256_mask_sll_epi16() {
15897 let a = _mm256_set1_epi16(1 << 15);
15898 let count = _mm_set1_epi16(2);
15899 let r = _mm256_mask_sll_epi16(a, 0, a, count);
15900 assert_eq_m256i(r, a);
15901 let r = _mm256_mask_sll_epi16(a, 0b11111111_11111111, a, count);
15902 let e = _mm256_set1_epi16(0);
15903 assert_eq_m256i(r, e);
15904 }
15905
15906 #[simd_test(enable = "avx512bw,avx512vl")]
15907 unsafe fn test_mm256_maskz_sll_epi16() {
15908 let a = _mm256_set1_epi16(1 << 15);
15909 let count = _mm_set1_epi16(2);
15910 let r = _mm256_maskz_sll_epi16(0, a, count);
15911 assert_eq_m256i(r, _mm256_setzero_si256());
15912 let r = _mm256_maskz_sll_epi16(0b11111111_11111111, a, count);
15913 let e = _mm256_set1_epi16(0);
15914 assert_eq_m256i(r, e);
15915 }
15916
15917 #[simd_test(enable = "avx512bw,avx512vl")]
15918 unsafe fn test_mm_mask_sll_epi16() {
15919 let a = _mm_set1_epi16(1 << 15);
15920 let count = _mm_set1_epi16(2);
15921 let r = _mm_mask_sll_epi16(a, 0, a, count);
15922 assert_eq_m128i(r, a);
15923 let r = _mm_mask_sll_epi16(a, 0b11111111, a, count);
15924 let e = _mm_set1_epi16(0);
15925 assert_eq_m128i(r, e);
15926 }
15927
15928 #[simd_test(enable = "avx512bw,avx512vl")]
15929 unsafe fn test_mm_maskz_sll_epi16() {
15930 let a = _mm_set1_epi16(1 << 15);
15931 let count = _mm_set1_epi16(2);
15932 let r = _mm_maskz_sll_epi16(0, a, count);
15933 assert_eq_m128i(r, _mm_setzero_si128());
15934 let r = _mm_maskz_sll_epi16(0b11111111, a, count);
15935 let e = _mm_set1_epi16(0);
15936 assert_eq_m128i(r, e);
15937 }
15938
15939 #[simd_test(enable = "avx512bw")]
15940 unsafe fn test_mm512_slli_epi16() {
15941 let a = _mm512_set1_epi16(1 << 15);
15942 let r = _mm512_slli_epi16::<1>(a);
15943 let e = _mm512_set1_epi16(0);
15944 assert_eq_m512i(r, e);
15945 }
15946
15947 #[simd_test(enable = "avx512bw")]
15948 unsafe fn test_mm512_mask_slli_epi16() {
15949 let a = _mm512_set1_epi16(1 << 15);
15950 let r = _mm512_mask_slli_epi16::<1>(a, 0, a);
15951 assert_eq_m512i(r, a);
15952 let r = _mm512_mask_slli_epi16::<1>(a, 0b11111111_11111111_11111111_11111111, a);
15953 let e = _mm512_set1_epi16(0);
15954 assert_eq_m512i(r, e);
15955 }
15956
15957 #[simd_test(enable = "avx512bw")]
15958 unsafe fn test_mm512_maskz_slli_epi16() {
15959 let a = _mm512_set1_epi16(1 << 15);
15960 let r = _mm512_maskz_slli_epi16::<1>(0, a);
15961 assert_eq_m512i(r, _mm512_setzero_si512());
15962 let r = _mm512_maskz_slli_epi16::<1>(0b11111111_11111111_11111111_11111111, a);
15963 let e = _mm512_set1_epi16(0);
15964 assert_eq_m512i(r, e);
15965 }
15966
15967 #[simd_test(enable = "avx512bw,avx512vl")]
15968 unsafe fn test_mm256_mask_slli_epi16() {
15969 let a = _mm256_set1_epi16(1 << 15);
15970 let r = _mm256_mask_slli_epi16::<1>(a, 0, a);
15971 assert_eq_m256i(r, a);
15972 let r = _mm256_mask_slli_epi16::<1>(a, 0b11111111_11111111, a);
15973 let e = _mm256_set1_epi16(0);
15974 assert_eq_m256i(r, e);
15975 }
15976
15977 #[simd_test(enable = "avx512bw,avx512vl")]
15978 unsafe fn test_mm256_maskz_slli_epi16() {
15979 let a = _mm256_set1_epi16(1 << 15);
15980 let r = _mm256_maskz_slli_epi16::<1>(0, a);
15981 assert_eq_m256i(r, _mm256_setzero_si256());
15982 let r = _mm256_maskz_slli_epi16::<1>(0b11111111_11111111, a);
15983 let e = _mm256_set1_epi16(0);
15984 assert_eq_m256i(r, e);
15985 }
15986
15987 #[simd_test(enable = "avx512bw,avx512vl")]
15988 unsafe fn test_mm_mask_slli_epi16() {
15989 let a = _mm_set1_epi16(1 << 15);
15990 let r = _mm_mask_slli_epi16::<1>(a, 0, a);
15991 assert_eq_m128i(r, a);
15992 let r = _mm_mask_slli_epi16::<1>(a, 0b11111111, a);
15993 let e = _mm_set1_epi16(0);
15994 assert_eq_m128i(r, e);
15995 }
15996
15997 #[simd_test(enable = "avx512bw,avx512vl")]
15998 unsafe fn test_mm_maskz_slli_epi16() {
15999 let a = _mm_set1_epi16(1 << 15);
16000 let r = _mm_maskz_slli_epi16::<1>(0, a);
16001 assert_eq_m128i(r, _mm_setzero_si128());
16002 let r = _mm_maskz_slli_epi16::<1>(0b11111111, a);
16003 let e = _mm_set1_epi16(0);
16004 assert_eq_m128i(r, e);
16005 }
16006
16007 #[simd_test(enable = "avx512bw")]
16008 unsafe fn test_mm512_sllv_epi16() {
16009 let a = _mm512_set1_epi16(1 << 15);
16010 let count = _mm512_set1_epi16(2);
16011 let r = _mm512_sllv_epi16(a, count);
16012 let e = _mm512_set1_epi16(0);
16013 assert_eq_m512i(r, e);
16014 }
16015
16016 #[simd_test(enable = "avx512bw")]
16017 unsafe fn test_mm512_mask_sllv_epi16() {
16018 let a = _mm512_set1_epi16(1 << 15);
16019 let count = _mm512_set1_epi16(2);
16020 let r = _mm512_mask_sllv_epi16(a, 0, a, count);
16021 assert_eq_m512i(r, a);
16022 let r = _mm512_mask_sllv_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
16023 let e = _mm512_set1_epi16(0);
16024 assert_eq_m512i(r, e);
16025 }
16026
16027 #[simd_test(enable = "avx512bw")]
16028 unsafe fn test_mm512_maskz_sllv_epi16() {
16029 let a = _mm512_set1_epi16(1 << 15);
16030 let count = _mm512_set1_epi16(2);
16031 let r = _mm512_maskz_sllv_epi16(0, a, count);
16032 assert_eq_m512i(r, _mm512_setzero_si512());
16033 let r = _mm512_maskz_sllv_epi16(0b11111111_11111111_11111111_11111111, a, count);
16034 let e = _mm512_set1_epi16(0);
16035 assert_eq_m512i(r, e);
16036 }
16037
16038 #[simd_test(enable = "avx512bw,avx512vl")]
16039 unsafe fn test_mm256_sllv_epi16() {
16040 let a = _mm256_set1_epi16(1 << 15);
16041 let count = _mm256_set1_epi16(2);
16042 let r = _mm256_sllv_epi16(a, count);
16043 let e = _mm256_set1_epi16(0);
16044 assert_eq_m256i(r, e);
16045 }
16046
16047 #[simd_test(enable = "avx512bw,avx512vl")]
16048 unsafe fn test_mm256_mask_sllv_epi16() {
16049 let a = _mm256_set1_epi16(1 << 15);
16050 let count = _mm256_set1_epi16(2);
16051 let r = _mm256_mask_sllv_epi16(a, 0, a, count);
16052 assert_eq_m256i(r, a);
16053 let r = _mm256_mask_sllv_epi16(a, 0b11111111_11111111, a, count);
16054 let e = _mm256_set1_epi16(0);
16055 assert_eq_m256i(r, e);
16056 }
16057
16058 #[simd_test(enable = "avx512bw,avx512vl")]
16059 unsafe fn test_mm256_maskz_sllv_epi16() {
16060 let a = _mm256_set1_epi16(1 << 15);
16061 let count = _mm256_set1_epi16(2);
16062 let r = _mm256_maskz_sllv_epi16(0, a, count);
16063 assert_eq_m256i(r, _mm256_setzero_si256());
16064 let r = _mm256_maskz_sllv_epi16(0b11111111_11111111, a, count);
16065 let e = _mm256_set1_epi16(0);
16066 assert_eq_m256i(r, e);
16067 }
16068
16069 #[simd_test(enable = "avx512bw,avx512vl")]
16070 unsafe fn test_mm_sllv_epi16() {
16071 let a = _mm_set1_epi16(1 << 15);
16072 let count = _mm_set1_epi16(2);
16073 let r = _mm_sllv_epi16(a, count);
16074 let e = _mm_set1_epi16(0);
16075 assert_eq_m128i(r, e);
16076 }
16077
16078 #[simd_test(enable = "avx512bw,avx512vl")]
16079 unsafe fn test_mm_mask_sllv_epi16() {
16080 let a = _mm_set1_epi16(1 << 15);
16081 let count = _mm_set1_epi16(2);
16082 let r = _mm_mask_sllv_epi16(a, 0, a, count);
16083 assert_eq_m128i(r, a);
16084 let r = _mm_mask_sllv_epi16(a, 0b11111111, a, count);
16085 let e = _mm_set1_epi16(0);
16086 assert_eq_m128i(r, e);
16087 }
16088
16089 #[simd_test(enable = "avx512bw,avx512vl")]
16090 unsafe fn test_mm_maskz_sllv_epi16() {
16091 let a = _mm_set1_epi16(1 << 15);
16092 let count = _mm_set1_epi16(2);
16093 let r = _mm_maskz_sllv_epi16(0, a, count);
16094 assert_eq_m128i(r, _mm_setzero_si128());
16095 let r = _mm_maskz_sllv_epi16(0b11111111, a, count);
16096 let e = _mm_set1_epi16(0);
16097 assert_eq_m128i(r, e);
16098 }
16099
16100 #[simd_test(enable = "avx512bw")]
16101 unsafe fn test_mm512_srl_epi16() {
16102 let a = _mm512_set1_epi16(1 << 1);
16103 let count = _mm_set1_epi16(2);
16104 let r = _mm512_srl_epi16(a, count);
16105 let e = _mm512_set1_epi16(0);
16106 assert_eq_m512i(r, e);
16107 }
16108
16109 #[simd_test(enable = "avx512bw")]
16110 unsafe fn test_mm512_mask_srl_epi16() {
16111 let a = _mm512_set1_epi16(1 << 1);
16112 let count = _mm_set1_epi16(2);
16113 let r = _mm512_mask_srl_epi16(a, 0, a, count);
16114 assert_eq_m512i(r, a);
16115 let r = _mm512_mask_srl_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
16116 let e = _mm512_set1_epi16(0);
16117 assert_eq_m512i(r, e);
16118 }
16119
16120 #[simd_test(enable = "avx512bw")]
16121 unsafe fn test_mm512_maskz_srl_epi16() {
16122 let a = _mm512_set1_epi16(1 << 1);
16123 let count = _mm_set1_epi16(2);
16124 let r = _mm512_maskz_srl_epi16(0, a, count);
16125 assert_eq_m512i(r, _mm512_setzero_si512());
16126 let r = _mm512_maskz_srl_epi16(0b11111111_11111111_11111111_11111111, a, count);
16127 let e = _mm512_set1_epi16(0);
16128 assert_eq_m512i(r, e);
16129 }
16130
16131 #[simd_test(enable = "avx512bw,avx512vl")]
16132 unsafe fn test_mm256_mask_srl_epi16() {
16133 let a = _mm256_set1_epi16(1 << 1);
16134 let count = _mm_set1_epi16(2);
16135 let r = _mm256_mask_srl_epi16(a, 0, a, count);
16136 assert_eq_m256i(r, a);
16137 let r = _mm256_mask_srl_epi16(a, 0b11111111_11111111, a, count);
16138 let e = _mm256_set1_epi16(0);
16139 assert_eq_m256i(r, e);
16140 }
16141
16142 #[simd_test(enable = "avx512bw,avx512vl")]
16143 unsafe fn test_mm256_maskz_srl_epi16() {
16144 let a = _mm256_set1_epi16(1 << 1);
16145 let count = _mm_set1_epi16(2);
16146 let r = _mm256_maskz_srl_epi16(0, a, count);
16147 assert_eq_m256i(r, _mm256_setzero_si256());
16148 let r = _mm256_maskz_srl_epi16(0b11111111_11111111, a, count);
16149 let e = _mm256_set1_epi16(0);
16150 assert_eq_m256i(r, e);
16151 }
16152
16153 #[simd_test(enable = "avx512bw,avx512vl")]
16154 unsafe fn test_mm_mask_srl_epi16() {
16155 let a = _mm_set1_epi16(1 << 1);
16156 let count = _mm_set1_epi16(2);
16157 let r = _mm_mask_srl_epi16(a, 0, a, count);
16158 assert_eq_m128i(r, a);
16159 let r = _mm_mask_srl_epi16(a, 0b11111111, a, count);
16160 let e = _mm_set1_epi16(0);
16161 assert_eq_m128i(r, e);
16162 }
16163
16164 #[simd_test(enable = "avx512bw,avx512vl")]
16165 unsafe fn test_mm_maskz_srl_epi16() {
16166 let a = _mm_set1_epi16(1 << 1);
16167 let count = _mm_set1_epi16(2);
16168 let r = _mm_maskz_srl_epi16(0, a, count);
16169 assert_eq_m128i(r, _mm_setzero_si128());
16170 let r = _mm_maskz_srl_epi16(0b11111111, a, count);
16171 let e = _mm_set1_epi16(0);
16172 assert_eq_m128i(r, e);
16173 }
16174
16175 #[simd_test(enable = "avx512bw")]
16176 unsafe fn test_mm512_srli_epi16() {
16177 let a = _mm512_set1_epi16(1 << 1);
16178 let r = _mm512_srli_epi16::<2>(a);
16179 let e = _mm512_set1_epi16(0);
16180 assert_eq_m512i(r, e);
16181 }
16182
16183 #[simd_test(enable = "avx512bw")]
16184 unsafe fn test_mm512_mask_srli_epi16() {
16185 let a = _mm512_set1_epi16(1 << 1);
16186 let r = _mm512_mask_srli_epi16::<2>(a, 0, a);
16187 assert_eq_m512i(r, a);
16188 let r = _mm512_mask_srli_epi16::<2>(a, 0b11111111_11111111_11111111_11111111, a);
16189 let e = _mm512_set1_epi16(0);
16190 assert_eq_m512i(r, e);
16191 }
16192
16193 #[simd_test(enable = "avx512bw")]
16194 unsafe fn test_mm512_maskz_srli_epi16() {
16195 let a = _mm512_set1_epi16(1 << 1);
16196 let r = _mm512_maskz_srli_epi16::<2>(0, a);
16197 assert_eq_m512i(r, _mm512_setzero_si512());
16198 let r = _mm512_maskz_srli_epi16::<2>(0b11111111_11111111_11111111_11111111, a);
16199 let e = _mm512_set1_epi16(0);
16200 assert_eq_m512i(r, e);
16201 }
16202
16203 #[simd_test(enable = "avx512bw,avx512vl")]
16204 unsafe fn test_mm256_mask_srli_epi16() {
16205 let a = _mm256_set1_epi16(1 << 1);
16206 let r = _mm256_mask_srli_epi16::<2>(a, 0, a);
16207 assert_eq_m256i(r, a);
16208 let r = _mm256_mask_srli_epi16::<2>(a, 0b11111111_11111111, a);
16209 let e = _mm256_set1_epi16(0);
16210 assert_eq_m256i(r, e);
16211 }
16212
16213 #[simd_test(enable = "avx512bw,avx512vl")]
16214 unsafe fn test_mm256_maskz_srli_epi16() {
16215 let a = _mm256_set1_epi16(1 << 1);
16216 let r = _mm256_maskz_srli_epi16::<2>(0, a);
16217 assert_eq_m256i(r, _mm256_setzero_si256());
16218 let r = _mm256_maskz_srli_epi16::<2>(0b11111111_11111111, a);
16219 let e = _mm256_set1_epi16(0);
16220 assert_eq_m256i(r, e);
16221 }
16222
16223 #[simd_test(enable = "avx512bw,avx512vl")]
16224 unsafe fn test_mm_mask_srli_epi16() {
16225 let a = _mm_set1_epi16(1 << 1);
16226 let r = _mm_mask_srli_epi16::<2>(a, 0, a);
16227 assert_eq_m128i(r, a);
16228 let r = _mm_mask_srli_epi16::<2>(a, 0b11111111, a);
16229 let e = _mm_set1_epi16(0);
16230 assert_eq_m128i(r, e);
16231 }
16232
16233 #[simd_test(enable = "avx512bw,avx512vl")]
16234 unsafe fn test_mm_maskz_srli_epi16() {
16235 let a = _mm_set1_epi16(1 << 1);
16236 let r = _mm_maskz_srli_epi16::<2>(0, a);
16237 assert_eq_m128i(r, _mm_setzero_si128());
16238 let r = _mm_maskz_srli_epi16::<2>(0b11111111, a);
16239 let e = _mm_set1_epi16(0);
16240 assert_eq_m128i(r, e);
16241 }
16242
16243 #[simd_test(enable = "avx512bw")]
16244 unsafe fn test_mm512_srlv_epi16() {
16245 let a = _mm512_set1_epi16(1 << 1);
16246 let count = _mm512_set1_epi16(2);
16247 let r = _mm512_srlv_epi16(a, count);
16248 let e = _mm512_set1_epi16(0);
16249 assert_eq_m512i(r, e);
16250 }
16251
16252 #[simd_test(enable = "avx512bw")]
16253 unsafe fn test_mm512_mask_srlv_epi16() {
16254 let a = _mm512_set1_epi16(1 << 1);
16255 let count = _mm512_set1_epi16(2);
16256 let r = _mm512_mask_srlv_epi16(a, 0, a, count);
16257 assert_eq_m512i(r, a);
16258 let r = _mm512_mask_srlv_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
16259 let e = _mm512_set1_epi16(0);
16260 assert_eq_m512i(r, e);
16261 }
16262
16263 #[simd_test(enable = "avx512bw")]
16264 unsafe fn test_mm512_maskz_srlv_epi16() {
16265 let a = _mm512_set1_epi16(1 << 1);
16266 let count = _mm512_set1_epi16(2);
16267 let r = _mm512_maskz_srlv_epi16(0, a, count);
16268 assert_eq_m512i(r, _mm512_setzero_si512());
16269 let r = _mm512_maskz_srlv_epi16(0b11111111_11111111_11111111_11111111, a, count);
16270 let e = _mm512_set1_epi16(0);
16271 assert_eq_m512i(r, e);
16272 }
16273
16274 #[simd_test(enable = "avx512bw,avx512vl")]
16275 unsafe fn test_mm256_srlv_epi16() {
16276 let a = _mm256_set1_epi16(1 << 1);
16277 let count = _mm256_set1_epi16(2);
16278 let r = _mm256_srlv_epi16(a, count);
16279 let e = _mm256_set1_epi16(0);
16280 assert_eq_m256i(r, e);
16281 }
16282
16283 #[simd_test(enable = "avx512bw,avx512vl")]
16284 unsafe fn test_mm256_mask_srlv_epi16() {
16285 let a = _mm256_set1_epi16(1 << 1);
16286 let count = _mm256_set1_epi16(2);
16287 let r = _mm256_mask_srlv_epi16(a, 0, a, count);
16288 assert_eq_m256i(r, a);
16289 let r = _mm256_mask_srlv_epi16(a, 0b11111111_11111111, a, count);
16290 let e = _mm256_set1_epi16(0);
16291 assert_eq_m256i(r, e);
16292 }
16293
16294 #[simd_test(enable = "avx512bw,avx512vl")]
16295 unsafe fn test_mm256_maskz_srlv_epi16() {
16296 let a = _mm256_set1_epi16(1 << 1);
16297 let count = _mm256_set1_epi16(2);
16298 let r = _mm256_maskz_srlv_epi16(0, a, count);
16299 assert_eq_m256i(r, _mm256_setzero_si256());
16300 let r = _mm256_maskz_srlv_epi16(0b11111111_11111111, a, count);
16301 let e = _mm256_set1_epi16(0);
16302 assert_eq_m256i(r, e);
16303 }
16304
16305 #[simd_test(enable = "avx512bw,avx512vl")]
16306 unsafe fn test_mm_srlv_epi16() {
16307 let a = _mm_set1_epi16(1 << 1);
16308 let count = _mm_set1_epi16(2);
16309 let r = _mm_srlv_epi16(a, count);
16310 let e = _mm_set1_epi16(0);
16311 assert_eq_m128i(r, e);
16312 }
16313
16314 #[simd_test(enable = "avx512bw,avx512vl")]
16315 unsafe fn test_mm_mask_srlv_epi16() {
16316 let a = _mm_set1_epi16(1 << 1);
16317 let count = _mm_set1_epi16(2);
16318 let r = _mm_mask_srlv_epi16(a, 0, a, count);
16319 assert_eq_m128i(r, a);
16320 let r = _mm_mask_srlv_epi16(a, 0b11111111, a, count);
16321 let e = _mm_set1_epi16(0);
16322 assert_eq_m128i(r, e);
16323 }
16324
16325 #[simd_test(enable = "avx512bw,avx512vl")]
16326 unsafe fn test_mm_maskz_srlv_epi16() {
16327 let a = _mm_set1_epi16(1 << 1);
16328 let count = _mm_set1_epi16(2);
16329 let r = _mm_maskz_srlv_epi16(0, a, count);
16330 assert_eq_m128i(r, _mm_setzero_si128());
16331 let r = _mm_maskz_srlv_epi16(0b11111111, a, count);
16332 let e = _mm_set1_epi16(0);
16333 assert_eq_m128i(r, e);
16334 }
16335
16336 #[simd_test(enable = "avx512bw")]
16337 unsafe fn test_mm512_sra_epi16() {
16338 let a = _mm512_set1_epi16(8);
16339 let count = _mm_set1_epi16(1);
16340 let r = _mm512_sra_epi16(a, count);
16341 let e = _mm512_set1_epi16(0);
16342 assert_eq_m512i(r, e);
16343 }
16344
16345 #[simd_test(enable = "avx512bw")]
16346 unsafe fn test_mm512_mask_sra_epi16() {
16347 let a = _mm512_set1_epi16(8);
16348 let count = _mm_set1_epi16(1);
16349 let r = _mm512_mask_sra_epi16(a, 0, a, count);
16350 assert_eq_m512i(r, a);
16351 let r = _mm512_mask_sra_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
16352 let e = _mm512_set1_epi16(0);
16353 assert_eq_m512i(r, e);
16354 }
16355
16356 #[simd_test(enable = "avx512bw")]
16357 unsafe fn test_mm512_maskz_sra_epi16() {
16358 let a = _mm512_set1_epi16(8);
16359 let count = _mm_set1_epi16(1);
16360 let r = _mm512_maskz_sra_epi16(0, a, count);
16361 assert_eq_m512i(r, _mm512_setzero_si512());
16362 let r = _mm512_maskz_sra_epi16(0b11111111_11111111_11111111_11111111, a, count);
16363 let e = _mm512_set1_epi16(0);
16364 assert_eq_m512i(r, e);
16365 }
16366
16367 #[simd_test(enable = "avx512bw,avx512vl")]
16368 unsafe fn test_mm256_mask_sra_epi16() {
16369 let a = _mm256_set1_epi16(8);
16370 let count = _mm_set1_epi16(1);
16371 let r = _mm256_mask_sra_epi16(a, 0, a, count);
16372 assert_eq_m256i(r, a);
16373 let r = _mm256_mask_sra_epi16(a, 0b11111111_11111111, a, count);
16374 let e = _mm256_set1_epi16(0);
16375 assert_eq_m256i(r, e);
16376 }
16377
16378 #[simd_test(enable = "avx512bw,avx512vl")]
16379 unsafe fn test_mm256_maskz_sra_epi16() {
16380 let a = _mm256_set1_epi16(8);
16381 let count = _mm_set1_epi16(1);
16382 let r = _mm256_maskz_sra_epi16(0, a, count);
16383 assert_eq_m256i(r, _mm256_setzero_si256());
16384 let r = _mm256_maskz_sra_epi16(0b11111111_11111111, a, count);
16385 let e = _mm256_set1_epi16(0);
16386 assert_eq_m256i(r, e);
16387 }
16388
16389 #[simd_test(enable = "avx512bw,avx512vl")]
16390 unsafe fn test_mm_mask_sra_epi16() {
16391 let a = _mm_set1_epi16(8);
16392 let count = _mm_set1_epi16(1);
16393 let r = _mm_mask_sra_epi16(a, 0, a, count);
16394 assert_eq_m128i(r, a);
16395 let r = _mm_mask_sra_epi16(a, 0b11111111, a, count);
16396 let e = _mm_set1_epi16(0);
16397 assert_eq_m128i(r, e);
16398 }
16399
16400 #[simd_test(enable = "avx512bw,avx512vl")]
16401 unsafe fn test_mm_maskz_sra_epi16() {
16402 let a = _mm_set1_epi16(8);
16403 let count = _mm_set1_epi16(1);
16404 let r = _mm_maskz_sra_epi16(0, a, count);
16405 assert_eq_m128i(r, _mm_setzero_si128());
16406 let r = _mm_maskz_sra_epi16(0b11111111, a, count);
16407 let e = _mm_set1_epi16(0);
16408 assert_eq_m128i(r, e);
16409 }
16410
16411 #[simd_test(enable = "avx512bw")]
16412 unsafe fn test_mm512_srai_epi16() {
16413 let a = _mm512_set1_epi16(8);
16414 let r = _mm512_srai_epi16::<2>(a);
16415 let e = _mm512_set1_epi16(2);
16416 assert_eq_m512i(r, e);
16417 }
16418
16419 #[simd_test(enable = "avx512bw")]
16420 unsafe fn test_mm512_mask_srai_epi16() {
16421 let a = _mm512_set1_epi16(8);
16422 let r = _mm512_mask_srai_epi16::<2>(a, 0, a);
16423 assert_eq_m512i(r, a);
16424 let r = _mm512_mask_srai_epi16::<2>(a, 0b11111111_11111111_11111111_11111111, a);
16425 let e = _mm512_set1_epi16(2);
16426 assert_eq_m512i(r, e);
16427 }
16428
16429 #[simd_test(enable = "avx512bw")]
16430 unsafe fn test_mm512_maskz_srai_epi16() {
16431 let a = _mm512_set1_epi16(8);
16432 let r = _mm512_maskz_srai_epi16::<2>(0, a);
16433 assert_eq_m512i(r, _mm512_setzero_si512());
16434 let r = _mm512_maskz_srai_epi16::<2>(0b11111111_11111111_11111111_11111111, a);
16435 let e = _mm512_set1_epi16(2);
16436 assert_eq_m512i(r, e);
16437 }
16438
16439 #[simd_test(enable = "avx512bw,avx512vl")]
16440 unsafe fn test_mm256_mask_srai_epi16() {
16441 let a = _mm256_set1_epi16(8);
16442 let r = _mm256_mask_srai_epi16::<2>(a, 0, a);
16443 assert_eq_m256i(r, a);
16444 let r = _mm256_mask_srai_epi16::<2>(a, 0b11111111_11111111, a);
16445 let e = _mm256_set1_epi16(2);
16446 assert_eq_m256i(r, e);
16447 }
16448
16449 #[simd_test(enable = "avx512bw,avx512vl")]
16450 unsafe fn test_mm256_maskz_srai_epi16() {
16451 let a = _mm256_set1_epi16(8);
16452 let r = _mm256_maskz_srai_epi16::<2>(0, a);
16453 assert_eq_m256i(r, _mm256_setzero_si256());
16454 let r = _mm256_maskz_srai_epi16::<2>(0b11111111_11111111, a);
16455 let e = _mm256_set1_epi16(2);
16456 assert_eq_m256i(r, e);
16457 }
16458
16459 #[simd_test(enable = "avx512bw,avx512vl")]
16460 unsafe fn test_mm_mask_srai_epi16() {
16461 let a = _mm_set1_epi16(8);
16462 let r = _mm_mask_srai_epi16::<2>(a, 0, a);
16463 assert_eq_m128i(r, a);
16464 let r = _mm_mask_srai_epi16::<2>(a, 0b11111111, a);
16465 let e = _mm_set1_epi16(2);
16466 assert_eq_m128i(r, e);
16467 }
16468
16469 #[simd_test(enable = "avx512bw,avx512vl")]
16470 unsafe fn test_mm_maskz_srai_epi16() {
16471 let a = _mm_set1_epi16(8);
16472 let r = _mm_maskz_srai_epi16::<2>(0, a);
16473 assert_eq_m128i(r, _mm_setzero_si128());
16474 let r = _mm_maskz_srai_epi16::<2>(0b11111111, a);
16475 let e = _mm_set1_epi16(2);
16476 assert_eq_m128i(r, e);
16477 }
16478
16479 #[simd_test(enable = "avx512bw")]
16480 unsafe fn test_mm512_srav_epi16() {
16481 let a = _mm512_set1_epi16(8);
16482 let count = _mm512_set1_epi16(2);
16483 let r = _mm512_srav_epi16(a, count);
16484 let e = _mm512_set1_epi16(2);
16485 assert_eq_m512i(r, e);
16486 }
16487
16488 #[simd_test(enable = "avx512bw")]
16489 unsafe fn test_mm512_mask_srav_epi16() {
16490 let a = _mm512_set1_epi16(8);
16491 let count = _mm512_set1_epi16(2);
16492 let r = _mm512_mask_srav_epi16(a, 0, a, count);
16493 assert_eq_m512i(r, a);
16494 let r = _mm512_mask_srav_epi16(a, 0b11111111_11111111_11111111_11111111, a, count);
16495 let e = _mm512_set1_epi16(2);
16496 assert_eq_m512i(r, e);
16497 }
16498
16499 #[simd_test(enable = "avx512bw")]
16500 unsafe fn test_mm512_maskz_srav_epi16() {
16501 let a = _mm512_set1_epi16(8);
16502 let count = _mm512_set1_epi16(2);
16503 let r = _mm512_maskz_srav_epi16(0, a, count);
16504 assert_eq_m512i(r, _mm512_setzero_si512());
16505 let r = _mm512_maskz_srav_epi16(0b11111111_11111111_11111111_11111111, a, count);
16506 let e = _mm512_set1_epi16(2);
16507 assert_eq_m512i(r, e);
16508 }
16509
16510 #[simd_test(enable = "avx512bw,avx512vl")]
16511 unsafe fn test_mm256_srav_epi16() {
16512 let a = _mm256_set1_epi16(8);
16513 let count = _mm256_set1_epi16(2);
16514 let r = _mm256_srav_epi16(a, count);
16515 let e = _mm256_set1_epi16(2);
16516 assert_eq_m256i(r, e);
16517 }
16518
16519 #[simd_test(enable = "avx512bw,avx512vl")]
16520 unsafe fn test_mm256_mask_srav_epi16() {
16521 let a = _mm256_set1_epi16(8);
16522 let count = _mm256_set1_epi16(2);
16523 let r = _mm256_mask_srav_epi16(a, 0, a, count);
16524 assert_eq_m256i(r, a);
16525 let r = _mm256_mask_srav_epi16(a, 0b11111111_11111111, a, count);
16526 let e = _mm256_set1_epi16(2);
16527 assert_eq_m256i(r, e);
16528 }
16529
16530 #[simd_test(enable = "avx512bw,avx512vl")]
16531 unsafe fn test_mm256_maskz_srav_epi16() {
16532 let a = _mm256_set1_epi16(8);
16533 let count = _mm256_set1_epi16(2);
16534 let r = _mm256_maskz_srav_epi16(0, a, count);
16535 assert_eq_m256i(r, _mm256_setzero_si256());
16536 let r = _mm256_maskz_srav_epi16(0b11111111_11111111, a, count);
16537 let e = _mm256_set1_epi16(2);
16538 assert_eq_m256i(r, e);
16539 }
16540
16541 #[simd_test(enable = "avx512bw,avx512vl")]
16542 unsafe fn test_mm_srav_epi16() {
16543 let a = _mm_set1_epi16(8);
16544 let count = _mm_set1_epi16(2);
16545 let r = _mm_srav_epi16(a, count);
16546 let e = _mm_set1_epi16(2);
16547 assert_eq_m128i(r, e);
16548 }
16549
16550 #[simd_test(enable = "avx512bw,avx512vl")]
16551 unsafe fn test_mm_mask_srav_epi16() {
16552 let a = _mm_set1_epi16(8);
16553 let count = _mm_set1_epi16(2);
16554 let r = _mm_mask_srav_epi16(a, 0, a, count);
16555 assert_eq_m128i(r, a);
16556 let r = _mm_mask_srav_epi16(a, 0b11111111, a, count);
16557 let e = _mm_set1_epi16(2);
16558 assert_eq_m128i(r, e);
16559 }
16560
16561 #[simd_test(enable = "avx512bw,avx512vl")]
16562 unsafe fn test_mm_maskz_srav_epi16() {
16563 let a = _mm_set1_epi16(8);
16564 let count = _mm_set1_epi16(2);
16565 let r = _mm_maskz_srav_epi16(0, a, count);
16566 assert_eq_m128i(r, _mm_setzero_si128());
16567 let r = _mm_maskz_srav_epi16(0b11111111, a, count);
16568 let e = _mm_set1_epi16(2);
16569 assert_eq_m128i(r, e);
16570 }
16571
16572 #[simd_test(enable = "avx512bw")]
16573 unsafe fn test_mm512_permutex2var_epi16() {
16574 #[rustfmt::skip]
16575 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16576 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16577 #[rustfmt::skip]
16578 let idx = _mm512_set_epi16(1, 1<<5, 2, 1<<5, 3, 1<<5, 4, 1<<5, 5, 1<<5, 6, 1<<5, 7, 1<<5, 8, 1<<5,
16579 9, 1<<5, 10, 1<<5, 11, 1<<5, 12, 1<<5, 13, 1<<5, 14, 1<<5, 15, 1<<5, 16, 1<<5);
16580 let b = _mm512_set1_epi16(100);
16581 let r = _mm512_permutex2var_epi16(a, idx, b);
16582 #[rustfmt::skip]
16583 let e = _mm512_set_epi16(
16584 30, 100, 29, 100, 28, 100, 27, 100, 26, 100, 25, 100, 24, 100, 23, 100,
16585 22, 100, 21, 100, 20, 100, 19, 100, 18, 100, 17, 100, 16, 100, 15, 100,
16586 );
16587 assert_eq_m512i(r, e);
16588 }
16589
16590 #[simd_test(enable = "avx512bw")]
16591 unsafe fn test_mm512_mask_permutex2var_epi16() {
16592 #[rustfmt::skip]
16593 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16594 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16595 #[rustfmt::skip]
16596 let idx = _mm512_set_epi16(1, 1<<5, 2, 1<<5, 3, 1<<5, 4, 1<<5, 5, 1<<5, 6, 1<<5, 7, 1<<5, 8, 1<<5,
16597 9, 1<<5, 10, 1<<5, 11, 1<<5, 12, 1<<5, 13, 1<<5, 14, 1<<5, 15, 1<<5, 16, 1<<5);
16598 let b = _mm512_set1_epi16(100);
16599 let r = _mm512_mask_permutex2var_epi16(a, 0, idx, b);
16600 assert_eq_m512i(r, a);
16601 let r = _mm512_mask_permutex2var_epi16(a, 0b11111111_11111111_11111111_11111111, idx, b);
16602 #[rustfmt::skip]
16603 let e = _mm512_set_epi16(
16604 30, 100, 29, 100, 28, 100, 27, 100, 26, 100, 25, 100, 24, 100, 23, 100,
16605 22, 100, 21, 100, 20, 100, 19, 100, 18, 100, 17, 100, 16, 100, 15, 100,
16606 );
16607 assert_eq_m512i(r, e);
16608 }
16609
16610 #[simd_test(enable = "avx512bw")]
16611 unsafe fn test_mm512_maskz_permutex2var_epi16() {
16612 #[rustfmt::skip]
16613 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16614 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16615 #[rustfmt::skip]
16616 let idx = _mm512_set_epi16(1, 1<<5, 2, 1<<5, 3, 1<<5, 4, 1<<5, 5, 1<<5, 6, 1<<5, 7, 1<<5, 8, 1<<5,
16617 9, 1<<5, 10, 1<<5, 11, 1<<5, 12, 1<<5, 13, 1<<5, 14, 1<<5, 15, 1<<5, 16, 1<<5);
16618 let b = _mm512_set1_epi16(100);
16619 let r = _mm512_maskz_permutex2var_epi16(0, a, idx, b);
16620 assert_eq_m512i(r, _mm512_setzero_si512());
16621 let r = _mm512_maskz_permutex2var_epi16(0b11111111_11111111_11111111_11111111, a, idx, b);
16622 #[rustfmt::skip]
16623 let e = _mm512_set_epi16(
16624 30, 100, 29, 100, 28, 100, 27, 100, 26, 100, 25, 100, 24, 100, 23, 100,
16625 22, 100, 21, 100, 20, 100, 19, 100, 18, 100, 17, 100, 16, 100, 15, 100,
16626 );
16627 assert_eq_m512i(r, e);
16628 }
16629
16630 #[simd_test(enable = "avx512bw")]
16631 unsafe fn test_mm512_mask2_permutex2var_epi16() {
16632 #[rustfmt::skip]
16633 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16634 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16635 #[rustfmt::skip]
16636 let idx = _mm512_set_epi16(1, 1<<5, 2, 1<<5, 3, 1<<5, 4, 1<<5, 5, 1<<5, 6, 1<<5, 7, 1<<5, 8, 1<<5,
16637 9, 1<<5, 10, 1<<5, 11, 1<<5, 12, 1<<5, 13, 1<<5, 14, 1<<5, 15, 1<<5, 16, 1<<5);
16638 let b = _mm512_set1_epi16(100);
16639 let r = _mm512_mask2_permutex2var_epi16(a, idx, 0, b);
16640 assert_eq_m512i(r, idx);
16641 let r = _mm512_mask2_permutex2var_epi16(a, idx, 0b11111111_11111111_11111111_11111111, b);
16642 #[rustfmt::skip]
16643 let e = _mm512_set_epi16(
16644 30, 100, 29, 100, 28, 100, 27, 100, 26, 100, 25, 100, 24, 100, 23, 100,
16645 22, 100, 21, 100, 20, 100, 19, 100, 18, 100, 17, 100, 16, 100, 15, 100,
16646 );
16647 assert_eq_m512i(r, e);
16648 }
16649
16650 #[simd_test(enable = "avx512bw,avx512vl")]
16651 unsafe fn test_mm256_permutex2var_epi16() {
16652 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16653 #[rustfmt::skip]
16654 let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
16655 let b = _mm256_set1_epi16(100);
16656 let r = _mm256_permutex2var_epi16(a, idx, b);
16657 let e = _mm256_set_epi16(
16658 14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
16659 );
16660 assert_eq_m256i(r, e);
16661 }
16662
16663 #[simd_test(enable = "avx512bw,avx512vl")]
16664 unsafe fn test_mm256_mask_permutex2var_epi16() {
16665 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16666 #[rustfmt::skip]
16667 let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
16668 let b = _mm256_set1_epi16(100);
16669 let r = _mm256_mask_permutex2var_epi16(a, 0, idx, b);
16670 assert_eq_m256i(r, a);
16671 let r = _mm256_mask_permutex2var_epi16(a, 0b11111111_11111111, idx, b);
16672 let e = _mm256_set_epi16(
16673 14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
16674 );
16675 assert_eq_m256i(r, e);
16676 }
16677
16678 #[simd_test(enable = "avx512bw,avx512vl")]
16679 unsafe fn test_mm256_maskz_permutex2var_epi16() {
16680 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16681 #[rustfmt::skip]
16682 let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
16683 let b = _mm256_set1_epi16(100);
16684 let r = _mm256_maskz_permutex2var_epi16(0, a, idx, b);
16685 assert_eq_m256i(r, _mm256_setzero_si256());
16686 let r = _mm256_maskz_permutex2var_epi16(0b11111111_11111111, a, idx, b);
16687 let e = _mm256_set_epi16(
16688 14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
16689 );
16690 assert_eq_m256i(r, e);
16691 }
16692
16693 #[simd_test(enable = "avx512bw,avx512vl")]
16694 unsafe fn test_mm256_mask2_permutex2var_epi16() {
16695 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16696 #[rustfmt::skip]
16697 let idx = _mm256_set_epi16(1, 1<<4, 2, 1<<4, 3, 1<<4, 4, 1<<4, 5, 1<<4, 6, 1<<4, 7, 1<<4, 8, 1<<4);
16698 let b = _mm256_set1_epi16(100);
16699 let r = _mm256_mask2_permutex2var_epi16(a, idx, 0, b);
16700 assert_eq_m256i(r, idx);
16701 let r = _mm256_mask2_permutex2var_epi16(a, idx, 0b11111111_11111111, b);
16702 #[rustfmt::skip]
16703 let e = _mm256_set_epi16(
16704 14, 100, 13, 100, 12, 100, 11, 100, 10, 100, 9, 100, 8, 100, 7, 100,
16705 );
16706 assert_eq_m256i(r, e);
16707 }
16708
16709 #[simd_test(enable = "avx512bw,avx512vl")]
16710 unsafe fn test_mm_permutex2var_epi16() {
16711 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16712 let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
16713 let b = _mm_set1_epi16(100);
16714 let r = _mm_permutex2var_epi16(a, idx, b);
16715 let e = _mm_set_epi16(6, 100, 5, 100, 4, 100, 3, 100);
16716 assert_eq_m128i(r, e);
16717 }
16718
16719 #[simd_test(enable = "avx512bw,avx512vl")]
16720 unsafe fn test_mm_mask_permutex2var_epi16() {
16721 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16722 let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
16723 let b = _mm_set1_epi16(100);
16724 let r = _mm_mask_permutex2var_epi16(a, 0, idx, b);
16725 assert_eq_m128i(r, a);
16726 let r = _mm_mask_permutex2var_epi16(a, 0b11111111, idx, b);
16727 let e = _mm_set_epi16(6, 100, 5, 100, 4, 100, 3, 100);
16728 assert_eq_m128i(r, e);
16729 }
16730
16731 #[simd_test(enable = "avx512bw,avx512vl")]
16732 unsafe fn test_mm_maskz_permutex2var_epi16() {
16733 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16734 let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
16735 let b = _mm_set1_epi16(100);
16736 let r = _mm_maskz_permutex2var_epi16(0, a, idx, b);
16737 assert_eq_m128i(r, _mm_setzero_si128());
16738 let r = _mm_maskz_permutex2var_epi16(0b11111111, a, idx, b);
16739 let e = _mm_set_epi16(6, 100, 5, 100, 4, 100, 3, 100);
16740 assert_eq_m128i(r, e);
16741 }
16742
16743 #[simd_test(enable = "avx512bw,avx512vl")]
16744 unsafe fn test_mm_mask2_permutex2var_epi16() {
16745 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16746 let idx = _mm_set_epi16(1, 1 << 3, 2, 1 << 3, 3, 1 << 3, 4, 1 << 3);
16747 let b = _mm_set1_epi16(100);
16748 let r = _mm_mask2_permutex2var_epi16(a, idx, 0, b);
16749 assert_eq_m128i(r, idx);
16750 let r = _mm_mask2_permutex2var_epi16(a, idx, 0b11111111, b);
16751 let e = _mm_set_epi16(6, 100, 5, 100, 4, 100, 3, 100);
16752 assert_eq_m128i(r, e);
16753 }
16754
16755 #[simd_test(enable = "avx512bw")]
16756 unsafe fn test_mm512_permutexvar_epi16() {
16757 let idx = _mm512_set1_epi16(1);
16758 #[rustfmt::skip]
16759 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16760 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16761 let r = _mm512_permutexvar_epi16(idx, a);
16762 let e = _mm512_set1_epi16(30);
16763 assert_eq_m512i(r, e);
16764 }
16765
16766 #[simd_test(enable = "avx512bw")]
16767 unsafe fn test_mm512_mask_permutexvar_epi16() {
16768 let idx = _mm512_set1_epi16(1);
16769 #[rustfmt::skip]
16770 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16771 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16772 let r = _mm512_mask_permutexvar_epi16(a, 0, idx, a);
16773 assert_eq_m512i(r, a);
16774 let r = _mm512_mask_permutexvar_epi16(a, 0b11111111_11111111_11111111_11111111, idx, a);
16775 let e = _mm512_set1_epi16(30);
16776 assert_eq_m512i(r, e);
16777 }
16778
16779 #[simd_test(enable = "avx512bw")]
16780 unsafe fn test_mm512_maskz_permutexvar_epi16() {
16781 let idx = _mm512_set1_epi16(1);
16782 #[rustfmt::skip]
16783 let a = _mm512_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16784 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
16785 let r = _mm512_maskz_permutexvar_epi16(0, idx, a);
16786 assert_eq_m512i(r, _mm512_setzero_si512());
16787 let r = _mm512_maskz_permutexvar_epi16(0b11111111_11111111_11111111_11111111, idx, a);
16788 let e = _mm512_set1_epi16(30);
16789 assert_eq_m512i(r, e);
16790 }
16791
16792 #[simd_test(enable = "avx512bw,avx512vl")]
16793 unsafe fn test_mm256_permutexvar_epi16() {
16794 let idx = _mm256_set1_epi16(1);
16795 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16796 let r = _mm256_permutexvar_epi16(idx, a);
16797 let e = _mm256_set1_epi16(14);
16798 assert_eq_m256i(r, e);
16799 }
16800
16801 #[simd_test(enable = "avx512bw,avx512vl")]
16802 unsafe fn test_mm256_mask_permutexvar_epi16() {
16803 let idx = _mm256_set1_epi16(1);
16804 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16805 let r = _mm256_mask_permutexvar_epi16(a, 0, idx, a);
16806 assert_eq_m256i(r, a);
16807 let r = _mm256_mask_permutexvar_epi16(a, 0b11111111_11111111, idx, a);
16808 let e = _mm256_set1_epi16(14);
16809 assert_eq_m256i(r, e);
16810 }
16811
16812 #[simd_test(enable = "avx512bw,avx512vl")]
16813 unsafe fn test_mm256_maskz_permutexvar_epi16() {
16814 let idx = _mm256_set1_epi16(1);
16815 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
16816 let r = _mm256_maskz_permutexvar_epi16(0, idx, a);
16817 assert_eq_m256i(r, _mm256_setzero_si256());
16818 let r = _mm256_maskz_permutexvar_epi16(0b11111111_11111111, idx, a);
16819 let e = _mm256_set1_epi16(14);
16820 assert_eq_m256i(r, e);
16821 }
16822
16823 #[simd_test(enable = "avx512bw,avx512vl")]
16824 unsafe fn test_mm_permutexvar_epi16() {
16825 let idx = _mm_set1_epi16(1);
16826 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16827 let r = _mm_permutexvar_epi16(idx, a);
16828 let e = _mm_set1_epi16(6);
16829 assert_eq_m128i(r, e);
16830 }
16831
16832 #[simd_test(enable = "avx512bw,avx512vl")]
16833 unsafe fn test_mm_mask_permutexvar_epi16() {
16834 let idx = _mm_set1_epi16(1);
16835 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16836 let r = _mm_mask_permutexvar_epi16(a, 0, idx, a);
16837 assert_eq_m128i(r, a);
16838 let r = _mm_mask_permutexvar_epi16(a, 0b11111111, idx, a);
16839 let e = _mm_set1_epi16(6);
16840 assert_eq_m128i(r, e);
16841 }
16842
16843 #[simd_test(enable = "avx512bw,avx512vl")]
16844 unsafe fn test_mm_maskz_permutexvar_epi16() {
16845 let idx = _mm_set1_epi16(1);
16846 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
16847 let r = _mm_maskz_permutexvar_epi16(0, idx, a);
16848 assert_eq_m128i(r, _mm_setzero_si128());
16849 let r = _mm_maskz_permutexvar_epi16(0b11111111, idx, a);
16850 let e = _mm_set1_epi16(6);
16851 assert_eq_m128i(r, e);
16852 }
16853
16854 #[simd_test(enable = "avx512bw")]
16855 unsafe fn test_mm512_mask_blend_epi16() {
16856 let a = _mm512_set1_epi16(1);
16857 let b = _mm512_set1_epi16(2);
16858 let r = _mm512_mask_blend_epi16(0b11111111_00000000_11111111_00000000, a, b);
16859 #[rustfmt::skip]
16860 let e = _mm512_set_epi16(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
16861 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
16862 assert_eq_m512i(r, e);
16863 }
16864
16865 #[simd_test(enable = "avx512bw,avx512vl")]
16866 unsafe fn test_mm256_mask_blend_epi16() {
16867 let a = _mm256_set1_epi16(1);
16868 let b = _mm256_set1_epi16(2);
16869 let r = _mm256_mask_blend_epi16(0b11111111_00000000, a, b);
16870 let e = _mm256_set_epi16(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
16871 assert_eq_m256i(r, e);
16872 }
16873
16874 #[simd_test(enable = "avx512bw,avx512vl")]
16875 unsafe fn test_mm_mask_blend_epi16() {
16876 let a = _mm_set1_epi16(1);
16877 let b = _mm_set1_epi16(2);
16878 let r = _mm_mask_blend_epi16(0b11110000, a, b);
16879 let e = _mm_set_epi16(2, 2, 2, 2, 1, 1, 1, 1);
16880 assert_eq_m128i(r, e);
16881 }
16882
16883 #[simd_test(enable = "avx512bw")]
16884 unsafe fn test_mm512_mask_blend_epi8() {
16885 let a = _mm512_set1_epi8(1);
16886 let b = _mm512_set1_epi8(2);
16887 let r = _mm512_mask_blend_epi8(
16888 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000,
16889 a,
16890 b,
16891 );
16892 #[rustfmt::skip]
16893 let e = _mm512_set_epi8(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
16894 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
16895 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
16896 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
16897 assert_eq_m512i(r, e);
16898 }
16899
16900 #[simd_test(enable = "avx512bw,avx512vl")]
16901 unsafe fn test_mm256_mask_blend_epi8() {
16902 let a = _mm256_set1_epi8(1);
16903 let b = _mm256_set1_epi8(2);
16904 let r = _mm256_mask_blend_epi8(0b11111111_00000000_11111111_00000000, a, b);
16905 #[rustfmt::skip]
16906 let e = _mm256_set_epi8(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
16907 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
16908 assert_eq_m256i(r, e);
16909 }
16910
16911 #[simd_test(enable = "avx512bw,avx512vl")]
16912 unsafe fn test_mm_mask_blend_epi8() {
16913 let a = _mm_set1_epi8(1);
16914 let b = _mm_set1_epi8(2);
16915 let r = _mm_mask_blend_epi8(0b11111111_00000000, a, b);
16916 let e = _mm_set_epi8(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1);
16917 assert_eq_m128i(r, e);
16918 }
16919
16920 #[simd_test(enable = "avx512bw")]
16921 unsafe fn test_mm512_broadcastw_epi16() {
16922 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16923 let r = _mm512_broadcastw_epi16(a);
16924 let e = _mm512_set1_epi16(24);
16925 assert_eq_m512i(r, e);
16926 }
16927
16928 #[simd_test(enable = "avx512bw")]
16929 unsafe fn test_mm512_mask_broadcastw_epi16() {
16930 let src = _mm512_set1_epi16(1);
16931 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16932 let r = _mm512_mask_broadcastw_epi16(src, 0, a);
16933 assert_eq_m512i(r, src);
16934 let r = _mm512_mask_broadcastw_epi16(src, 0b11111111_11111111_11111111_11111111, a);
16935 let e = _mm512_set1_epi16(24);
16936 assert_eq_m512i(r, e);
16937 }
16938
16939 #[simd_test(enable = "avx512bw")]
16940 unsafe fn test_mm512_maskz_broadcastw_epi16() {
16941 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16942 let r = _mm512_maskz_broadcastw_epi16(0, a);
16943 assert_eq_m512i(r, _mm512_setzero_si512());
16944 let r = _mm512_maskz_broadcastw_epi16(0b11111111_11111111_11111111_11111111, a);
16945 let e = _mm512_set1_epi16(24);
16946 assert_eq_m512i(r, e);
16947 }
16948
16949 #[simd_test(enable = "avx512bw,avx512vl")]
16950 unsafe fn test_mm256_mask_broadcastw_epi16() {
16951 let src = _mm256_set1_epi16(1);
16952 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16953 let r = _mm256_mask_broadcastw_epi16(src, 0, a);
16954 assert_eq_m256i(r, src);
16955 let r = _mm256_mask_broadcastw_epi16(src, 0b11111111_11111111, a);
16956 let e = _mm256_set1_epi16(24);
16957 assert_eq_m256i(r, e);
16958 }
16959
16960 #[simd_test(enable = "avx512bw,avx512vl")]
16961 unsafe fn test_mm256_maskz_broadcastw_epi16() {
16962 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16963 let r = _mm256_maskz_broadcastw_epi16(0, a);
16964 assert_eq_m256i(r, _mm256_setzero_si256());
16965 let r = _mm256_maskz_broadcastw_epi16(0b11111111_11111111, a);
16966 let e = _mm256_set1_epi16(24);
16967 assert_eq_m256i(r, e);
16968 }
16969
16970 #[simd_test(enable = "avx512bw,avx512vl")]
16971 unsafe fn test_mm_mask_broadcastw_epi16() {
16972 let src = _mm_set1_epi16(1);
16973 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16974 let r = _mm_mask_broadcastw_epi16(src, 0, a);
16975 assert_eq_m128i(r, src);
16976 let r = _mm_mask_broadcastw_epi16(src, 0b11111111, a);
16977 let e = _mm_set1_epi16(24);
16978 assert_eq_m128i(r, e);
16979 }
16980
16981 #[simd_test(enable = "avx512bw,avx512vl")]
16982 unsafe fn test_mm_maskz_broadcastw_epi16() {
16983 let a = _mm_set_epi16(17, 18, 19, 20, 21, 22, 23, 24);
16984 let r = _mm_maskz_broadcastw_epi16(0, a);
16985 assert_eq_m128i(r, _mm_setzero_si128());
16986 let r = _mm_maskz_broadcastw_epi16(0b11111111, a);
16987 let e = _mm_set1_epi16(24);
16988 assert_eq_m128i(r, e);
16989 }
16990
16991 #[simd_test(enable = "avx512bw")]
16992 unsafe fn test_mm512_broadcastb_epi8() {
16993 let a = _mm_set_epi8(
16994 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
16995 );
16996 let r = _mm512_broadcastb_epi8(a);
16997 let e = _mm512_set1_epi8(32);
16998 assert_eq_m512i(r, e);
16999 }
17000
17001 #[simd_test(enable = "avx512bw")]
17002 unsafe fn test_mm512_mask_broadcastb_epi8() {
17003 let src = _mm512_set1_epi8(1);
17004 let a = _mm_set_epi8(
17005 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17006 );
17007 let r = _mm512_mask_broadcastb_epi8(src, 0, a);
17008 assert_eq_m512i(r, src);
17009 let r = _mm512_mask_broadcastb_epi8(
17010 src,
17011 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17012 a,
17013 );
17014 let e = _mm512_set1_epi8(32);
17015 assert_eq_m512i(r, e);
17016 }
17017
17018 #[simd_test(enable = "avx512bw")]
17019 unsafe fn test_mm512_maskz_broadcastb_epi8() {
17020 let a = _mm_set_epi8(
17021 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17022 );
17023 let r = _mm512_maskz_broadcastb_epi8(0, a);
17024 assert_eq_m512i(r, _mm512_setzero_si512());
17025 let r = _mm512_maskz_broadcastb_epi8(
17026 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17027 a,
17028 );
17029 let e = _mm512_set1_epi8(32);
17030 assert_eq_m512i(r, e);
17031 }
17032
17033 #[simd_test(enable = "avx512bw,avx512vl")]
17034 unsafe fn test_mm256_mask_broadcastb_epi8() {
17035 let src = _mm256_set1_epi8(1);
17036 let a = _mm_set_epi8(
17037 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17038 );
17039 let r = _mm256_mask_broadcastb_epi8(src, 0, a);
17040 assert_eq_m256i(r, src);
17041 let r = _mm256_mask_broadcastb_epi8(src, 0b11111111_11111111_11111111_11111111, a);
17042 let e = _mm256_set1_epi8(32);
17043 assert_eq_m256i(r, e);
17044 }
17045
17046 #[simd_test(enable = "avx512bw,avx512vl")]
17047 unsafe fn test_mm256_maskz_broadcastb_epi8() {
17048 let a = _mm_set_epi8(
17049 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17050 );
17051 let r = _mm256_maskz_broadcastb_epi8(0, a);
17052 assert_eq_m256i(r, _mm256_setzero_si256());
17053 let r = _mm256_maskz_broadcastb_epi8(0b11111111_11111111_11111111_11111111, a);
17054 let e = _mm256_set1_epi8(32);
17055 assert_eq_m256i(r, e);
17056 }
17057
17058 #[simd_test(enable = "avx512bw,avx512vl")]
17059 unsafe fn test_mm_mask_broadcastb_epi8() {
17060 let src = _mm_set1_epi8(1);
17061 let a = _mm_set_epi8(
17062 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17063 );
17064 let r = _mm_mask_broadcastb_epi8(src, 0, a);
17065 assert_eq_m128i(r, src);
17066 let r = _mm_mask_broadcastb_epi8(src, 0b11111111_11111111, a);
17067 let e = _mm_set1_epi8(32);
17068 assert_eq_m128i(r, e);
17069 }
17070
17071 #[simd_test(enable = "avx512bw,avx512vl")]
17072 unsafe fn test_mm_maskz_broadcastb_epi8() {
17073 let a = _mm_set_epi8(
17074 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17075 );
17076 let r = _mm_maskz_broadcastb_epi8(0, a);
17077 assert_eq_m128i(r, _mm_setzero_si128());
17078 let r = _mm_maskz_broadcastb_epi8(0b11111111_11111111, a);
17079 let e = _mm_set1_epi8(32);
17080 assert_eq_m128i(r, e);
17081 }
17082
17083 #[simd_test(enable = "avx512bw")]
17084 unsafe fn test_mm512_unpackhi_epi16() {
17085 #[rustfmt::skip]
17086 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17087 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17088 #[rustfmt::skip]
17089 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17090 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17091 let r = _mm512_unpackhi_epi16(a, b);
17092 #[rustfmt::skip]
17093 let e = _mm512_set_epi16(33, 1, 34, 2, 35, 3, 36, 4, 41, 9, 42, 10, 43, 11, 44, 12,
17094 49, 17, 50, 18, 51, 19, 52, 20, 57, 25, 58, 26, 59, 27, 60, 28);
17095 assert_eq_m512i(r, e);
17096 }
17097
17098 #[simd_test(enable = "avx512bw")]
17099 unsafe fn test_mm512_mask_unpackhi_epi16() {
17100 #[rustfmt::skip]
17101 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17102 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17103 #[rustfmt::skip]
17104 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17105 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17106 let r = _mm512_mask_unpackhi_epi16(a, 0, a, b);
17107 assert_eq_m512i(r, a);
17108 let r = _mm512_mask_unpackhi_epi16(a, 0b11111111_11111111_11111111_11111111, a, b);
17109 #[rustfmt::skip]
17110 let e = _mm512_set_epi16(33, 1, 34, 2, 35, 3, 36, 4, 41, 9, 42, 10, 43, 11, 44, 12,
17111 49, 17, 50, 18, 51, 19, 52, 20, 57, 25, 58, 26, 59, 27, 60, 28);
17112 assert_eq_m512i(r, e);
17113 }
17114
17115 #[simd_test(enable = "avx512bw")]
17116 unsafe fn test_mm512_maskz_unpackhi_epi16() {
17117 #[rustfmt::skip]
17118 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17119 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17120 #[rustfmt::skip]
17121 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17122 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17123 let r = _mm512_maskz_unpackhi_epi16(0, a, b);
17124 assert_eq_m512i(r, _mm512_setzero_si512());
17125 let r = _mm512_maskz_unpackhi_epi16(0b11111111_11111111_11111111_11111111, a, b);
17126 #[rustfmt::skip]
17127 let e = _mm512_set_epi16(33, 1, 34, 2, 35, 3, 36, 4, 41, 9, 42, 10, 43, 11, 44, 12,
17128 49, 17, 50, 18, 51, 19, 52, 20, 57, 25, 58, 26, 59, 27, 60, 28);
17129 assert_eq_m512i(r, e);
17130 }
17131
17132 #[simd_test(enable = "avx512bw,avx512vl")]
17133 unsafe fn test_mm256_mask_unpackhi_epi16() {
17134 let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17135 let b = _mm256_set_epi16(
17136 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17137 );
17138 let r = _mm256_mask_unpackhi_epi16(a, 0, a, b);
17139 assert_eq_m256i(r, a);
17140 let r = _mm256_mask_unpackhi_epi16(a, 0b11111111_11111111, a, b);
17141 let e = _mm256_set_epi16(33, 1, 34, 2, 35, 3, 36, 4, 41, 9, 42, 10, 43, 11, 44, 12);
17142 assert_eq_m256i(r, e);
17143 }
17144
17145 #[simd_test(enable = "avx512bw,avx512vl")]
17146 unsafe fn test_mm256_maskz_unpackhi_epi16() {
17147 let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17148 let b = _mm256_set_epi16(
17149 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17150 );
17151 let r = _mm256_maskz_unpackhi_epi16(0, a, b);
17152 assert_eq_m256i(r, _mm256_setzero_si256());
17153 let r = _mm256_maskz_unpackhi_epi16(0b11111111_11111111, a, b);
17154 let e = _mm256_set_epi16(33, 1, 34, 2, 35, 3, 36, 4, 41, 9, 42, 10, 43, 11, 44, 12);
17155 assert_eq_m256i(r, e);
17156 }
17157
17158 #[simd_test(enable = "avx512bw,avx512vl")]
17159 unsafe fn test_mm_mask_unpackhi_epi16() {
17160 let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
17161 let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
17162 let r = _mm_mask_unpackhi_epi16(a, 0, a, b);
17163 assert_eq_m128i(r, a);
17164 let r = _mm_mask_unpackhi_epi16(a, 0b11111111, a, b);
17165 let e = _mm_set_epi16(33, 1, 34, 2, 35, 3, 36, 4);
17166 assert_eq_m128i(r, e);
17167 }
17168
17169 #[simd_test(enable = "avx512bw,avx512vl")]
17170 unsafe fn test_mm_maskz_unpackhi_epi16() {
17171 let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
17172 let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
17173 let r = _mm_maskz_unpackhi_epi16(0, a, b);
17174 assert_eq_m128i(r, _mm_setzero_si128());
17175 let r = _mm_maskz_unpackhi_epi16(0b11111111, a, b);
17176 let e = _mm_set_epi16(33, 1, 34, 2, 35, 3, 36, 4);
17177 assert_eq_m128i(r, e);
17178 }
17179
17180 #[simd_test(enable = "avx512bw")]
17181 unsafe fn test_mm512_unpackhi_epi8() {
17182 #[rustfmt::skip]
17183 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17184 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17185 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17186 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17187 #[rustfmt::skip]
17188 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17189 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17190 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17191 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17192 let r = _mm512_unpackhi_epi8(a, b);
17193 #[rustfmt::skip]
17194 let e = _mm512_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8,
17195 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23, 88, 24,
17196 97, 33, 98, 34, 99, 35, 100, 36, 101, 37, 102, 38, 103, 39, 104, 40,
17197 113, 49, 114, 50, 115, 51, 116, 52, 117, 53, 118, 54, 119, 55, 120, 56);
17198 assert_eq_m512i(r, e);
17199 }
17200
17201 #[simd_test(enable = "avx512bw")]
17202 unsafe fn test_mm512_mask_unpackhi_epi8() {
17203 #[rustfmt::skip]
17204 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17205 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17206 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17207 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17208 #[rustfmt::skip]
17209 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17210 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17211 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17212 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17213 let r = _mm512_mask_unpackhi_epi8(a, 0, a, b);
17214 assert_eq_m512i(r, a);
17215 let r = _mm512_mask_unpackhi_epi8(
17216 a,
17217 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17218 a,
17219 b,
17220 );
17221 #[rustfmt::skip]
17222 let e = _mm512_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8,
17223 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23, 88, 24,
17224 97, 33, 98, 34, 99, 35, 100, 36, 101, 37, 102, 38, 103, 39, 104, 40,
17225 113, 49, 114, 50, 115, 51, 116, 52, 117, 53, 118, 54, 119, 55, 120, 56);
17226 assert_eq_m512i(r, e);
17227 }
17228
17229 #[simd_test(enable = "avx512bw")]
17230 unsafe fn test_mm512_maskz_unpackhi_epi8() {
17231 #[rustfmt::skip]
17232 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17233 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17234 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17235 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17236 #[rustfmt::skip]
17237 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17238 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17239 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17240 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17241 let r = _mm512_maskz_unpackhi_epi8(0, a, b);
17242 assert_eq_m512i(r, _mm512_setzero_si512());
17243 let r = _mm512_maskz_unpackhi_epi8(
17244 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17245 a,
17246 b,
17247 );
17248 #[rustfmt::skip]
17249 let e = _mm512_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8,
17250 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23, 88, 24,
17251 97, 33, 98, 34, 99, 35, 100, 36, 101, 37, 102, 38, 103, 39, 104, 40,
17252 113, 49, 114, 50, 115, 51, 116, 52, 117, 53, 118, 54, 119, 55, 120, 56);
17253 assert_eq_m512i(r, e);
17254 }
17255
17256 #[simd_test(enable = "avx512bw,avx512vl")]
17257 unsafe fn test_mm256_mask_unpackhi_epi8() {
17258 #[rustfmt::skip]
17259 let a = _mm256_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17260 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17261 #[rustfmt::skip]
17262 let b = _mm256_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17263 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96);
17264 let r = _mm256_mask_unpackhi_epi8(a, 0, a, b);
17265 assert_eq_m256i(r, a);
17266 let r = _mm256_mask_unpackhi_epi8(a, 0b11111111_11111111_11111111_11111111, a, b);
17267 #[rustfmt::skip]
17268 let e = _mm256_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8,
17269 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23, 88, 24);
17270 assert_eq_m256i(r, e);
17271 }
17272
17273 #[simd_test(enable = "avx512bw,avx512vl")]
17274 unsafe fn test_mm256_maskz_unpackhi_epi8() {
17275 #[rustfmt::skip]
17276 let a = _mm256_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17277 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17278 #[rustfmt::skip]
17279 let b = _mm256_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17280 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96);
17281 let r = _mm256_maskz_unpackhi_epi8(0, a, b);
17282 assert_eq_m256i(r, _mm256_setzero_si256());
17283 let r = _mm256_maskz_unpackhi_epi8(0b11111111_11111111_11111111_11111111, a, b);
17284 #[rustfmt::skip]
17285 let e = _mm256_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8,
17286 81, 17, 82, 18, 83, 19, 84, 20, 85, 21, 86, 22, 87, 23, 88, 24);
17287 assert_eq_m256i(r, e);
17288 }
17289
17290 #[simd_test(enable = "avx512bw,avx512vl")]
17291 unsafe fn test_mm_mask_unpackhi_epi8() {
17292 let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17293 let b = _mm_set_epi8(
17294 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17295 );
17296 let r = _mm_mask_unpackhi_epi8(a, 0, a, b);
17297 assert_eq_m128i(r, a);
17298 let r = _mm_mask_unpackhi_epi8(a, 0b11111111_11111111, a, b);
17299 let e = _mm_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8);
17300 assert_eq_m128i(r, e);
17301 }
17302
17303 #[simd_test(enable = "avx512bw,avx512vl")]
17304 unsafe fn test_mm_maskz_unpackhi_epi8() {
17305 let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17306 let b = _mm_set_epi8(
17307 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17308 );
17309 let r = _mm_maskz_unpackhi_epi8(0, a, b);
17310 assert_eq_m128i(r, _mm_setzero_si128());
17311 let r = _mm_maskz_unpackhi_epi8(0b11111111_11111111, a, b);
17312 let e = _mm_set_epi8(65, 1, 66, 2, 67, 3, 68, 4, 69, 5, 70, 6, 71, 7, 72, 8);
17313 assert_eq_m128i(r, e);
17314 }
17315
17316 #[simd_test(enable = "avx512bw")]
17317 unsafe fn test_mm512_unpacklo_epi16() {
17318 #[rustfmt::skip]
17319 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17320 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17321 #[rustfmt::skip]
17322 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17323 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17324 let r = _mm512_unpacklo_epi16(a, b);
17325 #[rustfmt::skip]
17326 let e = _mm512_set_epi16(37, 5, 38, 6, 39, 7, 40, 8, 45, 13, 46, 14, 47, 15, 48, 16,
17327 53, 21, 54, 22, 55, 23, 56, 24, 61, 29, 62, 30, 63, 31, 64, 32);
17328 assert_eq_m512i(r, e);
17329 }
17330
17331 #[simd_test(enable = "avx512bw")]
17332 unsafe fn test_mm512_mask_unpacklo_epi16() {
17333 #[rustfmt::skip]
17334 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17335 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17336 #[rustfmt::skip]
17337 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17338 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17339 let r = _mm512_mask_unpacklo_epi16(a, 0, a, b);
17340 assert_eq_m512i(r, a);
17341 let r = _mm512_mask_unpacklo_epi16(a, 0b11111111_11111111_11111111_11111111, a, b);
17342 #[rustfmt::skip]
17343 let e = _mm512_set_epi16(37, 5, 38, 6, 39, 7, 40, 8, 45, 13, 46, 14, 47, 15, 48, 16,
17344 53, 21, 54, 22, 55, 23, 56, 24, 61, 29, 62, 30, 63, 31, 64, 32);
17345 assert_eq_m512i(r, e);
17346 }
17347
17348 #[simd_test(enable = "avx512bw")]
17349 unsafe fn test_mm512_maskz_unpacklo_epi16() {
17350 #[rustfmt::skip]
17351 let a = _mm512_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17352 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17353 #[rustfmt::skip]
17354 let b = _mm512_set_epi16(33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17355 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17356 let r = _mm512_maskz_unpacklo_epi16(0, a, b);
17357 assert_eq_m512i(r, _mm512_setzero_si512());
17358 let r = _mm512_maskz_unpacklo_epi16(0b11111111_11111111_11111111_11111111, a, b);
17359 #[rustfmt::skip]
17360 let e = _mm512_set_epi16(37, 5, 38, 6, 39, 7, 40, 8, 45, 13, 46, 14, 47, 15, 48, 16,
17361 53, 21, 54, 22, 55, 23, 56, 24, 61, 29, 62, 30, 63, 31, 64, 32);
17362 assert_eq_m512i(r, e);
17363 }
17364
17365 #[simd_test(enable = "avx512bw,avx512vl")]
17366 unsafe fn test_mm256_mask_unpacklo_epi16() {
17367 let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17368 let b = _mm256_set_epi16(
17369 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17370 );
17371 let r = _mm256_mask_unpacklo_epi16(a, 0, a, b);
17372 assert_eq_m256i(r, a);
17373 let r = _mm256_mask_unpacklo_epi16(a, 0b11111111_11111111, a, b);
17374 let e = _mm256_set_epi16(37, 5, 38, 6, 39, 7, 40, 8, 45, 13, 46, 14, 47, 15, 48, 16);
17375 assert_eq_m256i(r, e);
17376 }
17377
17378 #[simd_test(enable = "avx512bw,avx512vl")]
17379 unsafe fn test_mm256_maskz_unpacklo_epi16() {
17380 let a = _mm256_set_epi16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17381 let b = _mm256_set_epi16(
17382 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17383 );
17384 let r = _mm256_maskz_unpacklo_epi16(0, a, b);
17385 assert_eq_m256i(r, _mm256_setzero_si256());
17386 let r = _mm256_maskz_unpacklo_epi16(0b11111111_11111111, a, b);
17387 let e = _mm256_set_epi16(37, 5, 38, 6, 39, 7, 40, 8, 45, 13, 46, 14, 47, 15, 48, 16);
17388 assert_eq_m256i(r, e);
17389 }
17390
17391 #[simd_test(enable = "avx512bw,avx512vl")]
17392 unsafe fn test_mm_mask_unpacklo_epi16() {
17393 let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
17394 let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
17395 let r = _mm_mask_unpacklo_epi16(a, 0, a, b);
17396 assert_eq_m128i(r, a);
17397 let r = _mm_mask_unpacklo_epi16(a, 0b11111111, a, b);
17398 let e = _mm_set_epi16(37, 5, 38, 6, 39, 7, 40, 8);
17399 assert_eq_m128i(r, e);
17400 }
17401
17402 #[simd_test(enable = "avx512bw,avx512vl")]
17403 unsafe fn test_mm_maskz_unpacklo_epi16() {
17404 let a = _mm_set_epi16(1, 2, 3, 4, 5, 6, 7, 8);
17405 let b = _mm_set_epi16(33, 34, 35, 36, 37, 38, 39, 40);
17406 let r = _mm_maskz_unpacklo_epi16(0, a, b);
17407 assert_eq_m128i(r, _mm_setzero_si128());
17408 let r = _mm_maskz_unpacklo_epi16(0b11111111, a, b);
17409 let e = _mm_set_epi16(37, 5, 38, 6, 39, 7, 40, 8);
17410 assert_eq_m128i(r, e);
17411 }
17412
17413 #[simd_test(enable = "avx512bw")]
17414 unsafe fn test_mm512_unpacklo_epi8() {
17415 #[rustfmt::skip]
17416 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17417 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17418 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17419 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17420 #[rustfmt::skip]
17421 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17422 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17423 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17424 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17425 let r = _mm512_unpacklo_epi8(a, b);
17426 #[rustfmt::skip]
17427 let e = _mm512_set_epi8(73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17428 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31, 96, 32,
17429 105, 41, 106, 42, 107, 43, 108, 44, 109, 45, 110, 46, 111, 47, 112, 48,
17430 121, 57, 122, 58, 123, 59, 124, 60, 125, 61, 126, 62, 127, 63, 0, 64);
17431 assert_eq_m512i(r, e);
17432 }
17433
17434 #[simd_test(enable = "avx512bw")]
17435 unsafe fn test_mm512_mask_unpacklo_epi8() {
17436 #[rustfmt::skip]
17437 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17438 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17439 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17440 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17441 #[rustfmt::skip]
17442 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17443 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17444 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17445 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17446 let r = _mm512_mask_unpacklo_epi8(a, 0, a, b);
17447 assert_eq_m512i(r, a);
17448 let r = _mm512_mask_unpacklo_epi8(
17449 a,
17450 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17451 a,
17452 b,
17453 );
17454 #[rustfmt::skip]
17455 let e = _mm512_set_epi8(73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17456 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31, 96, 32,
17457 105, 41, 106, 42, 107, 43, 108, 44, 109, 45, 110, 46, 111, 47, 112, 48,
17458 121, 57, 122, 58, 123, 59, 124, 60, 125, 61, 126, 62, 127, 63, 0, 64);
17459 assert_eq_m512i(r, e);
17460 }
17461
17462 #[simd_test(enable = "avx512bw")]
17463 unsafe fn test_mm512_maskz_unpacklo_epi8() {
17464 #[rustfmt::skip]
17465 let a = _mm512_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17466 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
17467 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
17468 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
17469 #[rustfmt::skip]
17470 let b = _mm512_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17471 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
17472 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
17473 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 0);
17474 let r = _mm512_maskz_unpacklo_epi8(0, a, b);
17475 assert_eq_m512i(r, _mm512_setzero_si512());
17476 let r = _mm512_maskz_unpacklo_epi8(
17477 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17478 a,
17479 b,
17480 );
17481 #[rustfmt::skip]
17482 let e = _mm512_set_epi8(73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17483 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31, 96, 32,
17484 105, 41, 106, 42, 107, 43, 108, 44, 109, 45, 110, 46, 111, 47, 112, 48,
17485 121, 57, 122, 58, 123, 59, 124, 60, 125, 61, 126, 62, 127, 63, 0, 64);
17486 assert_eq_m512i(r, e);
17487 }
17488
17489 #[simd_test(enable = "avx512bw,avx512vl")]
17490 unsafe fn test_mm256_mask_unpacklo_epi8() {
17491 #[rustfmt::skip]
17492 let a = _mm256_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17493 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17494 #[rustfmt::skip]
17495 let b = _mm256_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17496 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96);
17497 let r = _mm256_mask_unpacklo_epi8(a, 0, a, b);
17498 assert_eq_m256i(r, a);
17499 let r = _mm256_mask_unpacklo_epi8(a, 0b11111111_11111111_11111111_11111111, a, b);
17500 #[rustfmt::skip]
17501 let e = _mm256_set_epi8(73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17502 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31, 96, 32);
17503 assert_eq_m256i(r, e);
17504 }
17505
17506 #[simd_test(enable = "avx512bw,avx512vl")]
17507 unsafe fn test_mm256_maskz_unpacklo_epi8() {
17508 #[rustfmt::skip]
17509 let a = _mm256_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17510 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
17511 #[rustfmt::skip]
17512 let b = _mm256_set_epi8(65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17513 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96);
17514 let r = _mm256_maskz_unpacklo_epi8(0, a, b);
17515 assert_eq_m256i(r, _mm256_setzero_si256());
17516 let r = _mm256_maskz_unpacklo_epi8(0b11111111_11111111_11111111_11111111, a, b);
17517 #[rustfmt::skip]
17518 let e = _mm256_set_epi8(73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17519 89, 25, 90, 26, 91, 27, 92, 28, 93, 29, 94, 30, 95, 31, 96, 32);
17520 assert_eq_m256i(r, e);
17521 }
17522
17523 #[simd_test(enable = "avx512bw,avx512vl")]
17524 unsafe fn test_mm_mask_unpacklo_epi8() {
17525 let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17526 let b = _mm_set_epi8(
17527 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17528 );
17529 let r = _mm_mask_unpacklo_epi8(a, 0, a, b);
17530 assert_eq_m128i(r, a);
17531 let r = _mm_mask_unpacklo_epi8(a, 0b11111111_11111111, a, b);
17532 let e = _mm_set_epi8(
17533 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17534 );
17535 assert_eq_m128i(r, e);
17536 }
17537
17538 #[simd_test(enable = "avx512bw,avx512vl")]
17539 unsafe fn test_mm_maskz_unpacklo_epi8() {
17540 let a = _mm_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
17541 let b = _mm_set_epi8(
17542 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,
17543 );
17544 let r = _mm_maskz_unpacklo_epi8(0, a, b);
17545 assert_eq_m128i(r, _mm_setzero_si128());
17546 let r = _mm_maskz_unpacklo_epi8(0b11111111_11111111, a, b);
17547 let e = _mm_set_epi8(
17548 73, 9, 74, 10, 75, 11, 76, 12, 77, 13, 78, 14, 79, 15, 80, 16,
17549 );
17550 assert_eq_m128i(r, e);
17551 }
17552
17553 #[simd_test(enable = "avx512bw")]
17554 unsafe fn test_mm512_mask_mov_epi16() {
17555 let src = _mm512_set1_epi16(1);
17556 let a = _mm512_set1_epi16(2);
17557 let r = _mm512_mask_mov_epi16(src, 0, a);
17558 assert_eq_m512i(r, src);
17559 let r = _mm512_mask_mov_epi16(src, 0b11111111_11111111_11111111_11111111, a);
17560 assert_eq_m512i(r, a);
17561 }
17562
17563 #[simd_test(enable = "avx512bw")]
17564 unsafe fn test_mm512_maskz_mov_epi16() {
17565 let a = _mm512_set1_epi16(2);
17566 let r = _mm512_maskz_mov_epi16(0, a);
17567 assert_eq_m512i(r, _mm512_setzero_si512());
17568 let r = _mm512_maskz_mov_epi16(0b11111111_11111111_11111111_11111111, a);
17569 assert_eq_m512i(r, a);
17570 }
17571
17572 #[simd_test(enable = "avx512bw,avx512vl")]
17573 unsafe fn test_mm256_mask_mov_epi16() {
17574 let src = _mm256_set1_epi16(1);
17575 let a = _mm256_set1_epi16(2);
17576 let r = _mm256_mask_mov_epi16(src, 0, a);
17577 assert_eq_m256i(r, src);
17578 let r = _mm256_mask_mov_epi16(src, 0b11111111_11111111, a);
17579 assert_eq_m256i(r, a);
17580 }
17581
17582 #[simd_test(enable = "avx512bw,avx512vl")]
17583 unsafe fn test_mm256_maskz_mov_epi16() {
17584 let a = _mm256_set1_epi16(2);
17585 let r = _mm256_maskz_mov_epi16(0, a);
17586 assert_eq_m256i(r, _mm256_setzero_si256());
17587 let r = _mm256_maskz_mov_epi16(0b11111111_11111111, a);
17588 assert_eq_m256i(r, a);
17589 }
17590
17591 #[simd_test(enable = "avx512bw,avx512vl")]
17592 unsafe fn test_mm_mask_mov_epi16() {
17593 let src = _mm_set1_epi16(1);
17594 let a = _mm_set1_epi16(2);
17595 let r = _mm_mask_mov_epi16(src, 0, a);
17596 assert_eq_m128i(r, src);
17597 let r = _mm_mask_mov_epi16(src, 0b11111111, a);
17598 assert_eq_m128i(r, a);
17599 }
17600
17601 #[simd_test(enable = "avx512bw,avx512vl")]
17602 unsafe fn test_mm_maskz_mov_epi16() {
17603 let a = _mm_set1_epi16(2);
17604 let r = _mm_maskz_mov_epi16(0, a);
17605 assert_eq_m128i(r, _mm_setzero_si128());
17606 let r = _mm_maskz_mov_epi16(0b11111111, a);
17607 assert_eq_m128i(r, a);
17608 }
17609
17610 #[simd_test(enable = "avx512bw")]
17611 unsafe fn test_mm512_mask_mov_epi8() {
17612 let src = _mm512_set1_epi8(1);
17613 let a = _mm512_set1_epi8(2);
17614 let r = _mm512_mask_mov_epi8(src, 0, a);
17615 assert_eq_m512i(r, src);
17616 let r = _mm512_mask_mov_epi8(
17617 src,
17618 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17619 a,
17620 );
17621 assert_eq_m512i(r, a);
17622 }
17623
17624 #[simd_test(enable = "avx512bw")]
17625 unsafe fn test_mm512_maskz_mov_epi8() {
17626 let a = _mm512_set1_epi8(2);
17627 let r = _mm512_maskz_mov_epi8(0, a);
17628 assert_eq_m512i(r, _mm512_setzero_si512());
17629 let r = _mm512_maskz_mov_epi8(
17630 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17631 a,
17632 );
17633 assert_eq_m512i(r, a);
17634 }
17635
17636 #[simd_test(enable = "avx512bw,avx512vl")]
17637 unsafe fn test_mm256_mask_mov_epi8() {
17638 let src = _mm256_set1_epi8(1);
17639 let a = _mm256_set1_epi8(2);
17640 let r = _mm256_mask_mov_epi8(src, 0, a);
17641 assert_eq_m256i(r, src);
17642 let r = _mm256_mask_mov_epi8(src, 0b11111111_11111111_11111111_11111111, a);
17643 assert_eq_m256i(r, a);
17644 }
17645
17646 #[simd_test(enable = "avx512bw,avx512vl")]
17647 unsafe fn test_mm256_maskz_mov_epi8() {
17648 let a = _mm256_set1_epi8(2);
17649 let r = _mm256_maskz_mov_epi8(0, a);
17650 assert_eq_m256i(r, _mm256_setzero_si256());
17651 let r = _mm256_maskz_mov_epi8(0b11111111_11111111_11111111_11111111, a);
17652 assert_eq_m256i(r, a);
17653 }
17654
17655 #[simd_test(enable = "avx512bw,avx512vl")]
17656 unsafe fn test_mm_mask_mov_epi8() {
17657 let src = _mm_set1_epi8(1);
17658 let a = _mm_set1_epi8(2);
17659 let r = _mm_mask_mov_epi8(src, 0, a);
17660 assert_eq_m128i(r, src);
17661 let r = _mm_mask_mov_epi8(src, 0b11111111_11111111, a);
17662 assert_eq_m128i(r, a);
17663 }
17664
17665 #[simd_test(enable = "avx512bw,avx512vl")]
17666 unsafe fn test_mm_maskz_mov_epi8() {
17667 let a = _mm_set1_epi8(2);
17668 let r = _mm_maskz_mov_epi8(0, a);
17669 assert_eq_m128i(r, _mm_setzero_si128());
17670 let r = _mm_maskz_mov_epi8(0b11111111_11111111, a);
17671 assert_eq_m128i(r, a);
17672 }
17673
17674 #[simd_test(enable = "avx512bw")]
17675 unsafe fn test_mm512_mask_set1_epi16() {
17676 let src = _mm512_set1_epi16(2);
17677 let a: i16 = 11;
17678 let r = _mm512_mask_set1_epi16(src, 0, a);
17679 assert_eq_m512i(r, src);
17680 let r = _mm512_mask_set1_epi16(src, 0b11111111_11111111_11111111_11111111, a);
17681 let e = _mm512_set1_epi16(11);
17682 assert_eq_m512i(r, e);
17683 }
17684
17685 #[simd_test(enable = "avx512bw")]
17686 unsafe fn test_mm512_maskz_set1_epi16() {
17687 let a: i16 = 11;
17688 let r = _mm512_maskz_set1_epi16(0, a);
17689 assert_eq_m512i(r, _mm512_setzero_si512());
17690 let r = _mm512_maskz_set1_epi16(0b11111111_11111111_11111111_11111111, a);
17691 let e = _mm512_set1_epi16(11);
17692 assert_eq_m512i(r, e);
17693 }
17694
17695 #[simd_test(enable = "avx512bw,avx512vl")]
17696 unsafe fn test_mm256_mask_set1_epi16() {
17697 let src = _mm256_set1_epi16(2);
17698 let a: i16 = 11;
17699 let r = _mm256_mask_set1_epi16(src, 0, a);
17700 assert_eq_m256i(r, src);
17701 let r = _mm256_mask_set1_epi16(src, 0b11111111_11111111, a);
17702 let e = _mm256_set1_epi16(11);
17703 assert_eq_m256i(r, e);
17704 }
17705
17706 #[simd_test(enable = "avx512bw,avx512vl")]
17707 unsafe fn test_mm256_maskz_set1_epi16() {
17708 let a: i16 = 11;
17709 let r = _mm256_maskz_set1_epi16(0, a);
17710 assert_eq_m256i(r, _mm256_setzero_si256());
17711 let r = _mm256_maskz_set1_epi16(0b11111111_11111111, a);
17712 let e = _mm256_set1_epi16(11);
17713 assert_eq_m256i(r, e);
17714 }
17715
17716 #[simd_test(enable = "avx512bw,avx512vl")]
17717 unsafe fn test_mm_mask_set1_epi16() {
17718 let src = _mm_set1_epi16(2);
17719 let a: i16 = 11;
17720 let r = _mm_mask_set1_epi16(src, 0, a);
17721 assert_eq_m128i(r, src);
17722 let r = _mm_mask_set1_epi16(src, 0b11111111, a);
17723 let e = _mm_set1_epi16(11);
17724 assert_eq_m128i(r, e);
17725 }
17726
17727 #[simd_test(enable = "avx512bw,avx512vl")]
17728 unsafe fn test_mm_maskz_set1_epi16() {
17729 let a: i16 = 11;
17730 let r = _mm_maskz_set1_epi16(0, a);
17731 assert_eq_m128i(r, _mm_setzero_si128());
17732 let r = _mm_maskz_set1_epi16(0b11111111, a);
17733 let e = _mm_set1_epi16(11);
17734 assert_eq_m128i(r, e);
17735 }
17736
17737 #[simd_test(enable = "avx512bw")]
17738 unsafe fn test_mm512_mask_set1_epi8() {
17739 let src = _mm512_set1_epi8(2);
17740 let a: i8 = 11;
17741 let r = _mm512_mask_set1_epi8(src, 0, a);
17742 assert_eq_m512i(r, src);
17743 let r = _mm512_mask_set1_epi8(
17744 src,
17745 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17746 a,
17747 );
17748 let e = _mm512_set1_epi8(11);
17749 assert_eq_m512i(r, e);
17750 }
17751
17752 #[simd_test(enable = "avx512bw")]
17753 unsafe fn test_mm512_maskz_set1_epi8() {
17754 let a: i8 = 11;
17755 let r = _mm512_maskz_set1_epi8(0, a);
17756 assert_eq_m512i(r, _mm512_setzero_si512());
17757 let r = _mm512_maskz_set1_epi8(
17758 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
17759 a,
17760 );
17761 let e = _mm512_set1_epi8(11);
17762 assert_eq_m512i(r, e);
17763 }
17764
17765 #[simd_test(enable = "avx512bw,avx512vl")]
17766 unsafe fn test_mm256_mask_set1_epi8() {
17767 let src = _mm256_set1_epi8(2);
17768 let a: i8 = 11;
17769 let r = _mm256_mask_set1_epi8(src, 0, a);
17770 assert_eq_m256i(r, src);
17771 let r = _mm256_mask_set1_epi8(src, 0b11111111_11111111_11111111_11111111, a);
17772 let e = _mm256_set1_epi8(11);
17773 assert_eq_m256i(r, e);
17774 }
17775
17776 #[simd_test(enable = "avx512bw,avx512vl")]
17777 unsafe fn test_mm256_maskz_set1_epi8() {
17778 let a: i8 = 11;
17779 let r = _mm256_maskz_set1_epi8(0, a);
17780 assert_eq_m256i(r, _mm256_setzero_si256());
17781 let r = _mm256_maskz_set1_epi8(0b11111111_11111111_11111111_11111111, a);
17782 let e = _mm256_set1_epi8(11);
17783 assert_eq_m256i(r, e);
17784 }
17785
17786 #[simd_test(enable = "avx512bw,avx512vl")]
17787 unsafe fn test_mm_mask_set1_epi8() {
17788 let src = _mm_set1_epi8(2);
17789 let a: i8 = 11;
17790 let r = _mm_mask_set1_epi8(src, 0, a);
17791 assert_eq_m128i(r, src);
17792 let r = _mm_mask_set1_epi8(src, 0b11111111_11111111, a);
17793 let e = _mm_set1_epi8(11);
17794 assert_eq_m128i(r, e);
17795 }
17796
17797 #[simd_test(enable = "avx512bw,avx512vl")]
17798 unsafe fn test_mm_maskz_set1_epi8() {
17799 let a: i8 = 11;
17800 let r = _mm_maskz_set1_epi8(0, a);
17801 assert_eq_m128i(r, _mm_setzero_si128());
17802 let r = _mm_maskz_set1_epi8(0b11111111_11111111, a);
17803 let e = _mm_set1_epi8(11);
17804 assert_eq_m128i(r, e);
17805 }
17806
17807 #[simd_test(enable = "avx512bw")]
17808 unsafe fn test_mm512_shufflelo_epi16() {
17809 #[rustfmt::skip]
17810 let a = _mm512_set_epi16(
17811 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17812 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17813 );
17814 #[rustfmt::skip]
17815 let e = _mm512_set_epi16(
17816 0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12,
17817 16, 17, 18, 19, 23, 22, 22, 20, 24, 25, 26, 27, 31, 30, 30, 28,
17818 );
17819 let r = _mm512_shufflelo_epi16::<0b00_01_01_11>(a);
17820 assert_eq_m512i(r, e);
17821 }
17822
17823 #[simd_test(enable = "avx512bw")]
17824 unsafe fn test_mm512_mask_shufflelo_epi16() {
17825 #[rustfmt::skip]
17826 let a = _mm512_set_epi16(
17827 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17828 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17829 );
17830 let r = _mm512_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
17831 assert_eq_m512i(r, a);
17832 let r = _mm512_mask_shufflelo_epi16::<0b00_01_01_11>(
17833 a,
17834 0b11111111_11111111_11111111_11111111,
17835 a,
17836 );
17837 #[rustfmt::skip]
17838 let e = _mm512_set_epi16(
17839 0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12,
17840 16, 17, 18, 19, 23, 22, 22, 20, 24, 25, 26, 27, 31, 30, 30, 28,
17841 );
17842 assert_eq_m512i(r, e);
17843 }
17844
17845 #[simd_test(enable = "avx512bw")]
17846 unsafe fn test_mm512_maskz_shufflelo_epi16() {
17847 #[rustfmt::skip]
17848 let a = _mm512_set_epi16(
17849 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17850 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17851 );
17852 let r = _mm512_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
17853 assert_eq_m512i(r, _mm512_setzero_si512());
17854 let r =
17855 _mm512_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111_11111111_11111111_11111111, a);
17856 #[rustfmt::skip]
17857 let e = _mm512_set_epi16(
17858 0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12,
17859 16, 17, 18, 19, 23, 22, 22, 20, 24, 25, 26, 27, 31, 30, 30, 28,
17860 );
17861 assert_eq_m512i(r, e);
17862 }
17863
17864 #[simd_test(enable = "avx512bw,avx512vl")]
17865 unsafe fn test_mm256_mask_shufflelo_epi16() {
17866 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
17867 let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
17868 assert_eq_m256i(r, a);
17869 let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0b11111111_11111111, a);
17870 let e = _mm256_set_epi16(0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12);
17871 assert_eq_m256i(r, e);
17872 }
17873
17874 #[simd_test(enable = "avx512bw,avx512vl")]
17875 unsafe fn test_mm256_maskz_shufflelo_epi16() {
17876 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
17877 let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
17878 assert_eq_m256i(r, _mm256_setzero_si256());
17879 let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111_11111111, a);
17880 let e = _mm256_set_epi16(0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12);
17881 assert_eq_m256i(r, e);
17882 }
17883
17884 #[simd_test(enable = "avx512bw,avx512vl")]
17885 unsafe fn test_mm_mask_shufflelo_epi16() {
17886 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
17887 let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a);
17888 assert_eq_m128i(r, a);
17889 let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0b11111111, a);
17890 let e = _mm_set_epi16(0, 1, 2, 3, 7, 6, 6, 4);
17891 assert_eq_m128i(r, e);
17892 }
17893
17894 #[simd_test(enable = "avx512bw,avx512vl")]
17895 unsafe fn test_mm_maskz_shufflelo_epi16() {
17896 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
17897 let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a);
17898 assert_eq_m128i(r, _mm_setzero_si128());
17899 let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111, a);
17900 let e = _mm_set_epi16(0, 1, 2, 3, 7, 6, 6, 4);
17901 assert_eq_m128i(r, e);
17902 }
17903
17904 #[simd_test(enable = "avx512bw")]
17905 unsafe fn test_mm512_shufflehi_epi16() {
17906 #[rustfmt::skip]
17907 let a = _mm512_set_epi16(
17908 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17909 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17910 );
17911 #[rustfmt::skip]
17912 let e = _mm512_set_epi16(
17913 3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15,
17914 19, 18, 18, 16, 20, 21, 22, 23, 27, 26, 26, 24, 28, 29, 30, 31,
17915 );
17916 let r = _mm512_shufflehi_epi16::<0b00_01_01_11>(a);
17917 assert_eq_m512i(r, e);
17918 }
17919
17920 #[simd_test(enable = "avx512bw")]
17921 unsafe fn test_mm512_mask_shufflehi_epi16() {
17922 #[rustfmt::skip]
17923 let a = _mm512_set_epi16(
17924 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17925 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17926 );
17927 let r = _mm512_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
17928 assert_eq_m512i(r, a);
17929 let r = _mm512_mask_shufflehi_epi16::<0b00_01_01_11>(
17930 a,
17931 0b11111111_11111111_11111111_11111111,
17932 a,
17933 );
17934 #[rustfmt::skip]
17935 let e = _mm512_set_epi16(
17936 3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15,
17937 19, 18, 18, 16, 20, 21, 22, 23, 27, 26, 26, 24, 28, 29, 30, 31,
17938 );
17939 assert_eq_m512i(r, e);
17940 }
17941
17942 #[simd_test(enable = "avx512bw")]
17943 unsafe fn test_mm512_maskz_shufflehi_epi16() {
17944 #[rustfmt::skip]
17945 let a = _mm512_set_epi16(
17946 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17947 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
17948 );
17949 let r = _mm512_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
17950 assert_eq_m512i(r, _mm512_setzero_si512());
17951 let r =
17952 _mm512_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111_11111111_11111111_11111111, a);
17953 #[rustfmt::skip]
17954 let e = _mm512_set_epi16(
17955 3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15,
17956 19, 18, 18, 16, 20, 21, 22, 23, 27, 26, 26, 24, 28, 29, 30, 31,
17957 );
17958 assert_eq_m512i(r, e);
17959 }
17960
17961 #[simd_test(enable = "avx512bw,avx512vl")]
17962 unsafe fn test_mm256_mask_shufflehi_epi16() {
17963 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
17964 let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
17965 assert_eq_m256i(r, a);
17966 let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0b11111111_11111111, a);
17967 let e = _mm256_set_epi16(3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15);
17968 assert_eq_m256i(r, e);
17969 }
17970
17971 #[simd_test(enable = "avx512bw,avx512vl")]
17972 unsafe fn test_mm256_maskz_shufflehi_epi16() {
17973 let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
17974 let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
17975 assert_eq_m256i(r, _mm256_setzero_si256());
17976 let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111_11111111, a);
17977 let e = _mm256_set_epi16(3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15);
17978 assert_eq_m256i(r, e);
17979 }
17980
17981 #[simd_test(enable = "avx512bw,avx512vl")]
17982 unsafe fn test_mm_mask_shufflehi_epi16() {
17983 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
17984 let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a);
17985 assert_eq_m128i(r, a);
17986 let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0b11111111, a);
17987 let e = _mm_set_epi16(3, 2, 2, 0, 4, 5, 6, 7);
17988 assert_eq_m128i(r, e);
17989 }
17990
17991 #[simd_test(enable = "avx512bw,avx512vl")]
17992 unsafe fn test_mm_maskz_shufflehi_epi16() {
17993 let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7);
17994 let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a);
17995 assert_eq_m128i(r, _mm_setzero_si128());
17996 let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111, a);
17997 let e = _mm_set_epi16(3, 2, 2, 0, 4, 5, 6, 7);
17998 assert_eq_m128i(r, e);
17999 }
18000
18001 #[simd_test(enable = "avx512bw")]
18002 unsafe fn test_mm512_shuffle_epi8() {
18003 #[rustfmt::skip]
18004 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
18005 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
18006 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
18007 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63);
18008 let b = _mm512_set1_epi8(1);
18009 let r = _mm512_shuffle_epi8(a, b);
18010 #[rustfmt::skip]
18011 let e = _mm512_set_epi8(14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18012 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30,
18013 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46,
18014 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62);
18015 assert_eq_m512i(r, e);
18016 }
18017
18018 #[simd_test(enable = "avx512bw")]
18019 unsafe fn test_mm512_mask_shuffle_epi8() {
18020 #[rustfmt::skip]
18021 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
18022 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
18023 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
18024 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63);
18025 let b = _mm512_set1_epi8(1);
18026 let r = _mm512_mask_shuffle_epi8(a, 0, a, b);
18027 assert_eq_m512i(r, a);
18028 let r = _mm512_mask_shuffle_epi8(
18029 a,
18030 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
18031 a,
18032 b,
18033 );
18034 #[rustfmt::skip]
18035 let e = _mm512_set_epi8(14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18036 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30,
18037 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46,
18038 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62);
18039 assert_eq_m512i(r, e);
18040 }
18041
18042 #[simd_test(enable = "avx512bw")]
18043 unsafe fn test_mm512_maskz_shuffle_epi8() {
18044 #[rustfmt::skip]
18045 let a = _mm512_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
18046 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
18047 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
18048 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63);
18049 let b = _mm512_set1_epi8(1);
18050 let r = _mm512_maskz_shuffle_epi8(0, a, b);
18051 assert_eq_m512i(r, _mm512_setzero_si512());
18052 let r = _mm512_maskz_shuffle_epi8(
18053 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
18054 a,
18055 b,
18056 );
18057 #[rustfmt::skip]
18058 let e = _mm512_set_epi8(14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18059 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30,
18060 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46, 46,
18061 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62, 62);
18062 assert_eq_m512i(r, e);
18063 }
18064
18065 #[simd_test(enable = "avx512bw,avx512vl")]
18066 unsafe fn test_mm256_mask_shuffle_epi8() {
18067 #[rustfmt::skip]
18068 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
18069 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
18070 let b = _mm256_set1_epi8(1);
18071 let r = _mm256_mask_shuffle_epi8(a, 0, a, b);
18072 assert_eq_m256i(r, a);
18073 let r = _mm256_mask_shuffle_epi8(a, 0b11111111_11111111_11111111_11111111, a, b);
18074 #[rustfmt::skip]
18075 let e = _mm256_set_epi8(14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18076 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30);
18077 assert_eq_m256i(r, e);
18078 }
18079
18080 #[simd_test(enable = "avx512bw,avx512vl")]
18081 unsafe fn test_mm256_maskz_shuffle_epi8() {
18082 #[rustfmt::skip]
18083 let a = _mm256_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
18084 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
18085 let b = _mm256_set1_epi8(1);
18086 let r = _mm256_maskz_shuffle_epi8(0, a, b);
18087 assert_eq_m256i(r, _mm256_setzero_si256());
18088 let r = _mm256_maskz_shuffle_epi8(0b11111111_11111111_11111111_11111111, a, b);
18089 #[rustfmt::skip]
18090 let e = _mm256_set_epi8(14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18091 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30);
18092 assert_eq_m256i(r, e);
18093 }
18094
18095 #[simd_test(enable = "avx512bw,avx512vl")]
18096 unsafe fn test_mm_mask_shuffle_epi8() {
18097 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
18098 let b = _mm_set1_epi8(1);
18099 let r = _mm_mask_shuffle_epi8(a, 0, a, b);
18100 assert_eq_m128i(r, a);
18101 let r = _mm_mask_shuffle_epi8(a, 0b11111111_11111111, a, b);
18102 let e = _mm_set_epi8(
18103 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18104 );
18105 assert_eq_m128i(r, e);
18106 }
18107
18108 #[simd_test(enable = "avx512bw,avx512vl")]
18109 unsafe fn test_mm_maskz_shuffle_epi8() {
18110 #[rustfmt::skip]
18111 let a = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
18112 let b = _mm_set1_epi8(1);
18113 let r = _mm_maskz_shuffle_epi8(0, a, b);
18114 assert_eq_m128i(r, _mm_setzero_si128());
18115 let r = _mm_maskz_shuffle_epi8(0b11111111_11111111, a, b);
18116 let e = _mm_set_epi8(
18117 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14,
18118 );
18119 assert_eq_m128i(r, e);
18120 }
18121
18122 #[simd_test(enable = "avx512bw")]
18123 unsafe fn test_mm512_test_epi16_mask() {
18124 let a = _mm512_set1_epi16(1 << 0);
18125 let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
18126 let r = _mm512_test_epi16_mask(a, b);
18127 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18128 assert_eq!(r, e);
18129 }
18130
18131 #[simd_test(enable = "avx512bw")]
18132 unsafe fn test_mm512_mask_test_epi16_mask() {
18133 let a = _mm512_set1_epi16(1 << 0);
18134 let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
18135 let r = _mm512_mask_test_epi16_mask(0, a, b);
18136 assert_eq!(r, 0);
18137 let r = _mm512_mask_test_epi16_mask(0b11111111_11111111_11111111_11111111, a, b);
18138 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18139 assert_eq!(r, e);
18140 }
18141
18142 #[simd_test(enable = "avx512bw,avx512vl")]
18143 unsafe fn test_mm256_test_epi16_mask() {
18144 let a = _mm256_set1_epi16(1 << 0);
18145 let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
18146 let r = _mm256_test_epi16_mask(a, b);
18147 let e: __mmask16 = 0b11111111_11111111;
18148 assert_eq!(r, e);
18149 }
18150
18151 #[simd_test(enable = "avx512bw,avx512vl")]
18152 unsafe fn test_mm256_mask_test_epi16_mask() {
18153 let a = _mm256_set1_epi16(1 << 0);
18154 let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
18155 let r = _mm256_mask_test_epi16_mask(0, a, b);
18156 assert_eq!(r, 0);
18157 let r = _mm256_mask_test_epi16_mask(0b11111111_11111111, a, b);
18158 let e: __mmask16 = 0b11111111_11111111;
18159 assert_eq!(r, e);
18160 }
18161
18162 #[simd_test(enable = "avx512bw,avx512vl")]
18163 unsafe fn test_mm_test_epi16_mask() {
18164 let a = _mm_set1_epi16(1 << 0);
18165 let b = _mm_set1_epi16(1 << 0 | 1 << 1);
18166 let r = _mm_test_epi16_mask(a, b);
18167 let e: __mmask8 = 0b11111111;
18168 assert_eq!(r, e);
18169 }
18170
18171 #[simd_test(enable = "avx512bw,avx512vl")]
18172 unsafe fn test_mm_mask_test_epi16_mask() {
18173 let a = _mm_set1_epi16(1 << 0);
18174 let b = _mm_set1_epi16(1 << 0 | 1 << 1);
18175 let r = _mm_mask_test_epi16_mask(0, a, b);
18176 assert_eq!(r, 0);
18177 let r = _mm_mask_test_epi16_mask(0b11111111, a, b);
18178 let e: __mmask8 = 0b11111111;
18179 assert_eq!(r, e);
18180 }
18181
18182 #[simd_test(enable = "avx512bw")]
18183 unsafe fn test_mm512_test_epi8_mask() {
18184 let a = _mm512_set1_epi8(1 << 0);
18185 let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
18186 let r = _mm512_test_epi8_mask(a, b);
18187 let e: __mmask64 =
18188 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18189 assert_eq!(r, e);
18190 }
18191
18192 #[simd_test(enable = "avx512bw")]
18193 unsafe fn test_mm512_mask_test_epi8_mask() {
18194 let a = _mm512_set1_epi8(1 << 0);
18195 let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
18196 let r = _mm512_mask_test_epi8_mask(0, a, b);
18197 assert_eq!(r, 0);
18198 let r = _mm512_mask_test_epi8_mask(
18199 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
18200 a,
18201 b,
18202 );
18203 let e: __mmask64 =
18204 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18205 assert_eq!(r, e);
18206 }
18207
18208 #[simd_test(enable = "avx512bw,avx512vl")]
18209 unsafe fn test_mm256_test_epi8_mask() {
18210 let a = _mm256_set1_epi8(1 << 0);
18211 let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
18212 let r = _mm256_test_epi8_mask(a, b);
18213 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18214 assert_eq!(r, e);
18215 }
18216
18217 #[simd_test(enable = "avx512bw,avx512vl")]
18218 unsafe fn test_mm256_mask_test_epi8_mask() {
18219 let a = _mm256_set1_epi8(1 << 0);
18220 let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
18221 let r = _mm256_mask_test_epi8_mask(0, a, b);
18222 assert_eq!(r, 0);
18223 let r = _mm256_mask_test_epi8_mask(0b11111111_11111111_11111111_11111111, a, b);
18224 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18225 assert_eq!(r, e);
18226 }
18227
18228 #[simd_test(enable = "avx512bw,avx512vl")]
18229 unsafe fn test_mm_test_epi8_mask() {
18230 let a = _mm_set1_epi8(1 << 0);
18231 let b = _mm_set1_epi8(1 << 0 | 1 << 1);
18232 let r = _mm_test_epi8_mask(a, b);
18233 let e: __mmask16 = 0b11111111_11111111;
18234 assert_eq!(r, e);
18235 }
18236
18237 #[simd_test(enable = "avx512bw,avx512vl")]
18238 unsafe fn test_mm_mask_test_epi8_mask() {
18239 let a = _mm_set1_epi8(1 << 0);
18240 let b = _mm_set1_epi8(1 << 0 | 1 << 1);
18241 let r = _mm_mask_test_epi8_mask(0, a, b);
18242 assert_eq!(r, 0);
18243 let r = _mm_mask_test_epi8_mask(0b11111111_11111111, a, b);
18244 let e: __mmask16 = 0b11111111_11111111;
18245 assert_eq!(r, e);
18246 }
18247
18248 #[simd_test(enable = "avx512bw")]
18249 unsafe fn test_mm512_testn_epi16_mask() {
18250 let a = _mm512_set1_epi16(1 << 0);
18251 let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
18252 let r = _mm512_testn_epi16_mask(a, b);
18253 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18254 assert_eq!(r, e);
18255 }
18256
18257 #[simd_test(enable = "avx512bw")]
18258 unsafe fn test_mm512_mask_testn_epi16_mask() {
18259 let a = _mm512_set1_epi16(1 << 0);
18260 let b = _mm512_set1_epi16(1 << 0 | 1 << 1);
18261 let r = _mm512_mask_testn_epi16_mask(0, a, b);
18262 assert_eq!(r, 0);
18263 let r = _mm512_mask_testn_epi16_mask(0b11111111_11111111_11111111_11111111, a, b);
18264 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18265 assert_eq!(r, e);
18266 }
18267
18268 #[simd_test(enable = "avx512bw,avx512vl")]
18269 unsafe fn test_mm256_testn_epi16_mask() {
18270 let a = _mm256_set1_epi16(1 << 0);
18271 let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
18272 let r = _mm256_testn_epi16_mask(a, b);
18273 let e: __mmask16 = 0b00000000_00000000;
18274 assert_eq!(r, e);
18275 }
18276
18277 #[simd_test(enable = "avx512bw,avx512vl")]
18278 unsafe fn test_mm256_mask_testn_epi16_mask() {
18279 let a = _mm256_set1_epi16(1 << 0);
18280 let b = _mm256_set1_epi16(1 << 0 | 1 << 1);
18281 let r = _mm256_mask_testn_epi16_mask(0, a, b);
18282 assert_eq!(r, 0);
18283 let r = _mm256_mask_testn_epi16_mask(0b11111111_11111111, a, b);
18284 let e: __mmask16 = 0b00000000_00000000;
18285 assert_eq!(r, e);
18286 }
18287
18288 #[simd_test(enable = "avx512bw,avx512vl")]
18289 unsafe fn test_mm_testn_epi16_mask() {
18290 let a = _mm_set1_epi16(1 << 0);
18291 let b = _mm_set1_epi16(1 << 0 | 1 << 1);
18292 let r = _mm_testn_epi16_mask(a, b);
18293 let e: __mmask8 = 0b00000000;
18294 assert_eq!(r, e);
18295 }
18296
18297 #[simd_test(enable = "avx512bw,avx512vl")]
18298 unsafe fn test_mm_mask_testn_epi16_mask() {
18299 let a = _mm_set1_epi16(1 << 0);
18300 let b = _mm_set1_epi16(1 << 0 | 1 << 1);
18301 let r = _mm_mask_testn_epi16_mask(0, a, b);
18302 assert_eq!(r, 0);
18303 let r = _mm_mask_testn_epi16_mask(0b11111111, a, b);
18304 let e: __mmask8 = 0b00000000;
18305 assert_eq!(r, e);
18306 }
18307
18308 #[simd_test(enable = "avx512bw")]
18309 unsafe fn test_mm512_testn_epi8_mask() {
18310 let a = _mm512_set1_epi8(1 << 0);
18311 let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
18312 let r = _mm512_testn_epi8_mask(a, b);
18313 let e: __mmask64 =
18314 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
18315 assert_eq!(r, e);
18316 }
18317
18318 #[simd_test(enable = "avx512bw")]
18319 unsafe fn test_mm512_mask_testn_epi8_mask() {
18320 let a = _mm512_set1_epi8(1 << 0);
18321 let b = _mm512_set1_epi8(1 << 0 | 1 << 1);
18322 let r = _mm512_mask_testn_epi8_mask(0, a, b);
18323 assert_eq!(r, 0);
18324 let r = _mm512_mask_testn_epi8_mask(
18325 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
18326 a,
18327 b,
18328 );
18329 let e: __mmask64 =
18330 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
18331 assert_eq!(r, e);
18332 }
18333
18334 #[simd_test(enable = "avx512bw,avx512vl")]
18335 unsafe fn test_mm256_testn_epi8_mask() {
18336 let a = _mm256_set1_epi8(1 << 0);
18337 let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
18338 let r = _mm256_testn_epi8_mask(a, b);
18339 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18340 assert_eq!(r, e);
18341 }
18342
18343 #[simd_test(enable = "avx512bw,avx512vl")]
18344 unsafe fn test_mm256_mask_testn_epi8_mask() {
18345 let a = _mm256_set1_epi8(1 << 0);
18346 let b = _mm256_set1_epi8(1 << 0 | 1 << 1);
18347 let r = _mm256_mask_testn_epi8_mask(0, a, b);
18348 assert_eq!(r, 0);
18349 let r = _mm256_mask_testn_epi8_mask(0b11111111_11111111_11111111_11111111, a, b);
18350 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18351 assert_eq!(r, e);
18352 }
18353
18354 #[simd_test(enable = "avx512bw,avx512vl")]
18355 unsafe fn test_mm_testn_epi8_mask() {
18356 let a = _mm_set1_epi8(1 << 0);
18357 let b = _mm_set1_epi8(1 << 0 | 1 << 1);
18358 let r = _mm_testn_epi8_mask(a, b);
18359 let e: __mmask16 = 0b00000000_00000000;
18360 assert_eq!(r, e);
18361 }
18362
18363 #[simd_test(enable = "avx512bw,avx512vl")]
18364 unsafe fn test_mm_mask_testn_epi8_mask() {
18365 let a = _mm_set1_epi8(1 << 0);
18366 let b = _mm_set1_epi8(1 << 0 | 1 << 1);
18367 let r = _mm_mask_testn_epi8_mask(0, a, b);
18368 assert_eq!(r, 0);
18369 let r = _mm_mask_testn_epi8_mask(0b11111111_11111111, a, b);
18370 let e: __mmask16 = 0b00000000_00000000;
18371 assert_eq!(r, e);
18372 }
18373
18374 #[simd_test(enable = "avx512bw")]
18375 unsafe fn test_store_mask64() {
18376 let a: __mmask64 =
18377 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
18378 let mut r = 0;
18379 _store_mask64(&mut r, a);
18380 assert_eq!(r, a);
18381 }
18382
18383 #[simd_test(enable = "avx512bw")]
18384 unsafe fn test_store_mask32() {
18385 let a: __mmask32 = 0b11111111_00000000_11111111_00000000;
18386 let mut r = 0;
18387 _store_mask32(&mut r, a);
18388 assert_eq!(r, a);
18389 }
18390
18391 #[simd_test(enable = "avx512bw")]
18392 unsafe fn test_load_mask64() {
18393 let p: __mmask64 =
18394 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
18395 let r = _load_mask64(&p);
18396 let e: __mmask64 =
18397 0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
18398 assert_eq!(r, e);
18399 }
18400
18401 #[simd_test(enable = "avx512bw")]
18402 unsafe fn test_load_mask32() {
18403 let p: __mmask32 = 0b11111111_00000000_11111111_00000000;
18404 let r = _load_mask32(&p);
18405 let e: __mmask32 = 0b11111111_00000000_11111111_00000000;
18406 assert_eq!(r, e);
18407 }
18408
18409 #[simd_test(enable = "avx512bw")]
18410 unsafe fn test_mm512_sad_epu8() {
18411 let a = _mm512_set1_epi8(2);
18412 let b = _mm512_set1_epi8(4);
18413 let r = _mm512_sad_epu8(a, b);
18414 let e = _mm512_set1_epi64(16);
18415 assert_eq_m512i(r, e);
18416 }
18417
18418 #[simd_test(enable = "avx512bw")]
18419 unsafe fn test_mm512_dbsad_epu8() {
18420 let a = _mm512_set1_epi8(2);
18421 let b = _mm512_set1_epi8(4);
18422 let r = _mm512_dbsad_epu8::<0>(a, b);
18423 let e = _mm512_set1_epi16(8);
18424 assert_eq_m512i(r, e);
18425 }
18426
18427 #[simd_test(enable = "avx512bw")]
18428 unsafe fn test_mm512_mask_dbsad_epu8() {
18429 let src = _mm512_set1_epi16(1);
18430 let a = _mm512_set1_epi8(2);
18431 let b = _mm512_set1_epi8(4);
18432 let r = _mm512_mask_dbsad_epu8::<0>(src, 0, a, b);
18433 assert_eq_m512i(r, src);
18434 let r = _mm512_mask_dbsad_epu8::<0>(src, 0b11111111_11111111_11111111_11111111, a, b);
18435 let e = _mm512_set1_epi16(8);
18436 assert_eq_m512i(r, e);
18437 }
18438
18439 #[simd_test(enable = "avx512bw")]
18440 unsafe fn test_mm512_maskz_dbsad_epu8() {
18441 let a = _mm512_set1_epi8(2);
18442 let b = _mm512_set1_epi8(4);
18443 let r = _mm512_maskz_dbsad_epu8::<0>(0, a, b);
18444 assert_eq_m512i(r, _mm512_setzero_si512());
18445 let r = _mm512_maskz_dbsad_epu8::<0>(0b11111111_11111111_11111111_11111111, a, b);
18446 let e = _mm512_set1_epi16(8);
18447 assert_eq_m512i(r, e);
18448 }
18449
18450 #[simd_test(enable = "avx512bw,avx512vl")]
18451 unsafe fn test_mm256_dbsad_epu8() {
18452 let a = _mm256_set1_epi8(2);
18453 let b = _mm256_set1_epi8(4);
18454 let r = _mm256_dbsad_epu8::<0>(a, b);
18455 let e = _mm256_set1_epi16(8);
18456 assert_eq_m256i(r, e);
18457 }
18458
18459 #[simd_test(enable = "avx512bw,avx512vl")]
18460 unsafe fn test_mm256_mask_dbsad_epu8() {
18461 let src = _mm256_set1_epi16(1);
18462 let a = _mm256_set1_epi8(2);
18463 let b = _mm256_set1_epi8(4);
18464 let r = _mm256_mask_dbsad_epu8::<0>(src, 0, a, b);
18465 assert_eq_m256i(r, src);
18466 let r = _mm256_mask_dbsad_epu8::<0>(src, 0b11111111_11111111, a, b);
18467 let e = _mm256_set1_epi16(8);
18468 assert_eq_m256i(r, e);
18469 }
18470
18471 #[simd_test(enable = "avx512bw,avx512vl")]
18472 unsafe fn test_mm256_maskz_dbsad_epu8() {
18473 let a = _mm256_set1_epi8(2);
18474 let b = _mm256_set1_epi8(4);
18475 let r = _mm256_maskz_dbsad_epu8::<0>(0, a, b);
18476 assert_eq_m256i(r, _mm256_setzero_si256());
18477 let r = _mm256_maskz_dbsad_epu8::<0>(0b11111111_11111111, a, b);
18478 let e = _mm256_set1_epi16(8);
18479 assert_eq_m256i(r, e);
18480 }
18481
18482 #[simd_test(enable = "avx512bw,avx512vl")]
18483 unsafe fn test_mm_dbsad_epu8() {
18484 let a = _mm_set1_epi8(2);
18485 let b = _mm_set1_epi8(4);
18486 let r = _mm_dbsad_epu8::<0>(a, b);
18487 let e = _mm_set1_epi16(8);
18488 assert_eq_m128i(r, e);
18489 }
18490
18491 #[simd_test(enable = "avx512bw,avx512vl")]
18492 unsafe fn test_mm_mask_dbsad_epu8() {
18493 let src = _mm_set1_epi16(1);
18494 let a = _mm_set1_epi8(2);
18495 let b = _mm_set1_epi8(4);
18496 let r = _mm_mask_dbsad_epu8::<0>(src, 0, a, b);
18497 assert_eq_m128i(r, src);
18498 let r = _mm_mask_dbsad_epu8::<0>(src, 0b11111111, a, b);
18499 let e = _mm_set1_epi16(8);
18500 assert_eq_m128i(r, e);
18501 }
18502
18503 #[simd_test(enable = "avx512bw,avx512vl")]
18504 unsafe fn test_mm_maskz_dbsad_epu8() {
18505 let a = _mm_set1_epi8(2);
18506 let b = _mm_set1_epi8(4);
18507 let r = _mm_maskz_dbsad_epu8::<0>(0, a, b);
18508 assert_eq_m128i(r, _mm_setzero_si128());
18509 let r = _mm_maskz_dbsad_epu8::<0>(0b11111111, a, b);
18510 let e = _mm_set1_epi16(8);
18511 assert_eq_m128i(r, e);
18512 }
18513
18514 #[simd_test(enable = "avx512bw")]
18515 unsafe fn test_mm512_movepi16_mask() {
18516 let a = _mm512_set1_epi16(1 << 15);
18517 let r = _mm512_movepi16_mask(a);
18518 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18519 assert_eq!(r, e);
18520 }
18521
18522 #[simd_test(enable = "avx512bw,avx512vl")]
18523 unsafe fn test_mm256_movepi16_mask() {
18524 let a = _mm256_set1_epi16(1 << 15);
18525 let r = _mm256_movepi16_mask(a);
18526 let e: __mmask16 = 0b11111111_11111111;
18527 assert_eq!(r, e);
18528 }
18529
18530 #[simd_test(enable = "avx512bw,avx512vl")]
18531 unsafe fn test_mm_movepi16_mask() {
18532 let a = _mm_set1_epi16(1 << 15);
18533 let r = _mm_movepi16_mask(a);
18534 let e: __mmask8 = 0b11111111;
18535 assert_eq!(r, e);
18536 }
18537
18538 #[simd_test(enable = "avx512bw")]
18539 unsafe fn test_mm512_movepi8_mask() {
18540 let a = _mm512_set1_epi8(1 << 7);
18541 let r = _mm512_movepi8_mask(a);
18542 let e: __mmask64 =
18543 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18544 assert_eq!(r, e);
18545 }
18546
18547 #[simd_test(enable = "avx512bw,avx512vl")]
18548 unsafe fn test_mm256_movepi8_mask() {
18549 let a = _mm256_set1_epi8(1 << 7);
18550 let r = _mm256_movepi8_mask(a);
18551 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18552 assert_eq!(r, e);
18553 }
18554
18555 #[simd_test(enable = "avx512bw,avx512vl")]
18556 unsafe fn test_mm_movepi8_mask() {
18557 let a = _mm_set1_epi8(1 << 7);
18558 let r = _mm_movepi8_mask(a);
18559 let e: __mmask16 = 0b11111111_11111111;
18560 assert_eq!(r, e);
18561 }
18562
18563 #[simd_test(enable = "avx512bw")]
18564 unsafe fn test_mm512_movm_epi16() {
18565 let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
18566 let r = _mm512_movm_epi16(a);
18567 let e = _mm512_set1_epi16(
18568 1 << 15
18569 | 1 << 14
18570 | 1 << 13
18571 | 1 << 12
18572 | 1 << 11
18573 | 1 << 10
18574 | 1 << 9
18575 | 1 << 8
18576 | 1 << 7
18577 | 1 << 6
18578 | 1 << 5
18579 | 1 << 4
18580 | 1 << 3
18581 | 1 << 2
18582 | 1 << 1
18583 | 1 << 0,
18584 );
18585 assert_eq_m512i(r, e);
18586 }
18587
18588 #[simd_test(enable = "avx512bw,avx512vl")]
18589 unsafe fn test_mm256_movm_epi16() {
18590 let a: __mmask16 = 0b11111111_11111111;
18591 let r = _mm256_movm_epi16(a);
18592 let e = _mm256_set1_epi16(
18593 1 << 15
18594 | 1 << 14
18595 | 1 << 13
18596 | 1 << 12
18597 | 1 << 11
18598 | 1 << 10
18599 | 1 << 9
18600 | 1 << 8
18601 | 1 << 7
18602 | 1 << 6
18603 | 1 << 5
18604 | 1 << 4
18605 | 1 << 3
18606 | 1 << 2
18607 | 1 << 1
18608 | 1 << 0,
18609 );
18610 assert_eq_m256i(r, e);
18611 }
18612
18613 #[simd_test(enable = "avx512bw,avx512vl")]
18614 unsafe fn test_mm_movm_epi16() {
18615 let a: __mmask8 = 0b11111111;
18616 let r = _mm_movm_epi16(a);
18617 let e = _mm_set1_epi16(
18618 1 << 15
18619 | 1 << 14
18620 | 1 << 13
18621 | 1 << 12
18622 | 1 << 11
18623 | 1 << 10
18624 | 1 << 9
18625 | 1 << 8
18626 | 1 << 7
18627 | 1 << 6
18628 | 1 << 5
18629 | 1 << 4
18630 | 1 << 3
18631 | 1 << 2
18632 | 1 << 1
18633 | 1 << 0,
18634 );
18635 assert_eq_m128i(r, e);
18636 }
18637
18638 #[simd_test(enable = "avx512bw")]
18639 unsafe fn test_mm512_movm_epi8() {
18640 let a: __mmask64 =
18641 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18642 let r = _mm512_movm_epi8(a);
18643 let e =
18644 _mm512_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0);
18645 assert_eq_m512i(r, e);
18646 }
18647
18648 #[simd_test(enable = "avx512bw,avx512vl")]
18649 unsafe fn test_mm256_movm_epi8() {
18650 let a: __mmask32 = 0b11111111_11111111_11111111_11111111;
18651 let r = _mm256_movm_epi8(a);
18652 let e =
18653 _mm256_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0);
18654 assert_eq_m256i(r, e);
18655 }
18656
18657 #[simd_test(enable = "avx512bw,avx512vl")]
18658 unsafe fn test_mm_movm_epi8() {
18659 let a: __mmask16 = 0b11111111_11111111;
18660 let r = _mm_movm_epi8(a);
18661 let e =
18662 _mm_set1_epi8(1 << 7 | 1 << 6 | 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0);
18663 assert_eq_m128i(r, e);
18664 }
18665
18666 #[simd_test(enable = "avx512bw")]
18667 unsafe fn test_kadd_mask32() {
18668 let a: __mmask32 = 11;
18669 let b: __mmask32 = 22;
18670 let r = _kadd_mask32(a, b);
18671 let e: __mmask32 = 33;
18672 assert_eq!(r, e);
18673 }
18674
18675 #[simd_test(enable = "avx512bw")]
18676 unsafe fn test_kadd_mask64() {
18677 let a: __mmask64 = 11;
18678 let b: __mmask64 = 22;
18679 let r = _kadd_mask64(a, b);
18680 let e: __mmask64 = 33;
18681 assert_eq!(r, e);
18682 }
18683
18684 #[simd_test(enable = "avx512bw")]
18685 unsafe fn test_kand_mask32() {
18686 let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
18687 let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
18688 let r = _kand_mask32(a, b);
18689 let e: __mmask32 = 0b11001100_00110011_11001100_00110011;
18690 assert_eq!(r, e);
18691 }
18692
18693 #[simd_test(enable = "avx512bw")]
18694 unsafe fn test_kand_mask64() {
18695 let a: __mmask64 =
18696 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18697 let b: __mmask64 =
18698 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18699 let r = _kand_mask64(a, b);
18700 let e: __mmask64 =
18701 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18702 assert_eq!(r, e);
18703 }
18704
18705 #[simd_test(enable = "avx512bw")]
18706 unsafe fn test_knot_mask32() {
18707 let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
18708 let r = _knot_mask32(a);
18709 let e: __mmask32 = 0b00110011_11001100_00110011_11001100;
18710 assert_eq!(r, e);
18711 }
18712
18713 #[simd_test(enable = "avx512bw")]
18714 unsafe fn test_knot_mask64() {
18715 let a: __mmask64 =
18716 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18717 let r = _knot_mask64(a);
18718 let e: __mmask64 =
18719 0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
18720 assert_eq!(r, e);
18721 }
18722
18723 #[simd_test(enable = "avx512bw")]
18724 unsafe fn test_kandn_mask32() {
18725 let a: __mmask32 = 0b11001100_00110011_11001100_00110011;
18726 let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
18727 let r = _kandn_mask32(a, b);
18728 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18729 assert_eq!(r, e);
18730 }
18731
18732 #[simd_test(enable = "avx512bw")]
18733 unsafe fn test_kandn_mask64() {
18734 let a: __mmask64 =
18735 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18736 let b: __mmask64 =
18737 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18738 let r = _kandn_mask64(a, b);
18739 let e: __mmask64 =
18740 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
18741 assert_eq!(r, e);
18742 }
18743
18744 #[simd_test(enable = "avx512bw")]
18745 unsafe fn test_kor_mask32() {
18746 let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
18747 let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
18748 let r = _kor_mask32(a, b);
18749 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18750 assert_eq!(r, e);
18751 }
18752
18753 #[simd_test(enable = "avx512bw")]
18754 unsafe fn test_kor_mask64() {
18755 let a: __mmask64 =
18756 0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
18757 let b: __mmask64 =
18758 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18759 let r = _kor_mask64(a, b);
18760 let e: __mmask64 =
18761 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18762 assert_eq!(r, e);
18763 }
18764
18765 #[simd_test(enable = "avx512bw")]
18766 unsafe fn test_kxor_mask32() {
18767 let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
18768 let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
18769 let r = _kxor_mask32(a, b);
18770 let e: __mmask32 = 0b11111111_11111111_11111111_11111111;
18771 assert_eq!(r, e);
18772 }
18773
18774 #[simd_test(enable = "avx512bw")]
18775 unsafe fn test_kxor_mask64() {
18776 let a: __mmask64 =
18777 0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
18778 let b: __mmask64 =
18779 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18780 let r = _kxor_mask64(a, b);
18781 let e: __mmask64 =
18782 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111;
18783 assert_eq!(r, e);
18784 }
18785
18786 #[simd_test(enable = "avx512bw")]
18787 unsafe fn test_kxnor_mask32() {
18788 let a: __mmask32 = 0b00110011_11001100_00110011_11001100;
18789 let b: __mmask32 = 0b11001100_00110011_11001100_00110011;
18790 let r = _kxnor_mask32(a, b);
18791 let e: __mmask32 = 0b00000000_00000000_00000000_00000000;
18792 assert_eq!(r, e);
18793 }
18794
18795 #[simd_test(enable = "avx512bw")]
18796 unsafe fn test_kxnor_mask64() {
18797 let a: __mmask64 =
18798 0b00110011_11001100_00110011_11001100_00110011_11001100_00110011_11001100;
18799 let b: __mmask64 =
18800 0b11001100_00110011_11001100_00110011_11001100_00110011_11001100_00110011;
18801 let r = _kxnor_mask64(a, b);
18802 let e: __mmask64 =
18803 0b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000;
18804 assert_eq!(r, e);
18805 }
18806
18807 #[simd_test(enable = "avx512bw")]
18808 unsafe fn test_mm512_cvtepi16_epi8() {
18809 let a = _mm512_set1_epi16(2);
18810 let r = _mm512_cvtepi16_epi8(a);
18811 let e = _mm256_set1_epi8(2);
18812 assert_eq_m256i(r, e);
18813 }
18814
18815 #[simd_test(enable = "avx512bw")]
18816 unsafe fn test_mm512_mask_cvtepi16_epi8() {
18817 let src = _mm256_set1_epi8(1);
18818 let a = _mm512_set1_epi16(2);
18819 let r = _mm512_mask_cvtepi16_epi8(src, 0, a);
18820 assert_eq_m256i(r, src);
18821 let r = _mm512_mask_cvtepi16_epi8(src, 0b11111111_11111111_11111111_11111111, a);
18822 let e = _mm256_set1_epi8(2);
18823 assert_eq_m256i(r, e);
18824 }
18825
18826 #[simd_test(enable = "avx512bw")]
18827 unsafe fn test_mm512_maskz_cvtepi16_epi8() {
18828 let a = _mm512_set1_epi16(2);
18829 let r = _mm512_maskz_cvtepi16_epi8(0, a);
18830 assert_eq_m256i(r, _mm256_setzero_si256());
18831 let r = _mm512_maskz_cvtepi16_epi8(0b11111111_11111111_11111111_11111111, a);
18832 let e = _mm256_set1_epi8(2);
18833 assert_eq_m256i(r, e);
18834 }
18835
18836 #[simd_test(enable = "avx512bw,avx512vl")]
18837 unsafe fn test_mm256_cvtepi16_epi8() {
18838 let a = _mm256_set1_epi16(2);
18839 let r = _mm256_cvtepi16_epi8(a);
18840 let e = _mm_set1_epi8(2);
18841 assert_eq_m128i(r, e);
18842 }
18843
18844 #[simd_test(enable = "avx512bw,avx512vl")]
18845 unsafe fn test_mm256_mask_cvtepi16_epi8() {
18846 let src = _mm_set1_epi8(1);
18847 let a = _mm256_set1_epi16(2);
18848 let r = _mm256_mask_cvtepi16_epi8(src, 0, a);
18849 assert_eq_m128i(r, src);
18850 let r = _mm256_mask_cvtepi16_epi8(src, 0b11111111_11111111, a);
18851 let e = _mm_set1_epi8(2);
18852 assert_eq_m128i(r, e);
18853 }
18854
18855 #[simd_test(enable = "avx512bw,avx512vl")]
18856 unsafe fn test_mm256_maskz_cvtepi16_epi8() {
18857 let a = _mm256_set1_epi16(2);
18858 let r = _mm256_maskz_cvtepi16_epi8(0, a);
18859 assert_eq_m128i(r, _mm_setzero_si128());
18860 let r = _mm256_maskz_cvtepi16_epi8(0b11111111_11111111, a);
18861 let e = _mm_set1_epi8(2);
18862 assert_eq_m128i(r, e);
18863 }
18864
18865 #[simd_test(enable = "avx512bw,avx512vl")]
18866 unsafe fn test_mm_cvtepi16_epi8() {
18867 let a = _mm_set1_epi16(2);
18868 let r = _mm_cvtepi16_epi8(a);
18869 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
18870 assert_eq_m128i(r, e);
18871 }
18872
18873 #[simd_test(enable = "avx512bw,avx512vl")]
18874 unsafe fn test_mm_mask_cvtepi16_epi8() {
18875 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
18876 let a = _mm_set1_epi16(2);
18877 let r = _mm_mask_cvtepi16_epi8(src, 0, a);
18878 assert_eq_m128i(r, src);
18879 let r = _mm_mask_cvtepi16_epi8(src, 0b11111111, a);
18880 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
18881 assert_eq_m128i(r, e);
18882 }
18883
18884 #[simd_test(enable = "avx512bw,avx512vl")]
18885 unsafe fn test_mm_maskz_cvtepi16_epi8() {
18886 let a = _mm_set1_epi16(2);
18887 let r = _mm_maskz_cvtepi16_epi8(0, a);
18888 assert_eq_m128i(r, _mm_setzero_si128());
18889 let r = _mm_maskz_cvtepi16_epi8(0b11111111, a);
18890 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2);
18891 assert_eq_m128i(r, e);
18892 }
18893
18894 #[simd_test(enable = "avx512bw")]
18895 unsafe fn test_mm512_cvtsepi16_epi8() {
18896 let a = _mm512_set1_epi16(i16::MAX);
18897 let r = _mm512_cvtsepi16_epi8(a);
18898 let e = _mm256_set1_epi8(i8::MAX);
18899 assert_eq_m256i(r, e);
18900 }
18901
18902 #[simd_test(enable = "avx512bw")]
18903 unsafe fn test_mm512_mask_cvtsepi16_epi8() {
18904 let src = _mm256_set1_epi8(1);
18905 let a = _mm512_set1_epi16(i16::MAX);
18906 let r = _mm512_mask_cvtsepi16_epi8(src, 0, a);
18907 assert_eq_m256i(r, src);
18908 let r = _mm512_mask_cvtsepi16_epi8(src, 0b11111111_11111111_11111111_11111111, a);
18909 let e = _mm256_set1_epi8(i8::MAX);
18910 assert_eq_m256i(r, e);
18911 }
18912
18913 #[simd_test(enable = "avx512bw,avx512vl")]
18914 unsafe fn test_mm256_cvtsepi16_epi8() {
18915 let a = _mm256_set1_epi16(i16::MAX);
18916 let r = _mm256_cvtsepi16_epi8(a);
18917 let e = _mm_set1_epi8(i8::MAX);
18918 assert_eq_m128i(r, e);
18919 }
18920
18921 #[simd_test(enable = "avx512bw,avx512vl")]
18922 unsafe fn test_mm256_mask_cvtsepi16_epi8() {
18923 let src = _mm_set1_epi8(1);
18924 let a = _mm256_set1_epi16(i16::MAX);
18925 let r = _mm256_mask_cvtsepi16_epi8(src, 0, a);
18926 assert_eq_m128i(r, src);
18927 let r = _mm256_mask_cvtsepi16_epi8(src, 0b11111111_11111111, a);
18928 let e = _mm_set1_epi8(i8::MAX);
18929 assert_eq_m128i(r, e);
18930 }
18931
18932 #[simd_test(enable = "avx512bw,avx512vl")]
18933 unsafe fn test_mm256_maskz_cvtsepi16_epi8() {
18934 let a = _mm256_set1_epi16(i16::MAX);
18935 let r = _mm256_maskz_cvtsepi16_epi8(0, a);
18936 assert_eq_m128i(r, _mm_setzero_si128());
18937 let r = _mm256_maskz_cvtsepi16_epi8(0b11111111_11111111, a);
18938 let e = _mm_set1_epi8(i8::MAX);
18939 assert_eq_m128i(r, e);
18940 }
18941
18942 #[simd_test(enable = "avx512bw,avx512vl")]
18943 unsafe fn test_mm_cvtsepi16_epi8() {
18944 let a = _mm_set1_epi16(i16::MAX);
18945 let r = _mm_cvtsepi16_epi8(a);
18946 #[rustfmt::skip]
18947 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
18948 assert_eq_m128i(r, e);
18949 }
18950
18951 #[simd_test(enable = "avx512bw,avx512vl")]
18952 unsafe fn test_mm_mask_cvtsepi16_epi8() {
18953 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
18954 let a = _mm_set1_epi16(i16::MAX);
18955 let r = _mm_mask_cvtsepi16_epi8(src, 0, a);
18956 assert_eq_m128i(r, src);
18957 let r = _mm_mask_cvtsepi16_epi8(src, 0b11111111, a);
18958 #[rustfmt::skip]
18959 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
18960 assert_eq_m128i(r, e);
18961 }
18962
18963 #[simd_test(enable = "avx512bw,avx512vl")]
18964 unsafe fn test_mm_maskz_cvtsepi16_epi8() {
18965 let a = _mm_set1_epi16(i16::MAX);
18966 let r = _mm_maskz_cvtsepi16_epi8(0, a);
18967 assert_eq_m128i(r, _mm_setzero_si128());
18968 let r = _mm_maskz_cvtsepi16_epi8(0b11111111, a);
18969 #[rustfmt::skip]
18970 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX);
18971 assert_eq_m128i(r, e);
18972 }
18973
18974 #[simd_test(enable = "avx512bw")]
18975 unsafe fn test_mm512_maskz_cvtsepi16_epi8() {
18976 let a = _mm512_set1_epi16(i16::MAX);
18977 let r = _mm512_maskz_cvtsepi16_epi8(0, a);
18978 assert_eq_m256i(r, _mm256_setzero_si256());
18979 let r = _mm512_maskz_cvtsepi16_epi8(0b11111111_11111111_11111111_11111111, a);
18980 let e = _mm256_set1_epi8(i8::MAX);
18981 assert_eq_m256i(r, e);
18982 }
18983
18984 #[simd_test(enable = "avx512bw")]
18985 unsafe fn test_mm512_cvtusepi16_epi8() {
18986 let a = _mm512_set1_epi16(i16::MIN);
18987 let r = _mm512_cvtusepi16_epi8(a);
18988 let e = _mm256_set1_epi8(-1);
18989 assert_eq_m256i(r, e);
18990 }
18991
18992 #[simd_test(enable = "avx512bw")]
18993 unsafe fn test_mm512_mask_cvtusepi16_epi8() {
18994 let src = _mm256_set1_epi8(1);
18995 let a = _mm512_set1_epi16(i16::MIN);
18996 let r = _mm512_mask_cvtusepi16_epi8(src, 0, a);
18997 assert_eq_m256i(r, src);
18998 let r = _mm512_mask_cvtusepi16_epi8(src, 0b11111111_11111111_11111111_11111111, a);
18999 let e = _mm256_set1_epi8(-1);
19000 assert_eq_m256i(r, e);
19001 }
19002
19003 #[simd_test(enable = "avx512bw")]
19004 unsafe fn test_mm512_maskz_cvtusepi16_epi8() {
19005 let a = _mm512_set1_epi16(i16::MIN);
19006 let r = _mm512_maskz_cvtusepi16_epi8(0, a);
19007 assert_eq_m256i(r, _mm256_setzero_si256());
19008 let r = _mm512_maskz_cvtusepi16_epi8(0b11111111_11111111_11111111_11111111, a);
19009 let e = _mm256_set1_epi8(-1);
19010 assert_eq_m256i(r, e);
19011 }
19012
19013 #[simd_test(enable = "avx512bw,avx512vl")]
19014 unsafe fn test_mm256_cvtusepi16_epi8() {
19015 let a = _mm256_set1_epi16(i16::MIN);
19016 let r = _mm256_cvtusepi16_epi8(a);
19017 let e = _mm_set1_epi8(-1);
19018 assert_eq_m128i(r, e);
19019 }
19020
19021 #[simd_test(enable = "avx512bw,avx512vl")]
19022 unsafe fn test_mm256_mask_cvtusepi16_epi8() {
19023 let src = _mm_set1_epi8(1);
19024 let a = _mm256_set1_epi16(i16::MIN);
19025 let r = _mm256_mask_cvtusepi16_epi8(src, 0, a);
19026 assert_eq_m128i(r, src);
19027 let r = _mm256_mask_cvtusepi16_epi8(src, 0b11111111_11111111, a);
19028 let e = _mm_set1_epi8(-1);
19029 assert_eq_m128i(r, e);
19030 }
19031
19032 #[simd_test(enable = "avx512bw,avx512vl")]
19033 unsafe fn test_mm256_maskz_cvtusepi16_epi8() {
19034 let a = _mm256_set1_epi16(i16::MIN);
19035 let r = _mm256_maskz_cvtusepi16_epi8(0, a);
19036 assert_eq_m128i(r, _mm_setzero_si128());
19037 let r = _mm256_maskz_cvtusepi16_epi8(0b11111111_11111111, a);
19038 let e = _mm_set1_epi8(-1);
19039 assert_eq_m128i(r, e);
19040 }
19041
19042 #[simd_test(enable = "avx512bw,avx512vl")]
19043 unsafe fn test_mm_cvtusepi16_epi8() {
19044 let a = _mm_set1_epi16(i16::MIN);
19045 let r = _mm_cvtusepi16_epi8(a);
19046 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
19047 assert_eq_m128i(r, e);
19048 }
19049
19050 #[simd_test(enable = "avx512bw,avx512vl")]
19051 unsafe fn test_mm_mask_cvtusepi16_epi8() {
19052 let src = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1);
19053 let a = _mm_set1_epi16(i16::MIN);
19054 let r = _mm_mask_cvtusepi16_epi8(src, 0, a);
19055 assert_eq_m128i(r, src);
19056 let r = _mm_mask_cvtusepi16_epi8(src, 0b11111111, a);
19057 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
19058 assert_eq_m128i(r, e);
19059 }
19060
19061 #[simd_test(enable = "avx512bw,avx512vl")]
19062 unsafe fn test_mm_maskz_cvtusepi16_epi8() {
19063 let a = _mm_set1_epi16(i16::MIN);
19064 let r = _mm_maskz_cvtusepi16_epi8(0, a);
19065 assert_eq_m128i(r, _mm_setzero_si128());
19066 let r = _mm_maskz_cvtusepi16_epi8(0b11111111, a);
19067 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1, -1, -1);
19068 assert_eq_m128i(r, e);
19069 }
19070
19071 #[simd_test(enable = "avx512bw")]
19072 unsafe fn test_mm512_cvtepi8_epi16() {
19073 let a = _mm256_set1_epi8(2);
19074 let r = _mm512_cvtepi8_epi16(a);
19075 let e = _mm512_set1_epi16(2);
19076 assert_eq_m512i(r, e);
19077 }
19078
19079 #[simd_test(enable = "avx512bw")]
19080 unsafe fn test_mm512_mask_cvtepi8_epi16() {
19081 let src = _mm512_set1_epi16(1);
19082 let a = _mm256_set1_epi8(2);
19083 let r = _mm512_mask_cvtepi8_epi16(src, 0, a);
19084 assert_eq_m512i(r, src);
19085 let r = _mm512_mask_cvtepi8_epi16(src, 0b11111111_11111111_11111111_11111111, a);
19086 let e = _mm512_set1_epi16(2);
19087 assert_eq_m512i(r, e);
19088 }
19089
19090 #[simd_test(enable = "avx512bw")]
19091 unsafe fn test_mm512_maskz_cvtepi8_epi16() {
19092 let a = _mm256_set1_epi8(2);
19093 let r = _mm512_maskz_cvtepi8_epi16(0, a);
19094 assert_eq_m512i(r, _mm512_setzero_si512());
19095 let r = _mm512_maskz_cvtepi8_epi16(0b11111111_11111111_11111111_11111111, a);
19096 let e = _mm512_set1_epi16(2);
19097 assert_eq_m512i(r, e);
19098 }
19099
19100 #[simd_test(enable = "avx512bw,avx512vl")]
19101 unsafe fn test_mm256_mask_cvtepi8_epi16() {
19102 let src = _mm256_set1_epi16(1);
19103 let a = _mm_set1_epi8(2);
19104 let r = _mm256_mask_cvtepi8_epi16(src, 0, a);
19105 assert_eq_m256i(r, src);
19106 let r = _mm256_mask_cvtepi8_epi16(src, 0b11111111_11111111, a);
19107 let e = _mm256_set1_epi16(2);
19108 assert_eq_m256i(r, e);
19109 }
19110
19111 #[simd_test(enable = "avx512bw,avx512vl")]
19112 unsafe fn test_mm256_maskz_cvtepi8_epi16() {
19113 let a = _mm_set1_epi8(2);
19114 let r = _mm256_maskz_cvtepi8_epi16(0, a);
19115 assert_eq_m256i(r, _mm256_setzero_si256());
19116 let r = _mm256_maskz_cvtepi8_epi16(0b11111111_11111111, a);
19117 let e = _mm256_set1_epi16(2);
19118 assert_eq_m256i(r, e);
19119 }
19120
19121 #[simd_test(enable = "avx512bw,avx512vl")]
19122 unsafe fn test_mm_mask_cvtepi8_epi16() {
19123 let src = _mm_set1_epi16(1);
19124 let a = _mm_set1_epi8(2);
19125 let r = _mm_mask_cvtepi8_epi16(src, 0, a);
19126 assert_eq_m128i(r, src);
19127 let r = _mm_mask_cvtepi8_epi16(src, 0b11111111, a);
19128 let e = _mm_set1_epi16(2);
19129 assert_eq_m128i(r, e);
19130 }
19131
19132 #[simd_test(enable = "avx512bw,avx512vl")]
19133 unsafe fn test_mm_maskz_cvtepi8_epi16() {
19134 let a = _mm_set1_epi8(2);
19135 let r = _mm_maskz_cvtepi8_epi16(0, a);
19136 assert_eq_m128i(r, _mm_setzero_si128());
19137 let r = _mm_maskz_cvtepi8_epi16(0b11111111, a);
19138 let e = _mm_set1_epi16(2);
19139 assert_eq_m128i(r, e);
19140 }
19141
19142 #[simd_test(enable = "avx512bw")]
19143 unsafe fn test_mm512_cvtepu8_epi16() {
19144 let a = _mm256_set1_epi8(2);
19145 let r = _mm512_cvtepu8_epi16(a);
19146 let e = _mm512_set1_epi16(2);
19147 assert_eq_m512i(r, e);
19148 }
19149
19150 #[simd_test(enable = "avx512bw")]
19151 unsafe fn test_mm512_mask_cvtepu8_epi16() {
19152 let src = _mm512_set1_epi16(1);
19153 let a = _mm256_set1_epi8(2);
19154 let r = _mm512_mask_cvtepu8_epi16(src, 0, a);
19155 assert_eq_m512i(r, src);
19156 let r = _mm512_mask_cvtepu8_epi16(src, 0b11111111_11111111_11111111_11111111, a);
19157 let e = _mm512_set1_epi16(2);
19158 assert_eq_m512i(r, e);
19159 }
19160
19161 #[simd_test(enable = "avx512bw")]
19162 unsafe fn test_mm512_maskz_cvtepu8_epi16() {
19163 let a = _mm256_set1_epi8(2);
19164 let r = _mm512_maskz_cvtepu8_epi16(0, a);
19165 assert_eq_m512i(r, _mm512_setzero_si512());
19166 let r = _mm512_maskz_cvtepu8_epi16(0b11111111_11111111_11111111_11111111, a);
19167 let e = _mm512_set1_epi16(2);
19168 assert_eq_m512i(r, e);
19169 }
19170
19171 #[simd_test(enable = "avx512bw,avx512vl")]
19172 unsafe fn test_mm256_mask_cvtepu8_epi16() {
19173 let src = _mm256_set1_epi16(1);
19174 let a = _mm_set1_epi8(2);
19175 let r = _mm256_mask_cvtepu8_epi16(src, 0, a);
19176 assert_eq_m256i(r, src);
19177 let r = _mm256_mask_cvtepu8_epi16(src, 0b11111111_11111111, a);
19178 let e = _mm256_set1_epi16(2);
19179 assert_eq_m256i(r, e);
19180 }
19181
19182 #[simd_test(enable = "avx512bw,avx512vl")]
19183 unsafe fn test_mm256_maskz_cvtepu8_epi16() {
19184 let a = _mm_set1_epi8(2);
19185 let r = _mm256_maskz_cvtepu8_epi16(0, a);
19186 assert_eq_m256i(r, _mm256_setzero_si256());
19187 let r = _mm256_maskz_cvtepu8_epi16(0b11111111_11111111, a);
19188 let e = _mm256_set1_epi16(2);
19189 assert_eq_m256i(r, e);
19190 }
19191
19192 #[simd_test(enable = "avx512bw,avx512vl")]
19193 unsafe fn test_mm_mask_cvtepu8_epi16() {
19194 let src = _mm_set1_epi16(1);
19195 let a = _mm_set1_epi8(2);
19196 let r = _mm_mask_cvtepu8_epi16(src, 0, a);
19197 assert_eq_m128i(r, src);
19198 let r = _mm_mask_cvtepu8_epi16(src, 0b11111111, a);
19199 let e = _mm_set1_epi16(2);
19200 assert_eq_m128i(r, e);
19201 }
19202
19203 #[simd_test(enable = "avx512bw,avx512vl")]
19204 unsafe fn test_mm_maskz_cvtepu8_epi16() {
19205 let a = _mm_set1_epi8(2);
19206 let r = _mm_maskz_cvtepu8_epi16(0, a);
19207 assert_eq_m128i(r, _mm_setzero_si128());
19208 let r = _mm_maskz_cvtepu8_epi16(0b11111111, a);
19209 let e = _mm_set1_epi16(2);
19210 assert_eq_m128i(r, e);
19211 }
19212
19213 #[simd_test(enable = "avx512bw")]
19214 unsafe fn test_mm512_bslli_epi128() {
19215 #[rustfmt::skip]
19216 let a = _mm512_set_epi8(
19217 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19218 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19219 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19220 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19221 );
19222 let r = _mm512_bslli_epi128::<9>(a);
19223 #[rustfmt::skip]
19224 let e = _mm512_set_epi8(
19225 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
19226 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
19227 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
19228 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
19229 );
19230 assert_eq_m512i(r, e);
19231 }
19232
19233 #[simd_test(enable = "avx512bw")]
19234 unsafe fn test_mm512_bsrli_epi128() {
19235 #[rustfmt::skip]
19236 let a = _mm512_set_epi8(
19237 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
19238 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
19239 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
19240 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
19241 );
19242 let r = _mm512_bsrli_epi128::<3>(a);
19243 #[rustfmt::skip]
19244 let e = _mm512_set_epi8(
19245 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
19246 0, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
19247 0, 0, 0, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
19248 0, 0, 0, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
19249 );
19250 assert_eq_m512i(r, e);
19251 }
19252
19253 #[simd_test(enable = "avx512bw")]
19254 unsafe fn test_mm512_alignr_epi8() {
19255 #[rustfmt::skip]
19256 let a = _mm512_set_epi8(
19257 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19258 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19259 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19260 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19261 );
19262 let b = _mm512_set1_epi8(1);
19263 let r = _mm512_alignr_epi8::<14>(a, b);
19264 #[rustfmt::skip]
19265 let e = _mm512_set_epi8(
19266 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19267 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19268 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19269 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19270 );
19271 assert_eq_m512i(r, e);
19272 }
19273
19274 #[simd_test(enable = "avx512bw")]
19275 unsafe fn test_mm512_mask_alignr_epi8() {
19276 #[rustfmt::skip]
19277 let a = _mm512_set_epi8(
19278 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19279 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19280 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19281 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19282 );
19283 let b = _mm512_set1_epi8(1);
19284 let r = _mm512_mask_alignr_epi8::<14>(a, 0, a, b);
19285 assert_eq_m512i(r, a);
19286 let r = _mm512_mask_alignr_epi8::<14>(
19287 a,
19288 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
19289 a,
19290 b,
19291 );
19292 #[rustfmt::skip]
19293 let e = _mm512_set_epi8(
19294 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19295 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19296 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19297 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19298 );
19299 assert_eq_m512i(r, e);
19300 }
19301
19302 #[simd_test(enable = "avx512bw")]
19303 unsafe fn test_mm512_maskz_alignr_epi8() {
19304 #[rustfmt::skip]
19305 let a = _mm512_set_epi8(
19306 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19307 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19308 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19309 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19310 );
19311 let b = _mm512_set1_epi8(1);
19312 let r = _mm512_maskz_alignr_epi8::<14>(0, a, b);
19313 assert_eq_m512i(r, _mm512_setzero_si512());
19314 let r = _mm512_maskz_alignr_epi8::<14>(
19315 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111,
19316 a,
19317 b,
19318 );
19319 #[rustfmt::skip]
19320 let e = _mm512_set_epi8(
19321 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19322 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19323 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19324 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19325 );
19326 assert_eq_m512i(r, e);
19327 }
19328
19329 #[simd_test(enable = "avx512bw,avx512vl")]
19330 unsafe fn test_mm256_mask_alignr_epi8() {
19331 #[rustfmt::skip]
19332 let a = _mm256_set_epi8(
19333 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19334 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19335 );
19336 let b = _mm256_set1_epi8(1);
19337 let r = _mm256_mask_alignr_epi8::<14>(a, 0, a, b);
19338 assert_eq_m256i(r, a);
19339 let r = _mm256_mask_alignr_epi8::<14>(a, 0b11111111_11111111_11111111_11111111, a, b);
19340 #[rustfmt::skip]
19341 let e = _mm256_set_epi8(
19342 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19343 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19344 );
19345 assert_eq_m256i(r, e);
19346 }
19347
19348 #[simd_test(enable = "avx512bw,avx512vl")]
19349 unsafe fn test_mm256_maskz_alignr_epi8() {
19350 #[rustfmt::skip]
19351 let a = _mm256_set_epi8(
19352 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19353 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0,
19354 );
19355 let b = _mm256_set1_epi8(1);
19356 let r = _mm256_maskz_alignr_epi8::<14>(0, a, b);
19357 assert_eq_m256i(r, _mm256_setzero_si256());
19358 let r = _mm256_maskz_alignr_epi8::<14>(0b11111111_11111111_11111111_11111111, a, b);
19359 #[rustfmt::skip]
19360 let e = _mm256_set_epi8(
19361 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19362 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1,
19363 );
19364 assert_eq_m256i(r, e);
19365 }
19366
19367 #[simd_test(enable = "avx512bw,avx512vl")]
19368 unsafe fn test_mm_mask_alignr_epi8() {
19369 let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
19370 let b = _mm_set1_epi8(1);
19371 let r = _mm_mask_alignr_epi8::<14>(a, 0, a, b);
19372 assert_eq_m128i(r, a);
19373 let r = _mm_mask_alignr_epi8::<14>(a, 0b11111111_11111111, a, b);
19374 let e = _mm_set_epi8(0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1);
19375 assert_eq_m128i(r, e);
19376 }
19377
19378 #[simd_test(enable = "avx512bw,avx512vl")]
19379 unsafe fn test_mm_maskz_alignr_epi8() {
19380 let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
19381 let b = _mm_set1_epi8(1);
19382 let r = _mm_maskz_alignr_epi8::<14>(0, a, b);
19383 assert_eq_m128i(r, _mm_setzero_si128());
19384 let r = _mm_maskz_alignr_epi8::<14>(0b11111111_11111111, a, b);
19385 let e = _mm_set_epi8(0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1);
19386 assert_eq_m128i(r, e);
19387 }
19388
19389 #[simd_test(enable = "avx512bw")]
19390 unsafe fn test_mm512_mask_cvtsepi16_storeu_epi8() {
19391 let a = _mm512_set1_epi16(i16::MAX);
19392 let mut r = _mm256_undefined_si256();
19393 _mm512_mask_cvtsepi16_storeu_epi8(
19394 &mut r as *mut _ as *mut i8,
19395 0b11111111_11111111_11111111_11111111,
19396 a,
19397 );
19398 let e = _mm256_set1_epi8(i8::MAX);
19399 assert_eq_m256i(r, e);
19400 }
19401
19402 #[simd_test(enable = "avx512bw,avx512vl")]
19403 unsafe fn test_mm256_mask_cvtsepi16_storeu_epi8() {
19404 let a = _mm256_set1_epi16(i16::MAX);
19405 let mut r = _mm_undefined_si128();
19406 _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
19407 let e = _mm_set1_epi8(i8::MAX);
19408 assert_eq_m128i(r, e);
19409 }
19410
19411 #[simd_test(enable = "avx512bw,avx512vl")]
19412 unsafe fn test_mm_mask_cvtsepi16_storeu_epi8() {
19413 let a = _mm_set1_epi16(i16::MAX);
19414 let mut r = _mm_set1_epi8(0);
19415 _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
19416 #[rustfmt::skip]
19417 let e = _mm_set_epi8(
19418 0, 0, 0, 0, 0, 0, 0, 0,
19419 i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX, i8::MAX,
19420 );
19421 assert_eq_m128i(r, e);
19422 }
19423
19424 #[simd_test(enable = "avx512bw")]
19425 unsafe fn test_mm512_mask_cvtepi16_storeu_epi8() {
19426 let a = _mm512_set1_epi16(8);
19427 let mut r = _mm256_undefined_si256();
19428 _mm512_mask_cvtepi16_storeu_epi8(
19429 &mut r as *mut _ as *mut i8,
19430 0b11111111_11111111_11111111_11111111,
19431 a,
19432 );
19433 let e = _mm256_set1_epi8(8);
19434 assert_eq_m256i(r, e);
19435 }
19436
19437 #[simd_test(enable = "avx512bw,avx512vl")]
19438 unsafe fn test_mm256_mask_cvtepi16_storeu_epi8() {
19439 let a = _mm256_set1_epi16(8);
19440 let mut r = _mm_undefined_si128();
19441 _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
19442 let e = _mm_set1_epi8(8);
19443 assert_eq_m128i(r, e);
19444 }
19445
19446 #[simd_test(enable = "avx512bw,avx512vl")]
19447 unsafe fn test_mm_mask_cvtepi16_storeu_epi8() {
19448 let a = _mm_set1_epi16(8);
19449 let mut r = _mm_set1_epi8(0);
19450 _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
19451 let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8);
19452 assert_eq_m128i(r, e);
19453 }
19454
19455 #[simd_test(enable = "avx512bw")]
19456 unsafe fn test_mm512_mask_cvtusepi16_storeu_epi8() {
19457 let a = _mm512_set1_epi16(i16::MAX);
19458 let mut r = _mm256_undefined_si256();
19459 _mm512_mask_cvtusepi16_storeu_epi8(
19460 &mut r as *mut _ as *mut i8,
19461 0b11111111_11111111_11111111_11111111,
19462 a,
19463 );
19464 let e = _mm256_set1_epi8(u8::MAX as i8);
19465 assert_eq_m256i(r, e);
19466 }
19467
19468 #[simd_test(enable = "avx512bw,avx512vl")]
19469 unsafe fn test_mm256_mask_cvtusepi16_storeu_epi8() {
19470 let a = _mm256_set1_epi16(i16::MAX);
19471 let mut r = _mm_undefined_si128();
19472 _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
19473 let e = _mm_set1_epi8(u8::MAX as i8);
19474 assert_eq_m128i(r, e);
19475 }
19476
19477 #[simd_test(enable = "avx512bw,avx512vl")]
19478 unsafe fn test_mm_mask_cvtusepi16_storeu_epi8() {
19479 let a = _mm_set1_epi16(i16::MAX);
19480 let mut r = _mm_set1_epi8(0);
19481 _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
19482 #[rustfmt::skip]
19483 let e = _mm_set_epi8(
19484 0, 0, 0, 0,
19485 0, 0, 0, 0,
19486 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
19487 u8::MAX as i8, u8::MAX as i8, u8::MAX as i8, u8::MAX as i8,
19488 );
19489 assert_eq_m128i(r, e);
19490 }
19491}
19492