1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * arch/arm/mach-orion5x/common.c |
4 | * |
5 | * Core functions for Marvell Orion 5x SoCs |
6 | * |
7 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
8 | */ |
9 | |
10 | #include <linux/kernel.h> |
11 | #include <linux/init.h> |
12 | #include <linux/io.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/dma-mapping.h> |
15 | #include <linux/serial_8250.h> |
16 | #include <linux/mv643xx_i2c.h> |
17 | #include <linux/ata_platform.h> |
18 | #include <linux/delay.h> |
19 | #include <linux/clk-provider.h> |
20 | #include <linux/cpu.h> |
21 | #include <asm/page.h> |
22 | #include <asm/setup.h> |
23 | #include <asm/system_misc.h> |
24 | #include <asm/mach/arch.h> |
25 | #include <asm/mach/map.h> |
26 | #include <asm/mach/time.h> |
27 | #include <linux/platform_data/mtd-orion_nand.h> |
28 | #include <linux/platform_data/usb-ehci-orion.h> |
29 | #include <plat/time.h> |
30 | #include <plat/common.h> |
31 | |
32 | #include "bridge-regs.h" |
33 | #include "common.h" |
34 | #include "orion5x.h" |
35 | |
36 | /***************************************************************************** |
37 | * I/O Address Mapping |
38 | ****************************************************************************/ |
39 | static struct map_desc orion5x_io_desc[] __initdata = { |
40 | { |
41 | .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, |
42 | .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), |
43 | .length = ORION5X_REGS_SIZE, |
44 | .type = MT_DEVICE, |
45 | }, { |
46 | .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, |
47 | .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), |
48 | .length = ORION5X_PCIE_WA_SIZE, |
49 | .type = MT_DEVICE, |
50 | }, |
51 | }; |
52 | |
53 | void __init orion5x_map_io(void) |
54 | { |
55 | iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); |
56 | } |
57 | |
58 | |
59 | /***************************************************************************** |
60 | * CLK tree |
61 | ****************************************************************************/ |
62 | static struct clk *tclk; |
63 | |
64 | void __init clk_init(void) |
65 | { |
66 | tclk = clk_register_fixed_rate(NULL, name: "tclk" , NULL, flags: 0, fixed_rate: orion5x_tclk); |
67 | |
68 | orion_clkdev_init(tclk); |
69 | } |
70 | |
71 | /***************************************************************************** |
72 | * EHCI0 |
73 | ****************************************************************************/ |
74 | void __init orion5x_ehci0_init(void) |
75 | { |
76 | orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, |
77 | EHCI_PHY_ORION); |
78 | } |
79 | |
80 | |
81 | /***************************************************************************** |
82 | * EHCI1 |
83 | ****************************************************************************/ |
84 | void __init orion5x_ehci1_init(void) |
85 | { |
86 | orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL); |
87 | } |
88 | |
89 | |
90 | /***************************************************************************** |
91 | * GE00 |
92 | ****************************************************************************/ |
93 | void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) |
94 | { |
95 | orion_ge00_init(eth_data, |
96 | ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM, |
97 | IRQ_ORION5X_ETH_ERR, |
98 | MV643XX_TX_CSUM_DEFAULT_LIMIT); |
99 | } |
100 | |
101 | |
102 | /***************************************************************************** |
103 | * I2C |
104 | ****************************************************************************/ |
105 | void __init orion5x_i2c_init(void) |
106 | { |
107 | orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8); |
108 | |
109 | } |
110 | |
111 | |
112 | /***************************************************************************** |
113 | * SATA |
114 | ****************************************************************************/ |
115 | void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) |
116 | { |
117 | orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA); |
118 | } |
119 | |
120 | |
121 | /***************************************************************************** |
122 | * SPI |
123 | ****************************************************************************/ |
124 | void __init orion5x_spi_init(void) |
125 | { |
126 | orion_spi_init(SPI_PHYS_BASE); |
127 | } |
128 | |
129 | |
130 | /***************************************************************************** |
131 | * UART0 |
132 | ****************************************************************************/ |
133 | void __init orion5x_uart0_init(void) |
134 | { |
135 | orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, |
136 | IRQ_ORION5X_UART0, tclk); |
137 | } |
138 | |
139 | /***************************************************************************** |
140 | * UART1 |
141 | ****************************************************************************/ |
142 | void __init orion5x_uart1_init(void) |
143 | { |
144 | orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, |
145 | IRQ_ORION5X_UART1, tclk); |
146 | } |
147 | |
148 | /***************************************************************************** |
149 | * XOR engine |
150 | ****************************************************************************/ |
151 | void __init orion5x_xor_init(void) |
152 | { |
153 | orion_xor0_init(ORION5X_XOR_PHYS_BASE, |
154 | ORION5X_XOR_PHYS_BASE + 0x200, |
155 | IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1); |
156 | } |
157 | |
158 | /***************************************************************************** |
159 | * Cryptographic Engines and Security Accelerator (CESA) |
160 | ****************************************************************************/ |
161 | static void __init orion5x_crypto_init(void) |
162 | { |
163 | mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET, |
164 | ORION_MBUS_SRAM_ATTR, |
165 | ORION5X_SRAM_PHYS_BASE, |
166 | ORION5X_SRAM_SIZE); |
167 | orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, |
168 | SZ_8K, IRQ_ORION5X_CESA); |
169 | } |
170 | |
171 | /***************************************************************************** |
172 | * Watchdog |
173 | ****************************************************************************/ |
174 | static struct resource orion_wdt_resource[] = { |
175 | DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), |
176 | DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), |
177 | }; |
178 | |
179 | static struct platform_device orion_wdt_device = { |
180 | .name = "orion_wdt" , |
181 | .id = -1, |
182 | .num_resources = ARRAY_SIZE(orion_wdt_resource), |
183 | .resource = orion_wdt_resource, |
184 | }; |
185 | |
186 | static void __init orion5x_wdt_init(void) |
187 | { |
188 | platform_device_register(&orion_wdt_device); |
189 | } |
190 | |
191 | |
192 | /***************************************************************************** |
193 | * Time handling |
194 | ****************************************************************************/ |
195 | void __init orion5x_init_early(void) |
196 | { |
197 | u32 rev, dev; |
198 | const char *mbus_soc_name; |
199 | |
200 | orion_time_set_base(TIMER_VIRT_BASE); |
201 | |
202 | /* Initialize the MBUS driver */ |
203 | orion5x_pcie_id(dev: &dev, rev: &rev); |
204 | if (dev == MV88F5281_DEV_ID) |
205 | mbus_soc_name = "marvell,orion5x-88f5281-mbus" ; |
206 | else if (dev == MV88F5182_DEV_ID) |
207 | mbus_soc_name = "marvell,orion5x-88f5182-mbus" ; |
208 | else if (dev == MV88F5181_DEV_ID) |
209 | mbus_soc_name = "marvell,orion5x-88f5181-mbus" ; |
210 | else if (dev == MV88F6183_DEV_ID) |
211 | mbus_soc_name = "marvell,orion5x-88f6183-mbus" ; |
212 | else |
213 | mbus_soc_name = NULL; |
214 | mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE, |
215 | ORION5X_BRIDGE_WINS_SZ, |
216 | ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ); |
217 | } |
218 | |
219 | void orion5x_setup_wins(void) |
220 | { |
221 | /* |
222 | * The PCIe windows will no longer be statically allocated |
223 | * here once Orion5x is migrated to the pci-mvebu driver. |
224 | */ |
225 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET, |
226 | ORION_MBUS_PCIE_IO_ATTR, |
227 | ORION5X_PCIE_IO_PHYS_BASE, |
228 | ORION5X_PCIE_IO_SIZE, |
229 | ORION5X_PCIE_IO_BUS_BASE); |
230 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET, |
231 | ORION_MBUS_PCIE_MEM_ATTR, |
232 | ORION5X_PCIE_MEM_PHYS_BASE, |
233 | ORION5X_PCIE_MEM_SIZE); |
234 | mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET, |
235 | ORION_MBUS_PCI_IO_ATTR, |
236 | ORION5X_PCI_IO_PHYS_BASE, |
237 | ORION5X_PCI_IO_SIZE, |
238 | ORION5X_PCI_IO_BUS_BASE); |
239 | mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET, |
240 | ORION_MBUS_PCI_MEM_ATTR, |
241 | ORION5X_PCI_MEM_PHYS_BASE, |
242 | ORION5X_PCI_MEM_SIZE); |
243 | } |
244 | |
245 | int orion5x_tclk; |
246 | |
247 | static int __init orion5x_find_tclk(void) |
248 | { |
249 | u32 dev, rev; |
250 | |
251 | orion5x_pcie_id(dev: &dev, rev: &rev); |
252 | if (dev == MV88F6183_DEV_ID && |
253 | (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0) |
254 | return 133333333; |
255 | |
256 | return 166666667; |
257 | } |
258 | |
259 | void __init orion5x_timer_init(void) |
260 | { |
261 | orion5x_tclk = orion5x_find_tclk(); |
262 | |
263 | orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, |
264 | IRQ_ORION5X_BRIDGE, orion5x_tclk); |
265 | } |
266 | |
267 | |
268 | /***************************************************************************** |
269 | * General |
270 | ****************************************************************************/ |
271 | /* |
272 | * Identify device ID and rev from PCIe configuration header space '0'. |
273 | */ |
274 | void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) |
275 | { |
276 | orion5x_pcie_id(dev, rev); |
277 | |
278 | if (*dev == MV88F5281_DEV_ID) { |
279 | if (*rev == MV88F5281_REV_D2) { |
280 | *dev_name = "MV88F5281-D2" ; |
281 | } else if (*rev == MV88F5281_REV_D1) { |
282 | *dev_name = "MV88F5281-D1" ; |
283 | } else if (*rev == MV88F5281_REV_D0) { |
284 | *dev_name = "MV88F5281-D0" ; |
285 | } else { |
286 | *dev_name = "MV88F5281-Rev-Unsupported" ; |
287 | } |
288 | } else if (*dev == MV88F5182_DEV_ID) { |
289 | if (*rev == MV88F5182_REV_A2) { |
290 | *dev_name = "MV88F5182-A2" ; |
291 | } else { |
292 | *dev_name = "MV88F5182-Rev-Unsupported" ; |
293 | } |
294 | } else if (*dev == MV88F5181_DEV_ID) { |
295 | if (*rev == MV88F5181_REV_B1) { |
296 | *dev_name = "MV88F5181-Rev-B1" ; |
297 | } else if (*rev == MV88F5181L_REV_A1) { |
298 | *dev_name = "MV88F5181L-Rev-A1" ; |
299 | } else { |
300 | *dev_name = "MV88F5181(L)-Rev-Unsupported" ; |
301 | } |
302 | } else if (*dev == MV88F6183_DEV_ID) { |
303 | if (*rev == MV88F6183_REV_B0) { |
304 | *dev_name = "MV88F6183-Rev-B0" ; |
305 | } else { |
306 | *dev_name = "MV88F6183-Rev-Unsupported" ; |
307 | } |
308 | } else { |
309 | *dev_name = "Device-Unknown" ; |
310 | } |
311 | } |
312 | |
313 | void __init orion5x_init(void) |
314 | { |
315 | char *dev_name; |
316 | u32 dev, rev; |
317 | |
318 | orion5x_id(dev: &dev, rev: &rev, dev_name: &dev_name); |
319 | printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n" , dev_name, orion5x_tclk); |
320 | |
321 | /* |
322 | * Setup Orion address map |
323 | */ |
324 | orion5x_setup_wins(); |
325 | |
326 | /* Setup root of clk tree */ |
327 | clk_init(); |
328 | |
329 | /* |
330 | * Don't issue "Wait for Interrupt" instruction if we are |
331 | * running on D0 5281 silicon. |
332 | */ |
333 | if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) { |
334 | printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n" ); |
335 | cpu_idle_poll_ctrl(enable: true); |
336 | } |
337 | |
338 | /* |
339 | * The 5082/5181l/5182/6082/6082l/6183 have crypto |
340 | * while 5180n/5181/5281 don't have crypto. |
341 | */ |
342 | if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) || |
343 | dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID) |
344 | orion5x_crypto_init(); |
345 | |
346 | /* |
347 | * Register watchdog driver |
348 | */ |
349 | orion5x_wdt_init(); |
350 | } |
351 | |
352 | void orion5x_restart(enum reboot_mode mode, const char *cmd) |
353 | { |
354 | /* |
355 | * Enable and issue soft reset |
356 | */ |
357 | orion5x_setbits(RSTOUTn_MASK, (1 << 2)); |
358 | orion5x_setbits(CPU_SOFT_RESET, 1); |
359 | mdelay(200); |
360 | orion5x_clrbits(CPU_SOFT_RESET, 1); |
361 | } |
362 | |
363 | /* |
364 | * Many orion-based systems have buggy bootloader implementations. |
365 | * This is a common fixup for bogus memory tags. |
366 | */ |
367 | void __init tag_fixup_mem32(struct tag *t, char **from) |
368 | { |
369 | for (; t->hdr.size; t = tag_next(t)) |
370 | if (t->hdr.tag == ATAG_MEM && |
371 | (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK || |
372 | t->u.mem.start & ~PAGE_MASK)) { |
373 | printk(KERN_WARNING |
374 | "Clearing invalid memory bank %dKB@0x%08x\n" , |
375 | t->u.mem.size / 1024, t->u.mem.start); |
376 | t->hdr.tag = 0; |
377 | } |
378 | } |
379 | |