1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This file contains common routines for dealing with free of page tables
4 * Along with common page table handling code
5 *
6 * Derived from arch/powerpc/mm/tlb_64.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
12 *
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
15 *
16 * Dave Engebretsen <engebret@us.ibm.com>
17 * Rework for PPC64 port.
18 */
19
20#include <linux/kernel.h>
21#include <linux/gfp.h>
22#include <linux/mm.h>
23#include <linux/percpu.h>
24#include <linux/hardirq.h>
25#include <linux/hugetlb.h>
26#include <asm/tlbflush.h>
27#include <asm/tlb.h>
28#include <asm/hugetlb.h>
29#include <asm/pte-walk.h>
30
31#ifdef CONFIG_PPC64
32#define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD)
33#else
34#define PGD_ALIGN PAGE_SIZE
35#endif
36
37pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN);
38
39static inline int is_exec_fault(void)
40{
41 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
42}
43
44/* We only try to do i/d cache coherency on stuff that looks like
45 * reasonably "normal" PTEs. We currently require a PTE to be present
46 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
47 * on userspace PTEs
48 */
49static inline int pte_looks_normal(pte_t pte, unsigned long addr)
50{
51
52 if (pte_present(a: pte) && !pte_special(pte)) {
53 if (pte_ci(pte))
54 return 0;
55 if (!is_kernel_addr(addr))
56 return 1;
57 }
58 return 0;
59}
60
61static struct folio *maybe_pte_to_folio(pte_t pte)
62{
63 unsigned long pfn = pte_pfn(pte);
64 struct page *page;
65
66 if (unlikely(!pfn_valid(pfn)))
67 return NULL;
68 page = pfn_to_page(pfn);
69 if (PageReserved(page))
70 return NULL;
71 return page_folio(page);
72}
73
74#ifdef CONFIG_PPC_BOOK3S
75
76/* Server-style MMU handles coherency when hashing if HW exec permission
77 * is supposed per page (currently 64-bit only). If not, then, we always
78 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
79 * support falls into the same category.
80 */
81
82static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr)
83{
84 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
85 if (pte_looks_normal(pte, addr) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
86 cpu_has_feature(CPU_FTR_NOEXECUTE))) {
87 struct folio *folio = maybe_pte_to_folio(pte);
88 if (!folio)
89 return pte;
90 if (!test_bit(PG_dcache_clean, &folio->flags)) {
91 flush_dcache_icache_folio(folio);
92 set_bit(PG_dcache_clean, &folio->flags);
93 }
94 }
95 return pte;
96}
97
98#else /* CONFIG_PPC_BOOK3S */
99
100static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr) { return pte; }
101
102#endif /* CONFIG_PPC_BOOK3S */
103
104/* Embedded type MMU with HW exec support. This is a bit more complicated
105 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
106 * instead we "filter out" the exec permission for non clean pages.
107 *
108 * This is also called once for the folio. So only work with folio->flags here.
109 */
110static inline pte_t set_pte_filter(pte_t pte, unsigned long addr)
111{
112 struct folio *folio;
113
114 if (radix_enabled())
115 return pte;
116
117 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
118 return set_pte_filter_hash(pte, addr);
119
120 /* No exec permission in the first place, move on */
121 if (!pte_exec(pte) || !pte_looks_normal(pte, addr))
122 return pte;
123
124 /* If you set _PAGE_EXEC on weird pages you're on your own */
125 folio = maybe_pte_to_folio(pte);
126 if (unlikely(!folio))
127 return pte;
128
129 /* If the page clean, we move on */
130 if (test_bit(PG_dcache_clean, &folio->flags))
131 return pte;
132
133 /* If it's an exec fault, we flush the cache and make it clean */
134 if (is_exec_fault()) {
135 flush_dcache_icache_folio(folio);
136 set_bit(nr: PG_dcache_clean, addr: &folio->flags);
137 return pte;
138 }
139
140 /* Else, we filter out _PAGE_EXEC */
141 return pte_exprotect(pte);
142}
143
144static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
145 int dirty)
146{
147 struct folio *folio;
148
149 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
150 return pte;
151
152 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
153 return pte;
154
155 /* So here, we only care about exec faults, as we use them
156 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
157 * if necessary. Also if _PAGE_EXEC is already set, same deal,
158 * we just bail out
159 */
160 if (dirty || pte_exec(pte) || !is_exec_fault())
161 return pte;
162
163#ifdef CONFIG_DEBUG_VM
164 /* So this is an exec fault, _PAGE_EXEC is not set. If it was
165 * an error we would have bailed out earlier in do_page_fault()
166 * but let's make sure of it
167 */
168 if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
169 return pte;
170#endif /* CONFIG_DEBUG_VM */
171
172 /* If you set _PAGE_EXEC on weird pages you're on your own */
173 folio = maybe_pte_to_folio(pte);
174 if (unlikely(!folio))
175 goto bail;
176
177 /* If the page is already clean, we move on */
178 if (test_bit(PG_dcache_clean, &folio->flags))
179 goto bail;
180
181 /* Clean the page and set PG_dcache_clean */
182 flush_dcache_icache_folio(folio);
183 set_bit(nr: PG_dcache_clean, addr: &folio->flags);
184
185 bail:
186 return pte_mkexec(pte);
187}
188
189/*
190 * set_pte stores a linux PTE into the linux page table.
191 */
192void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
193 pte_t pte, unsigned int nr)
194{
195
196 /* Note: mm->context.id might not yet have been assigned as
197 * this context might not have been activated yet when this
198 * is called. Filter the pte value and use the filtered value
199 * to setup all the ptes in the range.
200 */
201 pte = set_pte_filter(pte, addr);
202
203 /*
204 * We don't need to call arch_enter/leave_lazy_mmu_mode()
205 * because we expect set_ptes to be only be used on not present
206 * and not hw_valid ptes. Hence there is no translation cache flush
207 * involved that need to be batched.
208 */
209 for (;;) {
210
211 /*
212 * Make sure hardware valid bit is not set. We don't do
213 * tlb flush for this update.
214 */
215 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
216
217 /* Perform the setting of the PTE */
218 __set_pte_at(mm, addr, ptep, pte, 0);
219 if (--nr == 0)
220 break;
221 ptep++;
222 addr += PAGE_SIZE;
223 pte = pte_next_pfn(pte);
224 }
225}
226
227void unmap_kernel_page(unsigned long va)
228{
229 pmd_t *pmdp = pmd_off_k(va);
230 pte_t *ptep = pte_offset_kernel(pmd: pmdp, address: va);
231
232 pte_clear(mm: &init_mm, addr: va, ptep);
233 flush_tlb_kernel_range(start: va, end: va + PAGE_SIZE);
234}
235
236/*
237 * This is called when relaxing access to a PTE. It's also called in the page
238 * fault path when we don't hit any of the major fault cases, ie, a minor
239 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
240 * handled those two for us, we additionally deal with missing execute
241 * permission here on some processors
242 */
243int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
244 pte_t *ptep, pte_t entry, int dirty)
245{
246 int changed;
247 entry = set_access_flags_filter(pte: entry, vma, dirty);
248 changed = !pte_same(a: *(ptep), b: entry);
249 if (changed) {
250 assert_pte_locked(vma->vm_mm, address);
251 __ptep_set_access_flags(vma, ptep, entry,
252 address, mmu_virtual_psize);
253 }
254 return changed;
255}
256
257#ifdef CONFIG_HUGETLB_PAGE
258int huge_ptep_set_access_flags(struct vm_area_struct *vma,
259 unsigned long addr, pte_t *ptep,
260 pte_t pte, int dirty)
261{
262#ifdef HUGETLB_NEED_PRELOAD
263 /*
264 * The "return 1" forces a call of update_mmu_cache, which will write a
265 * TLB entry. Without this, platforms that don't do a write of the TLB
266 * entry in the TLB miss handler asm will fault ad infinitum.
267 */
268 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
269 return 1;
270#else
271 int changed, psize;
272
273 pte = set_access_flags_filter(pte, vma, dirty);
274 changed = !pte_same(a: *(ptep), b: pte);
275 if (changed) {
276
277#ifdef CONFIG_PPC_BOOK3S_64
278 struct hstate *h = hstate_vma(vma);
279
280 psize = hstate_get_psize(h);
281#ifdef CONFIG_DEBUG_VM
282 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
283#endif
284
285#else
286 /*
287 * Not used on non book3s64 platforms.
288 * 8xx compares it with mmu_virtual_psize to
289 * know if it is a huge page or not.
290 */
291 psize = MMU_PAGE_COUNT;
292#endif
293 __ptep_set_access_flags(vma, ptep, pte, addr, psize);
294 }
295 return changed;
296#endif
297}
298
299#if defined(CONFIG_PPC_8xx)
300void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
301 pte_t pte, unsigned long sz)
302{
303 pmd_t *pmd = pmd_off(mm, addr);
304 pte_basic_t val;
305 pte_basic_t *entry = (pte_basic_t *)ptep;
306 int num, i;
307
308 /*
309 * Make sure hardware valid bit is not set. We don't do
310 * tlb flush for this update.
311 */
312 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
313
314 pte = set_pte_filter(pte, addr);
315
316 val = pte_val(pte);
317
318 num = number_of_cells_per_pte(pmd, val, 1);
319
320 for (i = 0; i < num; i++, entry++, val += SZ_4K)
321 *entry = val;
322}
323#endif
324#endif /* CONFIG_HUGETLB_PAGE */
325
326#ifdef CONFIG_DEBUG_VM
327void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
328{
329 pgd_t *pgd;
330 p4d_t *p4d;
331 pud_t *pud;
332 pmd_t *pmd;
333 pte_t *pte;
334 spinlock_t *ptl;
335
336 if (mm == &init_mm)
337 return;
338 pgd = mm->pgd + pgd_index(addr);
339 BUG_ON(pgd_none(*pgd));
340 p4d = p4d_offset(pgd, address: addr);
341 BUG_ON(p4d_none(*p4d));
342 pud = pud_offset(p4d, address: addr);
343 BUG_ON(pud_none(*pud));
344 pmd = pmd_offset(pud, address: addr);
345 /*
346 * khugepaged to collapse normal pages to hugepage, first set
347 * pmd to none to force page fault/gup to take mmap_lock. After
348 * pmd is set to none, we do a pte_clear which does this assertion
349 * so if we find pmd none, return.
350 */
351 if (pmd_none(pmd: *pmd))
352 return;
353 pte = pte_offset_map_nolock(mm, pmd, addr, ptlp: &ptl);
354 BUG_ON(!pte);
355 assert_spin_locked(ptl);
356 pte_unmap(pte);
357}
358#endif /* CONFIG_DEBUG_VM */
359
360unsigned long vmalloc_to_phys(void *va)
361{
362 unsigned long pfn = vmalloc_to_pfn(addr: va);
363
364 BUG_ON(!pfn);
365 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
366}
367EXPORT_SYMBOL_GPL(vmalloc_to_phys);
368
369/*
370 * We have 4 cases for pgds and pmds:
371 * (1) invalid (all zeroes)
372 * (2) pointer to next table, as normal; bottom 6 bits == 0
373 * (3) leaf pte for huge page _PAGE_PTE set
374 * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
375 *
376 * So long as we atomically load page table pointers we are safe against teardown,
377 * we can follow the address down to the page and take a ref on it.
378 * This function need to be called with interrupts disabled. We use this variant
379 * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
380 */
381pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
382 bool *is_thp, unsigned *hpage_shift)
383{
384 pgd_t *pgdp;
385 p4d_t p4d, *p4dp;
386 pud_t pud, *pudp;
387 pmd_t pmd, *pmdp;
388 pte_t *ret_pte;
389 hugepd_t *hpdp = NULL;
390 unsigned pdshift;
391
392 if (hpage_shift)
393 *hpage_shift = 0;
394
395 if (is_thp)
396 *is_thp = false;
397
398 /*
399 * Always operate on the local stack value. This make sure the
400 * value don't get updated by a parallel THP split/collapse,
401 * page fault or a page unmap. The return pte_t * is still not
402 * stable. So should be checked there for above conditions.
403 * Top level is an exception because it is folded into p4d.
404 */
405 pgdp = pgdir + pgd_index(ea);
406 p4dp = p4d_offset(pgd: pgdp, address: ea);
407 p4d = READ_ONCE(*p4dp);
408 pdshift = P4D_SHIFT;
409
410 if (p4d_none(p4d))
411 return NULL;
412
413 if (p4d_leaf(p4d)) {
414 ret_pte = (pte_t *)p4dp;
415 goto out;
416 }
417
418 if (is_hugepd(__hugepd(p4d_val(p4d)))) {
419 hpdp = (hugepd_t *)&p4d;
420 goto out_huge;
421 }
422
423 /*
424 * Even if we end up with an unmap, the pgtable will not
425 * be freed, because we do an rcu free and here we are
426 * irq disabled
427 */
428 pdshift = PUD_SHIFT;
429 pudp = pud_offset(p4d: &p4d, address: ea);
430 pud = READ_ONCE(*pudp);
431
432 if (pud_none(pud))
433 return NULL;
434
435 if (pud_leaf(pud)) {
436 ret_pte = (pte_t *)pudp;
437 goto out;
438 }
439
440 if (is_hugepd(__hugepd(pud_val(pud)))) {
441 hpdp = (hugepd_t *)&pud;
442 goto out_huge;
443 }
444
445 pdshift = PMD_SHIFT;
446 pmdp = pmd_offset(pud: &pud, address: ea);
447 pmd = READ_ONCE(*pmdp);
448
449 /*
450 * A hugepage collapse is captured by this condition, see
451 * pmdp_collapse_flush.
452 */
453 if (pmd_none(pmd))
454 return NULL;
455
456#ifdef CONFIG_PPC_BOOK3S_64
457 /*
458 * A hugepage split is captured by this condition, see
459 * pmdp_invalidate.
460 *
461 * Huge page modification can be caught here too.
462 */
463 if (pmd_is_serializing(pmd))
464 return NULL;
465#endif
466
467 if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
468 if (is_thp)
469 *is_thp = true;
470 ret_pte = (pte_t *)pmdp;
471 goto out;
472 }
473
474 if (pmd_leaf(pte: pmd)) {
475 ret_pte = (pte_t *)pmdp;
476 goto out;
477 }
478
479 if (is_hugepd(__hugepd(pmd_val(pmd)))) {
480 hpdp = (hugepd_t *)&pmd;
481 goto out_huge;
482 }
483
484 return pte_offset_kernel(pmd: &pmd, address: ea);
485
486out_huge:
487 if (!hpdp)
488 return NULL;
489
490 ret_pte = hugepte_offset(*hpdp, ea, pdshift);
491 pdshift = hugepd_shift(*hpdp);
492out:
493 if (hpage_shift)
494 *hpage_shift = pdshift;
495 return ret_pte;
496}
497EXPORT_SYMBOL_GPL(__find_linux_pte);
498
499/* Note due to the way vm flags are laid out, the bits are XWR */
500const pgprot_t protection_map[16] = {
501 [VM_NONE] = PAGE_NONE,
502 [VM_READ] = PAGE_READONLY,
503 [VM_WRITE] = PAGE_COPY,
504 [VM_WRITE | VM_READ] = PAGE_COPY,
505 [VM_EXEC] = PAGE_EXECONLY_X,
506 [VM_EXEC | VM_READ] = PAGE_READONLY_X,
507 [VM_EXEC | VM_WRITE] = PAGE_COPY_X,
508 [VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_X,
509 [VM_SHARED] = PAGE_NONE,
510 [VM_SHARED | VM_READ] = PAGE_READONLY,
511 [VM_SHARED | VM_WRITE] = PAGE_SHARED,
512 [VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED,
513 [VM_SHARED | VM_EXEC] = PAGE_EXECONLY_X,
514 [VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X,
515 [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_X,
516 [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X
517};
518
519#ifndef CONFIG_PPC_BOOK3S_64
520DECLARE_VM_GET_PAGE_PROT
521#endif
522

source code of linux/arch/powerpc/mm/pgtable.c