1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) |
7 | * |
8 | * (C) Copyright 2020 Hewlett Packard Enterprise Development LP |
9 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
10 | */ |
11 | #include <linux/crash_dump.h> |
12 | #include <linux/cpuhotplug.h> |
13 | #include <linux/cpumask.h> |
14 | #include <linux/proc_fs.h> |
15 | #include <linux/memory.h> |
16 | #include <linux/export.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/acpi.h> |
19 | #include <linux/efi.h> |
20 | |
21 | #include <asm/e820/api.h> |
22 | #include <asm/uv/uv_mmrs.h> |
23 | #include <asm/uv/uv_hub.h> |
24 | #include <asm/uv/bios.h> |
25 | #include <asm/uv/uv.h> |
26 | #include <asm/apic.h> |
27 | |
28 | #include "local.h" |
29 | |
30 | static enum uv_system_type uv_system_type; |
31 | static int uv_hubbed_system; |
32 | static int uv_hubless_system; |
33 | static u64 gru_start_paddr, gru_end_paddr; |
34 | static union uvh_apicid uvh_apicid; |
35 | static int uv_node_id; |
36 | |
37 | /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ |
38 | static u8 uv_archtype[UV_AT_SIZE + 1]; |
39 | static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; |
40 | static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; |
41 | |
42 | /* Information derived from CPUID and some UV MMRs */ |
43 | static struct { |
44 | unsigned int apicid_shift; |
45 | unsigned int apicid_mask; |
46 | unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ |
47 | unsigned int pnode_mask; |
48 | unsigned int nasid_shift; |
49 | unsigned int gpa_shift; |
50 | unsigned int gnode_shift; |
51 | unsigned int m_skt; |
52 | unsigned int n_skt; |
53 | } uv_cpuid; |
54 | |
55 | static int uv_min_hub_revision_id; |
56 | |
57 | static struct apic apic_x2apic_uv_x; |
58 | static struct uv_hub_info_s uv_hub_info_node0; |
59 | |
60 | /* Set this to use hardware error handler instead of kernel panic: */ |
61 | static int disable_uv_undefined_panic = 1; |
62 | |
63 | unsigned long uv_undefined(char *str) |
64 | { |
65 | if (likely(!disable_uv_undefined_panic)) |
66 | panic(fmt: "UV: error: undefined MMR: %s\n" , str); |
67 | else |
68 | pr_crit("UV: error: undefined MMR: %s\n" , str); |
69 | |
70 | /* Cause a machine fault: */ |
71 | return ~0ul; |
72 | } |
73 | EXPORT_SYMBOL(uv_undefined); |
74 | |
75 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
76 | { |
77 | unsigned long val, *mmr; |
78 | |
79 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, size: sizeof(*mmr)); |
80 | val = *mmr; |
81 | early_iounmap(addr: mmr, size: sizeof(*mmr)); |
82 | |
83 | return val; |
84 | } |
85 | |
86 | static inline bool is_GRU_range(u64 start, u64 end) |
87 | { |
88 | if (!gru_start_paddr) |
89 | return false; |
90 | |
91 | return start >= gru_start_paddr && end <= gru_end_paddr; |
92 | } |
93 | |
94 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
95 | { |
96 | return is_ISA_range(start, end) || is_GRU_range(start, end); |
97 | } |
98 | |
99 | static void __init early_get_pnodeid(void) |
100 | { |
101 | int pnode; |
102 | |
103 | uv_cpuid.m_skt = 0; |
104 | if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { |
105 | union uvh_rh10_gam_addr_map_config_u m_n_config; |
106 | |
107 | m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); |
108 | uv_cpuid.n_skt = m_n_config.s.n_skt; |
109 | uv_cpuid.nasid_shift = 0; |
110 | } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { |
111 | union uvh_rh_gam_addr_map_config_u m_n_config; |
112 | |
113 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); |
114 | uv_cpuid.n_skt = m_n_config.s.n_skt; |
115 | if (is_uv(UV3)) |
116 | uv_cpuid.m_skt = m_n_config.s3.m_skt; |
117 | if (is_uv(UV2)) |
118 | uv_cpuid.m_skt = m_n_config.s2.m_skt; |
119 | uv_cpuid.nasid_shift = 1; |
120 | } else { |
121 | unsigned long GAM_ADDR_MAP_CONFIG = 0; |
122 | |
123 | WARN(GAM_ADDR_MAP_CONFIG == 0, |
124 | "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n" ); |
125 | uv_cpuid.n_skt = 0; |
126 | uv_cpuid.nasid_shift = 0; |
127 | } |
128 | |
129 | if (is_uv(UV4|UVY)) |
130 | uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ |
131 | |
132 | uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; |
133 | pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; |
134 | uv_cpuid.gpa_shift = 46; /* Default unless changed */ |
135 | |
136 | pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n" , |
137 | uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); |
138 | } |
139 | |
140 | /* Running on a UV Hubbed system, determine which UV Hub Type it is */ |
141 | static int __init early_set_hub_type(void) |
142 | { |
143 | union uvh_node_id_u node_id; |
144 | |
145 | /* |
146 | * The NODE_ID MMR is always at offset 0. |
147 | * Contains the chip part # + revision. |
148 | * Node_id field started with 15 bits, |
149 | * ... now 7 but upper 8 are masked to 0. |
150 | * All blades/nodes have the same part # and hub revision. |
151 | */ |
152 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
153 | uv_node_id = node_id.sx.node_id; |
154 | |
155 | switch (node_id.s.part_number) { |
156 | |
157 | case UV5_HUB_PART_NUMBER: |
158 | uv_min_hub_revision_id = node_id.s.revision |
159 | + UV5_HUB_REVISION_BASE; |
160 | uv_hub_type_set(UV5); |
161 | break; |
162 | |
163 | /* UV4/4A only have a revision difference */ |
164 | case UV4_HUB_PART_NUMBER: |
165 | uv_min_hub_revision_id = node_id.s.revision |
166 | + UV4_HUB_REVISION_BASE - 1; |
167 | uv_hub_type_set(UV4); |
168 | if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) |
169 | uv_hub_type_set(UV4|UV4A); |
170 | break; |
171 | |
172 | case UV3_HUB_PART_NUMBER: |
173 | case UV3_HUB_PART_NUMBER_X: |
174 | uv_min_hub_revision_id = node_id.s.revision |
175 | + UV3_HUB_REVISION_BASE; |
176 | uv_hub_type_set(UV3); |
177 | break; |
178 | |
179 | case UV2_HUB_PART_NUMBER: |
180 | case UV2_HUB_PART_NUMBER_X: |
181 | uv_min_hub_revision_id = node_id.s.revision |
182 | + UV2_HUB_REVISION_BASE - 1; |
183 | uv_hub_type_set(UV2); |
184 | break; |
185 | |
186 | default: |
187 | return 0; |
188 | } |
189 | |
190 | pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n" , |
191 | node_id.s.part_number, node_id.s.revision, |
192 | uv_min_hub_revision_id, is_uv(~0)); |
193 | |
194 | return 1; |
195 | } |
196 | |
197 | static void __init uv_tsc_check_sync(void) |
198 | { |
199 | u64 mmr; |
200 | int sync_state; |
201 | int mmr_shift; |
202 | char *state; |
203 | |
204 | /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ |
205 | if (!is_uv(UV2|UV3|UV4)) { |
206 | mark_tsc_async_resets(reason: "UV5+" ); |
207 | return; |
208 | } |
209 | |
210 | /* UV2,3,4, UV BIOS TSC sync state available */ |
211 | mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); |
212 | mmr_shift = |
213 | is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; |
214 | sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; |
215 | |
216 | /* Check if TSC is valid for all sockets */ |
217 | switch (sync_state) { |
218 | case UVH_TSC_SYNC_VALID: |
219 | state = "in sync" ; |
220 | mark_tsc_async_resets(reason: "UV BIOS" ); |
221 | break; |
222 | |
223 | /* If BIOS state unknown, don't do anything */ |
224 | case UVH_TSC_SYNC_UNKNOWN: |
225 | state = "unknown" ; |
226 | break; |
227 | |
228 | /* Otherwise, BIOS indicates problem with TSC */ |
229 | default: |
230 | state = "unstable" ; |
231 | mark_tsc_unstable(reason: "UV BIOS" ); |
232 | break; |
233 | } |
234 | pr_info("UV: TSC sync state from BIOS:0%d(%s)\n" , sync_state, state); |
235 | } |
236 | |
237 | /* Selector for (4|4A|5) structs */ |
238 | #define uvxy_field(sname, field, undef) ( \ |
239 | is_uv(UV4A) ? sname.s4a.field : \ |
240 | is_uv(UV4) ? sname.s4.field : \ |
241 | is_uv(UV3) ? sname.s3.field : \ |
242 | undef) |
243 | |
244 | static void __init early_get_apic_socketid_shift(void) |
245 | { |
246 | unsigned int sid_shift = topology_get_domain_shift(dom: TOPO_PKG_DOMAIN); |
247 | |
248 | if (is_uv2_hub() || is_uv3_hub()) |
249 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
250 | |
251 | if (sid_shift) { |
252 | uv_cpuid.apicid_shift = 0; |
253 | uv_cpuid.apicid_mask = (~(-1 << sid_shift)); |
254 | uv_cpuid.socketid_shift = sid_shift; |
255 | } else { |
256 | pr_info("UV: CPU does not have valid CPUID.11\n" ); |
257 | } |
258 | |
259 | pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n" , uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); |
260 | pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n" , uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); |
261 | } |
262 | |
263 | static void __init uv_stringify(int len, char *to, char *from) |
264 | { |
265 | strscpy(to, from, len); |
266 | |
267 | /* Trim trailing spaces */ |
268 | (void)strim(to); |
269 | } |
270 | |
271 | /* Find UV arch type entry in UVsystab */ |
272 | static unsigned long __init early_find_archtype(struct uv_systab *st) |
273 | { |
274 | int i; |
275 | |
276 | for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { |
277 | unsigned long ptr = st->entry[i].offset; |
278 | |
279 | if (!ptr) |
280 | continue; |
281 | ptr += (unsigned long)st; |
282 | if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) |
283 | return ptr; |
284 | } |
285 | return 0; |
286 | } |
287 | |
288 | /* Validate UV arch type field in UVsystab */ |
289 | static int __init decode_arch_type(unsigned long ptr) |
290 | { |
291 | struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; |
292 | int n = strlen(uv_ate->archtype); |
293 | |
294 | if (n > 0 && n < sizeof(uv_ate->archtype)) { |
295 | pr_info("UV: UVarchtype received from BIOS\n" ); |
296 | uv_stringify(len: sizeof(uv_archtype), to: uv_archtype, from: uv_ate->archtype); |
297 | return 1; |
298 | } |
299 | return 0; |
300 | } |
301 | |
302 | /* Determine if UV arch type entry might exist in UVsystab */ |
303 | static int __init early_get_arch_type(void) |
304 | { |
305 | unsigned long uvst_physaddr, uvst_size, ptr; |
306 | struct uv_systab *st; |
307 | u32 rev; |
308 | int ret; |
309 | |
310 | uvst_physaddr = get_uv_systab_phys(msg: 0); |
311 | if (!uvst_physaddr) |
312 | return 0; |
313 | |
314 | st = early_memremap_ro(phys_addr: uvst_physaddr, size: sizeof(struct uv_systab)); |
315 | if (!st) { |
316 | pr_err("UV: Cannot access UVsystab, remap failed\n" ); |
317 | return 0; |
318 | } |
319 | |
320 | rev = st->revision; |
321 | if (rev < UV_SYSTAB_VERSION_UV5) { |
322 | early_memunmap(addr: st, size: sizeof(struct uv_systab)); |
323 | return 0; |
324 | } |
325 | |
326 | uvst_size = st->size; |
327 | early_memunmap(addr: st, size: sizeof(struct uv_systab)); |
328 | st = early_memremap_ro(phys_addr: uvst_physaddr, size: uvst_size); |
329 | if (!st) { |
330 | pr_err("UV: Cannot access UVarchtype, remap failed\n" ); |
331 | return 0; |
332 | } |
333 | |
334 | ptr = early_find_archtype(st); |
335 | if (!ptr) { |
336 | early_memunmap(addr: st, size: uvst_size); |
337 | return 0; |
338 | } |
339 | |
340 | ret = decode_arch_type(ptr); |
341 | early_memunmap(addr: st, size: uvst_size); |
342 | return ret; |
343 | } |
344 | |
345 | /* UV system found, check which APIC MODE BIOS already selected */ |
346 | static void __init early_set_apic_mode(void) |
347 | { |
348 | if (x2apic_enabled()) |
349 | uv_system_type = UV_X2APIC; |
350 | else |
351 | uv_system_type = UV_LEGACY_APIC; |
352 | } |
353 | |
354 | static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id) |
355 | { |
356 | /* Save OEM_ID passed from ACPI MADT */ |
357 | uv_stringify(len: sizeof(oem_id), to: oem_id, from: _oem_id); |
358 | |
359 | /* Check if BIOS sent us a UVarchtype */ |
360 | if (!early_get_arch_type()) |
361 | |
362 | /* If not use OEM ID for UVarchtype */ |
363 | uv_stringify(len: sizeof(uv_archtype), to: uv_archtype, from: oem_id); |
364 | |
365 | /* Check if not hubbed */ |
366 | if (strncmp(uv_archtype, "SGI" , 3) != 0) { |
367 | |
368 | /* (Not hubbed), check if not hubless */ |
369 | if (strncmp(uv_archtype, "NSGI" , 4) != 0) |
370 | |
371 | /* (Not hubless), not a UV */ |
372 | return 0; |
373 | |
374 | /* Is UV hubless system */ |
375 | uv_hubless_system = 0x01; |
376 | |
377 | /* UV5 Hubless */ |
378 | if (strncmp(uv_archtype, "NSGI5" , 5) == 0) |
379 | uv_hubless_system |= 0x20; |
380 | |
381 | /* UV4 Hubless: CH */ |
382 | else if (strncmp(uv_archtype, "NSGI4" , 5) == 0) |
383 | uv_hubless_system |= 0x10; |
384 | |
385 | /* UV3 Hubless: UV300/MC990X w/o hub */ |
386 | else |
387 | uv_hubless_system |= 0x8; |
388 | |
389 | /* Copy OEM Table ID */ |
390 | uv_stringify(len: sizeof(oem_table_id), to: oem_table_id, from: _oem_table_id); |
391 | |
392 | pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n" , |
393 | oem_id, oem_table_id, uv_system_type, uv_hubless_system); |
394 | |
395 | return 0; |
396 | } |
397 | |
398 | if (numa_off) { |
399 | pr_err("UV: NUMA is off, disabling UV support\n" ); |
400 | return 0; |
401 | } |
402 | |
403 | /* Set hubbed type if true */ |
404 | uv_hub_info->hub_revision = |
405 | !strncmp(uv_archtype, "SGI5" , 4) ? UV5_HUB_REVISION_BASE : |
406 | !strncmp(uv_archtype, "SGI4" , 4) ? UV4_HUB_REVISION_BASE : |
407 | !strncmp(uv_archtype, "SGI3" , 4) ? UV3_HUB_REVISION_BASE : |
408 | !strcmp(uv_archtype, "SGI2" ) ? UV2_HUB_REVISION_BASE : 0; |
409 | |
410 | switch (uv_hub_info->hub_revision) { |
411 | case UV5_HUB_REVISION_BASE: |
412 | uv_hubbed_system = 0x21; |
413 | uv_hub_type_set(UV5); |
414 | break; |
415 | |
416 | case UV4_HUB_REVISION_BASE: |
417 | uv_hubbed_system = 0x11; |
418 | uv_hub_type_set(UV4); |
419 | break; |
420 | |
421 | case UV3_HUB_REVISION_BASE: |
422 | uv_hubbed_system = 0x9; |
423 | uv_hub_type_set(UV3); |
424 | break; |
425 | |
426 | case UV2_HUB_REVISION_BASE: |
427 | uv_hubbed_system = 0x5; |
428 | uv_hub_type_set(UV2); |
429 | break; |
430 | |
431 | default: |
432 | return 0; |
433 | } |
434 | |
435 | /* Get UV hub chip part number & revision */ |
436 | early_set_hub_type(); |
437 | |
438 | /* Other UV setup functions */ |
439 | early_set_apic_mode(); |
440 | early_get_pnodeid(); |
441 | early_get_apic_socketid_shift(); |
442 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
443 | x86_platform.nmi_init = uv_nmi_init; |
444 | uv_tsc_check_sync(); |
445 | |
446 | return 1; |
447 | } |
448 | |
449 | /* Called early to probe for the correct APIC driver */ |
450 | static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) |
451 | { |
452 | /* Set up early hub info fields for Node 0 */ |
453 | uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; |
454 | |
455 | /* If not UV, return. */ |
456 | if (uv_set_system_type(_oem_id, _oem_table_id) == 0) |
457 | return 0; |
458 | |
459 | /* Save for display of the OEM Table ID */ |
460 | uv_stringify(len: sizeof(oem_table_id), to: oem_table_id, from: _oem_table_id); |
461 | |
462 | pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n" , |
463 | oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), |
464 | uv_min_hub_revision_id); |
465 | |
466 | return 0; |
467 | } |
468 | |
469 | enum uv_system_type get_uv_system_type(void) |
470 | { |
471 | return uv_system_type; |
472 | } |
473 | |
474 | int uv_get_hubless_system(void) |
475 | { |
476 | return uv_hubless_system; |
477 | } |
478 | EXPORT_SYMBOL_GPL(uv_get_hubless_system); |
479 | |
480 | ssize_t uv_get_archtype(char *buf, int len) |
481 | { |
482 | return scnprintf(buf, size: len, fmt: "%s/%s" , uv_archtype, oem_table_id); |
483 | } |
484 | EXPORT_SYMBOL_GPL(uv_get_archtype); |
485 | |
486 | int is_uv_system(void) |
487 | { |
488 | return uv_system_type != UV_NONE; |
489 | } |
490 | EXPORT_SYMBOL_GPL(is_uv_system); |
491 | |
492 | int is_uv_hubbed(int uvtype) |
493 | { |
494 | return (uv_hubbed_system & uvtype); |
495 | } |
496 | EXPORT_SYMBOL_GPL(is_uv_hubbed); |
497 | |
498 | static int is_uv_hubless(int uvtype) |
499 | { |
500 | return (uv_hubless_system & uvtype); |
501 | } |
502 | |
503 | void **__uv_hub_info_list; |
504 | EXPORT_SYMBOL_GPL(__uv_hub_info_list); |
505 | |
506 | DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); |
507 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); |
508 | |
509 | short uv_possible_blades; |
510 | EXPORT_SYMBOL_GPL(uv_possible_blades); |
511 | |
512 | unsigned long sn_rtc_cycles_per_second; |
513 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); |
514 | |
515 | /* The following values are used for the per node hub info struct */ |
516 | static __initdata unsigned short _min_socket, _max_socket; |
517 | static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; |
518 | static __initdata struct uv_gam_range_entry *uv_gre_table; |
519 | static __initdata struct uv_gam_parameters *uv_gp_table; |
520 | static __initdata unsigned short *_socket_to_node; |
521 | static __initdata unsigned short *_socket_to_pnode; |
522 | static __initdata unsigned short *_pnode_to_socket; |
523 | static __initdata unsigned short *_node_to_socket; |
524 | |
525 | static __initdata struct uv_gam_range_s *_gr_table; |
526 | |
527 | #define SOCK_EMPTY ((unsigned short)~0) |
528 | |
529 | /* Default UV memory block size is 2GB */ |
530 | static unsigned long mem_block_size __initdata = (2UL << 30); |
531 | |
532 | /* Kernel parameter to specify UV mem block size */ |
533 | static int __init parse_mem_block_size(char *ptr) |
534 | { |
535 | unsigned long size = memparse(ptr, NULL); |
536 | |
537 | /* Size will be rounded down by set_block_size() below */ |
538 | mem_block_size = size; |
539 | return 0; |
540 | } |
541 | early_param("uv_memblksize" , parse_mem_block_size); |
542 | |
543 | static __init int adj_blksize(u32 lgre) |
544 | { |
545 | unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; |
546 | unsigned long size; |
547 | |
548 | for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) |
549 | if (IS_ALIGNED(base, size)) |
550 | break; |
551 | |
552 | if (size >= mem_block_size) |
553 | return 0; |
554 | |
555 | mem_block_size = size; |
556 | return 1; |
557 | } |
558 | |
559 | static __init void set_block_size(void) |
560 | { |
561 | unsigned int order = ffs(mem_block_size); |
562 | |
563 | if (order) { |
564 | /* adjust for ffs return of 1..64 */ |
565 | set_memory_block_size_order(order - 1); |
566 | pr_info("UV: mem_block_size set to 0x%lx\n" , mem_block_size); |
567 | } else { |
568 | /* bad or zero value, default to 1UL << 31 (2GB) */ |
569 | pr_err("UV: mem_block_size error with 0x%lx\n" , mem_block_size); |
570 | set_memory_block_size_order(31); |
571 | } |
572 | } |
573 | |
574 | /* Build GAM range lookup table: */ |
575 | static __init void build_uv_gr_table(void) |
576 | { |
577 | struct uv_gam_range_entry *gre = uv_gre_table; |
578 | struct uv_gam_range_s *grt; |
579 | unsigned long last_limit = 0, ram_limit = 0; |
580 | int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; |
581 | |
582 | if (!gre) |
583 | return; |
584 | |
585 | bytes = _gr_table_len * sizeof(struct uv_gam_range_s); |
586 | grt = kzalloc(size: bytes, GFP_KERNEL); |
587 | if (WARN_ON_ONCE(!grt)) |
588 | return; |
589 | _gr_table = grt; |
590 | |
591 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { |
592 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { |
593 | if (!ram_limit) { |
594 | /* Mark hole between RAM/non-RAM: */ |
595 | ram_limit = last_limit; |
596 | last_limit = gre->limit; |
597 | lsid++; |
598 | continue; |
599 | } |
600 | last_limit = gre->limit; |
601 | pr_info("UV: extra hole in GAM RE table @%d\n" , (int)(gre - uv_gre_table)); |
602 | continue; |
603 | } |
604 | if (_max_socket < gre->sockid) { |
605 | pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n" , gre->sockid, _max_socket, (int)(gre - uv_gre_table)); |
606 | continue; |
607 | } |
608 | sid = gre->sockid - _min_socket; |
609 | if (lsid < sid) { |
610 | /* New range: */ |
611 | grt = &_gr_table[indx]; |
612 | grt->base = lindx; |
613 | grt->nasid = gre->nasid; |
614 | grt->limit = last_limit = gre->limit; |
615 | lsid = sid; |
616 | lindx = indx++; |
617 | continue; |
618 | } |
619 | /* Update range: */ |
620 | if (lsid == sid && !ram_limit) { |
621 | /* .. if contiguous: */ |
622 | if (grt->limit == last_limit) { |
623 | grt->limit = last_limit = gre->limit; |
624 | continue; |
625 | } |
626 | } |
627 | /* Non-contiguous RAM range: */ |
628 | if (!ram_limit) { |
629 | grt++; |
630 | grt->base = lindx; |
631 | grt->nasid = gre->nasid; |
632 | grt->limit = last_limit = gre->limit; |
633 | continue; |
634 | } |
635 | /* Non-contiguous/non-RAM: */ |
636 | grt++; |
637 | /* base is this entry */ |
638 | grt->base = grt - _gr_table; |
639 | grt->nasid = gre->nasid; |
640 | grt->limit = last_limit = gre->limit; |
641 | lsid++; |
642 | } |
643 | |
644 | /* Shorten table if possible */ |
645 | grt++; |
646 | i = grt - _gr_table; |
647 | if (i < _gr_table_len) { |
648 | void *ret; |
649 | |
650 | bytes = i * sizeof(struct uv_gam_range_s); |
651 | ret = krealloc(objp: _gr_table, new_size: bytes, GFP_KERNEL); |
652 | if (ret) { |
653 | _gr_table = ret; |
654 | _gr_table_len = i; |
655 | } |
656 | } |
657 | |
658 | /* Display resultant GAM range table: */ |
659 | for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { |
660 | unsigned long start, end; |
661 | int gb = grt->base; |
662 | |
663 | start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; |
664 | end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; |
665 | |
666 | pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n" , i, grt->nasid, start, end, gb); |
667 | } |
668 | } |
669 | |
670 | static int uv_wakeup_secondary(u32 phys_apicid, unsigned long start_rip) |
671 | { |
672 | unsigned long val; |
673 | int pnode; |
674 | |
675 | pnode = uv_apicid_to_pnode(apicid: phys_apicid); |
676 | |
677 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
678 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | |
679 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
680 | APIC_DM_INIT; |
681 | |
682 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
683 | |
684 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
685 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | |
686 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
687 | APIC_DM_STARTUP; |
688 | |
689 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
690 | |
691 | return 0; |
692 | } |
693 | |
694 | static void uv_send_IPI_one(int cpu, int vector) |
695 | { |
696 | unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); |
697 | int pnode = uv_apicid_to_pnode(apicid); |
698 | unsigned long dmode, val; |
699 | |
700 | if (vector == NMI_VECTOR) |
701 | dmode = APIC_DELIVERY_MODE_NMI; |
702 | else |
703 | dmode = APIC_DELIVERY_MODE_FIXED; |
704 | |
705 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
706 | (apicid << UVH_IPI_INT_APIC_ID_SHFT) | |
707 | (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | |
708 | (vector << UVH_IPI_INT_VECTOR_SHFT); |
709 | |
710 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
711 | } |
712 | |
713 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
714 | { |
715 | unsigned int cpu; |
716 | |
717 | for_each_cpu(cpu, mask) |
718 | uv_send_IPI_one(cpu, vector); |
719 | } |
720 | |
721 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
722 | { |
723 | unsigned int this_cpu = smp_processor_id(); |
724 | unsigned int cpu; |
725 | |
726 | for_each_cpu(cpu, mask) { |
727 | if (cpu != this_cpu) |
728 | uv_send_IPI_one(cpu, vector); |
729 | } |
730 | } |
731 | |
732 | static void uv_send_IPI_allbutself(int vector) |
733 | { |
734 | unsigned int this_cpu = smp_processor_id(); |
735 | unsigned int cpu; |
736 | |
737 | for_each_online_cpu(cpu) { |
738 | if (cpu != this_cpu) |
739 | uv_send_IPI_one(cpu, vector); |
740 | } |
741 | } |
742 | |
743 | static void uv_send_IPI_all(int vector) |
744 | { |
745 | uv_send_IPI_mask(cpu_online_mask, vector); |
746 | } |
747 | |
748 | static int uv_probe(void) |
749 | { |
750 | return apic == &apic_x2apic_uv_x; |
751 | } |
752 | |
753 | static struct apic apic_x2apic_uv_x __ro_after_init = { |
754 | |
755 | .name = "UV large system" , |
756 | .probe = uv_probe, |
757 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
758 | |
759 | .dest_mode_logical = false, |
760 | |
761 | .disable_esr = 0, |
762 | |
763 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
764 | |
765 | .max_apic_id = UINT_MAX, |
766 | .get_apic_id = x2apic_get_apic_id, |
767 | |
768 | .calc_dest_apicid = apic_default_calc_apicid, |
769 | |
770 | .send_IPI = uv_send_IPI_one, |
771 | .send_IPI_mask = uv_send_IPI_mask, |
772 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, |
773 | .send_IPI_allbutself = uv_send_IPI_allbutself, |
774 | .send_IPI_all = uv_send_IPI_all, |
775 | .send_IPI_self = x2apic_send_IPI_self, |
776 | |
777 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
778 | |
779 | .read = native_apic_msr_read, |
780 | .write = native_apic_msr_write, |
781 | .eoi = native_apic_msr_eoi, |
782 | .icr_read = native_x2apic_icr_read, |
783 | .icr_write = native_x2apic_icr_write, |
784 | }; |
785 | |
786 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 |
787 | #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT |
788 | |
789 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) |
790 | { |
791 | union uvh_rh_gam_alias_2_overlay_config_u alias; |
792 | union uvh_rh_gam_alias_2_redirect_config_u redirect; |
793 | unsigned long m_redirect; |
794 | unsigned long m_overlay; |
795 | int i; |
796 | |
797 | for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { |
798 | switch (i) { |
799 | case 0: |
800 | m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; |
801 | m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; |
802 | break; |
803 | case 1: |
804 | m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; |
805 | m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; |
806 | break; |
807 | case 2: |
808 | m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; |
809 | m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; |
810 | break; |
811 | } |
812 | alias.v = uv_read_local_mmr(offset: m_overlay); |
813 | if (alias.s.enable && alias.s.base == 0) { |
814 | *size = (1UL << alias.s.m_alias); |
815 | redirect.v = uv_read_local_mmr(offset: m_redirect); |
816 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; |
817 | return; |
818 | } |
819 | } |
820 | *base = *size = 0; |
821 | } |
822 | |
823 | enum map_type {map_wb, map_uc}; |
824 | static const char * const mt[] = { "WB" , "UC" }; |
825 | |
826 | static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) |
827 | { |
828 | unsigned long bytes, paddr; |
829 | |
830 | paddr = base << pshift; |
831 | bytes = (1UL << bshift) * (max_pnode + 1); |
832 | if (!paddr) { |
833 | pr_info("UV: Map %s_HI base address NULL\n" , id); |
834 | return; |
835 | } |
836 | if (map_type == map_uc) |
837 | init_extra_mapping_uc(phys: paddr, size: bytes); |
838 | else |
839 | init_extra_mapping_wb(phys: paddr, size: bytes); |
840 | |
841 | pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n" , |
842 | id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); |
843 | } |
844 | |
845 | static __init void map_gru_high(int max_pnode) |
846 | { |
847 | union uvh_rh_gam_gru_overlay_config_u gru; |
848 | unsigned long mask, base; |
849 | int shift; |
850 | |
851 | if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { |
852 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); |
853 | shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; |
854 | mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; |
855 | } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { |
856 | gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); |
857 | shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; |
858 | mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; |
859 | } else { |
860 | pr_err("UV: GRU unavailable (no MMR)\n" ); |
861 | return; |
862 | } |
863 | |
864 | if (!gru.s.enable) { |
865 | pr_info("UV: GRU disabled (by BIOS)\n" ); |
866 | return; |
867 | } |
868 | |
869 | base = (gru.v & mask) >> shift; |
870 | map_high(id: "GRU" , base, pshift: shift, bshift: shift, max_pnode, map_type: map_wb); |
871 | gru_start_paddr = ((u64)base << shift); |
872 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); |
873 | } |
874 | |
875 | static __init void map_mmr_high(int max_pnode) |
876 | { |
877 | unsigned long base; |
878 | int shift; |
879 | bool enable; |
880 | |
881 | if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { |
882 | union uvh_rh10_gam_mmr_overlay_config_u mmr; |
883 | |
884 | mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); |
885 | enable = mmr.s.enable; |
886 | base = mmr.s.base; |
887 | shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; |
888 | } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { |
889 | union uvh_rh_gam_mmr_overlay_config_u mmr; |
890 | |
891 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); |
892 | enable = mmr.s.enable; |
893 | base = mmr.s.base; |
894 | shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; |
895 | } else { |
896 | pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n" , |
897 | __func__); |
898 | return; |
899 | } |
900 | |
901 | if (enable) |
902 | map_high(id: "MMR" , base, pshift: shift, bshift: shift, max_pnode, map_type: map_uc); |
903 | else |
904 | pr_info("UV: MMR disabled\n" ); |
905 | } |
906 | |
907 | /* Arch specific ENUM cases */ |
908 | enum mmioh_arch { |
909 | UV2_MMIOH = -1, |
910 | UVY_MMIOH0, UVY_MMIOH1, |
911 | UVX_MMIOH0, UVX_MMIOH1, |
912 | }; |
913 | |
914 | /* Calculate and Map MMIOH Regions */ |
915 | static void __init calc_mmioh_map(enum mmioh_arch index, |
916 | int min_pnode, int max_pnode, |
917 | int shift, unsigned long base, int m_io, int n_io) |
918 | { |
919 | unsigned long mmr, nasid_mask; |
920 | int nasid, min_nasid, max_nasid, lnasid, mapped; |
921 | int i, fi, li, n, max_io; |
922 | char id[8]; |
923 | |
924 | /* One (UV2) mapping */ |
925 | if (index == UV2_MMIOH) { |
926 | strscpy(id, "MMIOH" , sizeof(id)); |
927 | max_io = max_pnode; |
928 | mapped = 0; |
929 | goto map_exit; |
930 | } |
931 | |
932 | /* small and large MMIOH mappings */ |
933 | switch (index) { |
934 | case UVY_MMIOH0: |
935 | mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; |
936 | nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; |
937 | n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; |
938 | min_nasid = min_pnode; |
939 | max_nasid = max_pnode; |
940 | mapped = 1; |
941 | break; |
942 | case UVY_MMIOH1: |
943 | mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; |
944 | nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; |
945 | n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; |
946 | min_nasid = min_pnode; |
947 | max_nasid = max_pnode; |
948 | mapped = 1; |
949 | break; |
950 | case UVX_MMIOH0: |
951 | mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; |
952 | nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; |
953 | n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; |
954 | min_nasid = min_pnode * 2; |
955 | max_nasid = max_pnode * 2; |
956 | mapped = 1; |
957 | break; |
958 | case UVX_MMIOH1: |
959 | mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; |
960 | nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; |
961 | n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; |
962 | min_nasid = min_pnode * 2; |
963 | max_nasid = max_pnode * 2; |
964 | mapped = 1; |
965 | break; |
966 | default: |
967 | pr_err("UV:%s:Invalid mapping type:%d\n" , __func__, index); |
968 | return; |
969 | } |
970 | |
971 | /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ |
972 | snprintf(buf: id, size: sizeof(id), fmt: "MMIOH%d" , index%2); |
973 | |
974 | max_io = lnasid = fi = li = -1; |
975 | for (i = 0; i < n; i++) { |
976 | unsigned long m_redirect = mmr + i * 8; |
977 | unsigned long redirect = uv_read_local_mmr(offset: m_redirect); |
978 | |
979 | nasid = redirect & nasid_mask; |
980 | if (i == 0) |
981 | pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n" , |
982 | id, redirect, m_redirect, nasid); |
983 | |
984 | /* Invalid NASID check */ |
985 | if (nasid < min_nasid || max_nasid < nasid) { |
986 | /* Not an error: unused table entries get "poison" values */ |
987 | pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n" , |
988 | __func__, index, nasid, min_nasid, max_nasid); |
989 | nasid = -1; |
990 | } |
991 | |
992 | if (nasid == lnasid) { |
993 | li = i; |
994 | /* Last entry check: */ |
995 | if (i != n-1) |
996 | continue; |
997 | } |
998 | |
999 | /* Check if we have a cached (or last) redirect to print: */ |
1000 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { |
1001 | unsigned long addr1, addr2; |
1002 | int f, l; |
1003 | |
1004 | if (lnasid == -1) { |
1005 | f = l = i; |
1006 | lnasid = nasid; |
1007 | } else { |
1008 | f = fi; |
1009 | l = li; |
1010 | } |
1011 | addr1 = (base << shift) + f * (1ULL << m_io); |
1012 | addr2 = (base << shift) + (l + 1) * (1ULL << m_io); |
1013 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n" , |
1014 | id, fi, li, lnasid, addr1, addr2); |
1015 | if (max_io < l) |
1016 | max_io = l; |
1017 | } |
1018 | fi = li = i; |
1019 | lnasid = nasid; |
1020 | } |
1021 | |
1022 | map_exit: |
1023 | pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n" , |
1024 | id, base, shift, m_io, max_io, max_pnode); |
1025 | |
1026 | if (max_io >= 0 && !mapped) |
1027 | map_high(id, base, pshift: shift, bshift: m_io, max_pnode: max_io, map_type: map_uc); |
1028 | } |
1029 | |
1030 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
1031 | { |
1032 | /* UVY flavor */ |
1033 | if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { |
1034 | union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; |
1035 | union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; |
1036 | |
1037 | mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); |
1038 | if (unlikely(mmioh0.s.enable == 0)) |
1039 | pr_info("UV: MMIOH0 disabled\n" ); |
1040 | else |
1041 | calc_mmioh_map(index: UVY_MMIOH0, min_pnode, max_pnode, |
1042 | UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, |
1043 | base: mmioh0.s.base, m_io: mmioh0.s.m_io, n_io: mmioh0.s.n_io); |
1044 | |
1045 | mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); |
1046 | if (unlikely(mmioh1.s.enable == 0)) |
1047 | pr_info("UV: MMIOH1 disabled\n" ); |
1048 | else |
1049 | calc_mmioh_map(index: UVY_MMIOH1, min_pnode, max_pnode, |
1050 | UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, |
1051 | base: mmioh1.s.base, m_io: mmioh1.s.m_io, n_io: mmioh1.s.n_io); |
1052 | return; |
1053 | } |
1054 | /* UVX flavor */ |
1055 | if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { |
1056 | union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; |
1057 | union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; |
1058 | |
1059 | mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); |
1060 | if (unlikely(mmioh0.s.enable == 0)) |
1061 | pr_info("UV: MMIOH0 disabled\n" ); |
1062 | else { |
1063 | unsigned long base = uvxy_field(mmioh0, base, 0); |
1064 | int m_io = uvxy_field(mmioh0, m_io, 0); |
1065 | int n_io = uvxy_field(mmioh0, n_io, 0); |
1066 | |
1067 | calc_mmioh_map(index: UVX_MMIOH0, min_pnode, max_pnode, |
1068 | UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, |
1069 | base, m_io, n_io); |
1070 | } |
1071 | |
1072 | mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); |
1073 | if (unlikely(mmioh1.s.enable == 0)) |
1074 | pr_info("UV: MMIOH1 disabled\n" ); |
1075 | else { |
1076 | unsigned long base = uvxy_field(mmioh1, base, 0); |
1077 | int m_io = uvxy_field(mmioh1, m_io, 0); |
1078 | int n_io = uvxy_field(mmioh1, n_io, 0); |
1079 | |
1080 | calc_mmioh_map(index: UVX_MMIOH1, min_pnode, max_pnode, |
1081 | UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, |
1082 | base, m_io, n_io); |
1083 | } |
1084 | return; |
1085 | } |
1086 | |
1087 | /* UV2 flavor */ |
1088 | if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { |
1089 | union uvh_rh_gam_mmioh_overlay_config_u mmioh; |
1090 | |
1091 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); |
1092 | if (unlikely(mmioh.s2.enable == 0)) |
1093 | pr_info("UV: MMIOH disabled\n" ); |
1094 | else |
1095 | calc_mmioh_map(index: UV2_MMIOH, min_pnode, max_pnode, |
1096 | UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, |
1097 | base: mmioh.s2.base, m_io: mmioh.s2.m_io, n_io: mmioh.s2.n_io); |
1098 | return; |
1099 | } |
1100 | } |
1101 | |
1102 | static __init void map_low_mmrs(void) |
1103 | { |
1104 | if (UV_GLOBAL_MMR32_BASE) |
1105 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); |
1106 | |
1107 | if (UV_LOCAL_MMR_BASE) |
1108 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); |
1109 | } |
1110 | |
1111 | static __init void uv_rtc_init(void) |
1112 | { |
1113 | long status; |
1114 | u64 ticks_per_sec; |
1115 | |
1116 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); |
1117 | |
1118 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { |
1119 | pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n" ); |
1120 | |
1121 | /* BIOS gives wrong value for clock frequency, so guess: */ |
1122 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; |
1123 | } else { |
1124 | sn_rtc_cycles_per_second = ticks_per_sec; |
1125 | } |
1126 | } |
1127 | |
1128 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
1129 | static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) |
1130 | { |
1131 | int domain, bus, rc; |
1132 | |
1133 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
1134 | return 0; |
1135 | |
1136 | if ((command_bits & PCI_COMMAND_IO) == 0) |
1137 | return 0; |
1138 | |
1139 | domain = pci_domain_nr(bus: pdev->bus); |
1140 | bus = pdev->bus->number; |
1141 | |
1142 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); |
1143 | |
1144 | return rc; |
1145 | } |
1146 | |
1147 | /* |
1148 | * Called on each CPU to initialize the per_cpu UV data area. |
1149 | * FIXME: hotplug not supported yet |
1150 | */ |
1151 | void uv_cpu_init(void) |
1152 | { |
1153 | /* CPU 0 initialization will be done via uv_system_init. */ |
1154 | if (smp_processor_id() == 0) |
1155 | return; |
1156 | |
1157 | uv_hub_info->nr_online_cpus++; |
1158 | } |
1159 | |
1160 | struct mn { |
1161 | unsigned char m_val; |
1162 | unsigned char n_val; |
1163 | unsigned char m_shift; |
1164 | unsigned char n_lshift; |
1165 | }; |
1166 | |
1167 | /* Initialize caller's MN struct and fill in values */ |
1168 | static void get_mn(struct mn *mnp) |
1169 | { |
1170 | memset(mnp, 0, sizeof(*mnp)); |
1171 | mnp->n_val = uv_cpuid.n_skt; |
1172 | if (is_uv(UV4|UVY)) { |
1173 | mnp->m_val = 0; |
1174 | mnp->n_lshift = 0; |
1175 | } else if (is_uv3_hub()) { |
1176 | union uvyh_gr0_gam_gr_config_u m_gr_config; |
1177 | |
1178 | mnp->m_val = uv_cpuid.m_skt; |
1179 | m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); |
1180 | mnp->n_lshift = m_gr_config.s3.m_skt; |
1181 | } else if (is_uv2_hub()) { |
1182 | mnp->m_val = uv_cpuid.m_skt; |
1183 | mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; |
1184 | } |
1185 | mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; |
1186 | } |
1187 | |
1188 | static void __init uv_init_hub_info(struct uv_hub_info_s *hi) |
1189 | { |
1190 | struct mn mn; |
1191 | |
1192 | get_mn(mnp: &mn); |
1193 | hi->gpa_mask = mn.m_val ? |
1194 | (1UL << (mn.m_val + mn.n_val)) - 1 : |
1195 | (1UL << uv_cpuid.gpa_shift) - 1; |
1196 | |
1197 | hi->m_val = mn.m_val; |
1198 | hi->n_val = mn.n_val; |
1199 | hi->m_shift = mn.m_shift; |
1200 | hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; |
1201 | hi->hub_revision = uv_hub_info->hub_revision; |
1202 | hi->hub_type = uv_hub_info->hub_type; |
1203 | hi->pnode_mask = uv_cpuid.pnode_mask; |
1204 | hi->nasid_shift = uv_cpuid.nasid_shift; |
1205 | hi->min_pnode = _min_pnode; |
1206 | hi->min_socket = _min_socket; |
1207 | hi->node_to_socket = _node_to_socket; |
1208 | hi->pnode_to_socket = _pnode_to_socket; |
1209 | hi->socket_to_node = _socket_to_node; |
1210 | hi->socket_to_pnode = _socket_to_pnode; |
1211 | hi->gr_table_len = _gr_table_len; |
1212 | hi->gr_table = _gr_table; |
1213 | |
1214 | uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); |
1215 | hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; |
1216 | if (mn.m_val) |
1217 | hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; |
1218 | |
1219 | if (uv_gp_table) { |
1220 | hi->global_mmr_base = uv_gp_table->mmr_base; |
1221 | hi->global_mmr_shift = uv_gp_table->mmr_shift; |
1222 | hi->global_gru_base = uv_gp_table->gru_base; |
1223 | hi->global_gru_shift = uv_gp_table->gru_shift; |
1224 | hi->gpa_shift = uv_gp_table->gpa_shift; |
1225 | hi->gpa_mask = (1UL << hi->gpa_shift) - 1; |
1226 | } else { |
1227 | hi->global_mmr_base = |
1228 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & |
1229 | ~UV_MMR_ENABLE; |
1230 | hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; |
1231 | } |
1232 | |
1233 | get_lowmem_redirect(base: &hi->lowmem_remap_base, size: &hi->lowmem_remap_top); |
1234 | |
1235 | hi->apic_pnode_shift = uv_cpuid.socketid_shift; |
1236 | |
1237 | /* Show system specific info: */ |
1238 | pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n" , hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); |
1239 | pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n" , hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); |
1240 | pr_info("UV: mmr_base/shift:0x%lx/%ld\n" , hi->global_mmr_base, hi->global_mmr_shift); |
1241 | if (hi->global_gru_base) |
1242 | pr_info("UV: gru_base/shift:0x%lx/%ld\n" , |
1243 | hi->global_gru_base, hi->global_gru_shift); |
1244 | |
1245 | pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n" , hi->gnode_upper, hi->gnode_extra); |
1246 | } |
1247 | |
1248 | static void __init decode_gam_params(unsigned long ptr) |
1249 | { |
1250 | uv_gp_table = (struct uv_gam_parameters *)ptr; |
1251 | |
1252 | pr_info("UV: GAM Params...\n" ); |
1253 | pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n" , |
1254 | uv_gp_table->mmr_base, uv_gp_table->mmr_shift, |
1255 | uv_gp_table->gru_base, uv_gp_table->gru_shift, |
1256 | uv_gp_table->gpa_shift); |
1257 | } |
1258 | |
1259 | static void __init decode_gam_rng_tbl(unsigned long ptr) |
1260 | { |
1261 | struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; |
1262 | unsigned long lgre = 0, gend = 0; |
1263 | int index = 0; |
1264 | int sock_min = INT_MAX, pnode_min = INT_MAX; |
1265 | int sock_max = -1, pnode_max = -1; |
1266 | |
1267 | uv_gre_table = gre; |
1268 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { |
1269 | unsigned long size = ((unsigned long)(gre->limit - lgre) |
1270 | << UV_GAM_RANGE_SHFT); |
1271 | int order = 0; |
1272 | char suffix[] = " KMGTPE" ; |
1273 | int flag = ' '; |
1274 | |
1275 | while (size > 9999 && order < sizeof(suffix)) { |
1276 | size /= 1024; |
1277 | order++; |
1278 | } |
1279 | |
1280 | /* adjust max block size to current range start */ |
1281 | if (gre->type == 1 || gre->type == 2) |
1282 | if (adj_blksize(lgre)) |
1283 | flag = '*'; |
1284 | |
1285 | if (!index) { |
1286 | pr_info("UV: GAM Range Table...\n" ); |
1287 | pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n" , "Range" , "" , "Size" , "Type" , "NASID" , "SID" , "PN" ); |
1288 | } |
1289 | pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n" , |
1290 | index++, |
1291 | (unsigned long)lgre << UV_GAM_RANGE_SHFT, |
1292 | (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, |
1293 | flag, size, suffix[order], |
1294 | gre->type, gre->nasid, gre->sockid, gre->pnode); |
1295 | |
1296 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) |
1297 | gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; |
1298 | |
1299 | /* update to next range start */ |
1300 | lgre = gre->limit; |
1301 | if (sock_min > gre->sockid) |
1302 | sock_min = gre->sockid; |
1303 | if (sock_max < gre->sockid) |
1304 | sock_max = gre->sockid; |
1305 | if (pnode_min > gre->pnode) |
1306 | pnode_min = gre->pnode; |
1307 | if (pnode_max < gre->pnode) |
1308 | pnode_max = gre->pnode; |
1309 | } |
1310 | _min_socket = sock_min; |
1311 | _max_socket = sock_max; |
1312 | _min_pnode = pnode_min; |
1313 | _max_pnode = pnode_max; |
1314 | _gr_table_len = index; |
1315 | |
1316 | pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n" , |
1317 | index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); |
1318 | } |
1319 | |
1320 | /* Walk through UVsystab decoding the fields */ |
1321 | static int __init decode_uv_systab(void) |
1322 | { |
1323 | struct uv_systab *st; |
1324 | int i; |
1325 | |
1326 | /* Get mapped UVsystab pointer */ |
1327 | st = uv_systab; |
1328 | |
1329 | /* If UVsystab is version 1, there is no extended UVsystab */ |
1330 | if (st && st->revision == UV_SYSTAB_VERSION_1) |
1331 | return 0; |
1332 | |
1333 | if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { |
1334 | int rev = st ? st->revision : 0; |
1335 | |
1336 | pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n" , |
1337 | rev, UV_SYSTAB_VERSION_UV4_LATEST); |
1338 | pr_err("UV: Does not support UV, switch to non-UV x86_64\n" ); |
1339 | uv_system_type = UV_NONE; |
1340 | |
1341 | return -EINVAL; |
1342 | } |
1343 | |
1344 | for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { |
1345 | unsigned long ptr = st->entry[i].offset; |
1346 | |
1347 | if (!ptr) |
1348 | continue; |
1349 | |
1350 | /* point to payload */ |
1351 | ptr += (unsigned long)st; |
1352 | |
1353 | switch (st->entry[i].type) { |
1354 | case UV_SYSTAB_TYPE_GAM_PARAMS: |
1355 | decode_gam_params(ptr); |
1356 | break; |
1357 | |
1358 | case UV_SYSTAB_TYPE_GAM_RNG_TBL: |
1359 | decode_gam_rng_tbl(ptr); |
1360 | break; |
1361 | |
1362 | case UV_SYSTAB_TYPE_ARCH_TYPE: |
1363 | /* already processed in early startup */ |
1364 | break; |
1365 | |
1366 | default: |
1367 | pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n" , |
1368 | __func__, st->entry[i].type); |
1369 | break; |
1370 | } |
1371 | } |
1372 | return 0; |
1373 | } |
1374 | |
1375 | /* |
1376 | * Given a bitmask 'bits' representing presnt blades, numbered |
1377 | * starting at 'base', masking off unused high bits of blade number |
1378 | * with 'mask', update the minimum and maximum blade numbers that we |
1379 | * have found. (Masking with 'mask' necessary because of BIOS |
1380 | * treatment of system partitioning when creating this table we are |
1381 | * interpreting.) |
1382 | */ |
1383 | static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max) |
1384 | { |
1385 | int first, last; |
1386 | |
1387 | if (!bits) |
1388 | return; |
1389 | first = (base + __ffs(bits)) & mask; |
1390 | last = (base + __fls(word: bits)) & mask; |
1391 | |
1392 | if (*min > first) |
1393 | *min = first; |
1394 | if (*max < last) |
1395 | *max = last; |
1396 | } |
1397 | |
1398 | /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ |
1399 | static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) |
1400 | { |
1401 | unsigned long np; |
1402 | int i, uv_pb = 0; |
1403 | int sock_min = INT_MAX, sock_max = -1, s_mask; |
1404 | |
1405 | s_mask = (1 << uv_cpuid.n_skt) - 1; |
1406 | |
1407 | if (UVH_NODE_PRESENT_TABLE) { |
1408 | pr_info("UV: NODE_PRESENT_DEPTH = %d\n" , |
1409 | UVH_NODE_PRESENT_TABLE_DEPTH); |
1410 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { |
1411 | np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); |
1412 | pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n" , i, np); |
1413 | blade_update_min_max(bits: np, base: i * 64, mask: s_mask, min: &sock_min, max: &sock_max); |
1414 | } |
1415 | } |
1416 | if (UVH_NODE_PRESENT_0) { |
1417 | np = uv_read_local_mmr(UVH_NODE_PRESENT_0); |
1418 | pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n" , np); |
1419 | blade_update_min_max(bits: np, base: 0, mask: s_mask, min: &sock_min, max: &sock_max); |
1420 | } |
1421 | if (UVH_NODE_PRESENT_1) { |
1422 | np = uv_read_local_mmr(UVH_NODE_PRESENT_1); |
1423 | pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n" , np); |
1424 | blade_update_min_max(bits: np, base: 64, mask: s_mask, min: &sock_min, max: &sock_max); |
1425 | } |
1426 | |
1427 | /* Only update if we actually found some bits indicating blades present */ |
1428 | if (sock_max >= sock_min) { |
1429 | _min_socket = sock_min; |
1430 | _max_socket = sock_max; |
1431 | uv_pb = sock_max - sock_min + 1; |
1432 | } |
1433 | if (uv_possible_blades != uv_pb) |
1434 | uv_possible_blades = uv_pb; |
1435 | |
1436 | pr_info("UV: number nodes/possible blades %d (%d - %d)\n" , |
1437 | uv_pb, sock_min, sock_max); |
1438 | } |
1439 | |
1440 | static int __init alloc_conv_table(int num_elem, unsigned short **table) |
1441 | { |
1442 | int i; |
1443 | size_t bytes; |
1444 | |
1445 | bytes = num_elem * sizeof(*table[0]); |
1446 | *table = kmalloc(size: bytes, GFP_KERNEL); |
1447 | if (WARN_ON_ONCE(!*table)) |
1448 | return -ENOMEM; |
1449 | for (i = 0; i < num_elem; i++) |
1450 | ((unsigned short *)*table)[i] = SOCK_EMPTY; |
1451 | return 0; |
1452 | } |
1453 | |
1454 | /* Remove conversion table if it's 1:1 */ |
1455 | #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2) |
1456 | |
1457 | static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2) |
1458 | { |
1459 | int i; |
1460 | unsigned short *table = *tp; |
1461 | |
1462 | if (table == NULL) |
1463 | return; |
1464 | if (max != max2) |
1465 | return; |
1466 | for (i = 0; i < max; i++) { |
1467 | if (i != table[i]) |
1468 | return; |
1469 | } |
1470 | kfree(objp: table); |
1471 | *tp = NULL; |
1472 | pr_info("UV: %s is 1:1, conversion table removed\n" , tname); |
1473 | } |
1474 | |
1475 | /* |
1476 | * Build Socket Tables |
1477 | * If the number of nodes is >1 per socket, socket to node table will |
1478 | * contain lowest node number on that socket. |
1479 | */ |
1480 | static void __init build_socket_tables(void) |
1481 | { |
1482 | struct uv_gam_range_entry *gre = uv_gre_table; |
1483 | int nums, numn, nump; |
1484 | int i, lnid, apicid; |
1485 | int minsock = _min_socket; |
1486 | int maxsock = _max_socket; |
1487 | int minpnode = _min_pnode; |
1488 | int maxpnode = _max_pnode; |
1489 | |
1490 | if (!gre) { |
1491 | if (is_uv2_hub() || is_uv3_hub()) { |
1492 | pr_info("UV: No UVsystab socket table, ignoring\n" ); |
1493 | return; |
1494 | } |
1495 | pr_err("UV: Error: UVsystab address translations not available!\n" ); |
1496 | WARN_ON_ONCE(!gre); |
1497 | return; |
1498 | } |
1499 | |
1500 | numn = num_possible_nodes(); |
1501 | nump = maxpnode - minpnode + 1; |
1502 | nums = maxsock - minsock + 1; |
1503 | |
1504 | /* Allocate and clear tables */ |
1505 | if ((alloc_conv_table(num_elem: nump, table: &_pnode_to_socket) < 0) |
1506 | || (alloc_conv_table(num_elem: nums, table: &_socket_to_pnode) < 0) |
1507 | || (alloc_conv_table(num_elem: numn, table: &_node_to_socket) < 0) |
1508 | || (alloc_conv_table(num_elem: nums, table: &_socket_to_node) < 0)) { |
1509 | kfree(objp: _pnode_to_socket); |
1510 | kfree(objp: _socket_to_pnode); |
1511 | kfree(objp: _node_to_socket); |
1512 | return; |
1513 | } |
1514 | |
1515 | /* Fill in pnode/node/addr conversion list values: */ |
1516 | for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { |
1517 | if (gre->type == UV_GAM_RANGE_TYPE_HOLE) |
1518 | continue; |
1519 | i = gre->sockid - minsock; |
1520 | if (_socket_to_pnode[i] == SOCK_EMPTY) |
1521 | _socket_to_pnode[i] = gre->pnode; |
1522 | |
1523 | i = gre->pnode - minpnode; |
1524 | if (_pnode_to_socket[i] == SOCK_EMPTY) |
1525 | _pnode_to_socket[i] = gre->sockid; |
1526 | |
1527 | pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n" , |
1528 | gre->sockid, gre->type, gre->nasid, |
1529 | _socket_to_pnode[gre->sockid - minsock], |
1530 | _pnode_to_socket[gre->pnode - minpnode]); |
1531 | } |
1532 | |
1533 | /* Set socket -> node values: */ |
1534 | lnid = NUMA_NO_NODE; |
1535 | for (apicid = 0; apicid < ARRAY_SIZE(__apicid_to_node); apicid++) { |
1536 | int nid = __apicid_to_node[apicid]; |
1537 | int sockid; |
1538 | |
1539 | if ((nid == NUMA_NO_NODE) || (lnid == nid)) |
1540 | continue; |
1541 | lnid = nid; |
1542 | |
1543 | sockid = apicid >> uv_cpuid.socketid_shift; |
1544 | |
1545 | if (_socket_to_node[sockid - minsock] == SOCK_EMPTY) |
1546 | _socket_to_node[sockid - minsock] = nid; |
1547 | |
1548 | if (_node_to_socket[nid] == SOCK_EMPTY) |
1549 | _node_to_socket[nid] = sockid; |
1550 | |
1551 | pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n" , |
1552 | sockid, |
1553 | apicid, |
1554 | _node_to_socket[nid], |
1555 | nid, |
1556 | _socket_to_node[sockid - minsock]); |
1557 | } |
1558 | |
1559 | /* |
1560 | * If e.g. socket id == pnode for all pnodes, |
1561 | * system runs faster by removing corresponding conversion table. |
1562 | */ |
1563 | FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn); |
1564 | FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn); |
1565 | FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump); |
1566 | FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump); |
1567 | } |
1568 | |
1569 | /* Check which reboot to use */ |
1570 | static void check_efi_reboot(void) |
1571 | { |
1572 | /* If EFI reboot not available, use ACPI reboot */ |
1573 | if (!efi_enabled(EFI_BOOT)) |
1574 | reboot_type = BOOT_ACPI; |
1575 | } |
1576 | |
1577 | /* |
1578 | * User proc fs file handling now deprecated. |
1579 | * Recommend using /sys/firmware/sgi_uv/... instead. |
1580 | */ |
1581 | static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) |
1582 | { |
1583 | pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n" , |
1584 | current->comm); |
1585 | seq_printf(m: file, fmt: "0x%x\n" , uv_hubbed_system); |
1586 | return 0; |
1587 | } |
1588 | |
1589 | static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) |
1590 | { |
1591 | pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n" , |
1592 | current->comm); |
1593 | seq_printf(m: file, fmt: "0x%x\n" , uv_hubless_system); |
1594 | return 0; |
1595 | } |
1596 | |
1597 | static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) |
1598 | { |
1599 | pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n" , |
1600 | current->comm); |
1601 | seq_printf(m: file, fmt: "%s/%s\n" , uv_archtype, oem_table_id); |
1602 | return 0; |
1603 | } |
1604 | |
1605 | static __init void uv_setup_proc_files(int hubless) |
1606 | { |
1607 | struct proc_dir_entry *pde; |
1608 | |
1609 | pde = proc_mkdir(UV_PROC_NODE, NULL); |
1610 | proc_create_single("archtype" , 0, pde, proc_archtype_show); |
1611 | if (hubless) |
1612 | proc_create_single("hubless" , 0, pde, proc_hubless_show); |
1613 | else |
1614 | proc_create_single("hubbed" , 0, pde, proc_hubbed_show); |
1615 | } |
1616 | |
1617 | /* Initialize UV hubless systems */ |
1618 | static __init int uv_system_init_hubless(void) |
1619 | { |
1620 | int rc; |
1621 | |
1622 | /* Setup PCH NMI handler */ |
1623 | uv_nmi_setup_hubless(); |
1624 | |
1625 | /* Init kernel/BIOS interface */ |
1626 | rc = uv_bios_init(); |
1627 | if (rc < 0) |
1628 | return rc; |
1629 | |
1630 | /* Process UVsystab */ |
1631 | rc = decode_uv_systab(); |
1632 | if (rc < 0) |
1633 | return rc; |
1634 | |
1635 | /* Set section block size for current node memory */ |
1636 | set_block_size(); |
1637 | |
1638 | /* Create user access node */ |
1639 | if (rc >= 0) |
1640 | uv_setup_proc_files(hubless: 1); |
1641 | |
1642 | check_efi_reboot(); |
1643 | |
1644 | return rc; |
1645 | } |
1646 | |
1647 | static void __init uv_system_init_hub(void) |
1648 | { |
1649 | struct uv_hub_info_s hub_info = {0}; |
1650 | int bytes, cpu, nodeid, bid; |
1651 | unsigned short min_pnode = USHRT_MAX, max_pnode = 0; |
1652 | char *hub = is_uv5_hub() ? "UV500" : |
1653 | is_uv4_hub() ? "UV400" : |
1654 | is_uv3_hub() ? "UV300" : |
1655 | is_uv2_hub() ? "UV2000/3000" : NULL; |
1656 | struct uv_hub_info_s **uv_hub_info_list_blade; |
1657 | |
1658 | if (!hub) { |
1659 | pr_err("UV: Unknown/unsupported UV hub\n" ); |
1660 | return; |
1661 | } |
1662 | pr_info("UV: Found %s hub\n" , hub); |
1663 | |
1664 | map_low_mmrs(); |
1665 | |
1666 | /* Get uv_systab for decoding, setup UV BIOS calls */ |
1667 | uv_bios_init(); |
1668 | |
1669 | /* If there's an UVsystab problem then abort UV init: */ |
1670 | if (decode_uv_systab() < 0) { |
1671 | pr_err("UV: Mangled UVsystab format\n" ); |
1672 | return; |
1673 | } |
1674 | |
1675 | build_socket_tables(); |
1676 | build_uv_gr_table(); |
1677 | set_block_size(); |
1678 | uv_init_hub_info(hi: &hub_info); |
1679 | /* If UV2 or UV3 may need to get # blades from HW */ |
1680 | if (is_uv(UV2|UV3) && !uv_gre_table) |
1681 | boot_init_possible_blades(hub_info: &hub_info); |
1682 | else |
1683 | /* min/max sockets set in decode_gam_rng_tbl */ |
1684 | uv_possible_blades = (_max_socket - _min_socket) + 1; |
1685 | |
1686 | /* uv_num_possible_blades() is really the hub count: */ |
1687 | pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n" , uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); |
1688 | |
1689 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); |
1690 | hub_info.coherency_domain_number = sn_coherency_id; |
1691 | uv_rtc_init(); |
1692 | |
1693 | /* |
1694 | * __uv_hub_info_list[] is indexed by node, but there is only |
1695 | * one hub_info structure per blade. First, allocate one |
1696 | * structure per blade. Further down we create a per-node |
1697 | * table (__uv_hub_info_list[]) pointing to hub_info |
1698 | * structures for the correct blade. |
1699 | */ |
1700 | |
1701 | bytes = sizeof(void *) * uv_num_possible_blades(); |
1702 | uv_hub_info_list_blade = kzalloc(size: bytes, GFP_KERNEL); |
1703 | if (WARN_ON_ONCE(!uv_hub_info_list_blade)) |
1704 | return; |
1705 | |
1706 | bytes = sizeof(struct uv_hub_info_s); |
1707 | for_each_possible_blade(bid) { |
1708 | struct uv_hub_info_s *new_hub; |
1709 | |
1710 | /* Allocate & fill new per hub info list */ |
1711 | new_hub = (bid == 0) ? &uv_hub_info_node0 |
1712 | : kzalloc_node(size: bytes, GFP_KERNEL, node: uv_blade_to_node(blade: bid)); |
1713 | if (WARN_ON_ONCE(!new_hub)) { |
1714 | /* do not kfree() bid 0, which is statically allocated */ |
1715 | while (--bid > 0) |
1716 | kfree(objp: uv_hub_info_list_blade[bid]); |
1717 | kfree(objp: uv_hub_info_list_blade); |
1718 | return; |
1719 | } |
1720 | |
1721 | uv_hub_info_list_blade[bid] = new_hub; |
1722 | *new_hub = hub_info; |
1723 | |
1724 | /* Use information from GAM table if available: */ |
1725 | if (uv_gre_table) |
1726 | new_hub->pnode = uv_blade_to_pnode(bid); |
1727 | else /* Or fill in during CPU loop: */ |
1728 | new_hub->pnode = 0xffff; |
1729 | |
1730 | new_hub->numa_blade_id = bid; |
1731 | new_hub->memory_nid = NUMA_NO_NODE; |
1732 | new_hub->nr_possible_cpus = 0; |
1733 | new_hub->nr_online_cpus = 0; |
1734 | } |
1735 | |
1736 | /* |
1737 | * Now populate __uv_hub_info_list[] for each node with the |
1738 | * pointer to the struct for the blade it resides on. |
1739 | */ |
1740 | |
1741 | bytes = sizeof(void *) * num_possible_nodes(); |
1742 | __uv_hub_info_list = kzalloc(size: bytes, GFP_KERNEL); |
1743 | if (WARN_ON_ONCE(!__uv_hub_info_list)) { |
1744 | for_each_possible_blade(bid) |
1745 | /* bid 0 is statically allocated */ |
1746 | if (bid != 0) |
1747 | kfree(objp: uv_hub_info_list_blade[bid]); |
1748 | kfree(objp: uv_hub_info_list_blade); |
1749 | return; |
1750 | } |
1751 | |
1752 | for_each_node(nodeid) |
1753 | __uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nid: nodeid)]; |
1754 | |
1755 | /* Initialize per CPU info: */ |
1756 | for_each_possible_cpu(cpu) { |
1757 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
1758 | unsigned short bid; |
1759 | unsigned short pnode; |
1760 | |
1761 | pnode = uv_apicid_to_pnode(apicid); |
1762 | bid = uv_pnode_to_socket(pnode) - _min_socket; |
1763 | |
1764 | uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid]; |
1765 | uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; |
1766 | if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) |
1767 | uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); |
1768 | |
1769 | if (uv_cpu_hub_info(cpu)->pnode == 0xffff) |
1770 | uv_cpu_hub_info(cpu)->pnode = pnode; |
1771 | } |
1772 | |
1773 | for_each_possible_blade(bid) { |
1774 | unsigned short pnode = uv_hub_info_list_blade[bid]->pnode; |
1775 | |
1776 | if (pnode == 0xffff) |
1777 | continue; |
1778 | |
1779 | min_pnode = min(pnode, min_pnode); |
1780 | max_pnode = max(pnode, max_pnode); |
1781 | pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n" , |
1782 | bid, |
1783 | uv_hub_info_list_blade[bid]->pnode, |
1784 | uv_hub_info_list_blade[bid]->nr_possible_cpus); |
1785 | } |
1786 | |
1787 | pr_info("UV: min_pnode:%02x max_pnode:%02x\n" , min_pnode, max_pnode); |
1788 | map_gru_high(max_pnode); |
1789 | map_mmr_high(max_pnode); |
1790 | map_mmioh_high(min_pnode, max_pnode); |
1791 | |
1792 | kfree(objp: uv_hub_info_list_blade); |
1793 | uv_hub_info_list_blade = NULL; |
1794 | |
1795 | uv_nmi_setup(); |
1796 | uv_cpu_init(); |
1797 | uv_setup_proc_files(hubless: 0); |
1798 | |
1799 | /* Register Legacy VGA I/O redirection handler: */ |
1800 | pci_register_set_vga_state(func: uv_set_vga_state); |
1801 | |
1802 | check_efi_reboot(); |
1803 | } |
1804 | |
1805 | /* |
1806 | * There is a different code path needed to initialize a UV system that does |
1807 | * not have a "UV HUB" (referred to as "hubless"). |
1808 | */ |
1809 | void __init uv_system_init(void) |
1810 | { |
1811 | if (likely(!is_uv_system() && !is_uv_hubless(1))) |
1812 | return; |
1813 | |
1814 | if (is_uv_system()) |
1815 | uv_system_init_hub(); |
1816 | else |
1817 | uv_system_init_hubless(); |
1818 | } |
1819 | |
1820 | apic_driver(apic_x2apic_uv_x); |
1821 | |