1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023-2024 Arm Ltd.
4 * Based on the D1 CCU driver:
5 * Copyright (c) 2020 huangzhenwei@allwinnertech.com
6 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13
14#include "../clk.h"
15
16#include "ccu_common.h"
17#include "ccu_reset.h"
18
19#include "ccu_div.h"
20#include "ccu_gate.h"
21#include "ccu_mp.h"
22#include "ccu_mult.h"
23#include "ccu_nk.h"
24#include "ccu_nkm.h"
25#include "ccu_nkmp.h"
26#include "ccu_nm.h"
27
28#include "ccu-sun55i-a523.h"
29
30/*
31 * The 24 MHz oscillator, the root of most of the clock tree.
32 * .fw_name is the string used in the DT "clock-names" property, used to
33 * identify the corresponding clock in the "clocks" property.
34 */
35static const struct clk_parent_data osc24M[] = {
36 { .fw_name = "hosc" }
37};
38
39/**************************************************************************
40 * PLLs *
41 **************************************************************************/
42
43/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
44#define SUN55I_A523_PLL_DDR0_REG 0x010
45static struct ccu_nkmp pll_ddr_clk = {
46 .enable = BIT(27),
47 .lock = BIT(28),
48 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
49 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
50 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
51 .common = {
52 .reg = 0x010,
53 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
54 &ccu_nkmp_ops,
55 CLK_SET_RATE_GATE |
56 CLK_IS_CRITICAL),
57 },
58};
59
60/*
61 * There is no actual clock output with that frequency (2.4 GHz), instead it
62 * has multiple outputs with adjustable dividers from that base frequency.
63 * Model them separately as divider clocks based on that parent here.
64 */
65#define SUN55I_A523_PLL_PERIPH0_REG 0x020
66static struct ccu_nm pll_periph0_4x_clk = {
67 .enable = BIT(27),
68 .lock = BIT(28),
69 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
70 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
71 .common = {
72 .reg = 0x020,
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x",
74 osc24M, &ccu_nm_ops,
75 CLK_SET_RATE_GATE),
76 },
77};
78/*
79 * Most clock-defining macros expect an *array* of parent clocks, even if
80 * they do not contain a muxer to select between different parents.
81 * The macros ending in just _HW take a simple clock pointer, but then create
82 * a single-entry array out of that. The macros using _HWS take such an
83 * array (even when it is a single entry one), this avoids having those
84 * helper arrays created inside *every* clock definition.
85 * This means for every clock that is referenced more than once it is
86 * useful to create such a dummy array and use _HWS.
87 */
88static const struct clk_hw *pll_periph0_4x_hws[] = {
89 &pll_periph0_4x_clk.common.hw
90};
91
92static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
93 pll_periph0_4x_hws, 0x020, 16, 3, 0);
94static const struct clk_hw *pll_periph0_2x_hws[] = {
95 &pll_periph0_2x_clk.common.hw
96};
97static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
98 pll_periph0_4x_hws, 0x020, 20, 3, 0);
99static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M",
100 pll_periph0_4x_hws, 0x020, 2, 3, 0);
101static const struct clk_hw *pll_periph0_480M_hws[] = {
102 &pll_periph0_480M_clk.common.hw
103};
104static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M",
105 pll_periph0_2x_hws, 2, 1, 0);
106static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M",
107 pll_periph0_2x_hws, 3, 1, 0);
108static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M",
109 pll_periph0_2x_hws, 4, 1, 0);
110static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M",
111 pll_periph0_2x_hws, 6, 1, 0);
112static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
113 pll_periph0_2x_hws, 8, 1, 0);
114static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
115 pll_periph0_480M_hws, 3, 1, 0);
116static const struct clk_hw *pll_periph0_150M_hws[] = {
117 &pll_periph0_150M_clk.hw
118};
119
120#define SUN55I_A523_PLL_PERIPH1_REG 0x028
121static struct ccu_nm pll_periph1_4x_clk = {
122 .enable = BIT(27),
123 .lock = BIT(28),
124 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
125 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
126 .common = {
127 .reg = 0x028,
128 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph1-4x",
129 osc24M, &ccu_nm_ops,
130 CLK_SET_RATE_GATE),
131 },
132};
133
134static const struct clk_hw *pll_periph1_4x_hws[] = {
135 &pll_periph1_4x_clk.common.hw
136};
137static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
138 pll_periph1_4x_hws, 0x028, 16, 3, 0);
139static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M",
140 pll_periph1_4x_hws, 0x028, 20, 3, 0);
141static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M",
142 pll_periph1_4x_hws, 0x028, 2, 3, 0);
143
144static const struct clk_hw *pll_periph1_2x_hws[] = {
145 &pll_periph1_2x_clk.common.hw
146};
147static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M",
148 pll_periph1_2x_hws, 2, 1, 0);
149static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M",
150 pll_periph1_2x_hws, 3, 1, 0);
151static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M",
152 pll_periph1_2x_hws, 4, 1, 0);
153static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M",
154 pll_periph1_2x_hws, 6, 1, 0);
155static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M",
156 pll_periph1_2x_hws, 8, 1, 0);
157static const struct clk_hw *pll_periph1_480M_hws[] = {
158 &pll_periph1_480M_clk.common.hw
159};
160static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M",
161 pll_periph1_480M_hws, 3, 1, 0);
162
163#define SUN55I_A523_PLL_GPU_REG 0x030
164static struct ccu_nkmp pll_gpu_clk = {
165 .enable = BIT(27),
166 .lock = BIT(28),
167 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
168 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
169 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
170 .common = {
171 .reg = 0x030,
172 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-gpu", osc24M,
173 &ccu_nkmp_ops,
174 CLK_SET_RATE_GATE),
175 },
176};
177
178#define SUN55I_A523_PLL_VIDEO0_REG 0x040
179static struct ccu_nm pll_video0_8x_clk = {
180 .enable = BIT(27),
181 .lock = BIT(28),
182 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
183 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
184 .common = {
185 .reg = 0x040,
186 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-8x",
187 osc24M, &ccu_nm_ops,
188 CLK_SET_RATE_GATE),
189 },
190};
191
192static const struct clk_hw *pll_video0_8x_hws[] = {
193 &pll_video0_8x_clk.common.hw
194};
195static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x",
196 pll_video0_8x_hws, 0x040, 0, 1, 0);
197static CLK_FIXED_FACTOR_HWS(pll_video0_3x_clk, "pll-video0-3x",
198 pll_video0_8x_hws, 3, 1, CLK_SET_RATE_PARENT);
199
200#define SUN55I_A523_PLL_VIDEO1_REG 0x048
201static struct ccu_nm pll_video1_8x_clk = {
202 .enable = BIT(27),
203 .lock = BIT(28),
204 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
205 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
206 .common = {
207 .reg = 0x048,
208 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-8x",
209 osc24M, &ccu_nm_ops,
210 CLK_SET_RATE_GATE),
211 },
212};
213
214static const struct clk_hw *pll_video1_8x_hws[] = {
215 &pll_video1_8x_clk.common.hw
216};
217static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x",
218 pll_video1_8x_hws, 0x048, 0, 1, 0);
219static CLK_FIXED_FACTOR_HWS(pll_video1_3x_clk, "pll-video1-3x",
220 pll_video1_8x_hws, 3, 1, CLK_SET_RATE_PARENT);
221
222#define SUN55I_A523_PLL_VIDEO2_REG 0x050
223static struct ccu_nm pll_video2_8x_clk = {
224 .enable = BIT(27),
225 .lock = BIT(28),
226 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
227 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
228 .common = {
229 .reg = 0x050,
230 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video2-8x",
231 osc24M, &ccu_nm_ops,
232 CLK_SET_RATE_GATE),
233 },
234};
235
236static const struct clk_hw *pll_video2_8x_hws[] = {
237 &pll_video2_8x_clk.common.hw
238};
239static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x",
240 pll_video2_8x_hws, 0x050, 0, 1, 0);
241static CLK_FIXED_FACTOR_HWS(pll_video2_3x_clk, "pll-video2-3x",
242 pll_video2_8x_hws, 3, 1, CLK_SET_RATE_PARENT);
243
244#define SUN55I_A523_PLL_VE_REG 0x058
245static struct ccu_nkmp pll_ve_clk = {
246 .enable = BIT(27),
247 .lock = BIT(28),
248 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
249 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
250 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
251 .common = {
252 .reg = 0x058,
253 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
254 &ccu_nkmp_ops,
255 CLK_SET_RATE_GATE),
256 },
257};
258
259#define SUN55I_A523_PLL_VIDEO3_REG 0x068
260static struct ccu_nm pll_video3_8x_clk = {
261 .enable = BIT(27),
262 .lock = BIT(28),
263 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
264 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
265 .common = {
266 .reg = 0x068,
267 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video3-8x",
268 osc24M, &ccu_nm_ops,
269 CLK_SET_RATE_GATE),
270 },
271};
272
273static const struct clk_hw *pll_video3_8x_hws[] = {
274 &pll_video3_8x_clk.common.hw
275};
276static SUNXI_CCU_M_HWS(pll_video3_4x_clk, "pll-video3-4x",
277 pll_video3_8x_hws, 0x068, 0, 1, 0);
278static CLK_FIXED_FACTOR_HWS(pll_video3_3x_clk, "pll-video3-3x",
279 pll_video3_8x_hws, 3, 1, CLK_SET_RATE_PARENT);
280
281/*
282 * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
283 * Since we only need some fixed frequency from this PLL (22.5792MHz x 4 and
284 * 24.576MHz x 4), ignore those dividers and force both of them to 1 (encoded
285 * as 0), in the probe function below.
286 * The M factor must be an even number to produce a 50% duty cycle output.
287 */
288#define SUN55I_A523_PLL_AUDIO0_REG 0x078
289static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
290 { .rate = 90316800, .pattern = 0xc000872b, .m = 20, .n = 75 },
291 { .rate = 98304000, .pattern = 0xc0004dd3, .m = 12, .n = 49 },
292
293};
294
295static struct ccu_nm pll_audio0_4x_clk = {
296 .enable = BIT(27),
297 .lock = BIT(28),
298 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
299 .m = _SUNXI_CCU_DIV(16, 6),
300 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
301 0x178, BIT(31)),
302 .min_rate = 180000000U,
303 .max_rate = 3000000000U,
304 .common = {
305 .reg = 0x078,
306 .features = CCU_FEATURE_SIGMA_DELTA_MOD,
307 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x",
308 osc24M, &ccu_nm_ops,
309 CLK_SET_RATE_GATE),
310 },
311};
312
313static CLK_FIXED_FACTOR_HW(pll_audio0_2x_clk, "pll-audio0-2x",
314 &pll_audio0_4x_clk.common.hw, 2, 1, 0);
315static CLK_FIXED_FACTOR_HW(pll_audio0_clk, "pll-audio0",
316 &pll_audio0_4x_clk.common.hw, 4, 1, 0);
317
318#define SUN55I_A523_PLL_NPU_REG 0x080
319static struct ccu_nm pll_npu_4x_clk = {
320 .enable = BIT(27),
321 .lock = BIT(28),
322 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11),
323 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
324 .common = {
325 .reg = 0x0080,
326 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x",
327 osc24M, &ccu_nm_ops,
328 CLK_SET_RATE_GATE),
329 },
330};
331static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x",
332 &pll_npu_4x_clk.common.hw, 2, 1, CLK_SET_RATE_PARENT);
333
334static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x",
335 &pll_npu_4x_clk.common.hw, 4, 1, 0);
336
337
338/**************************************************************************
339 * bus clocks *
340 **************************************************************************/
341
342static const struct clk_parent_data ahb_apb0_parents[] = {
343 { .fw_name = "hosc" },
344 { .fw_name = "losc" },
345 { .fw_name = "iosc" },
346 { .hw = &pll_periph0_600M_clk.hw },
347};
348
349static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb0_parents, 0x510,
350 0, 5, /* M */
351 24, 2, /* mux */
352 0);
353static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw };
354
355static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb0_parents, 0x520,
356 0, 5, /* M */
357 24, 2, /* mux */
358 0);
359static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
360
361static const struct clk_parent_data apb1_parents[] = {
362 { .fw_name = "hosc" },
363 { .fw_name = "losc" },
364 { .fw_name = "iosc" },
365 { .hw = &pll_periph0_600M_clk.hw },
366 { .hw = &pll_periph0_480M_clk.common.hw },
367};
368static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524,
369 0, 5, /* M */
370 24, 3, /* mux */
371 0);
372static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
373
374static const struct clk_parent_data mbus_parents[] = {
375 { .hw = &pll_ddr_clk.common.hw },
376 { .hw = &pll_periph1_600M_clk.hw },
377 { .hw = &pll_periph1_480M_clk.common.hw },
378 { .hw = &pll_periph1_400M_clk.hw },
379 { .hw = &pll_periph1_150M_clk.hw },
380 { .fw_name = "hosc" },
381};
382static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents,
383 0x540,
384 0, 5, /* M */
385 0, 0, /* no P */
386 24, 3, /* mux */
387 BIT(31), /* gate */
388 0, CCU_FEATURE_UPDATE_BIT);
389
390static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };
391
392/**************************************************************************
393 * mod clocks with gates *
394 **************************************************************************/
395
396static const struct clk_hw *de_parents[] = {
397 &pll_periph0_300M_clk.hw,
398 &pll_periph0_400M_clk.hw,
399 &pll_video3_4x_clk.common.hw,
400 &pll_video3_3x_clk.hw,
401};
402
403static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
404 0, 5, /* M */
405 24, 3, /* mux */
406 BIT(31), /* gate */
407 CLK_SET_RATE_PARENT);
408
409static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws, 0x60c, BIT(0), 0);
410
411static const struct clk_hw *di_parents[] = {
412 &pll_periph0_300M_clk.hw,
413 &pll_periph0_400M_clk.hw,
414 &pll_video0_4x_clk.common.hw,
415 &pll_video1_4x_clk.common.hw,
416};
417
418static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0x620,
419 0, 5, /* M */
420 24, 3, /* mux */
421 BIT(31), /* gate */
422 CLK_SET_RATE_PARENT);
423
424static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0x62c, BIT(0), 0);
425
426static const struct clk_hw *g2d_parents[] = {
427 &pll_periph0_400M_clk.hw,
428 &pll_periph0_300M_clk.hw,
429 &pll_video0_4x_clk.common.hw,
430 &pll_video1_4x_clk.common.hw,
431};
432
433static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0x630,
434 0, 5, /* M */
435 24, 3, /* mux */
436 BIT(31), /* gate */
437 0);
438
439static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0x63c, BIT(0), 0);
440
441static const struct clk_hw *gpu_parents[] = {
442 &pll_gpu_clk.common.hw,
443 &pll_periph0_800M_clk.common.hw,
444 &pll_periph0_600M_clk.hw,
445 &pll_periph0_400M_clk.hw,
446 &pll_periph0_300M_clk.hw,
447 &pll_periph0_200M_clk.hw,
448};
449
450static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
451 0, 4, /* M */
452 24, 3, /* mux */
453 BIT(31), /* gate */
454 CLK_SET_RATE_PARENT);
455
456static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0x67c, BIT(0), 0);
457
458static const struct clk_parent_data ce_parents[] = {
459 { .fw_name = "hosc" },
460 { .hw = &pll_periph0_480M_clk.common.hw },
461 { .hw = &pll_periph0_400M_clk.hw },
462 { .hw = &pll_periph0_300M_clk.hw },
463};
464static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
465 0, 5, /* M */
466 24, 3, /* mux */
467 BIT(31), /* gate */
468 0);
469
470static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0x68c, BIT(0), 0);
471static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0x68c,
472 BIT(1), 0);
473
474static const struct clk_hw *ve_parents[] = {
475 &pll_ve_clk.common.hw,
476 &pll_periph0_480M_clk.common.hw,
477 &pll_periph0_400M_clk.hw,
478 &pll_periph0_300M_clk.hw,
479};
480static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
481 0, 5, /* M */
482 24, 3, /* mux */
483 BIT(31), /* gate */
484 CLK_SET_RATE_PARENT);
485
486static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
487
488static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
489
490static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,
491 BIT(0), 0);
492
493static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, 0x72c,
494 BIT(0), 0);
495
496static const struct clk_parent_data hstimer_parents[] = {
497 { .fw_name = "hosc" },
498 { .fw_name = "iosc" },
499 { .fw_name = "losc" },
500 { .hw = &pll_periph0_200M_clk.hw },
501};
502static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
503 hstimer_parents, 0x730,
504 0, 0, /* M */
505 0, 3, /* P */
506 24, 3, /* mux */
507 BIT(31), /* gate */
508 0);
509
510static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1",
511 hstimer_parents,
512 0x734,
513 0, 0, /* M */
514 0, 3, /* P */
515 24, 3, /* mux */
516 BIT(31), /* gate */
517 0);
518
519static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2",
520 hstimer_parents,
521 0x738,
522 0, 0, /* M */
523 0, 3, /* P */
524 24, 3, /* mux */
525 BIT(31), /* gate */
526 0);
527
528static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3",
529 hstimer_parents,
530 0x73c,
531 0, 0, /* M */
532 0, 3, /* P */
533 24, 3, /* mux */
534 BIT(31), /* gate */
535 0);
536
537static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4",
538 hstimer_parents,
539 0x740,
540 0, 0, /* M */
541 0, 3, /* P */
542 24, 3, /* mux */
543 BIT(31), /* gate */
544 0);
545
546static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5",
547 hstimer_parents,
548 0x744,
549 0, 0, /* M */
550 0, 3, /* P */
551 24, 3, /* mux */
552 BIT(31), /* gate */
553 0);
554
555static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c,
556 BIT(0), 0);
557
558static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws, 0x78c,
559 BIT(0), 0);
560
561static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb1_hws, 0x7ac, BIT(0), 0);
562static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb1_hws, 0x7ac, BIT(1), 0);
563
564static const struct clk_parent_data iommu_parents[] = {
565 { .hw = &pll_periph0_600M_clk.hw },
566 { .hw = &pll_ddr_clk.common.hw },
567 { .hw = &pll_periph0_480M_clk.common.hw },
568 { .hw = &pll_periph0_400M_clk.hw },
569 { .hw = &pll_periph0_150M_clk.hw },
570 { .fw_name = "hosc" },
571};
572
573static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents,
574 0x7b0,
575 0, 5, /* M */
576 0, 0, /* no P */
577 24, 3, /* mux */
578 BIT(31), /* gate */
579 CLK_SET_RATE_PARENT,
580 CCU_FEATURE_UPDATE_BIT);
581
582static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc,
583 BIT(0), 0);
584
585static const struct clk_parent_data dram_parents[] = {
586 { .hw = &pll_ddr_clk.common.hw },
587 { .hw = &pll_periph0_600M_clk.hw },
588 { .hw = &pll_periph0_480M_clk.common.hw },
589 { .hw = &pll_periph0_400M_clk.hw },
590 { .hw = &pll_periph0_150M_clk.hw },
591};
592static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents,
593 0x800,
594 0, 5, /* M */
595 0, 0, /* no P */
596 24, 3, /* mux */
597 BIT(31), /* gate */
598 CLK_IS_CRITICAL,
599 CCU_FEATURE_UPDATE_BIT);
600
601static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
602 0x804, BIT(0), 0);
603static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
604 0x804, BIT(1), 0);
605static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
606 0x804, BIT(2), 0);
607static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws,
608 0x804, BIT(5), 0);
609static SUNXI_CCU_GATE_HWS(mbus_usb3_clk, "mbus-usb3", mbus_hws,
610 0x804, BIT(6), 0);
611static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
612 0x804, BIT(8), 0);
613static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
614 0x804, BIT(9), 0);
615static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws,
616 0x804, BIT(12), 0);
617
618static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws, 0x80c,
619 BIT(0), CLK_IS_CRITICAL);
620
621static const struct clk_parent_data nand_mmc_parents[] = {
622 { .fw_name = "hosc" },
623 { .hw = &pll_periph0_400M_clk.hw },
624 { .hw = &pll_periph0_300M_clk.hw },
625 { .hw = &pll_periph1_400M_clk.hw },
626 { .hw = &pll_periph1_300M_clk.hw },
627};
628
629static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk, "nand0", nand_mmc_parents,
630 0x810,
631 0, 5, /* M */
632 24, 3, /* mux */
633 BIT(31), /* gate */
634 0);
635
636static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1", nand_mmc_parents,
637 0x814,
638 0, 5, /* M */
639 24, 3, /* mux */
640 BIT(31), /* gate */
641 0);
642
643static SUNXI_CCU_GATE_HWS(bus_nand_clk, "bus-nand", ahb_hws, 0x82c,
644 BIT(0), 0);
645
646static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents,
647 0x830,
648 0, 5, /* M */
649 8, 5, /* P */
650 24, 3, /* mux */
651 BIT(31), /* gate */
652 2, /* post div */
653 0);
654
655static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents,
656 0x834,
657 0, 5, /* M */
658 8, 5, /* P */
659 24, 3, /* mux */
660 BIT(31), /* gate */
661 2, /* post div */
662 0);
663
664static const struct clk_parent_data mmc2_parents[] = {
665 { .fw_name = "hosc" },
666 { .hw = &pll_periph0_800M_clk.common.hw },
667 { .hw = &pll_periph0_600M_clk.hw },
668 { .hw = &pll_periph1_800M_clk.common.hw },
669 { .hw = &pll_periph1_600M_clk.hw },
670};
671
672static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_parents,
673 0x838,
674 0, 5, /* M */
675 8, 5, /* P */
676 24, 3, /* mux */
677 BIT(31), /* gate */
678 2, /* post div */
679 0);
680
681static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0x84c, BIT(0), 0);
682static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0x84c, BIT(1), 0);
683static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0x84c, BIT(2), 0);
684
685static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, 0x88c,
686 BIT(0), 0);
687
688static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws, 0x90c,
689 BIT(0), 0);
690static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws, 0x90c,
691 BIT(1), 0);
692static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws, 0x90c,
693 BIT(2), 0);
694static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws, 0x90c,
695 BIT(3), 0);
696static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws, 0x90c,
697 BIT(4), 0);
698static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws, 0x90c,
699 BIT(5), 0);
700static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb1_hws, 0x90c,
701 BIT(6), 0);
702static SUNXI_CCU_GATE_HWS(bus_uart7_clk, "bus-uart7", apb1_hws, 0x90c,
703 BIT(7), 0);
704
705static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0x91c, BIT(0), 0);
706static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0x91c, BIT(1), 0);
707static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0x91c, BIT(2), 0);
708static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0);
709static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0x91c, BIT(4), 0);
710static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0x91c, BIT(5), 0);
711
712static SUNXI_CCU_GATE_HWS(bus_can_clk, "bus-can", apb1_hws, 0x92c, BIT(0), 0);
713
714static const struct clk_parent_data spi_parents[] = {
715 { .fw_name = "hosc" },
716 { .hw = &pll_periph0_300M_clk.hw },
717 { .hw = &pll_periph0_200M_clk.hw },
718 { .hw = &pll_periph1_300M_clk.hw },
719 { .hw = &pll_periph1_200M_clk.hw },
720};
721static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
722 0, 5, /* M */
723 8, 5, /* P */
724 24, 3, /* mux */
725 BIT(31), /* gate */
726 0);
727static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
728 0, 5, /* M */
729 8, 5, /* P */
730 24, 3, /* mux */
731 BIT(31), /* gate */
732 0);
733static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
734 0, 5, /* M */
735 8, 5, /* P */
736 24, 3, /* mux */
737 BIT(31), /* gate */
738 0);
739static SUNXI_CCU_DUALDIV_MUX_GATE(spifc_clk, "spifc", nand_mmc_parents, 0x950,
740 0, 5, /* M */
741 8, 5, /* P */
742 24, 3, /* mux */
743 BIT(31), /* gate */
744 0);
745static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0x96c, BIT(0), 0);
746static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0x96c, BIT(1), 0);
747static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0x96c, BIT(2), 0);
748static SUNXI_CCU_GATE_HWS(bus_spifc_clk, "bus-spifc", ahb_hws, 0x96c,
749 BIT(3), 0);
750
751static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M",
752 pll_periph0_150M_hws,
753 0x970, BIT(31) | BIT(30), 6, 0);
754static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M",
755 pll_periph0_150M_hws,
756 0x974, BIT(31) | BIT(30), 6, 0);
757static SUNXI_CCU_GATE_HWS(bus_emac0_clk, "bus-emac0", ahb_hws, 0x97c,
758 BIT(0), 0);
759static SUNXI_CCU_GATE_HWS(bus_emac1_clk, "bus-emac1", ahb_hws, 0x98c,
760 BIT(0), 0);
761
762static const struct clk_parent_data ir_rx_parents[] = {
763 { .fw_name = "losc" },
764 { .fw_name = "hosc" },
765};
766
767static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_rx_parents, 0x990,
768 0, 5, /* M */
769 24, 1, /* mux */
770 BIT(31), /* gate */
771 0);
772static SUNXI_CCU_GATE_HWS(bus_ir_rx_clk, "bus-ir-rx", apb0_hws, 0x99c,
773 BIT(0), 0);
774
775static const struct clk_parent_data ir_tx_ledc_parents[] = {
776 { .fw_name = "hosc" },
777 { .hw = &pll_periph1_600M_clk.hw },
778};
779static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents,
780 0x9c0,
781 0, 5, /* M */
782 24, 1, /* mux */
783 BIT(31), /* gate */
784 0);
785static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws, 0x9cc,
786 BIT(0), 0);
787
788static SUNXI_CCU_M_WITH_GATE(gpadc0_clk, "gpadc0", "hosc", 0x9e0,
789 0, 5, /* M */
790 BIT(31), /* gate */
791 0);
792static SUNXI_CCU_M_WITH_GATE(gpadc1_clk, "gpadc1", "hosc", 0x9e4,
793 0, 5, /* M */
794 BIT(31), /* gate */
795 0);
796static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0x9ec,
797 BIT(0), 0);
798static SUNXI_CCU_GATE_HWS(bus_gpadc1_clk, "bus-gpadc1", ahb_hws, 0x9ec,
799 BIT(1), 0);
800
801static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0x9fc, BIT(0), 0);
802
803/*
804 * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is
805 * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
806 * the OHCI module.
807 */
808static const struct clk_parent_data usb_ohci_parents[] = {
809 { .hw = &pll_periph0_4x_clk.common.hw },
810 { .fw_name = "hosc" },
811 { .fw_name = "losc" },
812 { .fw_name = "iosc" },
813};
814static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = {
815 { .index = 0, .div = 50 },
816 { .index = 1, .div = 2 },
817};
818
819static struct ccu_mux usb_ohci0_clk = {
820 .enable = BIT(31),
821 .mux = {
822 .shift = 24,
823 .width = 2,
824 .fixed_predivs = usb_ohci_predivs,
825 .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
826 },
827 .common = {
828 .reg = 0xa70,
829 .features = CCU_FEATURE_FIXED_PREDIV,
830 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
831 usb_ohci_parents,
832 &ccu_mux_ops,
833 0),
834 },
835};
836
837static struct ccu_mux usb_ohci1_clk = {
838 .enable = BIT(31),
839 .mux = {
840 .shift = 24,
841 .width = 2,
842 .fixed_predivs = usb_ohci_predivs,
843 .n_predivs = ARRAY_SIZE(usb_ohci_predivs),
844 },
845 .common = {
846 .reg = 0xa74,
847 .features = CCU_FEATURE_FIXED_PREDIV,
848 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
849 usb_ohci_parents,
850 &ccu_mux_ops,
851 0),
852 },
853};
854
855static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c,
856 BIT(0), 0);
857static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c,
858 BIT(1), 0);
859static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0xa8c,
860 BIT(4), 0);
861static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0xa8c,
862 BIT(5), 0);
863static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
864
865static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0xa9c,
866 BIT(0), 0);
867
868static const struct clk_parent_data losc_hosc_parents[] = {
869 { .fw_name = "hosc" },
870 { .fw_name = "losc" },
871};
872
873static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux",
874 losc_hosc_parents, 0xaa0,
875 0, 5, /* M */
876 24, 1, /* mux */
877 BIT(31), /* gate */
878 0);
879
880static SUNXI_CCU_GATE_HWS(bus_display0_top_clk, "bus-display0-top", ahb_hws,
881 0xabc, BIT(0), 0);
882static SUNXI_CCU_GATE_HWS(bus_display1_top_clk, "bus-display1-top", ahb_hws,
883 0xacc, BIT(0), 0);
884
885static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
886
887static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
888 pll_periph0_2x_hws,
889 0xb10, BIT(30), 36621, 0);
890
891static const struct clk_parent_data hdmi_cec_parents[] = {
892 { .fw_name = "losc" },
893 { .hw = &hdmi_cec_32k_clk.common.hw },
894};
895static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents,
896 0xb10,
897 24, 1, /* mux */
898 BIT(31), /* gate */
899 0);
900
901static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", ahb_hws, 0xb1c, BIT(0), 0);
902
903static const struct clk_parent_data mipi_dsi_parents[] = {
904 { .fw_name = "hosc" },
905 { .hw = &pll_periph0_200M_clk.hw },
906 { .hw = &pll_periph0_150M_clk.hw },
907};
908static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0",
909 mipi_dsi_parents, 0xb24,
910 0, 5, /* M */
911 24, 3, /* mux */
912 BIT(31), /* gate */
913 0);
914
915static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1",
916 mipi_dsi_parents, 0xb28,
917 0, 5, /* M */
918 24, 3, /* mux */
919 BIT(31), /* gate */
920 0);
921
922static SUNXI_CCU_GATE_HWS(bus_mipi_dsi0_clk, "bus-mipi-dsi0", ahb_hws, 0xb4c,
923 BIT(0), 0);
924
925static SUNXI_CCU_GATE_HWS(bus_mipi_dsi1_clk, "bus-mipi-dsi1", ahb_hws, 0xb4c,
926 BIT(1), 0);
927
928static const struct clk_hw *tcon_parents[] = {
929 &pll_video0_4x_clk.common.hw,
930 &pll_video1_4x_clk.common.hw,
931 &pll_video2_4x_clk.common.hw,
932 &pll_video3_4x_clk.common.hw,
933 &pll_periph0_2x_clk.common.hw,
934 &pll_video0_3x_clk.hw,
935 &pll_video1_3x_clk.hw,
936};
937static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
938 0xb60,
939 0, 5, /* M */
940 24, 3, /* mux */
941 BIT(31), /* gate */
942 CLK_SET_RATE_PARENT);
943
944static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
945 0xb64,
946 0, 5, /* M */
947 24, 3, /* mux */
948 BIT(31), /* gate */
949 CLK_SET_RATE_PARENT);
950
951static const struct clk_hw *tcon_tv_parents[] = {
952 &pll_video0_4x_clk.common.hw,
953 &pll_video1_4x_clk.common.hw,
954 &pll_video2_4x_clk.common.hw,
955 &pll_video3_4x_clk.common.hw,
956 &pll_periph0_2x_clk.common.hw,
957};
958static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2",
959 tcon_tv_parents, 0xb68,
960 0, 5, /* M */
961 24, 3, /* mux */
962 BIT(31), /* gate */
963 CLK_SET_RATE_PARENT);
964
965static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0",
966 tcon_parents, 0xb6c,
967 0, 5, /* M */
968 24, 3, /* mux */
969 BIT(31), /* gate */
970 CLK_SET_RATE_PARENT);
971
972static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1",
973 tcon_parents, 0xb70,
974 0, 5, /* M */
975 24, 3, /* mux */
976 BIT(31), /* gate */
977 CLK_SET_RATE_PARENT);
978
979static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0xb7c,
980 BIT(0), 0);
981static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0xb7c,
982 BIT(1), 0);
983static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0xb7c,
984 BIT(2), 0);
985
986static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_tv_parents,
987 0xb80,
988 0, 4, /* M */
989 24, 3, /* mux */
990 BIT(31), /* gate */
991 CLK_SET_RATE_PARENT);
992
993static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_tv_parents,
994 0xb84,
995 0, 4, /* M */
996 24, 3, /* mux */
997 BIT(31), /* gate */
998 CLK_SET_RATE_PARENT);
999
1000static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0xb9c,
1001 BIT(0), 0);
1002static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0xb9c,
1003 BIT(1), 0);
1004
1005static const struct clk_hw *edp_parents[] = {
1006 &pll_video0_4x_clk.common.hw,
1007 &pll_video1_4x_clk.common.hw,
1008 &pll_video2_4x_clk.common.hw,
1009 &pll_video3_4x_clk.common.hw,
1010 &pll_periph0_2x_clk.common.hw,
1011};
1012static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0,
1013 0, 4, /* M */
1014 24, 3, /* mux */
1015 BIT(31), /* gate */
1016 CLK_SET_RATE_PARENT);
1017
1018static SUNXI_CCU_GATE_HWS(bus_edp_clk, "bus-edp", ahb_hws, 0xbbc, BIT(0), 0);
1019
1020static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents,
1021 0xbf0,
1022 0, 4, /* M */
1023 24, 1, /* mux */
1024 BIT(31), /* gate */
1025 0);
1026
1027static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0xbfc, BIT(0), 0);
1028
1029static const struct clk_hw *csi_top_parents[] = {
1030 &pll_periph0_300M_clk.hw,
1031 &pll_periph0_400M_clk.hw,
1032 &pll_periph0_480M_clk.common.hw,
1033 &pll_video3_4x_clk.common.hw,
1034 &pll_video3_3x_clk.hw,
1035};
1036static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents,
1037 0xc04,
1038 0, 5, /* M */
1039 24, 3, /* mux */
1040 BIT(31), /* gate */
1041 0);
1042
1043static const struct clk_parent_data csi_mclk_parents[] = {
1044 { .fw_name = "hosc" },
1045 { .hw = &pll_video3_4x_clk.common.hw },
1046 { .hw = &pll_video0_4x_clk.common.hw },
1047 { .hw = &pll_video1_4x_clk.common.hw },
1048 { .hw = &pll_video2_4x_clk.common.hw },
1049};
1050static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents,
1051 0xc08,
1052 0, 5, /* M */
1053 8, 5, /* P */
1054 24, 3, /* mux */
1055 BIT(31), /* gate */
1056 0);
1057
1058static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents,
1059 0xc0c,
1060 0, 5, /* M */
1061 8, 5, /* P */
1062 24, 3, /* mux */
1063 BIT(31), /* gate */
1064 0);
1065
1066static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents,
1067 0xc10,
1068 0, 5, /* M */
1069 8, 5, /* P */
1070 24, 3, /* mux */
1071 BIT(31), /* gate */
1072 0);
1073
1074static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents,
1075 0xc14,
1076 0, 5, /* M */
1077 8, 5, /* P */
1078 24, 3, /* mux */
1079 BIT(31), /* gate */
1080 0);
1081
1082static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0xc1c, BIT(0), 0);
1083
1084static const struct clk_hw *isp_parents[] = {
1085 &pll_periph0_300M_clk.hw,
1086 &pll_periph0_400M_clk.hw,
1087 &pll_video2_4x_clk.common.hw,
1088 &pll_video3_4x_clk.common.hw,
1089};
1090static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0xc20,
1091 0, 5, /* M */
1092 24, 3, /* mux */
1093 BIT(31), /* gate */
1094 0);
1095
1096static const struct clk_parent_data dsp_parents[] = {
1097 { .fw_name = "hosc" },
1098 { .fw_name = "losc" },
1099 { .fw_name = "iosc" },
1100 { .hw = &pll_periph0_2x_clk.common.hw },
1101 { .hw = &pll_periph0_480M_clk.common.hw, },
1102};
1103static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
1104 0, 5, /* M */
1105 24, 3, /* mux */
1106 BIT(31), /* gate */
1107 0);
1108
1109static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
1110 0xf30, BIT(0), 0);
1111static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
1112 0xf30, BIT(1), 2, 0);
1113static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
1114 pll_periph0_480M_hws,
1115 0xf30, BIT(2), 30, 0);
1116static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
1117 pll_periph0_2x_hws,
1118 0xf30, BIT(3), 48, 0);
1119static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
1120 pll_periph0_2x_hws,
1121 0xf30, BIT(4), 24, 0);
1122
1123static const struct clk_parent_data fanout_27M_parents[] = {
1124 { .hw = &pll_video0_4x_clk.common.hw },
1125 { .hw = &pll_video1_4x_clk.common.hw },
1126 { .hw = &pll_video2_4x_clk.common.hw },
1127 { .hw = &pll_video3_4x_clk.common.hw },
1128};
1129static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
1130 fanout_27M_parents, 0xf34,
1131 0, 5, /* div0 */
1132 8, 5, /* div1 */
1133 24, 2, /* mux */
1134 BIT(31), /* gate */
1135 0);
1136
1137static const struct clk_parent_data fanout_pclk_parents[] = {
1138 { .hw = &apb0_clk.common.hw }
1139};
1140static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk",
1141 fanout_pclk_parents,
1142 0xf38,
1143 0, 5, /* div0 */
1144 5, 5, /* div1 */
1145 0, 0, /* mux */
1146 BIT(31), /* gate */
1147 0);
1148
1149static const struct clk_parent_data fanout_parents[] = {
1150 { .fw_name = "losc-fanout" },
1151 { .hw = &fanout_12M_clk.common.hw, },
1152 { .hw = &fanout_16M_clk.common.hw, },
1153 { .hw = &fanout_24M_clk.common.hw, },
1154 { .hw = &fanout_25M_clk.common.hw, },
1155 { .hw = &fanout_27M_clk.common.hw, },
1156 { .hw = &fanout_pclk_clk.common.hw, },
1157 { .hw = &fanout_50M_clk.common.hw, },
1158};
1159static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents,
1160 0xf3c,
1161 0, 3, /* mux */
1162 BIT(21), /* gate */
1163 0);
1164static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents,
1165 0xf3c,
1166 3, 3, /* mux */
1167 BIT(22), /* gate */
1168 0);
1169static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents,
1170 0xf3c,
1171 6, 3, /* mux */
1172 BIT(23), /* gate */
1173 0);
1174
1175/*
1176 * Contains all clocks that are controlled by a hardware register. They
1177 * have a (sunxi) .common member, which needs to be initialised by the common
1178 * sunxi CCU code, to be filled with the MMIO base address and the shared lock.
1179 */
1180static struct ccu_common *sun55i_a523_ccu_clks[] = {
1181 &pll_ddr_clk.common,
1182 &pll_periph0_4x_clk.common,
1183 &pll_periph0_2x_clk.common,
1184 &pll_periph0_800M_clk.common,
1185 &pll_periph0_480M_clk.common,
1186 &pll_periph1_4x_clk.common,
1187 &pll_periph1_2x_clk.common,
1188 &pll_periph1_800M_clk.common,
1189 &pll_periph1_480M_clk.common,
1190 &pll_gpu_clk.common,
1191 &pll_video0_8x_clk.common,
1192 &pll_video0_4x_clk.common,
1193 &pll_video1_8x_clk.common,
1194 &pll_video1_4x_clk.common,
1195 &pll_video2_8x_clk.common,
1196 &pll_video2_4x_clk.common,
1197 &pll_video3_8x_clk.common,
1198 &pll_video3_4x_clk.common,
1199 &pll_ve_clk.common,
1200 &pll_audio0_4x_clk.common,
1201 &pll_npu_4x_clk.common,
1202 &ahb_clk.common,
1203 &apb0_clk.common,
1204 &apb1_clk.common,
1205 &mbus_clk.common,
1206 &de_clk.common,
1207 &bus_de_clk.common,
1208 &di_clk.common,
1209 &bus_di_clk.common,
1210 &g2d_clk.common,
1211 &bus_g2d_clk.common,
1212 &gpu_clk.common,
1213 &bus_gpu_clk.common,
1214 &ce_clk.common,
1215 &bus_ce_clk.common,
1216 &bus_ce_sys_clk.common,
1217 &ve_clk.common,
1218 &bus_ve_clk.common,
1219 &bus_dma_clk.common,
1220 &bus_msgbox_clk.common,
1221 &bus_spinlock_clk.common,
1222 &hstimer0_clk.common,
1223 &hstimer1_clk.common,
1224 &hstimer2_clk.common,
1225 &hstimer3_clk.common,
1226 &hstimer4_clk.common,
1227 &hstimer5_clk.common,
1228 &bus_hstimer_clk.common,
1229 &bus_dbg_clk.common,
1230 &bus_pwm0_clk.common,
1231 &bus_pwm1_clk.common,
1232 &iommu_clk.common,
1233 &bus_iommu_clk.common,
1234 &dram_clk.common,
1235 &mbus_dma_clk.common,
1236 &mbus_ve_clk.common,
1237 &mbus_ce_clk.common,
1238 &mbus_nand_clk.common,
1239 &mbus_usb3_clk.common,
1240 &mbus_csi_clk.common,
1241 &mbus_isp_clk.common,
1242 &mbus_gmac1_clk.common,
1243 &bus_dram_clk.common,
1244 &nand0_clk.common,
1245 &nand1_clk.common,
1246 &bus_nand_clk.common,
1247 &mmc0_clk.common,
1248 &mmc1_clk.common,
1249 &mmc2_clk.common,
1250 &bus_sysdap_clk.common,
1251 &bus_mmc0_clk.common,
1252 &bus_mmc1_clk.common,
1253 &bus_mmc2_clk.common,
1254 &bus_uart0_clk.common,
1255 &bus_uart1_clk.common,
1256 &bus_uart2_clk.common,
1257 &bus_uart3_clk.common,
1258 &bus_uart4_clk.common,
1259 &bus_uart5_clk.common,
1260 &bus_uart6_clk.common,
1261 &bus_uart7_clk.common,
1262 &bus_i2c0_clk.common,
1263 &bus_i2c1_clk.common,
1264 &bus_i2c2_clk.common,
1265 &bus_i2c3_clk.common,
1266 &bus_i2c4_clk.common,
1267 &bus_i2c5_clk.common,
1268 &bus_can_clk.common,
1269 &spi0_clk.common,
1270 &spi1_clk.common,
1271 &spi2_clk.common,
1272 &spifc_clk.common,
1273 &bus_spi0_clk.common,
1274 &bus_spi1_clk.common,
1275 &bus_spi2_clk.common,
1276 &bus_spifc_clk.common,
1277 &emac0_25M_clk.common,
1278 &emac1_25M_clk.common,
1279 &bus_emac0_clk.common,
1280 &bus_emac1_clk.common,
1281 &ir_rx_clk.common,
1282 &bus_ir_rx_clk.common,
1283 &ir_tx_clk.common,
1284 &bus_ir_tx_clk.common,
1285 &gpadc0_clk.common,
1286 &gpadc1_clk.common,
1287 &bus_gpadc0_clk.common,
1288 &bus_gpadc1_clk.common,
1289 &bus_ths_clk.common,
1290 &usb_ohci0_clk.common,
1291 &usb_ohci1_clk.common,
1292 &bus_ohci0_clk.common,
1293 &bus_ohci1_clk.common,
1294 &bus_ehci0_clk.common,
1295 &bus_ehci1_clk.common,
1296 &bus_otg_clk.common,
1297 &bus_lradc_clk.common,
1298 &pcie_aux_clk.common,
1299 &bus_display0_top_clk.common,
1300 &bus_display1_top_clk.common,
1301 &hdmi_24M_clk.common,
1302 &hdmi_cec_32k_clk.common,
1303 &hdmi_cec_clk.common,
1304 &bus_hdmi_clk.common,
1305 &mipi_dsi0_clk.common,
1306 &mipi_dsi1_clk.common,
1307 &bus_mipi_dsi0_clk.common,
1308 &bus_mipi_dsi1_clk.common,
1309 &tcon_lcd0_clk.common,
1310 &tcon_lcd1_clk.common,
1311 &tcon_lcd2_clk.common,
1312 &combophy_dsi0_clk.common,
1313 &combophy_dsi1_clk.common,
1314 &bus_tcon_lcd0_clk.common,
1315 &bus_tcon_lcd1_clk.common,
1316 &bus_tcon_lcd2_clk.common,
1317 &tcon_tv0_clk.common,
1318 &tcon_tv1_clk.common,
1319 &bus_tcon_tv0_clk.common,
1320 &bus_tcon_tv1_clk.common,
1321 &edp_clk.common,
1322 &bus_edp_clk.common,
1323 &ledc_clk.common,
1324 &bus_ledc_clk.common,
1325 &csi_top_clk.common,
1326 &csi_mclk0_clk.common,
1327 &csi_mclk1_clk.common,
1328 &csi_mclk2_clk.common,
1329 &csi_mclk3_clk.common,
1330 &bus_csi_clk.common,
1331 &isp_clk.common,
1332 &dsp_clk.common,
1333 &fanout_24M_clk.common,
1334 &fanout_12M_clk.common,
1335 &fanout_16M_clk.common,
1336 &fanout_25M_clk.common,
1337 &fanout_27M_clk.common,
1338 &fanout_pclk_clk.common,
1339 &fanout0_clk.common,
1340 &fanout1_clk.common,
1341 &fanout2_clk.common,
1342};
1343
1344static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
1345 .num = CLK_NUMBER,
1346 .hws = {
1347 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
1348 [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
1349 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
1350 [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw,
1351 [CLK_PLL_PERIPH0_480M] = &pll_periph0_480M_clk.common.hw,
1352 [CLK_PLL_PERIPH0_600M] = &pll_periph0_600M_clk.hw,
1353 [CLK_PLL_PERIPH0_400M] = &pll_periph0_400M_clk.hw,
1354 [CLK_PLL_PERIPH0_300M] = &pll_periph0_300M_clk.hw,
1355 [CLK_PLL_PERIPH0_200M] = &pll_periph0_200M_clk.hw,
1356 [CLK_PLL_PERIPH0_160M] = &pll_periph0_160M_clk.hw,
1357 [CLK_PLL_PERIPH0_150M] = &pll_periph0_150M_clk.hw,
1358 [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.common.hw,
1359 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.common.hw,
1360 [CLK_PLL_PERIPH1_800M] = &pll_periph1_800M_clk.common.hw,
1361 [CLK_PLL_PERIPH1_480M] = &pll_periph1_480M_clk.common.hw,
1362 [CLK_PLL_PERIPH1_600M] = &pll_periph1_600M_clk.hw,
1363 [CLK_PLL_PERIPH1_400M] = &pll_periph1_400M_clk.hw,
1364 [CLK_PLL_PERIPH1_300M] = &pll_periph1_300M_clk.hw,
1365 [CLK_PLL_PERIPH1_200M] = &pll_periph1_200M_clk.hw,
1366 [CLK_PLL_PERIPH1_160M] = &pll_periph1_160M_clk.hw,
1367 [CLK_PLL_PERIPH1_150M] = &pll_periph1_150M_clk.hw,
1368 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1369 [CLK_PLL_VIDEO0_8X] = &pll_video0_8x_clk.common.hw,
1370 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
1371 [CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.hw,
1372 [CLK_PLL_VIDEO1_8X] = &pll_video1_8x_clk.common.hw,
1373 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
1374 [CLK_PLL_VIDEO1_3X] = &pll_video1_3x_clk.hw,
1375 [CLK_PLL_VIDEO2_8X] = &pll_video2_8x_clk.common.hw,
1376 [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.common.hw,
1377 [CLK_PLL_VIDEO2_3X] = &pll_video2_3x_clk.hw,
1378 [CLK_PLL_VIDEO3_8X] = &pll_video3_8x_clk.common.hw,
1379 [CLK_PLL_VIDEO3_4X] = &pll_video3_4x_clk.common.hw,
1380 [CLK_PLL_VIDEO3_3X] = &pll_video3_3x_clk.hw,
1381 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
1382 [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
1383 [CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw,
1384 [CLK_PLL_AUDIO0] = &pll_audio0_clk.hw,
1385 [CLK_PLL_NPU_4X] = &pll_npu_4x_clk.common.hw,
1386 [CLK_PLL_NPU_2X] = &pll_npu_2x_clk.hw,
1387 [CLK_PLL_NPU] = &pll_npu_1x_clk.hw,
1388 [CLK_AHB] = &ahb_clk.common.hw,
1389 [CLK_APB0] = &apb0_clk.common.hw,
1390 [CLK_APB1] = &apb1_clk.common.hw,
1391 [CLK_MBUS] = &mbus_clk.common.hw,
1392 [CLK_DE] = &de_clk.common.hw,
1393 [CLK_BUS_DE] = &bus_de_clk.common.hw,
1394 [CLK_DI] = &di_clk.common.hw,
1395 [CLK_BUS_DI] = &bus_di_clk.common.hw,
1396 [CLK_G2D] = &g2d_clk.common.hw,
1397 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
1398 [CLK_GPU] = &gpu_clk.common.hw,
1399 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
1400 [CLK_CE] = &ce_clk.common.hw,
1401 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1402 [CLK_BUS_CE_SYS] = &bus_ce_sys_clk.common.hw,
1403 [CLK_VE] = &ve_clk.common.hw,
1404 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1405 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1406 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
1407 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
1408 [CLK_HSTIMER0] = &hstimer0_clk.common.hw,
1409 [CLK_HSTIMER1] = &hstimer1_clk.common.hw,
1410 [CLK_HSTIMER2] = &hstimer2_clk.common.hw,
1411 [CLK_HSTIMER3] = &hstimer3_clk.common.hw,
1412 [CLK_HSTIMER4] = &hstimer4_clk.common.hw,
1413 [CLK_HSTIMER5] = &hstimer5_clk.common.hw,
1414 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1415 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1416 [CLK_BUS_PWM0] = &bus_pwm0_clk.common.hw,
1417 [CLK_BUS_PWM1] = &bus_pwm1_clk.common.hw,
1418 [CLK_IOMMU] = &iommu_clk.common.hw,
1419 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
1420 [CLK_DRAM] = &dram_clk.common.hw,
1421 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
1422 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
1423 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
1424 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
1425 [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw,
1426 [CLK_MBUS_EMAC1] = &mbus_gmac1_clk.common.hw,
1427 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1428 [CLK_NAND0] = &nand0_clk.common.hw,
1429 [CLK_NAND1] = &nand1_clk.common.hw,
1430 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
1431 [CLK_MMC0] = &mmc0_clk.common.hw,
1432 [CLK_MMC1] = &mmc1_clk.common.hw,
1433 [CLK_MMC2] = &mmc2_clk.common.hw,
1434 [CLK_BUS_SYSDAP] = &bus_sysdap_clk.common.hw,
1435 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1436 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1437 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1438 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1439 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1440 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1441 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1442 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1443 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1444 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
1445 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
1446 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1447 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1448 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1449 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1450 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
1451 [CLK_BUS_I2C5] = &bus_i2c5_clk.common.hw,
1452 [CLK_BUS_CAN] = &bus_can_clk.common.hw,
1453 [CLK_SPI0] = &spi0_clk.common.hw,
1454 [CLK_SPI1] = &spi1_clk.common.hw,
1455 [CLK_SPI2] = &spi2_clk.common.hw,
1456 [CLK_SPIFC] = &spifc_clk.common.hw,
1457 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1458 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1459 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
1460 [CLK_BUS_SPIFC] = &bus_spifc_clk.common.hw,
1461 [CLK_EMAC0_25M] = &emac0_25M_clk.common.hw,
1462 [CLK_EMAC1_25M] = &emac1_25M_clk.common.hw,
1463 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw,
1464 [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
1465 [CLK_IR_RX] = &ir_rx_clk.common.hw,
1466 [CLK_BUS_IR_RX] = &bus_ir_rx_clk.common.hw,
1467 [CLK_IR_TX] = &ir_tx_clk.common.hw,
1468 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
1469 [CLK_GPADC0] = &gpadc0_clk.common.hw,
1470 [CLK_GPADC1] = &gpadc1_clk.common.hw,
1471 [CLK_BUS_GPADC0] = &bus_gpadc0_clk.common.hw,
1472 [CLK_BUS_GPADC1] = &bus_gpadc1_clk.common.hw,
1473 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1474 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1475 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1476 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1477 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1478 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1479 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1480 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1481 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
1482 [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
1483 [CLK_BUS_DISPLAY0_TOP] = &bus_display0_top_clk.common.hw,
1484 [CLK_BUS_DISPLAY1_TOP] = &bus_display1_top_clk.common.hw,
1485 [CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
1486 [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
1487 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1488 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1489 [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw,
1490 [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw,
1491 [CLK_BUS_MIPI_DSI0] = &bus_mipi_dsi0_clk.common.hw,
1492 [CLK_BUS_MIPI_DSI1] = &bus_mipi_dsi1_clk.common.hw,
1493 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1494 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
1495 [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw,
1496 [CLK_COMBOPHY_DSI0] = &combophy_dsi0_clk.common.hw,
1497 [CLK_COMBOPHY_DSI1] = &combophy_dsi1_clk.common.hw,
1498 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1499 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1500 [CLK_BUS_TCON_LCD2] = &bus_tcon_lcd2_clk.common.hw,
1501 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1502 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
1503 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1504 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
1505 [CLK_EDP] = &edp_clk.common.hw,
1506 [CLK_BUS_EDP] = &bus_edp_clk.common.hw,
1507 [CLK_LEDC] = &ledc_clk.common.hw,
1508 [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
1509 [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1510 [CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw,
1511 [CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw,
1512 [CLK_CSI_MCLK2] = &csi_mclk2_clk.common.hw,
1513 [CLK_CSI_MCLK3] = &csi_mclk3_clk.common.hw,
1514 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1515 [CLK_ISP] = &isp_clk.common.hw,
1516 [CLK_DSP] = &dsp_clk.common.hw,
1517 [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
1518 [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
1519 [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
1520 [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
1521 [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
1522 [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
1523 [CLK_FANOUT0] = &fanout0_clk.common.hw,
1524 [CLK_FANOUT1] = &fanout1_clk.common.hw,
1525 [CLK_FANOUT2] = &fanout2_clk.common.hw,
1526 },
1527};
1528
1529static struct ccu_reset_map sun55i_a523_ccu_resets[] = {
1530 [RST_MBUS] = { 0x540, BIT(30) },
1531 [RST_BUS_NSI] = { 0x54c, BIT(16) },
1532 [RST_BUS_DE] = { 0x60c, BIT(16) },
1533 [RST_BUS_DI] = { 0x62c, BIT(16) },
1534 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1535 [RST_BUS_SYS] = { 0x64c, BIT(16) },
1536 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1537 [RST_BUS_CE] = { 0x68c, BIT(16) },
1538 [RST_BUS_SYS_CE] = { 0x68c, BIT(17) },
1539 [RST_BUS_VE] = { 0x69c, BIT(16) },
1540 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1541 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1542 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1543 [RST_BUS_CPUXTIMER] = { 0x74c, BIT(16) },
1544 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1545 [RST_BUS_PWM0] = { 0x7ac, BIT(16) },
1546 [RST_BUS_PWM1] = { 0x7ac, BIT(17) },
1547 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1548 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1549 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1550 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1551 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1552 [RST_BUS_SYSDAP] = { 0x88c, BIT(16) },
1553 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1554 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1555 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1556 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1557 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1558 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1559 [RST_BUS_UART6] = { 0x90c, BIT(22) },
1560 [RST_BUS_UART7] = { 0x90c, BIT(23) },
1561 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1562 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1563 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1564 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1565 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1566 [RST_BUS_I2C5] = { 0x91c, BIT(21) },
1567 [RST_BUS_CAN] = { 0x92c, BIT(16) },
1568 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1569 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1570 [RST_BUS_SPI2] = { 0x96c, BIT(18) },
1571 [RST_BUS_SPIFC] = { 0x96c, BIT(19) },
1572 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1573 [RST_BUS_EMAC1] = { 0x98c, BIT(16) | BIT(17) }, /* GMAC1-AXI */
1574 [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
1575 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1576 [RST_BUS_GPADC0] = { 0x9ec, BIT(16) },
1577 [RST_BUS_GPADC1] = { 0x9ec, BIT(17) },
1578 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1579 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1580 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1581 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1582 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1583 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1584 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1585 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1586 [RST_BUS_3] = { 0xa8c, BIT(25) }, /* BSP + register */
1587 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1588 [RST_BUS_PCIE_USB3] = { 0xaac, BIT(16) },
1589 [RST_BUS_DISPLAY0_TOP] = { 0xabc, BIT(16) },
1590 [RST_BUS_DISPLAY1_TOP] = { 0xacc, BIT(16) },
1591 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1592 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1593 [RST_BUS_MIPI_DSI0] = { 0xb4c, BIT(16) },
1594 [RST_BUS_MIPI_DSI1] = { 0xb4c, BIT(17) },
1595 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1596 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1597 [RST_BUS_TCON_LCD2] = { 0xb7c, BIT(18) },
1598 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1599 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1600 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1601 [RST_BUS_LVDS1] = { 0xbac, BIT(17) },
1602 [RST_BUS_EDP] = { 0xbbc, BIT(16) },
1603 [RST_BUS_VIDEO_OUT0] = { 0xbcc, BIT(16) },
1604 [RST_BUS_VIDEO_OUT1] = { 0xbcc, BIT(17) },
1605 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1606 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1607 [RST_BUS_ISP] = { 0xc2c, BIT(16) }, /* BSP + register */
1608};
1609
1610static const struct sunxi_ccu_desc sun55i_a523_ccu_desc = {
1611 .ccu_clks = sun55i_a523_ccu_clks,
1612 .num_ccu_clks = ARRAY_SIZE(sun55i_a523_ccu_clks),
1613
1614 .hw_clks = &sun55i_a523_hw_clks,
1615
1616 .resets = sun55i_a523_ccu_resets,
1617 .num_resets = ARRAY_SIZE(sun55i_a523_ccu_resets),
1618};
1619
1620static const u32 pll_regs[] = {
1621 SUN55I_A523_PLL_DDR0_REG,
1622 SUN55I_A523_PLL_PERIPH0_REG,
1623 SUN55I_A523_PLL_PERIPH1_REG,
1624 SUN55I_A523_PLL_GPU_REG,
1625 SUN55I_A523_PLL_VIDEO0_REG,
1626 SUN55I_A523_PLL_VIDEO1_REG,
1627 SUN55I_A523_PLL_VIDEO2_REG,
1628 SUN55I_A523_PLL_VE_REG,
1629 SUN55I_A523_PLL_VIDEO3_REG,
1630 SUN55I_A523_PLL_AUDIO0_REG,
1631 SUN55I_A523_PLL_NPU_REG,
1632};
1633
1634static int sun55i_a523_ccu_probe(struct platform_device *pdev)
1635{
1636 void __iomem *reg;
1637 u32 val;
1638 int i, ret;
1639
1640 reg = devm_platform_ioremap_resource(pdev, index: 0);
1641 if (IS_ERR(ptr: reg))
1642 return PTR_ERR(ptr: reg);
1643
1644 /*
1645 * The PLL clock code does not model all bits, for instance it does
1646 * not support a separate enable and gate bit. We present the
1647 * gate bit(27) as the enable bit, but then have to set the
1648 * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here.
1649 */
1650 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1651 val = readl(addr: reg + pll_regs[i]);
1652 val |= BIT(31) | BIT(30) | BIT(29);
1653 writel(val, addr: reg + pll_regs[i]);
1654 }
1655
1656 /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
1657 val = readl(addr: reg + SUN55I_A523_PLL_AUDIO0_REG);
1658 val &= ~(BIT(1) | BIT(0));
1659 writel(val, addr: reg + SUN55I_A523_PLL_AUDIO0_REG);
1660
1661 ret = devm_sunxi_ccu_probe(dev: &pdev->dev, reg, desc: &sun55i_a523_ccu_desc);
1662 if (ret)
1663 return ret;
1664
1665 return 0;
1666}
1667
1668static const struct of_device_id sun55i_a523_ccu_ids[] = {
1669 { .compatible = "allwinner,sun55i-a523-ccu" },
1670 { }
1671};
1672
1673static struct platform_driver sun55i_a523_ccu_driver = {
1674 .probe = sun55i_a523_ccu_probe,
1675 .driver = {
1676 .name = "sun55i-a523-ccu",
1677 .suppress_bind_attrs = true,
1678 .of_match_table = sun55i_a523_ccu_ids,
1679 },
1680};
1681module_platform_driver(sun55i_a523_ccu_driver);
1682
1683MODULE_IMPORT_NS("SUNXI_CCU");
1684MODULE_DESCRIPTION("Support for the Allwinner A523 CCU");
1685MODULE_LICENSE("GPL");
1686

source code of linux/drivers/clk/sunxi-ng/ccu-sun55i-a523.c