1// SPDX-License-Identifier: GPL-2.0+
2//
3// drivers/dma/imx-sdma.c
4//
5// This file contains a driver for the Freescale Smart DMA engine
6//
7// Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
8//
9// Based on code from Freescale:
10//
11// Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
12
13#include <linux/init.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/bitfield.h>
18#include <linux/bitops.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/sched.h>
24#include <linux/semaphore.h>
25#include <linux/spinlock.h>
26#include <linux/device.h>
27#include <linux/dma-mapping.h>
28#include <linux/firmware.h>
29#include <linux/slab.h>
30#include <linux/platform_device.h>
31#include <linux/dmaengine.h>
32#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/of_dma.h>
35#include <linux/workqueue.h>
36
37#include <asm/irq.h>
38#include <linux/dma/imx-dma.h>
39#include <linux/regmap.h>
40#include <linux/mfd/syscon.h>
41#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
42
43#include "dmaengine.h"
44#include "virt-dma.h"
45
46/* SDMA registers */
47#define SDMA_H_C0PTR 0x000
48#define SDMA_H_INTR 0x004
49#define SDMA_H_STATSTOP 0x008
50#define SDMA_H_START 0x00c
51#define SDMA_H_EVTOVR 0x010
52#define SDMA_H_DSPOVR 0x014
53#define SDMA_H_HOSTOVR 0x018
54#define SDMA_H_EVTPEND 0x01c
55#define SDMA_H_DSPENBL 0x020
56#define SDMA_H_RESET 0x024
57#define SDMA_H_EVTERR 0x028
58#define SDMA_H_INTRMSK 0x02c
59#define SDMA_H_PSW 0x030
60#define SDMA_H_EVTERRDBG 0x034
61#define SDMA_H_CONFIG 0x038
62#define SDMA_ONCE_ENB 0x040
63#define SDMA_ONCE_DATA 0x044
64#define SDMA_ONCE_INSTR 0x048
65#define SDMA_ONCE_STAT 0x04c
66#define SDMA_ONCE_CMD 0x050
67#define SDMA_EVT_MIRROR 0x054
68#define SDMA_ILLINSTADDR 0x058
69#define SDMA_CHN0ADDR 0x05c
70#define SDMA_ONCE_RTB 0x060
71#define SDMA_XTRIG_CONF1 0x070
72#define SDMA_XTRIG_CONF2 0x074
73#define SDMA_CHNENBL0_IMX35 0x200
74#define SDMA_CHNENBL0_IMX31 0x080
75#define SDMA_CHNPRI_0 0x100
76#define SDMA_DONE0_CONFIG 0x1000
77
78/*
79 * Buffer descriptor status values.
80 */
81#define BD_DONE 0x01
82#define BD_WRAP 0x02
83#define BD_CONT 0x04
84#define BD_INTR 0x08
85#define BD_RROR 0x10
86#define BD_LAST 0x20
87#define BD_EXTD 0x80
88
89/*
90 * Data Node descriptor status values.
91 */
92#define DND_END_OF_FRAME 0x80
93#define DND_END_OF_XFER 0x40
94#define DND_DONE 0x20
95#define DND_UNUSED 0x01
96
97/*
98 * IPCV2 descriptor status values.
99 */
100#define BD_IPCV2_END_OF_FRAME 0x40
101
102#define IPCV2_MAX_NODES 50
103/*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107#define DATA_ERROR 0x10000000
108
109/*
110 * Buffer descriptor commands.
111 */
112#define C0_ADDR 0x01
113#define C0_LOAD 0x02
114#define C0_DUMP 0x03
115#define C0_SETCTX 0x07
116#define C0_GETCTX 0x03
117#define C0_SETDM 0x01
118#define C0_SETPM 0x04
119#define C0_GETDM 0x02
120#define C0_GETPM 0x08
121/*
122 * Change endianness indicator in the BD command field
123 */
124#define CHANGE_ENDIANNESS 0x80
125
126/*
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
132 * 9 PA 1: Pad Adding
133 * 0: No Pad Adding
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
137 * 0: Source on AIPS
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
146 * LWML event mask
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
150 * HWML event mask
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
160 * by the application
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
164 */
165#define SDMA_WATERMARK_LEVEL_LWML 0xFF
166#define SDMA_WATERMARK_LEVEL_PS BIT(8)
167#define SDMA_WATERMARK_LEVEL_PA BIT(9)
168#define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169#define SDMA_WATERMARK_LEVEL_SP BIT(11)
170#define SDMA_WATERMARK_LEVEL_DP BIT(12)
171#define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172#define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173#define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174#define SDMA_WATERMARK_LEVEL_CONT BIT(31)
175
176#define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
179
180#define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
182 BIT(DMA_DEV_TO_DEV))
183
184#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
185#define SDMA_WATERMARK_LEVEL_OFF_FIFOS GENMASK(19, 16)
186#define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO GENMASK(31, 28)
187#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
188
189#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
190#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
191
192/*
193 * struct sdma_script_start_addrs - SDMA script start pointers
194 *
195 * start addresses of the different functions in the physical
196 * address space of the SDMA engine.
197 */
198struct sdma_script_start_addrs {
199 s32 ap_2_ap_addr;
200 s32 ap_2_bp_addr;
201 s32 ap_2_ap_fixed_addr;
202 s32 bp_2_ap_addr;
203 s32 loopback_on_dsp_side_addr;
204 s32 mcu_interrupt_only_addr;
205 s32 firi_2_per_addr;
206 s32 firi_2_mcu_addr;
207 s32 per_2_firi_addr;
208 s32 mcu_2_firi_addr;
209 s32 uart_2_per_addr;
210 s32 uart_2_mcu_addr;
211 s32 per_2_app_addr;
212 s32 mcu_2_app_addr;
213 s32 per_2_per_addr;
214 s32 uartsh_2_per_addr;
215 s32 uartsh_2_mcu_addr;
216 s32 per_2_shp_addr;
217 s32 mcu_2_shp_addr;
218 s32 ata_2_mcu_addr;
219 s32 mcu_2_ata_addr;
220 s32 app_2_per_addr;
221 s32 app_2_mcu_addr;
222 s32 shp_2_per_addr;
223 s32 shp_2_mcu_addr;
224 s32 mshc_2_mcu_addr;
225 s32 mcu_2_mshc_addr;
226 s32 spdif_2_mcu_addr;
227 s32 mcu_2_spdif_addr;
228 s32 asrc_2_mcu_addr;
229 s32 ext_mem_2_ipu_addr;
230 s32 descrambler_addr;
231 s32 dptc_dvfs_addr;
232 s32 utra_addr;
233 s32 ram_code_start_addr;
234 /* End of v1 array */
235 s32 mcu_2_ssish_addr;
236 s32 ssish_2_mcu_addr;
237 s32 hdmi_dma_addr;
238 /* End of v2 array */
239 s32 zcanfd_2_mcu_addr;
240 s32 zqspi_2_mcu_addr;
241 s32 mcu_2_ecspi_addr;
242 s32 mcu_2_sai_addr;
243 s32 sai_2_mcu_addr;
244 s32 uart_2_mcu_rom_addr;
245 s32 uartsh_2_mcu_rom_addr;
246 /* End of v3 array */
247 s32 mcu_2_zqspi_addr;
248 /* End of v4 array */
249};
250
251/*
252 * Mode/Count of data node descriptors - IPCv2
253 */
254struct sdma_mode_count {
255#define SDMA_BD_MAX_CNT 0xffff
256 u32 count : 16; /* size of the buffer pointed by this BD */
257 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
258 u32 command : 8; /* command mostly used for channel 0 */
259};
260
261/*
262 * Buffer descriptor
263 */
264struct sdma_buffer_descriptor {
265 struct sdma_mode_count mode;
266 u32 buffer_addr; /* address of the buffer described */
267 u32 ext_buffer_addr; /* extended buffer address */
268} __attribute__ ((packed));
269
270/**
271 * struct sdma_channel_control - Channel control Block
272 *
273 * @current_bd_ptr: current buffer descriptor processed
274 * @base_bd_ptr: first element of buffer descriptor array
275 * @unused: padding. The SDMA engine expects an array of 128 byte
276 * control blocks
277 */
278struct sdma_channel_control {
279 u32 current_bd_ptr;
280 u32 base_bd_ptr;
281 u32 unused[2];
282} __attribute__ ((packed));
283
284/**
285 * struct sdma_state_registers - SDMA context for a channel
286 *
287 * @pc: program counter
288 * @unused1: unused
289 * @t: test bit: status of arithmetic & test instruction
290 * @rpc: return program counter
291 * @unused0: unused
292 * @sf: source fault while loading data
293 * @spc: loop start program counter
294 * @unused2: unused
295 * @df: destination fault while storing data
296 * @epc: loop end program counter
297 * @lm: loop mode
298 */
299struct sdma_state_registers {
300 u32 pc :14;
301 u32 unused1: 1;
302 u32 t : 1;
303 u32 rpc :14;
304 u32 unused0: 1;
305 u32 sf : 1;
306 u32 spc :14;
307 u32 unused2: 1;
308 u32 df : 1;
309 u32 epc :14;
310 u32 lm : 2;
311} __attribute__ ((packed));
312
313/**
314 * struct sdma_context_data - sdma context specific to a channel
315 *
316 * @channel_state: channel state bits
317 * @gReg: general registers
318 * @mda: burst dma destination address register
319 * @msa: burst dma source address register
320 * @ms: burst dma status register
321 * @md: burst dma data register
322 * @pda: peripheral dma destination address register
323 * @psa: peripheral dma source address register
324 * @ps: peripheral dma status register
325 * @pd: peripheral dma data register
326 * @ca: CRC polynomial register
327 * @cs: CRC accumulator register
328 * @dda: dedicated core destination address register
329 * @dsa: dedicated core source address register
330 * @ds: dedicated core status register
331 * @dd: dedicated core data register
332 * @scratch0: 1st word of dedicated ram for context switch
333 * @scratch1: 2nd word of dedicated ram for context switch
334 * @scratch2: 3rd word of dedicated ram for context switch
335 * @scratch3: 4th word of dedicated ram for context switch
336 * @scratch4: 5th word of dedicated ram for context switch
337 * @scratch5: 6th word of dedicated ram for context switch
338 * @scratch6: 7th word of dedicated ram for context switch
339 * @scratch7: 8th word of dedicated ram for context switch
340 */
341struct sdma_context_data {
342 struct sdma_state_registers channel_state;
343 u32 gReg[8];
344 u32 mda;
345 u32 msa;
346 u32 ms;
347 u32 md;
348 u32 pda;
349 u32 psa;
350 u32 ps;
351 u32 pd;
352 u32 ca;
353 u32 cs;
354 u32 dda;
355 u32 dsa;
356 u32 ds;
357 u32 dd;
358 u32 scratch0;
359 u32 scratch1;
360 u32 scratch2;
361 u32 scratch3;
362 u32 scratch4;
363 u32 scratch5;
364 u32 scratch6;
365 u32 scratch7;
366} __attribute__ ((packed));
367
368
369struct sdma_engine;
370
371/**
372 * struct sdma_desc - descriptor structor for one transfer
373 * @vd: descriptor for virt dma
374 * @num_bd: number of descriptors currently handling
375 * @bd_phys: physical address of bd
376 * @buf_tail: ID of the buffer that was processed
377 * @buf_ptail: ID of the previous buffer that was processed
378 * @period_len: period length, used in cyclic.
379 * @chn_real_count: the real count updated from bd->mode.count
380 * @chn_count: the transfer count set
381 * @sdmac: sdma_channel pointer
382 * @bd: pointer of allocate bd
383 */
384struct sdma_desc {
385 struct virt_dma_desc vd;
386 unsigned int num_bd;
387 dma_addr_t bd_phys;
388 unsigned int buf_tail;
389 unsigned int buf_ptail;
390 unsigned int period_len;
391 unsigned int chn_real_count;
392 unsigned int chn_count;
393 struct sdma_channel *sdmac;
394 struct sdma_buffer_descriptor *bd;
395};
396
397/**
398 * struct sdma_channel - housekeeping for a SDMA channel
399 *
400 * @vc: virt_dma base structure
401 * @desc: sdma description including vd and other special member
402 * @sdma: pointer to the SDMA engine for this channel
403 * @channel: the channel number, matches dmaengine chan_id + 1
404 * @direction: transfer type. Needed for setting SDMA script
405 * @slave_config: Slave configuration
406 * @peripheral_type: Peripheral type. Needed for setting SDMA script
407 * @event_id0: aka dma request line
408 * @event_id1: for channels that use 2 events
409 * @word_size: peripheral access size
410 * @pc_from_device: script address for those device_2_memory
411 * @pc_to_device: script address for those memory_2_device
412 * @device_to_device: script address for those device_2_device
413 * @pc_to_pc: script address for those memory_2_memory
414 * @flags: loop mode or not
415 * @per_address: peripheral source or destination address in common case
416 * destination address in p_2_p case
417 * @per_address2: peripheral source address in p_2_p case
418 * @event_mask: event mask used in p_2_p script
419 * @watermark_level: value for gReg[7], some script will extend it from
420 * basic watermark such as p_2_p
421 * @shp_addr: value for gReg[6]
422 * @per_addr: value for gReg[2]
423 * @status: status of dma channel
424 * @data: specific sdma interface structure
425 * @terminate_worker: used to call back into terminate work function
426 * @terminated: terminated list
427 * @is_ram_script: flag for script in ram
428 * @n_fifos_src: number of source device fifos
429 * @n_fifos_dst: number of destination device fifos
430 * @sw_done: software done flag
431 * @stride_fifos_src: stride for source device FIFOs
432 * @stride_fifos_dst: stride for destination device FIFOs
433 * @words_per_fifo: copy number of words one time for one FIFO
434 */
435struct sdma_channel {
436 struct virt_dma_chan vc;
437 struct sdma_desc *desc;
438 struct sdma_engine *sdma;
439 unsigned int channel;
440 enum dma_transfer_direction direction;
441 struct dma_slave_config slave_config;
442 enum sdma_peripheral_type peripheral_type;
443 unsigned int event_id0;
444 unsigned int event_id1;
445 enum dma_slave_buswidth word_size;
446 unsigned int pc_from_device, pc_to_device;
447 unsigned int device_to_device;
448 unsigned int pc_to_pc;
449 unsigned long flags;
450 dma_addr_t per_address, per_address2;
451 unsigned long event_mask[2];
452 unsigned long watermark_level;
453 u32 shp_addr, per_addr;
454 enum dma_status status;
455 struct imx_dma_data data;
456 struct work_struct terminate_worker;
457 struct list_head terminated;
458 bool is_ram_script;
459 unsigned int n_fifos_src;
460 unsigned int n_fifos_dst;
461 unsigned int stride_fifos_src;
462 unsigned int stride_fifos_dst;
463 unsigned int words_per_fifo;
464 bool sw_done;
465};
466
467#define IMX_DMA_SG_LOOP BIT(0)
468
469#define MAX_DMA_CHANNELS 32
470#define MXC_SDMA_DEFAULT_PRIORITY 1
471#define MXC_SDMA_MIN_PRIORITY 1
472#define MXC_SDMA_MAX_PRIORITY 7
473
474#define SDMA_FIRMWARE_MAGIC 0x414d4453
475
476/**
477 * struct sdma_firmware_header - Layout of the firmware image
478 *
479 * @magic: "SDMA"
480 * @version_major: increased whenever layout of struct
481 * sdma_script_start_addrs changes.
482 * @version_minor: firmware minor version (for binary compatible changes)
483 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
484 * @num_script_addrs: Number of script addresses in this image
485 * @ram_code_start: offset of SDMA ram image in this firmware image
486 * @ram_code_size: size of SDMA ram image
487 */
488struct sdma_firmware_header {
489 u32 magic;
490 u32 version_major;
491 u32 version_minor;
492 u32 script_addrs_start;
493 u32 num_script_addrs;
494 u32 ram_code_start;
495 u32 ram_code_size;
496};
497
498struct sdma_driver_data {
499 int chnenbl0;
500 int num_events;
501 struct sdma_script_start_addrs *script_addrs;
502 bool check_ratio;
503 /*
504 * ecspi ERR009165 fixed should be done in sdma script
505 * and it has been fixed in soc from i.mx6ul.
506 * please get more information from the below link:
507 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
508 */
509 bool ecspi_fixed;
510};
511
512struct sdma_engine {
513 struct device *dev;
514 struct sdma_channel channel[MAX_DMA_CHANNELS];
515 struct sdma_channel_control *channel_control;
516 void __iomem *regs;
517 struct sdma_context_data *context;
518 dma_addr_t context_phys;
519 struct dma_device dma_device;
520 struct clk *clk_ipg;
521 struct clk *clk_ahb;
522 spinlock_t channel_0_lock;
523 u32 script_number;
524 struct sdma_script_start_addrs *script_addrs;
525 const struct sdma_driver_data *drvdata;
526 u32 spba_start_addr;
527 u32 spba_end_addr;
528 unsigned int irq;
529 dma_addr_t bd0_phys;
530 struct sdma_buffer_descriptor *bd0;
531 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
532 bool clk_ratio;
533 bool fw_loaded;
534};
535
536static int sdma_config_write(struct dma_chan *chan,
537 struct dma_slave_config *dmaengine_cfg,
538 enum dma_transfer_direction direction);
539
540static struct sdma_driver_data sdma_imx31 = {
541 .chnenbl0 = SDMA_CHNENBL0_IMX31,
542 .num_events = 32,
543};
544
545static struct sdma_script_start_addrs sdma_script_imx25 = {
546 .ap_2_ap_addr = 729,
547 .uart_2_mcu_addr = 904,
548 .per_2_app_addr = 1255,
549 .mcu_2_app_addr = 834,
550 .uartsh_2_mcu_addr = 1120,
551 .per_2_shp_addr = 1329,
552 .mcu_2_shp_addr = 1048,
553 .ata_2_mcu_addr = 1560,
554 .mcu_2_ata_addr = 1479,
555 .app_2_per_addr = 1189,
556 .app_2_mcu_addr = 770,
557 .shp_2_per_addr = 1407,
558 .shp_2_mcu_addr = 979,
559};
560
561static struct sdma_driver_data sdma_imx25 = {
562 .chnenbl0 = SDMA_CHNENBL0_IMX35,
563 .num_events = 48,
564 .script_addrs = &sdma_script_imx25,
565};
566
567static struct sdma_driver_data sdma_imx35 = {
568 .chnenbl0 = SDMA_CHNENBL0_IMX35,
569 .num_events = 48,
570};
571
572static struct sdma_script_start_addrs sdma_script_imx51 = {
573 .ap_2_ap_addr = 642,
574 .uart_2_mcu_addr = 817,
575 .mcu_2_app_addr = 747,
576 .mcu_2_shp_addr = 961,
577 .ata_2_mcu_addr = 1473,
578 .mcu_2_ata_addr = 1392,
579 .app_2_per_addr = 1033,
580 .app_2_mcu_addr = 683,
581 .shp_2_per_addr = 1251,
582 .shp_2_mcu_addr = 892,
583};
584
585static struct sdma_driver_data sdma_imx51 = {
586 .chnenbl0 = SDMA_CHNENBL0_IMX35,
587 .num_events = 48,
588 .script_addrs = &sdma_script_imx51,
589};
590
591static struct sdma_script_start_addrs sdma_script_imx53 = {
592 .ap_2_ap_addr = 642,
593 .app_2_mcu_addr = 683,
594 .mcu_2_app_addr = 747,
595 .uart_2_mcu_addr = 817,
596 .shp_2_mcu_addr = 891,
597 .mcu_2_shp_addr = 960,
598 .uartsh_2_mcu_addr = 1032,
599 .spdif_2_mcu_addr = 1100,
600 .mcu_2_spdif_addr = 1134,
601 .firi_2_mcu_addr = 1193,
602 .mcu_2_firi_addr = 1290,
603};
604
605static struct sdma_driver_data sdma_imx53 = {
606 .chnenbl0 = SDMA_CHNENBL0_IMX35,
607 .num_events = 48,
608 .script_addrs = &sdma_script_imx53,
609};
610
611static struct sdma_script_start_addrs sdma_script_imx6q = {
612 .ap_2_ap_addr = 642,
613 .uart_2_mcu_addr = 817,
614 .mcu_2_app_addr = 747,
615 .per_2_per_addr = 6331,
616 .uartsh_2_mcu_addr = 1032,
617 .mcu_2_shp_addr = 960,
618 .app_2_mcu_addr = 683,
619 .shp_2_mcu_addr = 891,
620 .spdif_2_mcu_addr = 1100,
621 .mcu_2_spdif_addr = 1134,
622};
623
624static struct sdma_driver_data sdma_imx6q = {
625 .chnenbl0 = SDMA_CHNENBL0_IMX35,
626 .num_events = 48,
627 .script_addrs = &sdma_script_imx6q,
628};
629
630static struct sdma_driver_data sdma_imx6ul = {
631 .chnenbl0 = SDMA_CHNENBL0_IMX35,
632 .num_events = 48,
633 .script_addrs = &sdma_script_imx6q,
634 .ecspi_fixed = true,
635};
636
637static struct sdma_script_start_addrs sdma_script_imx7d = {
638 .ap_2_ap_addr = 644,
639 .uart_2_mcu_addr = 819,
640 .mcu_2_app_addr = 749,
641 .uartsh_2_mcu_addr = 1034,
642 .mcu_2_shp_addr = 962,
643 .app_2_mcu_addr = 685,
644 .shp_2_mcu_addr = 893,
645 .spdif_2_mcu_addr = 1102,
646 .mcu_2_spdif_addr = 1136,
647};
648
649static struct sdma_driver_data sdma_imx7d = {
650 .chnenbl0 = SDMA_CHNENBL0_IMX35,
651 .num_events = 48,
652 .script_addrs = &sdma_script_imx7d,
653};
654
655static struct sdma_driver_data sdma_imx8mq = {
656 .chnenbl0 = SDMA_CHNENBL0_IMX35,
657 .num_events = 48,
658 .script_addrs = &sdma_script_imx7d,
659 .check_ratio = 1,
660};
661
662static const struct of_device_id sdma_dt_ids[] = {
663 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
664 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
665 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
666 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
667 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
668 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
669 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
670 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
671 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
672 { /* sentinel */ }
673};
674MODULE_DEVICE_TABLE(of, sdma_dt_ids);
675
676#define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
677#define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
678#define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
679#define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
680
681static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
682{
683 u32 chnenbl0 = sdma->drvdata->chnenbl0;
684 return chnenbl0 + event * 4;
685}
686
687static int sdma_config_ownership(struct sdma_channel *sdmac,
688 bool event_override, bool mcu_override, bool dsp_override)
689{
690 struct sdma_engine *sdma = sdmac->sdma;
691 int channel = sdmac->channel;
692 unsigned long evt, mcu, dsp;
693
694 if (event_override && mcu_override && dsp_override)
695 return -EINVAL;
696
697 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
698 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
699 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
700
701 if (dsp_override)
702 __clear_bit(channel, &dsp);
703 else
704 __set_bit(channel, &dsp);
705
706 if (event_override)
707 __clear_bit(channel, &evt);
708 else
709 __set_bit(channel, &evt);
710
711 if (mcu_override)
712 __clear_bit(channel, &mcu);
713 else
714 __set_bit(channel, &mcu);
715
716 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
717 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
718 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
719
720 return 0;
721}
722
723static int is_sdma_channel_enabled(struct sdma_engine *sdma, int channel)
724{
725 return !!(readl(addr: sdma->regs + SDMA_H_STATSTOP) & BIT(channel));
726}
727
728static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
729{
730 writel(BIT(channel), addr: sdma->regs + SDMA_H_START);
731}
732
733/*
734 * sdma_run_channel0 - run a channel and wait till it's done
735 */
736static int sdma_run_channel0(struct sdma_engine *sdma)
737{
738 int ret;
739 u32 reg;
740
741 sdma_enable_channel(sdma, channel: 0);
742
743 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
744 reg, !(reg & 1), 1, 500);
745 if (ret)
746 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
747
748 /* Set bits of CONFIG register with dynamic context switching */
749 reg = readl(addr: sdma->regs + SDMA_H_CONFIG);
750 if ((reg & SDMA_H_CONFIG_CSM) == 0) {
751 reg |= SDMA_H_CONFIG_CSM;
752 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
753 }
754
755 return ret;
756}
757
758static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
759 u32 address)
760{
761 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
762 void *buf_virt;
763 dma_addr_t buf_phys;
764 int ret;
765 unsigned long flags;
766
767 buf_virt = dma_alloc_coherent(dev: sdma->dev, size, dma_handle: &buf_phys, GFP_KERNEL);
768 if (!buf_virt)
769 return -ENOMEM;
770
771 spin_lock_irqsave(&sdma->channel_0_lock, flags);
772
773 bd0->mode.command = C0_SETPM;
774 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
775 bd0->mode.count = size / 2;
776 bd0->buffer_addr = buf_phys;
777 bd0->ext_buffer_addr = address;
778
779 memcpy(buf_virt, buf, size);
780
781 ret = sdma_run_channel0(sdma);
782
783 spin_unlock_irqrestore(lock: &sdma->channel_0_lock, flags);
784
785 dma_free_coherent(dev: sdma->dev, size, cpu_addr: buf_virt, dma_handle: buf_phys);
786
787 return ret;
788}
789
790static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
791{
792 struct sdma_engine *sdma = sdmac->sdma;
793 int channel = sdmac->channel;
794 unsigned long val;
795 u32 chnenbl = chnenbl_ofs(sdma, event);
796
797 val = readl_relaxed(sdma->regs + chnenbl);
798 __set_bit(channel, &val);
799 writel_relaxed(val, sdma->regs + chnenbl);
800
801 /* Set SDMA_DONEx_CONFIG is sw_done enabled */
802 if (sdmac->sw_done) {
803 val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
804 val |= SDMA_DONE0_CONFIG_DONE_SEL;
805 val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
806 writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
807 }
808}
809
810static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
811{
812 struct sdma_engine *sdma = sdmac->sdma;
813 int channel = sdmac->channel;
814 u32 chnenbl = chnenbl_ofs(sdma, event);
815 unsigned long val;
816
817 val = readl_relaxed(sdma->regs + chnenbl);
818 __clear_bit(channel, &val);
819 writel_relaxed(val, sdma->regs + chnenbl);
820}
821
822static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
823{
824 return container_of(t, struct sdma_desc, vd.tx);
825}
826
827static void sdma_start_desc(struct sdma_channel *sdmac)
828{
829 struct virt_dma_desc *vd = vchan_next_desc(vc: &sdmac->vc);
830 struct sdma_desc *desc;
831 struct sdma_engine *sdma = sdmac->sdma;
832 int channel = sdmac->channel;
833
834 if (!vd) {
835 sdmac->desc = NULL;
836 return;
837 }
838 sdmac->desc = desc = to_sdma_desc(t: &vd->tx);
839
840 list_del(entry: &vd->node);
841
842 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
843 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
844 sdma_enable_channel(sdma, channel: sdmac->channel);
845}
846
847static void sdma_update_channel_loop(struct sdma_channel *sdmac)
848{
849 struct sdma_buffer_descriptor *bd;
850 int error = 0;
851 enum dma_status old_status = sdmac->status;
852
853 /*
854 * loop mode. Iterate over descriptors, re-setup them and
855 * call callback function.
856 */
857 while (sdmac->desc) {
858 struct sdma_desc *desc = sdmac->desc;
859
860 bd = &desc->bd[desc->buf_tail];
861
862 if (bd->mode.status & BD_DONE)
863 break;
864
865 if (bd->mode.status & BD_RROR) {
866 bd->mode.status &= ~BD_RROR;
867 sdmac->status = DMA_ERROR;
868 error = -EIO;
869 }
870
871 /*
872 * We use bd->mode.count to calculate the residue, since contains
873 * the number of bytes present in the current buffer descriptor.
874 */
875
876 desc->chn_real_count = bd->mode.count;
877 bd->mode.count = desc->period_len;
878 desc->buf_ptail = desc->buf_tail;
879 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
880
881 /*
882 * The callback is called from the interrupt context in order
883 * to reduce latency and to avoid the risk of altering the
884 * SDMA transaction status by the time the client tasklet is
885 * executed.
886 */
887 spin_unlock(lock: &sdmac->vc.lock);
888 dmaengine_desc_get_callback_invoke(tx: &desc->vd.tx, NULL);
889 spin_lock(lock: &sdmac->vc.lock);
890
891 /* Assign buffer ownership to SDMA */
892 bd->mode.status |= BD_DONE;
893
894 if (error)
895 sdmac->status = old_status;
896 }
897
898 /*
899 * SDMA stops cyclic channel when DMA request triggers a channel and no SDMA
900 * owned buffer is available (i.e. BD_DONE was set too late).
901 */
902 if (sdmac->desc && !is_sdma_channel_enabled(sdma: sdmac->sdma, channel: sdmac->channel)) {
903 dev_warn(sdmac->sdma->dev, "restart cyclic channel %d\n", sdmac->channel);
904 sdma_enable_channel(sdma: sdmac->sdma, channel: sdmac->channel);
905 }
906}
907
908static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
909{
910 struct sdma_channel *sdmac = (struct sdma_channel *) data;
911 struct sdma_buffer_descriptor *bd;
912 int i, error = 0;
913
914 sdmac->desc->chn_real_count = 0;
915 /*
916 * non loop mode. Iterate over all descriptors, collect
917 * errors and call callback function
918 */
919 for (i = 0; i < sdmac->desc->num_bd; i++) {
920 bd = &sdmac->desc->bd[i];
921
922 if (bd->mode.status & (BD_DONE | BD_RROR))
923 error = -EIO;
924 sdmac->desc->chn_real_count += bd->mode.count;
925 }
926
927 if (error)
928 sdmac->status = DMA_ERROR;
929 else
930 sdmac->status = DMA_COMPLETE;
931}
932
933static irqreturn_t sdma_int_handler(int irq, void *dev_id)
934{
935 struct sdma_engine *sdma = dev_id;
936 unsigned long stat;
937
938 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
939 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
940 /* channel 0 is special and not handled here, see run_channel0() */
941 stat &= ~1;
942
943 while (stat) {
944 int channel = fls(x: stat) - 1;
945 struct sdma_channel *sdmac = &sdma->channel[channel];
946 struct sdma_desc *desc;
947
948 spin_lock(lock: &sdmac->vc.lock);
949 desc = sdmac->desc;
950 if (desc) {
951 if (sdmac->flags & IMX_DMA_SG_LOOP) {
952 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
953 sdma_update_channel_loop(sdmac);
954 else
955 vchan_cyclic_callback(vd: &desc->vd);
956 } else {
957 mxc_sdma_handle_channel_normal(data: sdmac);
958 vchan_cookie_complete(vd: &desc->vd);
959 sdma_start_desc(sdmac);
960 }
961 }
962
963 spin_unlock(lock: &sdmac->vc.lock);
964 __clear_bit(channel, &stat);
965 }
966
967 return IRQ_HANDLED;
968}
969
970/*
971 * sets the pc of SDMA script according to the peripheral type
972 */
973static int sdma_get_pc(struct sdma_channel *sdmac,
974 enum sdma_peripheral_type peripheral_type)
975{
976 struct sdma_engine *sdma = sdmac->sdma;
977 int per_2_emi = 0, emi_2_per = 0;
978 /*
979 * These are needed once we start to support transfers between
980 * two peripherals or memory-to-memory transfers
981 */
982 int per_2_per = 0, emi_2_emi = 0;
983
984 sdmac->pc_from_device = 0;
985 sdmac->pc_to_device = 0;
986 sdmac->device_to_device = 0;
987 sdmac->pc_to_pc = 0;
988 sdmac->is_ram_script = false;
989
990 switch (peripheral_type) {
991 case IMX_DMATYPE_MEMORY:
992 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
993 break;
994 case IMX_DMATYPE_DSP:
995 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
996 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
997 break;
998 case IMX_DMATYPE_FIRI:
999 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
1000 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
1001 break;
1002 case IMX_DMATYPE_UART:
1003 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
1004 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1005 break;
1006 case IMX_DMATYPE_UART_SP:
1007 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
1008 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1009 break;
1010 case IMX_DMATYPE_ATA:
1011 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
1012 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
1013 break;
1014 case IMX_DMATYPE_CSPI:
1015 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1016
1017 /* Use rom script mcu_2_app if ERR009165 fixed */
1018 if (sdmac->sdma->drvdata->ecspi_fixed) {
1019 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1020 } else {
1021 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
1022 sdmac->is_ram_script = true;
1023 }
1024
1025 break;
1026 case IMX_DMATYPE_EXT:
1027 case IMX_DMATYPE_SSI:
1028 case IMX_DMATYPE_SAI:
1029 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
1030 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
1031 break;
1032 case IMX_DMATYPE_SSI_DUAL:
1033 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
1034 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
1035 sdmac->is_ram_script = true;
1036 break;
1037 case IMX_DMATYPE_SSI_SP:
1038 case IMX_DMATYPE_MMC:
1039 case IMX_DMATYPE_SDHC:
1040 case IMX_DMATYPE_CSPI_SP:
1041 case IMX_DMATYPE_ESAI:
1042 case IMX_DMATYPE_MSHC_SP:
1043 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1044 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1045 break;
1046 case IMX_DMATYPE_ASRC:
1047 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
1048 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
1049 per_2_per = sdma->script_addrs->per_2_per_addr;
1050 sdmac->is_ram_script = true;
1051 break;
1052 case IMX_DMATYPE_ASRC_SP:
1053 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1054 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1055 per_2_per = sdma->script_addrs->per_2_per_addr;
1056 break;
1057 case IMX_DMATYPE_MSHC:
1058 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
1059 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
1060 break;
1061 case IMX_DMATYPE_CCM:
1062 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
1063 break;
1064 case IMX_DMATYPE_SPDIF:
1065 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
1066 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
1067 break;
1068 case IMX_DMATYPE_IPU_MEMORY:
1069 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
1070 break;
1071 case IMX_DMATYPE_MULTI_SAI:
1072 per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
1073 emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
1074 break;
1075 case IMX_DMATYPE_HDMI:
1076 emi_2_per = sdma->script_addrs->hdmi_dma_addr;
1077 sdmac->is_ram_script = true;
1078 break;
1079 default:
1080 dev_err(sdma->dev, "Unsupported transfer type %d\n",
1081 peripheral_type);
1082 return -EINVAL;
1083 }
1084
1085 sdmac->pc_from_device = per_2_emi;
1086 sdmac->pc_to_device = emi_2_per;
1087 sdmac->device_to_device = per_2_per;
1088 sdmac->pc_to_pc = emi_2_emi;
1089
1090 return 0;
1091}
1092
1093static int sdma_load_context(struct sdma_channel *sdmac)
1094{
1095 struct sdma_engine *sdma = sdmac->sdma;
1096 int channel = sdmac->channel;
1097 int load_address;
1098 struct sdma_context_data *context = sdma->context;
1099 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
1100 int ret;
1101 unsigned long flags;
1102
1103 if (sdmac->direction == DMA_DEV_TO_MEM)
1104 load_address = sdmac->pc_from_device;
1105 else if (sdmac->direction == DMA_DEV_TO_DEV)
1106 load_address = sdmac->device_to_device;
1107 else if (sdmac->direction == DMA_MEM_TO_MEM)
1108 load_address = sdmac->pc_to_pc;
1109 else
1110 load_address = sdmac->pc_to_device;
1111
1112 if (load_address < 0)
1113 return load_address;
1114
1115 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1116 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1117 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1118 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1119 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1120 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1121
1122 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1123
1124 memset(context, 0, sizeof(*context));
1125 context->channel_state.pc = load_address;
1126
1127 /* Send by context the event mask,base address for peripheral
1128 * and watermark level
1129 */
1130 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1131 context->gReg[4] = sdmac->per_addr;
1132 context->gReg[6] = sdmac->shp_addr;
1133 } else {
1134 context->gReg[0] = sdmac->event_mask[1];
1135 context->gReg[1] = sdmac->event_mask[0];
1136 context->gReg[2] = sdmac->per_addr;
1137 context->gReg[6] = sdmac->shp_addr;
1138 context->gReg[7] = sdmac->watermark_level;
1139 }
1140
1141 bd0->mode.command = C0_SETDM;
1142 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1143 bd0->mode.count = sizeof(*context) / 4;
1144 bd0->buffer_addr = sdma->context_phys;
1145 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1146 ret = sdma_run_channel0(sdma);
1147
1148 spin_unlock_irqrestore(lock: &sdma->channel_0_lock, flags);
1149
1150 return ret;
1151}
1152
1153static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1154{
1155 return container_of(chan, struct sdma_channel, vc.chan);
1156}
1157
1158static int sdma_disable_channel(struct dma_chan *chan)
1159{
1160 struct sdma_channel *sdmac = to_sdma_chan(chan);
1161 struct sdma_engine *sdma = sdmac->sdma;
1162 int channel = sdmac->channel;
1163
1164 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1165 sdmac->status = DMA_ERROR;
1166
1167 return 0;
1168}
1169static void sdma_channel_terminate_work(struct work_struct *work)
1170{
1171 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1172 terminate_worker);
1173 /*
1174 * According to NXP R&D team a delay of one BD SDMA cost time
1175 * (maximum is 1ms) should be added after disable of the channel
1176 * bit, to ensure SDMA core has really been stopped after SDMA
1177 * clients call .device_terminate_all.
1178 */
1179 usleep_range(min: 1000, max: 2000);
1180
1181 vchan_dma_desc_free_list(vc: &sdmac->vc, head: &sdmac->terminated);
1182}
1183
1184static int sdma_terminate_all(struct dma_chan *chan)
1185{
1186 struct sdma_channel *sdmac = to_sdma_chan(chan);
1187 unsigned long flags;
1188
1189 spin_lock_irqsave(&sdmac->vc.lock, flags);
1190
1191 sdma_disable_channel(chan);
1192
1193 if (sdmac->desc) {
1194 vchan_terminate_vdesc(vd: &sdmac->desc->vd);
1195 /*
1196 * move out current descriptor into terminated list so that
1197 * it could be free in sdma_channel_terminate_work alone
1198 * later without potential involving next descriptor raised
1199 * up before the last descriptor terminated.
1200 */
1201 vchan_get_all_descriptors(vc: &sdmac->vc, head: &sdmac->terminated);
1202 sdmac->desc = NULL;
1203 schedule_work(work: &sdmac->terminate_worker);
1204 }
1205
1206 spin_unlock_irqrestore(lock: &sdmac->vc.lock, flags);
1207
1208 return 0;
1209}
1210
1211static void sdma_channel_synchronize(struct dma_chan *chan)
1212{
1213 struct sdma_channel *sdmac = to_sdma_chan(chan);
1214
1215 vchan_synchronize(vc: &sdmac->vc);
1216
1217 flush_work(work: &sdmac->terminate_worker);
1218}
1219
1220static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1221{
1222 struct sdma_engine *sdma = sdmac->sdma;
1223
1224 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1225 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1226
1227 set_bit(nr: sdmac->event_id0 % 32, addr: &sdmac->event_mask[1]);
1228 set_bit(nr: sdmac->event_id1 % 32, addr: &sdmac->event_mask[0]);
1229
1230 if (sdmac->event_id0 > 31)
1231 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1232
1233 if (sdmac->event_id1 > 31)
1234 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1235
1236 /*
1237 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1238 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1239 * r0(event_mask[1]) and r1(event_mask[0]).
1240 */
1241 if (lwml > hwml) {
1242 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1243 SDMA_WATERMARK_LEVEL_HWML);
1244 sdmac->watermark_level |= hwml;
1245 sdmac->watermark_level |= lwml << 16;
1246 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1247 }
1248
1249 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1250 sdmac->per_address2 <= sdma->spba_end_addr)
1251 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1252
1253 if (sdmac->per_address >= sdma->spba_start_addr &&
1254 sdmac->per_address <= sdma->spba_end_addr)
1255 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1256
1257 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1258}
1259
1260static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
1261{
1262 unsigned int n_fifos;
1263 unsigned int stride_fifos;
1264 unsigned int words_per_fifo;
1265
1266 if (sdmac->sw_done)
1267 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
1268
1269 if (sdmac->direction == DMA_DEV_TO_MEM) {
1270 n_fifos = sdmac->n_fifos_src;
1271 stride_fifos = sdmac->stride_fifos_src;
1272 } else {
1273 n_fifos = sdmac->n_fifos_dst;
1274 stride_fifos = sdmac->stride_fifos_dst;
1275 }
1276
1277 words_per_fifo = sdmac->words_per_fifo;
1278
1279 sdmac->watermark_level |=
1280 FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, n_fifos);
1281 sdmac->watermark_level |=
1282 FIELD_PREP(SDMA_WATERMARK_LEVEL_OFF_FIFOS, stride_fifos);
1283 if (words_per_fifo)
1284 sdmac->watermark_level |=
1285 FIELD_PREP(SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO, (words_per_fifo - 1));
1286}
1287
1288static int sdma_config_channel(struct dma_chan *chan)
1289{
1290 struct sdma_channel *sdmac = to_sdma_chan(chan);
1291 int ret;
1292
1293 sdma_disable_channel(chan);
1294
1295 sdmac->event_mask[0] = 0;
1296 sdmac->event_mask[1] = 0;
1297 sdmac->shp_addr = 0;
1298 sdmac->per_addr = 0;
1299
1300 switch (sdmac->peripheral_type) {
1301 case IMX_DMATYPE_DSP:
1302 sdma_config_ownership(sdmac, event_override: false, mcu_override: true, dsp_override: true);
1303 break;
1304 case IMX_DMATYPE_MEMORY:
1305 sdma_config_ownership(sdmac, event_override: false, mcu_override: true, dsp_override: false);
1306 break;
1307 default:
1308 sdma_config_ownership(sdmac, event_override: true, mcu_override: true, dsp_override: false);
1309 break;
1310 }
1311
1312 ret = sdma_get_pc(sdmac, peripheral_type: sdmac->peripheral_type);
1313 if (ret)
1314 return ret;
1315
1316 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1317 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1318 /* Handle multiple event channels differently */
1319 if (sdmac->event_id1) {
1320 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1321 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1322 sdma_set_watermarklevel_for_p2p(sdmac);
1323 } else {
1324 if (sdmac->peripheral_type ==
1325 IMX_DMATYPE_MULTI_SAI)
1326 sdma_set_watermarklevel_for_sais(sdmac);
1327
1328 __set_bit(sdmac->event_id0, sdmac->event_mask);
1329 }
1330
1331 /* Address */
1332 sdmac->shp_addr = sdmac->per_address;
1333 sdmac->per_addr = sdmac->per_address2;
1334 } else {
1335 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1336 }
1337
1338 return 0;
1339}
1340
1341static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1342 unsigned int priority)
1343{
1344 struct sdma_engine *sdma = sdmac->sdma;
1345 int channel = sdmac->channel;
1346
1347 if (priority < MXC_SDMA_MIN_PRIORITY
1348 || priority > MXC_SDMA_MAX_PRIORITY) {
1349 return -EINVAL;
1350 }
1351
1352 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1353
1354 return 0;
1355}
1356
1357static int sdma_request_channel0(struct sdma_engine *sdma)
1358{
1359 int ret = -EBUSY;
1360
1361 sdma->bd0 = dma_alloc_coherent(dev: sdma->dev, PAGE_SIZE, dma_handle: &sdma->bd0_phys,
1362 GFP_NOWAIT);
1363 if (!sdma->bd0) {
1364 ret = -ENOMEM;
1365 goto out;
1366 }
1367
1368 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1369 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1370
1371 sdma_set_channel_priority(sdmac: &sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1372 return 0;
1373out:
1374
1375 return ret;
1376}
1377
1378
1379static int sdma_alloc_bd(struct sdma_desc *desc)
1380{
1381 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1382 int ret = 0;
1383
1384 desc->bd = dma_alloc_coherent(dev: desc->sdmac->sdma->dev, size: bd_size,
1385 dma_handle: &desc->bd_phys, GFP_NOWAIT);
1386 if (!desc->bd) {
1387 ret = -ENOMEM;
1388 goto out;
1389 }
1390out:
1391 return ret;
1392}
1393
1394static void sdma_free_bd(struct sdma_desc *desc)
1395{
1396 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1397
1398 dma_free_coherent(dev: desc->sdmac->sdma->dev, size: bd_size, cpu_addr: desc->bd,
1399 dma_handle: desc->bd_phys);
1400}
1401
1402static void sdma_desc_free(struct virt_dma_desc *vd)
1403{
1404 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1405
1406 sdma_free_bd(desc);
1407 kfree(objp: desc);
1408}
1409
1410static int sdma_alloc_chan_resources(struct dma_chan *chan)
1411{
1412 struct sdma_channel *sdmac = to_sdma_chan(chan);
1413 struct imx_dma_data *data = chan->private;
1414 struct imx_dma_data mem_data;
1415 int prio, ret;
1416
1417 /*
1418 * MEMCPY may never setup chan->private by filter function such as
1419 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1420 * Please note in any other slave case, you have to setup chan->private
1421 * with 'struct imx_dma_data' in your own filter function if you want to
1422 * request dma channel by dma_request_channel() rather than
1423 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1424 * to warn you to correct your filter function.
1425 */
1426 if (!data) {
1427 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1428 mem_data.priority = 2;
1429 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1430 mem_data.dma_request = 0;
1431 mem_data.dma_request2 = 0;
1432 data = &mem_data;
1433
1434 ret = sdma_get_pc(sdmac, peripheral_type: IMX_DMATYPE_MEMORY);
1435 if (ret)
1436 return ret;
1437 }
1438
1439 switch (data->priority) {
1440 case DMA_PRIO_HIGH:
1441 prio = 3;
1442 break;
1443 case DMA_PRIO_MEDIUM:
1444 prio = 2;
1445 break;
1446 case DMA_PRIO_LOW:
1447 default:
1448 prio = 1;
1449 break;
1450 }
1451
1452 sdmac->peripheral_type = data->peripheral_type;
1453 sdmac->event_id0 = data->dma_request;
1454 sdmac->event_id1 = data->dma_request2;
1455
1456 ret = clk_enable(clk: sdmac->sdma->clk_ipg);
1457 if (ret)
1458 return ret;
1459 ret = clk_enable(clk: sdmac->sdma->clk_ahb);
1460 if (ret)
1461 goto disable_clk_ipg;
1462
1463 ret = sdma_set_channel_priority(sdmac, priority: prio);
1464 if (ret)
1465 goto disable_clk_ahb;
1466
1467 return 0;
1468
1469disable_clk_ahb:
1470 clk_disable(clk: sdmac->sdma->clk_ahb);
1471disable_clk_ipg:
1472 clk_disable(clk: sdmac->sdma->clk_ipg);
1473 return ret;
1474}
1475
1476static void sdma_free_chan_resources(struct dma_chan *chan)
1477{
1478 struct sdma_channel *sdmac = to_sdma_chan(chan);
1479 struct sdma_engine *sdma = sdmac->sdma;
1480
1481 sdma_terminate_all(chan);
1482
1483 sdma_channel_synchronize(chan);
1484
1485 sdma_event_disable(sdmac, event: sdmac->event_id0);
1486 if (sdmac->event_id1)
1487 sdma_event_disable(sdmac, event: sdmac->event_id1);
1488
1489 sdmac->event_id0 = 0;
1490 sdmac->event_id1 = 0;
1491
1492 sdma_set_channel_priority(sdmac, priority: 0);
1493
1494 clk_disable(clk: sdma->clk_ipg);
1495 clk_disable(clk: sdma->clk_ahb);
1496}
1497
1498static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1499 enum dma_transfer_direction direction, u32 bds)
1500{
1501 struct sdma_desc *desc;
1502
1503 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
1504 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
1505 goto err_out;
1506 }
1507
1508 desc = kzalloc(size: (sizeof(*desc)), GFP_NOWAIT);
1509 if (!desc)
1510 goto err_out;
1511
1512 sdmac->status = DMA_IN_PROGRESS;
1513 sdmac->direction = direction;
1514 sdmac->flags = 0;
1515
1516 desc->chn_count = 0;
1517 desc->chn_real_count = 0;
1518 desc->buf_tail = 0;
1519 desc->buf_ptail = 0;
1520 desc->sdmac = sdmac;
1521 desc->num_bd = bds;
1522
1523 if (bds && sdma_alloc_bd(desc))
1524 goto err_desc_out;
1525
1526 /* No slave_config called in MEMCPY case, so do here */
1527 if (direction == DMA_MEM_TO_MEM)
1528 sdma_config_ownership(sdmac, event_override: false, mcu_override: true, dsp_override: false);
1529
1530 if (sdma_load_context(sdmac))
1531 goto err_bd_out;
1532
1533 return desc;
1534
1535err_bd_out:
1536 sdma_free_bd(desc);
1537err_desc_out:
1538 kfree(objp: desc);
1539err_out:
1540 return NULL;
1541}
1542
1543static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1544 struct dma_chan *chan, dma_addr_t dma_dst,
1545 dma_addr_t dma_src, size_t len, unsigned long flags)
1546{
1547 struct sdma_channel *sdmac = to_sdma_chan(chan);
1548 struct sdma_engine *sdma = sdmac->sdma;
1549 int channel = sdmac->channel;
1550 size_t count;
1551 int i = 0, param;
1552 struct sdma_buffer_descriptor *bd;
1553 struct sdma_desc *desc;
1554
1555 if (!chan || !len)
1556 return NULL;
1557
1558 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1559 &dma_src, &dma_dst, len, channel);
1560
1561 desc = sdma_transfer_init(sdmac, direction: DMA_MEM_TO_MEM,
1562 bds: len / SDMA_BD_MAX_CNT + 1);
1563 if (!desc)
1564 return NULL;
1565
1566 do {
1567 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1568 bd = &desc->bd[i];
1569 bd->buffer_addr = dma_src;
1570 bd->ext_buffer_addr = dma_dst;
1571 bd->mode.count = count;
1572 desc->chn_count += count;
1573 bd->mode.command = 0;
1574
1575 dma_src += count;
1576 dma_dst += count;
1577 len -= count;
1578 i++;
1579
1580 param = BD_DONE | BD_EXTD | BD_CONT;
1581 /* last bd */
1582 if (!len) {
1583 param |= BD_INTR;
1584 param |= BD_LAST;
1585 param &= ~BD_CONT;
1586 }
1587
1588 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1589 i, count, bd->buffer_addr,
1590 param & BD_WRAP ? "wrap" : "",
1591 param & BD_INTR ? " intr" : "");
1592
1593 bd->mode.status = param;
1594 } while (len);
1595
1596 return vchan_tx_prep(vc: &sdmac->vc, vd: &desc->vd, tx_flags: flags);
1597}
1598
1599static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1600 struct dma_chan *chan, struct scatterlist *sgl,
1601 unsigned int sg_len, enum dma_transfer_direction direction,
1602 unsigned long flags, void *context)
1603{
1604 struct sdma_channel *sdmac = to_sdma_chan(chan);
1605 struct sdma_engine *sdma = sdmac->sdma;
1606 int i, count;
1607 int channel = sdmac->channel;
1608 struct scatterlist *sg;
1609 struct sdma_desc *desc;
1610
1611 sdma_config_write(chan, dmaengine_cfg: &sdmac->slave_config, direction);
1612
1613 desc = sdma_transfer_init(sdmac, direction, bds: sg_len);
1614 if (!desc)
1615 goto err_out;
1616
1617 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1618 sg_len, channel);
1619
1620 for_each_sg(sgl, sg, sg_len, i) {
1621 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1622 int param;
1623
1624 bd->buffer_addr = sg->dma_address;
1625
1626 count = sg_dma_len(sg);
1627
1628 if (count > SDMA_BD_MAX_CNT) {
1629 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1630 channel, count, SDMA_BD_MAX_CNT);
1631 goto err_bd_out;
1632 }
1633
1634 bd->mode.count = count;
1635 desc->chn_count += count;
1636
1637 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1638 goto err_bd_out;
1639
1640 switch (sdmac->word_size) {
1641 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1642 bd->mode.command = 0;
1643 if (count & 3 || sg->dma_address & 3)
1644 goto err_bd_out;
1645 break;
1646 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1647 bd->mode.command = 2;
1648 if (count & 1 || sg->dma_address & 1)
1649 goto err_bd_out;
1650 break;
1651 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1652 bd->mode.command = 1;
1653 break;
1654 default:
1655 goto err_bd_out;
1656 }
1657
1658 param = BD_DONE | BD_EXTD | BD_CONT;
1659
1660 if (i + 1 == sg_len) {
1661 param |= BD_INTR;
1662 param |= BD_LAST;
1663 param &= ~BD_CONT;
1664 }
1665
1666 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1667 i, count, (u64)sg->dma_address,
1668 param & BD_WRAP ? "wrap" : "",
1669 param & BD_INTR ? " intr" : "");
1670
1671 bd->mode.status = param;
1672 }
1673
1674 return vchan_tx_prep(vc: &sdmac->vc, vd: &desc->vd, tx_flags: flags);
1675err_bd_out:
1676 sdma_free_bd(desc);
1677 kfree(objp: desc);
1678err_out:
1679 sdmac->status = DMA_ERROR;
1680 return NULL;
1681}
1682
1683static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1684 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1685 size_t period_len, enum dma_transfer_direction direction,
1686 unsigned long flags)
1687{
1688 struct sdma_channel *sdmac = to_sdma_chan(chan);
1689 struct sdma_engine *sdma = sdmac->sdma;
1690 int num_periods = 0;
1691 int channel = sdmac->channel;
1692 int i = 0, buf = 0;
1693 struct sdma_desc *desc;
1694
1695 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1696
1697 if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
1698 num_periods = buf_len / period_len;
1699
1700 sdma_config_write(chan, dmaengine_cfg: &sdmac->slave_config, direction);
1701
1702 desc = sdma_transfer_init(sdmac, direction, bds: num_periods);
1703 if (!desc)
1704 goto err_out;
1705
1706 desc->period_len = period_len;
1707
1708 sdmac->flags |= IMX_DMA_SG_LOOP;
1709
1710 if (period_len > SDMA_BD_MAX_CNT) {
1711 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1712 channel, period_len, SDMA_BD_MAX_CNT);
1713 goto err_bd_out;
1714 }
1715
1716 if (sdmac->peripheral_type == IMX_DMATYPE_HDMI)
1717 return vchan_tx_prep(vc: &sdmac->vc, vd: &desc->vd, tx_flags: flags);
1718
1719 while (buf < buf_len) {
1720 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1721 int param;
1722
1723 bd->buffer_addr = dma_addr;
1724
1725 bd->mode.count = period_len;
1726
1727 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1728 goto err_bd_out;
1729 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1730 bd->mode.command = 0;
1731 else
1732 bd->mode.command = sdmac->word_size;
1733
1734 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1735 if (i + 1 == num_periods)
1736 param |= BD_WRAP;
1737
1738 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1739 i, period_len, (u64)dma_addr,
1740 param & BD_WRAP ? "wrap" : "",
1741 param & BD_INTR ? " intr" : "");
1742
1743 bd->mode.status = param;
1744
1745 dma_addr += period_len;
1746 buf += period_len;
1747
1748 i++;
1749 }
1750
1751 return vchan_tx_prep(vc: &sdmac->vc, vd: &desc->vd, tx_flags: flags);
1752err_bd_out:
1753 sdma_free_bd(desc);
1754 kfree(objp: desc);
1755err_out:
1756 sdmac->status = DMA_ERROR;
1757 return NULL;
1758}
1759
1760static int sdma_config_write(struct dma_chan *chan,
1761 struct dma_slave_config *dmaengine_cfg,
1762 enum dma_transfer_direction direction)
1763{
1764 struct sdma_channel *sdmac = to_sdma_chan(chan);
1765
1766 if (direction == DMA_DEV_TO_MEM) {
1767 sdmac->per_address = dmaengine_cfg->src_addr;
1768 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1769 dmaengine_cfg->src_addr_width;
1770 sdmac->word_size = dmaengine_cfg->src_addr_width;
1771 } else if (direction == DMA_DEV_TO_DEV) {
1772 sdmac->per_address2 = dmaengine_cfg->src_addr;
1773 sdmac->per_address = dmaengine_cfg->dst_addr;
1774 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1775 SDMA_WATERMARK_LEVEL_LWML;
1776 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1777 SDMA_WATERMARK_LEVEL_HWML;
1778 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1779 } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1780 sdmac->per_address = dmaengine_cfg->dst_addr;
1781 sdmac->per_address2 = dmaengine_cfg->src_addr;
1782 sdmac->watermark_level = 0;
1783 } else {
1784 sdmac->per_address = dmaengine_cfg->dst_addr;
1785 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1786 dmaengine_cfg->dst_addr_width;
1787 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1788 }
1789 sdmac->direction = direction;
1790 return sdma_config_channel(chan);
1791}
1792
1793static int sdma_config(struct dma_chan *chan,
1794 struct dma_slave_config *dmaengine_cfg)
1795{
1796 struct sdma_channel *sdmac = to_sdma_chan(chan);
1797 struct sdma_engine *sdma = sdmac->sdma;
1798
1799 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1800
1801 if (dmaengine_cfg->peripheral_config) {
1802 struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
1803 if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
1804 dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
1805 dmaengine_cfg->peripheral_size,
1806 sizeof(struct sdma_peripheral_config));
1807 return -EINVAL;
1808 }
1809 sdmac->n_fifos_src = sdmacfg->n_fifos_src;
1810 sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
1811 sdmac->stride_fifos_src = sdmacfg->stride_fifos_src;
1812 sdmac->stride_fifos_dst = sdmacfg->stride_fifos_dst;
1813 sdmac->words_per_fifo = sdmacfg->words_per_fifo;
1814 sdmac->sw_done = sdmacfg->sw_done;
1815 }
1816
1817 /* Set ENBLn earlier to make sure dma request triggered after that */
1818 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1819 return -EINVAL;
1820 sdma_event_enable(sdmac, event: sdmac->event_id0);
1821
1822 if (sdmac->event_id1) {
1823 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1824 return -EINVAL;
1825 sdma_event_enable(sdmac, event: sdmac->event_id1);
1826 }
1827
1828 return 0;
1829}
1830
1831static enum dma_status sdma_tx_status(struct dma_chan *chan,
1832 dma_cookie_t cookie,
1833 struct dma_tx_state *txstate)
1834{
1835 struct sdma_channel *sdmac = to_sdma_chan(chan);
1836 struct sdma_desc *desc = NULL;
1837 u32 residue;
1838 struct virt_dma_desc *vd;
1839 enum dma_status ret;
1840 unsigned long flags;
1841
1842 ret = dma_cookie_status(chan, cookie, state: txstate);
1843 if (ret == DMA_COMPLETE || !txstate)
1844 return ret;
1845
1846 spin_lock_irqsave(&sdmac->vc.lock, flags);
1847
1848 vd = vchan_find_desc(&sdmac->vc, cookie);
1849 if (vd)
1850 desc = to_sdma_desc(t: &vd->tx);
1851 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
1852 desc = sdmac->desc;
1853
1854 if (desc) {
1855 if (sdmac->flags & IMX_DMA_SG_LOOP)
1856 residue = (desc->num_bd - desc->buf_ptail) *
1857 desc->period_len - desc->chn_real_count;
1858 else
1859 residue = desc->chn_count - desc->chn_real_count;
1860 } else {
1861 residue = 0;
1862 }
1863
1864 spin_unlock_irqrestore(lock: &sdmac->vc.lock, flags);
1865
1866 dma_set_tx_state(st: txstate, last: chan->completed_cookie, used: chan->cookie,
1867 residue);
1868
1869 return sdmac->status;
1870}
1871
1872static void sdma_issue_pending(struct dma_chan *chan)
1873{
1874 struct sdma_channel *sdmac = to_sdma_chan(chan);
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&sdmac->vc.lock, flags);
1878 if (vchan_issue_pending(vc: &sdmac->vc) && !sdmac->desc)
1879 sdma_start_desc(sdmac);
1880 spin_unlock_irqrestore(lock: &sdmac->vc.lock, flags);
1881}
1882
1883#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1884#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1885#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
1886#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
1887
1888static void sdma_add_scripts(struct sdma_engine *sdma,
1889 const struct sdma_script_start_addrs *addr)
1890{
1891 s32 *addr_arr = (u32 *)addr;
1892 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1893 int i;
1894
1895 /* use the default firmware in ROM if missing external firmware */
1896 if (!sdma->script_number)
1897 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1898
1899 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1900 / sizeof(s32)) {
1901 dev_err(sdma->dev,
1902 "SDMA script number %d not match with firmware.\n",
1903 sdma->script_number);
1904 return;
1905 }
1906
1907 for (i = 0; i < sdma->script_number; i++)
1908 if (addr_arr[i] > 0)
1909 saddr_arr[i] = addr_arr[i];
1910
1911 /*
1912 * For compatibility with NXP internal legacy kernel before 4.19 which
1913 * is based on uart ram script and mainline kernel based on uart rom
1914 * script, both uart ram/rom scripts are present in newer sdma
1915 * firmware. Use the rom versions if they are present (V3 or newer).
1916 */
1917 if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) {
1918 if (addr->uart_2_mcu_rom_addr)
1919 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr;
1920 if (addr->uartsh_2_mcu_rom_addr)
1921 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr;
1922 }
1923}
1924
1925static void sdma_load_firmware(const struct firmware *fw, void *context)
1926{
1927 struct sdma_engine *sdma = context;
1928 const struct sdma_firmware_header *header;
1929 const struct sdma_script_start_addrs *addr;
1930 unsigned short *ram_code;
1931
1932 if (!fw) {
1933 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1934 /* In this case we just use the ROM firmware. */
1935 return;
1936 }
1937
1938 if (fw->size < sizeof(*header))
1939 goto err_firmware;
1940
1941 header = (struct sdma_firmware_header *)fw->data;
1942
1943 if (header->magic != SDMA_FIRMWARE_MAGIC)
1944 goto err_firmware;
1945 if (header->ram_code_start + header->ram_code_size > fw->size)
1946 goto err_firmware;
1947 switch (header->version_major) {
1948 case 1:
1949 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1950 break;
1951 case 2:
1952 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1953 break;
1954 case 3:
1955 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1956 break;
1957 case 4:
1958 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1959 break;
1960 default:
1961 dev_err(sdma->dev, "unknown firmware version\n");
1962 goto err_firmware;
1963 }
1964
1965 addr = (void *)header + header->script_addrs_start;
1966 ram_code = (void *)header + header->ram_code_start;
1967
1968 clk_enable(clk: sdma->clk_ipg);
1969 clk_enable(clk: sdma->clk_ahb);
1970 /* download the RAM image for SDMA */
1971 sdma_load_script(sdma, buf: ram_code,
1972 size: header->ram_code_size,
1973 address: addr->ram_code_start_addr);
1974 clk_disable(clk: sdma->clk_ipg);
1975 clk_disable(clk: sdma->clk_ahb);
1976
1977 sdma_add_scripts(sdma, addr);
1978
1979 sdma->fw_loaded = true;
1980
1981 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1982 header->version_major,
1983 header->version_minor);
1984
1985err_firmware:
1986 release_firmware(fw);
1987}
1988
1989#define EVENT_REMAP_CELLS 3
1990
1991static int sdma_event_remap(struct sdma_engine *sdma)
1992{
1993 struct device_node *np = sdma->dev->of_node;
1994 struct device_node *gpr_np = of_parse_phandle(np, phandle_name: "gpr", index: 0);
1995 struct property *event_remap;
1996 struct regmap *gpr;
1997 char propname[] = "fsl,sdma-event-remap";
1998 u32 reg, val, shift, num_map, i;
1999 int ret = 0;
2000
2001 if (IS_ERR(ptr: np) || !gpr_np)
2002 goto out;
2003
2004 event_remap = of_find_property(np, name: propname, NULL);
2005 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
2006 if (!num_map) {
2007 dev_dbg(sdma->dev, "no event needs to be remapped\n");
2008 goto out;
2009 } else if (num_map % EVENT_REMAP_CELLS) {
2010 dev_err(sdma->dev, "the property %s must modulo %d\n",
2011 propname, EVENT_REMAP_CELLS);
2012 ret = -EINVAL;
2013 goto out;
2014 }
2015
2016 gpr = syscon_node_to_regmap(np: gpr_np);
2017 if (IS_ERR(ptr: gpr)) {
2018 dev_err(sdma->dev, "failed to get gpr regmap\n");
2019 ret = PTR_ERR(ptr: gpr);
2020 goto out;
2021 }
2022
2023 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
2024 ret = of_property_read_u32_index(np, propname, index: i, out_value: &reg);
2025 if (ret) {
2026 dev_err(sdma->dev, "failed to read property %s index %d\n",
2027 propname, i);
2028 goto out;
2029 }
2030
2031 ret = of_property_read_u32_index(np, propname, index: i + 1, out_value: &shift);
2032 if (ret) {
2033 dev_err(sdma->dev, "failed to read property %s index %d\n",
2034 propname, i + 1);
2035 goto out;
2036 }
2037
2038 ret = of_property_read_u32_index(np, propname, index: i + 2, out_value: &val);
2039 if (ret) {
2040 dev_err(sdma->dev, "failed to read property %s index %d\n",
2041 propname, i + 2);
2042 goto out;
2043 }
2044
2045 regmap_update_bits(map: gpr, reg, BIT(shift), val: val << shift);
2046 }
2047
2048out:
2049 if (gpr_np)
2050 of_node_put(node: gpr_np);
2051
2052 return ret;
2053}
2054
2055static int sdma_get_firmware(struct sdma_engine *sdma,
2056 const char *fw_name)
2057{
2058 int ret;
2059
2060 ret = request_firmware_nowait(THIS_MODULE,
2061 FW_ACTION_UEVENT, name: fw_name, device: sdma->dev,
2062 GFP_KERNEL, context: sdma, cont: sdma_load_firmware);
2063
2064 return ret;
2065}
2066
2067static int sdma_init(struct sdma_engine *sdma)
2068{
2069 int i, ret;
2070 dma_addr_t ccb_phys;
2071
2072 ret = clk_enable(clk: sdma->clk_ipg);
2073 if (ret)
2074 return ret;
2075 ret = clk_enable(clk: sdma->clk_ahb);
2076 if (ret)
2077 goto disable_clk_ipg;
2078
2079 if (sdma->drvdata->check_ratio &&
2080 (clk_get_rate(clk: sdma->clk_ahb) == clk_get_rate(clk: sdma->clk_ipg)))
2081 sdma->clk_ratio = 1;
2082
2083 /* Be sure SDMA has not started yet */
2084 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
2085
2086 sdma->channel_control = dma_alloc_coherent(dev: sdma->dev,
2087 MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control) +
2088 sizeof(struct sdma_context_data),
2089 dma_handle: &ccb_phys, GFP_KERNEL);
2090
2091 if (!sdma->channel_control) {
2092 ret = -ENOMEM;
2093 goto err_dma_alloc;
2094 }
2095
2096 sdma->context = (void *)sdma->channel_control +
2097 MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control);
2098 sdma->context_phys = ccb_phys +
2099 MAX_DMA_CHANNELS * sizeof(struct sdma_channel_control);
2100
2101 /* disable all channels */
2102 for (i = 0; i < sdma->drvdata->num_events; i++)
2103 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
2104
2105 /* All channels have priority 0 */
2106 for (i = 0; i < MAX_DMA_CHANNELS; i++)
2107 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
2108
2109 ret = sdma_request_channel0(sdma);
2110 if (ret)
2111 goto err_dma_alloc;
2112
2113 sdma_config_ownership(sdmac: &sdma->channel[0], event_override: false, mcu_override: true, dsp_override: false);
2114
2115 /* Set Command Channel (Channel Zero) */
2116 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
2117
2118 /* Set bits of CONFIG register but with static context switching */
2119 if (sdma->clk_ratio)
2120 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
2121 else
2122 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
2123
2124 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
2125
2126 /* Initializes channel's priorities */
2127 sdma_set_channel_priority(sdmac: &sdma->channel[0], priority: 7);
2128
2129 clk_disable(clk: sdma->clk_ipg);
2130 clk_disable(clk: sdma->clk_ahb);
2131
2132 return 0;
2133
2134err_dma_alloc:
2135 clk_disable(clk: sdma->clk_ahb);
2136disable_clk_ipg:
2137 clk_disable(clk: sdma->clk_ipg);
2138 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
2139 return ret;
2140}
2141
2142static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
2143{
2144 struct sdma_channel *sdmac = to_sdma_chan(chan);
2145 struct imx_dma_data *data = fn_param;
2146
2147 if (!imx_dma_is_general_purpose(chan))
2148 return false;
2149
2150 sdmac->data = *data;
2151 chan->private = &sdmac->data;
2152
2153 return true;
2154}
2155
2156static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
2157 struct of_dma *ofdma)
2158{
2159 struct sdma_engine *sdma = ofdma->of_dma_data;
2160 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
2161 struct imx_dma_data data;
2162
2163 if (dma_spec->args_count != 3)
2164 return NULL;
2165
2166 data.dma_request = dma_spec->args[0];
2167 data.peripheral_type = dma_spec->args[1];
2168 data.priority = dma_spec->args[2];
2169 /*
2170 * init dma_request2 to zero, which is not used by the dts.
2171 * For P2P, dma_request2 is init from dma_request_channel(),
2172 * chan->private will point to the imx_dma_data, and in
2173 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
2174 * be set to sdmac->event_id1.
2175 */
2176 data.dma_request2 = 0;
2177
2178 return __dma_request_channel(mask: &mask, fn: sdma_filter_fn, fn_param: &data,
2179 np: ofdma->of_node);
2180}
2181
2182static int sdma_probe(struct platform_device *pdev)
2183{
2184 struct device_node *np = pdev->dev.of_node;
2185 struct device_node *spba_bus;
2186 const char *fw_name;
2187 int ret;
2188 int irq;
2189 struct resource spba_res;
2190 int i;
2191 struct sdma_engine *sdma;
2192 s32 *saddr_arr;
2193
2194 ret = dma_coerce_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(32));
2195 if (ret)
2196 return ret;
2197
2198 sdma = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sdma), GFP_KERNEL);
2199 if (!sdma)
2200 return -ENOMEM;
2201
2202 spin_lock_init(&sdma->channel_0_lock);
2203
2204 sdma->dev = &pdev->dev;
2205 sdma->drvdata = of_device_get_match_data(dev: sdma->dev);
2206
2207 irq = platform_get_irq(pdev, 0);
2208 if (irq < 0)
2209 return irq;
2210
2211 sdma->regs = devm_platform_ioremap_resource(pdev, index: 0);
2212 if (IS_ERR(ptr: sdma->regs))
2213 return PTR_ERR(ptr: sdma->regs);
2214
2215 sdma->clk_ipg = devm_clk_get(dev: &pdev->dev, id: "ipg");
2216 if (IS_ERR(ptr: sdma->clk_ipg))
2217 return PTR_ERR(ptr: sdma->clk_ipg);
2218
2219 sdma->clk_ahb = devm_clk_get(dev: &pdev->dev, id: "ahb");
2220 if (IS_ERR(ptr: sdma->clk_ahb))
2221 return PTR_ERR(ptr: sdma->clk_ahb);
2222
2223 ret = clk_prepare(clk: sdma->clk_ipg);
2224 if (ret)
2225 return ret;
2226
2227 ret = clk_prepare(clk: sdma->clk_ahb);
2228 if (ret)
2229 goto err_clk;
2230
2231 ret = devm_request_irq(dev: &pdev->dev, irq, handler: sdma_int_handler, irqflags: 0,
2232 devname: dev_name(dev: &pdev->dev), dev_id: sdma);
2233 if (ret)
2234 goto err_irq;
2235
2236 sdma->irq = irq;
2237
2238 sdma->script_addrs = kzalloc(size: sizeof(*sdma->script_addrs), GFP_KERNEL);
2239 if (!sdma->script_addrs) {
2240 ret = -ENOMEM;
2241 goto err_irq;
2242 }
2243
2244 /* initially no scripts available */
2245 saddr_arr = (s32 *)sdma->script_addrs;
2246 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2247 saddr_arr[i] = -EINVAL;
2248
2249 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2250 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2251 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2252 dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask);
2253
2254 INIT_LIST_HEAD(list: &sdma->dma_device.channels);
2255 /* Initialize channel parameters */
2256 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2257 struct sdma_channel *sdmac = &sdma->channel[i];
2258
2259 sdmac->sdma = sdma;
2260
2261 sdmac->channel = i;
2262 sdmac->vc.desc_free = sdma_desc_free;
2263 INIT_LIST_HEAD(list: &sdmac->terminated);
2264 INIT_WORK(&sdmac->terminate_worker,
2265 sdma_channel_terminate_work);
2266 /*
2267 * Add the channel to the DMAC list. Do not add channel 0 though
2268 * because we need it internally in the SDMA driver. This also means
2269 * that channel 0 in dmaengine counting matches sdma channel 1.
2270 */
2271 if (i)
2272 vchan_init(vc: &sdmac->vc, dmadev: &sdma->dma_device);
2273 }
2274
2275 ret = sdma_init(sdma);
2276 if (ret)
2277 goto err_init;
2278
2279 ret = sdma_event_remap(sdma);
2280 if (ret)
2281 goto err_init;
2282
2283 if (sdma->drvdata->script_addrs)
2284 sdma_add_scripts(sdma, addr: sdma->drvdata->script_addrs);
2285
2286 sdma->dma_device.dev = &pdev->dev;
2287
2288 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2289 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2290 sdma->dma_device.device_tx_status = sdma_tx_status;
2291 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2292 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2293 sdma->dma_device.device_config = sdma_config;
2294 sdma->dma_device.device_terminate_all = sdma_terminate_all;
2295 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2296 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2297 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2298 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2299 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2300 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2301 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2302 sdma->dma_device.copy_align = 2;
2303 dma_set_max_seg_size(dev: sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2304
2305 platform_set_drvdata(pdev, data: sdma);
2306
2307 ret = dma_async_device_register(device: &sdma->dma_device);
2308 if (ret) {
2309 dev_err(&pdev->dev, "unable to register\n");
2310 goto err_init;
2311 }
2312
2313 if (np) {
2314 ret = of_dma_controller_register(np, of_dma_xlate: sdma_xlate, data: sdma);
2315 if (ret) {
2316 dev_err(&pdev->dev, "failed to register controller\n");
2317 goto err_register;
2318 }
2319
2320 spba_bus = of_find_compatible_node(NULL, NULL, compat: "fsl,spba-bus");
2321 ret = of_address_to_resource(dev: spba_bus, index: 0, r: &spba_res);
2322 if (!ret) {
2323 sdma->spba_start_addr = spba_res.start;
2324 sdma->spba_end_addr = spba_res.end;
2325 }
2326 of_node_put(node: spba_bus);
2327 }
2328
2329 /*
2330 * Because that device tree does not encode ROM script address,
2331 * the RAM script in firmware is mandatory for device tree
2332 * probe, otherwise it fails.
2333 */
2334 ret = of_property_read_string(np, propname: "fsl,sdma-ram-script-name",
2335 out_string: &fw_name);
2336 if (ret) {
2337 dev_warn(&pdev->dev, "failed to get firmware name\n");
2338 } else {
2339 ret = sdma_get_firmware(sdma, fw_name);
2340 if (ret)
2341 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2342 }
2343
2344 return 0;
2345
2346err_register:
2347 dma_async_device_unregister(device: &sdma->dma_device);
2348err_init:
2349 kfree(objp: sdma->script_addrs);
2350err_irq:
2351 clk_unprepare(clk: sdma->clk_ahb);
2352err_clk:
2353 clk_unprepare(clk: sdma->clk_ipg);
2354 return ret;
2355}
2356
2357static void sdma_remove(struct platform_device *pdev)
2358{
2359 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2360 int i;
2361
2362 devm_free_irq(dev: &pdev->dev, irq: sdma->irq, dev_id: sdma);
2363 dma_async_device_unregister(device: &sdma->dma_device);
2364 kfree(objp: sdma->script_addrs);
2365 clk_unprepare(clk: sdma->clk_ahb);
2366 clk_unprepare(clk: sdma->clk_ipg);
2367 /* Kill the tasklet */
2368 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2369 struct sdma_channel *sdmac = &sdma->channel[i];
2370
2371 tasklet_kill(t: &sdmac->vc.task);
2372 sdma_free_chan_resources(chan: &sdmac->vc.chan);
2373 }
2374
2375 platform_set_drvdata(pdev, NULL);
2376}
2377
2378static struct platform_driver sdma_driver = {
2379 .driver = {
2380 .name = "imx-sdma",
2381 .of_match_table = sdma_dt_ids,
2382 },
2383 .remove_new = sdma_remove,
2384 .probe = sdma_probe,
2385};
2386
2387module_platform_driver(sdma_driver);
2388
2389MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2390MODULE_DESCRIPTION("i.MX SDMA driver");
2391#if IS_ENABLED(CONFIG_SOC_IMX6Q)
2392MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2393#endif
2394#if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
2395MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2396#endif
2397MODULE_LICENSE("GPL");
2398

source code of linux/drivers/dma/imx-sdma.c