1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2019 American Megatrends International LLC.
4 *
5 * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
6 */
7
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/hashtable.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/seq_file.h>
18#include <linux/spinlock.h>
19#include <linux/string.h>
20
21#define ASPEED_SGPIO_CTRL 0x54
22
23#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
24#define ASPEED_SGPIO_ENABLE BIT(0)
25#define ASPEED_SGPIO_PINS_SHIFT 6
26
27struct aspeed_sgpio_pdata {
28 const u32 pin_mask;
29};
30
31struct aspeed_sgpio {
32 struct gpio_chip chip;
33 struct device *dev;
34 struct clk *pclk;
35 raw_spinlock_t lock;
36 void __iomem *base;
37 int irq;
38};
39
40struct aspeed_sgpio_bank {
41 u16 val_regs;
42 u16 rdata_reg;
43 u16 irq_regs;
44 u16 tolerance_regs;
45 const char names[4][3];
46};
47
48/*
49 * Note: The "value" register returns the input value when the GPIO is
50 * configured as an input.
51 *
52 * The "rdata" register returns the output value when the GPIO is
53 * configured as an output.
54 */
55static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
56 {
57 .val_regs = 0x0000,
58 .rdata_reg = 0x0070,
59 .irq_regs = 0x0004,
60 .tolerance_regs = 0x0018,
61 .names = { "A", "B", "C", "D" },
62 },
63 {
64 .val_regs = 0x001C,
65 .rdata_reg = 0x0074,
66 .irq_regs = 0x0020,
67 .tolerance_regs = 0x0034,
68 .names = { "E", "F", "G", "H" },
69 },
70 {
71 .val_regs = 0x0038,
72 .rdata_reg = 0x0078,
73 .irq_regs = 0x003C,
74 .tolerance_regs = 0x0050,
75 .names = { "I", "J", "K", "L" },
76 },
77 {
78 .val_regs = 0x0090,
79 .rdata_reg = 0x007C,
80 .irq_regs = 0x0094,
81 .tolerance_regs = 0x00A8,
82 .names = { "M", "N", "O", "P" },
83 },
84};
85
86enum aspeed_sgpio_reg {
87 reg_val,
88 reg_rdata,
89 reg_irq_enable,
90 reg_irq_type0,
91 reg_irq_type1,
92 reg_irq_type2,
93 reg_irq_status,
94 reg_tolerance,
95};
96
97#define GPIO_VAL_VALUE 0x00
98#define GPIO_IRQ_ENABLE 0x00
99#define GPIO_IRQ_TYPE0 0x04
100#define GPIO_IRQ_TYPE1 0x08
101#define GPIO_IRQ_TYPE2 0x0C
102#define GPIO_IRQ_STATUS 0x10
103
104static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
105 const struct aspeed_sgpio_bank *bank,
106 const enum aspeed_sgpio_reg reg)
107{
108 switch (reg) {
109 case reg_val:
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
111 case reg_rdata:
112 return gpio->base + bank->rdata_reg;
113 case reg_irq_enable:
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
115 case reg_irq_type0:
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
117 case reg_irq_type1:
118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
119 case reg_irq_type2:
120 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
121 case reg_irq_status:
122 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
123 case reg_tolerance:
124 return gpio->base + bank->tolerance_regs;
125 default:
126 /* acturally if code runs to here, it's an error case */
127 BUG();
128 }
129}
130
131#define GPIO_BANK(x) ((x) >> 6)
132#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
133#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
134
135static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
136{
137 unsigned int bank;
138
139 bank = GPIO_BANK(offset);
140
141 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
142 return &aspeed_sgpio_banks[bank];
143}
144
145static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
146 unsigned long *valid_mask, unsigned int ngpios)
147{
148 bitmap_set(map: valid_mask, start: 0, nbits: ngpios);
149 return 0;
150}
151
152static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
153 unsigned long *valid_mask, unsigned int ngpios)
154{
155 unsigned int i;
156
157 /* input GPIOs are even bits */
158 for (i = 0; i < ngpios; i++) {
159 if (i % 2)
160 clear_bit(nr: i, addr: valid_mask);
161 }
162}
163
164static bool aspeed_sgpio_is_input(unsigned int offset)
165{
166 return !(offset % 2);
167}
168
169static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
170{
171 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
172 const struct aspeed_sgpio_bank *bank = to_bank(offset);
173 unsigned long flags;
174 enum aspeed_sgpio_reg reg;
175 int rc = 0;
176
177 raw_spin_lock_irqsave(&gpio->lock, flags);
178
179 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
180 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
181
182 raw_spin_unlock_irqrestore(&gpio->lock, flags);
183
184 return rc;
185}
186
187static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
188{
189 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
190 const struct aspeed_sgpio_bank *bank = to_bank(offset);
191 void __iomem *addr_r, *addr_w;
192 u32 reg = 0;
193
194 if (aspeed_sgpio_is_input(offset))
195 return -EINVAL;
196
197 /* Since this is an output, read the cached value from rdata, then
198 * update val. */
199 addr_r = bank_reg(gpio, bank, reg: reg_rdata);
200 addr_w = bank_reg(gpio, bank, reg: reg_val);
201
202 reg = ioread32(addr_r);
203
204 if (val)
205 reg |= GPIO_BIT(offset);
206 else
207 reg &= ~GPIO_BIT(offset);
208
209 iowrite32(reg, addr_w);
210
211 return 0;
212}
213
214static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
215{
216 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
217 unsigned long flags;
218
219 raw_spin_lock_irqsave(&gpio->lock, flags);
220
221 sgpio_set_value(gc, offset, val);
222
223 raw_spin_unlock_irqrestore(&gpio->lock, flags);
224}
225
226static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
227{
228 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
229}
230
231static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
232{
233 struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
234 unsigned long flags;
235 int rc;
236
237 /* No special action is required for setting the direction; we'll
238 * error-out in sgpio_set_value if this isn't an output GPIO */
239
240 raw_spin_lock_irqsave(&gpio->lock, flags);
241 rc = sgpio_set_value(gc, offset, val);
242 raw_spin_unlock_irqrestore(&gpio->lock, flags);
243
244 return rc;
245}
246
247static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
248{
249 return !!aspeed_sgpio_is_input(offset);
250}
251
252static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
253 struct aspeed_sgpio **gpio,
254 const struct aspeed_sgpio_bank **bank,
255 u32 *bit, int *offset)
256{
257 struct aspeed_sgpio *internal;
258
259 *offset = irqd_to_hwirq(d);
260 internal = irq_data_get_irq_chip_data(d);
261 WARN_ON(!internal);
262
263 *gpio = internal;
264 *bank = to_bank(offset: *offset);
265 *bit = GPIO_BIT(*offset);
266}
267
268static void aspeed_sgpio_irq_ack(struct irq_data *d)
269{
270 const struct aspeed_sgpio_bank *bank;
271 struct aspeed_sgpio *gpio;
272 unsigned long flags;
273 void __iomem *status_addr;
274 int offset;
275 u32 bit;
276
277 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
278
279 status_addr = bank_reg(gpio, bank, reg: reg_irq_status);
280
281 raw_spin_lock_irqsave(&gpio->lock, flags);
282
283 iowrite32(bit, status_addr);
284
285 raw_spin_unlock_irqrestore(&gpio->lock, flags);
286}
287
288static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
289{
290 const struct aspeed_sgpio_bank *bank;
291 struct aspeed_sgpio *gpio;
292 unsigned long flags;
293 u32 reg, bit;
294 void __iomem *addr;
295 int offset;
296
297 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
298 addr = bank_reg(gpio, bank, reg: reg_irq_enable);
299
300 /* Unmasking the IRQ */
301 if (set)
302 gpiochip_enable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d));
303
304 raw_spin_lock_irqsave(&gpio->lock, flags);
305
306 reg = ioread32(addr);
307 if (set)
308 reg |= bit;
309 else
310 reg &= ~bit;
311
312 iowrite32(reg, addr);
313
314 raw_spin_unlock_irqrestore(&gpio->lock, flags);
315
316 /* Masking the IRQ */
317 if (!set)
318 gpiochip_disable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d));
319
320
321}
322
323static void aspeed_sgpio_irq_mask(struct irq_data *d)
324{
325 aspeed_sgpio_irq_set_mask(d, set: false);
326}
327
328static void aspeed_sgpio_irq_unmask(struct irq_data *d)
329{
330 aspeed_sgpio_irq_set_mask(d, set: true);
331}
332
333static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
334{
335 u32 type0 = 0;
336 u32 type1 = 0;
337 u32 type2 = 0;
338 u32 bit, reg;
339 const struct aspeed_sgpio_bank *bank;
340 irq_flow_handler_t handler;
341 struct aspeed_sgpio *gpio;
342 unsigned long flags;
343 void __iomem *addr;
344 int offset;
345
346 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
347
348 switch (type & IRQ_TYPE_SENSE_MASK) {
349 case IRQ_TYPE_EDGE_BOTH:
350 type2 |= bit;
351 fallthrough;
352 case IRQ_TYPE_EDGE_RISING:
353 type0 |= bit;
354 fallthrough;
355 case IRQ_TYPE_EDGE_FALLING:
356 handler = handle_edge_irq;
357 break;
358 case IRQ_TYPE_LEVEL_HIGH:
359 type0 |= bit;
360 fallthrough;
361 case IRQ_TYPE_LEVEL_LOW:
362 type1 |= bit;
363 handler = handle_level_irq;
364 break;
365 default:
366 return -EINVAL;
367 }
368
369 raw_spin_lock_irqsave(&gpio->lock, flags);
370
371 addr = bank_reg(gpio, bank, reg: reg_irq_type0);
372 reg = ioread32(addr);
373 reg = (reg & ~bit) | type0;
374 iowrite32(reg, addr);
375
376 addr = bank_reg(gpio, bank, reg: reg_irq_type1);
377 reg = ioread32(addr);
378 reg = (reg & ~bit) | type1;
379 iowrite32(reg, addr);
380
381 addr = bank_reg(gpio, bank, reg: reg_irq_type2);
382 reg = ioread32(addr);
383 reg = (reg & ~bit) | type2;
384 iowrite32(reg, addr);
385
386 raw_spin_unlock_irqrestore(&gpio->lock, flags);
387
388 irq_set_handler_locked(data: d, handler);
389
390 return 0;
391}
392
393static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
394{
395 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
396 struct irq_chip *ic = irq_desc_get_chip(desc);
397 struct aspeed_sgpio *data = gpiochip_get_data(gc);
398 unsigned int i, p;
399 unsigned long reg;
400
401 chained_irq_enter(chip: ic, desc);
402
403 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
404 const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
405
406 reg = ioread32(bank_reg(gpio: data, bank, reg: reg_irq_status));
407
408 for_each_set_bit(p, &reg, 32)
409 generic_handle_domain_irq(domain: gc->irq.domain, hwirq: (i * 32 + p) * 2);
410 }
411
412 chained_irq_exit(chip: ic, desc);
413}
414
415static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
416{
417 const struct aspeed_sgpio_bank *bank;
418 struct aspeed_sgpio *gpio;
419 u32 bit;
420 int offset;
421
422 irqd_to_aspeed_sgpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset);
423 seq_printf(m: p, fmt: dev_name(dev: gpio->dev));
424}
425
426static const struct irq_chip aspeed_sgpio_irq_chip = {
427 .irq_ack = aspeed_sgpio_irq_ack,
428 .irq_mask = aspeed_sgpio_irq_mask,
429 .irq_unmask = aspeed_sgpio_irq_unmask,
430 .irq_set_type = aspeed_sgpio_set_type,
431 .irq_print_chip = aspeed_sgpio_irq_print_chip,
432 .flags = IRQCHIP_IMMUTABLE,
433 GPIOCHIP_IRQ_RESOURCE_HELPERS,
434};
435
436static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
437 struct platform_device *pdev)
438{
439 int rc, i;
440 const struct aspeed_sgpio_bank *bank;
441 struct gpio_irq_chip *irq;
442
443 rc = platform_get_irq(pdev, 0);
444 if (rc < 0)
445 return rc;
446
447 gpio->irq = rc;
448
449 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
450 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
451 bank = &aspeed_sgpio_banks[i];
452 /* disable irq enable bits */
453 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_enable));
454 /* clear status bits */
455 iowrite32(0xffffffff, bank_reg(gpio, bank, reg: reg_irq_status));
456 }
457
458 irq = &gpio->chip.irq;
459 gpio_irq_chip_set_chip(girq: irq, chip: &aspeed_sgpio_irq_chip);
460 irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
461 irq->handler = handle_bad_irq;
462 irq->default_type = IRQ_TYPE_NONE;
463 irq->parent_handler = aspeed_sgpio_irq_handler;
464 irq->parent_handler_data = gpio;
465 irq->parents = &gpio->irq;
466 irq->num_parents = 1;
467
468 /* Apply default IRQ settings */
469 for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
470 bank = &aspeed_sgpio_banks[i];
471 /* set falling or level-low irq */
472 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type0));
473 /* trigger type is edge */
474 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type1));
475 /* single edge trigger */
476 iowrite32(0x00000000, bank_reg(gpio, bank, reg: reg_irq_type2));
477 }
478
479 return 0;
480}
481
482static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
483 .pin_mask = GENMASK(9, 6),
484};
485
486static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
487 unsigned int offset, bool enable)
488{
489 struct aspeed_sgpio *gpio = gpiochip_get_data(gc: chip);
490 unsigned long flags;
491 void __iomem *reg;
492 u32 val;
493
494 reg = bank_reg(gpio, bank: to_bank(offset), reg: reg_tolerance);
495
496 raw_spin_lock_irqsave(&gpio->lock, flags);
497
498 val = readl(addr: reg);
499
500 if (enable)
501 val |= GPIO_BIT(offset);
502 else
503 val &= ~GPIO_BIT(offset);
504
505 writel(val, addr: reg);
506
507 raw_spin_unlock_irqrestore(&gpio->lock, flags);
508
509 return 0;
510}
511
512static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
513 unsigned long config)
514{
515 unsigned long param = pinconf_to_config_param(config);
516 u32 arg = pinconf_to_config_argument(config);
517
518 if (param == PIN_CONFIG_PERSIST_STATE)
519 return aspeed_sgpio_reset_tolerance(chip, offset, enable: arg);
520
521 return -ENOTSUPP;
522}
523
524static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
525 .pin_mask = GENMASK(10, 6),
526};
527
528static const struct of_device_id aspeed_sgpio_of_table[] = {
529 { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
530 { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
531 { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
532 {}
533};
534
535MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
536
537static int __init aspeed_sgpio_probe(struct platform_device *pdev)
538{
539 u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
540 const struct aspeed_sgpio_pdata *pdata;
541 struct aspeed_sgpio *gpio;
542 unsigned long apb_freq;
543 int rc;
544
545 gpio = devm_kzalloc(dev: &pdev->dev, size: sizeof(*gpio), GFP_KERNEL);
546 if (!gpio)
547 return -ENOMEM;
548
549 gpio->base = devm_platform_ioremap_resource(pdev, index: 0);
550 if (IS_ERR(ptr: gpio->base))
551 return PTR_ERR(ptr: gpio->base);
552
553 gpio->dev = &pdev->dev;
554
555 pdata = device_get_match_data(dev: &pdev->dev);
556 if (!pdata)
557 return -EINVAL;
558
559 pin_mask = pdata->pin_mask;
560
561 rc = device_property_read_u32(dev: &pdev->dev, propname: "ngpios", val: &nr_gpios);
562 if (rc < 0) {
563 dev_err(&pdev->dev, "Could not read ngpios property\n");
564 return -EINVAL;
565 } else if (nr_gpios % 8) {
566 dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
567 nr_gpios);
568 return -EINVAL;
569 }
570
571 rc = device_property_read_u32(dev: &pdev->dev, propname: "bus-frequency", val: &sgpio_freq);
572 if (rc < 0) {
573 dev_err(&pdev->dev, "Could not read bus-frequency property\n");
574 return -EINVAL;
575 }
576
577 gpio->pclk = devm_clk_get(dev: &pdev->dev, NULL);
578 if (IS_ERR(ptr: gpio->pclk)) {
579 dev_err(&pdev->dev, "devm_clk_get failed\n");
580 return PTR_ERR(ptr: gpio->pclk);
581 }
582
583 apb_freq = clk_get_rate(clk: gpio->pclk);
584
585 /*
586 * From the datasheet,
587 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
588 * period = 2 * (GPIO254[31:16] + 1) / PCLK
589 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
590 * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
591 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
592 * GPIO254[31:16] = PCLK / (frequency * 2) - 1
593 */
594 if (sgpio_freq == 0)
595 return -EINVAL;
596
597 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
598
599 if (sgpio_clk_div > (1 << 16) - 1)
600 return -EINVAL;
601
602 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
603 iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
604 ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
605
606 raw_spin_lock_init(&gpio->lock);
607
608 gpio->chip.parent = &pdev->dev;
609 gpio->chip.ngpio = nr_gpios * 2;
610 gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
611 gpio->chip.direction_input = aspeed_sgpio_dir_in;
612 gpio->chip.direction_output = aspeed_sgpio_dir_out;
613 gpio->chip.get_direction = aspeed_sgpio_get_direction;
614 gpio->chip.request = NULL;
615 gpio->chip.free = NULL;
616 gpio->chip.get = aspeed_sgpio_get;
617 gpio->chip.set = aspeed_sgpio_set;
618 gpio->chip.set_config = aspeed_sgpio_set_config;
619 gpio->chip.label = dev_name(dev: &pdev->dev);
620 gpio->chip.base = -1;
621
622 aspeed_sgpio_setup_irqs(gpio, pdev);
623
624 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
625 if (rc < 0)
626 return rc;
627
628 return 0;
629}
630
631static struct platform_driver aspeed_sgpio_driver = {
632 .driver = {
633 .name = KBUILD_MODNAME,
634 .of_match_table = aspeed_sgpio_of_table,
635 },
636};
637
638module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
639MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
640

source code of linux/drivers/gpio/gpio-aspeed-sgpio.c