1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright 2015 IBM Corp. |
4 | * |
5 | * Joel Stanley <joel@jms.id.au> |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/gpio/aspeed.h> |
10 | #include <linux/gpio/driver.h> |
11 | #include <linux/hashtable.h> |
12 | #include <linux/init.h> |
13 | #include <linux/io.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/module.h> |
16 | #include <linux/pinctrl/consumer.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/seq_file.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/string.h> |
21 | |
22 | #include <asm/div64.h> |
23 | |
24 | /* |
25 | * These two headers aren't meant to be used by GPIO drivers. We need |
26 | * them in order to access gpio_chip_hwgpio() which we need to implement |
27 | * the aspeed specific API which allows the coprocessor to request |
28 | * access to some GPIOs and to arbitrate between coprocessor and ARM. |
29 | */ |
30 | #include <linux/gpio/consumer.h> |
31 | #include "gpiolib.h" |
32 | |
33 | struct aspeed_bank_props { |
34 | unsigned int bank; |
35 | u32 input; |
36 | u32 output; |
37 | }; |
38 | |
39 | struct aspeed_gpio_config { |
40 | unsigned int nr_gpios; |
41 | const struct aspeed_bank_props *props; |
42 | }; |
43 | |
44 | /* |
45 | * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled |
46 | * @timer_users: Tracks the number of users for each timer |
47 | * |
48 | * The @timer_users has four elements but the first element is unused. This is |
49 | * to simplify accounting and indexing, as a zero value in @offset_timer |
50 | * represents disabled debouncing for the GPIO. Any other value for an element |
51 | * of @offset_timer is used as an index into @timer_users. This behaviour of |
52 | * the zero value aligns with the behaviour of zero built from the timer |
53 | * configuration registers (i.e. debouncing is disabled). |
54 | */ |
55 | struct aspeed_gpio { |
56 | struct gpio_chip chip; |
57 | struct device *dev; |
58 | raw_spinlock_t lock; |
59 | void __iomem *base; |
60 | int irq; |
61 | const struct aspeed_gpio_config *config; |
62 | |
63 | u8 *offset_timer; |
64 | unsigned int timer_users[4]; |
65 | struct clk *clk; |
66 | |
67 | u32 *dcache; |
68 | u8 *cf_copro_bankmap; |
69 | }; |
70 | |
71 | struct aspeed_gpio_bank { |
72 | uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch |
73 | * +4: Rd/Wr: Direction (0=in, 1=out) |
74 | */ |
75 | uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ |
76 | uint16_t irq_regs; |
77 | uint16_t debounce_regs; |
78 | uint16_t tolerance_regs; |
79 | uint16_t cmdsrc_regs; |
80 | const char names[4][3]; |
81 | }; |
82 | |
83 | /* |
84 | * Note: The "value" register returns the input value sampled on the |
85 | * line even when the GPIO is configured as an output. Since |
86 | * that input goes through synchronizers, writing, then reading |
87 | * back may not return the written value right away. |
88 | * |
89 | * The "rdata" register returns the content of the write latch |
90 | * and thus can be used to read back what was last written |
91 | * reliably. |
92 | */ |
93 | |
94 | static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; |
95 | |
96 | static const struct aspeed_gpio_copro_ops *copro_ops; |
97 | static void *copro_data; |
98 | |
99 | static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { |
100 | { |
101 | .val_regs = 0x0000, |
102 | .rdata_reg = 0x00c0, |
103 | .irq_regs = 0x0008, |
104 | .debounce_regs = 0x0040, |
105 | .tolerance_regs = 0x001c, |
106 | .cmdsrc_regs = 0x0060, |
107 | .names = { "A" , "B" , "C" , "D" }, |
108 | }, |
109 | { |
110 | .val_regs = 0x0020, |
111 | .rdata_reg = 0x00c4, |
112 | .irq_regs = 0x0028, |
113 | .debounce_regs = 0x0048, |
114 | .tolerance_regs = 0x003c, |
115 | .cmdsrc_regs = 0x0068, |
116 | .names = { "E" , "F" , "G" , "H" }, |
117 | }, |
118 | { |
119 | .val_regs = 0x0070, |
120 | .rdata_reg = 0x00c8, |
121 | .irq_regs = 0x0098, |
122 | .debounce_regs = 0x00b0, |
123 | .tolerance_regs = 0x00ac, |
124 | .cmdsrc_regs = 0x0090, |
125 | .names = { "I" , "J" , "K" , "L" }, |
126 | }, |
127 | { |
128 | .val_regs = 0x0078, |
129 | .rdata_reg = 0x00cc, |
130 | .irq_regs = 0x00e8, |
131 | .debounce_regs = 0x0100, |
132 | .tolerance_regs = 0x00fc, |
133 | .cmdsrc_regs = 0x00e0, |
134 | .names = { "M" , "N" , "O" , "P" }, |
135 | }, |
136 | { |
137 | .val_regs = 0x0080, |
138 | .rdata_reg = 0x00d0, |
139 | .irq_regs = 0x0118, |
140 | .debounce_regs = 0x0130, |
141 | .tolerance_regs = 0x012c, |
142 | .cmdsrc_regs = 0x0110, |
143 | .names = { "Q" , "R" , "S" , "T" }, |
144 | }, |
145 | { |
146 | .val_regs = 0x0088, |
147 | .rdata_reg = 0x00d4, |
148 | .irq_regs = 0x0148, |
149 | .debounce_regs = 0x0160, |
150 | .tolerance_regs = 0x015c, |
151 | .cmdsrc_regs = 0x0140, |
152 | .names = { "U" , "V" , "W" , "X" }, |
153 | }, |
154 | { |
155 | .val_regs = 0x01E0, |
156 | .rdata_reg = 0x00d8, |
157 | .irq_regs = 0x0178, |
158 | .debounce_regs = 0x0190, |
159 | .tolerance_regs = 0x018c, |
160 | .cmdsrc_regs = 0x0170, |
161 | .names = { "Y" , "Z" , "AA" , "AB" }, |
162 | }, |
163 | { |
164 | .val_regs = 0x01e8, |
165 | .rdata_reg = 0x00dc, |
166 | .irq_regs = 0x01a8, |
167 | .debounce_regs = 0x01c0, |
168 | .tolerance_regs = 0x01bc, |
169 | .cmdsrc_regs = 0x01a0, |
170 | .names = { "AC" , "" , "" , "" }, |
171 | }, |
172 | }; |
173 | |
174 | enum aspeed_gpio_reg { |
175 | reg_val, |
176 | reg_rdata, |
177 | reg_dir, |
178 | reg_irq_enable, |
179 | reg_irq_type0, |
180 | reg_irq_type1, |
181 | reg_irq_type2, |
182 | reg_irq_status, |
183 | reg_debounce_sel1, |
184 | reg_debounce_sel2, |
185 | reg_tolerance, |
186 | reg_cmdsrc0, |
187 | reg_cmdsrc1, |
188 | }; |
189 | |
190 | #define GPIO_VAL_VALUE 0x00 |
191 | #define GPIO_VAL_DIR 0x04 |
192 | |
193 | #define GPIO_IRQ_ENABLE 0x00 |
194 | #define GPIO_IRQ_TYPE0 0x04 |
195 | #define GPIO_IRQ_TYPE1 0x08 |
196 | #define GPIO_IRQ_TYPE2 0x0c |
197 | #define GPIO_IRQ_STATUS 0x10 |
198 | |
199 | #define GPIO_DEBOUNCE_SEL1 0x00 |
200 | #define GPIO_DEBOUNCE_SEL2 0x04 |
201 | |
202 | #define GPIO_CMDSRC_0 0x00 |
203 | #define GPIO_CMDSRC_1 0x04 |
204 | #define GPIO_CMDSRC_ARM 0 |
205 | #define GPIO_CMDSRC_LPC 1 |
206 | #define GPIO_CMDSRC_COLDFIRE 2 |
207 | #define GPIO_CMDSRC_RESERVED 3 |
208 | |
209 | /* This will be resolved at compile time */ |
210 | static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, |
211 | const struct aspeed_gpio_bank *bank, |
212 | const enum aspeed_gpio_reg reg) |
213 | { |
214 | switch (reg) { |
215 | case reg_val: |
216 | return gpio->base + bank->val_regs + GPIO_VAL_VALUE; |
217 | case reg_rdata: |
218 | return gpio->base + bank->rdata_reg; |
219 | case reg_dir: |
220 | return gpio->base + bank->val_regs + GPIO_VAL_DIR; |
221 | case reg_irq_enable: |
222 | return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; |
223 | case reg_irq_type0: |
224 | return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; |
225 | case reg_irq_type1: |
226 | return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; |
227 | case reg_irq_type2: |
228 | return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; |
229 | case reg_irq_status: |
230 | return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; |
231 | case reg_debounce_sel1: |
232 | return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; |
233 | case reg_debounce_sel2: |
234 | return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; |
235 | case reg_tolerance: |
236 | return gpio->base + bank->tolerance_regs; |
237 | case reg_cmdsrc0: |
238 | return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; |
239 | case reg_cmdsrc1: |
240 | return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; |
241 | } |
242 | BUG(); |
243 | } |
244 | |
245 | #define GPIO_BANK(x) ((x) >> 5) |
246 | #define GPIO_OFFSET(x) ((x) & 0x1f) |
247 | #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) |
248 | |
249 | #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) |
250 | #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) |
251 | #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) |
252 | |
253 | static const struct aspeed_gpio_bank *to_bank(unsigned int offset) |
254 | { |
255 | unsigned int bank = GPIO_BANK(offset); |
256 | |
257 | WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); |
258 | return &aspeed_gpio_banks[bank]; |
259 | } |
260 | |
261 | static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) |
262 | { |
263 | return !(props->input || props->output); |
264 | } |
265 | |
266 | static inline const struct aspeed_bank_props *find_bank_props( |
267 | struct aspeed_gpio *gpio, unsigned int offset) |
268 | { |
269 | const struct aspeed_bank_props *props = gpio->config->props; |
270 | |
271 | while (!is_bank_props_sentinel(props)) { |
272 | if (props->bank == GPIO_BANK(offset)) |
273 | return props; |
274 | props++; |
275 | } |
276 | |
277 | return NULL; |
278 | } |
279 | |
280 | static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) |
281 | { |
282 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); |
283 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
284 | unsigned int group = GPIO_OFFSET(offset) / 8; |
285 | |
286 | return bank->names[group][0] != '\0' && |
287 | (!props || ((props->input | props->output) & GPIO_BIT(offset))); |
288 | } |
289 | |
290 | static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) |
291 | { |
292 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); |
293 | |
294 | return !props || (props->input & GPIO_BIT(offset)); |
295 | } |
296 | |
297 | #define have_irq(g, o) have_input((g), (o)) |
298 | #define have_debounce(g, o) have_input((g), (o)) |
299 | |
300 | static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) |
301 | { |
302 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); |
303 | |
304 | return !props || (props->output & GPIO_BIT(offset)); |
305 | } |
306 | |
307 | static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, |
308 | const struct aspeed_gpio_bank *bank, |
309 | int bindex, int cmdsrc) |
310 | { |
311 | void __iomem *c0 = bank_reg(gpio, bank, reg: reg_cmdsrc0); |
312 | void __iomem *c1 = bank_reg(gpio, bank, reg: reg_cmdsrc1); |
313 | u32 bit, reg; |
314 | |
315 | /* |
316 | * Each register controls 4 banks, so take the bottom 2 |
317 | * bits of the bank index, and use them to select the |
318 | * right control bit (0, 8, 16 or 24). |
319 | */ |
320 | bit = BIT((bindex & 3) << 3); |
321 | |
322 | /* Source 1 first to avoid illegal 11 combination */ |
323 | reg = ioread32(c1); |
324 | if (cmdsrc & 2) |
325 | reg |= bit; |
326 | else |
327 | reg &= ~bit; |
328 | iowrite32(reg, c1); |
329 | |
330 | /* Then Source 0 */ |
331 | reg = ioread32(c0); |
332 | if (cmdsrc & 1) |
333 | reg |= bit; |
334 | else |
335 | reg &= ~bit; |
336 | iowrite32(reg, c0); |
337 | } |
338 | |
339 | static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, |
340 | unsigned int offset) |
341 | { |
342 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
343 | |
344 | if (!copro_ops || !gpio->cf_copro_bankmap) |
345 | return false; |
346 | if (!gpio->cf_copro_bankmap[offset >> 3]) |
347 | return false; |
348 | if (!copro_ops->request_access) |
349 | return false; |
350 | |
351 | /* Pause the coprocessor */ |
352 | copro_ops->request_access(copro_data); |
353 | |
354 | /* Change command source back to ARM */ |
355 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: offset >> 3, GPIO_CMDSRC_ARM); |
356 | |
357 | /* Update cache */ |
358 | gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg: reg_rdata)); |
359 | |
360 | return true; |
361 | } |
362 | |
363 | static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, |
364 | unsigned int offset) |
365 | { |
366 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
367 | |
368 | if (!copro_ops || !gpio->cf_copro_bankmap) |
369 | return; |
370 | if (!gpio->cf_copro_bankmap[offset >> 3]) |
371 | return; |
372 | if (!copro_ops->release_access) |
373 | return; |
374 | |
375 | /* Change command source back to ColdFire */ |
376 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: offset >> 3, |
377 | GPIO_CMDSRC_COLDFIRE); |
378 | |
379 | /* Restart the coprocessor */ |
380 | copro_ops->release_access(copro_data); |
381 | } |
382 | |
383 | static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) |
384 | { |
385 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
386 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
387 | |
388 | return !!(ioread32(bank_reg(gpio, bank, reg: reg_val)) & GPIO_BIT(offset)); |
389 | } |
390 | |
391 | static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, |
392 | int val) |
393 | { |
394 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
395 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
396 | void __iomem *addr; |
397 | u32 reg; |
398 | |
399 | addr = bank_reg(gpio, bank, reg: reg_val); |
400 | reg = gpio->dcache[GPIO_BANK(offset)]; |
401 | |
402 | if (val) |
403 | reg |= GPIO_BIT(offset); |
404 | else |
405 | reg &= ~GPIO_BIT(offset); |
406 | gpio->dcache[GPIO_BANK(offset)] = reg; |
407 | |
408 | iowrite32(reg, addr); |
409 | } |
410 | |
411 | static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, |
412 | int val) |
413 | { |
414 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
415 | unsigned long flags; |
416 | bool copro; |
417 | |
418 | raw_spin_lock_irqsave(&gpio->lock, flags); |
419 | copro = aspeed_gpio_copro_request(gpio, offset); |
420 | |
421 | __aspeed_gpio_set(gc, offset, val); |
422 | |
423 | if (copro) |
424 | aspeed_gpio_copro_release(gpio, offset); |
425 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
426 | } |
427 | |
428 | static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) |
429 | { |
430 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
431 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
432 | void __iomem *addr = bank_reg(gpio, bank, reg: reg_dir); |
433 | unsigned long flags; |
434 | bool copro; |
435 | u32 reg; |
436 | |
437 | if (!have_input(gpio, offset)) |
438 | return -ENOTSUPP; |
439 | |
440 | raw_spin_lock_irqsave(&gpio->lock, flags); |
441 | |
442 | reg = ioread32(addr); |
443 | reg &= ~GPIO_BIT(offset); |
444 | |
445 | copro = aspeed_gpio_copro_request(gpio, offset); |
446 | iowrite32(reg, addr); |
447 | if (copro) |
448 | aspeed_gpio_copro_release(gpio, offset); |
449 | |
450 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
451 | |
452 | return 0; |
453 | } |
454 | |
455 | static int aspeed_gpio_dir_out(struct gpio_chip *gc, |
456 | unsigned int offset, int val) |
457 | { |
458 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
459 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
460 | void __iomem *addr = bank_reg(gpio, bank, reg: reg_dir); |
461 | unsigned long flags; |
462 | bool copro; |
463 | u32 reg; |
464 | |
465 | if (!have_output(gpio, offset)) |
466 | return -ENOTSUPP; |
467 | |
468 | raw_spin_lock_irqsave(&gpio->lock, flags); |
469 | |
470 | reg = ioread32(addr); |
471 | reg |= GPIO_BIT(offset); |
472 | |
473 | copro = aspeed_gpio_copro_request(gpio, offset); |
474 | __aspeed_gpio_set(gc, offset, val); |
475 | iowrite32(reg, addr); |
476 | |
477 | if (copro) |
478 | aspeed_gpio_copro_release(gpio, offset); |
479 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
480 | |
481 | return 0; |
482 | } |
483 | |
484 | static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) |
485 | { |
486 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
487 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
488 | unsigned long flags; |
489 | u32 val; |
490 | |
491 | if (!have_input(gpio, offset)) |
492 | return GPIO_LINE_DIRECTION_OUT; |
493 | |
494 | if (!have_output(gpio, offset)) |
495 | return GPIO_LINE_DIRECTION_IN; |
496 | |
497 | raw_spin_lock_irqsave(&gpio->lock, flags); |
498 | |
499 | val = ioread32(bank_reg(gpio, bank, reg: reg_dir)) & GPIO_BIT(offset); |
500 | |
501 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
502 | |
503 | return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; |
504 | } |
505 | |
506 | static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, |
507 | struct aspeed_gpio **gpio, |
508 | const struct aspeed_gpio_bank **bank, |
509 | u32 *bit, int *offset) |
510 | { |
511 | struct aspeed_gpio *internal; |
512 | |
513 | *offset = irqd_to_hwirq(d); |
514 | |
515 | internal = irq_data_get_irq_chip_data(d); |
516 | |
517 | /* This might be a bit of a questionable place to check */ |
518 | if (!have_irq(internal, *offset)) |
519 | return -ENOTSUPP; |
520 | |
521 | *gpio = internal; |
522 | *bank = to_bank(offset: *offset); |
523 | *bit = GPIO_BIT(*offset); |
524 | |
525 | return 0; |
526 | } |
527 | |
528 | static void aspeed_gpio_irq_ack(struct irq_data *d) |
529 | { |
530 | const struct aspeed_gpio_bank *bank; |
531 | struct aspeed_gpio *gpio; |
532 | unsigned long flags; |
533 | void __iomem *status_addr; |
534 | int rc, offset; |
535 | bool copro; |
536 | u32 bit; |
537 | |
538 | rc = irqd_to_aspeed_gpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset); |
539 | if (rc) |
540 | return; |
541 | |
542 | status_addr = bank_reg(gpio, bank, reg: reg_irq_status); |
543 | |
544 | raw_spin_lock_irqsave(&gpio->lock, flags); |
545 | copro = aspeed_gpio_copro_request(gpio, offset); |
546 | |
547 | iowrite32(bit, status_addr); |
548 | |
549 | if (copro) |
550 | aspeed_gpio_copro_release(gpio, offset); |
551 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
552 | } |
553 | |
554 | static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) |
555 | { |
556 | const struct aspeed_gpio_bank *bank; |
557 | struct aspeed_gpio *gpio; |
558 | unsigned long flags; |
559 | u32 reg, bit; |
560 | void __iomem *addr; |
561 | int rc, offset; |
562 | bool copro; |
563 | |
564 | rc = irqd_to_aspeed_gpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset); |
565 | if (rc) |
566 | return; |
567 | |
568 | addr = bank_reg(gpio, bank, reg: reg_irq_enable); |
569 | |
570 | /* Unmasking the IRQ */ |
571 | if (set) |
572 | gpiochip_enable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d)); |
573 | |
574 | raw_spin_lock_irqsave(&gpio->lock, flags); |
575 | copro = aspeed_gpio_copro_request(gpio, offset); |
576 | |
577 | reg = ioread32(addr); |
578 | if (set) |
579 | reg |= bit; |
580 | else |
581 | reg &= ~bit; |
582 | iowrite32(reg, addr); |
583 | |
584 | if (copro) |
585 | aspeed_gpio_copro_release(gpio, offset); |
586 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
587 | |
588 | /* Masking the IRQ */ |
589 | if (!set) |
590 | gpiochip_disable_irq(gc: &gpio->chip, offset: irqd_to_hwirq(d)); |
591 | } |
592 | |
593 | static void aspeed_gpio_irq_mask(struct irq_data *d) |
594 | { |
595 | aspeed_gpio_irq_set_mask(d, set: false); |
596 | } |
597 | |
598 | static void aspeed_gpio_irq_unmask(struct irq_data *d) |
599 | { |
600 | aspeed_gpio_irq_set_mask(d, set: true); |
601 | } |
602 | |
603 | static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) |
604 | { |
605 | u32 type0 = 0; |
606 | u32 type1 = 0; |
607 | u32 type2 = 0; |
608 | u32 bit, reg; |
609 | const struct aspeed_gpio_bank *bank; |
610 | irq_flow_handler_t handler; |
611 | struct aspeed_gpio *gpio; |
612 | unsigned long flags; |
613 | void __iomem *addr; |
614 | int rc, offset; |
615 | bool copro; |
616 | |
617 | rc = irqd_to_aspeed_gpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset); |
618 | if (rc) |
619 | return -EINVAL; |
620 | |
621 | switch (type & IRQ_TYPE_SENSE_MASK) { |
622 | case IRQ_TYPE_EDGE_BOTH: |
623 | type2 |= bit; |
624 | fallthrough; |
625 | case IRQ_TYPE_EDGE_RISING: |
626 | type0 |= bit; |
627 | fallthrough; |
628 | case IRQ_TYPE_EDGE_FALLING: |
629 | handler = handle_edge_irq; |
630 | break; |
631 | case IRQ_TYPE_LEVEL_HIGH: |
632 | type0 |= bit; |
633 | fallthrough; |
634 | case IRQ_TYPE_LEVEL_LOW: |
635 | type1 |= bit; |
636 | handler = handle_level_irq; |
637 | break; |
638 | default: |
639 | return -EINVAL; |
640 | } |
641 | |
642 | raw_spin_lock_irqsave(&gpio->lock, flags); |
643 | copro = aspeed_gpio_copro_request(gpio, offset); |
644 | |
645 | addr = bank_reg(gpio, bank, reg: reg_irq_type0); |
646 | reg = ioread32(addr); |
647 | reg = (reg & ~bit) | type0; |
648 | iowrite32(reg, addr); |
649 | |
650 | addr = bank_reg(gpio, bank, reg: reg_irq_type1); |
651 | reg = ioread32(addr); |
652 | reg = (reg & ~bit) | type1; |
653 | iowrite32(reg, addr); |
654 | |
655 | addr = bank_reg(gpio, bank, reg: reg_irq_type2); |
656 | reg = ioread32(addr); |
657 | reg = (reg & ~bit) | type2; |
658 | iowrite32(reg, addr); |
659 | |
660 | if (copro) |
661 | aspeed_gpio_copro_release(gpio, offset); |
662 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
663 | |
664 | irq_set_handler_locked(data: d, handler); |
665 | |
666 | return 0; |
667 | } |
668 | |
669 | static void aspeed_gpio_irq_handler(struct irq_desc *desc) |
670 | { |
671 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
672 | struct irq_chip *ic = irq_desc_get_chip(desc); |
673 | struct aspeed_gpio *data = gpiochip_get_data(gc); |
674 | unsigned int i, p, banks; |
675 | unsigned long reg; |
676 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
677 | |
678 | chained_irq_enter(chip: ic, desc); |
679 | |
680 | banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); |
681 | for (i = 0; i < banks; i++) { |
682 | const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; |
683 | |
684 | reg = ioread32(bank_reg(gpio: data, bank, reg: reg_irq_status)); |
685 | |
686 | for_each_set_bit(p, ®, 32) |
687 | generic_handle_domain_irq(domain: gc->irq.domain, hwirq: i * 32 + p); |
688 | } |
689 | |
690 | chained_irq_exit(chip: ic, desc); |
691 | } |
692 | |
693 | static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, |
694 | unsigned long *valid_mask, |
695 | unsigned int ngpios) |
696 | { |
697 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); |
698 | const struct aspeed_bank_props *props = gpio->config->props; |
699 | |
700 | while (!is_bank_props_sentinel(props)) { |
701 | unsigned int offset; |
702 | const unsigned long int input = props->input; |
703 | |
704 | /* Pretty crummy approach, but similar to GPIO core */ |
705 | for_each_clear_bit(offset, &input, 32) { |
706 | unsigned int i = props->bank * 32 + offset; |
707 | |
708 | if (i >= gpio->chip.ngpio) |
709 | break; |
710 | |
711 | clear_bit(nr: i, addr: valid_mask); |
712 | } |
713 | |
714 | props++; |
715 | } |
716 | } |
717 | |
718 | static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, |
719 | unsigned int offset, bool enable) |
720 | { |
721 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
722 | unsigned long flags; |
723 | void __iomem *treg; |
724 | bool copro; |
725 | u32 val; |
726 | |
727 | treg = bank_reg(gpio, bank: to_bank(offset), reg: reg_tolerance); |
728 | |
729 | raw_spin_lock_irqsave(&gpio->lock, flags); |
730 | copro = aspeed_gpio_copro_request(gpio, offset); |
731 | |
732 | val = readl(addr: treg); |
733 | |
734 | if (enable) |
735 | val |= GPIO_BIT(offset); |
736 | else |
737 | val &= ~GPIO_BIT(offset); |
738 | |
739 | writel(val, addr: treg); |
740 | |
741 | if (copro) |
742 | aspeed_gpio_copro_release(gpio, offset); |
743 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
744 | |
745 | return 0; |
746 | } |
747 | |
748 | static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) |
749 | { |
750 | if (!have_gpio(gpio: gpiochip_get_data(gc: chip), offset)) |
751 | return -ENODEV; |
752 | |
753 | return pinctrl_gpio_request(gc: chip, offset); |
754 | } |
755 | |
756 | static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) |
757 | { |
758 | pinctrl_gpio_free(gc: chip, offset); |
759 | } |
760 | |
761 | static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, |
762 | u32 *cycles) |
763 | { |
764 | u64 rate; |
765 | u64 n; |
766 | u32 r; |
767 | |
768 | rate = clk_get_rate(clk: gpio->clk); |
769 | if (!rate) |
770 | return -ENOTSUPP; |
771 | |
772 | n = rate * usecs; |
773 | r = do_div(n, 1000000); |
774 | |
775 | if (n >= U32_MAX) |
776 | return -ERANGE; |
777 | |
778 | /* At least as long as the requested time */ |
779 | *cycles = n + (!!r); |
780 | |
781 | return 0; |
782 | } |
783 | |
784 | /* Call under gpio->lock */ |
785 | static int register_allocated_timer(struct aspeed_gpio *gpio, |
786 | unsigned int offset, unsigned int timer) |
787 | { |
788 | if (WARN(gpio->offset_timer[offset] != 0, |
789 | "Offset %d already allocated timer %d\n" , |
790 | offset, gpio->offset_timer[offset])) |
791 | return -EINVAL; |
792 | |
793 | if (WARN(gpio->timer_users[timer] == UINT_MAX, |
794 | "Timer user count would overflow\n" )) |
795 | return -EPERM; |
796 | |
797 | gpio->offset_timer[offset] = timer; |
798 | gpio->timer_users[timer]++; |
799 | |
800 | return 0; |
801 | } |
802 | |
803 | /* Call under gpio->lock */ |
804 | static int unregister_allocated_timer(struct aspeed_gpio *gpio, |
805 | unsigned int offset) |
806 | { |
807 | if (WARN(gpio->offset_timer[offset] == 0, |
808 | "No timer allocated to offset %d\n" , offset)) |
809 | return -EINVAL; |
810 | |
811 | if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, |
812 | "No users recorded for timer %d\n" , |
813 | gpio->offset_timer[offset])) |
814 | return -EINVAL; |
815 | |
816 | gpio->timer_users[gpio->offset_timer[offset]]--; |
817 | gpio->offset_timer[offset] = 0; |
818 | |
819 | return 0; |
820 | } |
821 | |
822 | /* Call under gpio->lock */ |
823 | static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, |
824 | unsigned int offset) |
825 | { |
826 | return gpio->offset_timer[offset] > 0; |
827 | } |
828 | |
829 | /* Call under gpio->lock */ |
830 | static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, |
831 | unsigned int timer) |
832 | { |
833 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
834 | const u32 mask = GPIO_BIT(offset); |
835 | void __iomem *addr; |
836 | u32 val; |
837 | |
838 | /* Note: Debounce timer isn't under control of the command |
839 | * source registers, so no need to sync with the coprocessor |
840 | */ |
841 | addr = bank_reg(gpio, bank, reg: reg_debounce_sel1); |
842 | val = ioread32(addr); |
843 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); |
844 | |
845 | addr = bank_reg(gpio, bank, reg: reg_debounce_sel2); |
846 | val = ioread32(addr); |
847 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); |
848 | } |
849 | |
850 | static int enable_debounce(struct gpio_chip *chip, unsigned int offset, |
851 | unsigned long usecs) |
852 | { |
853 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
854 | u32 requested_cycles; |
855 | unsigned long flags; |
856 | int rc; |
857 | int i; |
858 | |
859 | if (!gpio->clk) |
860 | return -EINVAL; |
861 | |
862 | rc = usecs_to_cycles(gpio, usecs, cycles: &requested_cycles); |
863 | if (rc < 0) { |
864 | dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n" , |
865 | usecs, clk_get_rate(gpio->clk), rc); |
866 | return rc; |
867 | } |
868 | |
869 | raw_spin_lock_irqsave(&gpio->lock, flags); |
870 | |
871 | if (timer_allocation_registered(gpio, offset)) { |
872 | rc = unregister_allocated_timer(gpio, offset); |
873 | if (rc < 0) |
874 | goto out; |
875 | } |
876 | |
877 | /* Try to find a timer already configured for the debounce period */ |
878 | for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { |
879 | u32 cycles; |
880 | |
881 | cycles = ioread32(gpio->base + debounce_timers[i]); |
882 | if (requested_cycles == cycles) |
883 | break; |
884 | } |
885 | |
886 | if (i == ARRAY_SIZE(debounce_timers)) { |
887 | int j; |
888 | |
889 | /* |
890 | * As there are no timers configured for the requested debounce |
891 | * period, find an unused timer instead |
892 | */ |
893 | for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { |
894 | if (gpio->timer_users[j] == 0) |
895 | break; |
896 | } |
897 | |
898 | if (j == ARRAY_SIZE(gpio->timer_users)) { |
899 | dev_warn(chip->parent, |
900 | "Debounce timers exhausted, cannot debounce for period %luus\n" , |
901 | usecs); |
902 | |
903 | rc = -EPERM; |
904 | |
905 | /* |
906 | * We already adjusted the accounting to remove @offset |
907 | * as a user of its previous timer, so also configure |
908 | * the hardware so @offset has timers disabled for |
909 | * consistency. |
910 | */ |
911 | configure_timer(gpio, offset, timer: 0); |
912 | goto out; |
913 | } |
914 | |
915 | i = j; |
916 | |
917 | iowrite32(requested_cycles, gpio->base + debounce_timers[i]); |
918 | } |
919 | |
920 | if (WARN(i == 0, "Cannot register index of disabled timer\n" )) { |
921 | rc = -EINVAL; |
922 | goto out; |
923 | } |
924 | |
925 | register_allocated_timer(gpio, offset, timer: i); |
926 | configure_timer(gpio, offset, timer: i); |
927 | |
928 | out: |
929 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
930 | |
931 | return rc; |
932 | } |
933 | |
934 | static int disable_debounce(struct gpio_chip *chip, unsigned int offset) |
935 | { |
936 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
937 | unsigned long flags; |
938 | int rc; |
939 | |
940 | raw_spin_lock_irqsave(&gpio->lock, flags); |
941 | |
942 | rc = unregister_allocated_timer(gpio, offset); |
943 | if (!rc) |
944 | configure_timer(gpio, offset, timer: 0); |
945 | |
946 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
947 | |
948 | return rc; |
949 | } |
950 | |
951 | static int set_debounce(struct gpio_chip *chip, unsigned int offset, |
952 | unsigned long usecs) |
953 | { |
954 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
955 | |
956 | if (!have_debounce(gpio, offset)) |
957 | return -ENOTSUPP; |
958 | |
959 | if (usecs) |
960 | return enable_debounce(chip, offset, usecs); |
961 | |
962 | return disable_debounce(chip, offset); |
963 | } |
964 | |
965 | static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
966 | unsigned long config) |
967 | { |
968 | unsigned long param = pinconf_to_config_param(config); |
969 | u32 arg = pinconf_to_config_argument(config); |
970 | |
971 | if (param == PIN_CONFIG_INPUT_DEBOUNCE) |
972 | return set_debounce(chip, offset, usecs: arg); |
973 | else if (param == PIN_CONFIG_BIAS_DISABLE || |
974 | param == PIN_CONFIG_BIAS_PULL_DOWN || |
975 | param == PIN_CONFIG_DRIVE_STRENGTH) |
976 | return pinctrl_gpio_set_config(gc: chip, offset, config); |
977 | else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || |
978 | param == PIN_CONFIG_DRIVE_OPEN_SOURCE) |
979 | /* Return -ENOTSUPP to trigger emulation, as per datasheet */ |
980 | return -ENOTSUPP; |
981 | else if (param == PIN_CONFIG_PERSIST_STATE) |
982 | return aspeed_gpio_reset_tolerance(chip, offset, enable: arg); |
983 | |
984 | return -ENOTSUPP; |
985 | } |
986 | |
987 | /** |
988 | * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with |
989 | * the coprocessor for shared GPIO banks |
990 | * @ops: The callbacks |
991 | * @data: Pointer passed back to the callbacks |
992 | */ |
993 | int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) |
994 | { |
995 | copro_data = data; |
996 | copro_ops = ops; |
997 | |
998 | return 0; |
999 | } |
1000 | EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); |
1001 | |
1002 | /** |
1003 | * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire |
1004 | * bank gets marked and any access from the ARM will |
1005 | * result in handshaking via callbacks. |
1006 | * @desc: The GPIO to be marked |
1007 | * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space |
1008 | * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space |
1009 | * @bit: If non-NULL, returns the bit number of the GPIO in the registers |
1010 | */ |
1011 | int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, |
1012 | u16 *vreg_offset, u16 *dreg_offset, u8 *bit) |
1013 | { |
1014 | struct gpio_chip *chip = gpiod_to_chip(desc); |
1015 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
1016 | int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); |
1017 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
1018 | unsigned long flags; |
1019 | |
1020 | if (!gpio->cf_copro_bankmap) |
1021 | gpio->cf_copro_bankmap = kzalloc(size: gpio->chip.ngpio >> 3, GFP_KERNEL); |
1022 | if (!gpio->cf_copro_bankmap) |
1023 | return -ENOMEM; |
1024 | if (offset < 0 || offset > gpio->chip.ngpio) |
1025 | return -EINVAL; |
1026 | bindex = offset >> 3; |
1027 | |
1028 | raw_spin_lock_irqsave(&gpio->lock, flags); |
1029 | |
1030 | /* Sanity check, this shouldn't happen */ |
1031 | if (gpio->cf_copro_bankmap[bindex] == 0xff) { |
1032 | rc = -EIO; |
1033 | goto bail; |
1034 | } |
1035 | gpio->cf_copro_bankmap[bindex]++; |
1036 | |
1037 | /* Switch command source */ |
1038 | if (gpio->cf_copro_bankmap[bindex] == 1) |
1039 | aspeed_gpio_change_cmd_source(gpio, bank, bindex, |
1040 | GPIO_CMDSRC_COLDFIRE); |
1041 | |
1042 | if (vreg_offset) |
1043 | *vreg_offset = bank->val_regs; |
1044 | if (dreg_offset) |
1045 | *dreg_offset = bank->rdata_reg; |
1046 | if (bit) |
1047 | *bit = GPIO_OFFSET(offset); |
1048 | bail: |
1049 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
1050 | return rc; |
1051 | } |
1052 | EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); |
1053 | |
1054 | /** |
1055 | * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. |
1056 | * @desc: The GPIO to be marked |
1057 | */ |
1058 | int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) |
1059 | { |
1060 | struct gpio_chip *chip = gpiod_to_chip(desc); |
1061 | struct aspeed_gpio *gpio = gpiochip_get_data(gc: chip); |
1062 | int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); |
1063 | const struct aspeed_gpio_bank *bank = to_bank(offset); |
1064 | unsigned long flags; |
1065 | |
1066 | if (!gpio->cf_copro_bankmap) |
1067 | return -ENXIO; |
1068 | |
1069 | if (offset < 0 || offset > gpio->chip.ngpio) |
1070 | return -EINVAL; |
1071 | bindex = offset >> 3; |
1072 | |
1073 | raw_spin_lock_irqsave(&gpio->lock, flags); |
1074 | |
1075 | /* Sanity check, this shouldn't happen */ |
1076 | if (gpio->cf_copro_bankmap[bindex] == 0) { |
1077 | rc = -EIO; |
1078 | goto bail; |
1079 | } |
1080 | gpio->cf_copro_bankmap[bindex]--; |
1081 | |
1082 | /* Switch command source */ |
1083 | if (gpio->cf_copro_bankmap[bindex] == 0) |
1084 | aspeed_gpio_change_cmd_source(gpio, bank, bindex, |
1085 | GPIO_CMDSRC_ARM); |
1086 | bail: |
1087 | raw_spin_unlock_irqrestore(&gpio->lock, flags); |
1088 | return rc; |
1089 | } |
1090 | EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); |
1091 | |
1092 | static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) |
1093 | { |
1094 | const struct aspeed_gpio_bank *bank; |
1095 | struct aspeed_gpio *gpio; |
1096 | u32 bit; |
1097 | int rc, offset; |
1098 | |
1099 | rc = irqd_to_aspeed_gpio_data(d, gpio: &gpio, bank: &bank, bit: &bit, offset: &offset); |
1100 | if (rc) |
1101 | return; |
1102 | |
1103 | seq_printf(m: p, fmt: dev_name(dev: gpio->dev)); |
1104 | } |
1105 | |
1106 | static const struct irq_chip aspeed_gpio_irq_chip = { |
1107 | .irq_ack = aspeed_gpio_irq_ack, |
1108 | .irq_mask = aspeed_gpio_irq_mask, |
1109 | .irq_unmask = aspeed_gpio_irq_unmask, |
1110 | .irq_set_type = aspeed_gpio_set_type, |
1111 | .irq_print_chip = aspeed_gpio_irq_print_chip, |
1112 | .flags = IRQCHIP_IMMUTABLE, |
1113 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
1114 | }; |
1115 | |
1116 | /* |
1117 | * Any banks not specified in a struct aspeed_bank_props array are assumed to |
1118 | * have the properties: |
1119 | * |
1120 | * { .input = 0xffffffff, .output = 0xffffffff } |
1121 | */ |
1122 | |
1123 | static const struct aspeed_bank_props ast2400_bank_props[] = { |
1124 | /* input output */ |
1125 | { .bank: 5, .input: 0xffffffff, .output: 0x0000ffff }, /* U/V/W/X */ |
1126 | { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ |
1127 | { }, |
1128 | }; |
1129 | |
1130 | static const struct aspeed_gpio_config ast2400_config = |
1131 | /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ |
1132 | { .nr_gpios = 220, .props = ast2400_bank_props, }; |
1133 | |
1134 | static const struct aspeed_bank_props ast2500_bank_props[] = { |
1135 | /* input output */ |
1136 | { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ |
1137 | { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ |
1138 | { 7, 0x000000ff, 0x000000ff }, /* AC */ |
1139 | { }, |
1140 | }; |
1141 | |
1142 | static const struct aspeed_gpio_config ast2500_config = |
1143 | /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ |
1144 | { .nr_gpios = 232, .props = ast2500_bank_props, }; |
1145 | |
1146 | static const struct aspeed_bank_props ast2600_bank_props[] = { |
1147 | /* input output */ |
1148 | {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ |
1149 | {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ |
1150 | {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ |
1151 | { }, |
1152 | }; |
1153 | |
1154 | static const struct aspeed_gpio_config ast2600_config = |
1155 | /* |
1156 | * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. |
1157 | * We expect ngpio being set in the device tree and this is a fallback |
1158 | * option. |
1159 | */ |
1160 | { .nr_gpios = 208, .props = ast2600_bank_props, }; |
1161 | |
1162 | static const struct of_device_id aspeed_gpio_of_table[] = { |
1163 | { .compatible = "aspeed,ast2400-gpio" , .data = &ast2400_config, }, |
1164 | { .compatible = "aspeed,ast2500-gpio" , .data = &ast2500_config, }, |
1165 | { .compatible = "aspeed,ast2600-gpio" , .data = &ast2600_config, }, |
1166 | {} |
1167 | }; |
1168 | MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); |
1169 | |
1170 | static int __init aspeed_gpio_probe(struct platform_device *pdev) |
1171 | { |
1172 | const struct of_device_id *gpio_id; |
1173 | struct gpio_irq_chip *girq; |
1174 | struct aspeed_gpio *gpio; |
1175 | int rc, irq, i, banks, err; |
1176 | u32 ngpio; |
1177 | |
1178 | gpio = devm_kzalloc(dev: &pdev->dev, size: sizeof(*gpio), GFP_KERNEL); |
1179 | if (!gpio) |
1180 | return -ENOMEM; |
1181 | |
1182 | gpio->base = devm_platform_ioremap_resource(pdev, index: 0); |
1183 | if (IS_ERR(ptr: gpio->base)) |
1184 | return PTR_ERR(ptr: gpio->base); |
1185 | |
1186 | gpio->dev = &pdev->dev; |
1187 | |
1188 | raw_spin_lock_init(&gpio->lock); |
1189 | |
1190 | gpio_id = of_match_node(matches: aspeed_gpio_of_table, node: pdev->dev.of_node); |
1191 | if (!gpio_id) |
1192 | return -EINVAL; |
1193 | |
1194 | gpio->clk = of_clk_get(np: pdev->dev.of_node, index: 0); |
1195 | if (IS_ERR(ptr: gpio->clk)) { |
1196 | dev_warn(&pdev->dev, |
1197 | "Failed to get clock from devicetree, debouncing disabled\n" ); |
1198 | gpio->clk = NULL; |
1199 | } |
1200 | |
1201 | gpio->config = gpio_id->data; |
1202 | |
1203 | gpio->chip.parent = &pdev->dev; |
1204 | err = of_property_read_u32(np: pdev->dev.of_node, propname: "ngpios" , out_value: &ngpio); |
1205 | gpio->chip.ngpio = (u16) ngpio; |
1206 | if (err) |
1207 | gpio->chip.ngpio = gpio->config->nr_gpios; |
1208 | gpio->chip.direction_input = aspeed_gpio_dir_in; |
1209 | gpio->chip.direction_output = aspeed_gpio_dir_out; |
1210 | gpio->chip.get_direction = aspeed_gpio_get_direction; |
1211 | gpio->chip.request = aspeed_gpio_request; |
1212 | gpio->chip.free = aspeed_gpio_free; |
1213 | gpio->chip.get = aspeed_gpio_get; |
1214 | gpio->chip.set = aspeed_gpio_set; |
1215 | gpio->chip.set_config = aspeed_gpio_set_config; |
1216 | gpio->chip.label = dev_name(dev: &pdev->dev); |
1217 | gpio->chip.base = -1; |
1218 | |
1219 | /* Allocate a cache of the output registers */ |
1220 | banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); |
1221 | gpio->dcache = devm_kcalloc(dev: &pdev->dev, |
1222 | n: banks, size: sizeof(u32), GFP_KERNEL); |
1223 | if (!gpio->dcache) |
1224 | return -ENOMEM; |
1225 | |
1226 | /* |
1227 | * Populate it with initial values read from the HW and switch |
1228 | * all command sources to the ARM by default |
1229 | */ |
1230 | for (i = 0; i < banks; i++) { |
1231 | const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; |
1232 | void __iomem *addr = bank_reg(gpio, bank, reg: reg_rdata); |
1233 | gpio->dcache[i] = ioread32(addr); |
1234 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: 0, GPIO_CMDSRC_ARM); |
1235 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: 1, GPIO_CMDSRC_ARM); |
1236 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: 2, GPIO_CMDSRC_ARM); |
1237 | aspeed_gpio_change_cmd_source(gpio, bank, bindex: 3, GPIO_CMDSRC_ARM); |
1238 | } |
1239 | |
1240 | /* Set up an irqchip */ |
1241 | irq = platform_get_irq(pdev, 0); |
1242 | if (irq < 0) |
1243 | return irq; |
1244 | gpio->irq = irq; |
1245 | girq = &gpio->chip.irq; |
1246 | gpio_irq_chip_set_chip(girq, chip: &aspeed_gpio_irq_chip); |
1247 | |
1248 | girq->parent_handler = aspeed_gpio_irq_handler; |
1249 | girq->num_parents = 1; |
1250 | girq->parents = devm_kcalloc(dev: &pdev->dev, n: 1, size: sizeof(*girq->parents), GFP_KERNEL); |
1251 | if (!girq->parents) |
1252 | return -ENOMEM; |
1253 | girq->parents[0] = gpio->irq; |
1254 | girq->default_type = IRQ_TYPE_NONE; |
1255 | girq->handler = handle_bad_irq; |
1256 | girq->init_valid_mask = aspeed_init_irq_valid_mask; |
1257 | |
1258 | gpio->offset_timer = |
1259 | devm_kzalloc(dev: &pdev->dev, size: gpio->chip.ngpio, GFP_KERNEL); |
1260 | if (!gpio->offset_timer) |
1261 | return -ENOMEM; |
1262 | |
1263 | rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); |
1264 | if (rc < 0) |
1265 | return rc; |
1266 | |
1267 | return 0; |
1268 | } |
1269 | |
1270 | static struct platform_driver aspeed_gpio_driver = { |
1271 | .driver = { |
1272 | .name = KBUILD_MODNAME, |
1273 | .of_match_table = aspeed_gpio_of_table, |
1274 | }, |
1275 | }; |
1276 | |
1277 | module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); |
1278 | |
1279 | MODULE_DESCRIPTION("Aspeed GPIO Driver" ); |
1280 | MODULE_LICENSE("GPL" ); |
1281 | |