1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ |
3 | /* |
4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: |
15 | * |
16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. |
19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
28 | */ |
29 | |
30 | #include <linux/acpi.h> |
31 | #include <linux/device.h> |
32 | #include <linux/module.h> |
33 | #include <linux/oom.h> |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> |
36 | #include <linux/pm_runtime.h> |
37 | #include <linux/slab.h> |
38 | #include <linux/string_helpers.h> |
39 | #include <linux/vga_switcheroo.h> |
40 | #include <linux/vt.h> |
41 | |
42 | #include <drm/drm_aperture.h> |
43 | #include <drm/drm_atomic_helper.h> |
44 | #include <drm/drm_ioctl.h> |
45 | #include <drm/drm_managed.h> |
46 | #include <drm/drm_probe_helper.h> |
47 | |
48 | #include "display/intel_acpi.h" |
49 | #include "display/intel_bw.h" |
50 | #include "display/intel_cdclk.h" |
51 | #include "display/intel_display_driver.h" |
52 | #include "display/intel_display_types.h" |
53 | #include "display/intel_dmc.h" |
54 | #include "display/intel_dp.h" |
55 | #include "display/intel_dpt.h" |
56 | #include "display/intel_fbdev.h" |
57 | #include "display/intel_hotplug.h" |
58 | #include "display/intel_overlay.h" |
59 | #include "display/intel_pch_refclk.h" |
60 | #include "display/intel_pipe_crc.h" |
61 | #include "display/intel_pps.h" |
62 | #include "display/intel_sprite.h" |
63 | #include "display/intel_vga.h" |
64 | #include "display/skl_watermark.h" |
65 | |
66 | #include "gem/i915_gem_context.h" |
67 | #include "gem/i915_gem_create.h" |
68 | #include "gem/i915_gem_dmabuf.h" |
69 | #include "gem/i915_gem_ioctls.h" |
70 | #include "gem/i915_gem_mman.h" |
71 | #include "gem/i915_gem_pm.h" |
72 | #include "gt/intel_gt.h" |
73 | #include "gt/intel_gt_pm.h" |
74 | #include "gt/intel_gt_print.h" |
75 | #include "gt/intel_rc6.h" |
76 | |
77 | #include "pxp/intel_pxp.h" |
78 | #include "pxp/intel_pxp_debugfs.h" |
79 | #include "pxp/intel_pxp_pm.h" |
80 | |
81 | #include "soc/intel_dram.h" |
82 | #include "soc/intel_gmch.h" |
83 | |
84 | #include "i915_debugfs.h" |
85 | #include "i915_driver.h" |
86 | #include "i915_drm_client.h" |
87 | #include "i915_drv.h" |
88 | #include "i915_file_private.h" |
89 | #include "i915_getparam.h" |
90 | #include "i915_hwmon.h" |
91 | #include "i915_ioc32.h" |
92 | #include "i915_ioctl.h" |
93 | #include "i915_irq.h" |
94 | #include "i915_memcpy.h" |
95 | #include "i915_perf.h" |
96 | #include "i915_query.h" |
97 | #include "i915_suspend.h" |
98 | #include "i915_switcheroo.h" |
99 | #include "i915_sysfs.h" |
100 | #include "i915_utils.h" |
101 | #include "i915_vgpu.h" |
102 | #include "intel_clock_gating.h" |
103 | #include "intel_gvt.h" |
104 | #include "intel_memory_region.h" |
105 | #include "intel_pci_config.h" |
106 | #include "intel_pcode.h" |
107 | #include "intel_region_ttm.h" |
108 | #include "vlv_suspend.h" |
109 | |
110 | static const struct drm_driver i915_drm_driver; |
111 | |
112 | static int i915_workqueues_init(struct drm_i915_private *dev_priv) |
113 | { |
114 | /* |
115 | * The i915 workqueue is primarily used for batched retirement of |
116 | * requests (and thus managing bo) once the task has been completed |
117 | * by the GPU. i915_retire_requests() is called directly when we |
118 | * need high-priority retirement, such as waiting for an explicit |
119 | * bo. |
120 | * |
121 | * It is also used for periodic low-priority events, such as |
122 | * idle-timers and recording error state. |
123 | * |
124 | * All tasks on the workqueue are expected to acquire the dev mutex |
125 | * so there is no point in running more than one instance of the |
126 | * workqueue at any time. Use an ordered one. |
127 | */ |
128 | dev_priv->wq = alloc_ordered_workqueue("i915" , 0); |
129 | if (dev_priv->wq == NULL) |
130 | goto out_err; |
131 | |
132 | dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp" , 0); |
133 | if (dev_priv->display.hotplug.dp_wq == NULL) |
134 | goto out_free_wq; |
135 | |
136 | /* |
137 | * The unordered i915 workqueue should be used for all work |
138 | * scheduling that do not require running in order, which used |
139 | * to be scheduled on the system_wq before moving to a driver |
140 | * instance due deprecation of flush_scheduled_work(). |
141 | */ |
142 | dev_priv->unordered_wq = alloc_workqueue(fmt: "i915-unordered" , flags: 0, max_active: 0); |
143 | if (dev_priv->unordered_wq == NULL) |
144 | goto out_free_dp_wq; |
145 | |
146 | return 0; |
147 | |
148 | out_free_dp_wq: |
149 | destroy_workqueue(wq: dev_priv->display.hotplug.dp_wq); |
150 | out_free_wq: |
151 | destroy_workqueue(wq: dev_priv->wq); |
152 | out_err: |
153 | drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n" ); |
154 | |
155 | return -ENOMEM; |
156 | } |
157 | |
158 | static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) |
159 | { |
160 | destroy_workqueue(wq: dev_priv->unordered_wq); |
161 | destroy_workqueue(wq: dev_priv->display.hotplug.dp_wq); |
162 | destroy_workqueue(wq: dev_priv->wq); |
163 | } |
164 | |
165 | /* |
166 | * We don't keep the workarounds for pre-production hardware, so we expect our |
167 | * driver to fail on these machines in one way or another. A little warning on |
168 | * dmesg may help both the user and the bug triagers. |
169 | * |
170 | * Our policy for removing pre-production workarounds is to keep the |
171 | * current gen workarounds as a guide to the bring-up of the next gen |
172 | * (workarounds have a habit of persisting!). Anything older than that |
173 | * should be removed along with the complications they introduce. |
174 | */ |
175 | static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) |
176 | { |
177 | bool pre = false; |
178 | |
179 | pre |= IS_HASWELL_EARLY_SDV(dev_priv); |
180 | pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; |
181 | pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; |
182 | pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; |
183 | pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; |
184 | pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; |
185 | pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; |
186 | pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; |
187 | pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; |
188 | pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; |
189 | pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; |
190 | |
191 | if (pre) { |
192 | drm_err(&dev_priv->drm, "This is a pre-production stepping. " |
193 | "It may not be fully functional.\n" ); |
194 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
195 | } |
196 | } |
197 | |
198 | static void sanitize_gpu(struct drm_i915_private *i915) |
199 | { |
200 | if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { |
201 | struct intel_gt *gt; |
202 | unsigned int i; |
203 | |
204 | for_each_gt(gt, i915, i) |
205 | __intel_gt_reset(gt, ALL_ENGINES); |
206 | } |
207 | } |
208 | |
209 | /** |
210 | * i915_driver_early_probe - setup state not requiring device access |
211 | * @dev_priv: device private |
212 | * |
213 | * Initialize everything that is a "SW-only" state, that is state not |
214 | * requiring accessing the device or exposing the driver via kernel internal |
215 | * or userspace interfaces. Example steps belonging here: lock initialization, |
216 | * system memory allocation, setting up device specific attributes and |
217 | * function hooks not requiring accessing the device. |
218 | */ |
219 | static int i915_driver_early_probe(struct drm_i915_private *dev_priv) |
220 | { |
221 | int ret = 0; |
222 | |
223 | if (i915_inject_probe_failure(dev_priv)) |
224 | return -ENODEV; |
225 | |
226 | intel_device_info_runtime_init_early(dev_priv); |
227 | |
228 | intel_step_init(i915: dev_priv); |
229 | |
230 | intel_uncore_mmio_debug_init_early(i915: dev_priv); |
231 | |
232 | spin_lock_init(&dev_priv->irq_lock); |
233 | spin_lock_init(&dev_priv->gpu_error.lock); |
234 | mutex_init(&dev_priv->display.backlight.lock); |
235 | |
236 | mutex_init(&dev_priv->sb_lock); |
237 | cpu_latency_qos_add_request(req: &dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); |
238 | |
239 | mutex_init(&dev_priv->display.audio.mutex); |
240 | mutex_init(&dev_priv->display.wm.wm_mutex); |
241 | mutex_init(&dev_priv->display.pps.mutex); |
242 | mutex_init(&dev_priv->display.hdcp.hdcp_mutex); |
243 | |
244 | i915_memcpy_init_early(i915: dev_priv); |
245 | intel_runtime_pm_init_early(rpm: &dev_priv->runtime_pm); |
246 | |
247 | ret = i915_workqueues_init(dev_priv); |
248 | if (ret < 0) |
249 | return ret; |
250 | |
251 | ret = vlv_suspend_init(i915: dev_priv); |
252 | if (ret < 0) |
253 | goto err_workqueues; |
254 | |
255 | ret = intel_region_ttm_device_init(dev_priv); |
256 | if (ret) |
257 | goto err_ttm; |
258 | |
259 | ret = intel_root_gt_init_early(i915: dev_priv); |
260 | if (ret < 0) |
261 | goto err_rootgt; |
262 | |
263 | i915_gem_init_early(i915: dev_priv); |
264 | |
265 | /* This must be called before any calls to HAS_PCH_* */ |
266 | intel_detect_pch(dev_priv); |
267 | |
268 | intel_irq_init(dev_priv); |
269 | intel_display_driver_early_probe(i915: dev_priv); |
270 | intel_clock_gating_hooks_init(i915: dev_priv); |
271 | |
272 | intel_detect_preproduction_hw(dev_priv); |
273 | |
274 | return 0; |
275 | |
276 | err_rootgt: |
277 | intel_region_ttm_device_fini(dev_priv); |
278 | err_ttm: |
279 | vlv_suspend_cleanup(i915: dev_priv); |
280 | err_workqueues: |
281 | i915_workqueues_cleanup(dev_priv); |
282 | return ret; |
283 | } |
284 | |
285 | /** |
286 | * i915_driver_late_release - cleanup the setup done in |
287 | * i915_driver_early_probe() |
288 | * @dev_priv: device private |
289 | */ |
290 | static void i915_driver_late_release(struct drm_i915_private *dev_priv) |
291 | { |
292 | intel_irq_fini(dev_priv); |
293 | intel_power_domains_cleanup(dev_priv); |
294 | i915_gem_cleanup_early(i915: dev_priv); |
295 | intel_gt_driver_late_release_all(i915: dev_priv); |
296 | intel_region_ttm_device_fini(dev_priv); |
297 | vlv_suspend_cleanup(i915: dev_priv); |
298 | i915_workqueues_cleanup(dev_priv); |
299 | |
300 | cpu_latency_qos_remove_request(req: &dev_priv->sb_qos); |
301 | mutex_destroy(lock: &dev_priv->sb_lock); |
302 | |
303 | i915_params_free(params: &dev_priv->params); |
304 | } |
305 | |
306 | /** |
307 | * i915_driver_mmio_probe - setup device MMIO |
308 | * @dev_priv: device private |
309 | * |
310 | * Setup minimal device state necessary for MMIO accesses later in the |
311 | * initialization sequence. The setup here should avoid any other device-wide |
312 | * side effects or exposing the driver via kernel internal or user space |
313 | * interfaces. |
314 | */ |
315 | static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) |
316 | { |
317 | struct intel_gt *gt; |
318 | int ret, i; |
319 | |
320 | if (i915_inject_probe_failure(dev_priv)) |
321 | return -ENODEV; |
322 | |
323 | ret = intel_gmch_bridge_setup(i915: dev_priv); |
324 | if (ret < 0) |
325 | return ret; |
326 | |
327 | for_each_gt(gt, dev_priv, i) { |
328 | ret = intel_uncore_init_mmio(uncore: gt->uncore); |
329 | if (ret) |
330 | return ret; |
331 | |
332 | ret = drmm_add_action_or_reset(&dev_priv->drm, |
333 | intel_uncore_fini_mmio, |
334 | gt->uncore); |
335 | if (ret) |
336 | return ret; |
337 | } |
338 | |
339 | /* Try to make sure MCHBAR is enabled before poking at it */ |
340 | intel_gmch_bar_setup(i915: dev_priv); |
341 | intel_device_info_runtime_init(dev_priv); |
342 | intel_display_device_info_runtime_init(i915: dev_priv); |
343 | |
344 | for_each_gt(gt, dev_priv, i) { |
345 | ret = intel_gt_init_mmio(gt); |
346 | if (ret) |
347 | goto err_uncore; |
348 | } |
349 | |
350 | /* As early as possible, scrub existing GPU state before clobbering */ |
351 | sanitize_gpu(i915: dev_priv); |
352 | |
353 | return 0; |
354 | |
355 | err_uncore: |
356 | intel_gmch_bar_teardown(i915: dev_priv); |
357 | |
358 | return ret; |
359 | } |
360 | |
361 | /** |
362 | * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() |
363 | * @dev_priv: device private |
364 | */ |
365 | static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) |
366 | { |
367 | intel_gmch_bar_teardown(i915: dev_priv); |
368 | } |
369 | |
370 | /** |
371 | * i915_set_dma_info - set all relevant PCI dma info as configured for the |
372 | * platform |
373 | * @i915: valid i915 instance |
374 | * |
375 | * Set the dma max segment size, device and coherent masks. The dma mask set |
376 | * needs to occur before i915_ggtt_probe_hw. |
377 | * |
378 | * A couple of platforms have special needs. Address them as well. |
379 | * |
380 | */ |
381 | static int i915_set_dma_info(struct drm_i915_private *i915) |
382 | { |
383 | unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; |
384 | int ret; |
385 | |
386 | GEM_BUG_ON(!mask_size); |
387 | |
388 | /* |
389 | * We don't have a max segment size, so set it to the max so sg's |
390 | * debugging layer doesn't complain |
391 | */ |
392 | dma_set_max_seg_size(dev: i915->drm.dev, UINT_MAX); |
393 | |
394 | ret = dma_set_mask(dev: i915->drm.dev, DMA_BIT_MASK(mask_size)); |
395 | if (ret) |
396 | goto mask_err; |
397 | |
398 | /* overlay on gen2 is broken and can't address above 1G */ |
399 | if (GRAPHICS_VER(i915) == 2) |
400 | mask_size = 30; |
401 | |
402 | /* |
403 | * 965GM sometimes incorrectly writes to hardware status page (HWS) |
404 | * using 32bit addressing, overwriting memory if HWS is located |
405 | * above 4GB. |
406 | * |
407 | * The documentation also mentions an issue with undefined |
408 | * behaviour if any general state is accessed within a page above 4GB, |
409 | * which also needs to be handled carefully. |
410 | */ |
411 | if (IS_I965G(i915) || IS_I965GM(i915)) |
412 | mask_size = 32; |
413 | |
414 | ret = dma_set_coherent_mask(dev: i915->drm.dev, DMA_BIT_MASK(mask_size)); |
415 | if (ret) |
416 | goto mask_err; |
417 | |
418 | return 0; |
419 | |
420 | mask_err: |
421 | drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n" , ret); |
422 | return ret; |
423 | } |
424 | |
425 | static int i915_pcode_init(struct drm_i915_private *i915) |
426 | { |
427 | struct intel_gt *gt; |
428 | int id, ret; |
429 | |
430 | for_each_gt(gt, i915, id) { |
431 | ret = intel_pcode_init(uncore: gt->uncore); |
432 | if (ret) { |
433 | gt_err(gt, "intel_pcode_init failed %d\n" , ret); |
434 | return ret; |
435 | } |
436 | } |
437 | |
438 | return 0; |
439 | } |
440 | |
441 | /** |
442 | * i915_driver_hw_probe - setup state requiring device access |
443 | * @dev_priv: device private |
444 | * |
445 | * Setup state that requires accessing the device, but doesn't require |
446 | * exposing the driver via kernel internal or userspace interfaces. |
447 | */ |
448 | static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) |
449 | { |
450 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
451 | int ret; |
452 | |
453 | if (i915_inject_probe_failure(dev_priv)) |
454 | return -ENODEV; |
455 | |
456 | if (HAS_PPGTT(dev_priv)) { |
457 | if (intel_vgpu_active(i915: dev_priv) && |
458 | !intel_vgpu_has_full_ppgtt(i915: dev_priv)) { |
459 | i915_report_error(dev_priv, |
460 | "incompatible vGPU found, support for isolated ppGTT required\n" ); |
461 | return -ENXIO; |
462 | } |
463 | } |
464 | |
465 | if (HAS_EXECLISTS(dev_priv)) { |
466 | /* |
467 | * Older GVT emulation depends upon intercepting CSB mmio, |
468 | * which we no longer use, preferring to use the HWSP cache |
469 | * instead. |
470 | */ |
471 | if (intel_vgpu_active(i915: dev_priv) && |
472 | !intel_vgpu_has_hwsp_emulation(i915: dev_priv)) { |
473 | i915_report_error(dev_priv, |
474 | "old vGPU host found, support for HWSP emulation required\n" ); |
475 | return -ENXIO; |
476 | } |
477 | } |
478 | |
479 | /* needs to be done before ggtt probe */ |
480 | intel_dram_edram_detect(i915: dev_priv); |
481 | |
482 | ret = i915_set_dma_info(i915: dev_priv); |
483 | if (ret) |
484 | return ret; |
485 | |
486 | ret = i915_perf_init(i915: dev_priv); |
487 | if (ret) |
488 | return ret; |
489 | |
490 | ret = i915_ggtt_probe_hw(i915: dev_priv); |
491 | if (ret) |
492 | goto err_perf; |
493 | |
494 | ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, req_driver: dev_priv->drm.driver); |
495 | if (ret) |
496 | goto err_ggtt; |
497 | |
498 | ret = i915_ggtt_init_hw(i915: dev_priv); |
499 | if (ret) |
500 | goto err_ggtt; |
501 | |
502 | /* |
503 | * Make sure we probe lmem before we probe stolen-lmem. The BAR size |
504 | * might be different due to bar resizing. |
505 | */ |
506 | ret = intel_gt_tiles_init(i915: dev_priv); |
507 | if (ret) |
508 | goto err_ggtt; |
509 | |
510 | ret = intel_memory_regions_hw_probe(i915: dev_priv); |
511 | if (ret) |
512 | goto err_ggtt; |
513 | |
514 | ret = i915_ggtt_enable_hw(i915: dev_priv); |
515 | if (ret) { |
516 | drm_err(&dev_priv->drm, "failed to enable GGTT\n" ); |
517 | goto err_mem_regions; |
518 | } |
519 | |
520 | pci_set_master(dev: pdev); |
521 | |
522 | /* On the 945G/GM, the chipset reports the MSI capability on the |
523 | * integrated graphics even though the support isn't actually there |
524 | * according to the published specs. It doesn't appear to function |
525 | * correctly in testing on 945G. |
526 | * This may be a side effect of MSI having been made available for PEG |
527 | * and the registers being closely associated. |
528 | * |
529 | * According to chipset errata, on the 965GM, MSI interrupts may |
530 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
531 | * get lost on g4x as well, and interrupt delivery seems to stay |
532 | * properly dead afterwards. So we'll just disable them for all |
533 | * pre-gen5 chipsets. |
534 | * |
535 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy |
536 | * interrupts even when in MSI mode. This results in spurious |
537 | * interrupt warnings if the legacy irq no. is shared with another |
538 | * device. The kernel then disables that interrupt source and so |
539 | * prevents the other device from working properly. |
540 | */ |
541 | if (GRAPHICS_VER(dev_priv) >= 5) { |
542 | if (pci_enable_msi(dev: pdev) < 0) |
543 | drm_dbg(&dev_priv->drm, "can't enable MSI" ); |
544 | } |
545 | |
546 | ret = intel_gvt_init(dev_priv); |
547 | if (ret) |
548 | goto err_msi; |
549 | |
550 | intel_opregion_setup(dev_priv); |
551 | |
552 | ret = i915_pcode_init(i915: dev_priv); |
553 | if (ret) |
554 | goto err_opregion; |
555 | |
556 | /* |
557 | * Fill the dram structure to get the system dram info. This will be |
558 | * used for memory latency calculation. |
559 | */ |
560 | intel_dram_detect(i915: dev_priv); |
561 | |
562 | intel_bw_init_hw(dev_priv); |
563 | |
564 | return 0; |
565 | |
566 | err_opregion: |
567 | intel_opregion_cleanup(i915: dev_priv); |
568 | err_msi: |
569 | if (pdev->msi_enabled) |
570 | pci_disable_msi(dev: pdev); |
571 | err_mem_regions: |
572 | intel_memory_regions_driver_release(i915: dev_priv); |
573 | err_ggtt: |
574 | i915_ggtt_driver_release(i915: dev_priv); |
575 | i915_gem_drain_freed_objects(i915: dev_priv); |
576 | i915_ggtt_driver_late_release(i915: dev_priv); |
577 | err_perf: |
578 | i915_perf_fini(i915: dev_priv); |
579 | return ret; |
580 | } |
581 | |
582 | /** |
583 | * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() |
584 | * @dev_priv: device private |
585 | */ |
586 | static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) |
587 | { |
588 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
589 | |
590 | i915_perf_fini(i915: dev_priv); |
591 | |
592 | intel_opregion_cleanup(i915: dev_priv); |
593 | |
594 | if (pdev->msi_enabled) |
595 | pci_disable_msi(dev: pdev); |
596 | } |
597 | |
598 | /** |
599 | * i915_driver_register - register the driver with the rest of the system |
600 | * @dev_priv: device private |
601 | * |
602 | * Perform any steps necessary to make the driver available via kernel |
603 | * internal or userspace interfaces. |
604 | */ |
605 | static void i915_driver_register(struct drm_i915_private *dev_priv) |
606 | { |
607 | struct intel_gt *gt; |
608 | unsigned int i; |
609 | |
610 | i915_gem_driver_register(i915: dev_priv); |
611 | i915_pmu_register(i915: dev_priv); |
612 | |
613 | intel_vgpu_register(i915: dev_priv); |
614 | |
615 | /* Reveal our presence to userspace */ |
616 | if (drm_dev_register(dev: &dev_priv->drm, flags: 0)) { |
617 | drm_err(&dev_priv->drm, |
618 | "Failed to register driver for userspace access!\n" ); |
619 | return; |
620 | } |
621 | |
622 | i915_debugfs_register(dev_priv); |
623 | i915_setup_sysfs(i915: dev_priv); |
624 | |
625 | /* Depends on sysfs having been initialized */ |
626 | i915_perf_register(i915: dev_priv); |
627 | |
628 | for_each_gt(gt, dev_priv, i) |
629 | intel_gt_driver_register(gt); |
630 | |
631 | intel_pxp_debugfs_register(pxp: dev_priv->pxp); |
632 | |
633 | i915_hwmon_register(i915: dev_priv); |
634 | |
635 | intel_display_driver_register(i915: dev_priv); |
636 | |
637 | intel_power_domains_enable(dev_priv); |
638 | intel_runtime_pm_enable(rpm: &dev_priv->runtime_pm); |
639 | |
640 | intel_register_dsm_handler(); |
641 | |
642 | if (i915_switcheroo_register(i915: dev_priv)) |
643 | drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n" ); |
644 | } |
645 | |
646 | /** |
647 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() |
648 | * @dev_priv: device private |
649 | */ |
650 | static void i915_driver_unregister(struct drm_i915_private *dev_priv) |
651 | { |
652 | struct intel_gt *gt; |
653 | unsigned int i; |
654 | |
655 | i915_switcheroo_unregister(i915: dev_priv); |
656 | |
657 | intel_unregister_dsm_handler(); |
658 | |
659 | intel_runtime_pm_disable(rpm: &dev_priv->runtime_pm); |
660 | intel_power_domains_disable(dev_priv); |
661 | |
662 | intel_display_driver_unregister(i915: dev_priv); |
663 | |
664 | intel_pxp_fini(i915: dev_priv); |
665 | |
666 | for_each_gt(gt, dev_priv, i) |
667 | intel_gt_driver_unregister(gt); |
668 | |
669 | i915_hwmon_unregister(i915: dev_priv); |
670 | |
671 | i915_perf_unregister(i915: dev_priv); |
672 | i915_pmu_unregister(i915: dev_priv); |
673 | |
674 | i915_teardown_sysfs(i915: dev_priv); |
675 | drm_dev_unplug(dev: &dev_priv->drm); |
676 | |
677 | i915_gem_driver_unregister(i915: dev_priv); |
678 | } |
679 | |
680 | void |
681 | i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) |
682 | { |
683 | drm_printf(p, f: "iommu: %s\n" , |
684 | str_enabled_disabled(v: i915_vtd_active(i915))); |
685 | } |
686 | |
687 | static void i915_welcome_messages(struct drm_i915_private *dev_priv) |
688 | { |
689 | if (drm_debug_enabled(DRM_UT_DRIVER)) { |
690 | struct drm_printer p = drm_debug_printer(prefix: "i915 device info:" ); |
691 | struct intel_gt *gt; |
692 | unsigned int i; |
693 | |
694 | drm_printf(p: &p, f: "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n" , |
695 | INTEL_DEVID(dev_priv), |
696 | INTEL_REVID(dev_priv), |
697 | intel_platform_name(INTEL_INFO(dev_priv)->platform), |
698 | intel_subplatform(RUNTIME_INFO(dev_priv), |
699 | INTEL_INFO(dev_priv)->platform), |
700 | GRAPHICS_VER(dev_priv)); |
701 | |
702 | intel_device_info_print(INTEL_INFO(dev_priv), |
703 | RUNTIME_INFO(dev_priv), p: &p); |
704 | i915_print_iommu_status(i915: dev_priv, p: &p); |
705 | for_each_gt(gt, dev_priv, i) |
706 | intel_gt_info_print(info: >->info, p: &p); |
707 | } |
708 | |
709 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) |
710 | drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n" ); |
711 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) |
712 | drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n" ); |
713 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) |
714 | drm_info(&dev_priv->drm, |
715 | "DRM_I915_DEBUG_RUNTIME_PM enabled\n" ); |
716 | } |
717 | |
718 | static struct drm_i915_private * |
719 | i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) |
720 | { |
721 | const struct intel_device_info *match_info = |
722 | (struct intel_device_info *)ent->driver_data; |
723 | struct drm_i915_private *i915; |
724 | |
725 | i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, |
726 | struct drm_i915_private, drm); |
727 | if (IS_ERR(ptr: i915)) |
728 | return i915; |
729 | |
730 | pci_set_drvdata(pdev, data: i915); |
731 | |
732 | /* Device parameters start as a copy of module parameters. */ |
733 | i915_params_copy(dest: &i915->params, src: &i915_modparams); |
734 | |
735 | /* Set up device info and initial runtime info. */ |
736 | intel_device_info_driver_create(i915, device_id: pdev->device, match_info); |
737 | |
738 | intel_display_device_probe(i915); |
739 | |
740 | return i915; |
741 | } |
742 | |
743 | /** |
744 | * i915_driver_probe - setup chip and create an initial config |
745 | * @pdev: PCI device |
746 | * @ent: matching PCI ID entry |
747 | * |
748 | * The driver probe routine has to do several things: |
749 | * - drive output discovery via intel_display_driver_probe() |
750 | * - initialize the memory manager |
751 | * - allocate initial config memory |
752 | * - setup the DRM framebuffer with the allocated memory |
753 | */ |
754 | int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
755 | { |
756 | struct drm_i915_private *i915; |
757 | int ret; |
758 | |
759 | ret = pci_enable_device(dev: pdev); |
760 | if (ret) { |
761 | pr_err("Failed to enable graphics device: %pe\n" , ERR_PTR(ret)); |
762 | return ret; |
763 | } |
764 | |
765 | i915 = i915_driver_create(pdev, ent); |
766 | if (IS_ERR(ptr: i915)) { |
767 | pci_disable_device(dev: pdev); |
768 | return PTR_ERR(ptr: i915); |
769 | } |
770 | |
771 | ret = i915_driver_early_probe(dev_priv: i915); |
772 | if (ret < 0) |
773 | goto out_pci_disable; |
774 | |
775 | disable_rpm_wakeref_asserts(rpm: &i915->runtime_pm); |
776 | |
777 | intel_vgpu_detect(i915); |
778 | |
779 | ret = intel_gt_probe_all(i915); |
780 | if (ret < 0) |
781 | goto out_runtime_pm_put; |
782 | |
783 | ret = i915_driver_mmio_probe(dev_priv: i915); |
784 | if (ret < 0) |
785 | goto out_tiles_cleanup; |
786 | |
787 | ret = i915_driver_hw_probe(dev_priv: i915); |
788 | if (ret < 0) |
789 | goto out_cleanup_mmio; |
790 | |
791 | ret = intel_display_driver_probe_noirq(i915); |
792 | if (ret < 0) |
793 | goto out_cleanup_hw; |
794 | |
795 | ret = intel_irq_install(dev_priv: i915); |
796 | if (ret) |
797 | goto out_cleanup_modeset; |
798 | |
799 | ret = intel_display_driver_probe_nogem(i915); |
800 | if (ret) |
801 | goto out_cleanup_irq; |
802 | |
803 | ret = i915_gem_init(i915); |
804 | if (ret) |
805 | goto out_cleanup_modeset2; |
806 | |
807 | intel_pxp_init(i915); |
808 | |
809 | ret = intel_display_driver_probe(i915); |
810 | if (ret) |
811 | goto out_cleanup_gem; |
812 | |
813 | i915_driver_register(dev_priv: i915); |
814 | |
815 | enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm); |
816 | |
817 | i915_welcome_messages(dev_priv: i915); |
818 | |
819 | i915->do_release = true; |
820 | |
821 | return 0; |
822 | |
823 | out_cleanup_gem: |
824 | i915_gem_suspend(i915); |
825 | i915_gem_driver_remove(i915); |
826 | i915_gem_driver_release(i915); |
827 | out_cleanup_modeset2: |
828 | /* FIXME clean up the error path */ |
829 | intel_display_driver_remove(i915); |
830 | intel_irq_uninstall(dev_priv: i915); |
831 | intel_display_driver_remove_noirq(i915); |
832 | goto out_cleanup_modeset; |
833 | out_cleanup_irq: |
834 | intel_irq_uninstall(dev_priv: i915); |
835 | out_cleanup_modeset: |
836 | intel_display_driver_remove_nogem(i915); |
837 | out_cleanup_hw: |
838 | i915_driver_hw_remove(dev_priv: i915); |
839 | intel_memory_regions_driver_release(i915); |
840 | i915_ggtt_driver_release(i915); |
841 | i915_gem_drain_freed_objects(i915); |
842 | i915_ggtt_driver_late_release(i915); |
843 | out_cleanup_mmio: |
844 | i915_driver_mmio_release(dev_priv: i915); |
845 | out_tiles_cleanup: |
846 | intel_gt_release_all(i915); |
847 | out_runtime_pm_put: |
848 | enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm); |
849 | i915_driver_late_release(dev_priv: i915); |
850 | out_pci_disable: |
851 | pci_disable_device(dev: pdev); |
852 | i915_probe_error(i915, "Device initialization failed (%d)\n" , ret); |
853 | return ret; |
854 | } |
855 | |
856 | void i915_driver_remove(struct drm_i915_private *i915) |
857 | { |
858 | intel_wakeref_t wakeref; |
859 | |
860 | wakeref = intel_runtime_pm_get(rpm: &i915->runtime_pm); |
861 | |
862 | i915_driver_unregister(dev_priv: i915); |
863 | |
864 | /* Flush any external code that still may be under the RCU lock */ |
865 | synchronize_rcu(); |
866 | |
867 | i915_gem_suspend(i915); |
868 | |
869 | intel_gvt_driver_remove(dev_priv: i915); |
870 | |
871 | intel_display_driver_remove(i915); |
872 | |
873 | intel_irq_uninstall(dev_priv: i915); |
874 | |
875 | intel_display_driver_remove_noirq(i915); |
876 | |
877 | i915_reset_error_state(i915); |
878 | i915_gem_driver_remove(i915); |
879 | |
880 | intel_display_driver_remove_nogem(i915); |
881 | |
882 | i915_driver_hw_remove(dev_priv: i915); |
883 | |
884 | intel_runtime_pm_put(rpm: &i915->runtime_pm, wref: wakeref); |
885 | } |
886 | |
887 | static void i915_driver_release(struct drm_device *dev) |
888 | { |
889 | struct drm_i915_private *dev_priv = to_i915(dev); |
890 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
891 | intel_wakeref_t wakeref; |
892 | |
893 | if (!dev_priv->do_release) |
894 | return; |
895 | |
896 | wakeref = intel_runtime_pm_get(rpm); |
897 | |
898 | i915_gem_driver_release(i915: dev_priv); |
899 | |
900 | intel_memory_regions_driver_release(i915: dev_priv); |
901 | i915_ggtt_driver_release(i915: dev_priv); |
902 | i915_gem_drain_freed_objects(i915: dev_priv); |
903 | i915_ggtt_driver_late_release(i915: dev_priv); |
904 | |
905 | i915_driver_mmio_release(dev_priv); |
906 | |
907 | intel_runtime_pm_put(rpm, wref: wakeref); |
908 | |
909 | intel_runtime_pm_driver_release(rpm); |
910 | |
911 | i915_driver_late_release(dev_priv); |
912 | } |
913 | |
914 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
915 | { |
916 | struct drm_i915_private *i915 = to_i915(dev); |
917 | int ret; |
918 | |
919 | ret = i915_gem_open(i915, file); |
920 | if (ret) |
921 | return ret; |
922 | |
923 | return 0; |
924 | } |
925 | |
926 | /** |
927 | * i915_driver_lastclose - clean up after all DRM clients have exited |
928 | * @dev: DRM device |
929 | * |
930 | * Take care of cleaning up after all DRM clients have exited. In the |
931 | * mode setting case, we want to restore the kernel's initial mode (just |
932 | * in case the last client left us in a bad state). |
933 | * |
934 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
935 | * and DMA structures, since the kernel won't be using them, and clea |
936 | * up any GEM state. |
937 | */ |
938 | static void i915_driver_lastclose(struct drm_device *dev) |
939 | { |
940 | struct drm_i915_private *i915 = to_i915(dev); |
941 | |
942 | intel_fbdev_restore_mode(dev_priv: i915); |
943 | |
944 | vga_switcheroo_process_delayed_switch(); |
945 | } |
946 | |
947 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
948 | { |
949 | struct drm_i915_file_private *file_priv = file->driver_priv; |
950 | |
951 | i915_gem_context_close(file); |
952 | i915_drm_client_put(client: file_priv->client); |
953 | |
954 | kfree_rcu(file_priv, rcu); |
955 | |
956 | /* Catch up with all the deferred frees from "this" client */ |
957 | i915_gem_flush_free_objects(i915: to_i915(dev)); |
958 | } |
959 | |
960 | static void intel_suspend_encoders(struct drm_i915_private *dev_priv) |
961 | { |
962 | struct intel_encoder *encoder; |
963 | |
964 | if (!HAS_DISPLAY(dev_priv)) |
965 | return; |
966 | |
967 | /* |
968 | * TODO: check and remove holding the modeset locks if none of |
969 | * the encoders depends on this. |
970 | */ |
971 | drm_modeset_lock_all(dev: &dev_priv->drm); |
972 | for_each_intel_encoder(&dev_priv->drm, encoder) |
973 | if (encoder->suspend) |
974 | encoder->suspend(encoder); |
975 | drm_modeset_unlock_all(dev: &dev_priv->drm); |
976 | |
977 | for_each_intel_encoder(&dev_priv->drm, encoder) |
978 | if (encoder->suspend_complete) |
979 | encoder->suspend_complete(encoder); |
980 | } |
981 | |
982 | static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) |
983 | { |
984 | struct intel_encoder *encoder; |
985 | |
986 | if (!HAS_DISPLAY(dev_priv)) |
987 | return; |
988 | |
989 | /* |
990 | * TODO: check and remove holding the modeset locks if none of |
991 | * the encoders depends on this. |
992 | */ |
993 | drm_modeset_lock_all(dev: &dev_priv->drm); |
994 | for_each_intel_encoder(&dev_priv->drm, encoder) |
995 | if (encoder->shutdown) |
996 | encoder->shutdown(encoder); |
997 | drm_modeset_unlock_all(dev: &dev_priv->drm); |
998 | |
999 | for_each_intel_encoder(&dev_priv->drm, encoder) |
1000 | if (encoder->shutdown_complete) |
1001 | encoder->shutdown_complete(encoder); |
1002 | } |
1003 | |
1004 | void i915_driver_shutdown(struct drm_i915_private *i915) |
1005 | { |
1006 | disable_rpm_wakeref_asserts(rpm: &i915->runtime_pm); |
1007 | intel_runtime_pm_disable(rpm: &i915->runtime_pm); |
1008 | intel_power_domains_disable(dev_priv: i915); |
1009 | |
1010 | if (HAS_DISPLAY(i915)) { |
1011 | drm_kms_helper_poll_disable(dev: &i915->drm); |
1012 | |
1013 | drm_atomic_helper_shutdown(dev: &i915->drm); |
1014 | } |
1015 | |
1016 | intel_dp_mst_suspend(dev_priv: i915); |
1017 | |
1018 | intel_runtime_pm_disable_interrupts(dev_priv: i915); |
1019 | intel_hpd_cancel_work(dev_priv: i915); |
1020 | |
1021 | intel_suspend_encoders(dev_priv: i915); |
1022 | intel_shutdown_encoders(dev_priv: i915); |
1023 | |
1024 | intel_dmc_suspend(i915); |
1025 | |
1026 | i915_gem_suspend(i915); |
1027 | |
1028 | /* |
1029 | * The only requirement is to reboot with display DC states disabled, |
1030 | * for now leaving all display power wells in the INIT power domain |
1031 | * enabled. |
1032 | * |
1033 | * TODO: |
1034 | * - unify the pci_driver::shutdown sequence here with the |
1035 | * pci_driver.driver.pm.poweroff,poweroff_late sequence. |
1036 | * - unify the driver remove and system/runtime suspend sequences with |
1037 | * the above unified shutdown/poweroff sequence. |
1038 | */ |
1039 | intel_power_domains_driver_remove(dev_priv: i915); |
1040 | enable_rpm_wakeref_asserts(rpm: &i915->runtime_pm); |
1041 | |
1042 | intel_runtime_pm_driver_release(rpm: &i915->runtime_pm); |
1043 | } |
1044 | |
1045 | static bool suspend_to_idle(struct drm_i915_private *dev_priv) |
1046 | { |
1047 | #if IS_ENABLED(CONFIG_ACPI_SLEEP) |
1048 | if (acpi_target_system_state() < ACPI_STATE_S3) |
1049 | return true; |
1050 | #endif |
1051 | return false; |
1052 | } |
1053 | |
1054 | static void i915_drm_complete(struct drm_device *dev) |
1055 | { |
1056 | struct drm_i915_private *i915 = to_i915(dev); |
1057 | |
1058 | intel_pxp_resume_complete(pxp: i915->pxp); |
1059 | } |
1060 | |
1061 | static int i915_drm_prepare(struct drm_device *dev) |
1062 | { |
1063 | struct drm_i915_private *i915 = to_i915(dev); |
1064 | |
1065 | intel_pxp_suspend_prepare(pxp: i915->pxp); |
1066 | |
1067 | /* |
1068 | * NB intel_display_driver_suspend() may issue new requests after we've |
1069 | * ostensibly marked the GPU as ready-to-sleep here. We need to |
1070 | * split out that work and pull it forward so that after point, |
1071 | * the GPU is not woken again. |
1072 | */ |
1073 | return i915_gem_backup_suspend(i915); |
1074 | } |
1075 | |
1076 | static int i915_drm_suspend(struct drm_device *dev) |
1077 | { |
1078 | struct drm_i915_private *dev_priv = to_i915(dev); |
1079 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1080 | pci_power_t opregion_target_state; |
1081 | |
1082 | disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1083 | |
1084 | /* We do a lot of poking in a lot of registers, make sure they work |
1085 | * properly. */ |
1086 | intel_power_domains_disable(dev_priv); |
1087 | if (HAS_DISPLAY(dev_priv)) |
1088 | drm_kms_helper_poll_disable(dev); |
1089 | |
1090 | pci_save_state(dev: pdev); |
1091 | |
1092 | intel_display_driver_suspend(i915: dev_priv); |
1093 | |
1094 | intel_dp_mst_suspend(dev_priv); |
1095 | |
1096 | intel_runtime_pm_disable_interrupts(dev_priv); |
1097 | intel_hpd_cancel_work(dev_priv); |
1098 | |
1099 | intel_suspend_encoders(dev_priv); |
1100 | |
1101 | /* Must be called before GGTT is suspended. */ |
1102 | intel_dpt_suspend(i915: dev_priv); |
1103 | i915_ggtt_suspend(gtt: to_gt(i915: dev_priv)->ggtt); |
1104 | |
1105 | i915_save_display(i915: dev_priv); |
1106 | |
1107 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
1108 | intel_opregion_suspend(dev_priv, state: opregion_target_state); |
1109 | |
1110 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, synchronous: true); |
1111 | |
1112 | dev_priv->suspend_count++; |
1113 | |
1114 | intel_dmc_suspend(i915: dev_priv); |
1115 | |
1116 | enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1117 | |
1118 | i915_gem_drain_freed_objects(i915: dev_priv); |
1119 | |
1120 | return 0; |
1121 | } |
1122 | |
1123 | static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) |
1124 | { |
1125 | struct drm_i915_private *dev_priv = to_i915(dev); |
1126 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1127 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1128 | struct intel_gt *gt; |
1129 | int ret, i; |
1130 | bool s2idle = !hibernation && suspend_to_idle(dev_priv); |
1131 | |
1132 | disable_rpm_wakeref_asserts(rpm); |
1133 | |
1134 | intel_pxp_suspend(pxp: dev_priv->pxp); |
1135 | |
1136 | i915_gem_suspend_late(i915: dev_priv); |
1137 | |
1138 | for_each_gt(gt, dev_priv, i) |
1139 | intel_uncore_suspend(uncore: gt->uncore); |
1140 | |
1141 | intel_power_domains_suspend(dev_priv, s2idle); |
1142 | |
1143 | intel_display_power_suspend_late(i915: dev_priv); |
1144 | |
1145 | ret = vlv_suspend_complete(i915: dev_priv); |
1146 | if (ret) { |
1147 | drm_err(&dev_priv->drm, "Suspend complete failed: %d\n" , ret); |
1148 | intel_power_domains_resume(dev_priv); |
1149 | |
1150 | goto out; |
1151 | } |
1152 | |
1153 | pci_disable_device(dev: pdev); |
1154 | /* |
1155 | * During hibernation on some platforms the BIOS may try to access |
1156 | * the device even though it's already in D3 and hang the machine. So |
1157 | * leave the device in D0 on those platforms and hope the BIOS will |
1158 | * power down the device properly. The issue was seen on multiple old |
1159 | * GENs with different BIOS vendors, so having an explicit blacklist |
1160 | * is inpractical; apply the workaround on everything pre GEN6. The |
1161 | * platforms where the issue was seen: |
1162 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 |
1163 | * Fujitsu FSC S7110 |
1164 | * Acer Aspire 1830T |
1165 | */ |
1166 | if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) |
1167 | pci_set_power_state(dev: pdev, PCI_D3hot); |
1168 | |
1169 | out: |
1170 | enable_rpm_wakeref_asserts(rpm); |
1171 | if (!dev_priv->uncore.user_forcewake_count) |
1172 | intel_runtime_pm_driver_release(rpm); |
1173 | |
1174 | return ret; |
1175 | } |
1176 | |
1177 | int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, |
1178 | pm_message_t state) |
1179 | { |
1180 | int error; |
1181 | |
1182 | if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && |
1183 | state.event != PM_EVENT_FREEZE)) |
1184 | return -EINVAL; |
1185 | |
1186 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1187 | return 0; |
1188 | |
1189 | error = i915_drm_suspend(dev: &i915->drm); |
1190 | if (error) |
1191 | return error; |
1192 | |
1193 | return i915_drm_suspend_late(dev: &i915->drm, hibernation: false); |
1194 | } |
1195 | |
1196 | static int i915_drm_resume(struct drm_device *dev) |
1197 | { |
1198 | struct drm_i915_private *dev_priv = to_i915(dev); |
1199 | struct intel_gt *gt; |
1200 | int ret, i; |
1201 | |
1202 | disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1203 | |
1204 | ret = i915_pcode_init(i915: dev_priv); |
1205 | if (ret) |
1206 | return ret; |
1207 | |
1208 | sanitize_gpu(i915: dev_priv); |
1209 | |
1210 | ret = i915_ggtt_enable_hw(i915: dev_priv); |
1211 | if (ret) |
1212 | drm_err(&dev_priv->drm, "failed to re-enable GGTT\n" ); |
1213 | |
1214 | i915_ggtt_resume(ggtt: to_gt(i915: dev_priv)->ggtt); |
1215 | |
1216 | for_each_gt(gt, dev_priv, i) |
1217 | if (GRAPHICS_VER(gt->i915) >= 8) |
1218 | setup_private_pat(gt); |
1219 | |
1220 | /* Must be called after GGTT is resumed. */ |
1221 | intel_dpt_resume(i915: dev_priv); |
1222 | |
1223 | intel_dmc_resume(i915: dev_priv); |
1224 | |
1225 | i915_restore_display(i915: dev_priv); |
1226 | intel_pps_unlock_regs_wa(i915: dev_priv); |
1227 | |
1228 | intel_init_pch_refclk(dev_priv); |
1229 | |
1230 | /* |
1231 | * Interrupts have to be enabled before any batches are run. If not the |
1232 | * GPU will hang. i915_gem_init_hw() will initiate batches to |
1233 | * update/restore the context. |
1234 | * |
1235 | * drm_mode_config_reset() needs AUX interrupts. |
1236 | * |
1237 | * Modeset enabling in intel_display_driver_init_hw() also needs working |
1238 | * interrupts. |
1239 | */ |
1240 | intel_runtime_pm_enable_interrupts(dev_priv); |
1241 | |
1242 | if (HAS_DISPLAY(dev_priv)) |
1243 | drm_mode_config_reset(dev); |
1244 | |
1245 | i915_gem_resume(i915: dev_priv); |
1246 | |
1247 | intel_display_driver_init_hw(i915: dev_priv); |
1248 | |
1249 | intel_clock_gating_init(i915: dev_priv); |
1250 | intel_hpd_init(dev_priv); |
1251 | |
1252 | /* MST sideband requires HPD interrupts enabled */ |
1253 | intel_dp_mst_resume(dev_priv); |
1254 | intel_display_driver_resume(i915: dev_priv); |
1255 | |
1256 | intel_hpd_poll_disable(dev_priv); |
1257 | if (HAS_DISPLAY(dev_priv)) |
1258 | drm_kms_helper_poll_enable(dev); |
1259 | |
1260 | intel_opregion_resume(dev_priv); |
1261 | |
1262 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, synchronous: false); |
1263 | |
1264 | intel_power_domains_enable(dev_priv); |
1265 | |
1266 | intel_gvt_resume(dev_priv); |
1267 | |
1268 | enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1269 | |
1270 | return 0; |
1271 | } |
1272 | |
1273 | static int i915_drm_resume_early(struct drm_device *dev) |
1274 | { |
1275 | struct drm_i915_private *dev_priv = to_i915(dev); |
1276 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1277 | struct intel_gt *gt; |
1278 | int ret, i; |
1279 | |
1280 | /* |
1281 | * We have a resume ordering issue with the snd-hda driver also |
1282 | * requiring our device to be power up. Due to the lack of a |
1283 | * parent/child relationship we currently solve this with an early |
1284 | * resume hook. |
1285 | * |
1286 | * FIXME: This should be solved with a special hdmi sink device or |
1287 | * similar so that power domains can be employed. |
1288 | */ |
1289 | |
1290 | /* |
1291 | * Note that we need to set the power state explicitly, since we |
1292 | * powered off the device during freeze and the PCI core won't power |
1293 | * it back up for us during thaw. Powering off the device during |
1294 | * freeze is not a hard requirement though, and during the |
1295 | * suspend/resume phases the PCI core makes sure we get here with the |
1296 | * device powered on. So in case we change our freeze logic and keep |
1297 | * the device powered we can also remove the following set power state |
1298 | * call. |
1299 | */ |
1300 | ret = pci_set_power_state(dev: pdev, PCI_D0); |
1301 | if (ret) { |
1302 | drm_err(&dev_priv->drm, |
1303 | "failed to set PCI D0 power state (%d)\n" , ret); |
1304 | return ret; |
1305 | } |
1306 | |
1307 | /* |
1308 | * Note that pci_enable_device() first enables any parent bridge |
1309 | * device and only then sets the power state for this device. The |
1310 | * bridge enabling is a nop though, since bridge devices are resumed |
1311 | * first. The order of enabling power and enabling the device is |
1312 | * imposed by the PCI core as described above, so here we preserve the |
1313 | * same order for the freeze/thaw phases. |
1314 | * |
1315 | * TODO: eventually we should remove pci_disable_device() / |
1316 | * pci_enable_enable_device() from suspend/resume. Due to how they |
1317 | * depend on the device enable refcount we can't anyway depend on them |
1318 | * disabling/enabling the device. |
1319 | */ |
1320 | if (pci_enable_device(dev: pdev)) |
1321 | return -EIO; |
1322 | |
1323 | pci_set_master(dev: pdev); |
1324 | |
1325 | disable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1326 | |
1327 | ret = vlv_resume_prepare(i915: dev_priv, rpm_resume: false); |
1328 | if (ret) |
1329 | drm_err(&dev_priv->drm, |
1330 | "Resume prepare failed: %d, continuing anyway\n" , ret); |
1331 | |
1332 | for_each_gt(gt, dev_priv, i) |
1333 | intel_gt_resume_early(gt); |
1334 | |
1335 | intel_display_power_resume_early(i915: dev_priv); |
1336 | |
1337 | intel_power_domains_resume(dev_priv); |
1338 | |
1339 | enable_rpm_wakeref_asserts(rpm: &dev_priv->runtime_pm); |
1340 | |
1341 | return ret; |
1342 | } |
1343 | |
1344 | int i915_driver_resume_switcheroo(struct drm_i915_private *i915) |
1345 | { |
1346 | int ret; |
1347 | |
1348 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1349 | return 0; |
1350 | |
1351 | ret = i915_drm_resume_early(dev: &i915->drm); |
1352 | if (ret) |
1353 | return ret; |
1354 | |
1355 | return i915_drm_resume(dev: &i915->drm); |
1356 | } |
1357 | |
1358 | static int i915_pm_prepare(struct device *kdev) |
1359 | { |
1360 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1361 | |
1362 | if (!i915) { |
1363 | dev_err(kdev, "DRM not initialized, aborting suspend.\n" ); |
1364 | return -ENODEV; |
1365 | } |
1366 | |
1367 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1368 | return 0; |
1369 | |
1370 | return i915_drm_prepare(dev: &i915->drm); |
1371 | } |
1372 | |
1373 | static int i915_pm_suspend(struct device *kdev) |
1374 | { |
1375 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1376 | |
1377 | if (!i915) { |
1378 | dev_err(kdev, "DRM not initialized, aborting suspend.\n" ); |
1379 | return -ENODEV; |
1380 | } |
1381 | |
1382 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1383 | return 0; |
1384 | |
1385 | return i915_drm_suspend(dev: &i915->drm); |
1386 | } |
1387 | |
1388 | static int i915_pm_suspend_late(struct device *kdev) |
1389 | { |
1390 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1391 | |
1392 | /* |
1393 | * We have a suspend ordering issue with the snd-hda driver also |
1394 | * requiring our device to be power up. Due to the lack of a |
1395 | * parent/child relationship we currently solve this with an late |
1396 | * suspend hook. |
1397 | * |
1398 | * FIXME: This should be solved with a special hdmi sink device or |
1399 | * similar so that power domains can be employed. |
1400 | */ |
1401 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1402 | return 0; |
1403 | |
1404 | return i915_drm_suspend_late(dev: &i915->drm, hibernation: false); |
1405 | } |
1406 | |
1407 | static int i915_pm_poweroff_late(struct device *kdev) |
1408 | { |
1409 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1410 | |
1411 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1412 | return 0; |
1413 | |
1414 | return i915_drm_suspend_late(dev: &i915->drm, hibernation: true); |
1415 | } |
1416 | |
1417 | static int i915_pm_resume_early(struct device *kdev) |
1418 | { |
1419 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1420 | |
1421 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1422 | return 0; |
1423 | |
1424 | return i915_drm_resume_early(dev: &i915->drm); |
1425 | } |
1426 | |
1427 | static int i915_pm_resume(struct device *kdev) |
1428 | { |
1429 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1430 | |
1431 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1432 | return 0; |
1433 | |
1434 | return i915_drm_resume(dev: &i915->drm); |
1435 | } |
1436 | |
1437 | static void i915_pm_complete(struct device *kdev) |
1438 | { |
1439 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1440 | |
1441 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1442 | return; |
1443 | |
1444 | i915_drm_complete(dev: &i915->drm); |
1445 | } |
1446 | |
1447 | /* freeze: before creating the hibernation_image */ |
1448 | static int i915_pm_freeze(struct device *kdev) |
1449 | { |
1450 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1451 | int ret; |
1452 | |
1453 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
1454 | ret = i915_drm_suspend(dev: &i915->drm); |
1455 | if (ret) |
1456 | return ret; |
1457 | } |
1458 | |
1459 | ret = i915_gem_freeze(i915); |
1460 | if (ret) |
1461 | return ret; |
1462 | |
1463 | return 0; |
1464 | } |
1465 | |
1466 | static int i915_pm_freeze_late(struct device *kdev) |
1467 | { |
1468 | struct drm_i915_private *i915 = kdev_to_i915(kdev); |
1469 | int ret; |
1470 | |
1471 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
1472 | ret = i915_drm_suspend_late(dev: &i915->drm, hibernation: true); |
1473 | if (ret) |
1474 | return ret; |
1475 | } |
1476 | |
1477 | ret = i915_gem_freeze_late(i915); |
1478 | if (ret) |
1479 | return ret; |
1480 | |
1481 | return 0; |
1482 | } |
1483 | |
1484 | /* thaw: called after creating the hibernation image, but before turning off. */ |
1485 | static int i915_pm_thaw_early(struct device *kdev) |
1486 | { |
1487 | return i915_pm_resume_early(kdev); |
1488 | } |
1489 | |
1490 | static int i915_pm_thaw(struct device *kdev) |
1491 | { |
1492 | return i915_pm_resume(kdev); |
1493 | } |
1494 | |
1495 | /* restore: called after loading the hibernation image. */ |
1496 | static int i915_pm_restore_early(struct device *kdev) |
1497 | { |
1498 | return i915_pm_resume_early(kdev); |
1499 | } |
1500 | |
1501 | static int i915_pm_restore(struct device *kdev) |
1502 | { |
1503 | return i915_pm_resume(kdev); |
1504 | } |
1505 | |
1506 | static int intel_runtime_suspend(struct device *kdev) |
1507 | { |
1508 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
1509 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1510 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1511 | struct pci_dev *root_pdev; |
1512 | struct intel_gt *gt; |
1513 | int ret, i; |
1514 | |
1515 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) |
1516 | return -ENODEV; |
1517 | |
1518 | drm_dbg(&dev_priv->drm, "Suspending device\n" ); |
1519 | |
1520 | disable_rpm_wakeref_asserts(rpm); |
1521 | |
1522 | /* |
1523 | * We are safe here against re-faults, since the fault handler takes |
1524 | * an RPM reference. |
1525 | */ |
1526 | i915_gem_runtime_suspend(i915: dev_priv); |
1527 | |
1528 | intel_pxp_runtime_suspend(pxp: dev_priv->pxp); |
1529 | |
1530 | for_each_gt(gt, dev_priv, i) |
1531 | intel_gt_runtime_suspend(gt); |
1532 | |
1533 | intel_runtime_pm_disable_interrupts(dev_priv); |
1534 | |
1535 | for_each_gt(gt, dev_priv, i) |
1536 | intel_uncore_suspend(uncore: gt->uncore); |
1537 | |
1538 | intel_display_power_suspend(i915: dev_priv); |
1539 | |
1540 | ret = vlv_suspend_complete(i915: dev_priv); |
1541 | if (ret) { |
1542 | drm_err(&dev_priv->drm, |
1543 | "Runtime suspend failed, disabling it (%d)\n" , ret); |
1544 | intel_uncore_runtime_resume(uncore: &dev_priv->uncore); |
1545 | |
1546 | intel_runtime_pm_enable_interrupts(dev_priv); |
1547 | |
1548 | for_each_gt(gt, dev_priv, i) |
1549 | intel_gt_runtime_resume(gt); |
1550 | |
1551 | enable_rpm_wakeref_asserts(rpm); |
1552 | |
1553 | return ret; |
1554 | } |
1555 | |
1556 | enable_rpm_wakeref_asserts(rpm); |
1557 | intel_runtime_pm_driver_release(rpm); |
1558 | |
1559 | if (intel_uncore_arm_unclaimed_mmio_detection(uncore: &dev_priv->uncore)) |
1560 | drm_err(&dev_priv->drm, |
1561 | "Unclaimed access detected prior to suspending\n" ); |
1562 | |
1563 | /* |
1564 | * FIXME: Temporary hammer to avoid freezing the machine on our DGFX |
1565 | * This should be totally removed when we handle the pci states properly |
1566 | * on runtime PM. |
1567 | */ |
1568 | root_pdev = pcie_find_root_port(dev: pdev); |
1569 | if (root_pdev) |
1570 | pci_d3cold_disable(dev: root_pdev); |
1571 | |
1572 | /* |
1573 | * FIXME: We really should find a document that references the arguments |
1574 | * used below! |
1575 | */ |
1576 | if (IS_BROADWELL(dev_priv)) { |
1577 | /* |
1578 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop |
1579 | * being detected, and the call we do at intel_runtime_resume() |
1580 | * won't be able to restore them. Since PCI_D3hot matches the |
1581 | * actual specification and appears to be working, use it. |
1582 | */ |
1583 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
1584 | } else { |
1585 | /* |
1586 | * current versions of firmware which depend on this opregion |
1587 | * notification have repurposed the D1 definition to mean |
1588 | * "runtime suspended" vs. what you would normally expect (D3) |
1589 | * to distinguish it from notifications that might be sent via |
1590 | * the suspend path. |
1591 | */ |
1592 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
1593 | } |
1594 | |
1595 | assert_forcewakes_inactive(uncore: &dev_priv->uncore); |
1596 | |
1597 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
1598 | intel_hpd_poll_enable(dev_priv); |
1599 | |
1600 | drm_dbg(&dev_priv->drm, "Device suspended\n" ); |
1601 | return 0; |
1602 | } |
1603 | |
1604 | static int intel_runtime_resume(struct device *kdev) |
1605 | { |
1606 | struct drm_i915_private *dev_priv = kdev_to_i915(kdev); |
1607 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1608 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1609 | struct pci_dev *root_pdev; |
1610 | struct intel_gt *gt; |
1611 | int ret, i; |
1612 | |
1613 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) |
1614 | return -ENODEV; |
1615 | |
1616 | drm_dbg(&dev_priv->drm, "Resuming device\n" ); |
1617 | |
1618 | drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); |
1619 | disable_rpm_wakeref_asserts(rpm); |
1620 | |
1621 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
1622 | |
1623 | root_pdev = pcie_find_root_port(dev: pdev); |
1624 | if (root_pdev) |
1625 | pci_d3cold_enable(dev: root_pdev); |
1626 | |
1627 | if (intel_uncore_unclaimed_mmio(uncore: &dev_priv->uncore)) |
1628 | drm_dbg(&dev_priv->drm, |
1629 | "Unclaimed access during suspend, bios?\n" ); |
1630 | |
1631 | intel_display_power_resume(i915: dev_priv); |
1632 | |
1633 | ret = vlv_resume_prepare(i915: dev_priv, rpm_resume: true); |
1634 | |
1635 | for_each_gt(gt, dev_priv, i) |
1636 | intel_uncore_runtime_resume(uncore: gt->uncore); |
1637 | |
1638 | intel_runtime_pm_enable_interrupts(dev_priv); |
1639 | |
1640 | /* |
1641 | * No point of rolling back things in case of an error, as the best |
1642 | * we can do is to hope that things will still work (and disable RPM). |
1643 | */ |
1644 | for_each_gt(gt, dev_priv, i) |
1645 | intel_gt_runtime_resume(gt); |
1646 | |
1647 | intel_pxp_runtime_resume(pxp: dev_priv->pxp); |
1648 | |
1649 | /* |
1650 | * On VLV/CHV display interrupts are part of the display |
1651 | * power well, so hpd is reinitialized from there. For |
1652 | * everyone else do it here. |
1653 | */ |
1654 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1655 | intel_hpd_init(dev_priv); |
1656 | intel_hpd_poll_disable(dev_priv); |
1657 | } |
1658 | |
1659 | skl_watermark_ipc_update(i915: dev_priv); |
1660 | |
1661 | enable_rpm_wakeref_asserts(rpm); |
1662 | |
1663 | if (ret) |
1664 | drm_err(&dev_priv->drm, |
1665 | "Runtime resume failed, disabling it (%d)\n" , ret); |
1666 | else |
1667 | drm_dbg(&dev_priv->drm, "Device resumed\n" ); |
1668 | |
1669 | return ret; |
1670 | } |
1671 | |
1672 | const struct dev_pm_ops i915_pm_ops = { |
1673 | /* |
1674 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, |
1675 | * PMSG_RESUME] |
1676 | */ |
1677 | .prepare = i915_pm_prepare, |
1678 | .suspend = i915_pm_suspend, |
1679 | .suspend_late = i915_pm_suspend_late, |
1680 | .resume_early = i915_pm_resume_early, |
1681 | .resume = i915_pm_resume, |
1682 | .complete = i915_pm_complete, |
1683 | |
1684 | /* |
1685 | * S4 event handlers |
1686 | * @freeze, @freeze_late : called (1) before creating the |
1687 | * hibernation image [PMSG_FREEZE] and |
1688 | * (2) after rebooting, before restoring |
1689 | * the image [PMSG_QUIESCE] |
1690 | * @thaw, @thaw_early : called (1) after creating the hibernation |
1691 | * image, before writing it [PMSG_THAW] |
1692 | * and (2) after failing to create or |
1693 | * restore the image [PMSG_RECOVER] |
1694 | * @poweroff, @poweroff_late: called after writing the hibernation |
1695 | * image, before rebooting [PMSG_HIBERNATE] |
1696 | * @restore, @restore_early : called after rebooting and restoring the |
1697 | * hibernation image [PMSG_RESTORE] |
1698 | */ |
1699 | .freeze = i915_pm_freeze, |
1700 | .freeze_late = i915_pm_freeze_late, |
1701 | .thaw_early = i915_pm_thaw_early, |
1702 | .thaw = i915_pm_thaw, |
1703 | .poweroff = i915_pm_suspend, |
1704 | .poweroff_late = i915_pm_poweroff_late, |
1705 | .restore_early = i915_pm_restore_early, |
1706 | .restore = i915_pm_restore, |
1707 | |
1708 | /* S0ix (via runtime suspend) event handlers */ |
1709 | .runtime_suspend = intel_runtime_suspend, |
1710 | .runtime_resume = intel_runtime_resume, |
1711 | }; |
1712 | |
1713 | static const struct file_operations i915_driver_fops = { |
1714 | .owner = THIS_MODULE, |
1715 | .open = drm_open, |
1716 | .release = drm_release_noglobal, |
1717 | .unlocked_ioctl = drm_ioctl, |
1718 | .mmap = i915_gem_mmap, |
1719 | .poll = drm_poll, |
1720 | .read = drm_read, |
1721 | .compat_ioctl = i915_ioc32_compat_ioctl, |
1722 | .llseek = noop_llseek, |
1723 | #ifdef CONFIG_PROC_FS |
1724 | .show_fdinfo = drm_show_fdinfo, |
1725 | #endif |
1726 | }; |
1727 | |
1728 | static int |
1729 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, |
1730 | struct drm_file *file) |
1731 | { |
1732 | return -ENODEV; |
1733 | } |
1734 | |
1735 | static const struct drm_ioctl_desc i915_ioctls[] = { |
1736 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1737 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), |
1738 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), |
1739 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), |
1740 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), |
1741 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), |
1742 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), |
1743 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1744 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), |
1745 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), |
1746 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1747 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), |
1748 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1749 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1750 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), |
1751 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), |
1752 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1753 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1754 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), |
1755 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), |
1756 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
1757 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), |
1758 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), |
1759 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), |
1760 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), |
1761 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), |
1762 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1763 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), |
1764 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), |
1765 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), |
1766 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), |
1767 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), |
1768 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), |
1769 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), |
1770 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), |
1771 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), |
1772 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), |
1773 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), |
1774 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), |
1775 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), |
1776 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), |
1777 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), |
1778 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), |
1779 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), |
1780 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), |
1781 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), |
1782 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), |
1783 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), |
1784 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), |
1785 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), |
1786 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), |
1787 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), |
1788 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), |
1789 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), |
1790 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), |
1791 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), |
1792 | DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), |
1793 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), |
1794 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), |
1795 | }; |
1796 | |
1797 | /* |
1798 | * Interface history: |
1799 | * |
1800 | * 1.1: Original. |
1801 | * 1.2: Add Power Management |
1802 | * 1.3: Add vblank support |
1803 | * 1.4: Fix cmdbuffer path, add heap destroy |
1804 | * 1.5: Add vblank pipe configuration |
1805 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
1806 | * - Support vertical blank on secondary display pipe |
1807 | */ |
1808 | #define DRIVER_MAJOR 1 |
1809 | #define DRIVER_MINOR 6 |
1810 | #define DRIVER_PATCHLEVEL 0 |
1811 | |
1812 | static const struct drm_driver i915_drm_driver = { |
1813 | /* Don't use MTRRs here; the Xserver or userspace app should |
1814 | * deal with them for Intel hardware. |
1815 | */ |
1816 | .driver_features = |
1817 | DRIVER_GEM | |
1818 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | |
1819 | DRIVER_SYNCOBJ_TIMELINE, |
1820 | .release = i915_driver_release, |
1821 | .open = i915_driver_open, |
1822 | .lastclose = i915_driver_lastclose, |
1823 | .postclose = i915_driver_postclose, |
1824 | .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), |
1825 | |
1826 | .gem_prime_import = i915_gem_prime_import, |
1827 | |
1828 | .dumb_create = i915_gem_dumb_create, |
1829 | .dumb_map_offset = i915_gem_dumb_mmap_offset, |
1830 | |
1831 | .ioctls = i915_ioctls, |
1832 | .num_ioctls = ARRAY_SIZE(i915_ioctls), |
1833 | .fops = &i915_driver_fops, |
1834 | .name = DRIVER_NAME, |
1835 | .desc = DRIVER_DESC, |
1836 | .date = DRIVER_DATE, |
1837 | .major = DRIVER_MAJOR, |
1838 | .minor = DRIVER_MINOR, |
1839 | .patchlevel = DRIVER_PATCHLEVEL, |
1840 | }; |
1841 | |