1 | // SPDX-License-Identifier: GPL-2.0-only |
---|---|
2 | /* |
3 | * Copyright (C) 2016 Broadcom |
4 | */ |
5 | |
6 | /** |
7 | * DOC: VC4 DSI0/DSI1 module |
8 | * |
9 | * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a |
10 | * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI |
11 | * controller. |
12 | * |
13 | * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector, |
14 | * while the compute module brings both DSI0 and DSI1 out. |
15 | * |
16 | * This driver has been tested for DSI1 video-mode display only |
17 | * currently, with most of the information necessary for DSI0 |
18 | * hopefully present. |
19 | */ |
20 | |
21 | #include <linux/clk-provider.h> |
22 | #include <linux/clk.h> |
23 | #include <linux/completion.h> |
24 | #include <linux/component.h> |
25 | #include <linux/dma-mapping.h> |
26 | #include <linux/dmaengine.h> |
27 | #include <linux/io.h> |
28 | #include <linux/of.h> |
29 | #include <linux/of_address.h> |
30 | #include <linux/platform_device.h> |
31 | #include <linux/pm_runtime.h> |
32 | |
33 | #include <drm/drm_atomic_helper.h> |
34 | #include <drm/drm_bridge.h> |
35 | #include <drm/drm_edid.h> |
36 | #include <drm/drm_mipi_dsi.h> |
37 | #include <drm/drm_of.h> |
38 | #include <drm/drm_panel.h> |
39 | #include <drm/drm_probe_helper.h> |
40 | #include <drm/drm_simple_kms_helper.h> |
41 | |
42 | #include "vc4_drv.h" |
43 | #include "vc4_regs.h" |
44 | |
45 | #define DSI_CMD_FIFO_DEPTH 16 |
46 | #define DSI_PIX_FIFO_DEPTH 256 |
47 | #define DSI_PIX_FIFO_WIDTH 4 |
48 | |
49 | #define DSI0_CTRL 0x00 |
50 | |
51 | /* Command packet control. */ |
52 | #define DSI0_TXPKT1C 0x04 /* AKA PKTC */ |
53 | #define DSI1_TXPKT1C 0x04 |
54 | # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24) |
55 | # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24 |
56 | # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10) |
57 | # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10 |
58 | |
59 | # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8) |
60 | # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8 |
61 | /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */ |
62 | # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0 |
63 | /* Primary display where cmdfifo provides part of the payload and |
64 | * pixelvalve the rest. |
65 | */ |
66 | # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1 |
67 | /* Secondary display where cmdfifo provides part of the payload and |
68 | * pixfifo the rest. |
69 | */ |
70 | # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2 |
71 | |
72 | # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6) |
73 | # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6 |
74 | |
75 | # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4) |
76 | # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4 |
77 | /* Command only. Uses TXPKT1H and DISPLAY_NO */ |
78 | # define DSI_TXPKT1C_CMD_CTRL_TX 0 |
79 | /* Command with BTA for either ack or read data. */ |
80 | # define DSI_TXPKT1C_CMD_CTRL_RX 1 |
81 | /* Trigger according to TRIG_CMD */ |
82 | # define DSI_TXPKT1C_CMD_CTRL_TRIG 2 |
83 | /* BTA alone for getting error status after a command, or a TE trigger |
84 | * without a previous command. |
85 | */ |
86 | # define DSI_TXPKT1C_CMD_CTRL_BTA 3 |
87 | |
88 | # define DSI_TXPKT1C_CMD_MODE_LP BIT(3) |
89 | # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2) |
90 | # define DSI_TXPKT1C_CMD_TE_EN BIT(1) |
91 | # define DSI_TXPKT1C_CMD_EN BIT(0) |
92 | |
93 | /* Command packet header. */ |
94 | #define DSI0_TXPKT1H 0x08 /* AKA PKTH */ |
95 | #define DSI1_TXPKT1H 0x08 |
96 | # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24) |
97 | # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24 |
98 | # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) |
99 | # define DSI_TXPKT1H_BC_PARAM_SHIFT 8 |
100 | # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0) |
101 | # define DSI_TXPKT1H_BC_DT_SHIFT 0 |
102 | |
103 | #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */ |
104 | #define DSI1_RXPKT1H 0x14 |
105 | # define DSI_RXPKT1H_CRC_ERR BIT(31) |
106 | # define DSI_RXPKT1H_DET_ERR BIT(30) |
107 | # define DSI_RXPKT1H_ECC_ERR BIT(29) |
108 | # define DSI_RXPKT1H_COR_ERR BIT(28) |
109 | # define DSI_RXPKT1H_INCOMP_PKT BIT(25) |
110 | # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24) |
111 | /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */ |
112 | # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) |
113 | # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 |
114 | /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */ |
115 | # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16) |
116 | # define DSI_RXPKT1H_SHORT_1_SHIFT 16 |
117 | # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8) |
118 | # define DSI_RXPKT1H_SHORT_0_SHIFT 8 |
119 | # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0) |
120 | # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0 |
121 | |
122 | #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */ |
123 | #define DSI1_RXPKT2H 0x18 |
124 | # define DSI_RXPKT1H_DET_ERR BIT(30) |
125 | # define DSI_RXPKT1H_ECC_ERR BIT(29) |
126 | # define DSI_RXPKT1H_COR_ERR BIT(28) |
127 | # define DSI_RXPKT1H_INCOMP_PKT BIT(25) |
128 | # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) |
129 | # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 |
130 | # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0) |
131 | # define DSI_RXPKT1H_DT_SHIFT 0 |
132 | |
133 | #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */ |
134 | #define DSI1_TXPKT_CMD_FIFO 0x1c |
135 | |
136 | #define DSI0_DISP0_CTRL 0x18 |
137 | # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13) |
138 | # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13 |
139 | # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11) |
140 | # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11 |
141 | # define DSI_DISP0_LP_STOP_DISABLE 0 |
142 | # define DSI_DISP0_LP_STOP_PERLINE 1 |
143 | # define DSI_DISP0_LP_STOP_PERFRAME 2 |
144 | |
145 | /* Transmit RGB pixels and null packets only during HACTIVE, instead |
146 | * of going to LP-STOP. |
147 | */ |
148 | # define DSI_DISP_HACTIVE_NULL BIT(10) |
149 | /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */ |
150 | # define DSI_DISP_VBLP_CTRL BIT(9) |
151 | /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */ |
152 | # define DSI_DISP_HFP_CTRL BIT(8) |
153 | /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */ |
154 | # define DSI_DISP_HBP_CTRL BIT(7) |
155 | # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5) |
156 | # define DSI_DISP0_CHANNEL_SHIFT 5 |
157 | /* Enables end events for HSYNC/VSYNC, not just start events. */ |
158 | # define DSI_DISP0_ST_END BIT(4) |
159 | # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2) |
160 | # define DSI_DISP0_PFORMAT_SHIFT 2 |
161 | # define DSI_PFORMAT_RGB565 0 |
162 | # define DSI_PFORMAT_RGB666_PACKED 1 |
163 | # define DSI_PFORMAT_RGB666 2 |
164 | # define DSI_PFORMAT_RGB888 3 |
165 | /* Default is VIDEO mode. */ |
166 | # define DSI_DISP0_COMMAND_MODE BIT(1) |
167 | # define DSI_DISP0_ENABLE BIT(0) |
168 | |
169 | #define DSI0_DISP1_CTRL 0x1c |
170 | #define DSI1_DISP1_CTRL 0x2c |
171 | /* Format of the data written to TXPKT_PIX_FIFO. */ |
172 | # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1) |
173 | # define DSI_DISP1_PFORMAT_SHIFT 1 |
174 | # define DSI_DISP1_PFORMAT_16BIT 0 |
175 | # define DSI_DISP1_PFORMAT_24BIT 1 |
176 | # define DSI_DISP1_PFORMAT_32BIT_LE 2 |
177 | # define DSI_DISP1_PFORMAT_32BIT_BE 3 |
178 | |
179 | /* DISP1 is always command mode. */ |
180 | # define DSI_DISP1_ENABLE BIT(0) |
181 | |
182 | #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */ |
183 | |
184 | #define DSI0_INT_STAT 0x24 |
185 | #define DSI0_INT_EN 0x28 |
186 | # define DSI0_INT_FIFO_ERR BIT(25) |
187 | # define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23) |
188 | # define DSI0_INT_CMDC_DONE_SHIFT 23 |
189 | # define DSI0_INT_CMDC_DONE_NO_REPEAT 1 |
190 | # define DSI0_INT_CMDC_DONE_REPEAT 3 |
191 | # define DSI0_INT_PHY_DIR_RTF BIT(22) |
192 | # define DSI0_INT_PHY_D1_ULPS BIT(21) |
193 | # define DSI0_INT_PHY_D1_STOP BIT(20) |
194 | # define DSI0_INT_PHY_RXLPDT BIT(19) |
195 | # define DSI0_INT_PHY_RXTRIG BIT(18) |
196 | # define DSI0_INT_PHY_D0_ULPS BIT(17) |
197 | # define DSI0_INT_PHY_D0_LPDT BIT(16) |
198 | # define DSI0_INT_PHY_D0_FTR BIT(15) |
199 | # define DSI0_INT_PHY_D0_STOP BIT(14) |
200 | /* Signaled when the clock lane enters the given state. */ |
201 | # define DSI0_INT_PHY_CLK_ULPS BIT(13) |
202 | # define DSI0_INT_PHY_CLK_HS BIT(12) |
203 | # define DSI0_INT_PHY_CLK_FTR BIT(11) |
204 | /* Signaled on timeouts */ |
205 | # define DSI0_INT_PR_TO BIT(10) |
206 | # define DSI0_INT_TA_TO BIT(9) |
207 | # define DSI0_INT_LPRX_TO BIT(8) |
208 | # define DSI0_INT_HSTX_TO BIT(7) |
209 | /* Contention on a line when trying to drive the line low */ |
210 | # define DSI0_INT_ERR_CONT_LP1 BIT(6) |
211 | # define DSI0_INT_ERR_CONT_LP0 BIT(5) |
212 | /* Control error: incorrect line state sequence on data lane 0. */ |
213 | # define DSI0_INT_ERR_CONTROL BIT(4) |
214 | # define DSI0_INT_ERR_SYNC_ESC BIT(3) |
215 | # define DSI0_INT_RX2_PKT BIT(2) |
216 | # define DSI0_INT_RX1_PKT BIT(1) |
217 | # define DSI0_INT_CMD_PKT BIT(0) |
218 | |
219 | #define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \ |
220 | DSI0_INT_ERR_CONTROL | \ |
221 | DSI0_INT_ERR_CONT_LP0 | \ |
222 | DSI0_INT_ERR_CONT_LP1 | \ |
223 | DSI0_INT_HSTX_TO | \ |
224 | DSI0_INT_LPRX_TO | \ |
225 | DSI0_INT_TA_TO | \ |
226 | DSI0_INT_PR_TO) |
227 | |
228 | # define DSI1_INT_PHY_D3_ULPS BIT(30) |
229 | # define DSI1_INT_PHY_D3_STOP BIT(29) |
230 | # define DSI1_INT_PHY_D2_ULPS BIT(28) |
231 | # define DSI1_INT_PHY_D2_STOP BIT(27) |
232 | # define DSI1_INT_PHY_D1_ULPS BIT(26) |
233 | # define DSI1_INT_PHY_D1_STOP BIT(25) |
234 | # define DSI1_INT_PHY_D0_ULPS BIT(24) |
235 | # define DSI1_INT_PHY_D0_STOP BIT(23) |
236 | # define DSI1_INT_FIFO_ERR BIT(22) |
237 | # define DSI1_INT_PHY_DIR_RTF BIT(21) |
238 | # define DSI1_INT_PHY_RXLPDT BIT(20) |
239 | # define DSI1_INT_PHY_RXTRIG BIT(19) |
240 | # define DSI1_INT_PHY_D0_LPDT BIT(18) |
241 | # define DSI1_INT_PHY_DIR_FTR BIT(17) |
242 | |
243 | /* Signaled when the clock lane enters the given state. */ |
244 | # define DSI1_INT_PHY_CLOCK_ULPS BIT(16) |
245 | # define DSI1_INT_PHY_CLOCK_HS BIT(15) |
246 | # define DSI1_INT_PHY_CLOCK_STOP BIT(14) |
247 | |
248 | /* Signaled on timeouts */ |
249 | # define DSI1_INT_PR_TO BIT(13) |
250 | # define DSI1_INT_TA_TO BIT(12) |
251 | # define DSI1_INT_LPRX_TO BIT(11) |
252 | # define DSI1_INT_HSTX_TO BIT(10) |
253 | |
254 | /* Contention on a line when trying to drive the line low */ |
255 | # define DSI1_INT_ERR_CONT_LP1 BIT(9) |
256 | # define DSI1_INT_ERR_CONT_LP0 BIT(8) |
257 | |
258 | /* Control error: incorrect line state sequence on data lane 0. */ |
259 | # define DSI1_INT_ERR_CONTROL BIT(7) |
260 | /* LPDT synchronization error (bits received not a multiple of 8. */ |
261 | |
262 | # define DSI1_INT_ERR_SYNC_ESC BIT(6) |
263 | /* Signaled after receiving an error packet from the display in |
264 | * response to a read. |
265 | */ |
266 | # define DSI1_INT_RXPKT2 BIT(5) |
267 | /* Signaled after receiving a packet. The header and optional short |
268 | * response will be in RXPKT1H, and a long response will be in the |
269 | * RXPKT_FIFO. |
270 | */ |
271 | # define DSI1_INT_RXPKT1 BIT(4) |
272 | # define DSI1_INT_TXPKT2_DONE BIT(3) |
273 | # define DSI1_INT_TXPKT2_END BIT(2) |
274 | /* Signaled after all repeats of TXPKT1 are transferred. */ |
275 | # define DSI1_INT_TXPKT1_DONE BIT(1) |
276 | /* Signaled after each TXPKT1 repeat is scheduled. */ |
277 | # define DSI1_INT_TXPKT1_END BIT(0) |
278 | |
279 | #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \ |
280 | DSI1_INT_ERR_CONTROL | \ |
281 | DSI1_INT_ERR_CONT_LP0 | \ |
282 | DSI1_INT_ERR_CONT_LP1 | \ |
283 | DSI1_INT_HSTX_TO | \ |
284 | DSI1_INT_LPRX_TO | \ |
285 | DSI1_INT_TA_TO | \ |
286 | DSI1_INT_PR_TO) |
287 | |
288 | #define DSI0_STAT 0x2c |
289 | #define DSI0_HSTX_TO_CNT 0x30 |
290 | #define DSI0_LPRX_TO_CNT 0x34 |
291 | #define DSI0_TA_TO_CNT 0x38 |
292 | #define DSI0_PR_TO_CNT 0x3c |
293 | #define DSI0_PHYC 0x40 |
294 | # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20) |
295 | # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20 |
296 | # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18) |
297 | # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12) |
298 | # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12 |
299 | # define DSI1_PHYC_CLANE_ULPS BIT(17) |
300 | # define DSI1_PHYC_CLANE_ENABLE BIT(16) |
301 | # define DSI_PHYC_DLANE3_ULPS BIT(13) |
302 | # define DSI_PHYC_DLANE3_ENABLE BIT(12) |
303 | # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10) |
304 | # define DSI0_PHYC_CLANE_ULPS BIT(9) |
305 | # define DSI_PHYC_DLANE2_ULPS BIT(9) |
306 | # define DSI0_PHYC_CLANE_ENABLE BIT(8) |
307 | # define DSI_PHYC_DLANE2_ENABLE BIT(8) |
308 | # define DSI_PHYC_DLANE1_ULPS BIT(5) |
309 | # define DSI_PHYC_DLANE1_ENABLE BIT(4) |
310 | # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2) |
311 | # define DSI_PHYC_DLANE0_ULPS BIT(1) |
312 | # define DSI_PHYC_DLANE0_ENABLE BIT(0) |
313 | |
314 | #define DSI0_HS_CLT0 0x44 |
315 | #define DSI0_HS_CLT1 0x48 |
316 | #define DSI0_HS_CLT2 0x4c |
317 | #define DSI0_HS_DLT3 0x50 |
318 | #define DSI0_HS_DLT4 0x54 |
319 | #define DSI0_HS_DLT5 0x58 |
320 | #define DSI0_HS_DLT6 0x5c |
321 | #define DSI0_HS_DLT7 0x60 |
322 | |
323 | #define DSI0_PHY_AFEC0 0x64 |
324 | # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26) |
325 | # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25) |
326 | # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24) |
327 | # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29) |
328 | # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29 |
329 | # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26) |
330 | # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26 |
331 | # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23) |
332 | # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23 |
333 | # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20) |
334 | # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20 |
335 | # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17) |
336 | # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17 |
337 | # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20) |
338 | # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20 |
339 | # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16) |
340 | # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16 |
341 | # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12) |
342 | # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12 |
343 | # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16) |
344 | # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15) |
345 | # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14) |
346 | # define DSI1_PHY_AFEC0_RESET BIT(13) |
347 | # define DSI1_PHY_AFEC0_PD BIT(12) |
348 | # define DSI0_PHY_AFEC0_RESET BIT(11) |
349 | # define DSI1_PHY_AFEC0_PD_BG BIT(11) |
350 | # define DSI0_PHY_AFEC0_PD BIT(10) |
351 | # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10) |
352 | # define DSI0_PHY_AFEC0_PD_BG BIT(9) |
353 | # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) |
354 | # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) |
355 | # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8) |
356 | # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) |
357 | # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 |
358 | # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) |
359 | # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0 |
360 | |
361 | #define DSI0_PHY_AFEC1 0x68 |
362 | # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8) |
363 | # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8 |
364 | # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4) |
365 | # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4 |
366 | # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0) |
367 | # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0 |
368 | |
369 | #define DSI0_TST_SEL 0x6c |
370 | #define DSI0_TST_MON 0x70 |
371 | #define DSI0_ID 0x74 |
372 | # define DSI_ID_VALUE 0x00647369 |
373 | |
374 | #define DSI1_CTRL 0x00 |
375 | # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14) |
376 | # define DSI_CTRL_HS_CLKC_SHIFT 14 |
377 | # define DSI_CTRL_HS_CLKC_BYTE 0 |
378 | # define DSI_CTRL_HS_CLKC_DDR2 1 |
379 | # define DSI_CTRL_HS_CLKC_DDR 2 |
380 | |
381 | # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13) |
382 | # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12) |
383 | # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11) |
384 | # define DSI_CTRL_SOFT_RESET_CFG BIT(10) |
385 | # define DSI_CTRL_CAL_BYTE BIT(9) |
386 | # define DSI_CTRL_INV_BYTE BIT(8) |
387 | # define DSI_CTRL_CLR_LDF BIT(7) |
388 | # define DSI0_CTRL_CLR_PBCF BIT(6) |
389 | # define DSI1_CTRL_CLR_RXF BIT(6) |
390 | # define DSI0_CTRL_CLR_CPBCF BIT(5) |
391 | # define DSI1_CTRL_CLR_PDF BIT(5) |
392 | # define DSI0_CTRL_CLR_PDF BIT(4) |
393 | # define DSI1_CTRL_CLR_CDF BIT(4) |
394 | # define DSI0_CTRL_CLR_CDF BIT(3) |
395 | # define DSI0_CTRL_CTRL2 BIT(2) |
396 | # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2) |
397 | # define DSI0_CTRL_CTRL1 BIT(1) |
398 | # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) |
399 | # define DSI0_CTRL_CTRL0 BIT(0) |
400 | # define DSI1_CTRL_EN BIT(0) |
401 | # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ |
402 | DSI0_CTRL_CLR_PBCF | \ |
403 | DSI0_CTRL_CLR_CPBCF | \ |
404 | DSI0_CTRL_CLR_PDF | \ |
405 | DSI0_CTRL_CLR_CDF) |
406 | # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ |
407 | DSI1_CTRL_CLR_RXF | \ |
408 | DSI1_CTRL_CLR_PDF | \ |
409 | DSI1_CTRL_CLR_CDF) |
410 | |
411 | #define DSI1_TXPKT2C 0x0c |
412 | #define DSI1_TXPKT2H 0x10 |
413 | #define DSI1_TXPKT_PIX_FIFO 0x20 |
414 | #define DSI1_RXPKT_FIFO 0x24 |
415 | #define DSI1_DISP0_CTRL 0x28 |
416 | #define DSI1_INT_STAT 0x30 |
417 | #define DSI1_INT_EN 0x34 |
418 | /* State reporting bits. These mostly behave like INT_STAT, where |
419 | * writing a 1 clears the bit. |
420 | */ |
421 | #define DSI1_STAT 0x38 |
422 | # define DSI1_STAT_PHY_D3_ULPS BIT(31) |
423 | # define DSI1_STAT_PHY_D3_STOP BIT(30) |
424 | # define DSI1_STAT_PHY_D2_ULPS BIT(29) |
425 | # define DSI1_STAT_PHY_D2_STOP BIT(28) |
426 | # define DSI1_STAT_PHY_D1_ULPS BIT(27) |
427 | # define DSI1_STAT_PHY_D1_STOP BIT(26) |
428 | # define DSI1_STAT_PHY_D0_ULPS BIT(25) |
429 | # define DSI1_STAT_PHY_D0_STOP BIT(24) |
430 | # define DSI1_STAT_FIFO_ERR BIT(23) |
431 | # define DSI1_STAT_PHY_RXLPDT BIT(22) |
432 | # define DSI1_STAT_PHY_RXTRIG BIT(21) |
433 | # define DSI1_STAT_PHY_D0_LPDT BIT(20) |
434 | /* Set when in forward direction */ |
435 | # define DSI1_STAT_PHY_DIR BIT(19) |
436 | # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18) |
437 | # define DSI1_STAT_PHY_CLOCK_HS BIT(17) |
438 | # define DSI1_STAT_PHY_CLOCK_STOP BIT(16) |
439 | # define DSI1_STAT_PR_TO BIT(15) |
440 | # define DSI1_STAT_TA_TO BIT(14) |
441 | # define DSI1_STAT_LPRX_TO BIT(13) |
442 | # define DSI1_STAT_HSTX_TO BIT(12) |
443 | # define DSI1_STAT_ERR_CONT_LP1 BIT(11) |
444 | # define DSI1_STAT_ERR_CONT_LP0 BIT(10) |
445 | # define DSI1_STAT_ERR_CONTROL BIT(9) |
446 | # define DSI1_STAT_ERR_SYNC_ESC BIT(8) |
447 | # define DSI1_STAT_RXPKT2 BIT(7) |
448 | # define DSI1_STAT_RXPKT1 BIT(6) |
449 | # define DSI1_STAT_TXPKT2_BUSY BIT(5) |
450 | # define DSI1_STAT_TXPKT2_DONE BIT(4) |
451 | # define DSI1_STAT_TXPKT2_END BIT(3) |
452 | # define DSI1_STAT_TXPKT1_BUSY BIT(2) |
453 | # define DSI1_STAT_TXPKT1_DONE BIT(1) |
454 | # define DSI1_STAT_TXPKT1_END BIT(0) |
455 | |
456 | #define DSI1_HSTX_TO_CNT 0x3c |
457 | #define DSI1_LPRX_TO_CNT 0x40 |
458 | #define DSI1_TA_TO_CNT 0x44 |
459 | #define DSI1_PR_TO_CNT 0x48 |
460 | #define DSI1_PHYC 0x4c |
461 | |
462 | #define DSI1_HS_CLT0 0x50 |
463 | # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18) |
464 | # define DSI_HS_CLT0_CZERO_SHIFT 18 |
465 | # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9) |
466 | # define DSI_HS_CLT0_CPRE_SHIFT 9 |
467 | # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0) |
468 | # define DSI_HS_CLT0_CPREP_SHIFT 0 |
469 | |
470 | #define DSI1_HS_CLT1 0x54 |
471 | # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9) |
472 | # define DSI_HS_CLT1_CTRAIL_SHIFT 9 |
473 | # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0) |
474 | # define DSI_HS_CLT1_CPOST_SHIFT 0 |
475 | |
476 | #define DSI1_HS_CLT2 0x58 |
477 | # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0) |
478 | # define DSI_HS_CLT2_WUP_SHIFT 0 |
479 | |
480 | #define DSI1_HS_DLT3 0x5c |
481 | # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18) |
482 | # define DSI_HS_DLT3_EXIT_SHIFT 18 |
483 | # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9) |
484 | # define DSI_HS_DLT3_ZERO_SHIFT 9 |
485 | # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0) |
486 | # define DSI_HS_DLT3_PRE_SHIFT 0 |
487 | |
488 | #define DSI1_HS_DLT4 0x60 |
489 | # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18) |
490 | # define DSI_HS_DLT4_ANLAT_SHIFT 18 |
491 | # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9) |
492 | # define DSI_HS_DLT4_TRAIL_SHIFT 9 |
493 | # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0) |
494 | # define DSI_HS_DLT4_LPX_SHIFT 0 |
495 | |
496 | #define DSI1_HS_DLT5 0x64 |
497 | # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0) |
498 | # define DSI_HS_DLT5_INIT_SHIFT 0 |
499 | |
500 | #define DSI1_HS_DLT6 0x68 |
501 | # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24) |
502 | # define DSI_HS_DLT6_TA_GET_SHIFT 24 |
503 | # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16) |
504 | # define DSI_HS_DLT6_TA_SURE_SHIFT 16 |
505 | # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8) |
506 | # define DSI_HS_DLT6_TA_GO_SHIFT 8 |
507 | # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0) |
508 | # define DSI_HS_DLT6_LP_LPX_SHIFT 0 |
509 | |
510 | #define DSI1_HS_DLT7 0x6c |
511 | # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0) |
512 | # define DSI_HS_DLT7_LP_WUP_SHIFT 0 |
513 | |
514 | #define DSI1_PHY_AFEC0 0x70 |
515 | |
516 | #define DSI1_PHY_AFEC1 0x74 |
517 | # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16) |
518 | # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16 |
519 | # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12) |
520 | # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12 |
521 | # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8) |
522 | # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8 |
523 | # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4) |
524 | # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4 |
525 | # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0) |
526 | # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0 |
527 | |
528 | #define DSI1_TST_SEL 0x78 |
529 | #define DSI1_TST_MON 0x7c |
530 | #define DSI1_PHY_TST1 0x80 |
531 | #define DSI1_PHY_TST2 0x84 |
532 | #define DSI1_PHY_FIFO_STAT 0x88 |
533 | /* Actually, all registers in the range that aren't otherwise claimed |
534 | * will return the ID. |
535 | */ |
536 | #define DSI1_ID 0x8c |
537 | |
538 | struct vc4_dsi_variant { |
539 | /* Whether we're on bcm2835's DSI0 or DSI1. */ |
540 | unsigned int port; |
541 | |
542 | bool broken_axi_workaround; |
543 | |
544 | const char *debugfs_name; |
545 | const struct debugfs_reg32 *regs; |
546 | size_t nregs; |
547 | |
548 | }; |
549 | |
550 | /* General DSI hardware state. */ |
551 | struct vc4_dsi { |
552 | struct vc4_encoder encoder; |
553 | struct mipi_dsi_host dsi_host; |
554 | |
555 | struct platform_device *pdev; |
556 | |
557 | struct drm_bridge *out_bridge; |
558 | struct drm_bridge bridge; |
559 | |
560 | void __iomem *regs; |
561 | |
562 | struct dma_chan *reg_dma_chan; |
563 | dma_addr_t reg_dma_paddr; |
564 | u32 *reg_dma_mem; |
565 | dma_addr_t reg_paddr; |
566 | |
567 | const struct vc4_dsi_variant *variant; |
568 | |
569 | /* DSI channel for the panel we're connected to. */ |
570 | u32 channel; |
571 | u32 lanes; |
572 | u32 format; |
573 | u32 divider; |
574 | u32 mode_flags; |
575 | |
576 | /* Input clock from CPRMAN to the digital PHY, for the DSI |
577 | * escape clock. |
578 | */ |
579 | struct clk *escape_clock; |
580 | |
581 | /* Input clock to the analog PHY, used to generate the DSI bit |
582 | * clock. |
583 | */ |
584 | struct clk *pll_phy_clock; |
585 | |
586 | /* HS Clocks generated within the DSI analog PHY. */ |
587 | struct clk_fixed_factor phy_clocks[3]; |
588 | |
589 | struct clk_hw_onecell_data *clk_onecell; |
590 | |
591 | /* Pixel clock output to the pixelvalve, generated from the HS |
592 | * clock. |
593 | */ |
594 | struct clk *pixel_clock; |
595 | |
596 | struct completion xfer_completion; |
597 | int xfer_result; |
598 | |
599 | struct debugfs_regset32 regset; |
600 | }; |
601 | |
602 | #define host_to_dsi(host) \ |
603 | container_of_const(host, struct vc4_dsi, dsi_host) |
604 | |
605 | #define to_vc4_dsi(_encoder) \ |
606 | container_of_const(_encoder, struct vc4_dsi, encoder.base) |
607 | |
608 | #define bridge_to_vc4_dsi(_bridge) \ |
609 | container_of_const(_bridge, struct vc4_dsi, bridge) |
610 | |
611 | static inline void |
612 | dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) |
613 | { |
614 | struct drm_device *drm = dsi->bridge.dev; |
615 | struct dma_chan *chan = dsi->reg_dma_chan; |
616 | struct dma_async_tx_descriptor *tx; |
617 | dma_cookie_t cookie; |
618 | int ret; |
619 | |
620 | kunit_fail_current_test("Accessing a register in a unit test!\n"); |
621 | |
622 | /* DSI0 should be able to write normally. */ |
623 | if (!chan) { |
624 | writel(val, addr: dsi->regs + offset); |
625 | return; |
626 | } |
627 | |
628 | *dsi->reg_dma_mem = val; |
629 | |
630 | tx = chan->device->device_prep_dma_memcpy(chan, |
631 | dsi->reg_paddr + offset, |
632 | dsi->reg_dma_paddr, |
633 | 4, 0); |
634 | if (!tx) { |
635 | drm_err(drm, "Failed to set up DMA register write\n"); |
636 | return; |
637 | } |
638 | |
639 | cookie = tx->tx_submit(tx); |
640 | ret = dma_submit_error(cookie); |
641 | if (ret) { |
642 | drm_err(drm, "Failed to submit DMA: %d\n", ret); |
643 | return; |
644 | } |
645 | ret = dma_sync_wait(chan, cookie); |
646 | if (ret) |
647 | drm_err(drm, "Failed to wait for DMA: %d\n", ret); |
648 | } |
649 | |
650 | #define DSI_READ(offset) \ |
651 | ({ \ |
652 | kunit_fail_current_test("Accessing a register in a unit test!\n"); \ |
653 | readl(dsi->regs + (offset)); \ |
654 | }) |
655 | |
656 | #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val) |
657 | #define DSI_PORT_READ(offset) \ |
658 | DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset) |
659 | #define DSI_PORT_WRITE(offset, val) \ |
660 | DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val) |
661 | #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit) |
662 | |
663 | static const struct debugfs_reg32 dsi0_regs[] = { |
664 | VC4_REG32(DSI0_CTRL), |
665 | VC4_REG32(DSI0_STAT), |
666 | VC4_REG32(DSI0_HSTX_TO_CNT), |
667 | VC4_REG32(DSI0_LPRX_TO_CNT), |
668 | VC4_REG32(DSI0_TA_TO_CNT), |
669 | VC4_REG32(DSI0_PR_TO_CNT), |
670 | VC4_REG32(DSI0_DISP0_CTRL), |
671 | VC4_REG32(DSI0_DISP1_CTRL), |
672 | VC4_REG32(DSI0_INT_STAT), |
673 | VC4_REG32(DSI0_INT_EN), |
674 | VC4_REG32(DSI0_PHYC), |
675 | VC4_REG32(DSI0_HS_CLT0), |
676 | VC4_REG32(DSI0_HS_CLT1), |
677 | VC4_REG32(DSI0_HS_CLT2), |
678 | VC4_REG32(DSI0_HS_DLT3), |
679 | VC4_REG32(DSI0_HS_DLT4), |
680 | VC4_REG32(DSI0_HS_DLT5), |
681 | VC4_REG32(DSI0_HS_DLT6), |
682 | VC4_REG32(DSI0_HS_DLT7), |
683 | VC4_REG32(DSI0_PHY_AFEC0), |
684 | VC4_REG32(DSI0_PHY_AFEC1), |
685 | VC4_REG32(DSI0_ID), |
686 | }; |
687 | |
688 | static const struct debugfs_reg32 dsi1_regs[] = { |
689 | VC4_REG32(DSI1_CTRL), |
690 | VC4_REG32(DSI1_STAT), |
691 | VC4_REG32(DSI1_HSTX_TO_CNT), |
692 | VC4_REG32(DSI1_LPRX_TO_CNT), |
693 | VC4_REG32(DSI1_TA_TO_CNT), |
694 | VC4_REG32(DSI1_PR_TO_CNT), |
695 | VC4_REG32(DSI1_DISP0_CTRL), |
696 | VC4_REG32(DSI1_DISP1_CTRL), |
697 | VC4_REG32(DSI1_INT_STAT), |
698 | VC4_REG32(DSI1_INT_EN), |
699 | VC4_REG32(DSI1_PHYC), |
700 | VC4_REG32(DSI1_HS_CLT0), |
701 | VC4_REG32(DSI1_HS_CLT1), |
702 | VC4_REG32(DSI1_HS_CLT2), |
703 | VC4_REG32(DSI1_HS_DLT3), |
704 | VC4_REG32(DSI1_HS_DLT4), |
705 | VC4_REG32(DSI1_HS_DLT5), |
706 | VC4_REG32(DSI1_HS_DLT6), |
707 | VC4_REG32(DSI1_HS_DLT7), |
708 | VC4_REG32(DSI1_PHY_AFEC0), |
709 | VC4_REG32(DSI1_PHY_AFEC1), |
710 | VC4_REG32(DSI1_ID), |
711 | }; |
712 | |
713 | static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) |
714 | { |
715 | u32 afec0 = DSI_PORT_READ(PHY_AFEC0); |
716 | |
717 | if (latch) |
718 | afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); |
719 | else |
720 | afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); |
721 | |
722 | DSI_PORT_WRITE(PHY_AFEC0, afec0); |
723 | } |
724 | |
725 | /* Enters or exits Ultra Low Power State. */ |
726 | static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) |
727 | { |
728 | bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; |
729 | u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) | |
730 | DSI_PHYC_DLANE0_ULPS | |
731 | (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | |
732 | (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | |
733 | (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); |
734 | u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) | |
735 | DSI1_STAT_PHY_D0_ULPS | |
736 | (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | |
737 | (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | |
738 | (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); |
739 | u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) | |
740 | DSI1_STAT_PHY_D0_STOP | |
741 | (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | |
742 | (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | |
743 | (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); |
744 | int ret; |
745 | bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) & |
746 | DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS)); |
747 | |
748 | if (ulps == ulps_currently_enabled) |
749 | return; |
750 | |
751 | DSI_PORT_WRITE(STAT, stat_ulps); |
752 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps); |
753 | ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200); |
754 | if (ret) { |
755 | dev_warn(&dsi->pdev->dev, |
756 | "Timeout waiting for DSI ULPS entry: STAT 0x%08x", |
757 | DSI_PORT_READ(STAT)); |
758 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); |
759 | vc4_dsi_latch_ulps(dsi, latch: false); |
760 | return; |
761 | } |
762 | |
763 | /* The DSI module can't be disabled while the module is |
764 | * generating ULPS state. So, to be able to disable the |
765 | * module, we have the AFE latch the ULPS state and continue |
766 | * on to having the module enter STOP. |
767 | */ |
768 | vc4_dsi_latch_ulps(dsi, latch: ulps); |
769 | |
770 | DSI_PORT_WRITE(STAT, stat_stop); |
771 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); |
772 | ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200); |
773 | if (ret) { |
774 | dev_warn(&dsi->pdev->dev, |
775 | "Timeout waiting for DSI STOP entry: STAT 0x%08x", |
776 | DSI_PORT_READ(STAT)); |
777 | DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); |
778 | return; |
779 | } |
780 | } |
781 | |
782 | static u32 |
783 | dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui) |
784 | { |
785 | /* The HS timings have to be rounded up to a multiple of 8 |
786 | * because we're using the byte clock. |
787 | */ |
788 | return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8); |
789 | } |
790 | |
791 | /* ESC always runs at 100Mhz. */ |
792 | #define ESC_TIME_NS 10 |
793 | |
794 | static u32 |
795 | dsi_esc_timing(u32 ns) |
796 | { |
797 | return DIV_ROUND_UP(ns, ESC_TIME_NS); |
798 | } |
799 | |
800 | static void vc4_dsi_bridge_disable(struct drm_bridge *bridge, |
801 | struct drm_atomic_state *state) |
802 | { |
803 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
804 | u32 disp0_ctrl; |
805 | |
806 | disp0_ctrl = DSI_PORT_READ(DISP0_CTRL); |
807 | disp0_ctrl &= ~DSI_DISP0_ENABLE; |
808 | DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); |
809 | } |
810 | |
811 | static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge, |
812 | struct drm_atomic_state *state) |
813 | { |
814 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
815 | struct device *dev = &dsi->pdev->dev; |
816 | |
817 | clk_disable_unprepare(clk: dsi->pll_phy_clock); |
818 | clk_disable_unprepare(clk: dsi->escape_clock); |
819 | clk_disable_unprepare(clk: dsi->pixel_clock); |
820 | |
821 | pm_runtime_put(dev); |
822 | } |
823 | |
824 | /* Extends the mode's blank intervals to handle BCM2835's integer-only |
825 | * DSI PLL divider. |
826 | * |
827 | * On 2835, PLLD is set to 2Ghz, and may not be changed by the display |
828 | * driver since most peripherals are hanging off of the PLLD_PER |
829 | * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore |
830 | * the pixel clock), only has an integer divider off of DSI. |
831 | * |
832 | * To get our panel mode to refresh at the expected 60Hz, we need to |
833 | * extend the horizontal blank time. This means we drive a |
834 | * higher-than-expected clock rate to the panel, but that's what the |
835 | * firmware does too. |
836 | */ |
837 | static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge, |
838 | const struct drm_display_mode *mode, |
839 | struct drm_display_mode *adjusted_mode) |
840 | { |
841 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
842 | struct clk *phy_parent = clk_get_parent(clk: dsi->pll_phy_clock); |
843 | unsigned long parent_rate = clk_get_rate(clk: phy_parent); |
844 | unsigned long pixel_clock_hz = mode->clock * 1000; |
845 | unsigned long pll_clock = pixel_clock_hz * dsi->divider; |
846 | int divider; |
847 | |
848 | /* Find what divider gets us a faster clock than the requested |
849 | * pixel clock. |
850 | */ |
851 | for (divider = 1; divider < 255; divider++) { |
852 | if (parent_rate / (divider + 1) < pll_clock) |
853 | break; |
854 | } |
855 | |
856 | /* Now that we've picked a PLL divider, calculate back to its |
857 | * pixel clock. |
858 | */ |
859 | pll_clock = parent_rate / divider; |
860 | pixel_clock_hz = pll_clock / dsi->divider; |
861 | |
862 | adjusted_mode->clock = pixel_clock_hz / 1000; |
863 | |
864 | /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ |
865 | adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / |
866 | mode->clock; |
867 | adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; |
868 | adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; |
869 | |
870 | return true; |
871 | } |
872 | |
873 | static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, |
874 | struct drm_atomic_state *state) |
875 | { |
876 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
877 | const struct drm_crtc_state *crtc_state; |
878 | struct device *dev = &dsi->pdev->dev; |
879 | const struct drm_display_mode *mode; |
880 | struct drm_connector *connector; |
881 | bool debug_dump_regs = false; |
882 | unsigned long hs_clock; |
883 | struct drm_crtc *crtc; |
884 | u32 ui_ns; |
885 | /* Minimum LP state duration in escape clock cycles. */ |
886 | u32 lpx = dsi_esc_timing(ns: 60); |
887 | unsigned long pixel_clock_hz; |
888 | unsigned long dsip_clock; |
889 | unsigned long phy_clock; |
890 | int ret; |
891 | |
892 | ret = pm_runtime_resume_and_get(dev); |
893 | if (ret) { |
894 | drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port); |
895 | return; |
896 | } |
897 | |
898 | if (debug_dump_regs) { |
899 | struct drm_printer p = drm_info_printer(dev: &dsi->pdev->dev); |
900 | dev_info(&dsi->pdev->dev, "DSI regs before:\n"); |
901 | drm_print_regset32(p: &p, regset: &dsi->regset); |
902 | } |
903 | |
904 | /* |
905 | * Retrieve the CRTC adjusted mode. This requires a little dance to go |
906 | * from the bridge to the encoder, to the connector and to the CRTC. |
907 | */ |
908 | connector = drm_atomic_get_new_connector_for_encoder(state, |
909 | encoder: bridge->encoder); |
910 | crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; |
911 | crtc_state = drm_atomic_get_new_crtc_state(state, crtc); |
912 | mode = &crtc_state->adjusted_mode; |
913 | |
914 | pixel_clock_hz = mode->clock * 1000; |
915 | |
916 | /* Round up the clk_set_rate() request slightly, since |
917 | * PLLD_DSI1 is an integer divider and its rate selection will |
918 | * never round up. |
919 | */ |
920 | phy_clock = (pixel_clock_hz + 1000) * dsi->divider; |
921 | ret = clk_set_rate(clk: dsi->pll_phy_clock, rate: phy_clock); |
922 | if (ret) { |
923 | dev_err(&dsi->pdev->dev, |
924 | "Failed to set phy clock to %ld: %d\n", phy_clock, ret); |
925 | } |
926 | |
927 | /* Reset the DSI and all its fifos. */ |
928 | DSI_PORT_WRITE(CTRL, |
929 | DSI_CTRL_SOFT_RESET_CFG | |
930 | DSI_PORT_BIT(CTRL_RESET_FIFOS)); |
931 | |
932 | DSI_PORT_WRITE(CTRL, |
933 | DSI_CTRL_HSDT_EOT_DISABLE | |
934 | DSI_CTRL_RX_LPDT_EOT_DISABLE); |
935 | |
936 | /* Clear all stat bits so we see what has happened during enable. */ |
937 | DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT)); |
938 | |
939 | /* Set AFE CTR00/CTR1 to release powerdown of analog. */ |
940 | if (dsi->variant->port == 0) { |
941 | u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | |
942 | VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); |
943 | |
944 | if (dsi->lanes < 2) |
945 | afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; |
946 | |
947 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) |
948 | afec0 |= DSI0_PHY_AFEC0_RESET; |
949 | |
950 | DSI_PORT_WRITE(PHY_AFEC0, afec0); |
951 | |
952 | /* AFEC reset hold time */ |
953 | mdelay(1); |
954 | |
955 | DSI_PORT_WRITE(PHY_AFEC1, |
956 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | |
957 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | |
958 | VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); |
959 | } else { |
960 | u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | |
961 | VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | |
962 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | |
963 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | |
964 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | |
965 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | |
966 | VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); |
967 | |
968 | if (dsi->lanes < 4) |
969 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; |
970 | if (dsi->lanes < 3) |
971 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; |
972 | if (dsi->lanes < 2) |
973 | afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; |
974 | |
975 | afec0 |= DSI1_PHY_AFEC0_RESET; |
976 | |
977 | DSI_PORT_WRITE(PHY_AFEC0, afec0); |
978 | |
979 | DSI_PORT_WRITE(PHY_AFEC1, 0); |
980 | |
981 | /* AFEC reset hold time */ |
982 | mdelay(1); |
983 | } |
984 | |
985 | ret = clk_prepare_enable(clk: dsi->escape_clock); |
986 | if (ret) { |
987 | drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n", |
988 | ret); |
989 | return; |
990 | } |
991 | |
992 | ret = clk_prepare_enable(clk: dsi->pll_phy_clock); |
993 | if (ret) { |
994 | drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret); |
995 | return; |
996 | } |
997 | |
998 | hs_clock = clk_get_rate(clk: dsi->pll_phy_clock); |
999 | |
1000 | /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate, |
1001 | * not the pixel clock rate. DSIxP take from the APHY's byte, |
1002 | * DDR2, or DDR4 clock (we use byte) and feed into the PV at |
1003 | * that rate. Separately, a value derived from PIX_CLK_DIV |
1004 | * and HS_CLKC is fed into the PV to divide down to the actual |
1005 | * pixel clock for pushing pixels into DSI. |
1006 | */ |
1007 | dsip_clock = phy_clock / 8; |
1008 | ret = clk_set_rate(clk: dsi->pixel_clock, rate: dsip_clock); |
1009 | if (ret) { |
1010 | dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n", |
1011 | dsip_clock, ret); |
1012 | } |
1013 | |
1014 | ret = clk_prepare_enable(clk: dsi->pixel_clock); |
1015 | if (ret) { |
1016 | drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret); |
1017 | return; |
1018 | } |
1019 | |
1020 | /* How many ns one DSI unit interval is. Note that the clock |
1021 | * is DDR, so there's an extra divide by 2. |
1022 | */ |
1023 | ui_ns = DIV_ROUND_UP(500000000, hs_clock); |
1024 | |
1025 | DSI_PORT_WRITE(HS_CLT0, |
1026 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), |
1027 | DSI_HS_CLT0_CZERO) | |
1028 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), |
1029 | DSI_HS_CLT0_CPRE) | |
1030 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), |
1031 | DSI_HS_CLT0_CPREP)); |
1032 | |
1033 | DSI_PORT_WRITE(HS_CLT1, |
1034 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), |
1035 | DSI_HS_CLT1_CTRAIL) | |
1036 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), |
1037 | DSI_HS_CLT1_CPOST)); |
1038 | |
1039 | DSI_PORT_WRITE(HS_CLT2, |
1040 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), |
1041 | DSI_HS_CLT2_WUP)); |
1042 | |
1043 | DSI_PORT_WRITE(HS_DLT3, |
1044 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), |
1045 | DSI_HS_DLT3_EXIT) | |
1046 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), |
1047 | DSI_HS_DLT3_ZERO) | |
1048 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), |
1049 | DSI_HS_DLT3_PRE)); |
1050 | |
1051 | DSI_PORT_WRITE(HS_DLT4, |
1052 | VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), |
1053 | DSI_HS_DLT4_LPX) | |
1054 | VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), |
1055 | dsi_hs_timing(ui_ns, 60, 4)), |
1056 | DSI_HS_DLT4_TRAIL) | |
1057 | VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); |
1058 | |
1059 | /* T_INIT is how long STOP is driven after power-up to |
1060 | * indicate to the slave (also coming out of power-up) that |
1061 | * master init is complete, and should be greater than the |
1062 | * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The |
1063 | * D-PHY spec gives a minimum 100us for T_INIT,MASTER and |
1064 | * T_INIT,SLAVE, while allowing protocols on top of it to give |
1065 | * greater minimums. The vc4 firmware uses an extremely |
1066 | * conservative 5ms, and we maintain that here. |
1067 | */ |
1068 | DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, |
1069 | 5 * 1000 * 1000, 0), |
1070 | DSI_HS_DLT5_INIT)); |
1071 | |
1072 | DSI_PORT_WRITE(HS_DLT6, |
1073 | VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | |
1074 | VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | |
1075 | VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | |
1076 | VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); |
1077 | |
1078 | DSI_PORT_WRITE(HS_DLT7, |
1079 | VC4_SET_FIELD(dsi_esc_timing(1000000), |
1080 | DSI_HS_DLT7_LP_WUP)); |
1081 | |
1082 | DSI_PORT_WRITE(PHYC, |
1083 | DSI_PHYC_DLANE0_ENABLE | |
1084 | (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | |
1085 | (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | |
1086 | (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | |
1087 | DSI_PORT_BIT(PHYC_CLANE_ENABLE) | |
1088 | ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? |
1089 | 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) | |
1090 | (dsi->variant->port == 0 ? |
1091 | VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : |
1092 | VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); |
1093 | |
1094 | DSI_PORT_WRITE(CTRL, |
1095 | DSI_PORT_READ(CTRL) | |
1096 | DSI_CTRL_CAL_BYTE); |
1097 | |
1098 | /* HS timeout in HS clock cycles: disabled. */ |
1099 | DSI_PORT_WRITE(HSTX_TO_CNT, 0); |
1100 | /* LP receive timeout in HS clocks. */ |
1101 | DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff); |
1102 | /* Bus turnaround timeout */ |
1103 | DSI_PORT_WRITE(TA_TO_CNT, 100000); |
1104 | /* Display reset sequence timeout */ |
1105 | DSI_PORT_WRITE(PR_TO_CNT, 100000); |
1106 | |
1107 | /* Set up DISP1 for transferring long command payloads through |
1108 | * the pixfifo. |
1109 | */ |
1110 | DSI_PORT_WRITE(DISP1_CTRL, |
1111 | VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, |
1112 | DSI_DISP1_PFORMAT) | |
1113 | DSI_DISP1_ENABLE); |
1114 | |
1115 | /* Ungate the block. */ |
1116 | if (dsi->variant->port == 0) |
1117 | DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); |
1118 | else |
1119 | DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); |
1120 | |
1121 | /* Bring AFE out of reset. */ |
1122 | DSI_PORT_WRITE(PHY_AFEC0, |
1123 | DSI_PORT_READ(PHY_AFEC0) & |
1124 | ~DSI_PORT_BIT(PHY_AFEC0_RESET)); |
1125 | |
1126 | vc4_dsi_ulps(dsi, ulps: false); |
1127 | |
1128 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
1129 | DSI_PORT_WRITE(DISP0_CTRL, |
1130 | VC4_SET_FIELD(dsi->divider, |
1131 | DSI_DISP0_PIX_CLK_DIV) | |
1132 | VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | |
1133 | VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, |
1134 | DSI_DISP0_LP_STOP_CTRL) | |
1135 | DSI_DISP0_ST_END); |
1136 | } else { |
1137 | DSI_PORT_WRITE(DISP0_CTRL, |
1138 | DSI_DISP0_COMMAND_MODE); |
1139 | } |
1140 | } |
1141 | |
1142 | static void vc4_dsi_bridge_enable(struct drm_bridge *bridge, |
1143 | struct drm_atomic_state *state) |
1144 | { |
1145 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
1146 | bool debug_dump_regs = false; |
1147 | u32 disp0_ctrl; |
1148 | |
1149 | disp0_ctrl = DSI_PORT_READ(DISP0_CTRL); |
1150 | disp0_ctrl |= DSI_DISP0_ENABLE; |
1151 | DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); |
1152 | |
1153 | if (debug_dump_regs) { |
1154 | struct drm_printer p = drm_info_printer(dev: &dsi->pdev->dev); |
1155 | dev_info(&dsi->pdev->dev, "DSI regs after:\n"); |
1156 | drm_print_regset32(p: &p, regset: &dsi->regset); |
1157 | } |
1158 | } |
1159 | |
1160 | static int vc4_dsi_bridge_attach(struct drm_bridge *bridge, |
1161 | struct drm_encoder *encoder, |
1162 | enum drm_bridge_attach_flags flags) |
1163 | { |
1164 | struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); |
1165 | |
1166 | /* Attach the panel or bridge to the dsi bridge */ |
1167 | return drm_bridge_attach(encoder, bridge: dsi->out_bridge, |
1168 | previous: &dsi->bridge, flags); |
1169 | } |
1170 | |
1171 | static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host, |
1172 | const struct mipi_dsi_msg *msg) |
1173 | { |
1174 | struct vc4_dsi *dsi = host_to_dsi(host); |
1175 | struct drm_device *drm = dsi->bridge.dev; |
1176 | struct mipi_dsi_packet packet; |
1177 | u32 pkth = 0, pktc = 0; |
1178 | int i, ret; |
1179 | bool is_long = mipi_dsi_packet_format_is_long(type: msg->type); |
1180 | u32 cmd_fifo_len = 0, pix_fifo_len = 0; |
1181 | |
1182 | mipi_dsi_create_packet(packet: &packet, msg); |
1183 | |
1184 | pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); |
1185 | pkth |= VC4_SET_FIELD(packet.header[1] | |
1186 | (packet.header[2] << 8), |
1187 | DSI_TXPKT1H_BC_PARAM); |
1188 | if (is_long) { |
1189 | /* Divide data across the various FIFOs we have available. |
1190 | * The command FIFO takes byte-oriented data, but is of |
1191 | * limited size. The pixel FIFO (never actually used for |
1192 | * pixel data in reality) is word oriented, and substantially |
1193 | * larger. So, we use the pixel FIFO for most of the data, |
1194 | * sending the residual bytes in the command FIFO at the start. |
1195 | * |
1196 | * With this arrangement, the command FIFO will never get full. |
1197 | */ |
1198 | if (packet.payload_length <= 16) { |
1199 | cmd_fifo_len = packet.payload_length; |
1200 | pix_fifo_len = 0; |
1201 | } else { |
1202 | cmd_fifo_len = (packet.payload_length % |
1203 | DSI_PIX_FIFO_WIDTH); |
1204 | pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / |
1205 | DSI_PIX_FIFO_WIDTH); |
1206 | } |
1207 | |
1208 | WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH); |
1209 | |
1210 | pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); |
1211 | } |
1212 | |
1213 | if (msg->rx_len) { |
1214 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, |
1215 | DSI_TXPKT1C_CMD_CTRL); |
1216 | } else { |
1217 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, |
1218 | DSI_TXPKT1C_CMD_CTRL); |
1219 | } |
1220 | |
1221 | for (i = 0; i < cmd_fifo_len; i++) |
1222 | DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]); |
1223 | for (i = 0; i < pix_fifo_len; i++) { |
1224 | const u8 *pix = packet.payload + cmd_fifo_len + i * 4; |
1225 | |
1226 | DSI_PORT_WRITE(TXPKT_PIX_FIFO, |
1227 | pix[0] | |
1228 | pix[1] << 8 | |
1229 | pix[2] << 16 | |
1230 | pix[3] << 24); |
1231 | } |
1232 | |
1233 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) |
1234 | pktc |= DSI_TXPKT1C_CMD_MODE_LP; |
1235 | if (is_long) |
1236 | pktc |= DSI_TXPKT1C_CMD_TYPE_LONG; |
1237 | |
1238 | /* Send one copy of the packet. Larger repeats are used for pixel |
1239 | * data in command mode. |
1240 | */ |
1241 | pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); |
1242 | |
1243 | pktc |= DSI_TXPKT1C_CMD_EN; |
1244 | if (pix_fifo_len) { |
1245 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, |
1246 | DSI_TXPKT1C_DISPLAY_NO); |
1247 | } else { |
1248 | pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, |
1249 | DSI_TXPKT1C_DISPLAY_NO); |
1250 | } |
1251 | |
1252 | /* Enable the appropriate interrupt for the transfer completion. */ |
1253 | dsi->xfer_result = 0; |
1254 | reinit_completion(x: &dsi->xfer_completion); |
1255 | if (dsi->variant->port == 0) { |
1256 | DSI_PORT_WRITE(INT_STAT, |
1257 | DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF); |
1258 | if (msg->rx_len) { |
1259 | DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED | |
1260 | DSI0_INT_PHY_DIR_RTF)); |
1261 | } else { |
1262 | DSI_PORT_WRITE(INT_EN, |
1263 | (DSI0_INTERRUPTS_ALWAYS_ENABLED | |
1264 | VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT, |
1265 | DSI0_INT_CMDC_DONE))); |
1266 | } |
1267 | } else { |
1268 | DSI_PORT_WRITE(INT_STAT, |
1269 | DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF); |
1270 | if (msg->rx_len) { |
1271 | DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | |
1272 | DSI1_INT_PHY_DIR_RTF)); |
1273 | } else { |
1274 | DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | |
1275 | DSI1_INT_TXPKT1_DONE)); |
1276 | } |
1277 | } |
1278 | |
1279 | /* Send the packet. */ |
1280 | DSI_PORT_WRITE(TXPKT1H, pkth); |
1281 | DSI_PORT_WRITE(TXPKT1C, pktc); |
1282 | |
1283 | if (!wait_for_completion_timeout(x: &dsi->xfer_completion, |
1284 | timeout: msecs_to_jiffies(m: 1000))) { |
1285 | dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); |
1286 | dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", |
1287 | DSI_PORT_READ(INT_STAT)); |
1288 | ret = -ETIMEDOUT; |
1289 | } else { |
1290 | ret = dsi->xfer_result; |
1291 | } |
1292 | |
1293 | DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); |
1294 | |
1295 | if (ret) |
1296 | goto reset_fifo_and_return; |
1297 | |
1298 | if (ret == 0 && msg->rx_len) { |
1299 | u32 rxpkt1h = DSI_PORT_READ(RXPKT1H); |
1300 | u8 *msg_rx = msg->rx_buf; |
1301 | |
1302 | if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) { |
1303 | u32 rxlen = VC4_GET_FIELD(rxpkt1h, |
1304 | DSI_RXPKT1H_BC_PARAM); |
1305 | |
1306 | if (rxlen != msg->rx_len) { |
1307 | drm_err(drm, "DSI returned %db, expecting %db\n", |
1308 | rxlen, (int)msg->rx_len); |
1309 | ret = -ENXIO; |
1310 | goto reset_fifo_and_return; |
1311 | } |
1312 | |
1313 | for (i = 0; i < msg->rx_len; i++) |
1314 | msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO); |
1315 | } else { |
1316 | /* FINISHME: Handle AWER */ |
1317 | |
1318 | msg_rx[0] = VC4_GET_FIELD(rxpkt1h, |
1319 | DSI_RXPKT1H_SHORT_0); |
1320 | if (msg->rx_len > 1) { |
1321 | msg_rx[1] = VC4_GET_FIELD(rxpkt1h, |
1322 | DSI_RXPKT1H_SHORT_1); |
1323 | } |
1324 | } |
1325 | } |
1326 | |
1327 | return ret; |
1328 | |
1329 | reset_fifo_and_return: |
1330 | drm_err(drm, "DSI transfer failed, resetting: %d\n", ret); |
1331 | |
1332 | DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN); |
1333 | udelay(usec: 1); |
1334 | DSI_PORT_WRITE(CTRL, |
1335 | DSI_PORT_READ(CTRL) | |
1336 | DSI_PORT_BIT(CTRL_RESET_FIFOS)); |
1337 | |
1338 | DSI_PORT_WRITE(TXPKT1C, 0); |
1339 | DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); |
1340 | return ret; |
1341 | } |
1342 | |
1343 | static const struct component_ops vc4_dsi_ops; |
1344 | static int vc4_dsi_host_attach(struct mipi_dsi_host *host, |
1345 | struct mipi_dsi_device *device) |
1346 | { |
1347 | struct vc4_dsi *dsi = host_to_dsi(host); |
1348 | int ret; |
1349 | |
1350 | dsi->lanes = device->lanes; |
1351 | dsi->channel = device->channel; |
1352 | dsi->mode_flags = device->mode_flags; |
1353 | |
1354 | switch (device->format) { |
1355 | case MIPI_DSI_FMT_RGB888: |
1356 | dsi->format = DSI_PFORMAT_RGB888; |
1357 | dsi->divider = 24 / dsi->lanes; |
1358 | break; |
1359 | case MIPI_DSI_FMT_RGB666: |
1360 | dsi->format = DSI_PFORMAT_RGB666; |
1361 | dsi->divider = 24 / dsi->lanes; |
1362 | break; |
1363 | case MIPI_DSI_FMT_RGB666_PACKED: |
1364 | dsi->format = DSI_PFORMAT_RGB666_PACKED; |
1365 | dsi->divider = 18 / dsi->lanes; |
1366 | break; |
1367 | case MIPI_DSI_FMT_RGB565: |
1368 | dsi->format = DSI_PFORMAT_RGB565; |
1369 | dsi->divider = 16 / dsi->lanes; |
1370 | break; |
1371 | default: |
1372 | dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", |
1373 | dsi->format); |
1374 | return 0; |
1375 | } |
1376 | |
1377 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { |
1378 | dev_err(&dsi->pdev->dev, |
1379 | "Only VIDEO mode panels supported currently.\n"); |
1380 | return 0; |
1381 | } |
1382 | |
1383 | drm_bridge_add(bridge: &dsi->bridge); |
1384 | |
1385 | ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); |
1386 | if (ret) { |
1387 | drm_bridge_remove(bridge: &dsi->bridge); |
1388 | return ret; |
1389 | } |
1390 | |
1391 | return 0; |
1392 | } |
1393 | |
1394 | static int vc4_dsi_host_detach(struct mipi_dsi_host *host, |
1395 | struct mipi_dsi_device *device) |
1396 | { |
1397 | struct vc4_dsi *dsi = host_to_dsi(host); |
1398 | |
1399 | component_del(&dsi->pdev->dev, &vc4_dsi_ops); |
1400 | drm_bridge_remove(bridge: &dsi->bridge); |
1401 | return 0; |
1402 | } |
1403 | |
1404 | static const struct mipi_dsi_host_ops vc4_dsi_host_ops = { |
1405 | .attach = vc4_dsi_host_attach, |
1406 | .detach = vc4_dsi_host_detach, |
1407 | .transfer = vc4_dsi_host_transfer, |
1408 | }; |
1409 | |
1410 | static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = { |
1411 | .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, |
1412 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
1413 | .atomic_reset = drm_atomic_helper_bridge_reset, |
1414 | .atomic_pre_enable = vc4_dsi_bridge_pre_enable, |
1415 | .atomic_enable = vc4_dsi_bridge_enable, |
1416 | .atomic_disable = vc4_dsi_bridge_disable, |
1417 | .atomic_post_disable = vc4_dsi_bridge_post_disable, |
1418 | .attach = vc4_dsi_bridge_attach, |
1419 | .mode_fixup = vc4_dsi_bridge_mode_fixup, |
1420 | }; |
1421 | |
1422 | static int vc4_dsi_late_register(struct drm_encoder *encoder) |
1423 | { |
1424 | struct drm_device *drm = encoder->dev; |
1425 | struct vc4_dsi *dsi = to_vc4_dsi(encoder); |
1426 | |
1427 | vc4_debugfs_add_regset32(drm, filename: dsi->variant->debugfs_name, regset: &dsi->regset); |
1428 | |
1429 | return 0; |
1430 | } |
1431 | |
1432 | static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = { |
1433 | .late_register = vc4_dsi_late_register, |
1434 | }; |
1435 | |
1436 | static const struct vc4_dsi_variant bcm2711_dsi1_variant = { |
1437 | .port = 1, |
1438 | .debugfs_name = "dsi1_regs", |
1439 | .regs = dsi1_regs, |
1440 | .nregs = ARRAY_SIZE(dsi1_regs), |
1441 | }; |
1442 | |
1443 | static const struct vc4_dsi_variant bcm2835_dsi0_variant = { |
1444 | .port = 0, |
1445 | .debugfs_name = "dsi0_regs", |
1446 | .regs = dsi0_regs, |
1447 | .nregs = ARRAY_SIZE(dsi0_regs), |
1448 | }; |
1449 | |
1450 | static const struct vc4_dsi_variant bcm2835_dsi1_variant = { |
1451 | .port = 1, |
1452 | .broken_axi_workaround = true, |
1453 | .debugfs_name = "dsi1_regs", |
1454 | .regs = dsi1_regs, |
1455 | .nregs = ARRAY_SIZE(dsi1_regs), |
1456 | }; |
1457 | |
1458 | static const struct of_device_id vc4_dsi_dt_match[] = { |
1459 | { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant }, |
1460 | { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant }, |
1461 | { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant }, |
1462 | {} |
1463 | }; |
1464 | |
1465 | static void dsi_handle_error(struct vc4_dsi *dsi, |
1466 | irqreturn_t *ret, u32 stat, u32 bit, |
1467 | const char *type) |
1468 | { |
1469 | if (!(stat & bit)) |
1470 | return; |
1471 | |
1472 | drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port, |
1473 | type); |
1474 | *ret = IRQ_HANDLED; |
1475 | } |
1476 | |
1477 | /* |
1478 | * Initial handler for port 1 where we need the reg_dma workaround. |
1479 | * The register DMA writes sleep, so we can't do it in the top half. |
1480 | * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the |
1481 | * parent interrupt contrller until our interrupt thread is done. |
1482 | */ |
1483 | static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data) |
1484 | { |
1485 | struct vc4_dsi *dsi = data; |
1486 | u32 stat = DSI_PORT_READ(INT_STAT); |
1487 | |
1488 | if (!stat) |
1489 | return IRQ_NONE; |
1490 | |
1491 | return IRQ_WAKE_THREAD; |
1492 | } |
1493 | |
1494 | /* |
1495 | * Normal IRQ handler for port 0, or the threaded IRQ handler for port |
1496 | * 1 where we need the reg_dma workaround. |
1497 | */ |
1498 | static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) |
1499 | { |
1500 | struct vc4_dsi *dsi = data; |
1501 | u32 stat = DSI_PORT_READ(INT_STAT); |
1502 | irqreturn_t ret = IRQ_NONE; |
1503 | |
1504 | DSI_PORT_WRITE(INT_STAT, stat); |
1505 | |
1506 | dsi_handle_error(dsi, ret: &ret, stat, |
1507 | DSI_PORT_BIT(INT_ERR_SYNC_ESC), type: "LPDT sync"); |
1508 | dsi_handle_error(dsi, ret: &ret, stat, |
1509 | DSI_PORT_BIT(INT_ERR_CONTROL), type: "data lane 0 sequence"); |
1510 | dsi_handle_error(dsi, ret: &ret, stat, |
1511 | DSI_PORT_BIT(INT_ERR_CONT_LP0), type: "LP0 contention"); |
1512 | dsi_handle_error(dsi, ret: &ret, stat, |
1513 | DSI_PORT_BIT(INT_ERR_CONT_LP1), type: "LP1 contention"); |
1514 | dsi_handle_error(dsi, ret: &ret, stat, |
1515 | DSI_PORT_BIT(INT_HSTX_TO), type: "HSTX timeout"); |
1516 | dsi_handle_error(dsi, ret: &ret, stat, |
1517 | DSI_PORT_BIT(INT_LPRX_TO), type: "LPRX timeout"); |
1518 | dsi_handle_error(dsi, ret: &ret, stat, |
1519 | DSI_PORT_BIT(INT_TA_TO), type: "turnaround timeout"); |
1520 | dsi_handle_error(dsi, ret: &ret, stat, |
1521 | DSI_PORT_BIT(INT_PR_TO), type: "peripheral reset timeout"); |
1522 | |
1523 | if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : |
1524 | DSI0_INT_CMDC_DONE_MASK) | |
1525 | DSI_PORT_BIT(INT_PHY_DIR_RTF))) { |
1526 | complete(&dsi->xfer_completion); |
1527 | ret = IRQ_HANDLED; |
1528 | } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) { |
1529 | complete(&dsi->xfer_completion); |
1530 | dsi->xfer_result = -ETIMEDOUT; |
1531 | ret = IRQ_HANDLED; |
1532 | } |
1533 | |
1534 | return ret; |
1535 | } |
1536 | |
1537 | /** |
1538 | * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog |
1539 | * PHY that are consumed by CPRMAN (clk-bcm2835.c). |
1540 | * @dsi: DSI encoder |
1541 | */ |
1542 | static int |
1543 | vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) |
1544 | { |
1545 | struct device *dev = &dsi->pdev->dev; |
1546 | const char *parent_name = __clk_get_name(clk: dsi->pll_phy_clock); |
1547 | static const struct { |
1548 | const char *name; |
1549 | int div; |
1550 | } phy_clocks[] = { |
1551 | { "byte", 8 }, |
1552 | { "ddr2", 4 }, |
1553 | { "ddr", 2 }, |
1554 | }; |
1555 | int i; |
1556 | |
1557 | dsi->clk_onecell = devm_kzalloc(dev, |
1558 | size: sizeof(*dsi->clk_onecell) + |
1559 | ARRAY_SIZE(phy_clocks) * |
1560 | sizeof(struct clk_hw *), |
1561 | GFP_KERNEL); |
1562 | if (!dsi->clk_onecell) |
1563 | return -ENOMEM; |
1564 | dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); |
1565 | |
1566 | for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) { |
1567 | struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; |
1568 | struct clk_init_data init; |
1569 | char clk_name[16]; |
1570 | int ret; |
1571 | |
1572 | snprintf(buf: clk_name, size: sizeof(clk_name), |
1573 | fmt: "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); |
1574 | |
1575 | /* We just use core fixed factor clock ops for the PHY |
1576 | * clocks. The clocks are actually gated by the |
1577 | * PHY_AFEC0_DDRCLK_EN bits, which we should be |
1578 | * setting if we use the DDR/DDR2 clocks. However, |
1579 | * vc4_dsi_encoder_enable() is setting up both AFEC0, |
1580 | * setting both our parent DSI PLL's rate and this |
1581 | * clock's rate, so it knows if DDR/DDR2 are going to |
1582 | * be used and could enable the gates itself. |
1583 | */ |
1584 | fix->mult = 1; |
1585 | fix->div = phy_clocks[i].div; |
1586 | fix->hw.init = &init; |
1587 | |
1588 | memset(&init, 0, sizeof(init)); |
1589 | init.parent_names = &parent_name; |
1590 | init.num_parents = 1; |
1591 | init.name = clk_name; |
1592 | init.ops = &clk_fixed_factor_ops; |
1593 | |
1594 | ret = devm_clk_hw_register(dev, hw: &fix->hw); |
1595 | if (ret) |
1596 | return ret; |
1597 | |
1598 | dsi->clk_onecell->hws[i] = &fix->hw; |
1599 | } |
1600 | |
1601 | return of_clk_add_hw_provider(np: dev->of_node, |
1602 | get: of_clk_hw_onecell_get, |
1603 | data: dsi->clk_onecell); |
1604 | } |
1605 | |
1606 | static void vc4_dsi_dma_mem_release(void *ptr) |
1607 | { |
1608 | struct vc4_dsi *dsi = ptr; |
1609 | struct device *dev = &dsi->pdev->dev; |
1610 | |
1611 | dma_free_coherent(dev, size: 4, cpu_addr: dsi->reg_dma_mem, dma_handle: dsi->reg_dma_paddr); |
1612 | dsi->reg_dma_mem = NULL; |
1613 | } |
1614 | |
1615 | static void vc4_dsi_dma_chan_release(void *ptr) |
1616 | { |
1617 | struct vc4_dsi *dsi = ptr; |
1618 | |
1619 | dma_release_channel(chan: dsi->reg_dma_chan); |
1620 | dsi->reg_dma_chan = NULL; |
1621 | } |
1622 | |
1623 | static void vc4_dsi_release_action(struct drm_device *drm, void *ptr) |
1624 | { |
1625 | struct vc4_dsi *dsi = ptr; |
1626 | |
1627 | drm_bridge_put(bridge: &dsi->bridge); |
1628 | } |
1629 | |
1630 | static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) |
1631 | { |
1632 | struct platform_device *pdev = to_platform_device(dev); |
1633 | struct drm_device *drm = dev_get_drvdata(dev: master); |
1634 | struct vc4_dsi *dsi = dev_get_drvdata(dev); |
1635 | struct drm_encoder *encoder = &dsi->encoder.base; |
1636 | int ret; |
1637 | |
1638 | drm_bridge_get(bridge: &dsi->bridge); |
1639 | |
1640 | ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi); |
1641 | if (ret) |
1642 | return ret; |
1643 | |
1644 | dsi->variant = of_device_get_match_data(dev); |
1645 | |
1646 | dsi->encoder.type = dsi->variant->port ? |
1647 | VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0; |
1648 | |
1649 | dsi->regs = vc4_ioremap_regs(dev: pdev, index: 0); |
1650 | if (IS_ERR(ptr: dsi->regs)) |
1651 | return PTR_ERR(ptr: dsi->regs); |
1652 | |
1653 | dsi->regset.base = dsi->regs; |
1654 | dsi->regset.regs = dsi->variant->regs; |
1655 | dsi->regset.nregs = dsi->variant->nregs; |
1656 | |
1657 | if (DSI_PORT_READ(ID) != DSI_ID_VALUE) { |
1658 | dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n", |
1659 | DSI_PORT_READ(ID), DSI_ID_VALUE); |
1660 | return -ENODEV; |
1661 | } |
1662 | |
1663 | /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to |
1664 | * writes from the ARM. It does handle writes from the DMA engine, |
1665 | * so set up a channel for talking to it. |
1666 | */ |
1667 | if (dsi->variant->broken_axi_workaround) { |
1668 | dma_cap_mask_t dma_mask; |
1669 | |
1670 | dsi->reg_dma_mem = dma_alloc_coherent(dev, size: 4, |
1671 | dma_handle: &dsi->reg_dma_paddr, |
1672 | GFP_KERNEL); |
1673 | if (!dsi->reg_dma_mem) { |
1674 | drm_err(drm, "Failed to get DMA memory\n"); |
1675 | return -ENOMEM; |
1676 | } |
1677 | |
1678 | ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi); |
1679 | if (ret) |
1680 | return ret; |
1681 | |
1682 | dma_cap_zero(dma_mask); |
1683 | dma_cap_set(DMA_MEMCPY, dma_mask); |
1684 | |
1685 | dsi->reg_dma_chan = dma_request_chan_by_mask(mask: &dma_mask); |
1686 | if (IS_ERR(ptr: dsi->reg_dma_chan)) { |
1687 | ret = PTR_ERR(ptr: dsi->reg_dma_chan); |
1688 | if (ret != -EPROBE_DEFER) |
1689 | drm_err(drm, "Failed to get DMA channel: %d\n", |
1690 | ret); |
1691 | return ret; |
1692 | } |
1693 | |
1694 | ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi); |
1695 | if (ret) |
1696 | return ret; |
1697 | |
1698 | /* Get the physical address of the device's registers. The |
1699 | * struct resource for the regs gives us the bus address |
1700 | * instead. |
1701 | */ |
1702 | dsi->reg_paddr = be32_to_cpup(p: of_get_address(dev: dev->of_node, |
1703 | index: 0, NULL, NULL)); |
1704 | } |
1705 | |
1706 | init_completion(x: &dsi->xfer_completion); |
1707 | /* At startup enable error-reporting interrupts and nothing else. */ |
1708 | DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); |
1709 | /* Clear any existing interrupt state. */ |
1710 | DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); |
1711 | |
1712 | if (dsi->reg_dma_mem) |
1713 | ret = devm_request_threaded_irq(dev, irq: platform_get_irq(pdev, 0), |
1714 | handler: vc4_dsi_irq_defer_to_thread_handler, |
1715 | thread_fn: vc4_dsi_irq_handler, |
1716 | IRQF_ONESHOT, |
1717 | devname: "vc4 dsi", dev_id: dsi); |
1718 | else |
1719 | ret = devm_request_irq(dev, irq: platform_get_irq(pdev, 0), |
1720 | handler: vc4_dsi_irq_handler, irqflags: 0, devname: "vc4 dsi", dev_id: dsi); |
1721 | if (ret) { |
1722 | if (ret != -EPROBE_DEFER) |
1723 | dev_err(dev, "Failed to get interrupt: %d\n", ret); |
1724 | return ret; |
1725 | } |
1726 | |
1727 | dsi->escape_clock = devm_clk_get(dev, id: "escape"); |
1728 | if (IS_ERR(ptr: dsi->escape_clock)) { |
1729 | ret = PTR_ERR(ptr: dsi->escape_clock); |
1730 | if (ret != -EPROBE_DEFER) |
1731 | dev_err(dev, "Failed to get escape clock: %d\n", ret); |
1732 | return ret; |
1733 | } |
1734 | |
1735 | dsi->pll_phy_clock = devm_clk_get(dev, id: "phy"); |
1736 | if (IS_ERR(ptr: dsi->pll_phy_clock)) { |
1737 | ret = PTR_ERR(ptr: dsi->pll_phy_clock); |
1738 | if (ret != -EPROBE_DEFER) |
1739 | dev_err(dev, "Failed to get phy clock: %d\n", ret); |
1740 | return ret; |
1741 | } |
1742 | |
1743 | dsi->pixel_clock = devm_clk_get(dev, id: "pixel"); |
1744 | if (IS_ERR(ptr: dsi->pixel_clock)) { |
1745 | ret = PTR_ERR(ptr: dsi->pixel_clock); |
1746 | if (ret != -EPROBE_DEFER) |
1747 | dev_err(dev, "Failed to get pixel clock: %d\n", ret); |
1748 | return ret; |
1749 | } |
1750 | |
1751 | dsi->out_bridge = drmm_of_get_bridge(drm, node: dev->of_node, port: 0, endpoint: 0); |
1752 | if (IS_ERR(ptr: dsi->out_bridge)) |
1753 | return PTR_ERR(ptr: dsi->out_bridge); |
1754 | |
1755 | /* The esc clock rate is supposed to always be 100Mhz. */ |
1756 | ret = clk_set_rate(clk: dsi->escape_clock, rate: 100 * 1000000); |
1757 | if (ret) { |
1758 | dev_err(dev, "Failed to set esc clock: %d\n", ret); |
1759 | return ret; |
1760 | } |
1761 | |
1762 | ret = vc4_dsi_init_phy_clocks(dsi); |
1763 | if (ret) |
1764 | return ret; |
1765 | |
1766 | ret = drmm_encoder_init(dev: drm, encoder, |
1767 | funcs: &vc4_dsi_encoder_funcs, |
1768 | DRM_MODE_ENCODER_DSI, |
1769 | NULL); |
1770 | if (ret) |
1771 | return ret; |
1772 | |
1773 | ret = devm_pm_runtime_enable(dev); |
1774 | if (ret) |
1775 | return ret; |
1776 | |
1777 | ret = drm_bridge_attach(encoder, bridge: &dsi->bridge, NULL, flags: 0); |
1778 | if (ret) |
1779 | return ret; |
1780 | |
1781 | return 0; |
1782 | } |
1783 | |
1784 | static const struct component_ops vc4_dsi_ops = { |
1785 | .bind = vc4_dsi_bind, |
1786 | }; |
1787 | |
1788 | static int vc4_dsi_dev_probe(struct platform_device *pdev) |
1789 | { |
1790 | struct device *dev = &pdev->dev; |
1791 | struct vc4_dsi *dsi; |
1792 | |
1793 | dsi = devm_drm_bridge_alloc(&pdev->dev, struct vc4_dsi, bridge, &vc4_dsi_bridge_funcs); |
1794 | if (IS_ERR(ptr: dsi)) |
1795 | return PTR_ERR(ptr: dsi); |
1796 | dev_set_drvdata(dev, data: dsi); |
1797 | |
1798 | dsi->pdev = pdev; |
1799 | #ifdef CONFIG_OF |
1800 | dsi->bridge.of_node = dev->of_node; |
1801 | #endif |
1802 | dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; |
1803 | dsi->dsi_host.ops = &vc4_dsi_host_ops; |
1804 | dsi->dsi_host.dev = dev; |
1805 | mipi_dsi_host_register(host: &dsi->dsi_host); |
1806 | |
1807 | return 0; |
1808 | } |
1809 | |
1810 | static void vc4_dsi_dev_remove(struct platform_device *pdev) |
1811 | { |
1812 | struct device *dev = &pdev->dev; |
1813 | struct vc4_dsi *dsi = dev_get_drvdata(dev); |
1814 | |
1815 | mipi_dsi_host_unregister(host: &dsi->dsi_host); |
1816 | } |
1817 | |
1818 | struct platform_driver vc4_dsi_driver = { |
1819 | .probe = vc4_dsi_dev_probe, |
1820 | .remove = vc4_dsi_dev_remove, |
1821 | .driver = { |
1822 | .name = "vc4_dsi", |
1823 | .of_match_table = vc4_dsi_dt_match, |
1824 | }, |
1825 | }; |
1826 |
Definitions
- vc4_dsi_variant
- vc4_dsi
- dsi_dma_workaround_write
- dsi0_regs
- dsi1_regs
- vc4_dsi_latch_ulps
- vc4_dsi_ulps
- dsi_hs_timing
- dsi_esc_timing
- vc4_dsi_bridge_disable
- vc4_dsi_bridge_post_disable
- vc4_dsi_bridge_mode_fixup
- vc4_dsi_bridge_pre_enable
- vc4_dsi_bridge_enable
- vc4_dsi_bridge_attach
- vc4_dsi_host_transfer
- vc4_dsi_ops
- vc4_dsi_host_attach
- vc4_dsi_host_detach
- vc4_dsi_host_ops
- vc4_dsi_bridge_funcs
- vc4_dsi_late_register
- vc4_dsi_encoder_funcs
- bcm2711_dsi1_variant
- bcm2835_dsi0_variant
- bcm2835_dsi1_variant
- vc4_dsi_dt_match
- dsi_handle_error
- vc4_dsi_irq_defer_to_thread_handler
- vc4_dsi_irq_handler
- vc4_dsi_init_phy_clocks
- vc4_dsi_dma_mem_release
- vc4_dsi_dma_chan_release
- vc4_dsi_release_action
- vc4_dsi_bind
- vc4_dsi_ops
- vc4_dsi_dev_probe
- vc4_dsi_dev_remove
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