1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4	/* ethtool support for ixgbe */
5
6	#include <linux/interrupt.h>
7	#include <linux/types.h>
8	#include <linux/module.h>
9	#include <linux/slab.h>
10	#include <linux/pci.h>
11	#include <linux/netdevice.h>
12	#include <linux/ethtool.h>
13	#include <linux/vmalloc.h>
14	#include <linux/highmem.h>
15	#include <linux/uaccess.h>
16
17	#include "ixgbe.h"
18	#include "ixgbe_phy.h"
19
20
21	enum {NETDEV_STATS, IXGBE_STATS};
22
23	struct ixgbe_stats {
24	char stat_string[ETH_GSTRING_LEN];
25	int type;
26	int sizeof_stat;
27	int stat_offset;
28	};
29
30	#define IXGBE_STAT(m) IXGBE_STATS, \
31	sizeof(((struct ixgbe_adapter *)0)->m), \
32	offsetof(struct ixgbe_adapter, m)
33	#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
34	sizeof(((struct rtnl_link_stats64 *)0)->m), \
35	offsetof(struct rtnl_link_stats64, m)
36
37	static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
38	{"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
39	{"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
40	{"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
41	{"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
42	{"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
43	{"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
44	{"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
45	{"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
46	{"lsc_int", IXGBE_STAT(lsc_int)},
47	{"tx_busy", IXGBE_STAT(tx_busy)},
48	{"non_eop_descs", IXGBE_STAT(non_eop_descs)},
49	{"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
50	{"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
51	{"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
52	{"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
53	{"multicast", IXGBE_NETDEV_STAT(multicast)},
54	{"broadcast", IXGBE_STAT(stats.bprc)},
55	{"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
56	{"collisions", IXGBE_NETDEV_STAT(collisions)},
57	{"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
58	{"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
59	{"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
60	{"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
61	{"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
62	{"fdir_match", IXGBE_STAT(stats.fdirmatch)},
63	{"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
64	{"fdir_overflow", IXGBE_STAT(fdir_overflow)},
65	{"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
66	{"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
67	{"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
68	{"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
69	{"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
70	{"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
71	{"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
72	{"tx_restart_queue", IXGBE_STAT(restart_queue)},
73	{"rx_length_errors", IXGBE_STAT(stats.rlec)},
74	{"rx_long_length_errors", IXGBE_STAT(stats.roc)},
75	{"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
76	{"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
77	{"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
78	{"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
79	{"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
80	{"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
81	{"alloc_rx_page", IXGBE_STAT(alloc_rx_page)},
82	{"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
83	{"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
84	{"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
85	{"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
86	{"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
87	{"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
88	{"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
89	{"tx_hwtstamp_timeouts", IXGBE_STAT(tx_hwtstamp_timeouts)},
90	{"tx_hwtstamp_skipped", IXGBE_STAT(tx_hwtstamp_skipped)},
91	{"rx_hwtstamp_cleared", IXGBE_STAT(rx_hwtstamp_cleared)},
92	{"tx_ipsec", IXGBE_STAT(tx_ipsec)},
93	{"rx_ipsec", IXGBE_STAT(rx_ipsec)},
94	#ifdef IXGBE_FCOE
95	{"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
96	{"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
97	{"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
98	{"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
99	{"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
100	{"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
101	{"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
102	{"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
103	#endif /* IXGBE_FCOE */
104	};
105
106	/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
107	* we set the num_rx_queues to evaluate to num_tx_queues. This is
108	* used because we do not have a good way to get the max number of
109	* rx queues with CONFIG_RPS disabled.
110	*/
111	#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
112
113	#define IXGBE_QUEUE_STATS_LEN ( \
114	(netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
115	(sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
116	#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
117	#define IXGBE_PB_STATS_LEN ( \
118	(sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
119	sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
120	sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
121	sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
122	/ sizeof(u64))
123	#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
124	IXGBE_PB_STATS_LEN + \
125	IXGBE_QUEUE_STATS_LEN)
126
127	static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
128	"Register test (offline)", "Eeprom test (offline)",
129	"Interrupt test (offline)", "Loopback test (offline)",
130	"Link test (on/offline)"
131	};
132	#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
133
134	static const char ixgbe_priv_flags_strings[][ETH_GSTRING_LEN] = {
135	#define IXGBE_PRIV_FLAGS_LEGACY_RX BIT(0)
136	"legacy-rx",
137	#define IXGBE_PRIV_FLAGS_VF_IPSEC_EN BIT(1)
138	"vf-ipsec",
139	#define IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF BIT(2)
140	"mdd-disable-vf",
141	};
142
143	#define IXGBE_PRIV_FLAGS_STR_LEN ARRAY_SIZE(ixgbe_priv_flags_strings)
144
145	#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
146
147	static void ixgbe_set_supported_10gtypes(struct ixgbe_hw *hw,
148	struct ethtool_link_ksettings *cmd)
149	{
150	if (!ixgbe_isbackplane(hw->phy.media_type)) {
151	ethtool_link_ksettings_add_link_mode(cmd, supported,
152	10000baseT_Full);
153	return;
154	}
155
156	switch (hw->device_id) {
157	case IXGBE_DEV_ID_82598:
158	case IXGBE_DEV_ID_82599_KX4:
159	case IXGBE_DEV_ID_82599_KX4_MEZZ:
160	case IXGBE_DEV_ID_X550EM_X_KX4:
161	ethtool_link_ksettings_add_link_mode
162	(cmd, supported, 10000baseKX4_Full);
163	break;
164	case IXGBE_DEV_ID_82598_BX:
165	case IXGBE_DEV_ID_82599_KR:
166	case IXGBE_DEV_ID_X550EM_X_KR:
167	case IXGBE_DEV_ID_X550EM_X_XFI:
168	ethtool_link_ksettings_add_link_mode
169	(cmd, supported, 10000baseKR_Full);
170	break;
171	default:
172	ethtool_link_ksettings_add_link_mode
173	(cmd, supported, 10000baseKX4_Full);
174	ethtool_link_ksettings_add_link_mode
175	(cmd, supported, 10000baseKR_Full);
176	break;
177	}
178	}
179
180	static void ixgbe_set_advertising_10gtypes(struct ixgbe_hw *hw,
181	struct ethtool_link_ksettings *cmd)
182	{
183	if (!ixgbe_isbackplane(hw->phy.media_type)) {
184	ethtool_link_ksettings_add_link_mode(cmd, advertising,
185	10000baseT_Full);
186	return;
187	}
188
189	switch (hw->device_id) {
190	case IXGBE_DEV_ID_82598:
191	case IXGBE_DEV_ID_82599_KX4:
192	case IXGBE_DEV_ID_82599_KX4_MEZZ:
193	case IXGBE_DEV_ID_X550EM_X_KX4:
194	ethtool_link_ksettings_add_link_mode
195	(cmd, advertising, 10000baseKX4_Full);
196	break;
197	case IXGBE_DEV_ID_82598_BX:
198	case IXGBE_DEV_ID_82599_KR:
199	case IXGBE_DEV_ID_X550EM_X_KR:
200	case IXGBE_DEV_ID_X550EM_X_XFI:
201	ethtool_link_ksettings_add_link_mode
202	(cmd, advertising, 10000baseKR_Full);
203	break;
204	default:
205	ethtool_link_ksettings_add_link_mode
206	(cmd, advertising, 10000baseKX4_Full);
207	ethtool_link_ksettings_add_link_mode
208	(cmd, advertising, 10000baseKR_Full);
209	break;
210	}
211	}
212
213	static int ixgbe_get_link_ksettings(struct net_device *netdev,
214	struct ethtool_link_ksettings *cmd)
215	{
216	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
217	struct ixgbe_hw *hw = &adapter->hw;
218	ixgbe_link_speed supported_link;
219	bool autoneg = false;
220
221	ethtool_link_ksettings_zero_link_mode(cmd, supported);
222	ethtool_link_ksettings_zero_link_mode(cmd, advertising);
223
224	hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
225
226	/* set the supported link speeds */
227	if (supported_link & IXGBE_LINK_SPEED_10GB_FULL) {
228	ixgbe_set_supported_10gtypes(hw, cmd);
229	ixgbe_set_advertising_10gtypes(hw, cmd);
230	}
231	if (supported_link & IXGBE_LINK_SPEED_5GB_FULL)
232	ethtool_link_ksettings_add_link_mode(cmd, supported,
233	5000baseT_Full);
234
235	if (supported_link & IXGBE_LINK_SPEED_2_5GB_FULL)
236	ethtool_link_ksettings_add_link_mode(cmd, supported,
237	2500baseT_Full);
238
239	if (supported_link & IXGBE_LINK_SPEED_1GB_FULL) {
240	if (ixgbe_isbackplane(hw->phy.media_type)) {
241	ethtool_link_ksettings_add_link_mode(cmd, supported,
242	1000baseKX_Full);
243	ethtool_link_ksettings_add_link_mode(cmd, advertising,
244	1000baseKX_Full);
245	} else {
246	ethtool_link_ksettings_add_link_mode(cmd, supported,
247	1000baseT_Full);
248	ethtool_link_ksettings_add_link_mode(cmd, advertising,
249	1000baseT_Full);
250	}
251	}
252	if (supported_link & IXGBE_LINK_SPEED_100_FULL) {
253	ethtool_link_ksettings_add_link_mode(cmd, supported,
254	100baseT_Full);
255	ethtool_link_ksettings_add_link_mode(cmd, advertising,
256	100baseT_Full);
257	}
258	if (supported_link & IXGBE_LINK_SPEED_10_FULL) {
259	ethtool_link_ksettings_add_link_mode(cmd, supported,
260	10baseT_Full);
261	ethtool_link_ksettings_add_link_mode(cmd, advertising,
262	10baseT_Full);
263	}
264
265	/* set the advertised speeds */
266	if (hw->phy.autoneg_advertised) {
267	ethtool_link_ksettings_zero_link_mode(cmd, advertising);
268	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL)
269	ethtool_link_ksettings_add_link_mode(cmd, advertising,
270	10baseT_Full);
271	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
272	ethtool_link_ksettings_add_link_mode(cmd, advertising,
273	100baseT_Full);
274	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
275	ixgbe_set_advertising_10gtypes(hw, cmd);
276	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
277	if (ethtool_link_ksettings_test_link_mode
278	(cmd, supported, 1000baseKX_Full))
279	ethtool_link_ksettings_add_link_mode
280	(cmd, advertising, 1000baseKX_Full);
281	else
282	ethtool_link_ksettings_add_link_mode
283	(cmd, advertising, 1000baseT_Full);
284	}
285	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL)
286	ethtool_link_ksettings_add_link_mode(cmd, advertising,
287	5000baseT_Full);
288	if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
289	ethtool_link_ksettings_add_link_mode(cmd, advertising,
290	2500baseT_Full);
291	} else {
292	if (hw->phy.multispeed_fiber && !autoneg) {
293	if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
294	ethtool_link_ksettings_add_link_mode
295	(cmd, advertising, 10000baseT_Full);
296	}
297	}
298
299	if (autoneg) {
300	ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
301	ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
302	cmd->base.autoneg = AUTONEG_ENABLE;
303	} else
304	cmd->base.autoneg = AUTONEG_DISABLE;
305
306	/* Determine the remaining settings based on the PHY type. */
307	switch (adapter->hw.phy.type) {
308	case ixgbe_phy_tn:
309	case ixgbe_phy_aq:
310	case ixgbe_phy_x550em_ext_t:
311	case ixgbe_phy_fw:
312	case ixgbe_phy_cu_unknown:
313	ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
314	ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
315	cmd->base.port = PORT_TP;
316	break;
317	case ixgbe_phy_qt:
318	ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
319	ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
320	cmd->base.port = PORT_FIBRE;
321	break;
322	case ixgbe_phy_nl:
323	case ixgbe_phy_sfp_passive_tyco:
324	case ixgbe_phy_sfp_passive_unknown:
325	case ixgbe_phy_sfp_ftl:
326	case ixgbe_phy_sfp_avago:
327	case ixgbe_phy_sfp_intel:
328	case ixgbe_phy_sfp_unknown:
329	case ixgbe_phy_qsfp_passive_unknown:
330	case ixgbe_phy_qsfp_active_unknown:
331	case ixgbe_phy_qsfp_intel:
332	case ixgbe_phy_qsfp_unknown:
333	/* SFP+ devices, further checking needed */
334	switch (adapter->hw.phy.sfp_type) {
335	case ixgbe_sfp_type_da_cu:
336	case ixgbe_sfp_type_da_cu_core0:
337	case ixgbe_sfp_type_da_cu_core1:
338	ethtool_link_ksettings_add_link_mode(cmd, supported,
339	FIBRE);
340	ethtool_link_ksettings_add_link_mode(cmd, advertising,
341	FIBRE);
342	cmd->base.port = PORT_DA;
343	break;
344	case ixgbe_sfp_type_sr:
345	case ixgbe_sfp_type_lr:
346	case ixgbe_sfp_type_srlr_core0:
347	case ixgbe_sfp_type_srlr_core1:
348	case ixgbe_sfp_type_1g_sx_core0:
349	case ixgbe_sfp_type_1g_sx_core1:
350	case ixgbe_sfp_type_1g_lx_core0:
351	case ixgbe_sfp_type_1g_lx_core1:
352	ethtool_link_ksettings_add_link_mode(cmd, supported,
353	FIBRE);
354	ethtool_link_ksettings_add_link_mode(cmd, advertising,
355	FIBRE);
356	cmd->base.port = PORT_FIBRE;
357	break;
358	case ixgbe_sfp_type_not_present:
359	ethtool_link_ksettings_add_link_mode(cmd, supported,
360	FIBRE);
361	ethtool_link_ksettings_add_link_mode(cmd, advertising,
362	FIBRE);
363	cmd->base.port = PORT_NONE;
364	break;
365	case ixgbe_sfp_type_1g_cu_core0:
366	case ixgbe_sfp_type_1g_cu_core1:
367	ethtool_link_ksettings_add_link_mode(cmd, supported,
368	TP);
369	ethtool_link_ksettings_add_link_mode(cmd, advertising,
370	TP);
371	cmd->base.port = PORT_TP;
372	break;
373	case ixgbe_sfp_type_unknown:
374	default:
375	ethtool_link_ksettings_add_link_mode(cmd, supported,
376	FIBRE);
377	ethtool_link_ksettings_add_link_mode(cmd, advertising,
378	FIBRE);
379	cmd->base.port = PORT_OTHER;
380	break;
381	}
382	break;
383	case ixgbe_phy_xaui:
384	ethtool_link_ksettings_add_link_mode(cmd, supported,
385	FIBRE);
386	ethtool_link_ksettings_add_link_mode(cmd, advertising,
387	FIBRE);
388	cmd->base.port = PORT_NONE;
389	break;
390	case ixgbe_phy_unknown:
391	case ixgbe_phy_generic:
392	case ixgbe_phy_sfp_unsupported:
393	default:
394	ethtool_link_ksettings_add_link_mode(cmd, supported,
395	FIBRE);
396	ethtool_link_ksettings_add_link_mode(cmd, advertising,
397	FIBRE);
398	cmd->base.port = PORT_OTHER;
399	break;
400	}
401
402	/* Indicate pause support */
403	ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
404
405	switch (hw->fc.requested_mode) {
406	case ixgbe_fc_full:
407	ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
408	break;
409	case ixgbe_fc_rx_pause:
410	ethtool_link_ksettings_add_link_mode(cmd, advertising, Pause);
411	ethtool_link_ksettings_add_link_mode(cmd, advertising,
412	Asym_Pause);
413	break;
414	case ixgbe_fc_tx_pause:
415	ethtool_link_ksettings_add_link_mode(cmd, advertising,
416	Asym_Pause);
417	break;
418	default:
419	ethtool_link_ksettings_del_link_mode(cmd, advertising, Pause);
420	ethtool_link_ksettings_del_link_mode(cmd, advertising,
421	Asym_Pause);
422	}
423
424	if (netif_carrier_ok(dev: netdev)) {
425	switch (adapter->link_speed) {
426	case IXGBE_LINK_SPEED_10GB_FULL:
427	cmd->base.speed = SPEED_10000;
428	break;
429	case IXGBE_LINK_SPEED_5GB_FULL:
430	cmd->base.speed = SPEED_5000;
431	break;
432	case IXGBE_LINK_SPEED_2_5GB_FULL:
433	cmd->base.speed = SPEED_2500;
434	break;
435	case IXGBE_LINK_SPEED_1GB_FULL:
436	cmd->base.speed = SPEED_1000;
437	break;
438	case IXGBE_LINK_SPEED_100_FULL:
439	cmd->base.speed = SPEED_100;
440	break;
441	case IXGBE_LINK_SPEED_10_FULL:
442	cmd->base.speed = SPEED_10;
443	break;
444	default:
445	break;
446	}
447	cmd->base.duplex = DUPLEX_FULL;
448	} else {
449	cmd->base.speed = SPEED_UNKNOWN;
450	cmd->base.duplex = DUPLEX_UNKNOWN;
451	}
452
453	return 0;
454	}
455
456	static int ixgbe_set_link_ksettings(struct net_device *netdev,
457	const struct ethtool_link_ksettings *cmd)
458	{
459	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
460	struct ixgbe_hw *hw = &adapter->hw;
461	u32 advertised, old;
462	s32 err = 0;
463
464	if ((hw->phy.media_type == ixgbe_media_type_copper) ||
465	(hw->phy.multispeed_fiber)) {
466	/*
467	* this function does not support duplex forcing, but can
468	* limit the advertising of the adapter to the specified speed
469	*/
470	if (!linkmode_subset(src1: cmd->link_modes.advertising,
471	src2: cmd->link_modes.supported))
472	return -EINVAL;
473
474	/* only allow one speed at a time if no autoneg */
475	if (!cmd->base.autoneg && hw->phy.multispeed_fiber) {
476	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
477	10000baseT_Full) &&
478	ethtool_link_ksettings_test_link_mode(cmd, advertising,
479	1000baseT_Full))
480	return -EINVAL;
481	}
482
483	old = hw->phy.autoneg_advertised;
484	advertised = 0;
485	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
486	10000baseT_Full))
487	advertised |= IXGBE_LINK_SPEED_10GB_FULL;
488	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
489	5000baseT_Full))
490	advertised |= IXGBE_LINK_SPEED_5GB_FULL;
491	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
492	2500baseT_Full))
493	advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
494	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
495	1000baseT_Full))
496	advertised |= IXGBE_LINK_SPEED_1GB_FULL;
497
498	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
499	100baseT_Full))
500	advertised |= IXGBE_LINK_SPEED_100_FULL;
501
502	if (ethtool_link_ksettings_test_link_mode(cmd, advertising,
503	10baseT_Full))
504	advertised |= IXGBE_LINK_SPEED_10_FULL;
505
506	if (old == advertised)
507	return err;
508	/* this sets the link speed and restarts auto-neg */
509	while (test_and_set_bit(nr: __IXGBE_IN_SFP_INIT, addr: &adapter->state))
510	usleep_range(min: 1000, max: 2000);
511
512	hw->mac.autotry_restart = true;
513	err = hw->mac.ops.setup_link(hw, advertised, true);
514	if (err) {
515	e_info(probe, "setup link failed with code %d\n", err);
516	hw->mac.ops.setup_link(hw, old, true);
517	}
518	clear_bit(nr: __IXGBE_IN_SFP_INIT, addr: &adapter->state);
519	} else {
520	/* in this case we currently only support 10Gb/FULL */
521	u32 speed = cmd->base.speed;
522
523	if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
524	(!ethtool_link_ksettings_test_link_mode(cmd, advertising,
525	10000baseT_Full)) ||
526	(speed + cmd->base.duplex != SPEED_10000 + DUPLEX_FULL))
527	return -EINVAL;
528	}
529
530	return err;
531	}
532
533	static void ixgbe_get_pause_stats(struct net_device *netdev,
534	struct ethtool_pause_stats *stats)
535	{
536	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
537	struct ixgbe_hw_stats *hwstats = &adapter->stats;
538
539	stats->tx_pause_frames = hwstats->lxontxc + hwstats->lxofftxc;
540	stats->rx_pause_frames = hwstats->lxonrxc + hwstats->lxoffrxc;
541	}
542
543	static void ixgbe_get_pauseparam(struct net_device *netdev,
544	struct ethtool_pauseparam *pause)
545	{
546	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
547	struct ixgbe_hw *hw = &adapter->hw;
548
549	if (ixgbe_device_supports_autoneg_fc(hw) &&
550	!hw->fc.disable_fc_autoneg)
551	pause->autoneg = 1;
552	else
553	pause->autoneg = 0;
554
555	if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
556	pause->rx_pause = 1;
557	} else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
558	pause->tx_pause = 1;
559	} else if (hw->fc.current_mode == ixgbe_fc_full) {
560	pause->rx_pause = 1;
561	pause->tx_pause = 1;
562	}
563	}
564
565	static int ixgbe_set_pauseparam(struct net_device *netdev,
566	struct ethtool_pauseparam *pause)
567	{
568	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
569	struct ixgbe_hw *hw = &adapter->hw;
570	struct ixgbe_fc_info fc = hw->fc;
571
572	/* 82598 does no support link flow control with DCB enabled */
573	if ((hw->mac.type == ixgbe_mac_82598EB) &&
574	(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
575	return -EINVAL;
576
577	/* some devices do not support autoneg of link flow control */
578	if ((pause->autoneg == AUTONEG_ENABLE) &&
579	!ixgbe_device_supports_autoneg_fc(hw))
580	return -EINVAL;
581
582	fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
583
584	if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
585	fc.requested_mode = ixgbe_fc_full;
586	else if (pause->rx_pause && !pause->tx_pause)
587	fc.requested_mode = ixgbe_fc_rx_pause;
588	else if (!pause->rx_pause && pause->tx_pause)
589	fc.requested_mode = ixgbe_fc_tx_pause;
590	else
591	fc.requested_mode = ixgbe_fc_none;
592
593	/* if the thing changed then we'll update and use new autoneg */
594	if (memcmp(p: &fc, q: &hw->fc, size: sizeof(struct ixgbe_fc_info))) {
595	hw->fc = fc;
596	if (netif_running(dev: netdev))
597	ixgbe_reinit_locked(adapter);
598	else
599	ixgbe_reset(adapter);
600	}
601
602	return 0;
603	}
604
605	static u32 ixgbe_get_msglevel(struct net_device *netdev)
606	{
607	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
608	return adapter->msg_enable;
609	}
610
611	static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
612	{
613	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
614	adapter->msg_enable = data;
615	}
616
617	static int ixgbe_get_regs_len(struct net_device *netdev)
618	{
619	#define IXGBE_REGS_LEN 1145
620	return IXGBE_REGS_LEN * sizeof(u32);
621	}
622
623	#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
624
625	static void ixgbe_get_regs(struct net_device *netdev,
626	struct ethtool_regs *regs, void *p)
627	{
628	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
629	struct ixgbe_hw *hw = &adapter->hw;
630	u32 *regs_buff = p;
631	u8 i;
632
633	memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
634
635	regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
636	hw->device_id;
637
638	/* General Registers */
639	regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
640	regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
641	regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
642	regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
643	regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
644	regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
645	regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
646	regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
647
648	/* NVM Register */
649	regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
650	regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
651	regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
652	regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
653	regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
654	regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
655	regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
656	regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
657	regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
658	regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
659
660	/* Interrupt */
661	/* don't read EICR because it can clear interrupt causes, instead
662	* read EICS which is a shadow but doesn't clear EICR */
663	regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
664	regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
665	regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
666	regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
667	regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
668	regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
669	regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
670	regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
671	regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
672	regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
673	regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
674	regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
675
676	/* Flow Control */
677	regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
678	for (i = 0; i < 4; i++)
679	regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
680	for (i = 0; i < 8; i++) {
681	switch (hw->mac.type) {
682	case ixgbe_mac_82598EB:
683	regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
684	regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
685	break;
686	case ixgbe_mac_82599EB:
687	case ixgbe_mac_X540:
688	case ixgbe_mac_X550:
689	case ixgbe_mac_X550EM_x:
690	case ixgbe_mac_x550em_a:
691	regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
692	regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
693	break;
694	default:
695	break;
696	}
697	}
698	regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
699	regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
700
701	/* Receive DMA */
702	for (i = 0; i < 64; i++)
703	regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
704	for (i = 0; i < 64; i++)
705	regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
706	for (i = 0; i < 64; i++)
707	regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
708	for (i = 0; i < 64; i++)
709	regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
710	for (i = 0; i < 64; i++)
711	regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
712	for (i = 0; i < 64; i++)
713	regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
714	for (i = 0; i < 16; i++)
715	regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
716	for (i = 0; i < 16; i++)
717	regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
718	regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
719	for (i = 0; i < 8; i++)
720	regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
721	regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
722	regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
723
724	/* Receive */
725	regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
726	regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
727	for (i = 0; i < 16; i++)
728	regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
729	for (i = 0; i < 16; i++)
730	regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
731	regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
732	regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
733	regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
734	regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
735	regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
736	regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
737	for (i = 0; i < 8; i++)
738	regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
739	for (i = 0; i < 8; i++)
740	regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
741	regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
742
743	/* Transmit */
744	for (i = 0; i < 32; i++)
745	regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
746	for (i = 0; i < 32; i++)
747	regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
748	for (i = 0; i < 32; i++)
749	regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
750	for (i = 0; i < 32; i++)
751	regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
752	for (i = 0; i < 32; i++)
753	regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
754	for (i = 0; i < 32; i++)
755	regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
756	for (i = 0; i < 32; i++)
757	regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
758	for (i = 0; i < 32; i++)
759	regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
760	regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
761	for (i = 0; i < 16; i++)
762	regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
763	regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
764	for (i = 0; i < 8; i++)
765	regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
766	regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
767
768	/* Wake Up */
769	regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
770	regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
771	regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
772	regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
773	regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
774	regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
775	regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
776	regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
777	regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
778
779	/* DCB */
780	regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
781	regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
782
783	switch (hw->mac.type) {
784	case ixgbe_mac_82598EB:
785	regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
786	regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
787	for (i = 0; i < 8; i++)
788	regs_buff[833 + i] =
789	IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
790	for (i = 0; i < 8; i++)
791	regs_buff[841 + i] =
792	IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
793	for (i = 0; i < 8; i++)
794	regs_buff[849 + i] =
795	IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
796	for (i = 0; i < 8; i++)
797	regs_buff[857 + i] =
798	IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
799	break;
800	case ixgbe_mac_82599EB:
801	case ixgbe_mac_X540:
802	case ixgbe_mac_X550:
803	case ixgbe_mac_X550EM_x:
804	case ixgbe_mac_x550em_a:
805	regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
806	regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
807	for (i = 0; i < 8; i++)
808	regs_buff[833 + i] =
809	IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
810	for (i = 0; i < 8; i++)
811	regs_buff[841 + i] =
812	IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
813	for (i = 0; i < 8; i++)
814	regs_buff[849 + i] =
815	IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
816	for (i = 0; i < 8; i++)
817	regs_buff[857 + i] =
818	IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
819	break;
820	default:
821	break;
822	}
823
824	for (i = 0; i < 8; i++)
825	regs_buff[865 + i] =
826	IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
827	for (i = 0; i < 8; i++)
828	regs_buff[873 + i] =
829	IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
830
831	/* Statistics */
832	regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
833	regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
834	regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
835	regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
836	for (i = 0; i < 8; i++)
837	regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
838	regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
839	regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
840	regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
841	regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
842	regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
843	regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
844	regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
845	for (i = 0; i < 8; i++)
846	regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
847	for (i = 0; i < 8; i++)
848	regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
849	for (i = 0; i < 8; i++)
850	regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
851	for (i = 0; i < 8; i++)
852	regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
853	regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
854	regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
855	regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
856	regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
857	regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
858	regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
859	regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
860	regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
861	regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
862	regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
863	regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
864	regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
865	regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
866	regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
867	for (i = 0; i < 8; i++)
868	regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
869	regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
870	regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
871	regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
872	regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
873	regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
874	regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
875	regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
876	regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
877	regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
878	regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
879	regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
880	regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
881	regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
882	regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
883	regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
884	regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
885	regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
886	regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
887	regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
888	regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
889	for (i = 0; i < 16; i++)
890	regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
891	for (i = 0; i < 16; i++)
892	regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
893	for (i = 0; i < 16; i++)
894	regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
895	for (i = 0; i < 16; i++)
896	regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
897
898	/* MAC */
899	regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
900	regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
901	regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
902	regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
903	regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
904	regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
905	regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
906	regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
907	regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
908	regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
909	regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
910	regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
911	regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
912	regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
913	regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
914	regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
915	regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
916	regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
917	regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
918	regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
919	regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
920	regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
921	regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
922	regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
923	regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
924	regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
925	regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
926	regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
927	regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
928	regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
929	regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
930	regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
931	regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
932
933	/* Diagnostic */
934	regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
935	for (i = 0; i < 8; i++)
936	regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
937	regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
938	for (i = 0; i < 4; i++)
939	regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
940	regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
941	regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
942	for (i = 0; i < 8; i++)
943	regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
944	regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
945	for (i = 0; i < 4; i++)
946	regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
947	regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
948	regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
949	for (i = 0; i < 4; i++)
950	regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
951	regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
952	for (i = 0; i < 4; i++)
953	regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
954	for (i = 0; i < 8; i++)
955	regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
956	regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
957	regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
958	regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
959	regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
960	regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
961	regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
962	regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
963	regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
964	regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
965
966	/* 82599 X540 specific registers */
967	regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
968
969	/* 82599 X540 specific DCB registers */
970	regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
971	regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
972	for (i = 0; i < 4; i++)
973	regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
974	regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
975	/* same as RTTQCNRM */
976	regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
977	/* same as RTTQCNRR */
978
979	/* X540 specific DCB registers */
980	regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
981	regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
982
983	/* Security config registers */
984	regs_buff[1139] = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
985	regs_buff[1140] = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
986	regs_buff[1141] = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
987	regs_buff[1142] = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
988	regs_buff[1143] = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
989	regs_buff[1144] = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
990	}
991
992	static int ixgbe_get_eeprom_len(struct net_device *netdev)
993	{
994	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
995	return adapter->hw.eeprom.word_size * 2;
996	}
997
998	static int ixgbe_get_eeprom(struct net_device *netdev,
999	struct ethtool_eeprom *eeprom, u8 *bytes)
1000	{
1001	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1002	struct ixgbe_hw *hw = &adapter->hw;
1003	u16 *eeprom_buff;
1004	int first_word, last_word, eeprom_len;
1005	int ret_val = 0;
1006	u16 i;
1007
1008	if (eeprom->len == 0)
1009	return -EINVAL;
1010
1011	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1012
1013	first_word = eeprom->offset >> 1;
1014	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1015	eeprom_len = last_word - first_word + 1;
1016
1017	eeprom_buff = kmalloc_array(n: eeprom_len, size: sizeof(u16), GFP_KERNEL);
1018	if (!eeprom_buff)
1019	return -ENOMEM;
1020
1021	ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
1022	eeprom_buff);
1023
1024	/* Device's eeprom is always little-endian, word addressable */
1025	for (i = 0; i < eeprom_len; i++)
1026	le16_to_cpus(&eeprom_buff[i]);
1027
1028	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
1029	kfree(objp: eeprom_buff);
1030
1031	return ret_val;
1032	}
1033
1034	static int ixgbe_set_eeprom(struct net_device *netdev,
1035	struct ethtool_eeprom *eeprom, u8 *bytes)
1036	{
1037	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1038	struct ixgbe_hw *hw = &adapter->hw;
1039	u16 *eeprom_buff;
1040	void *ptr;
1041	int max_len, first_word, last_word, ret_val = 0;
1042	u16 i;
1043
1044	if (eeprom->len == 0)
1045	return -EINVAL;
1046
1047	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
1048	return -EINVAL;
1049
1050	max_len = hw->eeprom.word_size * 2;
1051
1052	first_word = eeprom->offset >> 1;
1053	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
1054	eeprom_buff = kmalloc(size: max_len, GFP_KERNEL);
1055	if (!eeprom_buff)
1056	return -ENOMEM;
1057
1058	ptr = eeprom_buff;
1059
1060	if (eeprom->offset & 1) {
1061	/*
1062	* need read/modify/write of first changed EEPROM word
1063	* only the second byte of the word is being modified
1064	*/
1065	ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
1066	if (ret_val)
1067	goto err;
1068
1069	ptr++;
1070	}
1071	if ((eeprom->offset + eeprom->len) & 1) {
1072	/*
1073	* need read/modify/write of last changed EEPROM word
1074	* only the first byte of the word is being modified
1075	*/
1076	ret_val = hw->eeprom.ops.read(hw, last_word,
1077	&eeprom_buff[last_word - first_word]);
1078	if (ret_val)
1079	goto err;
1080	}
1081
1082	/* Device's eeprom is always little-endian, word addressable */
1083	for (i = 0; i < last_word - first_word + 1; i++)
1084	le16_to_cpus(&eeprom_buff[i]);
1085
1086	memcpy(ptr, bytes, eeprom->len);
1087
1088	for (i = 0; i < last_word - first_word + 1; i++)
1089	cpu_to_le16s(&eeprom_buff[i]);
1090
1091	ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
1092	last_word - first_word + 1,
1093	eeprom_buff);
1094
1095	/* Update the checksum */
1096	if (ret_val == 0)
1097	hw->eeprom.ops.update_checksum(hw);
1098
1099	err:
1100	kfree(objp: eeprom_buff);
1101	return ret_val;
1102	}
1103
1104	static void ixgbe_get_drvinfo(struct net_device *netdev,
1105	struct ethtool_drvinfo *drvinfo)
1106	{
1107	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1108
1109	strscpy(p: drvinfo->driver, q: ixgbe_driver_name, size: sizeof(drvinfo->driver));
1110
1111	strscpy(p: drvinfo->fw_version, q: adapter->eeprom_id,
1112	size: sizeof(drvinfo->fw_version));
1113
1114	strscpy(p: drvinfo->bus_info, q: pci_name(pdev: adapter->pdev),
1115	size: sizeof(drvinfo->bus_info));
1116
1117	drvinfo->n_priv_flags = IXGBE_PRIV_FLAGS_STR_LEN;
1118	}
1119
1120	static u32 ixgbe_get_max_rxd(struct ixgbe_adapter *adapter)
1121	{
1122	switch (adapter->hw.mac.type) {
1123	case ixgbe_mac_82598EB:
1124	return IXGBE_MAX_RXD_82598;
1125	case ixgbe_mac_82599EB:
1126	return IXGBE_MAX_RXD_82599;
1127	case ixgbe_mac_X540:
1128	return IXGBE_MAX_RXD_X540;
1129	case ixgbe_mac_X550:
1130	case ixgbe_mac_X550EM_x:
1131	case ixgbe_mac_x550em_a:
1132	return IXGBE_MAX_RXD_X550;
1133	default:
1134	return IXGBE_MAX_RXD_82598;
1135	}
1136	}
1137
1138	static u32 ixgbe_get_max_txd(struct ixgbe_adapter *adapter)
1139	{
1140	switch (adapter->hw.mac.type) {
1141	case ixgbe_mac_82598EB:
1142	return IXGBE_MAX_TXD_82598;
1143	case ixgbe_mac_82599EB:
1144	return IXGBE_MAX_TXD_82599;
1145	case ixgbe_mac_X540:
1146	return IXGBE_MAX_TXD_X540;
1147	case ixgbe_mac_X550:
1148	case ixgbe_mac_X550EM_x:
1149	case ixgbe_mac_x550em_a:
1150	return IXGBE_MAX_TXD_X550;
1151	default:
1152	return IXGBE_MAX_TXD_82598;
1153	}
1154	}
1155
1156	static void ixgbe_get_ringparam(struct net_device *netdev,
1157	struct ethtool_ringparam *ring,
1158	struct kernel_ethtool_ringparam *kernel_ring,
1159	struct netlink_ext_ack *extack)
1160	{
1161	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1162	struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
1163	struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
1164
1165	ring->rx_max_pending = ixgbe_get_max_rxd(adapter);
1166	ring->tx_max_pending = ixgbe_get_max_txd(adapter);
1167	ring->rx_pending = rx_ring->count;
1168	ring->tx_pending = tx_ring->count;
1169	}
1170
1171	static int ixgbe_set_ringparam(struct net_device *netdev,
1172	struct ethtool_ringparam *ring,
1173	struct kernel_ethtool_ringparam *kernel_ring,
1174	struct netlink_ext_ack *extack)
1175	{
1176	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1177	struct ixgbe_ring *temp_ring;
1178	int i, j, err = 0;
1179	u32 new_rx_count, new_tx_count;
1180
1181	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1182	return -EINVAL;
1183
1184	new_tx_count = clamp_t(u32, ring->tx_pending,
1185	IXGBE_MIN_TXD, ixgbe_get_max_txd(adapter));
1186	new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1187
1188	new_rx_count = clamp_t(u32, ring->rx_pending,
1189	IXGBE_MIN_RXD, ixgbe_get_max_rxd(adapter));
1190	new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1191
1192	if ((new_tx_count == adapter->tx_ring_count) &&
1193	(new_rx_count == adapter->rx_ring_count)) {
1194	/* nothing to do */
1195	return 0;
1196	}
1197
1198	while (test_and_set_bit(nr: __IXGBE_RESETTING, addr: &adapter->state))
1199	usleep_range(min: 1000, max: 2000);
1200
1201	if (!netif_running(dev: adapter->netdev)) {
1202	for (i = 0; i < adapter->num_tx_queues; i++)
1203	adapter->tx_ring[i]->count = new_tx_count;
1204	for (i = 0; i < adapter->num_xdp_queues; i++)
1205	adapter->xdp_ring[i]->count = new_tx_count;
1206	for (i = 0; i < adapter->num_rx_queues; i++)
1207	adapter->rx_ring[i]->count = new_rx_count;
1208	adapter->tx_ring_count = new_tx_count;
1209	adapter->xdp_ring_count = new_tx_count;
1210	adapter->rx_ring_count = new_rx_count;
1211	goto clear_reset;
1212	}
1213
1214	/* allocate temporary buffer to store rings in */
1215	i = max_t(int, adapter->num_tx_queues + adapter->num_xdp_queues,
1216	adapter->num_rx_queues);
1217	temp_ring = vmalloc(array_size(i, sizeof(struct ixgbe_ring)));
1218
1219	if (!temp_ring) {
1220	err = -ENOMEM;
1221	goto clear_reset;
1222	}
1223
1224	ixgbe_down(adapter);
1225
1226	/*
1227	* Setup new Tx resources and free the old Tx resources in that order.
1228	* We can then assign the new resources to the rings via a memcpy.
1229	* The advantage to this approach is that we are guaranteed to still
1230	* have resources even in the case of an allocation failure.
1231	*/
1232	if (new_tx_count != adapter->tx_ring_count) {
1233	for (i = 0; i < adapter->num_tx_queues; i++) {
1234	memcpy(&temp_ring[i], adapter->tx_ring[i],
1235	sizeof(struct ixgbe_ring));
1236
1237	temp_ring[i].count = new_tx_count;
1238	err = ixgbe_setup_tx_resources(&temp_ring[i]);
1239	if (err) {
1240	while (i) {
1241	i--;
1242	ixgbe_free_tx_resources(&temp_ring[i]);
1243	}
1244	goto err_setup;
1245	}
1246	}
1247
1248	for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1249	memcpy(&temp_ring[i], adapter->xdp_ring[j],
1250	sizeof(struct ixgbe_ring));
1251
1252	temp_ring[i].count = new_tx_count;
1253	err = ixgbe_setup_tx_resources(&temp_ring[i]);
1254	if (err) {
1255	while (i) {
1256	i--;
1257	ixgbe_free_tx_resources(&temp_ring[i]);
1258	}
1259	goto err_setup;
1260	}
1261	}
1262
1263	for (i = 0; i < adapter->num_tx_queues; i++) {
1264	ixgbe_free_tx_resources(adapter->tx_ring[i]);
1265
1266	memcpy(adapter->tx_ring[i], &temp_ring[i],
1267	sizeof(struct ixgbe_ring));
1268	}
1269	for (j = 0; j < adapter->num_xdp_queues; j++, i++) {
1270	ixgbe_free_tx_resources(adapter->xdp_ring[j]);
1271
1272	memcpy(adapter->xdp_ring[j], &temp_ring[i],
1273	sizeof(struct ixgbe_ring));
1274	}
1275
1276	adapter->tx_ring_count = new_tx_count;
1277	}
1278
1279	/* Repeat the process for the Rx rings if needed */
1280	if (new_rx_count != adapter->rx_ring_count) {
1281	for (i = 0; i < adapter->num_rx_queues; i++) {
1282	memcpy(&temp_ring[i], adapter->rx_ring[i],
1283	sizeof(struct ixgbe_ring));
1284
1285	/* Clear copied XDP RX-queue info */
1286	memset(&temp_ring[i].xdp_rxq, 0,
1287	sizeof(temp_ring[i].xdp_rxq));
1288
1289	temp_ring[i].count = new_rx_count;
1290	err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
1291	if (err) {
1292	while (i) {
1293	i--;
1294	ixgbe_free_rx_resources(&temp_ring[i]);
1295	}
1296	goto err_setup;
1297	}
1298
1299	}
1300
1301	for (i = 0; i < adapter->num_rx_queues; i++) {
1302	ixgbe_free_rx_resources(adapter->rx_ring[i]);
1303
1304	memcpy(adapter->rx_ring[i], &temp_ring[i],
1305	sizeof(struct ixgbe_ring));
1306	}
1307
1308	adapter->rx_ring_count = new_rx_count;
1309	}
1310
1311	err_setup:
1312	ixgbe_up(adapter);
1313	vfree(addr: temp_ring);
1314	clear_reset:
1315	clear_bit(nr: __IXGBE_RESETTING, addr: &adapter->state);
1316	return err;
1317	}
1318
1319	static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1320	{
1321	switch (sset) {
1322	case ETH_SS_TEST:
1323	return IXGBE_TEST_LEN;
1324	case ETH_SS_STATS:
1325	return IXGBE_STATS_LEN;
1326	case ETH_SS_PRIV_FLAGS:
1327	return IXGBE_PRIV_FLAGS_STR_LEN;
1328	default:
1329	return -EOPNOTSUPP;
1330	}
1331	}
1332
1333	static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1334	struct ethtool_stats *stats, u64 *data)
1335	{
1336	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1337	struct rtnl_link_stats64 temp;
1338	const struct rtnl_link_stats64 *net_stats;
1339	unsigned int start;
1340	struct ixgbe_ring *ring;
1341	int i, j;
1342	char *p = NULL;
1343
1344	ixgbe_update_stats(adapter);
1345	net_stats = dev_get_stats(dev: netdev, storage: &temp);
1346	for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1347	switch (ixgbe_gstrings_stats[i].type) {
1348	case NETDEV_STATS:
1349	p = (char *) net_stats +
1350	ixgbe_gstrings_stats[i].stat_offset;
1351	break;
1352	case IXGBE_STATS:
1353	p = (char *) adapter +
1354	ixgbe_gstrings_stats[i].stat_offset;
1355	break;
1356	default:
1357	data[i] = 0;
1358	continue;
1359	}
1360
1361	data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1362	sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1363	}
1364	for (j = 0; j < netdev->num_tx_queues; j++) {
1365	ring = adapter->tx_ring[j];
1366	if (!ring) {
1367	data[i] = 0;
1368	data[i+1] = 0;
1369	i += 2;
1370	continue;
1371	}
1372
1373	do {
1374	start = u64_stats_fetch_begin(syncp: &ring->syncp);
1375	data[i] = ring->stats.packets;
1376	data[i+1] = ring->stats.bytes;
1377	} while (u64_stats_fetch_retry(syncp: &ring->syncp, start));
1378	i += 2;
1379	}
1380	for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1381	ring = adapter->rx_ring[j];
1382	if (!ring) {
1383	data[i] = 0;
1384	data[i+1] = 0;
1385	i += 2;
1386	continue;
1387	}
1388
1389	do {
1390	start = u64_stats_fetch_begin(syncp: &ring->syncp);
1391	data[i] = ring->stats.packets;
1392	data[i+1] = ring->stats.bytes;
1393	} while (u64_stats_fetch_retry(syncp: &ring->syncp, start));
1394	i += 2;
1395	}
1396
1397	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1398	data[i++] = adapter->stats.pxontxc[j];
1399	data[i++] = adapter->stats.pxofftxc[j];
1400	}
1401	for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1402	data[i++] = adapter->stats.pxonrxc[j];
1403	data[i++] = adapter->stats.pxoffrxc[j];
1404	}
1405	}
1406
1407	static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1408	u8 *data)
1409	{
1410	unsigned int i;
1411	u8 *p = data;
1412
1413	switch (stringset) {
1414	case ETH_SS_TEST:
1415	for (i = 0; i < IXGBE_TEST_LEN; i++)
1416	ethtool_sprintf(data: &p, fmt: "%s", ixgbe_gstrings_test[i]);
1417	break;
1418	case ETH_SS_STATS:
1419	for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++)
1420	ethtool_sprintf(data: &p, fmt: "%s",
1421	ixgbe_gstrings_stats[i].stat_string);
1422	for (i = 0; i < netdev->num_tx_queues; i++) {
1423	ethtool_sprintf(data: &p, fmt: "tx_queue_%u_packets", i);
1424	ethtool_sprintf(data: &p, fmt: "tx_queue_%u_bytes", i);
1425	}
1426	for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1427	ethtool_sprintf(data: &p, fmt: "rx_queue_%u_packets", i);
1428	ethtool_sprintf(data: &p, fmt: "rx_queue_%u_bytes", i);
1429	}
1430	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1431	ethtool_sprintf(data: &p, fmt: "tx_pb_%u_pxon", i);
1432	ethtool_sprintf(data: &p, fmt: "tx_pb_%u_pxoff", i);
1433	}
1434	for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1435	ethtool_sprintf(data: &p, fmt: "rx_pb_%u_pxon", i);
1436	ethtool_sprintf(data: &p, fmt: "rx_pb_%u_pxoff", i);
1437	}
1438	/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1439	break;
1440	case ETH_SS_PRIV_FLAGS:
1441	memcpy(data, ixgbe_priv_flags_strings,
1442	IXGBE_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
1443	}
1444	}
1445
1446	static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1447	{
1448	struct ixgbe_hw *hw = &adapter->hw;
1449	bool link_up;
1450	u32 link_speed = 0;
1451
1452	if (ixgbe_removed(addr: hw->hw_addr)) {
1453	*data = 1;
1454	return 1;
1455	}
1456	*data = 0;
1457
1458	hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1459	if (link_up)
1460	return *data;
1461	else
1462	*data = 1;
1463	return *data;
1464	}
1465
1466	/* ethtool register test data */
1467	struct ixgbe_reg_test {
1468	u16 reg;
1469	u8 array_len;
1470	u8 test_type;
1471	u32 mask;
1472	u32 write;
1473	};
1474
1475	/* In the hardware, registers are laid out either singly, in arrays
1476	* spaced 0x40 bytes apart, or in contiguous tables. We assume
1477	* most tests take place on arrays or single registers (handled
1478	* as a single-element array) and special-case the tables.
1479	* Table tests are always pattern tests.
1480	*
1481	* We also make provision for some required setup steps by specifying
1482	* registers to be written without any read-back testing.
1483	*/
1484
1485	#define PATTERN_TEST 1
1486	#define SET_READ_TEST 2
1487	#define WRITE_NO_TEST 3
1488	#define TABLE32_TEST 4
1489	#define TABLE64_TEST_LO 5
1490	#define TABLE64_TEST_HI 6
1491
1492	/* default 82599 register test */
1493	static const struct ixgbe_reg_test reg_test_82599[] = {
1494	{ IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1495	{ IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1496	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1497	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1498	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1499	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1500	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1501	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1502	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1503	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1504	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1505	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1506	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1507	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1508	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1509	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1510	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1511	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1512	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1513	{ .reg = 0 }
1514	};
1515
1516	/* default 82598 register test */
1517	static const struct ixgbe_reg_test reg_test_82598[] = {
1518	{ IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1519	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1520	{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1521	{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1522	{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1523	{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1524	{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1525	/* Enable all four RX queues before testing. */
1526	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1527	/* RDH is read-only for 82598, only test RDT. */
1528	{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1529	{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1530	{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1531	{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1532	{ IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1533	{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1534	{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1535	{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1536	{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1537	{ IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1538	{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1539	{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1540	{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1541	{ .reg = 0 }
1542	};
1543
1544	static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1545	u32 mask, u32 write)
1546	{
1547	u32 pat, val, before;
1548	static const u32 test_pattern[] = {
1549	0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1550
1551	if (ixgbe_removed(addr: adapter->hw.hw_addr)) {
1552	*data = 1;
1553	return true;
1554	}
1555	for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1556	before = ixgbe_read_reg(hw: &adapter->hw, reg);
1557	ixgbe_write_reg(hw: &adapter->hw, reg, value: test_pattern[pat] & write);
1558	val = ixgbe_read_reg(hw: &adapter->hw, reg);
1559	if (val != (test_pattern[pat] & write & mask)) {
1560	e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1561	reg, val, (test_pattern[pat] & write & mask));
1562	*data = reg;
1563	ixgbe_write_reg(hw: &adapter->hw, reg, value: before);
1564	return true;
1565	}
1566	ixgbe_write_reg(hw: &adapter->hw, reg, value: before);
1567	}
1568	return false;
1569	}
1570
1571	static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1572	u32 mask, u32 write)
1573	{
1574	u32 val, before;
1575
1576	if (ixgbe_removed(addr: adapter->hw.hw_addr)) {
1577	*data = 1;
1578	return true;
1579	}
1580	before = ixgbe_read_reg(hw: &adapter->hw, reg);
1581	ixgbe_write_reg(hw: &adapter->hw, reg, value: write & mask);
1582	val = ixgbe_read_reg(hw: &adapter->hw, reg);
1583	if ((write & mask) != (val & mask)) {
1584	e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1585	reg, (val & mask), (write & mask));
1586	*data = reg;
1587	ixgbe_write_reg(hw: &adapter->hw, reg, value: before);
1588	return true;
1589	}
1590	ixgbe_write_reg(hw: &adapter->hw, reg, value: before);
1591	return false;
1592	}
1593
1594	static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1595	{
1596	const struct ixgbe_reg_test *test;
1597	u32 value, before, after;
1598	u32 i, toggle;
1599
1600	if (ixgbe_removed(addr: adapter->hw.hw_addr)) {
1601	e_err(drv, "Adapter removed - register test blocked\n");
1602	*data = 1;
1603	return 1;
1604	}
1605	switch (adapter->hw.mac.type) {
1606	case ixgbe_mac_82598EB:
1607	toggle = 0x7FFFF3FF;
1608	test = reg_test_82598;
1609	break;
1610	case ixgbe_mac_82599EB:
1611	case ixgbe_mac_X540:
1612	case ixgbe_mac_X550:
1613	case ixgbe_mac_X550EM_x:
1614	case ixgbe_mac_x550em_a:
1615	toggle = 0x7FFFF30F;
1616	test = reg_test_82599;
1617	break;
1618	default:
1619	*data = 1;
1620	return 1;
1621	}
1622
1623	/*
1624	* Because the status register is such a special case,
1625	* we handle it separately from the rest of the register
1626	* tests. Some bits are read-only, some toggle, and some
1627	* are writeable on newer MACs.
1628	*/
1629	before = ixgbe_read_reg(hw: &adapter->hw, IXGBE_STATUS);
1630	value = (ixgbe_read_reg(hw: &adapter->hw, IXGBE_STATUS) & toggle);
1631	ixgbe_write_reg(hw: &adapter->hw, IXGBE_STATUS, value: toggle);
1632	after = ixgbe_read_reg(hw: &adapter->hw, IXGBE_STATUS) & toggle;
1633	if (value != after) {
1634	e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1635	after, value);
1636	*data = 1;
1637	return 1;
1638	}
1639	/* restore previous status */
1640	ixgbe_write_reg(hw: &adapter->hw, IXGBE_STATUS, value: before);
1641
1642	/*
1643	* Perform the remainder of the register test, looping through
1644	* the test table until we either fail or reach the null entry.
1645	*/
1646	while (test->reg) {
1647	for (i = 0; i < test->array_len; i++) {
1648	bool b = false;
1649
1650	switch (test->test_type) {
1651	case PATTERN_TEST:
1652	b = reg_pattern_test(adapter, data,
1653	reg: test->reg + (i * 0x40),
1654	mask: test->mask,
1655	write: test->write);
1656	break;
1657	case SET_READ_TEST:
1658	b = reg_set_and_check(adapter, data,
1659	reg: test->reg + (i * 0x40),
1660	mask: test->mask,
1661	write: test->write);
1662	break;
1663	case WRITE_NO_TEST:
1664	ixgbe_write_reg(hw: &adapter->hw,
1665	reg: test->reg + (i * 0x40),
1666	value: test->write);
1667	break;
1668	case TABLE32_TEST:
1669	b = reg_pattern_test(adapter, data,
1670	reg: test->reg + (i * 4),
1671	mask: test->mask,
1672	write: test->write);
1673	break;
1674	case TABLE64_TEST_LO:
1675	b = reg_pattern_test(adapter, data,
1676	reg: test->reg + (i * 8),
1677	mask: test->mask,
1678	write: test->write);
1679	break;
1680	case TABLE64_TEST_HI:
1681	b = reg_pattern_test(adapter, data,
1682	reg: (test->reg + 4) + (i * 8),
1683	mask: test->mask,
1684	write: test->write);
1685	break;
1686	}
1687	if (b)
1688	return 1;
1689	}
1690	test++;
1691	}
1692
1693	*data = 0;
1694	return 0;
1695	}
1696
1697	static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1698	{
1699	struct ixgbe_hw *hw = &adapter->hw;
1700	if (hw->eeprom.ops.validate_checksum(hw, NULL))
1701	*data = 1;
1702	else
1703	*data = 0;
1704	return *data;
1705	}
1706
1707	static irqreturn_t ixgbe_test_intr(int irq, void *data)
1708	{
1709	struct net_device *netdev = (struct net_device *) data;
1710	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
1711
1712	adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1713
1714	return IRQ_HANDLED;
1715	}
1716
1717	static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1718	{
1719	struct net_device *netdev = adapter->netdev;
1720	u32 mask, i = 0, shared_int = true;
1721	u32 irq = adapter->pdev->irq;
1722
1723	*data = 0;
1724
1725	/* Hook up test interrupt handler just for this test */
1726	if (adapter->msix_entries) {
1727	/* NOTE: we don't test MSI-X interrupts here, yet */
1728	return 0;
1729	} else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1730	shared_int = false;
1731	if (request_irq(irq, handler: ixgbe_test_intr, flags: 0, name: netdev->name,
1732	dev: netdev)) {
1733	*data = 1;
1734	return -1;
1735	}
1736	} else if (!request_irq(irq, handler: ixgbe_test_intr, IRQF_PROBE_SHARED,
1737	name: netdev->name, dev: netdev)) {
1738	shared_int = false;
1739	} else if (request_irq(irq, handler: ixgbe_test_intr, IRQF_SHARED,
1740	name: netdev->name, dev: netdev)) {
1741	*data = 1;
1742	return -1;
1743	}
1744	e_info(hw, "testing %s interrupt\n", shared_int ?
1745	"shared" : "unshared");
1746
1747	/* Disable all the interrupts */
1748	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1749	IXGBE_WRITE_FLUSH(&adapter->hw);
1750	usleep_range(min: 10000, max: 20000);
1751
1752	/* Test each interrupt */
1753	for (; i < 10; i++) {
1754	/* Interrupt to test */
1755	mask = BIT(i);
1756
1757	if (!shared_int) {
1758	/*
1759	* Disable the interrupts to be reported in
1760	* the cause register and then force the same
1761	* interrupt and see if one gets posted. If
1762	* an interrupt was posted to the bus, the
1763	* test failed.
1764	*/
1765	adapter->test_icr = 0;
1766	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1767	~mask & 0x00007FFF);
1768	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1769	~mask & 0x00007FFF);
1770	IXGBE_WRITE_FLUSH(&adapter->hw);
1771	usleep_range(min: 10000, max: 20000);
1772
1773	if (adapter->test_icr & mask) {
1774	*data = 3;
1775	break;
1776	}
1777	}
1778
1779	/*
1780	* Enable the interrupt to be reported in the cause
1781	* register and then force the same interrupt and see
1782	* if one gets posted. If an interrupt was not posted
1783	* to the bus, the test failed.
1784	*/
1785	adapter->test_icr = 0;
1786	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1787	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1788	IXGBE_WRITE_FLUSH(&adapter->hw);
1789	usleep_range(min: 10000, max: 20000);
1790
1791	if (!(adapter->test_icr & mask)) {
1792	*data = 4;
1793	break;
1794	}
1795
1796	if (!shared_int) {
1797	/*
1798	* Disable the other interrupts to be reported in
1799	* the cause register and then force the other
1800	* interrupts and see if any get posted. If
1801	* an interrupt was posted to the bus, the
1802	* test failed.
1803	*/
1804	adapter->test_icr = 0;
1805	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1806	~mask & 0x00007FFF);
1807	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1808	~mask & 0x00007FFF);
1809	IXGBE_WRITE_FLUSH(&adapter->hw);
1810	usleep_range(min: 10000, max: 20000);
1811
1812	if (adapter->test_icr) {
1813	*data = 5;
1814	break;
1815	}
1816	}
1817	}
1818
1819	/* Disable all the interrupts */
1820	IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1821	IXGBE_WRITE_FLUSH(&adapter->hw);
1822	usleep_range(min: 10000, max: 20000);
1823
1824	/* Unhook test interrupt handler */
1825	free_irq(irq, netdev);
1826
1827	return *data;
1828	}
1829
1830	static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1831	{
1832	/* Shut down the DMA engines now so they can be reinitialized later,
1833	* since the test rings and normally used rings should overlap on
1834	* queue 0 we can just use the standard disable Rx/Tx calls and they
1835	* will take care of disabling the test rings for us.
1836	*/
1837
1838	/* first Rx */
1839	ixgbe_disable_rx(adapter);
1840
1841	/* now Tx */
1842	ixgbe_disable_tx(adapter);
1843
1844	ixgbe_reset(adapter);
1845
1846	ixgbe_free_tx_resources(&adapter->test_tx_ring);
1847	ixgbe_free_rx_resources(&adapter->test_rx_ring);
1848	}
1849
1850	static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1851	{
1852	struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1853	struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1854	struct ixgbe_hw *hw = &adapter->hw;
1855	u32 rctl, reg_data;
1856	int ret_val;
1857	int err;
1858
1859	/* Setup Tx descriptor ring and Tx buffers */
1860	tx_ring->count = IXGBE_DEFAULT_TXD;
1861	tx_ring->queue_index = 0;
1862	tx_ring->dev = &adapter->pdev->dev;
1863	tx_ring->netdev = adapter->netdev;
1864	tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1865
1866	err = ixgbe_setup_tx_resources(tx_ring);
1867	if (err)
1868	return 1;
1869
1870	switch (adapter->hw.mac.type) {
1871	case ixgbe_mac_82599EB:
1872	case ixgbe_mac_X540:
1873	case ixgbe_mac_X550:
1874	case ixgbe_mac_X550EM_x:
1875	case ixgbe_mac_x550em_a:
1876	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1877	reg_data |= IXGBE_DMATXCTL_TE;
1878	IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1879	break;
1880	default:
1881	break;
1882	}
1883
1884	ixgbe_configure_tx_ring(adapter, tx_ring);
1885
1886	/* Setup Rx Descriptor ring and Rx buffers */
1887	rx_ring->count = IXGBE_DEFAULT_RXD;
1888	rx_ring->queue_index = 0;
1889	rx_ring->dev = &adapter->pdev->dev;
1890	rx_ring->netdev = adapter->netdev;
1891	rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1892
1893	err = ixgbe_setup_rx_resources(adapter, rx_ring);
1894	if (err) {
1895	ret_val = 4;
1896	goto err_nomem;
1897	}
1898
1899	hw->mac.ops.disable_rx(hw);
1900
1901	ixgbe_configure_rx_ring(adapter, rx_ring);
1902
1903	rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1904	rctl |= IXGBE_RXCTRL_DMBYPS;
1905	IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1906
1907	hw->mac.ops.enable_rx(hw);
1908
1909	return 0;
1910
1911	err_nomem:
1912	ixgbe_free_desc_rings(adapter);
1913	return ret_val;
1914	}
1915
1916	static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1917	{
1918	struct ixgbe_hw *hw = &adapter->hw;
1919	u32 reg_data;
1920
1921
1922	/* Setup MAC loopback */
1923	reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1924	reg_data |= IXGBE_HLREG0_LPBK;
1925	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1926
1927	reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1928	reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1929	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1930
1931	/* X540 and X550 needs to set the MACC.FLU bit to force link up */
1932	switch (adapter->hw.mac.type) {
1933	case ixgbe_mac_X540:
1934	case ixgbe_mac_X550:
1935	case ixgbe_mac_X550EM_x:
1936	case ixgbe_mac_x550em_a:
1937	reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1938	reg_data |= IXGBE_MACC_FLU;
1939	IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1940	break;
1941	default:
1942	if (hw->mac.orig_autoc) {
1943	reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1944	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1945	} else {
1946	return 10;
1947	}
1948	}
1949	IXGBE_WRITE_FLUSH(hw);
1950	usleep_range(min: 10000, max: 20000);
1951
1952	/* Disable Atlas Tx lanes; re-enabled in reset path */
1953	if (hw->mac.type == ixgbe_mac_82598EB) {
1954	u8 atlas;
1955
1956	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1957	atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1958	hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1959
1960	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1961	atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1962	hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1963
1964	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1965	atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1966	hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1967
1968	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1969	atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1970	hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1971	}
1972
1973	return 0;
1974	}
1975
1976	static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1977	{
1978	u32 reg_data;
1979
1980	reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1981	reg_data &= ~IXGBE_HLREG0_LPBK;
1982	IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1983	}
1984
1985	static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1986	unsigned int frame_size)
1987	{
1988	memset(skb->data, 0xFF, frame_size);
1989	frame_size >>= 1;
1990	memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1991	skb->data[frame_size + 10] = 0xBE;
1992	skb->data[frame_size + 12] = 0xAF;
1993	}
1994
1995	static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1996	unsigned int frame_size)
1997	{
1998	unsigned char *data;
1999
2000	frame_size >>= 1;
2001
2002	data = page_address(rx_buffer->page) + rx_buffer->page_offset;
2003
2004	return data[3] == 0xFF && data[frame_size + 10] == 0xBE &&
2005	data[frame_size + 12] == 0xAF;
2006	}
2007
2008	static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
2009	struct ixgbe_ring *tx_ring,
2010	unsigned int size)
2011	{
2012	union ixgbe_adv_rx_desc *rx_desc;
2013	u16 rx_ntc, tx_ntc, count = 0;
2014
2015	/* initialize next to clean and descriptor values */
2016	rx_ntc = rx_ring->next_to_clean;
2017	tx_ntc = tx_ring->next_to_clean;
2018	rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2019
2020	while (tx_ntc != tx_ring->next_to_use) {
2021	union ixgbe_adv_tx_desc *tx_desc;
2022	struct ixgbe_tx_buffer *tx_buffer;
2023
2024	tx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);
2025
2026	/* if DD is not set transmit has not completed */
2027	if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
2028	return count;
2029
2030	/* unmap buffer on Tx side */
2031	tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
2032
2033	/* Free all the Tx ring sk_buffs */
2034	dev_kfree_skb_any(skb: tx_buffer->skb);
2035
2036	/* unmap skb header data */
2037	dma_unmap_single(tx_ring->dev,
2038	dma_unmap_addr(tx_buffer, dma),
2039	dma_unmap_len(tx_buffer, len),
2040	DMA_TO_DEVICE);
2041	dma_unmap_len_set(tx_buffer, len, 0);
2042
2043	/* increment Tx next to clean counter */
2044	tx_ntc++;
2045	if (tx_ntc == tx_ring->count)
2046	tx_ntc = 0;
2047	}
2048
2049	while (rx_desc->wb.upper.length) {
2050	struct ixgbe_rx_buffer *rx_buffer;
2051
2052	/* check Rx buffer */
2053	rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
2054
2055	/* sync Rx buffer for CPU read */
2056	dma_sync_single_for_cpu(dev: rx_ring->dev,
2057	addr: rx_buffer->dma,
2058	size: ixgbe_rx_bufsz(ring: rx_ring),
2059	dir: DMA_FROM_DEVICE);
2060
2061	/* verify contents of skb */
2062	if (ixgbe_check_lbtest_frame(rx_buffer, frame_size: size))
2063	count++;
2064	else
2065	break;
2066
2067	/* sync Rx buffer for device write */
2068	dma_sync_single_for_device(dev: rx_ring->dev,
2069	addr: rx_buffer->dma,
2070	size: ixgbe_rx_bufsz(ring: rx_ring),
2071	dir: DMA_FROM_DEVICE);
2072
2073	/* increment Rx next to clean counter */
2074	rx_ntc++;
2075	if (rx_ntc == rx_ring->count)
2076	rx_ntc = 0;
2077
2078	/* fetch next descriptor */
2079	rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
2080	}
2081
2082	netdev_tx_reset_queue(q: txring_txq(ring: tx_ring));
2083
2084	/* re-map buffers to ring, store next to clean values */
2085	ixgbe_alloc_rx_buffers(rx_ring, count);
2086	rx_ring->next_to_clean = rx_ntc;
2087	tx_ring->next_to_clean = tx_ntc;
2088
2089	return count;
2090	}
2091
2092	static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
2093	{
2094	struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
2095	struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
2096	int i, j, lc, good_cnt, ret_val = 0;
2097	unsigned int size = 1024;
2098	netdev_tx_t tx_ret_val;
2099	struct sk_buff *skb;
2100	u32 flags_orig = adapter->flags;
2101
2102	/* DCB can modify the frames on Tx */
2103	adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2104
2105	/* allocate test skb */
2106	skb = alloc_skb(size, GFP_KERNEL);
2107	if (!skb)
2108	return 11;
2109
2110	/* place data into test skb */
2111	ixgbe_create_lbtest_frame(skb, frame_size: size);
2112	skb_put(skb, len: size);
2113
2114	/*
2115	* Calculate the loop count based on the largest descriptor ring
2116	* The idea is to wrap the largest ring a number of times using 64
2117	* send/receive pairs during each loop
2118	*/
2119
2120	if (rx_ring->count <= tx_ring->count)
2121	lc = ((tx_ring->count / 64) * 2) + 1;
2122	else
2123	lc = ((rx_ring->count / 64) * 2) + 1;
2124
2125	for (j = 0; j <= lc; j++) {
2126	/* reset count of good packets */
2127	good_cnt = 0;
2128
2129	/* place 64 packets on the transmit queue*/
2130	for (i = 0; i < 64; i++) {
2131	skb_get(skb);
2132	tx_ret_val = ixgbe_xmit_frame_ring(skb,
2133	adapter,
2134	tx_ring);
2135	if (tx_ret_val == NETDEV_TX_OK)
2136	good_cnt++;
2137	}
2138
2139	if (good_cnt != 64) {
2140	ret_val = 12;
2141	break;
2142	}
2143
2144	/* allow 200 milliseconds for packets to go from Tx to Rx */
2145	msleep(msecs: 200);
2146
2147	good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
2148	if (good_cnt != 64) {
2149	ret_val = 13;
2150	break;
2151	}
2152	}
2153
2154	/* free the original skb */
2155	kfree_skb(skb);
2156	adapter->flags = flags_orig;
2157
2158	return ret_val;
2159	}
2160
2161	static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
2162	{
2163	*data = ixgbe_setup_desc_rings(adapter);
2164	if (*data)
2165	goto out;
2166	*data = ixgbe_setup_loopback_test(adapter);
2167	if (*data)
2168	goto err_loopback;
2169	*data = ixgbe_run_loopback_test(adapter);
2170	ixgbe_loopback_cleanup(adapter);
2171
2172	err_loopback:
2173	ixgbe_free_desc_rings(adapter);
2174	out:
2175	return *data;
2176	}
2177
2178	static void ixgbe_diag_test(struct net_device *netdev,
2179	struct ethtool_test *eth_test, u64 *data)
2180	{
2181	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2182	bool if_running = netif_running(dev: netdev);
2183
2184	if (ixgbe_removed(addr: adapter->hw.hw_addr)) {
2185	e_err(hw, "Adapter removed - test blocked\n");
2186	data[0] = 1;
2187	data[1] = 1;
2188	data[2] = 1;
2189	data[3] = 1;
2190	data[4] = 1;
2191	eth_test->flags |= ETH_TEST_FL_FAILED;
2192	return;
2193	}
2194	set_bit(nr: __IXGBE_TESTING, addr: &adapter->state);
2195	if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2196	struct ixgbe_hw *hw = &adapter->hw;
2197
2198	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2199	int i;
2200	for (i = 0; i < adapter->num_vfs; i++) {
2201	if (adapter->vfinfo[i].clear_to_send) {
2202	netdev_warn(dev: netdev, format: "offline diagnostic is not supported when VFs are present\n");
2203	data[0] = 1;
2204	data[1] = 1;
2205	data[2] = 1;
2206	data[3] = 1;
2207	data[4] = 1;
2208	eth_test->flags |= ETH_TEST_FL_FAILED;
2209	clear_bit(nr: __IXGBE_TESTING,
2210	addr: &adapter->state);
2211	return;
2212	}
2213	}
2214	}
2215
2216	/* Offline tests */
2217	e_info(hw, "offline testing starting\n");
2218
2219	/* Link test performed before hardware reset so autoneg doesn't
2220	* interfere with test result
2221	*/
2222	if (ixgbe_link_test(adapter, data: &data[4]))
2223	eth_test->flags |= ETH_TEST_FL_FAILED;
2224
2225	if (if_running)
2226	/* indicate we're in test mode */
2227	ixgbe_close(netdev);
2228	else
2229	ixgbe_reset(adapter);
2230
2231	e_info(hw, "register testing starting\n");
2232	if (ixgbe_reg_test(adapter, data: &data[0]))
2233	eth_test->flags |= ETH_TEST_FL_FAILED;
2234
2235	ixgbe_reset(adapter);
2236	e_info(hw, "eeprom testing starting\n");
2237	if (ixgbe_eeprom_test(adapter, data: &data[1]))
2238	eth_test->flags |= ETH_TEST_FL_FAILED;
2239
2240	ixgbe_reset(adapter);
2241	e_info(hw, "interrupt testing starting\n");
2242	if (ixgbe_intr_test(adapter, data: &data[2]))
2243	eth_test->flags |= ETH_TEST_FL_FAILED;
2244
2245	/* If SRIOV or VMDq is enabled then skip MAC
2246	* loopback diagnostic. */
2247	if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2248	IXGBE_FLAG_VMDQ_ENABLED)) {
2249	e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2250	data[3] = 0;
2251	goto skip_loopback;
2252	}
2253
2254	ixgbe_reset(adapter);
2255	e_info(hw, "loopback testing starting\n");
2256	if (ixgbe_loopback_test(adapter, data: &data[3]))
2257	eth_test->flags |= ETH_TEST_FL_FAILED;
2258
2259	skip_loopback:
2260	ixgbe_reset(adapter);
2261
2262	/* clear testing bit and return adapter to previous state */
2263	clear_bit(nr: __IXGBE_TESTING, addr: &adapter->state);
2264	if (if_running)
2265	ixgbe_open(netdev);
2266	else if (hw->mac.ops.disable_tx_laser)
2267	hw->mac.ops.disable_tx_laser(hw);
2268	} else {
2269	e_info(hw, "online testing starting\n");
2270
2271	/* Online tests */
2272	if (ixgbe_link_test(adapter, data: &data[4]))
2273	eth_test->flags |= ETH_TEST_FL_FAILED;
2274
2275	/* Offline tests aren't run; pass by default */
2276	data[0] = 0;
2277	data[1] = 0;
2278	data[2] = 0;
2279	data[3] = 0;
2280
2281	clear_bit(nr: __IXGBE_TESTING, addr: &adapter->state);
2282	}
2283	}
2284
2285	static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2286	struct ethtool_wolinfo *wol)
2287	{
2288	struct ixgbe_hw *hw = &adapter->hw;
2289	int retval = 0;
2290
2291	/* WOL not supported for all devices */
2292	if (!ixgbe_wol_supported(adapter, device_id: hw->device_id,
2293	subdevice_id: hw->subsystem_device_id)) {
2294	retval = 1;
2295	wol->supported = 0;
2296	}
2297
2298	return retval;
2299	}
2300
2301	static void ixgbe_get_wol(struct net_device *netdev,
2302	struct ethtool_wolinfo *wol)
2303	{
2304	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2305
2306	wol->supported = WAKE_UCAST | WAKE_MCAST |
2307	WAKE_BCAST | WAKE_MAGIC;
2308	wol->wolopts = 0;
2309
2310	if (ixgbe_wol_exclusion(adapter, wol) ||
2311	!device_can_wakeup(dev: &adapter->pdev->dev))
2312	return;
2313
2314	if (adapter->wol & IXGBE_WUFC_EX)
2315	wol->wolopts |= WAKE_UCAST;
2316	if (adapter->wol & IXGBE_WUFC_MC)
2317	wol->wolopts |= WAKE_MCAST;
2318	if (adapter->wol & IXGBE_WUFC_BC)
2319	wol->wolopts |= WAKE_BCAST;
2320	if (adapter->wol & IXGBE_WUFC_MAG)
2321	wol->wolopts |= WAKE_MAGIC;
2322	}
2323
2324	static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2325	{
2326	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2327
2328	if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE |
2329	WAKE_FILTER))
2330	return -EOPNOTSUPP;
2331
2332	if (ixgbe_wol_exclusion(adapter, wol))
2333	return wol->wolopts ? -EOPNOTSUPP : 0;
2334
2335	adapter->wol = 0;
2336
2337	if (wol->wolopts & WAKE_UCAST)
2338	adapter->wol |= IXGBE_WUFC_EX;
2339	if (wol->wolopts & WAKE_MCAST)
2340	adapter->wol |= IXGBE_WUFC_MC;
2341	if (wol->wolopts & WAKE_BCAST)
2342	adapter->wol |= IXGBE_WUFC_BC;
2343	if (wol->wolopts & WAKE_MAGIC)
2344	adapter->wol |= IXGBE_WUFC_MAG;
2345
2346	device_set_wakeup_enable(dev: &adapter->pdev->dev, enable: adapter->wol);
2347
2348	return 0;
2349	}
2350
2351	static int ixgbe_nway_reset(struct net_device *netdev)
2352	{
2353	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2354
2355	if (netif_running(dev: netdev))
2356	ixgbe_reinit_locked(adapter);
2357
2358	return 0;
2359	}
2360
2361	static int ixgbe_set_phys_id(struct net_device *netdev,
2362	enum ethtool_phys_id_state state)
2363	{
2364	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2365	struct ixgbe_hw *hw = &adapter->hw;
2366
2367	if (!hw->mac.ops.led_on || !hw->mac.ops.led_off)
2368	return -EOPNOTSUPP;
2369
2370	switch (state) {
2371	case ETHTOOL_ID_ACTIVE:
2372	adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2373	return 2;
2374
2375	case ETHTOOL_ID_ON:
2376	hw->mac.ops.led_on(hw, hw->mac.led_link_act);
2377	break;
2378
2379	case ETHTOOL_ID_OFF:
2380	hw->mac.ops.led_off(hw, hw->mac.led_link_act);
2381	break;
2382
2383	case ETHTOOL_ID_INACTIVE:
2384	/* Restore LED settings */
2385	IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2386	break;
2387	}
2388
2389	return 0;
2390	}
2391
2392	static int ixgbe_get_coalesce(struct net_device *netdev,
2393	struct ethtool_coalesce *ec,
2394	struct kernel_ethtool_coalesce *kernel_coal,
2395	struct netlink_ext_ack *extack)
2396	{
2397	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2398
2399	/* only valid if in constant ITR mode */
2400	if (adapter->rx_itr_setting <= 1)
2401	ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2402	else
2403	ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2404
2405	/* if in mixed tx/rx queues per vector mode, report only rx settings */
2406	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2407	return 0;
2408
2409	/* only valid if in constant ITR mode */
2410	if (adapter->tx_itr_setting <= 1)
2411	ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2412	else
2413	ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2414
2415	return 0;
2416	}
2417
2418	/*
2419	* this function must be called before setting the new value of
2420	* rx_itr_setting
2421	*/
2422	static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2423	{
2424	struct net_device *netdev = adapter->netdev;
2425
2426	/* nothing to do if LRO or RSC are not enabled */
2427	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2428	!(netdev->features & NETIF_F_LRO))
2429	return false;
2430
2431	/* check the feature flag value and enable RSC if necessary */
2432	if (adapter->rx_itr_setting == 1 ||
2433	adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2434	if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2435	adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2436	e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2437	return true;
2438	}
2439	/* if interrupt rate is too high then disable RSC */
2440	} else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2441	adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2442	e_info(probe, "rx-usecs set too low, disabling RSC\n");
2443	return true;
2444	}
2445	return false;
2446	}
2447
2448	static int ixgbe_set_coalesce(struct net_device *netdev,
2449	struct ethtool_coalesce *ec,
2450	struct kernel_ethtool_coalesce *kernel_coal,
2451	struct netlink_ext_ack *extack)
2452	{
2453	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
2454	struct ixgbe_q_vector *q_vector;
2455	int i;
2456	u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2457	bool need_reset = false;
2458
2459	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2460	/* reject Tx specific changes in case of mixed RxTx vectors */
2461	if (ec->tx_coalesce_usecs)
2462	return -EINVAL;
2463	tx_itr_prev = adapter->rx_itr_setting;
2464	} else {
2465	tx_itr_prev = adapter->tx_itr_setting;
2466	}
2467
2468	if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2469	(ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2470	return -EINVAL;
2471
2472	if (ec->rx_coalesce_usecs > 1)
2473	adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2474	else
2475	adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2476
2477	if (adapter->rx_itr_setting == 1)
2478	rx_itr_param = IXGBE_20K_ITR;
2479	else
2480	rx_itr_param = adapter->rx_itr_setting;
2481
2482	if (ec->tx_coalesce_usecs > 1)
2483	adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2484	else
2485	adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2486
2487	if (adapter->tx_itr_setting == 1)
2488	tx_itr_param = IXGBE_12K_ITR;
2489	else
2490	tx_itr_param = adapter->tx_itr_setting;
2491
2492	/* mixed Rx/Tx */
2493	if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2494	adapter->tx_itr_setting = adapter->rx_itr_setting;
2495
2496	/* detect ITR changes that require update of TXDCTL.WTHRESH */
2497	if ((adapter->tx_itr_setting != 1) &&
2498	(adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2499	if ((tx_itr_prev == 1) ||
2500	(tx_itr_prev >= IXGBE_100K_ITR))
2501	need_reset = true;
2502	} else {
2503	if ((tx_itr_prev != 1) &&
2504	(tx_itr_prev < IXGBE_100K_ITR))
2505	need_reset = true;
2506	}
2507
2508	/* check the old value and enable RSC if necessary */
2509	need_reset |= ixgbe_update_rsc(adapter);
2510
2511	for (i = 0; i < adapter->num_q_vectors; i++) {
2512	q_vector = adapter->q_vector[i];
2513	if (q_vector->tx.count && !q_vector->rx.count)
2514	/* tx only */
2515	q_vector->itr = tx_itr_param;
2516	else
2517	/* rx only or mixed */
2518	q_vector->itr = rx_itr_param;
2519	ixgbe_write_eitr(q_vector);
2520	}
2521
2522	/*
2523	* do reset here at the end to make sure EITR==0 case is handled
2524	* correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2525	* also locks in RSC enable/disable which requires reset
2526	*/
2527	if (need_reset)
2528	ixgbe_do_reset(netdev);
2529
2530	return 0;
2531	}
2532
2533	static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2534	struct ethtool_rxnfc *cmd)
2535	{
2536	union ixgbe_atr_input *mask = &adapter->fdir_mask;
2537	struct ethtool_rx_flow_spec *fsp =
2538	(struct ethtool_rx_flow_spec *)&cmd->fs;
2539	struct hlist_node *node2;
2540	struct ixgbe_fdir_filter *rule = NULL;
2541
2542	/* report total rule count */
2543	cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2544
2545	hlist_for_each_entry_safe(rule, node2,
2546	&adapter->fdir_filter_list, fdir_node) {
2547	if (fsp->location <= rule->sw_idx)
2548	break;
2549	}
2550
2551	if (!rule || fsp->location != rule->sw_idx)
2552	return -EINVAL;
2553
2554	/* fill out the flow spec entry */
2555
2556	/* set flow type field */
2557	switch (rule->filter.formatted.flow_type) {
2558	case IXGBE_ATR_FLOW_TYPE_TCPV4:
2559	fsp->flow_type = TCP_V4_FLOW;
2560	break;
2561	case IXGBE_ATR_FLOW_TYPE_UDPV4:
2562	fsp->flow_type = UDP_V4_FLOW;
2563	break;
2564	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2565	fsp->flow_type = SCTP_V4_FLOW;
2566	break;
2567	case IXGBE_ATR_FLOW_TYPE_IPV4:
2568	fsp->flow_type = IP_USER_FLOW;
2569	fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2570	fsp->h_u.usr_ip4_spec.proto = 0;
2571	fsp->m_u.usr_ip4_spec.proto = 0;
2572	break;
2573	default:
2574	return -EINVAL;
2575	}
2576
2577	fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2578	fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2579	fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2580	fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2581	fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2582	fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2583	fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2584	fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2585	fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2586	fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2587	fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2588	fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2589	fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2590	fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2591	fsp->flow_type |= FLOW_EXT;
2592
2593	/* record action */
2594	if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2595	fsp->ring_cookie = RX_CLS_FLOW_DISC;
2596	else
2597	fsp->ring_cookie = rule->action;
2598
2599	return 0;
2600	}
2601
2602	static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2603	struct ethtool_rxnfc *cmd,
2604	u32 *rule_locs)
2605	{
2606	struct hlist_node *node2;
2607	struct ixgbe_fdir_filter *rule;
2608	int cnt = 0;
2609
2610	/* report total rule count */
2611	cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2612
2613	hlist_for_each_entry_safe(rule, node2,
2614	&adapter->fdir_filter_list, fdir_node) {
2615	if (cnt == cmd->rule_cnt)
2616	return -EMSGSIZE;
2617	rule_locs[cnt] = rule->sw_idx;
2618	cnt++;
2619	}
2620
2621	cmd->rule_cnt = cnt;
2622
2623	return 0;
2624	}
2625
2626	static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2627	struct ethtool_rxnfc *cmd)
2628	{
2629	cmd->data = 0;
2630
2631	/* Report default options for RSS on ixgbe */
2632	switch (cmd->flow_type) {
2633	case TCP_V4_FLOW:
2634	cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2635	fallthrough;
2636	case UDP_V4_FLOW:
2637	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2638	cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2639	fallthrough;
2640	case SCTP_V4_FLOW:
2641	case AH_ESP_V4_FLOW:
2642	case AH_V4_FLOW:
2643	case ESP_V4_FLOW:
2644	case IPV4_FLOW:
2645	cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2646	break;
2647	case TCP_V6_FLOW:
2648	cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2649	fallthrough;
2650	case UDP_V6_FLOW:
2651	if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2652	cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2653	fallthrough;
2654	case SCTP_V6_FLOW:
2655	case AH_ESP_V6_FLOW:
2656	case AH_V6_FLOW:
2657	case ESP_V6_FLOW:
2658	case IPV6_FLOW:
2659	cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2660	break;
2661	default:
2662	return -EINVAL;
2663	}
2664
2665	return 0;
2666	}
2667
2668	static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2669	{
2670	if (adapter->hw.mac.type < ixgbe_mac_X550)
2671	return 16;
2672	else
2673	return 64;
2674	}
2675
2676	static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2677	u32 *rule_locs)
2678	{
2679	struct ixgbe_adapter *adapter = netdev_priv(dev);
2680	int ret = -EOPNOTSUPP;
2681
2682	switch (cmd->cmd) {
2683	case ETHTOOL_GRXRINGS:
2684	cmd->data = min_t(int, adapter->num_rx_queues,
2685	ixgbe_rss_indir_tbl_max(adapter));
2686	ret = 0;
2687	break;
2688	case ETHTOOL_GRXCLSRLCNT:
2689	cmd->rule_cnt = adapter->fdir_filter_count;
2690	ret = 0;
2691	break;
2692	case ETHTOOL_GRXCLSRULE:
2693	ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2694	break;
2695	case ETHTOOL_GRXCLSRLALL:
2696	ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2697	break;
2698	case ETHTOOL_GRXFH:
2699	ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2700	break;
2701	default:
2702	break;
2703	}
2704
2705	return ret;
2706	}
2707
2708	int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2709	struct ixgbe_fdir_filter *input,
2710	u16 sw_idx)
2711	{
2712	struct ixgbe_hw *hw = &adapter->hw;
2713	struct hlist_node *node2;
2714	struct ixgbe_fdir_filter *rule, *parent;
2715	int err = -EINVAL;
2716
2717	parent = NULL;
2718	rule = NULL;
2719
2720	hlist_for_each_entry_safe(rule, node2,
2721	&adapter->fdir_filter_list, fdir_node) {
2722	/* hash found, or no matching entry */
2723	if (rule->sw_idx >= sw_idx)
2724	break;
2725	parent = rule;
2726	}
2727
2728	/* if there is an old rule occupying our place remove it */
2729	if (rule && (rule->sw_idx == sw_idx)) {
2730	if (!input || (rule->filter.formatted.bkt_hash !=
2731	input->filter.formatted.bkt_hash)) {
2732	err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2733	input: &rule->filter,
2734	soft_id: sw_idx);
2735	}
2736
2737	hlist_del(n: &rule->fdir_node);
2738	kfree(objp: rule);
2739	adapter->fdir_filter_count--;
2740	}
2741
2742	/*
2743	* If no input this was a delete, err should be 0 if a rule was
2744	* successfully found and removed from the list else -EINVAL
2745	*/
2746	if (!input)
2747	return err;
2748
2749	/* initialize node and set software index */
2750	INIT_HLIST_NODE(h: &input->fdir_node);
2751
2752	/* add filter to the list */
2753	if (parent)
2754	hlist_add_behind(n: &input->fdir_node, prev: &parent->fdir_node);
2755	else
2756	hlist_add_head(n: &input->fdir_node,
2757	h: &adapter->fdir_filter_list);
2758
2759	/* update counts */
2760	adapter->fdir_filter_count++;
2761
2762	return 0;
2763	}
2764
2765	static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2766	u8 *flow_type)
2767	{
2768	switch (fsp->flow_type & ~FLOW_EXT) {
2769	case TCP_V4_FLOW:
2770	*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2771	break;
2772	case UDP_V4_FLOW:
2773	*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2774	break;
2775	case SCTP_V4_FLOW:
2776	*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2777	break;
2778	case IP_USER_FLOW:
2779	switch (fsp->h_u.usr_ip4_spec.proto) {
2780	case IPPROTO_TCP:
2781	*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2782	break;
2783	case IPPROTO_UDP:
2784	*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2785	break;
2786	case IPPROTO_SCTP:
2787	*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2788	break;
2789	case 0:
2790	if (!fsp->m_u.usr_ip4_spec.proto) {
2791	*flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2792	break;
2793	}
2794	fallthrough;
2795	default:
2796	return 0;
2797	}
2798	break;
2799	default:
2800	return 0;
2801	}
2802
2803	return 1;
2804	}
2805
2806	static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2807	struct ethtool_rxnfc *cmd)
2808	{
2809	struct ethtool_rx_flow_spec *fsp =
2810	(struct ethtool_rx_flow_spec *)&cmd->fs;
2811	struct ixgbe_hw *hw = &adapter->hw;
2812	struct ixgbe_fdir_filter *input;
2813	union ixgbe_atr_input mask;
2814	u8 queue;
2815	int err;
2816
2817	if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2818	return -EOPNOTSUPP;
2819
2820	/* ring_cookie is a masked into a set of queues and ixgbe pools or
2821	* we use the drop index.
2822	*/
2823	if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2824	queue = IXGBE_FDIR_DROP_QUEUE;
2825	} else {
2826	u32 ring = ethtool_get_flow_spec_ring(ring_cookie: fsp->ring_cookie);
2827	u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie: fsp->ring_cookie);
2828
2829	if (!vf && (ring >= adapter->num_rx_queues))
2830	return -EINVAL;
2831	else if (vf &&
2832	((vf > adapter->num_vfs) ||
2833	ring >= adapter->num_rx_queues_per_pool))
2834	return -EINVAL;
2835
2836	/* Map the ring onto the absolute queue index */
2837	if (!vf)
2838	queue = adapter->rx_ring[ring]->reg_idx;
2839	else
2840	queue = ((vf - 1) *
2841	adapter->num_rx_queues_per_pool) + ring;
2842	}
2843
2844	/* Don't allow indexes to exist outside of available space */
2845	if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2846	e_err(drv, "Location out of range\n");
2847	return -EINVAL;
2848	}
2849
2850	input = kzalloc(size: sizeof(*input), GFP_ATOMIC);
2851	if (!input)
2852	return -ENOMEM;
2853
2854	memset(&mask, 0, sizeof(union ixgbe_atr_input));
2855
2856	/* set SW index */
2857	input->sw_idx = fsp->location;
2858
2859	/* record flow type */
2860	if (!ixgbe_flowspec_to_flow_type(fsp,
2861	flow_type: &input->filter.formatted.flow_type)) {
2862	e_err(drv, "Unrecognized flow type\n");
2863	goto err_out;
2864	}
2865
2866	mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2867	IXGBE_ATR_L4TYPE_MASK;
2868
2869	if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2870	mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2871
2872	/* Copy input into formatted structures */
2873	input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2874	mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2875	input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2876	mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2877	input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2878	mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2879	input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2880	mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2881
2882	if (fsp->flow_type & FLOW_EXT) {
2883	input->filter.formatted.vm_pool =
2884	(unsigned char)ntohl(fsp->h_ext.data[1]);
2885	mask.formatted.vm_pool =
2886	(unsigned char)ntohl(fsp->m_ext.data[1]);
2887	input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2888	mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2889	input->filter.formatted.flex_bytes =
2890	fsp->h_ext.vlan_etype;
2891	mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2892	}
2893
2894	/* determine if we need to drop or route the packet */
2895	if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2896	input->action = IXGBE_FDIR_DROP_QUEUE;
2897	else
2898	input->action = fsp->ring_cookie;
2899
2900	spin_lock(lock: &adapter->fdir_perfect_lock);
2901
2902	if (hlist_empty(h: &adapter->fdir_filter_list)) {
2903	/* save mask and program input mask into HW */
2904	memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2905	err = ixgbe_fdir_set_input_mask_82599(hw, input_mask: &mask);
2906	if (err) {
2907	e_err(drv, "Error writing mask\n");
2908	goto err_out_w_lock;
2909	}
2910	} else if (memcmp(p: &adapter->fdir_mask, q: &mask, size: sizeof(mask))) {
2911	e_err(drv, "Only one mask supported per port\n");
2912	goto err_out_w_lock;
2913	}
2914
2915	/* apply mask and compute/store hash */
2916	ixgbe_atr_compute_perfect_hash_82599(input: &input->filter, mask: &mask);
2917
2918	/* program filters to filter memory */
2919	err = ixgbe_fdir_write_perfect_filter_82599(hw,
2920	input: &input->filter, soft_id: input->sw_idx, queue);
2921	if (err)
2922	goto err_out_w_lock;
2923
2924	ixgbe_update_ethtool_fdir_entry(adapter, input, sw_idx: input->sw_idx);
2925
2926	spin_unlock(lock: &adapter->fdir_perfect_lock);
2927
2928	return err;
2929	err_out_w_lock:
2930	spin_unlock(lock: &adapter->fdir_perfect_lock);
2931	err_out:
2932	kfree(objp: input);
2933	return -EINVAL;
2934	}
2935
2936	static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2937	struct ethtool_rxnfc *cmd)
2938	{
2939	struct ethtool_rx_flow_spec *fsp =
2940	(struct ethtool_rx_flow_spec *)&cmd->fs;
2941	int err;
2942
2943	spin_lock(lock: &adapter->fdir_perfect_lock);
2944	err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, sw_idx: fsp->location);
2945	spin_unlock(lock: &adapter->fdir_perfect_lock);
2946
2947	return err;
2948	}
2949
2950	#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2951	IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2952	static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2953	struct ethtool_rxnfc *nfc)
2954	{
2955	u32 flags2 = adapter->flags2;
2956
2957	/*
2958	* RSS does not support anything other than hashing
2959	* to queues on src and dst IPs and ports
2960	*/
2961	if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2962	RXH_L4_B_0_1 | RXH_L4_B_2_3))
2963	return -EINVAL;
2964
2965	switch (nfc->flow_type) {
2966	case TCP_V4_FLOW:
2967	case TCP_V6_FLOW:
2968	if (!(nfc->data & RXH_IP_SRC) ||
2969	!(nfc->data & RXH_IP_DST) ||
2970	!(nfc->data & RXH_L4_B_0_1) ||
2971	!(nfc->data & RXH_L4_B_2_3))
2972	return -EINVAL;
2973	break;
2974	case UDP_V4_FLOW:
2975	if (!(nfc->data & RXH_IP_SRC) ||
2976	!(nfc->data & RXH_IP_DST))
2977	return -EINVAL;
2978	switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2979	case 0:
2980	flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2981	break;
2982	case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2983	flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2984	break;
2985	default:
2986	return -EINVAL;
2987	}
2988	break;
2989	case UDP_V6_FLOW:
2990	if (!(nfc->data & RXH_IP_SRC) ||
2991	!(nfc->data & RXH_IP_DST))
2992	return -EINVAL;
2993	switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2994	case 0:
2995	flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2996	break;
2997	case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2998	flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2999	break;
3000	default:
3001	return -EINVAL;
3002	}
3003	break;
3004	case AH_ESP_V4_FLOW:
3005	case AH_V4_FLOW:
3006	case ESP_V4_FLOW:
3007	case SCTP_V4_FLOW:
3008	case AH_ESP_V6_FLOW:
3009	case AH_V6_FLOW:
3010	case ESP_V6_FLOW:
3011	case SCTP_V6_FLOW:
3012	if (!(nfc->data & RXH_IP_SRC) ||
3013	!(nfc->data & RXH_IP_DST) ||
3014	(nfc->data & RXH_L4_B_0_1) ||
3015	(nfc->data & RXH_L4_B_2_3))
3016	return -EINVAL;
3017	break;
3018	default:
3019	return -EINVAL;
3020	}
3021
3022	/* if we changed something we need to update flags */
3023	if (flags2 != adapter->flags2) {
3024	struct ixgbe_hw *hw = &adapter->hw;
3025	u32 mrqc;
3026	unsigned int pf_pool = adapter->num_vfs;
3027
3028	if ((hw->mac.type >= ixgbe_mac_X550) &&
3029	(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3030	mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
3031	else
3032	mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3033
3034	if ((flags2 & UDP_RSS_FLAGS) &&
3035	!(adapter->flags2 & UDP_RSS_FLAGS))
3036	e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
3037
3038	adapter->flags2 = flags2;
3039
3040	/* Perform hash on these packet types */
3041	mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
3042	| IXGBE_MRQC_RSS_FIELD_IPV4_TCP
3043	| IXGBE_MRQC_RSS_FIELD_IPV6
3044	| IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3045
3046	mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
3047	IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
3048
3049	if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3050	mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3051
3052	if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3053	mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3054
3055	if ((hw->mac.type >= ixgbe_mac_X550) &&
3056	(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3057	IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
3058	else
3059	IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3060	}
3061
3062	return 0;
3063	}
3064
3065	static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3066	{
3067	struct ixgbe_adapter *adapter = netdev_priv(dev);
3068	int ret = -EOPNOTSUPP;
3069
3070	switch (cmd->cmd) {
3071	case ETHTOOL_SRXCLSRLINS:
3072	ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
3073	break;
3074	case ETHTOOL_SRXCLSRLDEL:
3075	ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
3076	break;
3077	case ETHTOOL_SRXFH:
3078	ret = ixgbe_set_rss_hash_opt(adapter, nfc: cmd);
3079	break;
3080	default:
3081	break;
3082	}
3083
3084	return ret;
3085	}
3086
3087	static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
3088	{
3089	return IXGBE_RSS_KEY_SIZE;
3090	}
3091
3092	static u32 ixgbe_rss_indir_size(struct net_device *netdev)
3093	{
3094	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3095
3096	return ixgbe_rss_indir_tbl_entries(adapter);
3097	}
3098
3099	static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
3100	{
3101	int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
3102	u16 rss_m = adapter->ring_feature[RING_F_RSS].mask;
3103
3104	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3105	rss_m = adapter->ring_feature[RING_F_RSS].indices - 1;
3106
3107	for (i = 0; i < reta_size; i++)
3108	indir[i] = adapter->rss_indir_tbl[i] & rss_m;
3109	}
3110
3111	static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3112	u8 *hfunc)
3113	{
3114	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3115
3116	if (hfunc)
3117	*hfunc = ETH_RSS_HASH_TOP;
3118
3119	if (indir)
3120	ixgbe_get_reta(adapter, indir);
3121
3122	if (key)
3123	memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
3124
3125	return 0;
3126	}
3127
3128	static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
3129	const u8 *key, const u8 hfunc)
3130	{
3131	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3132	int i;
3133	u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3134
3135	if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
3136	return -EOPNOTSUPP;
3137
3138	/* Fill out the redirection table */
3139	if (indir) {
3140	int max_queues = min_t(int, adapter->num_rx_queues,
3141	ixgbe_rss_indir_tbl_max(adapter));
3142
3143	/*Allow at least 2 queues w/ SR-IOV.*/
3144	if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3145	(max_queues < 2))
3146	max_queues = 2;
3147
3148	/* Verify user input. */
3149	for (i = 0; i < reta_entries; i++)
3150	if (indir[i] >= max_queues)
3151	return -EINVAL;
3152
3153	for (i = 0; i < reta_entries; i++)
3154	adapter->rss_indir_tbl[i] = indir[i];
3155
3156	ixgbe_store_reta(adapter);
3157	}
3158
3159	/* Fill out the rss hash key */
3160	if (key) {
3161	memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
3162	ixgbe_store_key(adapter);
3163	}
3164
3165	return 0;
3166	}
3167
3168	static int ixgbe_get_ts_info(struct net_device *dev,
3169	struct ethtool_ts_info *info)
3170	{
3171	struct ixgbe_adapter *adapter = netdev_priv(dev);
3172
3173	/* we always support timestamping disabled */
3174	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
3175
3176	switch (adapter->hw.mac.type) {
3177	case ixgbe_mac_X550:
3178	case ixgbe_mac_X550EM_x:
3179	case ixgbe_mac_x550em_a:
3180	info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3181	break;
3182	case ixgbe_mac_X540:
3183	case ixgbe_mac_82599EB:
3184	info->rx_filters |=
3185	BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3186	BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3187	BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3188	break;
3189	default:
3190	return ethtool_op_get_ts_info(dev, eti: info);
3191	}
3192
3193	info->so_timestamping =
3194	SOF_TIMESTAMPING_TX_SOFTWARE |
3195	SOF_TIMESTAMPING_RX_SOFTWARE |
3196	SOF_TIMESTAMPING_SOFTWARE |
3197	SOF_TIMESTAMPING_TX_HARDWARE |
3198	SOF_TIMESTAMPING_RX_HARDWARE |
3199	SOF_TIMESTAMPING_RAW_HARDWARE;
3200
3201	if (adapter->ptp_clock)
3202	info->phc_index = ptp_clock_index(ptp: adapter->ptp_clock);
3203	else
3204	info->phc_index = -1;
3205
3206	info->tx_types =
3207	BIT(HWTSTAMP_TX_OFF) |
3208	BIT(HWTSTAMP_TX_ON);
3209
3210	return 0;
3211	}
3212
3213	static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3214	{
3215	unsigned int max_combined;
3216	u8 tcs = adapter->hw_tcs;
3217
3218	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3219	/* We only support one q_vector without MSI-X */
3220	max_combined = 1;
3221	} else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3222	/* Limit value based on the queue mask */
3223	max_combined = adapter->ring_feature[RING_F_RSS].mask + 1;
3224	} else if (tcs > 1) {
3225	/* For DCB report channels per traffic class */
3226	if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3227	/* 8 TC w/ 4 queues per TC */
3228	max_combined = 4;
3229	} else if (tcs > 4) {
3230	/* 8 TC w/ 8 queues per TC */
3231	max_combined = 8;
3232	} else {
3233	/* 4 TC w/ 16 queues per TC */
3234	max_combined = 16;
3235	}
3236	} else if (adapter->atr_sample_rate) {
3237	/* support up to 64 queues with ATR */
3238	max_combined = IXGBE_MAX_FDIR_INDICES;
3239	} else {
3240	/* support up to 16 queues with RSS */
3241	max_combined = ixgbe_max_rss_indices(adapter);
3242	}
3243
3244	return min_t(int, max_combined, num_online_cpus());
3245	}
3246
3247	static void ixgbe_get_channels(struct net_device *dev,
3248	struct ethtool_channels *ch)
3249	{
3250	struct ixgbe_adapter *adapter = netdev_priv(dev);
3251
3252	/* report maximum channels */
3253	ch->max_combined = ixgbe_max_channels(adapter);
3254
3255	/* report info for other vector */
3256	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3257	ch->max_other = NON_Q_VECTORS;
3258	ch->other_count = NON_Q_VECTORS;
3259	}
3260
3261	/* record RSS queues */
3262	ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3263
3264	/* nothing else to report if RSS is disabled */
3265	if (ch->combined_count == 1)
3266	return;
3267
3268	/* we do not support ATR queueing if SR-IOV is enabled */
3269	if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3270	return;
3271
3272	/* same thing goes for being DCB enabled */
3273	if (adapter->hw_tcs > 1)
3274	return;
3275
3276	/* if ATR is disabled we can exit */
3277	if (!adapter->atr_sample_rate)
3278	return;
3279
3280	/* report flow director queues as maximum channels */
3281	ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3282	}
3283
3284	static int ixgbe_set_channels(struct net_device *dev,
3285	struct ethtool_channels *ch)
3286	{
3287	struct ixgbe_adapter *adapter = netdev_priv(dev);
3288	unsigned int count = ch->combined_count;
3289	u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3290
3291	/* verify they are not requesting separate vectors */
3292	if (!count || ch->rx_count || ch->tx_count)
3293	return -EINVAL;
3294
3295	/* verify other_count has not changed */
3296	if (ch->other_count != NON_Q_VECTORS)
3297	return -EINVAL;
3298
3299	/* verify the number of channels does not exceed hardware limits */
3300	if (count > ixgbe_max_channels(adapter))
3301	return -EINVAL;
3302
3303	/* update feature limits from largest to smallest supported values */
3304	adapter->ring_feature[RING_F_FDIR].limit = count;
3305
3306	/* cap RSS limit */
3307	if (count > max_rss_indices)
3308	count = max_rss_indices;
3309	adapter->ring_feature[RING_F_RSS].limit = count;
3310
3311	#ifdef IXGBE_FCOE
3312	/* cap FCoE limit at 8 */
3313	if (count > IXGBE_FCRETA_SIZE)
3314	count = IXGBE_FCRETA_SIZE;
3315	adapter->ring_feature[RING_F_FCOE].limit = count;
3316
3317	#endif
3318	/* use setup TC to update any traffic class queue mapping */
3319	return ixgbe_setup_tc(dev, tc: adapter->hw_tcs);
3320	}
3321
3322	static int ixgbe_get_module_info(struct net_device *dev,
3323	struct ethtool_modinfo *modinfo)
3324	{
3325	struct ixgbe_adapter *adapter = netdev_priv(dev);
3326	struct ixgbe_hw *hw = &adapter->hw;
3327	s32 status;
3328	u8 sff8472_rev, addr_mode;
3329	bool page_swap = false;
3330
3331	if (hw->phy.type == ixgbe_phy_fw)
3332	return -ENXIO;
3333
3334	/* Check whether we support SFF-8472 or not */
3335	status = hw->phy.ops.read_i2c_eeprom(hw,
3336	IXGBE_SFF_SFF_8472_COMP,
3337	&sff8472_rev);
3338	if (status)
3339	return -EIO;
3340
3341	/* addressing mode is not supported */
3342	status = hw->phy.ops.read_i2c_eeprom(hw,
3343	IXGBE_SFF_SFF_8472_SWAP,
3344	&addr_mode);
3345	if (status)
3346	return -EIO;
3347
3348	if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3349	e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3350	page_swap = true;
3351	}
3352
3353	if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap ||
3354	!(addr_mode & IXGBE_SFF_DDM_IMPLEMENTED)) {
3355	/* We have a SFP, but it does not support SFF-8472 */
3356	modinfo->type = ETH_MODULE_SFF_8079;
3357	modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3358	} else {
3359	/* We have a SFP which supports a revision of SFF-8472. */
3360	modinfo->type = ETH_MODULE_SFF_8472;
3361	modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3362	}
3363
3364	return 0;
3365	}
3366
3367	static int ixgbe_get_module_eeprom(struct net_device *dev,
3368	struct ethtool_eeprom *ee,
3369	u8 *data)
3370	{
3371	struct ixgbe_adapter *adapter = netdev_priv(dev);
3372	struct ixgbe_hw *hw = &adapter->hw;
3373	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3374	u8 databyte = 0xFF;
3375	int i = 0;
3376
3377	if (ee->len == 0)
3378	return -EINVAL;
3379
3380	if (hw->phy.type == ixgbe_phy_fw)
3381	return -ENXIO;
3382
3383	for (i = ee->offset; i < ee->offset + ee->len; i++) {
3384	/* I2C reads can take long time */
3385	if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3386	return -EBUSY;
3387
3388	if (i < ETH_MODULE_SFF_8079_LEN)
3389	status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3390	else
3391	status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3392
3393	if (status)
3394	return -EIO;
3395
3396	data[i - ee->offset] = databyte;
3397	}
3398
3399	return 0;
3400	}
3401
3402	static const struct {
3403	ixgbe_link_speed mac_speed;
3404	u32 supported;
3405	} ixgbe_ls_map[] = {
3406	{ IXGBE_LINK_SPEED_10_FULL, SUPPORTED_10baseT_Full },
3407	{ IXGBE_LINK_SPEED_100_FULL, SUPPORTED_100baseT_Full },
3408	{ IXGBE_LINK_SPEED_1GB_FULL, SUPPORTED_1000baseT_Full },
3409	{ IXGBE_LINK_SPEED_2_5GB_FULL, SUPPORTED_2500baseX_Full },
3410	{ IXGBE_LINK_SPEED_10GB_FULL, SUPPORTED_10000baseT_Full },
3411	};
3412
3413	static const struct {
3414	u32 lp_advertised;
3415	u32 mac_speed;
3416	} ixgbe_lp_map[] = {
3417	{ FW_PHY_ACT_UD_2_100M_TX_EEE, SUPPORTED_100baseT_Full },
3418	{ FW_PHY_ACT_UD_2_1G_T_EEE, SUPPORTED_1000baseT_Full },
3419	{ FW_PHY_ACT_UD_2_10G_T_EEE, SUPPORTED_10000baseT_Full },
3420	{ FW_PHY_ACT_UD_2_1G_KX_EEE, SUPPORTED_1000baseKX_Full },
3421	{ FW_PHY_ACT_UD_2_10G_KX4_EEE, SUPPORTED_10000baseKX4_Full },
3422	{ FW_PHY_ACT_UD_2_10G_KR_EEE, SUPPORTED_10000baseKR_Full},
3423	};
3424
3425	static int
3426	ixgbe_get_eee_fw(struct ixgbe_adapter *adapter, struct ethtool_eee *edata)
3427	{
3428	u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
3429	struct ixgbe_hw *hw = &adapter->hw;
3430	s32 rc;
3431	u16 i;
3432
3433	rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_UD_2, data: &info);
3434	if (rc)
3435	return rc;
3436
3437	edata->lp_advertised = 0;
3438	for (i = 0; i < ARRAY_SIZE(ixgbe_lp_map); ++i) {
3439	if (info[0] & ixgbe_lp_map[i].lp_advertised)
3440	edata->lp_advertised |= ixgbe_lp_map[i].mac_speed;
3441	}
3442
3443	edata->supported = 0;
3444	for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3445	if (hw->phy.eee_speeds_supported & ixgbe_ls_map[i].mac_speed)
3446	edata->supported |= ixgbe_ls_map[i].supported;
3447	}
3448
3449	edata->advertised = 0;
3450	for (i = 0; i < ARRAY_SIZE(ixgbe_ls_map); ++i) {
3451	if (hw->phy.eee_speeds_advertised & ixgbe_ls_map[i].mac_speed)
3452	edata->advertised |= ixgbe_ls_map[i].supported;
3453	}
3454
3455	edata->eee_enabled = !!edata->advertised;
3456	edata->tx_lpi_enabled = edata->eee_enabled;
3457	if (edata->advertised & edata->lp_advertised)
3458	edata->eee_active = true;
3459
3460	return 0;
3461	}
3462
3463	static int ixgbe_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3464	{
3465	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3466	struct ixgbe_hw *hw = &adapter->hw;
3467
3468	if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3469	return -EOPNOTSUPP;
3470
3471	if (hw->phy.eee_speeds_supported && hw->phy.type == ixgbe_phy_fw)
3472	return ixgbe_get_eee_fw(adapter, edata);
3473
3474	return -EOPNOTSUPP;
3475	}
3476
3477	static int ixgbe_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
3478	{
3479	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3480	struct ixgbe_hw *hw = &adapter->hw;
3481	struct ethtool_eee eee_data;
3482	s32 ret_val;
3483
3484	if (!(adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE))
3485	return -EOPNOTSUPP;
3486
3487	memset(&eee_data, 0, sizeof(struct ethtool_eee));
3488
3489	ret_val = ixgbe_get_eee(netdev, edata: &eee_data);
3490	if (ret_val)
3491	return ret_val;
3492
3493	if (eee_data.eee_enabled && !edata->eee_enabled) {
3494	if (eee_data.tx_lpi_enabled != edata->tx_lpi_enabled) {
3495	e_err(drv, "Setting EEE tx-lpi is not supported\n");
3496	return -EINVAL;
3497	}
3498
3499	if (eee_data.tx_lpi_timer != edata->tx_lpi_timer) {
3500	e_err(drv,
3501	"Setting EEE Tx LPI timer is not supported\n");
3502	return -EINVAL;
3503	}
3504
3505	if (eee_data.advertised != edata->advertised) {
3506	e_err(drv,
3507	"Setting EEE advertised speeds is not supported\n");
3508	return -EINVAL;
3509	}
3510	}
3511
3512	if (eee_data.eee_enabled != edata->eee_enabled) {
3513	if (edata->eee_enabled) {
3514	adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
3515	hw->phy.eee_speeds_advertised =
3516	hw->phy.eee_speeds_supported;
3517	} else {
3518	adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
3519	hw->phy.eee_speeds_advertised = 0;
3520	}
3521
3522	/* reset link */
3523	if (netif_running(dev: netdev))
3524	ixgbe_reinit_locked(adapter);
3525	else
3526	ixgbe_reset(adapter);
3527	}
3528
3529	return 0;
3530	}
3531
3532	static u32 ixgbe_get_priv_flags(struct net_device *netdev)
3533	{
3534	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3535	u32 priv_flags = 0;
3536
3537	if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
3538	priv_flags |= IXGBE_PRIV_FLAGS_LEGACY_RX;
3539
3540	if (adapter->flags2 & IXGBE_FLAG2_VF_IPSEC_ENABLED)
3541	priv_flags |= IXGBE_PRIV_FLAGS_VF_IPSEC_EN;
3542
3543	if (adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF)
3544	priv_flags |= IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF;
3545
3546	return priv_flags;
3547	}
3548
3549	static int ixgbe_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3550	{
3551	struct ixgbe_adapter *adapter = netdev_priv(dev: netdev);
3552	unsigned int flags2 = adapter->flags2;
3553	unsigned int i;
3554
3555	flags2 &= ~IXGBE_FLAG2_RX_LEGACY;
3556	if (priv_flags & IXGBE_PRIV_FLAGS_LEGACY_RX)
3557	flags2 |= IXGBE_FLAG2_RX_LEGACY;
3558
3559	flags2 &= ~IXGBE_FLAG2_VF_IPSEC_ENABLED;
3560	if (priv_flags & IXGBE_PRIV_FLAGS_VF_IPSEC_EN)
3561	flags2 |= IXGBE_FLAG2_VF_IPSEC_ENABLED;
3562
3563	flags2 &= ~IXGBE_FLAG2_AUTO_DISABLE_VF;
3564	if (priv_flags & IXGBE_PRIV_FLAGS_AUTO_DISABLE_VF) {
3565	if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3566	/* Reset primary abort counter */
3567	for (i = 0; i < adapter->num_vfs; i++)
3568	adapter->vfinfo[i].primary_abort_count = 0;
3569
3570	flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF;
3571	} else {
3572	e_info(probe,
3573	"Cannot set private flags: Operation not supported\n");
3574	return -EOPNOTSUPP;
3575	}
3576	}
3577
3578	if (flags2 != adapter->flags2) {
3579	adapter->flags2 = flags2;
3580
3581	/* reset interface to repopulate queues */
3582	if (netif_running(dev: netdev))
3583	ixgbe_reinit_locked(adapter);
3584	}
3585
3586	return 0;
3587	}
3588
3589	static const struct ethtool_ops ixgbe_ethtool_ops = {
3590	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3591	.get_drvinfo = ixgbe_get_drvinfo,
3592	.get_regs_len = ixgbe_get_regs_len,
3593	.get_regs = ixgbe_get_regs,
3594	.get_wol = ixgbe_get_wol,
3595	.set_wol = ixgbe_set_wol,
3596	.nway_reset = ixgbe_nway_reset,
3597	.get_link = ethtool_op_get_link,
3598	.get_eeprom_len = ixgbe_get_eeprom_len,
3599	.get_eeprom = ixgbe_get_eeprom,
3600	.set_eeprom = ixgbe_set_eeprom,
3601	.get_ringparam = ixgbe_get_ringparam,
3602	.set_ringparam = ixgbe_set_ringparam,
3603	.get_pause_stats = ixgbe_get_pause_stats,
3604	.get_pauseparam = ixgbe_get_pauseparam,
3605	.set_pauseparam = ixgbe_set_pauseparam,
3606	.get_msglevel = ixgbe_get_msglevel,
3607	.set_msglevel = ixgbe_set_msglevel,
3608	.self_test = ixgbe_diag_test,
3609	.get_strings = ixgbe_get_strings,
3610	.set_phys_id = ixgbe_set_phys_id,
3611	.get_sset_count = ixgbe_get_sset_count,
3612	.get_ethtool_stats = ixgbe_get_ethtool_stats,
3613	.get_coalesce = ixgbe_get_coalesce,
3614	.set_coalesce = ixgbe_set_coalesce,
3615	.get_rxnfc = ixgbe_get_rxnfc,
3616	.set_rxnfc = ixgbe_set_rxnfc,
3617	.get_rxfh_indir_size = ixgbe_rss_indir_size,
3618	.get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3619	.get_rxfh = ixgbe_get_rxfh,
3620	.set_rxfh = ixgbe_set_rxfh,
3621	.get_eee = ixgbe_get_eee,
3622	.set_eee = ixgbe_set_eee,
3623	.get_channels = ixgbe_get_channels,
3624	.set_channels = ixgbe_set_channels,
3625	.get_priv_flags = ixgbe_get_priv_flags,
3626	.set_priv_flags = ixgbe_set_priv_flags,
3627	.get_ts_info = ixgbe_get_ts_info,
3628	.get_module_info = ixgbe_get_module_info,
3629	.get_module_eeprom = ixgbe_get_module_eeprom,
3630	.get_link_ksettings = ixgbe_get_link_ksettings,
3631	.set_link_ksettings = ixgbe_set_link_ksettings,
3632	};
3633
3634	void ixgbe_set_ethtool_ops(struct net_device *netdev)
3635	{
3636	netdev->ethtool_ops = &ixgbe_ethtool_ops;
3637	}
3638