1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* NVM Express device driver
4	* Copyright (c) 2011-2014, Intel Corporation.
5	*/
6
7	#include <linux/acpi.h>
8	#include <linux/async.h>
9	#include <linux/blkdev.h>
10	#include <linux/blk-mq.h>
11	#include <linux/blk-integrity.h>
12	#include <linux/dmi.h>
13	#include <linux/init.h>
14	#include <linux/interrupt.h>
15	#include <linux/io.h>
16	#include <linux/kstrtox.h>
17	#include <linux/memremap.h>
18	#include <linux/mm.h>
19	#include <linux/module.h>
20	#include <linux/mutex.h>
21	#include <linux/nodemask.h>
22	#include <linux/once.h>
23	#include <linux/pci.h>
24	#include <linux/suspend.h>
25	#include <linux/t10-pi.h>
26	#include <linux/types.h>
27	#include <linux/io-64-nonatomic-lo-hi.h>
28	#include <linux/io-64-nonatomic-hi-lo.h>
29	#include <linux/sed-opal.h>
30	#include <linux/pci-p2pdma.h>
31
32	#include "trace.h"
33	#include "nvme.h"
34
35	#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36	#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38	/* Optimisation for I/Os between 4k and 128k */
39	#define NVME_SMALL_POOL_SIZE 256
40
41	/*
42	* These can be higher, but we need to ensure that any command doesn't
43	* require an sg allocation that needs more than a page of data.
44	*/
45	#define NVME_MAX_KB_SZ 8192
46	#define NVME_MAX_NR_DESCRIPTORS 5
47
48	/*
49	* For data SGLs we support a single descriptors worth of SGL entries, but for
50	* now we also limit it to avoid an allocation larger than PAGE_SIZE for the
51	* scatterlist.
52	*/
53	#define NVME_MAX_SEGS \
54	min(NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc), \
55	(PAGE_SIZE / sizeof(struct scatterlist)))
56
57	/*
58	* For metadata SGLs, only the small descriptor is supported, and the first
59	* entry is the segment descriptor, which for the data pointer sits in the SQE.
60	*/
61	#define NVME_MAX_META_SEGS \
62	((NVME_SMALL_POOL_SIZE / sizeof(struct nvme_sgl_desc)) - 1)
63
64	static int use_threaded_interrupts;
65	module_param(use_threaded_interrupts, int, 0444);
66
67	static bool use_cmb_sqes = true;
68	module_param(use_cmb_sqes, bool, 0444);
69	MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
70
71	static unsigned int max_host_mem_size_mb = 128;
72	module_param(max_host_mem_size_mb, uint, 0444);
73	MODULE_PARM_DESC(max_host_mem_size_mb,
74	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
75
76	static unsigned int sgl_threshold = SZ_32K;
77	module_param(sgl_threshold, uint, 0644);
78	MODULE_PARM_DESC(sgl_threshold,
79	"Use SGLs when average request segment size is larger or equal to "
80	"this size. Use 0 to disable SGLs.");
81
82	#define NVME_PCI_MIN_QUEUE_SIZE 2
83	#define NVME_PCI_MAX_QUEUE_SIZE 4095
84	static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
85	static const struct kernel_param_ops io_queue_depth_ops = {
86	.set = io_queue_depth_set,
87	.get = param_get_uint,
88	};
89
90	static unsigned int io_queue_depth = 1024;
91	module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
92	MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
93
94	static int io_queue_count_set(const char *val, const struct kernel_param *kp)
95	{
96	unsigned int n;
97	int ret;
98
99	ret = kstrtouint(s: val, base: 10, res: &n);
100	if (ret != 0 || n > num_possible_cpus())
101	return -EINVAL;
102	return param_set_uint(val, kp);
103	}
104
105	static const struct kernel_param_ops io_queue_count_ops = {
106	.set = io_queue_count_set,
107	.get = param_get_uint,
108	};
109
110	static unsigned int write_queues;
111	module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
112	MODULE_PARM_DESC(write_queues,
113	"Number of queues to use for writes. If not set, reads and writes "
114	"will share a queue set.");
115
116	static unsigned int poll_queues;
117	module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
118	MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
119
120	static bool noacpi;
121	module_param(noacpi, bool, 0444);
122	MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
123
124	struct nvme_dev;
125	struct nvme_queue;
126
127	static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
128	static void nvme_delete_io_queues(struct nvme_dev *dev);
129	static void nvme_update_attrs(struct nvme_dev *dev);
130
131	struct nvme_descriptor_pools {
132	struct dma_pool *large;
133	struct dma_pool *small;
134	};
135
136	/*
137	* Represents an NVM Express device. Each nvme_dev is a PCI function.
138	*/
139	struct nvme_dev {
140	struct nvme_queue *queues;
141	struct blk_mq_tag_set tagset;
142	struct blk_mq_tag_set admin_tagset;
143	u32 __iomem *dbs;
144	struct device *dev;
145	unsigned online_queues;
146	unsigned max_qid;
147	unsigned io_queues[HCTX_MAX_TYPES];
148	unsigned int num_vecs;
149	u32 q_depth;
150	int io_sqes;
151	u32 db_stride;
152	void __iomem *bar;
153	unsigned long bar_mapped_size;
154	struct mutex shutdown_lock;
155	bool subsystem;
156	u64 cmb_size;
157	bool cmb_use_sqes;
158	u32 cmbsz;
159	u32 cmbloc;
160	struct nvme_ctrl ctrl;
161	u32 last_ps;
162	bool hmb;
163	struct sg_table *hmb_sgt;
164
165	mempool_t *iod_mempool;
166	mempool_t *iod_meta_mempool;
167
168	/* shadow doorbell buffer support: */
169	__le32 *dbbuf_dbs;
170	dma_addr_t dbbuf_dbs_dma_addr;
171	__le32 *dbbuf_eis;
172	dma_addr_t dbbuf_eis_dma_addr;
173
174	/* host memory buffer support: */
175	u64 host_mem_size;
176	u32 nr_host_mem_descs;
177	u32 host_mem_descs_size;
178	dma_addr_t host_mem_descs_dma;
179	struct nvme_host_mem_buf_desc *host_mem_descs;
180	void **host_mem_desc_bufs;
181	unsigned int nr_allocated_queues;
182	unsigned int nr_write_queues;
183	unsigned int nr_poll_queues;
184	struct nvme_descriptor_pools descriptor_pools[];
185	};
186
187	static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
188	{
189	return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
190	NVME_PCI_MAX_QUEUE_SIZE);
191	}
192
193	static inline unsigned int sq_idx(unsigned int qid, u32 stride)
194	{
195	return qid * 2 * stride;
196	}
197
198	static inline unsigned int cq_idx(unsigned int qid, u32 stride)
199	{
200	return (qid * 2 + 1) * stride;
201	}
202
203	static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
204	{
205	return container_of(ctrl, struct nvme_dev, ctrl);
206	}
207
208	/*
209	* An NVM Express queue. Each device has at least two (one for admin
210	* commands and one for I/O commands).
211	*/
212	struct nvme_queue {
213	struct nvme_dev *dev;
214	struct nvme_descriptor_pools descriptor_pools;
215	spinlock_t sq_lock;
216	void *sq_cmds;
217	/* only used for poll queues: */
218	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
219	struct nvme_completion *cqes;
220	dma_addr_t sq_dma_addr;
221	dma_addr_t cq_dma_addr;
222	u32 __iomem *q_db;
223	u32 q_depth;
224	u16 cq_vector;
225	u16 sq_tail;
226	u16 last_sq_tail;
227	u16 cq_head;
228	u16 qid;
229	u8 cq_phase;
230	u8 sqes;
231	unsigned long flags;
232	#define NVMEQ_ENABLED 0
233	#define NVMEQ_SQ_CMB 1
234	#define NVMEQ_DELETE_ERROR 2
235	#define NVMEQ_POLLED 3
236	__le32 *dbbuf_sq_db;
237	__le32 *dbbuf_cq_db;
238	__le32 *dbbuf_sq_ei;
239	__le32 *dbbuf_cq_ei;
240	struct completion delete_done;
241	};
242
243	/* bits for iod->flags */
244	enum nvme_iod_flags {
245	/* this command has been aborted by the timeout handler */
246	IOD_ABORTED = 1U << 0,
247
248	/* uses the small descriptor pool */
249	IOD_SMALL_DESCRIPTOR = 1U << 1,
250	};
251
252	/*
253	* The nvme_iod describes the data in an I/O.
254	*/
255	struct nvme_iod {
256	struct nvme_request req;
257	struct nvme_command cmd;
258	u8 flags;
259	u8 nr_descriptors;
260	unsigned int dma_len; /* length of single DMA segment mapping */
261	dma_addr_t first_dma;
262	dma_addr_t meta_dma;
263	struct sg_table sgt;
264	struct sg_table meta_sgt;
265	struct nvme_sgl_desc *meta_descriptor;
266	void *descriptors[NVME_MAX_NR_DESCRIPTORS];
267	};
268
269	static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
270	{
271	return dev->nr_allocated_queues * 8 * dev->db_stride;
272	}
273
274	static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
275	{
276	unsigned int mem_size = nvme_dbbuf_size(dev);
277
278	if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
279	return;
280
281	if (dev->dbbuf_dbs) {
282	/*
283	* Clear the dbbuf memory so the driver doesn't observe stale
284	* values from the previous instantiation.
285	*/
286	memset(dev->dbbuf_dbs, 0, mem_size);
287	memset(dev->dbbuf_eis, 0, mem_size);
288	return;
289	}
290
291	dev->dbbuf_dbs = dma_alloc_coherent(dev: dev->dev, size: mem_size,
292	dma_handle: &dev->dbbuf_dbs_dma_addr,
293	GFP_KERNEL);
294	if (!dev->dbbuf_dbs)
295	goto fail;
296	dev->dbbuf_eis = dma_alloc_coherent(dev: dev->dev, size: mem_size,
297	dma_handle: &dev->dbbuf_eis_dma_addr,
298	GFP_KERNEL);
299	if (!dev->dbbuf_eis)
300	goto fail_free_dbbuf_dbs;
301	return;
302
303	fail_free_dbbuf_dbs:
304	dma_free_coherent(dev: dev->dev, size: mem_size, cpu_addr: dev->dbbuf_dbs,
305	dma_handle: dev->dbbuf_dbs_dma_addr);
306	dev->dbbuf_dbs = NULL;
307	fail:
308	dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
309	}
310
311	static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
312	{
313	unsigned int mem_size = nvme_dbbuf_size(dev);
314
315	if (dev->dbbuf_dbs) {
316	dma_free_coherent(dev: dev->dev, size: mem_size,
317	cpu_addr: dev->dbbuf_dbs, dma_handle: dev->dbbuf_dbs_dma_addr);
318	dev->dbbuf_dbs = NULL;
319	}
320	if (dev->dbbuf_eis) {
321	dma_free_coherent(dev: dev->dev, size: mem_size,
322	cpu_addr: dev->dbbuf_eis, dma_handle: dev->dbbuf_eis_dma_addr);
323	dev->dbbuf_eis = NULL;
324	}
325	}
326
327	static void nvme_dbbuf_init(struct nvme_dev *dev,
328	struct nvme_queue *nvmeq, int qid)
329	{
330	if (!dev->dbbuf_dbs || !qid)
331	return;
332
333	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, stride: dev->db_stride)];
334	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, stride: dev->db_stride)];
335	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, stride: dev->db_stride)];
336	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, stride: dev->db_stride)];
337	}
338
339	static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
340	{
341	if (!nvmeq->qid)
342	return;
343
344	nvmeq->dbbuf_sq_db = NULL;
345	nvmeq->dbbuf_cq_db = NULL;
346	nvmeq->dbbuf_sq_ei = NULL;
347	nvmeq->dbbuf_cq_ei = NULL;
348	}
349
350	static void nvme_dbbuf_set(struct nvme_dev *dev)
351	{
352	struct nvme_command c = { };
353	unsigned int i;
354
355	if (!dev->dbbuf_dbs)
356	return;
357
358	c.dbbuf.opcode = nvme_admin_dbbuf;
359	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
360	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
361
362	if (nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0)) {
363	dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
364	/* Free memory and continue on */
365	nvme_dbbuf_dma_free(dev);
366
367	for (i = 1; i <= dev->online_queues; i++)
368	nvme_dbbuf_free(nvmeq: &dev->queues[i]);
369	}
370	}
371
372	static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
373	{
374	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
375	}
376
377	/* Update dbbuf and return true if an MMIO is required */
378	static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
379	volatile __le32 *dbbuf_ei)
380	{
381	if (dbbuf_db) {
382	u16 old_value, event_idx;
383
384	/*
385	* Ensure that the queue is written before updating
386	* the doorbell in memory
387	*/
388	wmb();
389
390	old_value = le32_to_cpu(*dbbuf_db);
391	*dbbuf_db = cpu_to_le32(value);
392
393	/*
394	* Ensure that the doorbell is updated before reading the event
395	* index from memory. The controller needs to provide similar
396	* ordering to ensure the event index is updated before reading
397	* the doorbell.
398	*/
399	mb();
400
401	event_idx = le32_to_cpu(*dbbuf_ei);
402	if (!nvme_dbbuf_need_event(event_idx, new_idx: value, old: old_value))
403	return false;
404	}
405
406	return true;
407	}
408
409	/*
410	* Will slightly overestimate the number of pages needed. This is OK
411	* as it only leads to a small amount of wasted memory for the lifetime of
412	* the I/O.
413	*/
414	static __always_inline int nvme_pci_npages_prp(void)
415	{
416	unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
417	unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
418	return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
419	}
420
421	static struct nvme_descriptor_pools *
422	nvme_setup_descriptor_pools(struct nvme_dev *dev, unsigned numa_node)
423	{
424	struct nvme_descriptor_pools *pools = &dev->descriptor_pools[numa_node];
425	size_t small_align = NVME_SMALL_POOL_SIZE;
426
427	if (pools->small)
428	return pools; /* already initialized */
429
430	pools->large = dma_pool_create_node(name: "nvme descriptor page", dev: dev->dev,
431	NVME_CTRL_PAGE_SIZE, NVME_CTRL_PAGE_SIZE, boundary: 0, node: numa_node);
432	if (!pools->large)
433	return ERR_PTR(error: -ENOMEM);
434
435	if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512)
436	small_align = 512;
437
438	pools->small = dma_pool_create_node(name: "nvme descriptor small", dev: dev->dev,
439	NVME_SMALL_POOL_SIZE, align: small_align, boundary: 0, node: numa_node);
440	if (!pools->small) {
441	dma_pool_destroy(pool: pools->large);
442	pools->large = NULL;
443	return ERR_PTR(error: -ENOMEM);
444	}
445
446	return pools;
447	}
448
449	static void nvme_release_descriptor_pools(struct nvme_dev *dev)
450	{
451	unsigned i;
452
453	for (i = 0; i < nr_node_ids; i++) {
454	struct nvme_descriptor_pools *pools = &dev->descriptor_pools[i];
455
456	dma_pool_destroy(pool: pools->large);
457	dma_pool_destroy(pool: pools->small);
458	}
459	}
460
461	static int nvme_init_hctx_common(struct blk_mq_hw_ctx *hctx, void *data,
462	unsigned qid)
463	{
464	struct nvme_dev *dev = to_nvme_dev(ctrl: data);
465	struct nvme_queue *nvmeq = &dev->queues[qid];
466	struct nvme_descriptor_pools *pools;
467	struct blk_mq_tags *tags;
468
469	tags = qid ? dev->tagset.tags[qid - 1] : dev->admin_tagset.tags[0];
470	WARN_ON(tags != hctx->tags);
471	pools = nvme_setup_descriptor_pools(dev, numa_node: hctx->numa_node);
472	if (IS_ERR(ptr: pools))
473	return PTR_ERR(ptr: pools);
474
475	nvmeq->descriptor_pools = *pools;
476	hctx->driver_data = nvmeq;
477	return 0;
478	}
479
480	static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
481	unsigned int hctx_idx)
482	{
483	WARN_ON(hctx_idx != 0);
484	return nvme_init_hctx_common(hctx, data, qid: 0);
485	}
486
487	static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
488	unsigned int hctx_idx)
489	{
490	return nvme_init_hctx_common(hctx, data, qid: hctx_idx + 1);
491	}
492
493	static int nvme_pci_init_request(struct blk_mq_tag_set *set,
494	struct request *req, unsigned int hctx_idx,
495	unsigned int numa_node)
496	{
497	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
498
499	nvme_req(req)->ctrl = set->driver_data;
500	nvme_req(req)->cmd = &iod->cmd;
501	return 0;
502	}
503
504	static int queue_irq_offset(struct nvme_dev *dev)
505	{
506	/* if we have more than 1 vec, admin queue offsets us by 1 */
507	if (dev->num_vecs > 1)
508	return 1;
509
510	return 0;
511	}
512
513	static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
514	{
515	struct nvme_dev *dev = to_nvme_dev(ctrl: set->driver_data);
516	int i, qoff, offset;
517
518	offset = queue_irq_offset(dev);
519	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
520	struct blk_mq_queue_map *map = &set->map[i];
521
522	map->nr_queues = dev->io_queues[i];
523	if (!map->nr_queues) {
524	BUG_ON(i == HCTX_TYPE_DEFAULT);
525	continue;
526	}
527
528	/*
529	* The poll queue(s) doesn't have an IRQ (and hence IRQ
530	* affinity), so use the regular blk-mq cpu mapping
531	*/
532	map->queue_offset = qoff;
533	if (i != HCTX_TYPE_POLL && offset)
534	blk_mq_map_hw_queues(qmap: map, dev: dev->dev, offset);
535	else
536	blk_mq_map_queues(qmap: map);
537	qoff += map->nr_queues;
538	offset += map->nr_queues;
539	}
540	}
541
542	/*
543	* Write sq tail if we are asked to, or if the next command would wrap.
544	*/
545	static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
546	{
547	if (!write_sq) {
548	u16 next_tail = nvmeq->sq_tail + 1;
549
550	if (next_tail == nvmeq->q_depth)
551	next_tail = 0;
552	if (next_tail != nvmeq->last_sq_tail)
553	return;
554	}
555
556	if (nvme_dbbuf_update_and_check_event(value: nvmeq->sq_tail,
557	dbbuf_db: nvmeq->dbbuf_sq_db, dbbuf_ei: nvmeq->dbbuf_sq_ei))
558	writel(val: nvmeq->sq_tail, addr: nvmeq->q_db);
559	nvmeq->last_sq_tail = nvmeq->sq_tail;
560	}
561
562	static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
563	struct nvme_command *cmd)
564	{
565	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
566	absolute_pointer(cmd), sizeof(*cmd));
567	if (++nvmeq->sq_tail == nvmeq->q_depth)
568	nvmeq->sq_tail = 0;
569	}
570
571	static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
572	{
573	struct nvme_queue *nvmeq = hctx->driver_data;
574
575	spin_lock(lock: &nvmeq->sq_lock);
576	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
577	nvme_write_sq_db(nvmeq, write_sq: true);
578	spin_unlock(lock: &nvmeq->sq_lock);
579	}
580
581	static inline bool nvme_pci_metadata_use_sgls(struct nvme_dev *dev,
582	struct request *req)
583	{
584	if (!nvme_ctrl_meta_sgl_supported(ctrl: &dev->ctrl))
585	return false;
586	return req->nr_integrity_segments > 1 ||
587	nvme_req(req)->flags & NVME_REQ_USERCMD;
588	}
589
590	static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
591	int nseg)
592	{
593	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
594	unsigned int avg_seg_size;
595
596	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
597
598	if (!nvme_ctrl_sgl_supported(ctrl: &dev->ctrl))
599	return false;
600	if (!nvmeq->qid)
601	return false;
602	if (nvme_pci_metadata_use_sgls(dev, req))
603	return true;
604	if (!sgl_threshold || avg_seg_size < sgl_threshold)
605	return nvme_req(req)->flags & NVME_REQ_USERCMD;
606	return true;
607	}
608
609	static inline struct dma_pool *nvme_dma_pool(struct nvme_queue *nvmeq,
610	struct nvme_iod *iod)
611	{
612	if (iod->flags & IOD_SMALL_DESCRIPTOR)
613	return nvmeq->descriptor_pools.small;
614	return nvmeq->descriptor_pools.large;
615	}
616
617	static void nvme_free_descriptors(struct nvme_queue *nvmeq, struct request *req)
618	{
619	const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
620	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
621	dma_addr_t dma_addr = iod->first_dma;
622	int i;
623
624	if (iod->nr_descriptors == 1) {
625	dma_pool_free(pool: nvme_dma_pool(nvmeq, iod), vaddr: iod->descriptors[0],
626	addr: dma_addr);
627	return;
628	}
629
630	for (i = 0; i < iod->nr_descriptors; i++) {
631	__le64 *prp_list = iod->descriptors[i];
632	dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
633
634	dma_pool_free(pool: nvmeq->descriptor_pools.large, vaddr: prp_list,
635	addr: dma_addr);
636	dma_addr = next_dma_addr;
637	}
638	}
639
640	static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_queue *nvmeq,
641	struct request *req)
642	{
643	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
644
645	if (iod->dma_len) {
646	dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
647	rq_dma_dir(req));
648	return;
649	}
650
651	WARN_ON_ONCE(!iod->sgt.nents);
652
653	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req), attrs: 0);
654	nvme_free_descriptors(nvmeq, req);
655	mempool_free(element: iod->sgt.sgl, pool: dev->iod_mempool);
656	}
657
658	static void nvme_print_sgl(struct scatterlist *sgl, int nents)
659	{
660	int i;
661	struct scatterlist *sg;
662
663	for_each_sg(sgl, sg, nents, i) {
664	dma_addr_t phys = sg_phys(sg);
665	pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
666	"dma_address:%pad dma_length:%d\n",
667	i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
668	sg_dma_len(sg));
669	}
670	}
671
672	static blk_status_t nvme_pci_setup_prps(struct nvme_queue *nvmeq,
673	struct request *req, struct nvme_rw_command *cmnd)
674	{
675	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
676	int length = blk_rq_payload_bytes(rq: req);
677	struct scatterlist *sg = iod->sgt.sgl;
678	int dma_len = sg_dma_len(sg);
679	u64 dma_addr = sg_dma_address(sg);
680	int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
681	__le64 *prp_list;
682	dma_addr_t prp_dma;
683	int i;
684
685	length -= (NVME_CTRL_PAGE_SIZE - offset);
686	if (length <= 0) {
687	iod->first_dma = 0;
688	goto done;
689	}
690
691	dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
692	if (dma_len) {
693	dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
694	} else {
695	sg = sg_next(sg);
696	dma_addr = sg_dma_address(sg);
697	dma_len = sg_dma_len(sg);
698	}
699
700	if (length <= NVME_CTRL_PAGE_SIZE) {
701	iod->first_dma = dma_addr;
702	goto done;
703	}
704
705	if (DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE) <=
706	NVME_SMALL_POOL_SIZE / sizeof(__le64))
707	iod->flags |= IOD_SMALL_DESCRIPTOR;
708
709	prp_list = dma_pool_alloc(pool: nvme_dma_pool(nvmeq, iod), GFP_ATOMIC,
710	handle: &prp_dma);
711	if (!prp_list)
712	return BLK_STS_RESOURCE;
713	iod->descriptors[iod->nr_descriptors++] = prp_list;
714	iod->first_dma = prp_dma;
715	i = 0;
716	for (;;) {
717	if (i == NVME_CTRL_PAGE_SIZE >> 3) {
718	__le64 *old_prp_list = prp_list;
719
720	prp_list = dma_pool_alloc(pool: nvmeq->descriptor_pools.large,
721	GFP_ATOMIC, handle: &prp_dma);
722	if (!prp_list)
723	goto free_prps;
724	iod->descriptors[iod->nr_descriptors++] = prp_list;
725	prp_list[0] = old_prp_list[i - 1];
726	old_prp_list[i - 1] = cpu_to_le64(prp_dma);
727	i = 1;
728	}
729	prp_list[i++] = cpu_to_le64(dma_addr);
730	dma_len -= NVME_CTRL_PAGE_SIZE;
731	dma_addr += NVME_CTRL_PAGE_SIZE;
732	length -= NVME_CTRL_PAGE_SIZE;
733	if (length <= 0)
734	break;
735	if (dma_len > 0)
736	continue;
737	if (unlikely(dma_len < 0))
738	goto bad_sgl;
739	sg = sg_next(sg);
740	dma_addr = sg_dma_address(sg);
741	dma_len = sg_dma_len(sg);
742	}
743	done:
744	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
745	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
746	return BLK_STS_OK;
747	free_prps:
748	nvme_free_descriptors(nvmeq, req);
749	return BLK_STS_RESOURCE;
750	bad_sgl:
751	WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
752	"Invalid SGL for payload:%d nents:%d\n",
753	blk_rq_payload_bytes(req), iod->sgt.nents);
754	return BLK_STS_IOERR;
755	}
756
757	static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
758	struct scatterlist *sg)
759	{
760	sge->addr = cpu_to_le64(sg_dma_address(sg));
761	sge->length = cpu_to_le32(sg_dma_len(sg));
762	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
763	}
764
765	static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
766	dma_addr_t dma_addr, int entries)
767	{
768	sge->addr = cpu_to_le64(dma_addr);
769	sge->length = cpu_to_le32(entries * sizeof(*sge));
770	sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
771	}
772
773	static blk_status_t nvme_pci_setup_sgls(struct nvme_queue *nvmeq,
774	struct request *req, struct nvme_rw_command *cmd)
775	{
776	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
777	struct nvme_sgl_desc *sg_list;
778	struct scatterlist *sg = iod->sgt.sgl;
779	unsigned int entries = iod->sgt.nents;
780	dma_addr_t sgl_dma;
781	int i = 0;
782
783	/* setting the transfer type as SGL */
784	cmd->flags = NVME_CMD_SGL_METABUF;
785
786	if (entries == 1) {
787	nvme_pci_sgl_set_data(sge: &cmd->dptr.sgl, sg);
788	return BLK_STS_OK;
789	}
790
791	if (entries <= NVME_SMALL_POOL_SIZE / sizeof(*sg_list))
792	iod->flags |= IOD_SMALL_DESCRIPTOR;
793
794	sg_list = dma_pool_alloc(pool: nvme_dma_pool(nvmeq, iod), GFP_ATOMIC,
795	handle: &sgl_dma);
796	if (!sg_list)
797	return BLK_STS_RESOURCE;
798	iod->descriptors[iod->nr_descriptors++] = sg_list;
799	iod->first_dma = sgl_dma;
800
801	nvme_pci_sgl_set_seg(sge: &cmd->dptr.sgl, dma_addr: sgl_dma, entries);
802	do {
803	nvme_pci_sgl_set_data(sge: &sg_list[i++], sg);
804	sg = sg_next(sg);
805	} while (--entries > 0);
806
807	return BLK_STS_OK;
808	}
809
810	static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
811	struct request *req, struct nvme_rw_command *cmnd,
812	struct bio_vec *bv)
813	{
814	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
815	unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
816	unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
817
818	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
819	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->first_dma))
820	return BLK_STS_RESOURCE;
821	iod->dma_len = bv->bv_len;
822
823	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
824	if (bv->bv_len > first_prp_len)
825	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
826	else
827	cmnd->dptr.prp2 = 0;
828	return BLK_STS_OK;
829	}
830
831	static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
832	struct request *req, struct nvme_rw_command *cmnd,
833	struct bio_vec *bv)
834	{
835	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
836
837	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
838	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->first_dma))
839	return BLK_STS_RESOURCE;
840	iod->dma_len = bv->bv_len;
841
842	cmnd->flags = NVME_CMD_SGL_METABUF;
843	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
844	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
845	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
846	return BLK_STS_OK;
847	}
848
849	static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
850	struct nvme_command *cmnd)
851	{
852	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
853	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
854	blk_status_t ret = BLK_STS_RESOURCE;
855	int rc;
856
857	if (blk_rq_nr_phys_segments(rq: req) == 1) {
858	struct bio_vec bv = req_bvec(rq: req);
859
860	if (!is_pci_p2pdma_page(page: bv.bv_page)) {
861	if (!nvme_pci_metadata_use_sgls(dev, req) &&
862	(bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) +
863	bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
864	return nvme_setup_prp_simple(dev, req,
865	cmnd: &cmnd->rw, bv: &bv);
866
867	if (nvmeq->qid && sgl_threshold &&
868	nvme_ctrl_sgl_supported(ctrl: &dev->ctrl))
869	return nvme_setup_sgl_simple(dev, req,
870	cmnd: &cmnd->rw, bv: &bv);
871	}
872	}
873
874	iod->dma_len = 0;
875	iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
876	if (!iod->sgt.sgl)
877	return BLK_STS_RESOURCE;
878	sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(rq: req));
879	iod->sgt.orig_nents = blk_rq_map_sg(rq: req, sglist: iod->sgt.sgl);
880	if (!iod->sgt.orig_nents)
881	goto out_free_sg;
882
883	rc = dma_map_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req),
884	DMA_ATTR_NO_WARN);
885	if (rc) {
886	if (rc == -EREMOTEIO)
887	ret = BLK_STS_TARGET;
888	goto out_free_sg;
889	}
890
891	if (nvme_pci_use_sgls(dev, req, nseg: iod->sgt.nents))
892	ret = nvme_pci_setup_sgls(nvmeq, req, cmd: &cmnd->rw);
893	else
894	ret = nvme_pci_setup_prps(nvmeq, req, cmnd: &cmnd->rw);
895	if (ret != BLK_STS_OK)
896	goto out_unmap_sg;
897	return BLK_STS_OK;
898
899	out_unmap_sg:
900	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->sgt, rq_dma_dir(req), attrs: 0);
901	out_free_sg:
902	mempool_free(element: iod->sgt.sgl, pool: dev->iod_mempool);
903	return ret;
904	}
905
906	static blk_status_t nvme_pci_setup_meta_sgls(struct nvme_dev *dev,
907	struct request *req)
908	{
909	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
910	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
911	struct nvme_rw_command *cmnd = &iod->cmd.rw;
912	struct nvme_sgl_desc *sg_list;
913	struct scatterlist *sgl, *sg;
914	unsigned int entries;
915	dma_addr_t sgl_dma;
916	int rc, i;
917
918	iod->meta_sgt.sgl = mempool_alloc(dev->iod_meta_mempool, GFP_ATOMIC);
919	if (!iod->meta_sgt.sgl)
920	return BLK_STS_RESOURCE;
921
922	sg_init_table(iod->meta_sgt.sgl, req->nr_integrity_segments);
923	iod->meta_sgt.orig_nents = blk_rq_map_integrity_sg(req,
924	iod->meta_sgt.sgl);
925	if (!iod->meta_sgt.orig_nents)
926	goto out_free_sg;
927
928	rc = dma_map_sgtable(dev: dev->dev, sgt: &iod->meta_sgt, rq_dma_dir(req),
929	DMA_ATTR_NO_WARN);
930	if (rc)
931	goto out_free_sg;
932
933	sg_list = dma_pool_alloc(pool: nvmeq->descriptor_pools.small, GFP_ATOMIC,
934	handle: &sgl_dma);
935	if (!sg_list)
936	goto out_unmap_sg;
937
938	entries = iod->meta_sgt.nents;
939	iod->meta_descriptor = sg_list;
940	iod->meta_dma = sgl_dma;
941
942	cmnd->flags = NVME_CMD_SGL_METASEG;
943	cmnd->metadata = cpu_to_le64(sgl_dma);
944
945	sgl = iod->meta_sgt.sgl;
946	if (entries == 1) {
947	nvme_pci_sgl_set_data(sge: sg_list, sg: sgl);
948	return BLK_STS_OK;
949	}
950
951	sgl_dma += sizeof(*sg_list);
952	nvme_pci_sgl_set_seg(sge: sg_list, dma_addr: sgl_dma, entries);
953	for_each_sg(sgl, sg, entries, i)
954	nvme_pci_sgl_set_data(sge: &sg_list[i + 1], sg);
955
956	return BLK_STS_OK;
957
958	out_unmap_sg:
959	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->meta_sgt, rq_dma_dir(req), attrs: 0);
960	out_free_sg:
961	mempool_free(element: iod->meta_sgt.sgl, pool: dev->iod_meta_mempool);
962	return BLK_STS_RESOURCE;
963	}
964
965	static blk_status_t nvme_pci_setup_meta_mptr(struct nvme_dev *dev,
966	struct request *req)
967	{
968	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
969	struct bio_vec bv = rq_integrity_vec(rq: req);
970	struct nvme_command *cmnd = &iod->cmd;
971
972	iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0);
973	if (dma_mapping_error(dev: dev->dev, dma_addr: iod->meta_dma))
974	return BLK_STS_IOERR;
975	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
976	return BLK_STS_OK;
977	}
978
979	static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req)
980	{
981	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
982
983	if ((iod->cmd.common.flags & NVME_CMD_SGL_METABUF) &&
984	nvme_pci_metadata_use_sgls(dev, req))
985	return nvme_pci_setup_meta_sgls(dev, req);
986	return nvme_pci_setup_meta_mptr(dev, req);
987	}
988
989	static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
990	{
991	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
992	blk_status_t ret;
993
994	iod->flags = 0;
995	iod->nr_descriptors = 0;
996	iod->sgt.nents = 0;
997	iod->meta_sgt.nents = 0;
998
999	ret = nvme_setup_cmd(ns: req->q->queuedata, req);
1000	if (ret)
1001	return ret;
1002
1003	if (blk_rq_nr_phys_segments(rq: req)) {
1004	ret = nvme_map_data(dev, req, cmnd: &iod->cmd);
1005	if (ret)
1006	goto out_free_cmd;
1007	}
1008
1009	if (blk_integrity_rq(rq: req)) {
1010	ret = nvme_map_metadata(dev, req);
1011	if (ret)
1012	goto out_unmap_data;
1013	}
1014
1015	nvme_start_request(rq: req);
1016	return BLK_STS_OK;
1017	out_unmap_data:
1018	if (blk_rq_nr_phys_segments(rq: req))
1019	nvme_unmap_data(dev, nvmeq: req->mq_hctx->driver_data, req);
1020	out_free_cmd:
1021	nvme_cleanup_cmd(req);
1022	return ret;
1023	}
1024
1025	static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
1026	const struct blk_mq_queue_data *bd)
1027	{
1028	struct nvme_queue *nvmeq = hctx->driver_data;
1029	struct nvme_dev *dev = nvmeq->dev;
1030	struct request *req = bd->rq;
1031	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
1032	blk_status_t ret;
1033
1034	/*
1035	* We should not need to do this, but we're still using this to
1036	* ensure we can drain requests on a dying queue.
1037	*/
1038	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
1039	return BLK_STS_IOERR;
1040
1041	if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
1042	return nvme_fail_nonready_command(ctrl: &dev->ctrl, req);
1043
1044	ret = nvme_prep_rq(dev, req);
1045	if (unlikely(ret))
1046	return ret;
1047	spin_lock(lock: &nvmeq->sq_lock);
1048	nvme_sq_copy_cmd(nvmeq, cmd: &iod->cmd);
1049	nvme_write_sq_db(nvmeq, write_sq: bd->last);
1050	spin_unlock(lock: &nvmeq->sq_lock);
1051	return BLK_STS_OK;
1052	}
1053
1054	static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct rq_list *rqlist)
1055	{
1056	struct request *req;
1057
1058	if (rq_list_empty(rl: rqlist))
1059	return;
1060
1061	spin_lock(lock: &nvmeq->sq_lock);
1062	while ((req = rq_list_pop(rl: rqlist))) {
1063	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
1064
1065	nvme_sq_copy_cmd(nvmeq, cmd: &iod->cmd);
1066	}
1067	nvme_write_sq_db(nvmeq, write_sq: true);
1068	spin_unlock(lock: &nvmeq->sq_lock);
1069	}
1070
1071	static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
1072	{
1073	/*
1074	* We should not need to do this, but we're still using this to
1075	* ensure we can drain requests on a dying queue.
1076	*/
1077	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
1078	return false;
1079	if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
1080	return false;
1081
1082	return nvme_prep_rq(dev: nvmeq->dev, req) == BLK_STS_OK;
1083	}
1084
1085	static void nvme_queue_rqs(struct rq_list *rqlist)
1086	{
1087	struct rq_list submit_list = { };
1088	struct rq_list requeue_list = { };
1089	struct nvme_queue *nvmeq = NULL;
1090	struct request *req;
1091
1092	while ((req = rq_list_pop(rl: rqlist))) {
1093	if (nvmeq && nvmeq != req->mq_hctx->driver_data)
1094	nvme_submit_cmds(nvmeq, rqlist: &submit_list);
1095	nvmeq = req->mq_hctx->driver_data;
1096
1097	if (nvme_prep_rq_batch(nvmeq, req))
1098	rq_list_add_tail(rl: &submit_list, rq: req);
1099	else
1100	rq_list_add_tail(rl: &requeue_list, rq: req);
1101	}
1102
1103	if (nvmeq)
1104	nvme_submit_cmds(nvmeq, rqlist: &submit_list);
1105	*rqlist = requeue_list;
1106	}
1107
1108	static __always_inline void nvme_unmap_metadata(struct nvme_dev *dev,
1109	struct nvme_queue *nvmeq,
1110	struct request *req)
1111	{
1112	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
1113
1114	if (!iod->meta_sgt.nents) {
1115	dma_unmap_page(dev->dev, iod->meta_dma,
1116	rq_integrity_vec(req).bv_len,
1117	rq_dma_dir(req));
1118	return;
1119	}
1120
1121	dma_pool_free(pool: nvmeq->descriptor_pools.small, vaddr: iod->meta_descriptor,
1122	addr: iod->meta_dma);
1123	dma_unmap_sgtable(dev: dev->dev, sgt: &iod->meta_sgt, rq_dma_dir(req), attrs: 0);
1124	mempool_free(element: iod->meta_sgt.sgl, pool: dev->iod_meta_mempool);
1125	}
1126
1127	static __always_inline void nvme_pci_unmap_rq(struct request *req)
1128	{
1129	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1130	struct nvme_dev *dev = nvmeq->dev;
1131
1132	if (blk_integrity_rq(rq: req))
1133	nvme_unmap_metadata(dev, nvmeq, req);
1134
1135	if (blk_rq_nr_phys_segments(rq: req))
1136	nvme_unmap_data(dev, nvmeq, req);
1137	}
1138
1139	static void nvme_pci_complete_rq(struct request *req)
1140	{
1141	nvme_pci_unmap_rq(req);
1142	nvme_complete_rq(req);
1143	}
1144
1145	static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1146	{
1147	nvme_complete_batch(iob, fn: nvme_pci_unmap_rq);
1148	}
1149
1150	/* We read the CQE phase first to check if the rest of the entry is valid */
1151	static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1152	{
1153	struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1154
1155	return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1156	}
1157
1158	static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1159	{
1160	u16 head = nvmeq->cq_head;
1161
1162	if (nvme_dbbuf_update_and_check_event(value: head, dbbuf_db: nvmeq->dbbuf_cq_db,
1163	dbbuf_ei: nvmeq->dbbuf_cq_ei))
1164	writel(val: head, addr: nvmeq->q_db + nvmeq->dev->db_stride);
1165	}
1166
1167	static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1168	{
1169	if (!nvmeq->qid)
1170	return nvmeq->dev->admin_tagset.tags[0];
1171	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1172	}
1173
1174	static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1175	struct io_comp_batch *iob, u16 idx)
1176	{
1177	struct nvme_completion *cqe = &nvmeq->cqes[idx];
1178	__u16 command_id = READ_ONCE(cqe->command_id);
1179	struct request *req;
1180
1181	/*
1182	* AEN requests are special as they don't time out and can
1183	* survive any kind of queue freeze and often don't respond to
1184	* aborts. We don't even bother to allocate a struct request
1185	* for them but rather special case them here.
1186	*/
1187	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1188	nvme_complete_async_event(ctrl: &nvmeq->dev->ctrl,
1189	status: cqe->status, res: &cqe->result);
1190	return;
1191	}
1192
1193	req = nvme_find_rq(tags: nvme_queue_tagset(nvmeq), command_id);
1194	if (unlikely(!req)) {
1195	dev_warn(nvmeq->dev->ctrl.device,
1196	"invalid id %d completed on queue %d\n",
1197	command_id, le16_to_cpu(cqe->sq_id));
1198	return;
1199	}
1200
1201	trace_nvme_sq(req, sq_head: cqe->sq_head, sq_tail: nvmeq->sq_tail);
1202	if (!nvme_try_complete_req(req, status: cqe->status, result: cqe->result) &&
1203	!blk_mq_add_to_batch(req, iob,
1204	is_error: nvme_req(req)->status != NVME_SC_SUCCESS,
1205	complete: nvme_pci_complete_batch))
1206	nvme_pci_complete_rq(req);
1207	}
1208
1209	static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1210	{
1211	u32 tmp = nvmeq->cq_head + 1;
1212
1213	if (tmp == nvmeq->q_depth) {
1214	nvmeq->cq_head = 0;
1215	nvmeq->cq_phase ^= 1;
1216	} else {
1217	nvmeq->cq_head = tmp;
1218	}
1219	}
1220
1221	static inline bool nvme_poll_cq(struct nvme_queue *nvmeq,
1222	struct io_comp_batch *iob)
1223	{
1224	bool found = false;
1225
1226	while (nvme_cqe_pending(nvmeq)) {
1227	found = true;
1228	/*
1229	* load-load control dependency between phase and the rest of
1230	* the cqe requires a full read memory barrier
1231	*/
1232	dma_rmb();
1233	nvme_handle_cqe(nvmeq, iob, idx: nvmeq->cq_head);
1234	nvme_update_cq_head(nvmeq);
1235	}
1236
1237	if (found)
1238	nvme_ring_cq_doorbell(nvmeq);
1239	return found;
1240	}
1241
1242	static irqreturn_t nvme_irq(int irq, void *data)
1243	{
1244	struct nvme_queue *nvmeq = data;
1245	DEFINE_IO_COMP_BATCH(iob);
1246
1247	if (nvme_poll_cq(nvmeq, iob: &iob)) {
1248	if (!rq_list_empty(rl: &iob.req_list))
1249	nvme_pci_complete_batch(iob: &iob);
1250	return IRQ_HANDLED;
1251	}
1252	return IRQ_NONE;
1253	}
1254
1255	static irqreturn_t nvme_irq_check(int irq, void *data)
1256	{
1257	struct nvme_queue *nvmeq = data;
1258
1259	if (nvme_cqe_pending(nvmeq))
1260	return IRQ_WAKE_THREAD;
1261	return IRQ_NONE;
1262	}
1263
1264	/*
1265	* Poll for completions for any interrupt driven queue
1266	* Can be called from any context.
1267	*/
1268	static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1269	{
1270	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1271
1272	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1273
1274	disable_irq(irq: pci_irq_vector(dev: pdev, nr: nvmeq->cq_vector));
1275	spin_lock(lock: &nvmeq->cq_poll_lock);
1276	nvme_poll_cq(nvmeq, NULL);
1277	spin_unlock(lock: &nvmeq->cq_poll_lock);
1278	enable_irq(irq: pci_irq_vector(dev: pdev, nr: nvmeq->cq_vector));
1279	}
1280
1281	static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1282	{
1283	struct nvme_queue *nvmeq = hctx->driver_data;
1284	bool found;
1285
1286	if (!nvme_cqe_pending(nvmeq))
1287	return 0;
1288
1289	spin_lock(lock: &nvmeq->cq_poll_lock);
1290	found = nvme_poll_cq(nvmeq, iob);
1291	spin_unlock(lock: &nvmeq->cq_poll_lock);
1292
1293	return found;
1294	}
1295
1296	static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1297	{
1298	struct nvme_dev *dev = to_nvme_dev(ctrl);
1299	struct nvme_queue *nvmeq = &dev->queues[0];
1300	struct nvme_command c = { };
1301
1302	c.common.opcode = nvme_admin_async_event;
1303	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1304
1305	spin_lock(lock: &nvmeq->sq_lock);
1306	nvme_sq_copy_cmd(nvmeq, cmd: &c);
1307	nvme_write_sq_db(nvmeq, write_sq: true);
1308	spin_unlock(lock: &nvmeq->sq_lock);
1309	}
1310
1311	static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl)
1312	{
1313	struct nvme_dev *dev = to_nvme_dev(ctrl);
1314	int ret = 0;
1315
1316	/*
1317	* Taking the shutdown_lock ensures the BAR mapping is not being
1318	* altered by reset_work. Holding this lock before the RESETTING state
1319	* change, if successful, also ensures nvme_remove won't be able to
1320	* proceed to iounmap until we're done.
1321	*/
1322	mutex_lock(&dev->shutdown_lock);
1323	if (!dev->bar_mapped_size) {
1324	ret = -ENODEV;
1325	goto unlock;
1326	}
1327
1328	if (!nvme_change_ctrl_state(ctrl, new_state: NVME_CTRL_RESETTING)) {
1329	ret = -EBUSY;
1330	goto unlock;
1331	}
1332
1333	writel(NVME_SUBSYS_RESET, addr: dev->bar + NVME_REG_NSSR);
1334	nvme_change_ctrl_state(ctrl, new_state: NVME_CTRL_LIVE);
1335
1336	/*
1337	* Read controller status to flush the previous write and trigger a
1338	* pcie read error.
1339	*/
1340	readl(addr: dev->bar + NVME_REG_CSTS);
1341	unlock:
1342	mutex_unlock(lock: &dev->shutdown_lock);
1343	return ret;
1344	}
1345
1346	static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1347	{
1348	struct nvme_command c = { };
1349
1350	c.delete_queue.opcode = opcode;
1351	c.delete_queue.qid = cpu_to_le16(id);
1352
1353	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1354	}
1355
1356	static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1357	struct nvme_queue *nvmeq, s16 vector)
1358	{
1359	struct nvme_command c = { };
1360	int flags = NVME_QUEUE_PHYS_CONTIG;
1361
1362	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1363	flags |= NVME_CQ_IRQ_ENABLED;
1364
1365	/*
1366	* Note: we (ab)use the fact that the prp fields survive if no data
1367	* is attached to the request.
1368	*/
1369	c.create_cq.opcode = nvme_admin_create_cq;
1370	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1371	c.create_cq.cqid = cpu_to_le16(qid);
1372	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1373	c.create_cq.cq_flags = cpu_to_le16(flags);
1374	c.create_cq.irq_vector = cpu_to_le16(vector);
1375
1376	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1377	}
1378
1379	static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1380	struct nvme_queue *nvmeq)
1381	{
1382	struct nvme_ctrl *ctrl = &dev->ctrl;
1383	struct nvme_command c = { };
1384	int flags = NVME_QUEUE_PHYS_CONTIG;
1385
1386	/*
1387	* Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1388	* set. Since URGENT priority is zeroes, it makes all queues
1389	* URGENT.
1390	*/
1391	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1392	flags |= NVME_SQ_PRIO_MEDIUM;
1393
1394	/*
1395	* Note: we (ab)use the fact that the prp fields survive if no data
1396	* is attached to the request.
1397	*/
1398	c.create_sq.opcode = nvme_admin_create_sq;
1399	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1400	c.create_sq.sqid = cpu_to_le16(qid);
1401	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1402	c.create_sq.sq_flags = cpu_to_le16(flags);
1403	c.create_sq.cqid = cpu_to_le16(qid);
1404
1405	return nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
1406	}
1407
1408	static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1409	{
1410	return adapter_delete_queue(dev, opcode: nvme_admin_delete_cq, id: cqid);
1411	}
1412
1413	static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1414	{
1415	return adapter_delete_queue(dev, opcode: nvme_admin_delete_sq, id: sqid);
1416	}
1417
1418	static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1419	{
1420	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1421
1422	dev_warn(nvmeq->dev->ctrl.device,
1423	"Abort status: 0x%x", nvme_req(req)->status);
1424	atomic_inc(v: &nvmeq->dev->ctrl.abort_limit);
1425	blk_mq_free_request(rq: req);
1426	return RQ_END_IO_NONE;
1427	}
1428
1429	static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1430	{
1431	/* If true, indicates loss of adapter communication, possibly by a
1432	* NVMe Subsystem reset.
1433	*/
1434	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1435
1436	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1437	switch (nvme_ctrl_state(ctrl: &dev->ctrl)) {
1438	case NVME_CTRL_RESETTING:
1439	case NVME_CTRL_CONNECTING:
1440	return false;
1441	default:
1442	break;
1443	}
1444
1445	/* We shouldn't reset unless the controller is on fatal error state
1446	* _or_ if we lost the communication with it.
1447	*/
1448	if (!(csts & NVME_CSTS_CFS) && !nssro)
1449	return false;
1450
1451	return true;
1452	}
1453
1454	static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1455	{
1456	/* Read a config register to help see what died. */
1457	u16 pci_status;
1458	int result;
1459
1460	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1461	val: &pci_status);
1462	if (result == PCIBIOS_SUCCESSFUL)
1463	dev_warn(dev->ctrl.device,
1464	"controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1465	csts, pci_status);
1466	else
1467	dev_warn(dev->ctrl.device,
1468	"controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1469	csts, result);
1470
1471	if (csts != ~0)
1472	return;
1473
1474	dev_warn(dev->ctrl.device,
1475	"Does your device have a faulty power saving mode enabled?\n");
1476	dev_warn(dev->ctrl.device,
1477	"Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n");
1478	}
1479
1480	static enum blk_eh_timer_return nvme_timeout(struct request *req)
1481	{
1482	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq: req);
1483	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1484	struct nvme_dev *dev = nvmeq->dev;
1485	struct request *abort_req;
1486	struct nvme_command cmd = { };
1487	struct pci_dev *pdev = to_pci_dev(dev->dev);
1488	u32 csts = readl(addr: dev->bar + NVME_REG_CSTS);
1489	u8 opcode;
1490
1491	/*
1492	* Shutdown the device immediately if we see it is disconnected. This
1493	* unblocks PCIe error handling if the nvme driver is waiting in
1494	* error_resume for a device that has been removed. We can't unbind the
1495	* driver while the driver's error callback is waiting to complete, so
1496	* we're relying on a timeout to break that deadlock if a removal
1497	* occurs while reset work is running.
1498	*/
1499	if (pci_dev_is_disconnected(dev: pdev))
1500	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
1501	if (nvme_state_terminal(ctrl: &dev->ctrl))
1502	goto disable;
1503
1504	/* If PCI error recovery process is happening, we cannot reset or
1505	* the recovery mechanism will surely fail.
1506	*/
1507	mb();
1508	if (pci_channel_offline(pdev))
1509	return BLK_EH_RESET_TIMER;
1510
1511	/*
1512	* Reset immediately if the controller is failed
1513	*/
1514	if (nvme_should_reset(dev, csts)) {
1515	nvme_warn_reset(dev, csts);
1516	goto disable;
1517	}
1518
1519	/*
1520	* Did we miss an interrupt?
1521	*/
1522	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1523	nvme_poll(hctx: req->mq_hctx, NULL);
1524	else
1525	nvme_poll_irqdisable(nvmeq);
1526
1527	if (blk_mq_rq_state(rq: req) != MQ_RQ_IN_FLIGHT) {
1528	dev_warn(dev->ctrl.device,
1529	"I/O tag %d (%04x) QID %d timeout, completion polled\n",
1530	req->tag, nvme_cid(req), nvmeq->qid);
1531	return BLK_EH_DONE;
1532	}
1533
1534	/*
1535	* Shutdown immediately if controller times out while starting. The
1536	* reset work will see the pci device disabled when it gets the forced
1537	* cancellation error. All outstanding requests are completed on
1538	* shutdown, so we return BLK_EH_DONE.
1539	*/
1540	switch (nvme_ctrl_state(ctrl: &dev->ctrl)) {
1541	case NVME_CTRL_CONNECTING:
1542	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
1543	fallthrough;
1544	case NVME_CTRL_DELETING:
1545	dev_warn_ratelimited(dev->ctrl.device,
1546	"I/O tag %d (%04x) QID %d timeout, disable controller\n",
1547	req->tag, nvme_cid(req), nvmeq->qid);
1548	nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1549	nvme_dev_disable(dev, shutdown: true);
1550	return BLK_EH_DONE;
1551	case NVME_CTRL_RESETTING:
1552	return BLK_EH_RESET_TIMER;
1553	default:
1554	break;
1555	}
1556
1557	/*
1558	* Shutdown the controller immediately and schedule a reset if the
1559	* command was already aborted once before and still hasn't been
1560	* returned to the driver, or if this is the admin queue.
1561	*/
1562	opcode = nvme_req(req)->cmd->common.opcode;
1563	if (!nvmeq->qid || (iod->flags & IOD_ABORTED)) {
1564	dev_warn(dev->ctrl.device,
1565	"I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1566	req->tag, nvme_cid(req), opcode,
1567	nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
1568	nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1569	goto disable;
1570	}
1571
1572	if (atomic_dec_return(v: &dev->ctrl.abort_limit) < 0) {
1573	atomic_inc(v: &dev->ctrl.abort_limit);
1574	return BLK_EH_RESET_TIMER;
1575	}
1576	iod->flags |= IOD_ABORTED;
1577
1578	cmd.abort.opcode = nvme_admin_abort_cmd;
1579	cmd.abort.cid = nvme_cid(rq: req);
1580	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1581
1582	dev_warn(nvmeq->dev->ctrl.device,
1583	"I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1584	req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1585	nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1586	blk_rq_bytes(req));
1587
1588	abort_req = blk_mq_alloc_request(q: dev->ctrl.admin_q, opf: nvme_req_op(cmd: &cmd),
1589	flags: BLK_MQ_REQ_NOWAIT);
1590	if (IS_ERR(ptr: abort_req)) {
1591	atomic_inc(v: &dev->ctrl.abort_limit);
1592	return BLK_EH_RESET_TIMER;
1593	}
1594	nvme_init_request(req: abort_req, cmd: &cmd);
1595
1596	abort_req->end_io = abort_endio;
1597	abort_req->end_io_data = NULL;
1598	blk_execute_rq_nowait(rq: abort_req, at_head: false);
1599
1600	/*
1601	* The aborted req will be completed on receiving the abort req.
1602	* We enable the timer again. If hit twice, it'll cause a device reset,
1603	* as the device then is in a faulty state.
1604	*/
1605	return BLK_EH_RESET_TIMER;
1606
1607	disable:
1608	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_RESETTING)) {
1609	if (nvme_state_terminal(ctrl: &dev->ctrl))
1610	nvme_dev_disable(dev, shutdown: true);
1611	return BLK_EH_DONE;
1612	}
1613
1614	nvme_dev_disable(dev, shutdown: false);
1615	if (nvme_try_sched_reset(ctrl: &dev->ctrl))
1616	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
1617	return BLK_EH_DONE;
1618	}
1619
1620	static void nvme_free_queue(struct nvme_queue *nvmeq)
1621	{
1622	dma_free_coherent(dev: nvmeq->dev->dev, CQ_SIZE(nvmeq),
1623	cpu_addr: (void *)nvmeq->cqes, dma_handle: nvmeq->cq_dma_addr);
1624	if (!nvmeq->sq_cmds)
1625	return;
1626
1627	if (test_and_clear_bit(NVMEQ_SQ_CMB, addr: &nvmeq->flags)) {
1628	pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1629	addr: nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1630	} else {
1631	dma_free_coherent(dev: nvmeq->dev->dev, SQ_SIZE(nvmeq),
1632	cpu_addr: nvmeq->sq_cmds, dma_handle: nvmeq->sq_dma_addr);
1633	}
1634	}
1635
1636	static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1637	{
1638	int i;
1639
1640	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1641	dev->ctrl.queue_count--;
1642	nvme_free_queue(nvmeq: &dev->queues[i]);
1643	}
1644	}
1645
1646	static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1647	{
1648	struct nvme_queue *nvmeq = &dev->queues[qid];
1649
1650	if (!test_and_clear_bit(NVMEQ_ENABLED, addr: &nvmeq->flags))
1651	return;
1652
1653	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1654	mb();
1655
1656	nvmeq->dev->online_queues--;
1657	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1658	nvme_quiesce_admin_queue(ctrl: &nvmeq->dev->ctrl);
1659	if (!test_and_clear_bit(NVMEQ_POLLED, addr: &nvmeq->flags))
1660	pci_free_irq(to_pci_dev(dev->dev), nr: nvmeq->cq_vector, dev_id: nvmeq);
1661	}
1662
1663	static void nvme_suspend_io_queues(struct nvme_dev *dev)
1664	{
1665	int i;
1666
1667	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1668	nvme_suspend_queue(dev, qid: i);
1669	}
1670
1671	/*
1672	* Called only on a device that has been disabled and after all other threads
1673	* that can check this device's completion queues have synced, except
1674	* nvme_poll(). This is the last chance for the driver to see a natural
1675	* completion before nvme_cancel_request() terminates all incomplete requests.
1676	*/
1677	static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1678	{
1679	int i;
1680
1681	for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1682	spin_lock(lock: &dev->queues[i].cq_poll_lock);
1683	nvme_poll_cq(nvmeq: &dev->queues[i], NULL);
1684	spin_unlock(lock: &dev->queues[i].cq_poll_lock);
1685	}
1686	}
1687
1688	static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1689	int entry_size)
1690	{
1691	int q_depth = dev->q_depth;
1692	unsigned q_size_aligned = roundup(q_depth * entry_size,
1693	NVME_CTRL_PAGE_SIZE);
1694
1695	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1696	u64 mem_per_q = div_u64(dividend: dev->cmb_size, divisor: nr_io_queues);
1697
1698	mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1699	q_depth = div_u64(dividend: mem_per_q, divisor: entry_size);
1700
1701	/*
1702	* Ensure the reduced q_depth is above some threshold where it
1703	* would be better to map queues in system memory with the
1704	* original depth
1705	*/
1706	if (q_depth < 64)
1707	return -ENOMEM;
1708	}
1709
1710	return q_depth;
1711	}
1712
1713	static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1714	int qid)
1715	{
1716	struct pci_dev *pdev = to_pci_dev(dev->dev);
1717
1718	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1719	nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1720	if (nvmeq->sq_cmds) {
1721	nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1722	addr: nvmeq->sq_cmds);
1723	if (nvmeq->sq_dma_addr) {
1724	set_bit(NVMEQ_SQ_CMB, addr: &nvmeq->flags);
1725	return 0;
1726	}
1727
1728	pci_free_p2pmem(pdev, addr: nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1729	}
1730	}
1731
1732	nvmeq->sq_cmds = dma_alloc_coherent(dev: dev->dev, SQ_SIZE(nvmeq),
1733	dma_handle: &nvmeq->sq_dma_addr, GFP_KERNEL);
1734	if (!nvmeq->sq_cmds)
1735	return -ENOMEM;
1736	return 0;
1737	}
1738
1739	static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1740	{
1741	struct nvme_queue *nvmeq = &dev->queues[qid];
1742
1743	if (dev->ctrl.queue_count > qid)
1744	return 0;
1745
1746	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1747	nvmeq->q_depth = depth;
1748	nvmeq->cqes = dma_alloc_coherent(dev: dev->dev, CQ_SIZE(nvmeq),
1749	dma_handle: &nvmeq->cq_dma_addr, GFP_KERNEL);
1750	if (!nvmeq->cqes)
1751	goto free_nvmeq;
1752
1753	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1754	goto free_cqdma;
1755
1756	nvmeq->dev = dev;
1757	spin_lock_init(&nvmeq->sq_lock);
1758	spin_lock_init(&nvmeq->cq_poll_lock);
1759	nvmeq->cq_head = 0;
1760	nvmeq->cq_phase = 1;
1761	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1762	nvmeq->qid = qid;
1763	dev->ctrl.queue_count++;
1764
1765	return 0;
1766
1767	free_cqdma:
1768	dma_free_coherent(dev: dev->dev, CQ_SIZE(nvmeq), cpu_addr: (void *)nvmeq->cqes,
1769	dma_handle: nvmeq->cq_dma_addr);
1770	free_nvmeq:
1771	return -ENOMEM;
1772	}
1773
1774	static int queue_request_irq(struct nvme_queue *nvmeq)
1775	{
1776	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1777	int nr = nvmeq->dev->ctrl.instance;
1778
1779	if (use_threaded_interrupts) {
1780	return pci_request_irq(dev: pdev, nr: nvmeq->cq_vector, handler: nvme_irq_check,
1781	thread_fn: nvme_irq, dev_id: nvmeq, fmt: "nvme%dq%d", nr, nvmeq->qid);
1782	} else {
1783	return pci_request_irq(dev: pdev, nr: nvmeq->cq_vector, handler: nvme_irq,
1784	NULL, dev_id: nvmeq, fmt: "nvme%dq%d", nr, nvmeq->qid);
1785	}
1786	}
1787
1788	static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1789	{
1790	struct nvme_dev *dev = nvmeq->dev;
1791
1792	nvmeq->sq_tail = 0;
1793	nvmeq->last_sq_tail = 0;
1794	nvmeq->cq_head = 0;
1795	nvmeq->cq_phase = 1;
1796	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1797	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1798	nvme_dbbuf_init(dev, nvmeq, qid);
1799	dev->online_queues++;
1800	wmb(); /* ensure the first interrupt sees the initialization */
1801	}
1802
1803	/*
1804	* Try getting shutdown_lock while setting up IO queues.
1805	*/
1806	static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1807	{
1808	/*
1809	* Give up if the lock is being held by nvme_dev_disable.
1810	*/
1811	if (!mutex_trylock(&dev->shutdown_lock))
1812	return -ENODEV;
1813
1814	/*
1815	* Controller is in wrong state, fail early.
1816	*/
1817	if (nvme_ctrl_state(ctrl: &dev->ctrl) != NVME_CTRL_CONNECTING) {
1818	mutex_unlock(lock: &dev->shutdown_lock);
1819	return -ENODEV;
1820	}
1821
1822	return 0;
1823	}
1824
1825	static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1826	{
1827	struct nvme_dev *dev = nvmeq->dev;
1828	int result;
1829	u16 vector = 0;
1830
1831	clear_bit(NVMEQ_DELETE_ERROR, addr: &nvmeq->flags);
1832
1833	/*
1834	* A queue's vector matches the queue identifier unless the controller
1835	* has only one vector available.
1836	*/
1837	if (!polled)
1838	vector = dev->num_vecs == 1 ? 0 : qid;
1839	else
1840	set_bit(NVMEQ_POLLED, addr: &nvmeq->flags);
1841
1842	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1843	if (result)
1844	return result;
1845
1846	result = adapter_alloc_sq(dev, qid, nvmeq);
1847	if (result < 0)
1848	return result;
1849	if (result)
1850	goto release_cq;
1851
1852	nvmeq->cq_vector = vector;
1853
1854	result = nvme_setup_io_queues_trylock(dev);
1855	if (result)
1856	return result;
1857	nvme_init_queue(nvmeq, qid);
1858	if (!polled) {
1859	result = queue_request_irq(nvmeq);
1860	if (result < 0)
1861	goto release_sq;
1862	}
1863
1864	set_bit(NVMEQ_ENABLED, addr: &nvmeq->flags);
1865	mutex_unlock(lock: &dev->shutdown_lock);
1866	return result;
1867
1868	release_sq:
1869	dev->online_queues--;
1870	mutex_unlock(lock: &dev->shutdown_lock);
1871	adapter_delete_sq(dev, sqid: qid);
1872	release_cq:
1873	adapter_delete_cq(dev, cqid: qid);
1874	return result;
1875	}
1876
1877	static const struct blk_mq_ops nvme_mq_admin_ops = {
1878	.queue_rq = nvme_queue_rq,
1879	.complete = nvme_pci_complete_rq,
1880	.init_hctx = nvme_admin_init_hctx,
1881	.init_request = nvme_pci_init_request,
1882	.timeout = nvme_timeout,
1883	};
1884
1885	static const struct blk_mq_ops nvme_mq_ops = {
1886	.queue_rq = nvme_queue_rq,
1887	.queue_rqs = nvme_queue_rqs,
1888	.complete = nvme_pci_complete_rq,
1889	.commit_rqs = nvme_commit_rqs,
1890	.init_hctx = nvme_init_hctx,
1891	.init_request = nvme_pci_init_request,
1892	.map_queues = nvme_pci_map_queues,
1893	.timeout = nvme_timeout,
1894	.poll = nvme_poll,
1895	};
1896
1897	static void nvme_dev_remove_admin(struct nvme_dev *dev)
1898	{
1899	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1900	/*
1901	* If the controller was reset during removal, it's possible
1902	* user requests may be waiting on a stopped queue. Start the
1903	* queue to flush these to completion.
1904	*/
1905	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
1906	nvme_remove_admin_tag_set(ctrl: &dev->ctrl);
1907	}
1908	}
1909
1910	static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1911	{
1912	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1913	}
1914
1915	static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1916	{
1917	struct pci_dev *pdev = to_pci_dev(dev->dev);
1918
1919	if (size <= dev->bar_mapped_size)
1920	return 0;
1921	if (size > pci_resource_len(pdev, 0))
1922	return -ENOMEM;
1923	if (dev->bar)
1924	iounmap(addr: dev->bar);
1925	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1926	if (!dev->bar) {
1927	dev->bar_mapped_size = 0;
1928	return -ENOMEM;
1929	}
1930	dev->bar_mapped_size = size;
1931	dev->dbs = dev->bar + NVME_REG_DBS;
1932
1933	return 0;
1934	}
1935
1936	static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1937	{
1938	int result;
1939	u32 aqa;
1940	struct nvme_queue *nvmeq;
1941
1942	result = nvme_remap_bar(dev, size: db_bar_size(dev, nr_io_queues: 0));
1943	if (result < 0)
1944	return result;
1945
1946	dev->subsystem = readl(addr: dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1947	NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1948
1949	if (dev->subsystem &&
1950	(readl(addr: dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1951	writel(val: NVME_CSTS_NSSRO, addr: dev->bar + NVME_REG_CSTS);
1952
1953	/*
1954	* If the device has been passed off to us in an enabled state, just
1955	* clear the enabled bit. The spec says we should set the 'shutdown
1956	* notification bits', but doing so may cause the device to complete
1957	* commands to the admin queue ... and we don't know what memory that
1958	* might be pointing at!
1959	*/
1960	result = nvme_disable_ctrl(ctrl: &dev->ctrl, shutdown: false);
1961	if (result < 0)
1962	return result;
1963
1964	result = nvme_alloc_queue(dev, qid: 0, NVME_AQ_DEPTH);
1965	if (result)
1966	return result;
1967
1968	dev->ctrl.numa_node = dev_to_node(dev: dev->dev);
1969
1970	nvmeq = &dev->queues[0];
1971	aqa = nvmeq->q_depth - 1;
1972	aqa |= aqa << 16;
1973
1974	writel(val: aqa, addr: dev->bar + NVME_REG_AQA);
1975	lo_hi_writeq(val: nvmeq->sq_dma_addr, addr: dev->bar + NVME_REG_ASQ);
1976	lo_hi_writeq(val: nvmeq->cq_dma_addr, addr: dev->bar + NVME_REG_ACQ);
1977
1978	result = nvme_enable_ctrl(ctrl: &dev->ctrl);
1979	if (result)
1980	return result;
1981
1982	nvmeq->cq_vector = 0;
1983	nvme_init_queue(nvmeq, qid: 0);
1984	result = queue_request_irq(nvmeq);
1985	if (result) {
1986	dev->online_queues--;
1987	return result;
1988	}
1989
1990	set_bit(NVMEQ_ENABLED, addr: &nvmeq->flags);
1991	return result;
1992	}
1993
1994	static int nvme_create_io_queues(struct nvme_dev *dev)
1995	{
1996	unsigned i, max, rw_queues;
1997	int ret = 0;
1998
1999	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
2000	if (nvme_alloc_queue(dev, qid: i, depth: dev->q_depth)) {
2001	ret = -ENOMEM;
2002	break;
2003	}
2004	}
2005
2006	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
2007	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
2008	rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
2009	dev->io_queues[HCTX_TYPE_READ];
2010	} else {
2011	rw_queues = max;
2012	}
2013
2014	for (i = dev->online_queues; i <= max; i++) {
2015	bool polled = i > rw_queues;
2016
2017	ret = nvme_create_queue(nvmeq: &dev->queues[i], qid: i, polled);
2018	if (ret)
2019	break;
2020	}
2021
2022	/*
2023	* Ignore failing Create SQ/CQ commands, we can continue with less
2024	* than the desired amount of queues, and even a controller without
2025	* I/O queues can still be used to issue admin commands. This might
2026	* be useful to upgrade a buggy firmware for example.
2027	*/
2028	return ret >= 0 ? 0 : ret;
2029	}
2030
2031	static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
2032	{
2033	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
2034
2035	return 1ULL << (12 + 4 * szu);
2036	}
2037
2038	static u32 nvme_cmb_size(struct nvme_dev *dev)
2039	{
2040	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
2041	}
2042
2043	static void nvme_map_cmb(struct nvme_dev *dev)
2044	{
2045	u64 size, offset;
2046	resource_size_t bar_size;
2047	struct pci_dev *pdev = to_pci_dev(dev->dev);
2048	int bar;
2049
2050	if (dev->cmb_size)
2051	return;
2052
2053	if (NVME_CAP_CMBS(dev->ctrl.cap))
2054	writel(val: NVME_CMBMSC_CRE, addr: dev->bar + NVME_REG_CMBMSC);
2055
2056	dev->cmbsz = readl(addr: dev->bar + NVME_REG_CMBSZ);
2057	if (!dev->cmbsz)
2058	return;
2059	dev->cmbloc = readl(addr: dev->bar + NVME_REG_CMBLOC);
2060
2061	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
2062	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
2063	bar = NVME_CMB_BIR(dev->cmbloc);
2064	bar_size = pci_resource_len(pdev, bar);
2065
2066	if (offset > bar_size)
2067	return;
2068
2069	/*
2070	* Controllers may support a CMB size larger than their BAR, for
2071	* example, due to being behind a bridge. Reduce the CMB to the
2072	* reported size of the BAR
2073	*/
2074	size = min(size, bar_size - offset);
2075
2076	if (!IS_ALIGNED(size, memremap_compat_align()) ||
2077	!IS_ALIGNED(pci_resource_start(pdev, bar),
2078	memremap_compat_align()))
2079	return;
2080
2081	/*
2082	* Tell the controller about the host side address mapping the CMB,
2083	* and enable CMB decoding for the NVMe 1.4+ scheme:
2084	*/
2085	if (NVME_CAP_CMBS(dev->ctrl.cap)) {
2086	hi_lo_writeq(val: NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
2087	(pci_bus_address(pdev, bar) + offset),
2088	addr: dev->bar + NVME_REG_CMBMSC);
2089	}
2090
2091	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
2092	dev_warn(dev->ctrl.device,
2093	"failed to register the CMB\n");
2094	hi_lo_writeq(val: 0, addr: dev->bar + NVME_REG_CMBMSC);
2095	return;
2096	}
2097
2098	dev->cmb_size = size;
2099	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
2100
2101	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
2102	(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
2103	pci_p2pmem_publish(pdev, publish: true);
2104
2105	nvme_update_attrs(dev);
2106	}
2107
2108	static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
2109	{
2110	u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
2111	u64 dma_addr = dev->host_mem_descs_dma;
2112	struct nvme_command c = { };
2113	int ret;
2114
2115	c.features.opcode = nvme_admin_set_features;
2116	c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
2117	c.features.dword11 = cpu_to_le32(bits);
2118	c.features.dword12 = cpu_to_le32(host_mem_size);
2119	c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
2120	c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
2121	c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
2122
2123	ret = nvme_submit_sync_cmd(q: dev->ctrl.admin_q, cmd: &c, NULL, bufflen: 0);
2124	if (ret) {
2125	dev_warn(dev->ctrl.device,
2126	"failed to set host mem (err %d, flags %#x).\n",
2127	ret, bits);
2128	} else
2129	dev->hmb = bits & NVME_HOST_MEM_ENABLE;
2130
2131	return ret;
2132	}
2133
2134	static void nvme_free_host_mem_multi(struct nvme_dev *dev)
2135	{
2136	int i;
2137
2138	for (i = 0; i < dev->nr_host_mem_descs; i++) {
2139	struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2140	size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2141
2142	dma_free_attrs(dev: dev->dev, size, cpu_addr: dev->host_mem_desc_bufs[i],
2143	le64_to_cpu(desc->addr),
2144	DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2145	}
2146
2147	kfree(objp: dev->host_mem_desc_bufs);
2148	dev->host_mem_desc_bufs = NULL;
2149	}
2150
2151	static void nvme_free_host_mem(struct nvme_dev *dev)
2152	{
2153	if (dev->hmb_sgt)
2154	dma_free_noncontiguous(dev: dev->dev, size: dev->host_mem_size,
2155	sgt: dev->hmb_sgt, dir: DMA_BIDIRECTIONAL);
2156	else
2157	nvme_free_host_mem_multi(dev);
2158
2159	dma_free_coherent(dev: dev->dev, size: dev->host_mem_descs_size,
2160	cpu_addr: dev->host_mem_descs, dma_handle: dev->host_mem_descs_dma);
2161	dev->host_mem_descs = NULL;
2162	dev->host_mem_descs_size = 0;
2163	dev->nr_host_mem_descs = 0;
2164	}
2165
2166	static int nvme_alloc_host_mem_single(struct nvme_dev *dev, u64 size)
2167	{
2168	dev->hmb_sgt = dma_alloc_noncontiguous(dev: dev->dev, size,
2169	dir: DMA_BIDIRECTIONAL, GFP_KERNEL, attrs: 0);
2170	if (!dev->hmb_sgt)
2171	return -ENOMEM;
2172
2173	dev->host_mem_descs = dma_alloc_coherent(dev: dev->dev,
2174	size: sizeof(*dev->host_mem_descs), dma_handle: &dev->host_mem_descs_dma,
2175	GFP_KERNEL);
2176	if (!dev->host_mem_descs) {
2177	dma_free_noncontiguous(dev: dev->dev, size, sgt: dev->hmb_sgt,
2178	dir: DMA_BIDIRECTIONAL);
2179	dev->hmb_sgt = NULL;
2180	return -ENOMEM;
2181	}
2182	dev->host_mem_size = size;
2183	dev->host_mem_descs_size = sizeof(*dev->host_mem_descs);
2184	dev->nr_host_mem_descs = 1;
2185
2186	dev->host_mem_descs[0].addr =
2187	cpu_to_le64(dev->hmb_sgt->sgl->dma_address);
2188	dev->host_mem_descs[0].size = cpu_to_le32(size / NVME_CTRL_PAGE_SIZE);
2189	return 0;
2190	}
2191
2192	static int nvme_alloc_host_mem_multi(struct nvme_dev *dev, u64 preferred,
2193	u32 chunk_size)
2194	{
2195	struct nvme_host_mem_buf_desc *descs;
2196	u32 max_entries, len, descs_size;
2197	dma_addr_t descs_dma;
2198	int i = 0;
2199	void **bufs;
2200	u64 size, tmp;
2201
2202	tmp = (preferred + chunk_size - 1);
2203	do_div(tmp, chunk_size);
2204	max_entries = tmp;
2205
2206	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2207	max_entries = dev->ctrl.hmmaxd;
2208
2209	descs_size = max_entries * sizeof(*descs);
2210	descs = dma_alloc_coherent(dev: dev->dev, size: descs_size, dma_handle: &descs_dma,
2211	GFP_KERNEL);
2212	if (!descs)
2213	goto out;
2214
2215	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2216	if (!bufs)
2217	goto out_free_descs;
2218
2219	for (size = 0; size < preferred && i < max_entries; size += len) {
2220	dma_addr_t dma_addr;
2221
2222	len = min_t(u64, chunk_size, preferred - size);
2223	bufs[i] = dma_alloc_attrs(dev: dev->dev, size: len, dma_handle: &dma_addr, GFP_KERNEL,
2224	DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2225	if (!bufs[i])
2226	break;
2227
2228	descs[i].addr = cpu_to_le64(dma_addr);
2229	descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2230	i++;
2231	}
2232
2233	if (!size)
2234	goto out_free_bufs;
2235
2236	dev->nr_host_mem_descs = i;
2237	dev->host_mem_size = size;
2238	dev->host_mem_descs = descs;
2239	dev->host_mem_descs_dma = descs_dma;
2240	dev->host_mem_descs_size = descs_size;
2241	dev->host_mem_desc_bufs = bufs;
2242	return 0;
2243
2244	out_free_bufs:
2245	kfree(objp: bufs);
2246	out_free_descs:
2247	dma_free_coherent(dev: dev->dev, size: descs_size, cpu_addr: descs, dma_handle: descs_dma);
2248	out:
2249	dev->host_mem_descs = NULL;
2250	return -ENOMEM;
2251	}
2252
2253	static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2254	{
2255	unsigned long dma_merge_boundary = dma_get_merge_boundary(dev: dev->dev);
2256	u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2257	u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2258	u64 chunk_size;
2259
2260	/*
2261	* If there is an IOMMU that can merge pages, try a virtually
2262	* non-contiguous allocation for a single segment first.
2263	*/
2264	if (dma_merge_boundary && (PAGE_SIZE & dma_merge_boundary) == 0) {
2265	if (!nvme_alloc_host_mem_single(dev, size: preferred))
2266	return 0;
2267	}
2268
2269	/* start big and work our way down */
2270	for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2271	if (!nvme_alloc_host_mem_multi(dev, preferred, chunk_size)) {
2272	if (!min || dev->host_mem_size >= min)
2273	return 0;
2274	nvme_free_host_mem(dev);
2275	}
2276	}
2277
2278	return -ENOMEM;
2279	}
2280
2281	static int nvme_setup_host_mem(struct nvme_dev *dev)
2282	{
2283	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2284	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2285	u64 min = (u64)dev->ctrl.hmmin * 4096;
2286	u32 enable_bits = NVME_HOST_MEM_ENABLE;
2287	int ret;
2288
2289	if (!dev->ctrl.hmpre)
2290	return 0;
2291
2292	preferred = min(preferred, max);
2293	if (min > max) {
2294	dev_warn(dev->ctrl.device,
2295	"min host memory (%lld MiB) above limit (%d MiB).\n",
2296	min >> ilog2(SZ_1M), max_host_mem_size_mb);
2297	nvme_free_host_mem(dev);
2298	return 0;
2299	}
2300
2301	/*
2302	* If we already have a buffer allocated check if we can reuse it.
2303	*/
2304	if (dev->host_mem_descs) {
2305	if (dev->host_mem_size >= min)
2306	enable_bits |= NVME_HOST_MEM_RETURN;
2307	else
2308	nvme_free_host_mem(dev);
2309	}
2310
2311	if (!dev->host_mem_descs) {
2312	if (nvme_alloc_host_mem(dev, min, preferred)) {
2313	dev_warn(dev->ctrl.device,
2314	"failed to allocate host memory buffer.\n");
2315	return 0; /* controller must work without HMB */
2316	}
2317
2318	dev_info(dev->ctrl.device,
2319	"allocated %lld MiB host memory buffer (%u segment%s).\n",
2320	dev->host_mem_size >> ilog2(SZ_1M),
2321	dev->nr_host_mem_descs,
2322	str_plural(dev->nr_host_mem_descs));
2323	}
2324
2325	ret = nvme_set_host_mem(dev, bits: enable_bits);
2326	if (ret)
2327	nvme_free_host_mem(dev);
2328	return ret;
2329	}
2330
2331	static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2332	char *buf)
2333	{
2334	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2335
2336	return sysfs_emit(buf, fmt: "cmbloc : x%08x\ncmbsz : x%08x\n",
2337	ndev->cmbloc, ndev->cmbsz);
2338	}
2339	static DEVICE_ATTR_RO(cmb);
2340
2341	static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2342	char *buf)
2343	{
2344	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2345
2346	return sysfs_emit(buf, fmt: "%u\n", ndev->cmbloc);
2347	}
2348	static DEVICE_ATTR_RO(cmbloc);
2349
2350	static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2351	char *buf)
2352	{
2353	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2354
2355	return sysfs_emit(buf, fmt: "%u\n", ndev->cmbsz);
2356	}
2357	static DEVICE_ATTR_RO(cmbsz);
2358
2359	static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2360	char *buf)
2361	{
2362	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2363
2364	return sysfs_emit(buf, fmt: "%d\n", ndev->hmb);
2365	}
2366
2367	static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2368	const char *buf, size_t count)
2369	{
2370	struct nvme_dev *ndev = to_nvme_dev(ctrl: dev_get_drvdata(dev));
2371	bool new;
2372	int ret;
2373
2374	if (kstrtobool(s: buf, res: &new) < 0)
2375	return -EINVAL;
2376
2377	if (new == ndev->hmb)
2378	return count;
2379
2380	if (new) {
2381	ret = nvme_setup_host_mem(dev: ndev);
2382	} else {
2383	ret = nvme_set_host_mem(dev: ndev, bits: 0);
2384	if (!ret)
2385	nvme_free_host_mem(dev: ndev);
2386	}
2387
2388	if (ret < 0)
2389	return ret;
2390
2391	return count;
2392	}
2393	static DEVICE_ATTR_RW(hmb);
2394
2395	static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2396	struct attribute *a, int n)
2397	{
2398	struct nvme_ctrl *ctrl =
2399	dev_get_drvdata(container_of(kobj, struct device, kobj));
2400	struct nvme_dev *dev = to_nvme_dev(ctrl);
2401
2402	if (a == &dev_attr_cmb.attr ||
2403	a == &dev_attr_cmbloc.attr ||
2404	a == &dev_attr_cmbsz.attr) {
2405	if (!dev->cmbsz)
2406	return 0;
2407	}
2408	if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2409	return 0;
2410
2411	return a->mode;
2412	}
2413
2414	static struct attribute *nvme_pci_attrs[] = {
2415	&dev_attr_cmb.attr,
2416	&dev_attr_cmbloc.attr,
2417	&dev_attr_cmbsz.attr,
2418	&dev_attr_hmb.attr,
2419	NULL,
2420	};
2421
2422	static const struct attribute_group nvme_pci_dev_attrs_group = {
2423	.attrs = nvme_pci_attrs,
2424	.is_visible = nvme_pci_attrs_are_visible,
2425	};
2426
2427	static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2428	&nvme_dev_attrs_group,
2429	&nvme_pci_dev_attrs_group,
2430	NULL,
2431	};
2432
2433	static void nvme_update_attrs(struct nvme_dev *dev)
2434	{
2435	sysfs_update_group(kobj: &dev->ctrl.device->kobj, grp: &nvme_pci_dev_attrs_group);
2436	}
2437
2438	/*
2439	* nirqs is the number of interrupts available for write and read
2440	* queues. The core already reserved an interrupt for the admin queue.
2441	*/
2442	static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2443	{
2444	struct nvme_dev *dev = affd->priv;
2445	unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2446
2447	/*
2448	* If there is no interrupt available for queues, ensure that
2449	* the default queue is set to 1. The affinity set size is
2450	* also set to one, but the irq core ignores it for this case.
2451	*
2452	* If only one interrupt is available or 'write_queue' == 0, combine
2453	* write and read queues.
2454	*
2455	* If 'write_queues' > 0, ensure it leaves room for at least one read
2456	* queue.
2457	*/
2458	if (!nrirqs) {
2459	nrirqs = 1;
2460	nr_read_queues = 0;
2461	} else if (nrirqs == 1 || !nr_write_queues) {
2462	nr_read_queues = 0;
2463	} else if (nr_write_queues >= nrirqs) {
2464	nr_read_queues = 1;
2465	} else {
2466	nr_read_queues = nrirqs - nr_write_queues;
2467	}
2468
2469	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2470	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2471	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2472	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2473	affd->nr_sets = nr_read_queues ? 2 : 1;
2474	}
2475
2476	static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2477	{
2478	struct pci_dev *pdev = to_pci_dev(dev->dev);
2479	struct irq_affinity affd = {
2480	.pre_vectors = 1,
2481	.calc_sets = nvme_calc_irq_sets,
2482	.priv = dev,
2483	};
2484	unsigned int irq_queues, poll_queues;
2485	unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2486
2487	/*
2488	* Poll queues don't need interrupts, but we need at least one I/O queue
2489	* left over for non-polled I/O.
2490	*/
2491	poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2492	dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2493
2494	/*
2495	* Initialize for the single interrupt case, will be updated in
2496	* nvme_calc_irq_sets().
2497	*/
2498	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2499	dev->io_queues[HCTX_TYPE_READ] = 0;
2500
2501	/*
2502	* We need interrupts for the admin queue and each non-polled I/O queue,
2503	* but some Apple controllers require all queues to use the first
2504	* vector.
2505	*/
2506	irq_queues = 1;
2507	if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2508	irq_queues += (nr_io_queues - poll_queues);
2509	if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2510	flags &= ~PCI_IRQ_MSI;
2511	return pci_alloc_irq_vectors_affinity(dev: pdev, min_vecs: 1, max_vecs: irq_queues, flags,
2512	affd: &affd);
2513	}
2514
2515	static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2516	{
2517	/*
2518	* If tags are shared with admin queue (Apple bug), then
2519	* make sure we only use one IO queue.
2520	*/
2521	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2522	return 1;
2523	return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2524	}
2525
2526	static int nvme_setup_io_queues(struct nvme_dev *dev)
2527	{
2528	struct nvme_queue *adminq = &dev->queues[0];
2529	struct pci_dev *pdev = to_pci_dev(dev->dev);
2530	unsigned int nr_io_queues;
2531	unsigned long size;
2532	int result;
2533
2534	/*
2535	* Sample the module parameters once at reset time so that we have
2536	* stable values to work with.
2537	*/
2538	dev->nr_write_queues = write_queues;
2539	dev->nr_poll_queues = poll_queues;
2540
2541	nr_io_queues = dev->nr_allocated_queues - 1;
2542	result = nvme_set_queue_count(ctrl: &dev->ctrl, count: &nr_io_queues);
2543	if (result < 0)
2544	return result;
2545
2546	if (nr_io_queues == 0)
2547	return 0;
2548
2549	/*
2550	* Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2551	* from set to unset. If there is a window to it is truely freed,
2552	* pci_free_irq_vectors() jumping into this window will crash.
2553	* And take lock to avoid racing with pci_free_irq_vectors() in
2554	* nvme_dev_disable() path.
2555	*/
2556	result = nvme_setup_io_queues_trylock(dev);
2557	if (result)
2558	return result;
2559	if (test_and_clear_bit(NVMEQ_ENABLED, addr: &adminq->flags))
2560	pci_free_irq(dev: pdev, nr: 0, dev_id: adminq);
2561
2562	if (dev->cmb_use_sqes) {
2563	result = nvme_cmb_qdepth(dev, nr_io_queues,
2564	entry_size: sizeof(struct nvme_command));
2565	if (result > 0) {
2566	dev->q_depth = result;
2567	dev->ctrl.sqsize = result - 1;
2568	} else {
2569	dev->cmb_use_sqes = false;
2570	}
2571	}
2572
2573	do {
2574	size = db_bar_size(dev, nr_io_queues);
2575	result = nvme_remap_bar(dev, size);
2576	if (!result)
2577	break;
2578	if (!--nr_io_queues) {
2579	result = -ENOMEM;
2580	goto out_unlock;
2581	}
2582	} while (1);
2583	adminq->q_db = dev->dbs;
2584
2585	retry:
2586	/* Deregister the admin queue's interrupt */
2587	if (test_and_clear_bit(NVMEQ_ENABLED, addr: &adminq->flags))
2588	pci_free_irq(dev: pdev, nr: 0, dev_id: adminq);
2589
2590	/*
2591	* If we enable msix early due to not intx, disable it again before
2592	* setting up the full range we need.
2593	*/
2594	pci_free_irq_vectors(dev: pdev);
2595
2596	result = nvme_setup_irqs(dev, nr_io_queues);
2597	if (result <= 0) {
2598	result = -EIO;
2599	goto out_unlock;
2600	}
2601
2602	dev->num_vecs = result;
2603	result = max(result - 1, 1);
2604	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2605
2606	/*
2607	* Should investigate if there's a performance win from allocating
2608	* more queues than interrupt vectors; it might allow the submission
2609	* path to scale better, even if the receive path is limited by the
2610	* number of interrupts.
2611	*/
2612	result = queue_request_irq(nvmeq: adminq);
2613	if (result)
2614	goto out_unlock;
2615	set_bit(NVMEQ_ENABLED, addr: &adminq->flags);
2616	mutex_unlock(lock: &dev->shutdown_lock);
2617
2618	result = nvme_create_io_queues(dev);
2619	if (result || dev->online_queues < 2)
2620	return result;
2621
2622	if (dev->online_queues - 1 < dev->max_qid) {
2623	nr_io_queues = dev->online_queues - 1;
2624	nvme_delete_io_queues(dev);
2625	result = nvme_setup_io_queues_trylock(dev);
2626	if (result)
2627	return result;
2628	nvme_suspend_io_queues(dev);
2629	goto retry;
2630	}
2631	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2632	dev->io_queues[HCTX_TYPE_DEFAULT],
2633	dev->io_queues[HCTX_TYPE_READ],
2634	dev->io_queues[HCTX_TYPE_POLL]);
2635	return 0;
2636	out_unlock:
2637	mutex_unlock(lock: &dev->shutdown_lock);
2638	return result;
2639	}
2640
2641	static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2642	blk_status_t error)
2643	{
2644	struct nvme_queue *nvmeq = req->end_io_data;
2645
2646	blk_mq_free_request(rq: req);
2647	complete(&nvmeq->delete_done);
2648	return RQ_END_IO_NONE;
2649	}
2650
2651	static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2652	blk_status_t error)
2653	{
2654	struct nvme_queue *nvmeq = req->end_io_data;
2655
2656	if (error)
2657	set_bit(NVMEQ_DELETE_ERROR, addr: &nvmeq->flags);
2658
2659	return nvme_del_queue_end(req, error);
2660	}
2661
2662	static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2663	{
2664	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2665	struct request *req;
2666	struct nvme_command cmd = { };
2667
2668	cmd.delete_queue.opcode = opcode;
2669	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2670
2671	req = blk_mq_alloc_request(q, opf: nvme_req_op(cmd: &cmd), flags: BLK_MQ_REQ_NOWAIT);
2672	if (IS_ERR(ptr: req))
2673	return PTR_ERR(ptr: req);
2674	nvme_init_request(req, cmd: &cmd);
2675
2676	if (opcode == nvme_admin_delete_cq)
2677	req->end_io = nvme_del_cq_end;
2678	else
2679	req->end_io = nvme_del_queue_end;
2680	req->end_io_data = nvmeq;
2681
2682	init_completion(x: &nvmeq->delete_done);
2683	blk_execute_rq_nowait(rq: req, at_head: false);
2684	return 0;
2685	}
2686
2687	static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2688	{
2689	int nr_queues = dev->online_queues - 1, sent = 0;
2690	unsigned long timeout;
2691
2692	retry:
2693	timeout = NVME_ADMIN_TIMEOUT;
2694	while (nr_queues > 0) {
2695	if (nvme_delete_queue(nvmeq: &dev->queues[nr_queues], opcode))
2696	break;
2697	nr_queues--;
2698	sent++;
2699	}
2700	while (sent) {
2701	struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2702
2703	timeout = wait_for_completion_io_timeout(x: &nvmeq->delete_done,
2704	timeout);
2705	if (timeout == 0)
2706	return false;
2707
2708	sent--;
2709	if (nr_queues)
2710	goto retry;
2711	}
2712	return true;
2713	}
2714
2715	static void nvme_delete_io_queues(struct nvme_dev *dev)
2716	{
2717	if (__nvme_delete_io_queues(dev, opcode: nvme_admin_delete_sq))
2718	__nvme_delete_io_queues(dev, opcode: nvme_admin_delete_cq);
2719	}
2720
2721	static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2722	{
2723	if (dev->io_queues[HCTX_TYPE_POLL])
2724	return 3;
2725	if (dev->io_queues[HCTX_TYPE_READ])
2726	return 2;
2727	return 1;
2728	}
2729
2730	static bool nvme_pci_update_nr_queues(struct nvme_dev *dev)
2731	{
2732	if (!dev->ctrl.tagset) {
2733	nvme_alloc_io_tag_set(ctrl: &dev->ctrl, set: &dev->tagset, ops: &nvme_mq_ops,
2734	nr_maps: nvme_pci_nr_maps(dev), cmd_size: sizeof(struct nvme_iod));
2735	return true;
2736	}
2737
2738	/* Give up if we are racing with nvme_dev_disable() */
2739	if (!mutex_trylock(&dev->shutdown_lock))
2740	return false;
2741
2742	/* Check if nvme_dev_disable() has been executed already */
2743	if (!dev->online_queues) {
2744	mutex_unlock(lock: &dev->shutdown_lock);
2745	return false;
2746	}
2747
2748	blk_mq_update_nr_hw_queues(set: &dev->tagset, nr_hw_queues: dev->online_queues - 1);
2749	/* free previously allocated queues that are no longer usable */
2750	nvme_free_queues(dev, lowest: dev->online_queues);
2751	mutex_unlock(lock: &dev->shutdown_lock);
2752	return true;
2753	}
2754
2755	static int nvme_pci_enable(struct nvme_dev *dev)
2756	{
2757	int result = -ENOMEM;
2758	struct pci_dev *pdev = to_pci_dev(dev->dev);
2759	unsigned int flags = PCI_IRQ_ALL_TYPES;
2760
2761	if (pci_enable_device_mem(dev: pdev))
2762	return result;
2763
2764	pci_set_master(dev: pdev);
2765
2766	if (readl(addr: dev->bar + NVME_REG_CSTS) == -1) {
2767	result = -ENODEV;
2768	goto disable;
2769	}
2770
2771	/*
2772	* Some devices and/or platforms don't advertise or work with INTx
2773	* interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2774	* adjust this later.
2775	*/
2776	if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2777	flags &= ~PCI_IRQ_MSI;
2778	result = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, flags);
2779	if (result < 0)
2780	goto disable;
2781
2782	dev->ctrl.cap = lo_hi_readq(addr: dev->bar + NVME_REG_CAP);
2783
2784	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2785	io_queue_depth);
2786	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2787	dev->dbs = dev->bar + 4096;
2788
2789	/*
2790	* Some Apple controllers require a non-standard SQE size.
2791	* Interestingly they also seem to ignore the CC:IOSQES register
2792	* so we don't bother updating it here.
2793	*/
2794	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2795	dev->io_sqes = 7;
2796	else
2797	dev->io_sqes = NVME_NVM_IOSQES;
2798
2799	if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) {
2800	dev->q_depth = 2;
2801	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2802	(pdev->device == 0xa821 || pdev->device == 0xa822) &&
2803	NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2804	dev->q_depth = 64;
2805	dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2806	"set queue depth=%u\n", dev->q_depth);
2807	}
2808
2809	/*
2810	* Controllers with the shared tags quirk need the IO queue to be
2811	* big enough so that we get 32 tags for the admin queue
2812	*/
2813	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2814	(dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2815	dev->q_depth = NVME_AQ_DEPTH + 2;
2816	dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2817	dev->q_depth);
2818	}
2819	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2820
2821	nvme_map_cmb(dev);
2822
2823	pci_save_state(dev: pdev);
2824
2825	result = nvme_pci_configure_admin_queue(dev);
2826	if (result)
2827	goto free_irq;
2828	return result;
2829
2830	free_irq:
2831	pci_free_irq_vectors(dev: pdev);
2832	disable:
2833	pci_disable_device(dev: pdev);
2834	return result;
2835	}
2836
2837	static void nvme_dev_unmap(struct nvme_dev *dev)
2838	{
2839	if (dev->bar)
2840	iounmap(addr: dev->bar);
2841	pci_release_mem_regions(to_pci_dev(dev->dev));
2842	}
2843
2844	static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2845	{
2846	struct pci_dev *pdev = to_pci_dev(dev->dev);
2847	u32 csts;
2848
2849	if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2850	return true;
2851	if (pdev->error_state != pci_channel_io_normal)
2852	return true;
2853
2854	csts = readl(addr: dev->bar + NVME_REG_CSTS);
2855	return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2856	}
2857
2858	static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2859	{
2860	enum nvme_ctrl_state state = nvme_ctrl_state(ctrl: &dev->ctrl);
2861	struct pci_dev *pdev = to_pci_dev(dev->dev);
2862	bool dead;
2863
2864	mutex_lock(&dev->shutdown_lock);
2865	dead = nvme_pci_ctrl_is_dead(dev);
2866	if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2867	if (pci_is_enabled(pdev))
2868	nvme_start_freeze(ctrl: &dev->ctrl);
2869	/*
2870	* Give the controller a chance to complete all entered requests
2871	* if doing a safe shutdown.
2872	*/
2873	if (!dead && shutdown)
2874	nvme_wait_freeze_timeout(ctrl: &dev->ctrl, NVME_IO_TIMEOUT);
2875	}
2876
2877	nvme_quiesce_io_queues(ctrl: &dev->ctrl);
2878
2879	if (!dead && dev->ctrl.queue_count > 0) {
2880	nvme_delete_io_queues(dev);
2881	nvme_disable_ctrl(ctrl: &dev->ctrl, shutdown);
2882	nvme_poll_irqdisable(nvmeq: &dev->queues[0]);
2883	}
2884	nvme_suspend_io_queues(dev);
2885	nvme_suspend_queue(dev, qid: 0);
2886	pci_free_irq_vectors(dev: pdev);
2887	if (pci_is_enabled(pdev))
2888	pci_disable_device(dev: pdev);
2889	nvme_reap_pending_cqes(dev);
2890
2891	nvme_cancel_tagset(ctrl: &dev->ctrl);
2892	nvme_cancel_admin_tagset(ctrl: &dev->ctrl);
2893
2894	/*
2895	* The driver will not be starting up queues again if shutting down so
2896	* must flush all entered requests to their failed completion to avoid
2897	* deadlocking blk-mq hot-cpu notifier.
2898	*/
2899	if (shutdown) {
2900	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
2901	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2902	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
2903	}
2904	mutex_unlock(lock: &dev->shutdown_lock);
2905	}
2906
2907	static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2908	{
2909	if (!nvme_wait_reset(ctrl: &dev->ctrl))
2910	return -EBUSY;
2911	nvme_dev_disable(dev, shutdown);
2912	return 0;
2913	}
2914
2915	static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2916	{
2917	size_t meta_size = sizeof(struct scatterlist) * (NVME_MAX_META_SEGS + 1);
2918	size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2919
2920	dev->iod_mempool = mempool_create_node(1,
2921	mempool_kmalloc, mempool_kfree,
2922	(void *)alloc_size, GFP_KERNEL,
2923	dev_to_node(dev->dev));
2924	if (!dev->iod_mempool)
2925	return -ENOMEM;
2926
2927	dev->iod_meta_mempool = mempool_create_node(1,
2928	mempool_kmalloc, mempool_kfree,
2929	(void *)meta_size, GFP_KERNEL,
2930	dev_to_node(dev->dev));
2931	if (!dev->iod_meta_mempool)
2932	goto free;
2933
2934	return 0;
2935	free:
2936	mempool_destroy(pool: dev->iod_mempool);
2937	return -ENOMEM;
2938	}
2939
2940	static void nvme_free_tagset(struct nvme_dev *dev)
2941	{
2942	if (dev->tagset.tags)
2943	nvme_remove_io_tag_set(ctrl: &dev->ctrl);
2944	dev->ctrl.tagset = NULL;
2945	}
2946
2947	/* pairs with nvme_pci_alloc_dev */
2948	static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2949	{
2950	struct nvme_dev *dev = to_nvme_dev(ctrl);
2951
2952	nvme_free_tagset(dev);
2953	put_device(dev: dev->dev);
2954	kfree(objp: dev->queues);
2955	kfree(objp: dev);
2956	}
2957
2958	static void nvme_reset_work(struct work_struct *work)
2959	{
2960	struct nvme_dev *dev =
2961	container_of(work, struct nvme_dev, ctrl.reset_work);
2962	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2963	int result;
2964
2965	if (nvme_ctrl_state(ctrl: &dev->ctrl) != NVME_CTRL_RESETTING) {
2966	dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2967	dev->ctrl.state);
2968	result = -ENODEV;
2969	goto out;
2970	}
2971
2972	/*
2973	* If we're called to reset a live controller first shut it down before
2974	* moving on.
2975	*/
2976	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2977	nvme_dev_disable(dev, shutdown: false);
2978	nvme_sync_queues(ctrl: &dev->ctrl);
2979
2980	mutex_lock(&dev->shutdown_lock);
2981	result = nvme_pci_enable(dev);
2982	if (result)
2983	goto out_unlock;
2984	nvme_unquiesce_admin_queue(ctrl: &dev->ctrl);
2985	mutex_unlock(lock: &dev->shutdown_lock);
2986
2987	/*
2988	* Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2989	* initializing procedure here.
2990	*/
2991	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_CONNECTING)) {
2992	dev_warn(dev->ctrl.device,
2993	"failed to mark controller CONNECTING\n");
2994	result = -EBUSY;
2995	goto out;
2996	}
2997
2998	result = nvme_init_ctrl_finish(ctrl: &dev->ctrl, was_suspended: was_suspend);
2999	if (result)
3000	goto out;
3001
3002	if (nvme_ctrl_meta_sgl_supported(ctrl: &dev->ctrl))
3003	dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
3004	else
3005	dev->ctrl.max_integrity_segments = 1;
3006
3007	nvme_dbbuf_dma_alloc(dev);
3008
3009	result = nvme_setup_host_mem(dev);
3010	if (result < 0)
3011	goto out;
3012
3013	result = nvme_setup_io_queues(dev);
3014	if (result)
3015	goto out;
3016
3017	/*
3018	* Freeze and update the number of I/O queues as those might have
3019	* changed. If there are no I/O queues left after this reset, keep the
3020	* controller around but remove all namespaces.
3021	*/
3022	if (dev->online_queues > 1) {
3023	nvme_dbbuf_set(dev);
3024	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
3025	nvme_wait_freeze(ctrl: &dev->ctrl);
3026	if (!nvme_pci_update_nr_queues(dev))
3027	goto out;
3028	nvme_unfreeze(ctrl: &dev->ctrl);
3029	} else {
3030	dev_warn(dev->ctrl.device, "IO queues lost\n");
3031	nvme_mark_namespaces_dead(ctrl: &dev->ctrl);
3032	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
3033	nvme_remove_namespaces(ctrl: &dev->ctrl);
3034	nvme_free_tagset(dev);
3035	}
3036
3037	/*
3038	* If only admin queue live, keep it to do further investigation or
3039	* recovery.
3040	*/
3041	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_LIVE)) {
3042	dev_warn(dev->ctrl.device,
3043	"failed to mark controller live state\n");
3044	result = -ENODEV;
3045	goto out;
3046	}
3047
3048	nvme_start_ctrl(ctrl: &dev->ctrl);
3049	return;
3050
3051	out_unlock:
3052	mutex_unlock(lock: &dev->shutdown_lock);
3053	out:
3054	/*
3055	* Set state to deleting now to avoid blocking nvme_wait_reset(), which
3056	* may be holding this pci_dev's device lock.
3057	*/
3058	dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
3059	result);
3060	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
3061	nvme_dev_disable(dev, shutdown: true);
3062	nvme_sync_queues(ctrl: &dev->ctrl);
3063	nvme_mark_namespaces_dead(ctrl: &dev->ctrl);
3064	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
3065	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DEAD);
3066	}
3067
3068	static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
3069	{
3070	*val = readl(addr: to_nvme_dev(ctrl)->bar + off);
3071	return 0;
3072	}
3073
3074	static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
3075	{
3076	writel(val, addr: to_nvme_dev(ctrl)->bar + off);
3077	return 0;
3078	}
3079
3080	static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
3081	{
3082	*val = lo_hi_readq(addr: to_nvme_dev(ctrl)->bar + off);
3083	return 0;
3084	}
3085
3086	static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
3087	{
3088	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3089
3090	return snprintf(buf, size, fmt: "%s\n", dev_name(dev: &pdev->dev));
3091	}
3092
3093	static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
3094	{
3095	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3096	struct nvme_subsystem *subsys = ctrl->subsys;
3097
3098	dev_err(ctrl->device,
3099	"VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
3100	pdev->vendor, pdev->device,
3101	nvme_strlen(subsys->model, sizeof(subsys->model)),
3102	subsys->model, nvme_strlen(subsys->firmware_rev,
3103	sizeof(subsys->firmware_rev)),
3104	subsys->firmware_rev);
3105	}
3106
3107	static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
3108	{
3109	struct nvme_dev *dev = to_nvme_dev(ctrl);
3110
3111	return dma_pci_p2pdma_supported(dev: dev->dev);
3112	}
3113
3114	static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
3115	.name = "pcie",
3116	.module = THIS_MODULE,
3117	.flags = NVME_F_METADATA_SUPPORTED,
3118	.dev_attr_groups = nvme_pci_dev_attr_groups,
3119	.reg_read32 = nvme_pci_reg_read32,
3120	.reg_write32 = nvme_pci_reg_write32,
3121	.reg_read64 = nvme_pci_reg_read64,
3122	.free_ctrl = nvme_pci_free_ctrl,
3123	.submit_async_event = nvme_pci_submit_async_event,
3124	.subsystem_reset = nvme_pci_subsystem_reset,
3125	.get_address = nvme_pci_get_address,
3126	.print_device_info = nvme_pci_print_device_info,
3127	.supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
3128	};
3129
3130	static int nvme_dev_map(struct nvme_dev *dev)
3131	{
3132	struct pci_dev *pdev = to_pci_dev(dev->dev);
3133
3134	if (pci_request_mem_regions(pdev, name: "nvme"))
3135	return -ENODEV;
3136
3137	if (nvme_remap_bar(dev, size: NVME_REG_DBS + 4096))
3138	goto release;
3139
3140	return 0;
3141	release:
3142	pci_release_mem_regions(pdev);
3143	return -ENODEV;
3144	}
3145
3146	static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3147	{
3148	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3149	/*
3150	* Several Samsung devices seem to drop off the PCIe bus
3151	* randomly when APST is on and uses the deepest sleep state.
3152	* This has been observed on a Samsung "SM951 NVMe SAMSUNG
3153	* 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3154	* 950 PRO 256GB", but it seems to be restricted to two Dell
3155	* laptops.
3156	*/
3157	if (dmi_match(f: DMI_SYS_VENDOR, str: "Dell Inc.") &&
3158	(dmi_match(f: DMI_PRODUCT_NAME, str: "XPS 15 9550") ||
3159	dmi_match(f: DMI_PRODUCT_NAME, str: "Precision 5510")))
3160	return NVME_QUIRK_NO_DEEPEST_PS;
3161	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3162	/*
3163	* Samsung SSD 960 EVO drops off the PCIe bus after system
3164	* suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3165	* within few minutes after bootup on a Coffee Lake board -
3166	* ASUS PRIME Z370-A
3167	*/
3168	if (dmi_match(f: DMI_BOARD_VENDOR, str: "ASUSTeK COMPUTER INC.") &&
3169	(dmi_match(f: DMI_BOARD_NAME, str: "PRIME B350M-A") ||
3170	dmi_match(f: DMI_BOARD_NAME, str: "PRIME Z370-A")))
3171	return NVME_QUIRK_NO_APST;
3172	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3173	pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3174	(pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3175	/*
3176	* Forcing to use host managed nvme power settings for
3177	* lowest idle power with quick resume latency on
3178	* Samsung and Toshiba SSDs based on suspend behavior
3179	* on Coffee Lake board for LENOVO C640
3180	*/
3181	if ((dmi_match(f: DMI_BOARD_VENDOR, str: "LENOVO")) &&
3182	dmi_match(f: DMI_BOARD_NAME, str: "LNVNB161216"))
3183	return NVME_QUIRK_SIMPLE_SUSPEND;
3184	} else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
3185	pdev->device == 0x500f)) {
3186	/*
3187	* Exclude some Kingston NV1 and A2000 devices from
3188	* NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
3189	* lot of energy with s2idle sleep on some TUXEDO platforms.
3190	*/
3191	if (dmi_match(f: DMI_BOARD_NAME, str: "NS5X_NS7XAU") ||
3192	dmi_match(f: DMI_BOARD_NAME, str: "NS5x_7xAU") ||
3193	dmi_match(f: DMI_BOARD_NAME, str: "NS5x_7xPU") ||
3194	dmi_match(f: DMI_BOARD_NAME, str: "PH4PRX1_PH6PRX1"))
3195	return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3196	} else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
3197	/*
3198	* Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
3199	* because of high power consumption (> 2 Watt) in s2idle
3200	* sleep. Only some boards with Intel CPU are affected.
3201	*/
3202	if (dmi_match(f: DMI_BOARD_NAME, str: "DN50Z-140HC-YD") ||
3203	dmi_match(f: DMI_BOARD_NAME, str: "GMxPXxx") ||
3204	dmi_match(f: DMI_BOARD_NAME, str: "GXxMRXx") ||
3205	dmi_match(f: DMI_BOARD_NAME, str: "PH4PG31") ||
3206	dmi_match(f: DMI_BOARD_NAME, str: "PH4PRX1_PH6PRX1") ||
3207	dmi_match(f: DMI_BOARD_NAME, str: "PH6PG01_PH6PG71"))
3208	return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3209	}
3210
3211	/*
3212	* NVMe SSD drops off the PCIe bus after system idle
3213	* for 10 hours on a Lenovo N60z board.
3214	*/
3215	if (dmi_match(f: DMI_BOARD_NAME, str: "LXKT-ZXEG-N6"))
3216	return NVME_QUIRK_NO_APST;
3217
3218	return 0;
3219	}
3220
3221	static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
3222	const struct pci_device_id *id)
3223	{
3224	unsigned long quirks = id->driver_data;
3225	int node = dev_to_node(dev: &pdev->dev);
3226	struct nvme_dev *dev;
3227	int ret = -ENOMEM;
3228
3229	dev = kzalloc_node(struct_size(dev, descriptor_pools, nr_node_ids),
3230	GFP_KERNEL, node);
3231	if (!dev)
3232	return ERR_PTR(error: -ENOMEM);
3233	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3234	mutex_init(&dev->shutdown_lock);
3235
3236	dev->nr_write_queues = write_queues;
3237	dev->nr_poll_queues = poll_queues;
3238	dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3239	dev->queues = kcalloc_node(dev->nr_allocated_queues,
3240	sizeof(struct nvme_queue), GFP_KERNEL, node);
3241	if (!dev->queues)
3242	goto out_free_dev;
3243
3244	dev->dev = get_device(dev: &pdev->dev);
3245
3246	quirks |= check_vendor_combination_bug(pdev);
3247	if (!noacpi &&
3248	!(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
3249	acpi_storage_d3(dev: &pdev->dev)) {
3250	/*
3251	* Some systems use a bios work around to ask for D3 on
3252	* platforms that support kernel managed suspend.
3253	*/
3254	dev_info(&pdev->dev,
3255	"platform quirk: setting simple suspend\n");
3256	quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3257	}
3258	ret = nvme_init_ctrl(ctrl: &dev->ctrl, dev: &pdev->dev, ops: &nvme_pci_ctrl_ops,
3259	quirks);
3260	if (ret)
3261	goto out_put_device;
3262
3263	if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
3264	dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(48));
3265	else
3266	dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(64));
3267	dma_set_min_align_mask(dev: &pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3268	dma_set_max_seg_size(dev: &pdev->dev, size: 0xffffffff);
3269
3270	/*
3271	* Limit the max command size to prevent iod->sg allocations going
3272	* over a single page.
3273	*/
3274	dev->ctrl.max_hw_sectors = min_t(u32,
3275	NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3276	dev->ctrl.max_segments = NVME_MAX_SEGS;
3277	dev->ctrl.max_integrity_segments = 1;
3278	return dev;
3279
3280	out_put_device:
3281	put_device(dev: dev->dev);
3282	kfree(objp: dev->queues);
3283	out_free_dev:
3284	kfree(objp: dev);
3285	return ERR_PTR(error: ret);
3286	}
3287
3288	static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3289	{
3290	struct nvme_dev *dev;
3291	int result = -ENOMEM;
3292
3293	dev = nvme_pci_alloc_dev(pdev, id);
3294	if (IS_ERR(ptr: dev))
3295	return PTR_ERR(ptr: dev);
3296
3297	result = nvme_add_ctrl(ctrl: &dev->ctrl);
3298	if (result)
3299	goto out_put_ctrl;
3300
3301	result = nvme_dev_map(dev);
3302	if (result)
3303	goto out_uninit_ctrl;
3304
3305	result = nvme_pci_alloc_iod_mempool(dev);
3306	if (result)
3307	goto out_dev_unmap;
3308
3309	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3310
3311	result = nvme_pci_enable(dev);
3312	if (result)
3313	goto out_release_iod_mempool;
3314
3315	result = nvme_alloc_admin_tag_set(ctrl: &dev->ctrl, set: &dev->admin_tagset,
3316	ops: &nvme_mq_admin_ops, cmd_size: sizeof(struct nvme_iod));
3317	if (result)
3318	goto out_disable;
3319
3320	/*
3321	* Mark the controller as connecting before sending admin commands to
3322	* allow the timeout handler to do the right thing.
3323	*/
3324	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_CONNECTING)) {
3325	dev_warn(dev->ctrl.device,
3326	"failed to mark controller CONNECTING\n");
3327	result = -EBUSY;
3328	goto out_disable;
3329	}
3330
3331	result = nvme_init_ctrl_finish(ctrl: &dev->ctrl, was_suspended: false);
3332	if (result)
3333	goto out_disable;
3334
3335	if (nvme_ctrl_meta_sgl_supported(ctrl: &dev->ctrl))
3336	dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
3337	else
3338	dev->ctrl.max_integrity_segments = 1;
3339
3340	nvme_dbbuf_dma_alloc(dev);
3341
3342	result = nvme_setup_host_mem(dev);
3343	if (result < 0)
3344	goto out_disable;
3345
3346	result = nvme_setup_io_queues(dev);
3347	if (result)
3348	goto out_disable;
3349
3350	if (dev->online_queues > 1) {
3351	nvme_alloc_io_tag_set(ctrl: &dev->ctrl, set: &dev->tagset, ops: &nvme_mq_ops,
3352	nr_maps: nvme_pci_nr_maps(dev), cmd_size: sizeof(struct nvme_iod));
3353	nvme_dbbuf_set(dev);
3354	}
3355
3356	if (!dev->ctrl.tagset)
3357	dev_warn(dev->ctrl.device, "IO queues not created\n");
3358
3359	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_LIVE)) {
3360	dev_warn(dev->ctrl.device,
3361	"failed to mark controller live state\n");
3362	result = -ENODEV;
3363	goto out_disable;
3364	}
3365
3366	pci_set_drvdata(pdev, data: dev);
3367
3368	nvme_start_ctrl(ctrl: &dev->ctrl);
3369	nvme_put_ctrl(ctrl: &dev->ctrl);
3370	flush_work(work: &dev->ctrl.scan_work);
3371	return 0;
3372
3373	out_disable:
3374	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
3375	nvme_dev_disable(dev, shutdown: true);
3376	nvme_free_host_mem(dev);
3377	nvme_dev_remove_admin(dev);
3378	nvme_dbbuf_dma_free(dev);
3379	nvme_free_queues(dev, lowest: 0);
3380	out_release_iod_mempool:
3381	mempool_destroy(pool: dev->iod_mempool);
3382	mempool_destroy(pool: dev->iod_meta_mempool);
3383	out_dev_unmap:
3384	nvme_dev_unmap(dev);
3385	out_uninit_ctrl:
3386	nvme_uninit_ctrl(ctrl: &dev->ctrl);
3387	out_put_ctrl:
3388	nvme_put_ctrl(ctrl: &dev->ctrl);
3389	return result;
3390	}
3391
3392	static void nvme_reset_prepare(struct pci_dev *pdev)
3393	{
3394	struct nvme_dev *dev = pci_get_drvdata(pdev);
3395
3396	/*
3397	* We don't need to check the return value from waiting for the reset
3398	* state as pci_dev device lock is held, making it impossible to race
3399	* with ->remove().
3400	*/
3401	nvme_disable_prepare_reset(dev, shutdown: false);
3402	nvme_sync_queues(ctrl: &dev->ctrl);
3403	}
3404
3405	static void nvme_reset_done(struct pci_dev *pdev)
3406	{
3407	struct nvme_dev *dev = pci_get_drvdata(pdev);
3408
3409	if (!nvme_try_sched_reset(ctrl: &dev->ctrl))
3410	flush_work(work: &dev->ctrl.reset_work);
3411	}
3412
3413	static void nvme_shutdown(struct pci_dev *pdev)
3414	{
3415	struct nvme_dev *dev = pci_get_drvdata(pdev);
3416
3417	nvme_disable_prepare_reset(dev, shutdown: true);
3418	}
3419
3420	/*
3421	* The driver's remove may be called on a device in a partially initialized
3422	* state. This function must not have any dependencies on the device state in
3423	* order to proceed.
3424	*/
3425	static void nvme_remove(struct pci_dev *pdev)
3426	{
3427	struct nvme_dev *dev = pci_get_drvdata(pdev);
3428
3429	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DELETING);
3430	pci_set_drvdata(pdev, NULL);
3431
3432	if (!pci_device_is_present(pdev)) {
3433	nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_DEAD);
3434	nvme_dev_disable(dev, shutdown: true);
3435	}
3436
3437	flush_work(work: &dev->ctrl.reset_work);
3438	nvme_stop_ctrl(ctrl: &dev->ctrl);
3439	nvme_remove_namespaces(ctrl: &dev->ctrl);
3440	nvme_dev_disable(dev, shutdown: true);
3441	nvme_free_host_mem(dev);
3442	nvme_dev_remove_admin(dev);
3443	nvme_dbbuf_dma_free(dev);
3444	nvme_free_queues(dev, lowest: 0);
3445	mempool_destroy(pool: dev->iod_mempool);
3446	mempool_destroy(pool: dev->iod_meta_mempool);
3447	nvme_release_descriptor_pools(dev);
3448	nvme_dev_unmap(dev);
3449	nvme_uninit_ctrl(ctrl: &dev->ctrl);
3450	}
3451
3452	#ifdef CONFIG_PM_SLEEP
3453	static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3454	{
3455	return nvme_get_features(dev: ctrl, fid: NVME_FEAT_POWER_MGMT, dword11: 0, NULL, buflen: 0, result: ps);
3456	}
3457
3458	static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3459	{
3460	return nvme_set_features(dev: ctrl, fid: NVME_FEAT_POWER_MGMT, dword11: ps, NULL, buflen: 0, NULL);
3461	}
3462
3463	static int nvme_resume(struct device *dev)
3464	{
3465	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3466	struct nvme_ctrl *ctrl = &ndev->ctrl;
3467
3468	if (ndev->last_ps == U32_MAX ||
3469	nvme_set_power_state(ctrl, ps: ndev->last_ps) != 0)
3470	goto reset;
3471	if (ctrl->hmpre && nvme_setup_host_mem(dev: ndev))
3472	goto reset;
3473
3474	return 0;
3475	reset:
3476	return nvme_try_sched_reset(ctrl);
3477	}
3478
3479	static int nvme_suspend(struct device *dev)
3480	{
3481	struct pci_dev *pdev = to_pci_dev(dev);
3482	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3483	struct nvme_ctrl *ctrl = &ndev->ctrl;
3484	int ret = -EBUSY;
3485
3486	ndev->last_ps = U32_MAX;
3487
3488	/*
3489	* The platform does not remove power for a kernel managed suspend so
3490	* use host managed nvme power settings for lowest idle power if
3491	* possible. This should have quicker resume latency than a full device
3492	* shutdown. But if the firmware is involved after the suspend or the
3493	* device does not support any non-default power states, shut down the
3494	* device fully.
3495	*
3496	* If ASPM is not enabled for the device, shut down the device and allow
3497	* the PCI bus layer to put it into D3 in order to take the PCIe link
3498	* down, so as to allow the platform to achieve its minimum low-power
3499	* state (which may not be possible if the link is up).
3500	*/
3501	if (pm_suspend_via_firmware() || !ctrl->npss ||
3502	!pcie_aspm_enabled(pdev) ||
3503	(ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3504	return nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3505
3506	nvme_start_freeze(ctrl);
3507	nvme_wait_freeze(ctrl);
3508	nvme_sync_queues(ctrl);
3509
3510	if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3511	goto unfreeze;
3512
3513	/*
3514	* Host memory access may not be successful in a system suspend state,
3515	* but the specification allows the controller to access memory in a
3516	* non-operational power state.
3517	*/
3518	if (ndev->hmb) {
3519	ret = nvme_set_host_mem(dev: ndev, bits: 0);
3520	if (ret < 0)
3521	goto unfreeze;
3522	}
3523
3524	ret = nvme_get_power_state(ctrl, ps: &ndev->last_ps);
3525	if (ret < 0)
3526	goto unfreeze;
3527
3528	/*
3529	* A saved state prevents pci pm from generically controlling the
3530	* device's power. If we're using protocol specific settings, we don't
3531	* want pci interfering.
3532	*/
3533	pci_save_state(dev: pdev);
3534
3535	ret = nvme_set_power_state(ctrl, ps: ctrl->npss);
3536	if (ret < 0)
3537	goto unfreeze;
3538
3539	if (ret) {
3540	/* discard the saved state */
3541	pci_load_saved_state(dev: pdev, NULL);
3542
3543	/*
3544	* Clearing npss forces a controller reset on resume. The
3545	* correct value will be rediscovered then.
3546	*/
3547	ret = nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3548	ctrl->npss = 0;
3549	}
3550	unfreeze:
3551	nvme_unfreeze(ctrl);
3552	return ret;
3553	}
3554
3555	static int nvme_simple_suspend(struct device *dev)
3556	{
3557	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3558
3559	return nvme_disable_prepare_reset(dev: ndev, shutdown: true);
3560	}
3561
3562	static int nvme_simple_resume(struct device *dev)
3563	{
3564	struct pci_dev *pdev = to_pci_dev(dev);
3565	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3566
3567	return nvme_try_sched_reset(ctrl: &ndev->ctrl);
3568	}
3569
3570	static const struct dev_pm_ops nvme_dev_pm_ops = {
3571	.suspend = nvme_suspend,
3572	.resume = nvme_resume,
3573	.freeze = nvme_simple_suspend,
3574	.thaw = nvme_simple_resume,
3575	.poweroff = nvme_simple_suspend,
3576	.restore = nvme_simple_resume,
3577	};
3578	#endif /* CONFIG_PM_SLEEP */
3579
3580	static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3581	pci_channel_state_t state)
3582	{
3583	struct nvme_dev *dev = pci_get_drvdata(pdev);
3584
3585	/*
3586	* A frozen channel requires a reset. When detected, this method will
3587	* shutdown the controller to quiesce. The controller will be restarted
3588	* after the slot reset through driver's slot_reset callback.
3589	*/
3590	switch (state) {
3591	case pci_channel_io_normal:
3592	return PCI_ERS_RESULT_CAN_RECOVER;
3593	case pci_channel_io_frozen:
3594	dev_warn(dev->ctrl.device,
3595	"frozen state error detected, reset controller\n");
3596	if (!nvme_change_ctrl_state(ctrl: &dev->ctrl, new_state: NVME_CTRL_RESETTING)) {
3597	nvme_dev_disable(dev, shutdown: true);
3598	return PCI_ERS_RESULT_DISCONNECT;
3599	}
3600	nvme_dev_disable(dev, shutdown: false);
3601	return PCI_ERS_RESULT_NEED_RESET;
3602	case pci_channel_io_perm_failure:
3603	dev_warn(dev->ctrl.device,
3604	"failure state error detected, request disconnect\n");
3605	return PCI_ERS_RESULT_DISCONNECT;
3606	}
3607	return PCI_ERS_RESULT_NEED_RESET;
3608	}
3609
3610	static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3611	{
3612	struct nvme_dev *dev = pci_get_drvdata(pdev);
3613
3614	dev_info(dev->ctrl.device, "restart after slot reset\n");
3615	pci_restore_state(dev: pdev);
3616	if (nvme_try_sched_reset(ctrl: &dev->ctrl))
3617	nvme_unquiesce_io_queues(ctrl: &dev->ctrl);
3618	return PCI_ERS_RESULT_RECOVERED;
3619	}
3620
3621	static void nvme_error_resume(struct pci_dev *pdev)
3622	{
3623	struct nvme_dev *dev = pci_get_drvdata(pdev);
3624
3625	flush_work(work: &dev->ctrl.reset_work);
3626	}
3627
3628	static const struct pci_error_handlers nvme_err_handler = {
3629	.error_detected = nvme_error_detected,
3630	.slot_reset = nvme_slot_reset,
3631	.resume = nvme_error_resume,
3632	.reset_prepare = nvme_reset_prepare,
3633	.reset_done = nvme_reset_done,
3634	};
3635
3636	static const struct pci_device_id nvme_id_table[] = {
3637	{ PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3638	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3639	NVME_QUIRK_DEALLOCATE_ZEROES, },
3640	{ PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3641	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3642	NVME_QUIRK_DEALLOCATE_ZEROES, },
3643	{ PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3644	.driver_data = NVME_QUIRK_STRIPE_SIZE |
3645	NVME_QUIRK_IGNORE_DEV_SUBNQN |
3646	NVME_QUIRK_BOGUS_NID, },
3647	{ PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3648	.driver_data = NVME_QUIRK_STRIPE_SIZE, },
3649	{ PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3650	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3651	NVME_QUIRK_MEDIUM_PRIO_SQ |
3652	NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3653	NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3654	{ PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3655	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3656	{ PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3657	.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3658	NVME_QUIRK_DISABLE_WRITE_ZEROES |
3659	NVME_QUIRK_BOGUS_NID, },
3660	{ PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3661	.driver_data = NVME_QUIRK_BOGUS_NID, },
3662	{ PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */
3663	.driver_data = NVME_QUIRK_DMAPOOL_ALIGN_512, },
3664	{ PCI_DEVICE(0x126f, 0x1001), /* Silicon Motion generic */
3665	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3666	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3667	{ PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3668	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3669	NVME_QUIRK_BOGUS_NID, },
3670	{ PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3671	.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3672	NVME_QUIRK_BOGUS_NID, },
3673	{ PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3674	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3675	NVME_QUIRK_NO_NS_DESC_LIST, },
3676	{ PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3677	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3678	{ PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3679	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3680	{ PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3681	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3682	{ PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3683	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3684	{ PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3685	.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3686	NVME_QUIRK_DISABLE_WRITE_ZEROES|
3687	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3688	{ PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3689	.driver_data = NVME_QUIRK_BROKEN_MSI },
3690	{ PCI_DEVICE(0x15b7, 0x5009), /* Sandisk SN550 */
3691	.driver_data = NVME_QUIRK_BROKEN_MSI |
3692	NVME_QUIRK_NO_DEEPEST_PS },
3693	{ PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3694	.driver_data = NVME_QUIRK_BOGUS_NID, },
3695	{ PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3696	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3697	NVME_QUIRK_BOGUS_NID, },
3698	{ PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3699	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3700	{ PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3701	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3702	{ PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3703	.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3704	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3705	{ PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3706	.driver_data = NVME_QUIRK_BOGUS_NID, },
3707	{ PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3708	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3709	NVME_QUIRK_BOGUS_NID, },
3710	{ PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3711	.driver_data = NVME_QUIRK_BOGUS_NID, },
3712	{ PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3713	.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3714	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3715	{ PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3716	.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3717	{ PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3718	.driver_data = NVME_QUIRK_BOGUS_NID, },
3719	{ PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3720	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3721	{ PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3722	.driver_data = NVME_QUIRK_BOGUS_NID, },
3723	{ PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */
3724	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3725	{ PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3726	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3727	{ PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3728	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3729	{ PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3730	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3731	NVME_QUIRK_BOGUS_NID, },
3732	{ PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3733	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3734	{ PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3735	.driver_data = NVME_QUIRK_BOGUS_NID, },
3736	{ PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3737	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3738	{ PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3739	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3740	{ PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3741	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3742	{ PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3743	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3744	{ PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3745	.driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3746	{ PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3747	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3748	{ PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3749	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3750	{ PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3751	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3752	{ PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3753	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3754	{ PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3755	.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3756	{ PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3757	.driver_data = NVME_QUIRK_BOGUS_NID, },
3758	{ PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3759	.driver_data = NVME_QUIRK_BOGUS_NID, },
3760	{ PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3761	.driver_data = NVME_QUIRK_BOGUS_NID, },
3762	{ PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3763	.driver_data = NVME_QUIRK_BOGUS_NID, },
3764	{ PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3765	.driver_data = NVME_QUIRK_BOGUS_NID, },
3766	{ PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3767	.driver_data = NVME_QUIRK_BOGUS_NID, },
3768	{ PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3769	.driver_data = NVME_QUIRK_BOGUS_NID, },
3770	{ PCI_DEVICE(0x1dbe, 0x5216), /* Acer/INNOGRIT FA100/5216 NVMe SSD */
3771	.driver_data = NVME_QUIRK_BOGUS_NID, },
3772	{ PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3773	.driver_data = NVME_QUIRK_BOGUS_NID, },
3774	{ PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3775	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3776	{ PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3777	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3778	{ PCI_DEVICE(0x025e, 0xf1ac), /* SOLIDIGM P44 pro SSDPFKKW020X7 */
3779	.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3780	{ PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3781	.driver_data = NVME_QUIRK_BOGUS_NID, },
3782	{ PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3783	.driver_data = NVME_QUIRK_BOGUS_NID, },
3784	{ PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3785	.driver_data = NVME_QUIRK_BOGUS_NID, },
3786	{ PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3787	.driver_data = NVME_QUIRK_BOGUS_NID |
3788	NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3789	{ PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3790	.driver_data = NVME_QUIRK_BOGUS_NID, },
3791	{ PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3792	.driver_data = NVME_QUIRK_BOGUS_NID, },
3793	{ PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3794	.driver_data = NVME_QUIRK_BOGUS_NID, },
3795	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3796	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3797	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3798	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3799	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3800	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3801	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3802	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3803	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3804	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3805	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3806	.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3807	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3808	/*
3809	* Fix for the Apple controller found in the MacBook8,1 and
3810	* some MacBook7,1 to avoid controller resets and data loss.
3811	*/
3812	.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3813	NVME_QUIRK_QDEPTH_ONE },
3814	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3815	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3816	.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3817	NVME_QUIRK_128_BYTES_SQES |
3818	NVME_QUIRK_SHARED_TAGS |
3819	NVME_QUIRK_SKIP_CID_GEN |
3820	NVME_QUIRK_IDENTIFY_CNS },
3821	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3822	{ 0, }
3823	};
3824	MODULE_DEVICE_TABLE(pci, nvme_id_table);
3825
3826	static struct pci_driver nvme_driver = {
3827	.name = "nvme",
3828	.id_table = nvme_id_table,
3829	.probe = nvme_probe,
3830	.remove = nvme_remove,
3831	.shutdown = nvme_shutdown,
3832	.driver = {
3833	.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3834	#ifdef CONFIG_PM_SLEEP
3835	.pm = &nvme_dev_pm_ops,
3836	#endif
3837	},
3838	.sriov_configure = pci_sriov_configure_simple,
3839	.err_handler = &nvme_err_handler,
3840	};
3841
3842	static int __init nvme_init(void)
3843	{
3844	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3845	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3846	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3847	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3848	BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_DESCRIPTORS);
3849
3850	return pci_register_driver(&nvme_driver);
3851	}
3852
3853	static void __exit nvme_exit(void)
3854	{
3855	pci_unregister_driver(dev: &nvme_driver);
3856	flush_workqueue(nvme_wq);
3857	}
3858
3859	MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3860	MODULE_LICENSE("GPL");
3861	MODULE_VERSION("1.0");
3862	MODULE_DESCRIPTION("NVMe host PCIe transport driver");
3863	module_init(nvme_init);
3864	module_exit(nvme_exit);
3865