1 | // SPDX-License-Identifier: GPL-2.0 |
---|---|
2 | /* |
3 | * This file contains work-arounds for many known PCI hardware bugs. |
4 | * Devices present only on certain architectures (host bridges et cetera) |
5 | * should be handled in arch-specific code. |
6 | * |
7 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
8 | * |
9 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
10 | * |
11 | * Init/reset quirks for USB host controllers should be in the USB quirks |
12 | * file, where their drivers can use them. |
13 | */ |
14 | |
15 | #include <linux/aer.h> |
16 | #include <linux/align.h> |
17 | #include <linux/bitfield.h> |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/export.h> |
21 | #include <linux/pci.h> |
22 | #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ |
23 | #include <linux/init.h> |
24 | #include <linux/delay.h> |
25 | #include <linux/acpi.h> |
26 | #include <linux/dmi.h> |
27 | #include <linux/ioport.h> |
28 | #include <linux/sched.h> |
29 | #include <linux/ktime.h> |
30 | #include <linux/mm.h> |
31 | #include <linux/nvme.h> |
32 | #include <linux/platform_data/x86/apple.h> |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/sizes.h> |
35 | #include <linux/suspend.h> |
36 | #include <linux/switchtec.h> |
37 | #include "pci.h" |
38 | |
39 | static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) |
40 | { |
41 | if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) |
42 | return true; |
43 | |
44 | return lnksta & PCI_EXP_LNKSTA_LBMS; |
45 | } |
46 | |
47 | /* |
48 | * Retrain the link of a downstream PCIe port by hand if necessary. |
49 | * |
50 | * This is needed at least where a downstream port of the ASMedia ASM2824 |
51 | * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 |
52 | * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > |
53 | * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched |
54 | * board. |
55 | * |
56 | * In such a configuration the switches are supposed to negotiate the link |
57 | * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link |
58 | * continues switching between the two speeds indefinitely and the data |
59 | * link layer never reaches the active state, with link training reported |
60 | * repeatedly active ~84% of the time. Forcing the target link speed to |
61 | * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to |
62 | * each other correctly however. And more interestingly retraining with a |
63 | * higher target link speed afterwards lets the two successfully negotiate |
64 | * 5.0GT/s. |
65 | * |
66 | * With the ASM2824 we can rely on the otherwise optional Data Link Layer |
67 | * Link Active status bit and in the failed link training scenario it will |
68 | * be off along with the Link Bandwidth Management Status indicating that |
69 | * hardware has changed the link speed or width in an attempt to correct |
70 | * unreliable link operation. For a port that has been left unconnected |
71 | * both bits will be clear. So use this information to detect the problem |
72 | * rather than polling the Link Training bit and watching out for flips or |
73 | * at least the active status. |
74 | * |
75 | * Since the exact nature of the problem isn't known and in principle this |
76 | * could trigger where an ASM2824 device is downstream rather upstream, |
77 | * apply this erratum workaround to any downstream ports as long as they |
78 | * support Link Active reporting and have the Link Control 2 register. |
79 | * Restrict the speed to 2.5GT/s then with the Target Link Speed field, |
80 | * request a retrain and check the result. |
81 | * |
82 | * If this turns out successful and we know by the Vendor:Device ID it is |
83 | * safe to do so, then lift the restriction, letting the devices negotiate |
84 | * a higher speed. Also check for a similar 2.5GT/s speed restriction the |
85 | * firmware may have already arranged and lift it with ports that already |
86 | * report their data link being up. |
87 | * |
88 | * Otherwise revert the speed to the original setting and request a retrain |
89 | * again to remove any residual state, ignoring the result as it's supposed |
90 | * to fail anyway. |
91 | * |
92 | * Return 0 if the link has been successfully retrained. Return an error |
93 | * if retraining was not needed or we attempted a retrain and it failed. |
94 | */ |
95 | int pcie_failed_link_retrain(struct pci_dev *dev) |
96 | { |
97 | static const struct pci_device_id ids[] = { |
98 | { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ |
99 | {} |
100 | }; |
101 | u16 lnksta, lnkctl2; |
102 | int ret = -ENOTTY; |
103 | |
104 | if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || |
105 | !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) |
106 | return ret; |
107 | |
108 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, val: &lnkctl2); |
109 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, val: &lnksta); |
110 | if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { |
111 | u16 oldlnkctl2 = lnkctl2; |
112 | |
113 | pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); |
114 | |
115 | ret = pcie_set_target_speed(port: dev, speed_req: PCIE_SPEED_2_5GT, use_lt: false); |
116 | if (ret) { |
117 | pci_info(dev, "retraining failed\n"); |
118 | pcie_set_target_speed(port: dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), |
119 | use_lt: true); |
120 | return ret; |
121 | } |
122 | |
123 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, val: &lnksta); |
124 | } |
125 | |
126 | if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && |
127 | (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && |
128 | pci_match_id(ids, dev)) { |
129 | u32 lnkcap; |
130 | |
131 | pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); |
132 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, val: &lnkcap); |
133 | ret = pcie_set_target_speed(port: dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), use_lt: false); |
134 | if (ret) { |
135 | pci_info(dev, "retraining failed\n"); |
136 | return ret; |
137 | } |
138 | } |
139 | |
140 | return ret; |
141 | } |
142 | |
143 | static ktime_t fixup_debug_start(struct pci_dev *dev, |
144 | void (*fn)(struct pci_dev *dev)) |
145 | { |
146 | if (initcall_debug) |
147 | pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); |
148 | |
149 | return ktime_get(); |
150 | } |
151 | |
152 | static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, |
153 | void (*fn)(struct pci_dev *dev)) |
154 | { |
155 | ktime_t delta, rettime; |
156 | unsigned long long duration; |
157 | |
158 | rettime = ktime_get(); |
159 | delta = ktime_sub(rettime, calltime); |
160 | duration = (unsigned long long) ktime_to_ns(kt: delta) >> 10; |
161 | if (initcall_debug || duration > 10000) |
162 | pci_info(dev, "%pS took %lld usecs\n", fn, duration); |
163 | } |
164 | |
165 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
166 | struct pci_fixup *end) |
167 | { |
168 | ktime_t calltime; |
169 | |
170 | for (; f < end; f++) |
171 | if ((f->class == (u32) (dev->class >> f->class_shift) || |
172 | f->class == (u32) PCI_ANY_ID) && |
173 | (f->vendor == dev->vendor || |
174 | f->vendor == (u16) PCI_ANY_ID) && |
175 | (f->device == dev->device || |
176 | f->device == (u16) PCI_ANY_ID)) { |
177 | void (*hook)(struct pci_dev *dev); |
178 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS |
179 | hook = offset_to_ptr(off: &f->hook_offset); |
180 | #else |
181 | hook = f->hook; |
182 | #endif |
183 | calltime = fixup_debug_start(dev, fn: hook); |
184 | hook(dev); |
185 | fixup_debug_report(dev, calltime, fn: hook); |
186 | } |
187 | } |
188 | |
189 | extern struct pci_fixup __start_pci_fixups_early[]; |
190 | extern struct pci_fixup __end_pci_fixups_early[]; |
191 | extern struct pci_fixup __start_pci_fixups_header[]; |
192 | extern struct pci_fixup __end_pci_fixups_header[]; |
193 | extern struct pci_fixup __start_pci_fixups_final[]; |
194 | extern struct pci_fixup __end_pci_fixups_final[]; |
195 | extern struct pci_fixup __start_pci_fixups_enable[]; |
196 | extern struct pci_fixup __end_pci_fixups_enable[]; |
197 | extern struct pci_fixup __start_pci_fixups_resume[]; |
198 | extern struct pci_fixup __end_pci_fixups_resume[]; |
199 | extern struct pci_fixup __start_pci_fixups_resume_early[]; |
200 | extern struct pci_fixup __end_pci_fixups_resume_early[]; |
201 | extern struct pci_fixup __start_pci_fixups_suspend[]; |
202 | extern struct pci_fixup __end_pci_fixups_suspend[]; |
203 | extern struct pci_fixup __start_pci_fixups_suspend_late[]; |
204 | extern struct pci_fixup __end_pci_fixups_suspend_late[]; |
205 | |
206 | static bool pci_apply_fixup_final_quirks; |
207 | |
208 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) |
209 | { |
210 | struct pci_fixup *start, *end; |
211 | |
212 | switch (pass) { |
213 | case pci_fixup_early: |
214 | start = __start_pci_fixups_early; |
215 | end = __end_pci_fixups_early; |
216 | break; |
217 | |
218 | case pci_fixup_header: |
219 | start = __start_pci_fixups_header; |
220 | end = __end_pci_fixups_header; |
221 | break; |
222 | |
223 | case pci_fixup_final: |
224 | if (!pci_apply_fixup_final_quirks) |
225 | return; |
226 | start = __start_pci_fixups_final; |
227 | end = __end_pci_fixups_final; |
228 | break; |
229 | |
230 | case pci_fixup_enable: |
231 | start = __start_pci_fixups_enable; |
232 | end = __end_pci_fixups_enable; |
233 | break; |
234 | |
235 | case pci_fixup_resume: |
236 | start = __start_pci_fixups_resume; |
237 | end = __end_pci_fixups_resume; |
238 | break; |
239 | |
240 | case pci_fixup_resume_early: |
241 | start = __start_pci_fixups_resume_early; |
242 | end = __end_pci_fixups_resume_early; |
243 | break; |
244 | |
245 | case pci_fixup_suspend: |
246 | start = __start_pci_fixups_suspend; |
247 | end = __end_pci_fixups_suspend; |
248 | break; |
249 | |
250 | case pci_fixup_suspend_late: |
251 | start = __start_pci_fixups_suspend_late; |
252 | end = __end_pci_fixups_suspend_late; |
253 | break; |
254 | |
255 | default: |
256 | /* stupid compiler warning, you would think with an enum... */ |
257 | return; |
258 | } |
259 | pci_do_fixups(dev, f: start, end); |
260 | } |
261 | EXPORT_SYMBOL(pci_fixup_device); |
262 | |
263 | static int __init pci_apply_final_quirks(void) |
264 | { |
265 | struct pci_dev *dev = NULL; |
266 | u8 cls = 0; |
267 | u8 tmp; |
268 | |
269 | if (pci_cache_line_size) |
270 | pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); |
271 | |
272 | pci_apply_fixup_final_quirks = true; |
273 | for_each_pci_dev(dev) { |
274 | pci_fixup_device(pci_fixup_final, dev); |
275 | /* |
276 | * If arch hasn't set it explicitly yet, use the CLS |
277 | * value shared by all PCI devices. If there's a |
278 | * mismatch, fall back to the default value. |
279 | */ |
280 | if (!pci_cache_line_size) { |
281 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, val: &tmp); |
282 | if (!cls) |
283 | cls = tmp; |
284 | if (!tmp || cls == tmp) |
285 | continue; |
286 | |
287 | pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", |
288 | cls << 2, tmp << 2, |
289 | pci_dfl_cache_line_size << 2); |
290 | pci_cache_line_size = pci_dfl_cache_line_size; |
291 | } |
292 | } |
293 | |
294 | if (!pci_cache_line_size) { |
295 | pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, |
296 | pci_dfl_cache_line_size << 2); |
297 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
298 | } |
299 | |
300 | return 0; |
301 | } |
302 | fs_initcall_sync(pci_apply_final_quirks); |
303 | |
304 | /* |
305 | * Decoding should be disabled for a PCI device during BAR sizing to avoid |
306 | * conflict. But doing so may cause problems on host bridge and perhaps other |
307 | * key system devices. For devices that need to have mmio decoding always-on, |
308 | * we need to set the dev->mmio_always_on bit. |
309 | */ |
310 | static void quirk_mmio_always_on(struct pci_dev *dev) |
311 | { |
312 | dev->mmio_always_on = 1; |
313 | } |
314 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
315 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); |
316 | |
317 | /* |
318 | * The Mellanox Tavor device gives false positive parity errors. Disable |
319 | * parity error reporting. |
320 | */ |
321 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); |
322 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); |
323 | |
324 | /* |
325 | * Deal with broken BIOSes that neglect to enable passive release, |
326 | * which can cause problems in combination with the 82441FX/PPro MTRRs |
327 | */ |
328 | static void quirk_passive_release(struct pci_dev *dev) |
329 | { |
330 | struct pci_dev *d = NULL; |
331 | unsigned char dlc; |
332 | |
333 | /* |
334 | * We have to make sure a particular bit is set in the PIIX3 |
335 | * ISA bridge, so we have to go out and find it. |
336 | */ |
337 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, from: d))) { |
338 | pci_read_config_byte(dev: d, where: 0x82, val: &dlc); |
339 | if (!(dlc & 1<<1)) { |
340 | pci_info(d, "PIIX3: Enabling Passive Release\n"); |
341 | dlc |= 1<<1; |
342 | pci_write_config_byte(dev: d, where: 0x82, val: dlc); |
343 | } |
344 | } |
345 | } |
346 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
347 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
348 | |
349 | #ifdef CONFIG_X86_32 |
350 | /* |
351 | * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a |
352 | * workaround but VIA don't answer queries. If you happen to have good |
353 | * contacts at VIA ask them for me please -- Alan |
354 | * |
355 | * This appears to be BIOS not version dependent. So presumably there is a |
356 | * chipset level fix. |
357 | */ |
358 | static void quirk_isa_dma_hangs(struct pci_dev *dev) |
359 | { |
360 | if (!isa_dma_bridge_buggy) { |
361 | isa_dma_bridge_buggy = 1; |
362 | pci_info(dev, "Activating ISA DMA hang workarounds\n"); |
363 | } |
364 | } |
365 | /* |
366 | * It's not totally clear which chipsets are the problematic ones. We know |
367 | * 82C586 and 82C596 variants are affected. |
368 | */ |
369 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
370 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); |
371 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); |
372 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); |
373 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); |
374 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); |
375 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); |
376 | #endif |
377 | |
378 | #ifdef CONFIG_HAS_IOPORT |
379 | /* |
380 | * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear |
381 | * for some HT machines to use C4 w/o hanging. |
382 | */ |
383 | static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) |
384 | { |
385 | u32 pmbase; |
386 | u16 pm1a; |
387 | |
388 | pci_read_config_dword(dev, where: 0x40, val: &pmbase); |
389 | pmbase = pmbase & 0xff80; |
390 | pm1a = inw(port: pmbase); |
391 | |
392 | if (pm1a & 0x10) { |
393 | pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); |
394 | outw(value: 0x10, port: pmbase); |
395 | } |
396 | } |
397 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); |
398 | #endif |
399 | |
400 | /* Chipsets where PCI->PCI transfers vanish or hang */ |
401 | static void quirk_nopcipci(struct pci_dev *dev) |
402 | { |
403 | if ((pci_pci_problems & PCIPCI_FAIL) == 0) { |
404 | pci_info(dev, "Disabling direct PCI/PCI transfers\n"); |
405 | pci_pci_problems |= PCIPCI_FAIL; |
406 | } |
407 | } |
408 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
409 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); |
410 | |
411 | static void quirk_nopciamd(struct pci_dev *dev) |
412 | { |
413 | u8 rev; |
414 | pci_read_config_byte(dev, where: 0x08, val: &rev); |
415 | if (rev == 0x13) { |
416 | /* Erratum 24 */ |
417 | pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
418 | pci_pci_problems |= PCIAGP_FAIL; |
419 | } |
420 | } |
421 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
422 | |
423 | /* Triton requires workarounds to be used by the drivers */ |
424 | static void quirk_triton(struct pci_dev *dev) |
425 | { |
426 | if ((pci_pci_problems&PCIPCI_TRITON) == 0) { |
427 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
428 | pci_pci_problems |= PCIPCI_TRITON; |
429 | } |
430 | } |
431 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
432 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); |
433 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); |
434 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); |
435 | |
436 | /* |
437 | * VIA Apollo KT133 needs PCI latency patch |
438 | * Made according to a Windows driver-based patch by George E. Breese; |
439 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm |
440 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on |
441 | * which Mr Breese based his work. |
442 | * |
443 | * Updated based on further information from the site and also on |
444 | * information provided by VIA |
445 | */ |
446 | static void quirk_vialatency(struct pci_dev *dev) |
447 | { |
448 | struct pci_dev *p; |
449 | u8 busarb; |
450 | |
451 | /* |
452 | * Ok, we have a potential problem chipset here. Now see if we have |
453 | * a buggy southbridge. |
454 | */ |
455 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
456 | if (p != NULL) { |
457 | |
458 | /* |
459 | * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; |
460 | * thanks Dan Hollis. |
461 | * Check for buggy part revisions |
462 | */ |
463 | if (p->revision < 0x40 || p->revision > 0x42) |
464 | goto exit; |
465 | } else { |
466 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); |
467 | if (p == NULL) /* No problem parts */ |
468 | goto exit; |
469 | |
470 | /* Check for buggy part revisions */ |
471 | if (p->revision < 0x10 || p->revision > 0x12) |
472 | goto exit; |
473 | } |
474 | |
475 | /* |
476 | * Ok we have the problem. Now set the PCI master grant to occur |
477 | * every master grant. The apparent bug is that under high PCI load |
478 | * (quite common in Linux of course) you can get data loss when the |
479 | * CPU is held off the bus for 3 bus master requests. This happens |
480 | * to include the IDE controllers.... |
481 | * |
482 | * VIA only apply this fix when an SB Live! is present but under |
483 | * both Linux and Windows this isn't enough, and we have seen |
484 | * corruption without SB Live! but with things like 3 UDMA IDE |
485 | * controllers. So we ignore that bit of the VIA recommendation.. |
486 | */ |
487 | pci_read_config_byte(dev, where: 0x76, val: &busarb); |
488 | |
489 | /* |
490 | * Set bit 4 and bit 5 of byte 76 to 0x01 |
491 | * "Master priority rotation on every PCI master grant" |
492 | */ |
493 | busarb &= ~(1<<5); |
494 | busarb |= (1<<4); |
495 | pci_write_config_byte(dev, where: 0x76, val: busarb); |
496 | pci_info(dev, "Applying VIA southbridge workaround\n"); |
497 | exit: |
498 | pci_dev_put(dev: p); |
499 | } |
500 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
501 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); |
502 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
503 | /* Must restore this on a resume from RAM */ |
504 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
505 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); |
506 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); |
507 | |
508 | /* VIA Apollo VP3 needs ETBF on BT848/878 */ |
509 | static void quirk_viaetbf(struct pci_dev *dev) |
510 | { |
511 | if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { |
512 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
513 | pci_pci_problems |= PCIPCI_VIAETBF; |
514 | } |
515 | } |
516 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
517 | |
518 | static void quirk_vsfx(struct pci_dev *dev) |
519 | { |
520 | if ((pci_pci_problems&PCIPCI_VSFX) == 0) { |
521 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
522 | pci_pci_problems |= PCIPCI_VSFX; |
523 | } |
524 | } |
525 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
526 | |
527 | /* |
528 | * ALi Magik requires workarounds to be used by the drivers that DMA to AGP |
529 | * space. Latency must be set to 0xA and Triton workaround applied too. |
530 | * [Info kindly provided by ALi] |
531 | */ |
532 | static void quirk_alimagik(struct pci_dev *dev) |
533 | { |
534 | if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { |
535 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
536 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
537 | } |
538 | } |
539 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
540 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); |
541 | |
542 | /* Natoma has some interesting boundary conditions with Zoran stuff at least */ |
543 | static void quirk_natoma(struct pci_dev *dev) |
544 | { |
545 | if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { |
546 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
547 | pci_pci_problems |= PCIPCI_NATOMA; |
548 | } |
549 | } |
550 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
551 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); |
552 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); |
553 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); |
554 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); |
555 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); |
556 | |
557 | /* |
558 | * This chip can cause PCI parity errors if config register 0xA0 is read |
559 | * while DMAs are occurring. |
560 | */ |
561 | static void quirk_citrine(struct pci_dev *dev) |
562 | { |
563 | dev->cfg_size = 0xA0; |
564 | } |
565 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
566 | |
567 | /* |
568 | * This chip can cause bus lockups if config addresses above 0x600 |
569 | * are read or written. |
570 | */ |
571 | static void quirk_nfp6000(struct pci_dev *dev) |
572 | { |
573 | dev->cfg_size = 0x600; |
574 | } |
575 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); |
576 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); |
577 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); |
578 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); |
579 | |
580 | /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ |
581 | static void quirk_extend_bar_to_page(struct pci_dev *dev) |
582 | { |
583 | int i; |
584 | |
585 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
586 | struct resource *r = &dev->resource[i]; |
587 | const char *r_name = pci_resource_name(dev, i); |
588 | |
589 | if (r->flags & IORESOURCE_MEM && resource_size(res: r) < PAGE_SIZE) { |
590 | resource_set_range(res: r, start: 0, PAGE_SIZE); |
591 | r->flags |= IORESOURCE_UNSET; |
592 | pci_info(dev, "%s %pR: expanded to page size\n", |
593 | r_name, r); |
594 | } |
595 | } |
596 | } |
597 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); |
598 | |
599 | /* |
600 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
601 | * If it's needed, re-allocate the region. |
602 | */ |
603 | static void quirk_s3_64M(struct pci_dev *dev) |
604 | { |
605 | struct resource *r = &dev->resource[0]; |
606 | |
607 | if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(res: r) != SZ_64M) { |
608 | r->flags |= IORESOURCE_UNSET; |
609 | resource_set_range(res: r, start: 0, SZ_64M); |
610 | } |
611 | } |
612 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
613 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); |
614 | |
615 | static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, |
616 | const char *name) |
617 | { |
618 | u32 region; |
619 | struct pci_bus_region bus_region; |
620 | struct resource *res = pci_resource_n(dev, pos); |
621 | const char *res_name = pci_resource_name(dev, i: pos); |
622 | |
623 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), val: ®ion); |
624 | |
625 | if (!region) |
626 | return; |
627 | |
628 | res->name = pci_name(pdev: dev); |
629 | res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; |
630 | res->flags |= |
631 | (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); |
632 | region &= ~(size - 1); |
633 | |
634 | /* Convert from PCI bus to resource space */ |
635 | bus_region.start = region; |
636 | bus_region.end = region + size - 1; |
637 | pcibios_bus_to_resource(bus: dev->bus, res, region: &bus_region); |
638 | |
639 | pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); |
640 | } |
641 | |
642 | /* |
643 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS |
644 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. |
645 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k |
646 | * (which conflicts w/ BAR1's memory range). |
647 | * |
648 | * CS553x's ISA PCI BARs may also be read-only (ref: |
649 | * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). |
650 | */ |
651 | static void quirk_cs5536_vsa(struct pci_dev *dev) |
652 | { |
653 | static char *name = "CS5536 ISA bridge"; |
654 | |
655 | if (pci_resource_len(dev, 0) != 8) { |
656 | quirk_io(dev, pos: 0, size: 8, name); /* SMB */ |
657 | quirk_io(dev, pos: 1, size: 256, name); /* GPIO */ |
658 | quirk_io(dev, pos: 2, size: 64, name); /* MFGPT */ |
659 | pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", |
660 | name); |
661 | } |
662 | } |
663 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); |
664 | |
665 | static void quirk_io_region(struct pci_dev *dev, int port, |
666 | unsigned int size, int nr, const char *name) |
667 | { |
668 | u16 region; |
669 | struct pci_bus_region bus_region; |
670 | struct resource *res = pci_resource_n(dev, nr); |
671 | |
672 | pci_read_config_word(dev, where: port, val: ®ion); |
673 | region &= ~(size - 1); |
674 | |
675 | if (!region) |
676 | return; |
677 | |
678 | res->name = pci_name(pdev: dev); |
679 | res->flags = IORESOURCE_IO; |
680 | |
681 | /* Convert from PCI bus to resource space */ |
682 | bus_region.start = region; |
683 | bus_region.end = region + size - 1; |
684 | pcibios_bus_to_resource(bus: dev->bus, res, region: &bus_region); |
685 | |
686 | /* |
687 | * "res" is typically a bridge window resource that's not being |
688 | * used for a bridge window, so it's just a place to stash this |
689 | * non-standard resource. Printing "nr" or pci_resource_name() of |
690 | * it doesn't really make sense. |
691 | */ |
692 | if (!pci_claim_resource(dev, nr)) |
693 | pci_info(dev, "quirk: %pR claimed by %s\n", res, name); |
694 | } |
695 | |
696 | /* |
697 | * ATI Northbridge setups MCE the processor if you even read somewhere |
698 | * between 0x3b0->0x3bb or read 0x3d3 |
699 | */ |
700 | static void quirk_ati_exploding_mce(struct pci_dev *dev) |
701 | { |
702 | pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
703 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
704 | request_region(0x3b0, 0x0C, "RadeonIGP"); |
705 | request_region(0x3d3, 0x01, "RadeonIGP"); |
706 | } |
707 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
708 | |
709 | /* |
710 | * In the AMD NL platform, this device ([1022:7912]) has a class code of |
711 | * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will |
712 | * claim it. The same applies on the VanGogh platform device ([1022:163a]). |
713 | * |
714 | * But the dwc3 driver is a more specific driver for this device, and we'd |
715 | * prefer to use it instead of xhci. To prevent xhci from claiming the |
716 | * device, change the class code to 0x0c03fe, which the PCI r3.0 spec |
717 | * defines as "USB device (not host controller)". The dwc3 driver can then |
718 | * claim it based on its Vendor and Device ID. |
719 | */ |
720 | static void quirk_amd_dwc_class(struct pci_dev *pdev) |
721 | { |
722 | u32 class = pdev->class; |
723 | |
724 | if (class != PCI_CLASS_SERIAL_USB_DEVICE) { |
725 | /* Use "USB Device (not host controller)" class */ |
726 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; |
727 | pci_info(pdev, |
728 | "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", |
729 | class, pdev->class); |
730 | } |
731 | } |
732 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, |
733 | quirk_amd_dwc_class); |
734 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, |
735 | quirk_amd_dwc_class); |
736 | |
737 | /* |
738 | * Synopsys USB 3.x host HAPS platform has a class code of |
739 | * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these |
740 | * devices should use dwc3-haps driver. Change these devices' class code to |
741 | * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming |
742 | * them. |
743 | */ |
744 | static void quirk_synopsys_haps(struct pci_dev *pdev) |
745 | { |
746 | u32 class = pdev->class; |
747 | |
748 | switch (pdev->device) { |
749 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: |
750 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: |
751 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: |
752 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; |
753 | pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", |
754 | class, pdev->class); |
755 | break; |
756 | } |
757 | } |
758 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, |
759 | PCI_CLASS_SERIAL_USB_XHCI, 0, |
760 | quirk_synopsys_haps); |
761 | |
762 | /* |
763 | * Let's make the southbridge information explicit instead of having to |
764 | * worry about people probing the ACPI areas, for example.. (Yes, it |
765 | * happens, and if you read the wrong ACPI register it will put the machine |
766 | * to sleep with no way of waking it up again. Bummer). |
767 | * |
768 | * ALI M7101: Two IO regions pointed to by words at |
769 | * 0xE0 (64 bytes of ACPI registers) |
770 | * 0xE2 (32 bytes of SMB registers) |
771 | */ |
772 | static void quirk_ali7101_acpi(struct pci_dev *dev) |
773 | { |
774 | quirk_io_region(dev, port: 0xE0, size: 64, nr: PCI_BRIDGE_RESOURCES, name: "ali7101 ACPI"); |
775 | quirk_io_region(dev, port: 0xE2, size: 32, nr: PCI_BRIDGE_RESOURCES+1, name: "ali7101 SMB"); |
776 | } |
777 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
778 | |
779 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
780 | { |
781 | u32 devres; |
782 | u32 mask, size, base; |
783 | |
784 | pci_read_config_dword(dev, where: port, val: &devres); |
785 | if ((devres & enable) != enable) |
786 | return; |
787 | mask = (devres >> 16) & 15; |
788 | base = devres & 0xffff; |
789 | size = 16; |
790 | for (;;) { |
791 | unsigned int bit = size >> 1; |
792 | if ((bit & mask) == bit) |
793 | break; |
794 | size = bit; |
795 | } |
796 | /* |
797 | * For now we only print it out. Eventually we'll want to |
798 | * reserve it (at least if it's in the 0x1000+ range), but |
799 | * let's get enough confirmation reports first. |
800 | */ |
801 | base &= -size; |
802 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
803 | } |
804 | |
805 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
806 | { |
807 | u32 devres; |
808 | u32 mask, size, base; |
809 | |
810 | pci_read_config_dword(dev, where: port, val: &devres); |
811 | if ((devres & enable) != enable) |
812 | return; |
813 | base = devres & 0xffff0000; |
814 | mask = (devres & 0x3f) << 16; |
815 | size = 128 << 16; |
816 | for (;;) { |
817 | unsigned int bit = size >> 1; |
818 | if ((bit & mask) == bit) |
819 | break; |
820 | size = bit; |
821 | } |
822 | |
823 | /* |
824 | * For now we only print it out. Eventually we'll want to |
825 | * reserve it, but let's get enough confirmation reports first. |
826 | */ |
827 | base &= -size; |
828 | pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
829 | } |
830 | |
831 | /* |
832 | * PIIX4 ACPI: Two IO regions pointed to by longwords at |
833 | * 0x40 (64 bytes of ACPI registers) |
834 | * 0x90 (16 bytes of SMB registers) |
835 | * and a few strange programmable PIIX4 device resources. |
836 | */ |
837 | static void quirk_piix4_acpi(struct pci_dev *dev) |
838 | { |
839 | u32 res_a; |
840 | |
841 | quirk_io_region(dev, port: 0x40, size: 64, nr: PCI_BRIDGE_RESOURCES, name: "PIIX4 ACPI"); |
842 | quirk_io_region(dev, port: 0x90, size: 16, nr: PCI_BRIDGE_RESOURCES+1, name: "PIIX4 SMB"); |
843 | |
844 | /* Device resource A has enables for some of the other ones */ |
845 | pci_read_config_dword(dev, where: 0x5c, val: &res_a); |
846 | |
847 | piix4_io_quirk(dev, name: "PIIX4 devres B", port: 0x60, enable: 3 << 21); |
848 | piix4_io_quirk(dev, name: "PIIX4 devres C", port: 0x64, enable: 3 << 21); |
849 | |
850 | /* Device resource D is just bitfields for static resources */ |
851 | |
852 | /* Device 12 enabled? */ |
853 | if (res_a & (1 << 29)) { |
854 | piix4_io_quirk(dev, name: "PIIX4 devres E", port: 0x68, enable: 1 << 20); |
855 | piix4_mem_quirk(dev, name: "PIIX4 devres F", port: 0x6c, enable: 1 << 7); |
856 | } |
857 | /* Device 13 enabled? */ |
858 | if (res_a & (1 << 30)) { |
859 | piix4_io_quirk(dev, name: "PIIX4 devres G", port: 0x70, enable: 1 << 20); |
860 | piix4_mem_quirk(dev, name: "PIIX4 devres H", port: 0x74, enable: 1 << 7); |
861 | } |
862 | piix4_io_quirk(dev, name: "PIIX4 devres I", port: 0x78, enable: 1 << 20); |
863 | piix4_io_quirk(dev, name: "PIIX4 devres J", port: 0x7c, enable: 1 << 20); |
864 | } |
865 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
866 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); |
867 | |
868 | #define ICH_PMBASE 0x40 |
869 | #define ICH_ACPI_CNTL 0x44 |
870 | #define ICH4_ACPI_EN 0x10 |
871 | #define ICH6_ACPI_EN 0x80 |
872 | #define ICH4_GPIOBASE 0x58 |
873 | #define ICH4_GPIO_CNTL 0x5c |
874 | #define ICH4_GPIO_EN 0x10 |
875 | #define ICH6_GPIOBASE 0x48 |
876 | #define ICH6_GPIO_CNTL 0x4c |
877 | #define ICH6_GPIO_EN 0x10 |
878 | |
879 | /* |
880 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at |
881 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) |
882 | * 0x58 (64 bytes of GPIO I/O space) |
883 | */ |
884 | static void quirk_ich4_lpc_acpi(struct pci_dev *dev) |
885 | { |
886 | u8 enable; |
887 | |
888 | /* |
889 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict |
890 | * with low legacy (and fixed) ports. We don't know the decoding |
891 | * priority and can't tell whether the legacy device or the one created |
892 | * here is really at that address. This happens on boards with broken |
893 | * BIOSes. |
894 | */ |
895 | pci_read_config_byte(dev, ICH_ACPI_CNTL, val: &enable); |
896 | if (enable & ICH4_ACPI_EN) |
897 | quirk_io_region(dev, ICH_PMBASE, size: 128, nr: PCI_BRIDGE_RESOURCES, |
898 | name: "ICH4 ACPI/GPIO/TCO"); |
899 | |
900 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, val: &enable); |
901 | if (enable & ICH4_GPIO_EN) |
902 | quirk_io_region(dev, ICH4_GPIOBASE, size: 64, nr: PCI_BRIDGE_RESOURCES+1, |
903 | name: "ICH4 GPIO"); |
904 | } |
905 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); |
907 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); |
908 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); |
909 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); |
910 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); |
911 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); |
912 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); |
913 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); |
914 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); |
915 | |
916 | static void ich6_lpc_acpi_gpio(struct pci_dev *dev) |
917 | { |
918 | u8 enable; |
919 | |
920 | pci_read_config_byte(dev, ICH_ACPI_CNTL, val: &enable); |
921 | if (enable & ICH6_ACPI_EN) |
922 | quirk_io_region(dev, ICH_PMBASE, size: 128, nr: PCI_BRIDGE_RESOURCES, |
923 | name: "ICH6 ACPI/GPIO/TCO"); |
924 | |
925 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, val: &enable); |
926 | if (enable & ICH6_GPIO_EN) |
927 | quirk_io_region(dev, ICH6_GPIOBASE, size: 64, nr: PCI_BRIDGE_RESOURCES+1, |
928 | name: "ICH6 GPIO"); |
929 | } |
930 | |
931 | static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, |
932 | const char *name, int dynsize) |
933 | { |
934 | u32 val; |
935 | u32 size, base; |
936 | |
937 | pci_read_config_dword(dev, where: reg, val: &val); |
938 | |
939 | /* Enabled? */ |
940 | if (!(val & 1)) |
941 | return; |
942 | base = val & 0xfffc; |
943 | if (dynsize) { |
944 | /* |
945 | * This is not correct. It is 16, 32 or 64 bytes depending on |
946 | * register D31:F0:ADh bits 5:4. |
947 | * |
948 | * But this gets us at least _part_ of it. |
949 | */ |
950 | size = 16; |
951 | } else { |
952 | size = 128; |
953 | } |
954 | base &= ~(size-1); |
955 | |
956 | /* |
957 | * Just print it out for now. We should reserve it after more |
958 | * debugging. |
959 | */ |
960 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); |
961 | } |
962 | |
963 | static void quirk_ich6_lpc(struct pci_dev *dev) |
964 | { |
965 | /* Shared ACPI/GPIO decode with all ICH6+ */ |
966 | ich6_lpc_acpi_gpio(dev); |
967 | |
968 | /* ICH6-specific generic IO decode */ |
969 | ich6_lpc_generic_decode(dev, reg: 0x84, name: "LPC Generic IO decode 1", dynsize: 0); |
970 | ich6_lpc_generic_decode(dev, reg: 0x88, name: "LPC Generic IO decode 2", dynsize: 1); |
971 | } |
972 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); |
973 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); |
974 | |
975 | static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, |
976 | const char *name) |
977 | { |
978 | u32 val; |
979 | u32 mask, base; |
980 | |
981 | pci_read_config_dword(dev, where: reg, val: &val); |
982 | |
983 | /* Enabled? */ |
984 | if (!(val & 1)) |
985 | return; |
986 | |
987 | /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ |
988 | base = val & 0xfffc; |
989 | mask = (val >> 16) & 0xfc; |
990 | mask |= 3; |
991 | |
992 | /* |
993 | * Just print it out for now. We should reserve it after more |
994 | * debugging. |
995 | */ |
996 | pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); |
997 | } |
998 | |
999 | /* ICH7-10 has the same common LPC generic IO decode registers */ |
1000 | static void quirk_ich7_lpc(struct pci_dev *dev) |
1001 | { |
1002 | /* We share the common ACPI/GPIO decode with ICH6 */ |
1003 | ich6_lpc_acpi_gpio(dev); |
1004 | |
1005 | /* And have 4 ICH7+ generic decodes */ |
1006 | ich7_lpc_generic_decode(dev, reg: 0x84, name: "ICH7 LPC Generic IO decode 1"); |
1007 | ich7_lpc_generic_decode(dev, reg: 0x88, name: "ICH7 LPC Generic IO decode 2"); |
1008 | ich7_lpc_generic_decode(dev, reg: 0x8c, name: "ICH7 LPC Generic IO decode 3"); |
1009 | ich7_lpc_generic_decode(dev, reg: 0x90, name: "ICH7 LPC Generic IO decode 4"); |
1010 | } |
1011 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); |
1012 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); |
1013 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); |
1014 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); |
1015 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); |
1016 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); |
1017 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); |
1018 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); |
1019 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); |
1020 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); |
1021 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); |
1022 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); |
1023 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); |
1024 | |
1025 | /* |
1026 | * VIA ACPI: One IO region pointed to by longword at |
1027 | * 0x48 or 0x20 (256 bytes of ACPI registers) |
1028 | */ |
1029 | static void quirk_vt82c586_acpi(struct pci_dev *dev) |
1030 | { |
1031 | if (dev->revision & 0x10) |
1032 | quirk_io_region(dev, port: 0x48, size: 256, nr: PCI_BRIDGE_RESOURCES, |
1033 | name: "vt82c586 ACPI"); |
1034 | } |
1035 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1036 | |
1037 | /* |
1038 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at |
1039 | * 0x48 (256 bytes of ACPI registers) |
1040 | * 0x70 (128 bytes of hardware monitoring register) |
1041 | * 0x90 (16 bytes of SMB registers) |
1042 | */ |
1043 | static void quirk_vt82c686_acpi(struct pci_dev *dev) |
1044 | { |
1045 | quirk_vt82c586_acpi(dev); |
1046 | |
1047 | quirk_io_region(dev, port: 0x70, size: 128, nr: PCI_BRIDGE_RESOURCES+1, |
1048 | name: "vt82c686 HW-mon"); |
1049 | |
1050 | quirk_io_region(dev, port: 0x90, size: 16, nr: PCI_BRIDGE_RESOURCES+2, name: "vt82c686 SMB"); |
1051 | } |
1052 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1053 | |
1054 | /* |
1055 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at |
1056 | * 0x88 (128 bytes of power management registers) |
1057 | * 0xd0 (16 bytes of SMB registers) |
1058 | */ |
1059 | static void quirk_vt8235_acpi(struct pci_dev *dev) |
1060 | { |
1061 | quirk_io_region(dev, port: 0x88, size: 128, nr: PCI_BRIDGE_RESOURCES, name: "vt8235 PM"); |
1062 | quirk_io_region(dev, port: 0xd0, size: 16, nr: PCI_BRIDGE_RESOURCES+1, name: "vt8235 SMB"); |
1063 | } |
1064 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); |
1065 | |
1066 | /* |
1067 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast |
1068 | * back-to-back: Disable fast back-to-back on the secondary bus segment |
1069 | */ |
1070 | static void quirk_xio2000a(struct pci_dev *dev) |
1071 | { |
1072 | struct pci_dev *pdev; |
1073 | u16 command; |
1074 | |
1075 | pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); |
1076 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { |
1077 | pci_read_config_word(dev: pdev, PCI_COMMAND, val: &command); |
1078 | if (command & PCI_COMMAND_FAST_BACK) |
1079 | pci_write_config_word(dev: pdev, PCI_COMMAND, val: command & ~PCI_COMMAND_FAST_BACK); |
1080 | } |
1081 | } |
1082 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, |
1083 | quirk_xio2000a); |
1084 | |
1085 | #ifdef CONFIG_X86_IO_APIC |
1086 | |
1087 | #include <asm/io_apic.h> |
1088 | |
1089 | /* |
1090 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip |
1091 | * devices to the external APIC. |
1092 | * |
1093 | * TODO: When we have device-specific interrupt routers, this code will go |
1094 | * away from quirks. |
1095 | */ |
1096 | static void quirk_via_ioapic(struct pci_dev *dev) |
1097 | { |
1098 | u8 tmp; |
1099 | |
1100 | if (nr_ioapics < 1) |
1101 | tmp = 0; /* nothing routed to external APIC */ |
1102 | else |
1103 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ |
1104 | |
1105 | pci_info(dev, "%s VIA external APIC routing\n", |
1106 | tmp ? "Enabling": "Disabling"); |
1107 | |
1108 | /* Offset 0x58: External APIC IRQ output control */ |
1109 | pci_write_config_byte(dev, where: 0x58, val: tmp); |
1110 | } |
1111 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1112 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1113 | |
1114 | /* |
1115 | * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. |
1116 | * This leads to doubled level interrupt rates. |
1117 | * Set this bit to get rid of cycle wastage. |
1118 | * Otherwise uncritical. |
1119 | */ |
1120 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
1121 | { |
1122 | u8 misc_control2; |
1123 | #define BYPASS_APIC_DEASSERT 8 |
1124 | |
1125 | pci_read_config_byte(dev, where: 0x5B, val: &misc_control2); |
1126 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { |
1127 | pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
1128 | pci_write_config_byte(dev, where: 0x5B, val: misc_control2|BYPASS_APIC_DEASSERT); |
1129 | } |
1130 | } |
1131 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
1132 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
1133 | |
1134 | /* |
1135 | * The AMD IO-APIC can hang the box when an APIC IRQ is masked. |
1136 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
1137 | * is currently marked NoFix |
1138 | * |
1139 | * We have multiple reports of hangs with this chipset that went away with |
1140 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1141 | * of course. However the advice is demonstrably good even if so. |
1142 | */ |
1143 | static void quirk_amd_ioapic(struct pci_dev *dev) |
1144 | { |
1145 | if (dev->revision >= 0x02) { |
1146 | pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
1147 | pci_warn(dev, " : booting with the \"noapic\" option\n"); |
1148 | } |
1149 | } |
1150 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1151 | #endif /* CONFIG_X86_IO_APIC */ |
1152 | |
1153 | #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) |
1154 | |
1155 | static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) |
1156 | { |
1157 | /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ |
1158 | if (dev->subsystem_device == 0xa118) |
1159 | dev->sriov->link = dev->devfn; |
1160 | } |
1161 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); |
1162 | #endif |
1163 | |
1164 | /* |
1165 | * Some settings of MMRBC can lead to data corruption so block changes. |
1166 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide |
1167 | */ |
1168 | static void quirk_amd_8131_mmrbc(struct pci_dev *dev) |
1169 | { |
1170 | if (dev->subordinate && dev->revision <= 0x12) { |
1171 | pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", |
1172 | dev->revision); |
1173 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
1174 | } |
1175 | } |
1176 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); |
1177 | |
1178 | /* |
1179 | * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up |
1180 | * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register |
1181 | * at all. Therefore it seems like setting the pci_dev's IRQ to the value |
1182 | * of the ACPI SCI interrupt is only done for convenience. |
1183 | * -jgarzik |
1184 | */ |
1185 | static void quirk_via_acpi(struct pci_dev *d) |
1186 | { |
1187 | u8 irq; |
1188 | |
1189 | /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ |
1190 | pci_read_config_byte(dev: d, where: 0x42, val: &irq); |
1191 | irq &= 0xf; |
1192 | if (irq && (irq != 2)) |
1193 | d->irq = irq; |
1194 | } |
1195 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
1196 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); |
1197 | |
1198 | /* VIA bridges which have VLink */ |
1199 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
1200 | |
1201 | static void quirk_via_bridge(struct pci_dev *dev) |
1202 | { |
1203 | /* See what bridge we have and find the device ranges */ |
1204 | switch (dev->device) { |
1205 | case PCI_DEVICE_ID_VIA_82C686: |
1206 | /* |
1207 | * The VT82C686 is special; it attaches to PCI and can have |
1208 | * any device number. All its subdevices are functions of |
1209 | * that single device. |
1210 | */ |
1211 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); |
1212 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); |
1213 | break; |
1214 | case PCI_DEVICE_ID_VIA_8237: |
1215 | case PCI_DEVICE_ID_VIA_8237A: |
1216 | via_vlink_dev_lo = 15; |
1217 | break; |
1218 | case PCI_DEVICE_ID_VIA_8235: |
1219 | via_vlink_dev_lo = 16; |
1220 | break; |
1221 | case PCI_DEVICE_ID_VIA_8231: |
1222 | case PCI_DEVICE_ID_VIA_8233_0: |
1223 | case PCI_DEVICE_ID_VIA_8233A: |
1224 | case PCI_DEVICE_ID_VIA_8233C_0: |
1225 | via_vlink_dev_lo = 17; |
1226 | break; |
1227 | } |
1228 | } |
1229 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); |
1230 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); |
1231 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); |
1232 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); |
1233 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); |
1234 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); |
1235 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); |
1236 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); |
1237 | |
1238 | /* |
1239 | * quirk_via_vlink - VIA VLink IRQ number update |
1240 | * @dev: PCI device |
1241 | * |
1242 | * If the device we are dealing with is on a PIC IRQ we need to ensure that |
1243 | * the IRQ line register which usually is not relevant for PCI cards, is |
1244 | * actually written so that interrupts get sent to the right place. |
1245 | * |
1246 | * We only do this on systems where a VIA south bridge was detected, and |
1247 | * only for VIA devices on the motherboard (see quirk_via_bridge above). |
1248 | */ |
1249 | static void quirk_via_vlink(struct pci_dev *dev) |
1250 | { |
1251 | u8 irq, new_irq; |
1252 | |
1253 | /* Check if we have VLink at all */ |
1254 | if (via_vlink_dev_lo == -1) |
1255 | return; |
1256 | |
1257 | new_irq = dev->irq; |
1258 | |
1259 | /* Don't quirk interrupts outside the legacy IRQ range */ |
1260 | if (!new_irq || new_irq > 15) |
1261 | return; |
1262 | |
1263 | /* Internal device ? */ |
1264 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
1265 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) |
1266 | return; |
1267 | |
1268 | /* |
1269 | * This is an internal VLink device on a PIC interrupt. The BIOS |
1270 | * ought to have set this but may not have, so we redo it. |
1271 | */ |
1272 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, val: &irq); |
1273 | if (new_irq != irq) { |
1274 | pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", |
1275 | irq, new_irq); |
1276 | udelay(usec: 15); /* unknown if delay really needed */ |
1277 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, val: new_irq); |
1278 | } |
1279 | } |
1280 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
1281 | |
1282 | /* |
1283 | * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID |
1284 | * of VT82C597 for backward compatibility. We need to switch it off to be |
1285 | * able to recognize the real type of the chip. |
1286 | */ |
1287 | static void quirk_vt82c598_id(struct pci_dev *dev) |
1288 | { |
1289 | pci_write_config_byte(dev, where: 0xfc, val: 0); |
1290 | pci_read_config_word(dev, PCI_DEVICE_ID, val: &dev->device); |
1291 | } |
1292 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1293 | |
1294 | /* |
1295 | * CardBus controllers have a legacy base address that enables them to |
1296 | * respond as i82365 pcmcia controllers. We don't want them to do this |
1297 | * even if the Linux CardBus driver is not loaded, because the Linux i82365 |
1298 | * driver does not (and should not) handle CardBus. |
1299 | */ |
1300 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1301 | { |
1302 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, val: 0); |
1303 | } |
1304 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
1305 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); |
1306 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
1307 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); |
1308 | |
1309 | /* |
1310 | * Following the PCI ordering rules is optional on the AMD762. I'm not sure |
1311 | * what the designers were smoking but let's not inhale... |
1312 | * |
1313 | * To be fair to AMD, it follows the spec by default, it's BIOS people who |
1314 | * turn it off! |
1315 | */ |
1316 | static void quirk_amd_ordering(struct pci_dev *dev) |
1317 | { |
1318 | u32 pcic; |
1319 | pci_read_config_dword(dev, where: 0x4C, val: &pcic); |
1320 | if ((pcic & 6) != 6) { |
1321 | pcic |= 6; |
1322 | pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1323 | pci_write_config_dword(dev, where: 0x4C, val: pcic); |
1324 | pci_read_config_dword(dev, where: 0x84, val: &pcic); |
1325 | pcic |= (1 << 23); /* Required in this mode */ |
1326 | pci_write_config_dword(dev, where: 0x84, val: pcic); |
1327 | } |
1328 | } |
1329 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1330 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1331 | |
1332 | /* |
1333 | * DreamWorks-provided workaround for Dunord I-3000 problem |
1334 | * |
1335 | * This card decodes and responds to addresses not apparently assigned to |
1336 | * it. We force a larger allocation to ensure that nothing gets put too |
1337 | * close to it. |
1338 | */ |
1339 | static void quirk_dunord(struct pci_dev *dev) |
1340 | { |
1341 | struct resource *r = &dev->resource[1]; |
1342 | |
1343 | r->flags |= IORESOURCE_UNSET; |
1344 | resource_set_range(res: r, start: 0, SZ_16M); |
1345 | } |
1346 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1347 | |
1348 | /* |
1349 | * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive |
1350 | * decoding (transparent), and does indicate this in the ProgIf. |
1351 | * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. |
1352 | */ |
1353 | static void quirk_transparent_bridge(struct pci_dev *dev) |
1354 | { |
1355 | dev->transparent = 1; |
1356 | } |
1357 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
1358 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); |
1359 | |
1360 | /* |
1361 | * Common misconfiguration of the MediaGX/Geode PCI master that will reduce |
1362 | * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets |
1363 | * found at http://www.national.com/analog for info on what these bits do. |
1364 | * <christer@weinigel.se> |
1365 | */ |
1366 | static void quirk_mediagx_master(struct pci_dev *dev) |
1367 | { |
1368 | u8 reg; |
1369 | |
1370 | pci_read_config_byte(dev, where: 0x41, val: ®); |
1371 | if (reg & 2) { |
1372 | reg &= ~2; |
1373 | pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", |
1374 | reg); |
1375 | pci_write_config_byte(dev, where: 0x41, val: reg); |
1376 | } |
1377 | } |
1378 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1379 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1380 | |
1381 | /* |
1382 | * Ensure C0 rev restreaming is off. This is normally done by the BIOS but |
1383 | * in the odd case it is not the results are corruption hence the presence |
1384 | * of a Linux check. |
1385 | */ |
1386 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1387 | { |
1388 | u16 config; |
1389 | |
1390 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1391 | return; |
1392 | pci_read_config_word(dev: pdev, where: 0x40, val: &config); |
1393 | if (config & (1<<6)) { |
1394 | config &= ~(1<<6); |
1395 | pci_write_config_word(dev: pdev, where: 0x40, val: config); |
1396 | pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1397 | } |
1398 | } |
1399 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1400 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1401 | |
1402 | static void quirk_amd_ide_mode(struct pci_dev *pdev) |
1403 | { |
1404 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
1405 | u8 tmp; |
1406 | |
1407 | pci_read_config_byte(dev: pdev, PCI_CLASS_DEVICE, val: &tmp); |
1408 | if (tmp == 0x01) { |
1409 | pci_read_config_byte(dev: pdev, where: 0x40, val: &tmp); |
1410 | pci_write_config_byte(dev: pdev, where: 0x40, val: tmp|1); |
1411 | pci_write_config_byte(dev: pdev, where: 0x9, val: 1); |
1412 | pci_write_config_byte(dev: pdev, where: 0xa, val: 6); |
1413 | pci_write_config_byte(dev: pdev, where: 0x40, val: tmp); |
1414 | |
1415 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
1416 | pci_info(pdev, "set SATA to AHCI mode\n"); |
1417 | } |
1418 | } |
1419 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
1420 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
1421 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
1422 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
1423 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1424 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1425 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
1426 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
1427 | |
1428 | /* Serverworks CSB5 IDE does not fully support native mode */ |
1429 | static void quirk_svwks_csb5ide(struct pci_dev *pdev) |
1430 | { |
1431 | u8 prog; |
1432 | pci_read_config_byte(dev: pdev, PCI_CLASS_PROG, val: &prog); |
1433 | if (prog & 5) { |
1434 | prog &= ~5; |
1435 | pdev->class &= ~5; |
1436 | pci_write_config_byte(dev: pdev, PCI_CLASS_PROG, val: prog); |
1437 | /* PCI layer will sort out resources */ |
1438 | } |
1439 | } |
1440 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1441 | |
1442 | /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ |
1443 | static void quirk_ide_samemode(struct pci_dev *pdev) |
1444 | { |
1445 | u8 prog; |
1446 | |
1447 | pci_read_config_byte(dev: pdev, PCI_CLASS_PROG, val: &prog); |
1448 | |
1449 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { |
1450 | pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); |
1451 | prog &= ~5; |
1452 | pdev->class &= ~5; |
1453 | pci_write_config_byte(dev: pdev, PCI_CLASS_PROG, val: prog); |
1454 | } |
1455 | } |
1456 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1457 | |
1458 | /* Some ATA devices break if put into D3 */ |
1459 | static void quirk_no_ata_d3(struct pci_dev *pdev) |
1460 | { |
1461 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; |
1462 | } |
1463 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ |
1464 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, |
1465 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
1466 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
1467 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
1468 | /* ALi loses some register settings that we cannot then restore */ |
1469 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, |
1470 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
1471 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures |
1472 | occur when mode detecting */ |
1473 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
1474 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); |
1475 | |
1476 | /* |
1477 | * This was originally an Alpha-specific thing, but it really fits here. |
1478 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
1479 | */ |
1480 | static void quirk_eisa_bridge(struct pci_dev *dev) |
1481 | { |
1482 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; |
1483 | } |
1484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1485 | |
1486 | /* |
1487 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge |
1488 | * is not activated. The myth is that Asus said that they do not want the |
1489 | * users to be irritated by just another PCI Device in the Win98 device |
1490 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
1491 | * package 2.7.0 for details) |
1492 | * |
1493 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
1494 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it |
1495 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1496 | * is either the Host bridge (preferred) or on-board VGA controller. |
1497 | * |
1498 | * Note that we used to unhide the SMBus that way on Toshiba laptops |
1499 | * (Satellite A40 and Tecra M2) but then found that the thermal management |
1500 | * was done by SMM code, which could cause unsynchronized concurrent |
1501 | * accesses to the SMBus registers, with potentially bad effects. Thus you |
1502 | * should be very careful when adding new entries: if SMM is accessing the |
1503 | * Intel SMBus, this is a very good reason to leave it hidden. |
1504 | * |
1505 | * Likewise, many recent laptops use ACPI for thermal management. If the |
1506 | * ACPI DSDT code accesses the SMBus, then Linux should not access it |
1507 | * natively, and keeping the SMBus hidden is the right thing to do. If you |
1508 | * are about to add an entry in the table below, please first disassemble |
1509 | * the DSDT and double-check that there is no code accessing the SMBus. |
1510 | */ |
1511 | static int asus_hides_smbus; |
1512 | |
1513 | static void asus_hides_smbus_hostbridge(struct pci_dev *dev) |
1514 | { |
1515 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
1516 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) |
1517 | switch (dev->subsystem_device) { |
1518 | case 0x8025: /* P4B-LX */ |
1519 | case 0x8070: /* P4B */ |
1520 | case 0x8088: /* P4B533 */ |
1521 | case 0x1626: /* L3C notebook */ |
1522 | asus_hides_smbus = 1; |
1523 | } |
1524 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1525 | switch (dev->subsystem_device) { |
1526 | case 0x80b1: /* P4GE-V */ |
1527 | case 0x80b2: /* P4PE */ |
1528 | case 0x8093: /* P4B533-V */ |
1529 | asus_hides_smbus = 1; |
1530 | } |
1531 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1532 | switch (dev->subsystem_device) { |
1533 | case 0x8030: /* P4T533 */ |
1534 | asus_hides_smbus = 1; |
1535 | } |
1536 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1537 | switch (dev->subsystem_device) { |
1538 | case 0x8070: /* P4G8X Deluxe */ |
1539 | asus_hides_smbus = 1; |
1540 | } |
1541 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
1542 | switch (dev->subsystem_device) { |
1543 | case 0x80c9: /* PU-DLS */ |
1544 | asus_hides_smbus = 1; |
1545 | } |
1546 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1547 | switch (dev->subsystem_device) { |
1548 | case 0x1751: /* M2N notebook */ |
1549 | case 0x1821: /* M5N notebook */ |
1550 | case 0x1897: /* A6L notebook */ |
1551 | asus_hides_smbus = 1; |
1552 | } |
1553 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1554 | switch (dev->subsystem_device) { |
1555 | case 0x184b: /* W1N notebook */ |
1556 | case 0x186a: /* M6Ne notebook */ |
1557 | asus_hides_smbus = 1; |
1558 | } |
1559 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1560 | switch (dev->subsystem_device) { |
1561 | case 0x80f2: /* P4P800-X */ |
1562 | asus_hides_smbus = 1; |
1563 | } |
1564 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
1565 | switch (dev->subsystem_device) { |
1566 | case 0x1882: /* M6V notebook */ |
1567 | case 0x1977: /* A6VA notebook */ |
1568 | asus_hides_smbus = 1; |
1569 | } |
1570 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1571 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1572 | switch (dev->subsystem_device) { |
1573 | case 0x088C: /* HP Compaq nc8000 */ |
1574 | case 0x0890: /* HP Compaq nc6000 */ |
1575 | asus_hides_smbus = 1; |
1576 | } |
1577 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1578 | switch (dev->subsystem_device) { |
1579 | case 0x12bc: /* HP D330L */ |
1580 | case 0x12bd: /* HP D530 */ |
1581 | case 0x006a: /* HP Compaq nx9500 */ |
1582 | asus_hides_smbus = 1; |
1583 | } |
1584 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1585 | switch (dev->subsystem_device) { |
1586 | case 0x12bf: /* HP xw4100 */ |
1587 | asus_hides_smbus = 1; |
1588 | } |
1589 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1590 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1591 | switch (dev->subsystem_device) { |
1592 | case 0xC00C: /* Samsung P35 notebook */ |
1593 | asus_hides_smbus = 1; |
1594 | } |
1595 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1596 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1597 | switch (dev->subsystem_device) { |
1598 | case 0x0058: /* Compaq Evo N620c */ |
1599 | asus_hides_smbus = 1; |
1600 | } |
1601 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
1602 | switch (dev->subsystem_device) { |
1603 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
1604 | /* Motherboard doesn't have Host bridge |
1605 | * subvendor/subdevice IDs, therefore checking |
1606 | * its on-board VGA controller */ |
1607 | asus_hides_smbus = 1; |
1608 | } |
1609 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
1610 | switch (dev->subsystem_device) { |
1611 | case 0x00b8: /* Compaq Evo D510 CMT */ |
1612 | case 0x00b9: /* Compaq Evo D510 SFF */ |
1613 | case 0x00ba: /* Compaq Evo D510 USDT */ |
1614 | /* Motherboard doesn't have Host bridge |
1615 | * subvendor/subdevice IDs and on-board VGA |
1616 | * controller is disabled if an AGP card is |
1617 | * inserted, therefore checking USB UHCI |
1618 | * Controller #1 */ |
1619 | asus_hides_smbus = 1; |
1620 | } |
1621 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1622 | switch (dev->subsystem_device) { |
1623 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ |
1624 | /* Motherboard doesn't have host bridge |
1625 | * subvendor/subdevice IDs, therefore checking |
1626 | * its on-board VGA controller */ |
1627 | asus_hides_smbus = 1; |
1628 | } |
1629 | } |
1630 | } |
1631 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1632 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); |
1633 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); |
1634 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); |
1635 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
1636 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1637 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); |
1638 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); |
1639 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); |
1640 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); |
1641 | |
1642 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); |
1643 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
1644 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
1645 | |
1646 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1647 | { |
1648 | u16 val; |
1649 | |
1650 | if (likely(!asus_hides_smbus)) |
1651 | return; |
1652 | |
1653 | pci_read_config_word(dev, where: 0xF2, val: &val); |
1654 | if (val & 0x8) { |
1655 | pci_write_config_word(dev, where: 0xF2, val: val & (~0x8)); |
1656 | pci_read_config_word(dev, where: 0xF2, val: &val); |
1657 | if (val & 0x8) |
1658 | pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", |
1659 | val); |
1660 | else |
1661 | pci_info(dev, "Enabled i801 SMBus device\n"); |
1662 | } |
1663 | } |
1664 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1665 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); |
1666 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); |
1667 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); |
1668 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); |
1669 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); |
1670 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
1671 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1672 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); |
1673 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); |
1674 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); |
1675 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); |
1676 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); |
1677 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); |
1678 | |
1679 | /* It appears we just have one such device. If not, we have a warning */ |
1680 | static void __iomem *asus_rcba_base; |
1681 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) |
1682 | { |
1683 | u32 rcba; |
1684 | |
1685 | if (likely(!asus_hides_smbus)) |
1686 | return; |
1687 | WARN_ON(asus_rcba_base); |
1688 | |
1689 | pci_read_config_dword(dev, where: 0xF0, val: &rcba); |
1690 | /* use bits 31:14, 16 kB aligned */ |
1691 | asus_rcba_base = ioremap(offset: rcba & 0xFFFFC000, size: 0x4000); |
1692 | if (asus_rcba_base == NULL) |
1693 | return; |
1694 | } |
1695 | |
1696 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) |
1697 | { |
1698 | u32 val; |
1699 | |
1700 | if (likely(!asus_hides_smbus || !asus_rcba_base)) |
1701 | return; |
1702 | |
1703 | /* read the Function Disable register, dword mode only */ |
1704 | val = readl(addr: asus_rcba_base + 0x3418); |
1705 | |
1706 | /* enable the SMBus device */ |
1707 | writel(val: val & 0xFFFFFFF7, addr: asus_rcba_base + 0x3418); |
1708 | } |
1709 | |
1710 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) |
1711 | { |
1712 | if (likely(!asus_hides_smbus || !asus_rcba_base)) |
1713 | return; |
1714 | |
1715 | iounmap(addr: asus_rcba_base); |
1716 | asus_rcba_base = NULL; |
1717 | pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); |
1718 | } |
1719 | |
1720 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) |
1721 | { |
1722 | asus_hides_smbus_lpc_ich6_suspend(dev); |
1723 | asus_hides_smbus_lpc_ich6_resume_early(dev); |
1724 | asus_hides_smbus_lpc_ich6_resume(dev); |
1725 | } |
1726 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
1727 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1728 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); |
1729 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); |
1730 | |
1731 | /* SiS 96x south bridge: BIOS typically hides SMBus device... */ |
1732 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1733 | { |
1734 | u8 val = 0; |
1735 | pci_read_config_byte(dev, where: 0x77, val: &val); |
1736 | if (val & 0x10) { |
1737 | pci_info(dev, "Enabling SiS 96x SMBus\n"); |
1738 | pci_write_config_byte(dev, where: 0x77, val: val & ~0x10); |
1739 | } |
1740 | } |
1741 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1742 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); |
1743 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); |
1744 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
1745 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1746 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); |
1747 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); |
1748 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); |
1749 | |
1750 | /* |
1751 | * ... This is further complicated by the fact that some SiS96x south |
1752 | * bridges pretend to be 85C503/5513 instead. In that case see if we |
1753 | * spotted a compatible north bridge to make sure. |
1754 | * (pci_find_device() doesn't work yet) |
1755 | * |
1756 | * We can also enable the sis96x bit in the discovery register.. |
1757 | */ |
1758 | #define SIS_DETECT_REGISTER 0x40 |
1759 | |
1760 | static void quirk_sis_503(struct pci_dev *dev) |
1761 | { |
1762 | u8 reg; |
1763 | u16 devid; |
1764 | |
1765 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, val: ®); |
1766 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, val: reg | (1 << 6)); |
1767 | pci_read_config_word(dev, PCI_DEVICE_ID, val: &devid); |
1768 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { |
1769 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, val: reg); |
1770 | return; |
1771 | } |
1772 | |
1773 | /* |
1774 | * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case |
1775 | * it has already been processed. (Depends on link order, which is |
1776 | * apparently not guaranteed) |
1777 | */ |
1778 | dev->device = devid; |
1779 | quirk_sis_96x_smbus(dev); |
1780 | } |
1781 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1782 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1783 | |
1784 | /* |
1785 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller |
1786 | * and MC97 modem controller are disabled when a second PCI soundcard is |
1787 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. |
1788 | * -- bjd |
1789 | */ |
1790 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
1791 | { |
1792 | u8 val; |
1793 | int asus_hides_ac97 = 0; |
1794 | |
1795 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { |
1796 | if (dev->device == PCI_DEVICE_ID_VIA_8237) |
1797 | asus_hides_ac97 = 1; |
1798 | } |
1799 | |
1800 | if (!asus_hides_ac97) |
1801 | return; |
1802 | |
1803 | pci_read_config_byte(dev, where: 0x50, val: &val); |
1804 | if (val & 0xc0) { |
1805 | pci_write_config_byte(dev, where: 0x50, val: val & (~0xc0)); |
1806 | pci_read_config_byte(dev, where: 0x50, val: &val); |
1807 | if (val & 0xc0) |
1808 | pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", |
1809 | val); |
1810 | else |
1811 | pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); |
1812 | } |
1813 | } |
1814 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1815 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1816 | |
1817 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
1818 | |
1819 | /* |
1820 | * If we are using libata we can drive this chip properly but must do this |
1821 | * early on to make the additional device appear during the PCI scanning. |
1822 | */ |
1823 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
1824 | { |
1825 | u32 conf1, conf5, class; |
1826 | u8 hdr; |
1827 | |
1828 | /* Only poke fn 0 */ |
1829 | if (PCI_FUNC(pdev->devfn)) |
1830 | return; |
1831 | |
1832 | pci_read_config_dword(dev: pdev, where: 0x40, val: &conf1); |
1833 | pci_read_config_dword(dev: pdev, where: 0x80, val: &conf5); |
1834 | |
1835 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1836 | conf5 &= ~(1 << 24); /* Clear bit 24 */ |
1837 | |
1838 | switch (pdev->device) { |
1839 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1840 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ |
1841 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
1842 | /* The controller should be in single function ahci mode */ |
1843 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ |
1844 | break; |
1845 | |
1846 | case PCI_DEVICE_ID_JMICRON_JMB365: |
1847 | case PCI_DEVICE_ID_JMICRON_JMB366: |
1848 | /* Redirect IDE second PATA port to the right spot */ |
1849 | conf5 |= (1 << 24); |
1850 | fallthrough; |
1851 | case PCI_DEVICE_ID_JMICRON_JMB361: |
1852 | case PCI_DEVICE_ID_JMICRON_JMB363: |
1853 | case PCI_DEVICE_ID_JMICRON_JMB369: |
1854 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
1855 | /* Set the class codes correctly and then direct IDE 0 */ |
1856 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
1857 | break; |
1858 | |
1859 | case PCI_DEVICE_ID_JMICRON_JMB368: |
1860 | /* The controller should be in single function IDE mode */ |
1861 | conf1 |= 0x00C00000; /* Set 22, 23 */ |
1862 | break; |
1863 | } |
1864 | |
1865 | pci_write_config_dword(dev: pdev, where: 0x40, val: conf1); |
1866 | pci_write_config_dword(dev: pdev, where: 0x80, val: conf5); |
1867 | |
1868 | /* Update pdev accordingly */ |
1869 | pci_read_config_byte(dev: pdev, PCI_HEADER_TYPE, val: &hdr); |
1870 | pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; |
1871 | pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); |
1872 | |
1873 | pci_read_config_dword(dev: pdev, PCI_CLASS_REVISION, val: &class); |
1874 | pdev->class = class >> 8; |
1875 | } |
1876 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1877 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
1878 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
1879 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
1880 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
1881 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1882 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
1883 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
1884 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
1885 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1886 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); |
1887 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
1888 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
1889 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
1890 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1891 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); |
1892 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); |
1893 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
1894 | |
1895 | #endif |
1896 | |
1897 | static void quirk_jmicron_async_suspend(struct pci_dev *dev) |
1898 | { |
1899 | if (dev->multifunction) { |
1900 | device_disable_async_suspend(dev: &dev->dev); |
1901 | pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); |
1902 | } |
1903 | } |
1904 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); |
1905 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); |
1906 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); |
1907 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); |
1908 | |
1909 | #ifdef CONFIG_X86_IO_APIC |
1910 | static void quirk_alder_ioapic(struct pci_dev *pdev) |
1911 | { |
1912 | int i; |
1913 | |
1914 | if ((pdev->class >> 8) != 0xff00) |
1915 | return; |
1916 | |
1917 | /* |
1918 | * The first BAR is the location of the IO-APIC... we must |
1919 | * not touch this (and it's already covered by the fixmap), so |
1920 | * forcibly insert it into the resource tree. |
1921 | */ |
1922 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
1923 | insert_resource(parent: &iomem_resource, new: &pdev->resource[0]); |
1924 | |
1925 | /* |
1926 | * The next five BARs all seem to be rubbish, so just clean |
1927 | * them out. |
1928 | */ |
1929 | for (i = 1; i < PCI_STD_NUM_BARS; i++) |
1930 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
1931 | } |
1932 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1933 | #endif |
1934 | |
1935 | static void quirk_no_msi(struct pci_dev *dev) |
1936 | { |
1937 | pci_info(dev, "avoiding MSI to work around a hardware defect\n"); |
1938 | dev->no_msi = 1; |
1939 | } |
1940 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); |
1941 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); |
1942 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); |
1943 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); |
1944 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); |
1945 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); |
1946 | |
1947 | static void quirk_pcie_mch(struct pci_dev *pdev) |
1948 | { |
1949 | pdev->no_msi = 1; |
1950 | } |
1951 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1952 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); |
1953 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); |
1954 | |
1955 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); |
1956 | |
1957 | /* |
1958 | * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are |
1959 | * actually on the AMBA bus. These fake PCI devices can support SVA via |
1960 | * SMMU stall feature, by setting dma-can-stall for ACPI platforms. |
1961 | * |
1962 | * Normally stalling must not be enabled for PCI devices, since it would |
1963 | * break the PCI requirement for free-flowing writes and may lead to |
1964 | * deadlock. We expect PCI devices to support ATS and PRI if they want to |
1965 | * be fault-tolerant, so there's no ACPI binding to describe anything else, |
1966 | * even when a "PCI" device turns out to be a regular old SoC device |
1967 | * dressed up as a RCiEP and normal rules don't apply. |
1968 | */ |
1969 | static void quirk_huawei_pcie_sva(struct pci_dev *pdev) |
1970 | { |
1971 | struct property_entry properties[] = { |
1972 | PROPERTY_ENTRY_BOOL("dma-can-stall"), |
1973 | {}, |
1974 | }; |
1975 | |
1976 | if (pdev->revision != 0x21 && pdev->revision != 0x30) |
1977 | return; |
1978 | |
1979 | pdev->pasid_no_tlp = 1; |
1980 | |
1981 | /* |
1982 | * Set the dma-can-stall property on ACPI platforms. Device tree |
1983 | * can set it directly. |
1984 | */ |
1985 | if (!pdev->dev.of_node && |
1986 | device_create_managed_software_node(dev: &pdev->dev, properties, NULL)) |
1987 | pci_warn(pdev, "could not add stall property"); |
1988 | } |
1989 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); |
1990 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); |
1991 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); |
1992 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); |
1993 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); |
1994 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); |
1995 | |
1996 | /* |
1997 | * It's possible for the MSI to get corrupted if SHPC and ACPI are used |
1998 | * together on certain PXH-based systems. |
1999 | */ |
2000 | static void quirk_pcie_pxh(struct pci_dev *dev) |
2001 | { |
2002 | dev->no_msi = 1; |
2003 | pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
2004 | } |
2005 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); |
2006 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); |
2007 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); |
2008 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); |
2009 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); |
2010 | |
2011 | /* |
2012 | * Some Intel PCI Express chipsets have trouble with downstream device |
2013 | * power management. |
2014 | */ |
2015 | static void quirk_intel_pcie_pm(struct pci_dev *dev) |
2016 | { |
2017 | pci_pm_d3hot_delay = 120; |
2018 | dev->no_d1d2 = 1; |
2019 | } |
2020 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
2021 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); |
2022 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); |
2023 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); |
2024 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); |
2025 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); |
2026 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); |
2027 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); |
2028 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); |
2029 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); |
2030 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); |
2031 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); |
2032 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); |
2033 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); |
2034 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); |
2035 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); |
2036 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); |
2037 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); |
2038 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); |
2039 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); |
2040 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); |
2041 | |
2042 | static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) |
2043 | { |
2044 | if (dev->d3hot_delay >= delay) |
2045 | return; |
2046 | |
2047 | dev->d3hot_delay = delay; |
2048 | pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", |
2049 | dev->d3hot_delay); |
2050 | } |
2051 | |
2052 | static void quirk_radeon_pm(struct pci_dev *dev) |
2053 | { |
2054 | if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && |
2055 | dev->subsystem_device == 0x00e2) |
2056 | quirk_d3hot_delay(dev, delay: 20); |
2057 | } |
2058 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); |
2059 | |
2060 | /* |
2061 | * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus |
2062 | * reset is performed too soon after transition to D0, extend d3hot_delay |
2063 | * to previous effective default for all NVIDIA HDA controllers. |
2064 | */ |
2065 | static void quirk_nvidia_hda_pm(struct pci_dev *dev) |
2066 | { |
2067 | quirk_d3hot_delay(dev, delay: 20); |
2068 | } |
2069 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
2070 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, |
2071 | quirk_nvidia_hda_pm); |
2072 | |
2073 | /* |
2074 | * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. |
2075 | * https://bugzilla.kernel.org/show_bug.cgi?id=205587 |
2076 | * |
2077 | * The kernel attempts to transition these devices to D3cold, but that seems |
2078 | * to be ineffective on the platforms in question; the PCI device appears to |
2079 | * remain on in D3hot state. The D3hot-to-D0 transition then requires an |
2080 | * extended delay in order to succeed. |
2081 | */ |
2082 | static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) |
2083 | { |
2084 | quirk_d3hot_delay(dev, delay: 20); |
2085 | } |
2086 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); |
2087 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); |
2088 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); |
2089 | |
2090 | #ifdef CONFIG_X86_IO_APIC |
2091 | static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) |
2092 | { |
2093 | noioapicreroute = 1; |
2094 | pr_info("%s detected: disable boot interrupt reroute\n", d->ident); |
2095 | |
2096 | return 0; |
2097 | } |
2098 | |
2099 | static const struct dmi_system_id boot_interrupt_dmi_table[] = { |
2100 | /* |
2101 | * Systems to exclude from boot interrupt reroute quirks |
2102 | */ |
2103 | { |
2104 | .callback = dmi_disable_ioapicreroute, |
2105 | .ident = "ASUSTek Computer INC. M2N-LR", |
2106 | .matches = { |
2107 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), |
2108 | DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), |
2109 | }, |
2110 | }, |
2111 | {} |
2112 | }; |
2113 | |
2114 | /* |
2115 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, |
2116 | * remap the original interrupt in the Linux kernel to the boot interrupt, so |
2117 | * that a PCI device's interrupt handler is installed on the boot interrupt |
2118 | * line instead. |
2119 | */ |
2120 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) |
2121 | { |
2122 | dmi_check_system(list: boot_interrupt_dmi_table); |
2123 | if (noioapicquirk || noioapicreroute) |
2124 | return; |
2125 | |
2126 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; |
2127 | pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", |
2128 | dev->vendor, dev->device); |
2129 | } |
2130 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
2131 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); |
2132 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); |
2133 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); |
2134 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); |
2135 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); |
2136 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); |
2137 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); |
2138 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
2139 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); |
2140 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); |
2141 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); |
2142 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); |
2143 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); |
2144 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); |
2145 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); |
2146 | |
2147 | /* |
2148 | * On some chipsets we can disable the generation of legacy INTx boot |
2149 | * interrupts. |
2150 | */ |
2151 | |
2152 | /* |
2153 | * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no |
2154 | * 300641-004US, section 5.7.3. |
2155 | * |
2156 | * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. |
2157 | * Core IO on Xeon E5 v2, see Intel order no 329188-003. |
2158 | * Core IO on Xeon E7 v2, see Intel order no 329595-002. |
2159 | * Core IO on Xeon E5 v3, see Intel order no 330784-003. |
2160 | * Core IO on Xeon E7 v3, see Intel order no 332315-001US. |
2161 | * Core IO on Xeon E5 v4, see Intel order no 333810-002US. |
2162 | * Core IO on Xeon E7 v4, see Intel order no 332315-001US. |
2163 | * Core IO on Xeon D-1500, see Intel order no 332051-001. |
2164 | * Core IO on Xeon Scalable, see Intel order no 610950. |
2165 | */ |
2166 | #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ |
2167 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) |
2168 | |
2169 | #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ |
2170 | #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) |
2171 | |
2172 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) |
2173 | { |
2174 | u16 pci_config_word; |
2175 | u32 pci_config_dword; |
2176 | |
2177 | if (noioapicquirk) |
2178 | return; |
2179 | |
2180 | switch (dev->device) { |
2181 | case PCI_DEVICE_ID_INTEL_ESB_10: |
2182 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, |
2183 | val: &pci_config_word); |
2184 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; |
2185 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, |
2186 | val: pci_config_word); |
2187 | break; |
2188 | case 0x3c28: /* Xeon E5 1600/2600/4600 */ |
2189 | case 0x0e28: /* Xeon E5/E7 V2 */ |
2190 | case 0x2f28: /* Xeon E5/E7 V3,V4 */ |
2191 | case 0x6f28: /* Xeon D-1500 */ |
2192 | case 0x2034: /* Xeon Scalable Family */ |
2193 | pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, |
2194 | val: &pci_config_dword); |
2195 | pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; |
2196 | pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, |
2197 | val: pci_config_dword); |
2198 | break; |
2199 | default: |
2200 | return; |
2201 | } |
2202 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
2203 | dev->vendor, dev->device); |
2204 | } |
2205 | /* |
2206 | * Device 29 Func 5 Device IDs of IO-APIC |
2207 | * containing ABAR—APIC1 Alternate Base Address Register |
2208 | */ |
2209 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, |
2210 | quirk_disable_intel_boot_interrupt); |
2211 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, |
2212 | quirk_disable_intel_boot_interrupt); |
2213 | |
2214 | /* |
2215 | * Device 5 Func 0 Device IDs of Core IO modules/hubs |
2216 | * containing Coherent Interface Protocol Interrupt Control |
2217 | * |
2218 | * Device IDs obtained from volume 2 datasheets of commented |
2219 | * families above. |
2220 | */ |
2221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, |
2222 | quirk_disable_intel_boot_interrupt); |
2223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, |
2224 | quirk_disable_intel_boot_interrupt); |
2225 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, |
2226 | quirk_disable_intel_boot_interrupt); |
2227 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, |
2228 | quirk_disable_intel_boot_interrupt); |
2229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, |
2230 | quirk_disable_intel_boot_interrupt); |
2231 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, |
2232 | quirk_disable_intel_boot_interrupt); |
2233 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, |
2234 | quirk_disable_intel_boot_interrupt); |
2235 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, |
2236 | quirk_disable_intel_boot_interrupt); |
2237 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, |
2238 | quirk_disable_intel_boot_interrupt); |
2239 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, |
2240 | quirk_disable_intel_boot_interrupt); |
2241 | |
2242 | /* Disable boot interrupts on HT-1000 */ |
2243 | #define BC_HT1000_FEATURE_REG 0x64 |
2244 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) |
2245 | #define BC_HT1000_MAP_IDX 0xC00 |
2246 | #define BC_HT1000_MAP_DATA 0xC01 |
2247 | |
2248 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) |
2249 | { |
2250 | u32 pci_config_dword; |
2251 | u8 irq; |
2252 | |
2253 | if (noioapicquirk) |
2254 | return; |
2255 | |
2256 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, val: &pci_config_dword); |
2257 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, val: pci_config_dword | |
2258 | BC_HT1000_PIC_REGS_ENABLE); |
2259 | |
2260 | for (irq = 0x10; irq < 0x10 + 32; irq++) { |
2261 | outb(value: irq, BC_HT1000_MAP_IDX); |
2262 | outb(value: 0x00, BC_HT1000_MAP_DATA); |
2263 | } |
2264 | |
2265 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, val: pci_config_dword); |
2266 | |
2267 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
2268 | dev->vendor, dev->device); |
2269 | } |
2270 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
2271 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
2272 | |
2273 | /* Disable boot interrupts on AMD and ATI chipsets */ |
2274 | |
2275 | /* |
2276 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 |
2277 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode |
2278 | * (due to an erratum). |
2279 | */ |
2280 | #define AMD_813X_MISC 0x40 |
2281 | #define AMD_813X_NOIOAMODE (1<<0) |
2282 | #define AMD_813X_REV_B1 0x12 |
2283 | #define AMD_813X_REV_B2 0x13 |
2284 | |
2285 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) |
2286 | { |
2287 | u32 pci_config_dword; |
2288 | |
2289 | if (noioapicquirk) |
2290 | return; |
2291 | if ((dev->revision == AMD_813X_REV_B1) || |
2292 | (dev->revision == AMD_813X_REV_B2)) |
2293 | return; |
2294 | |
2295 | pci_read_config_dword(dev, AMD_813X_MISC, val: &pci_config_dword); |
2296 | pci_config_dword &= ~AMD_813X_NOIOAMODE; |
2297 | pci_write_config_dword(dev, AMD_813X_MISC, val: pci_config_dword); |
2298 | |
2299 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
2300 | dev->vendor, dev->device); |
2301 | } |
2302 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2303 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2304 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2305 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2306 | |
2307 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 |
2308 | |
2309 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) |
2310 | { |
2311 | u16 pci_config_word; |
2312 | |
2313 | if (noioapicquirk) |
2314 | return; |
2315 | |
2316 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, val: &pci_config_word); |
2317 | if (!pci_config_word) { |
2318 | pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", |
2319 | dev->vendor, dev->device); |
2320 | return; |
2321 | } |
2322 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, val: 0); |
2323 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
2324 | dev->vendor, dev->device); |
2325 | } |
2326 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
2327 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
2328 | #endif /* CONFIG_X86_IO_APIC */ |
2329 | |
2330 | /* |
2331 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size |
2332 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. |
2333 | * Re-allocate the region if needed... |
2334 | */ |
2335 | static void quirk_tc86c001_ide(struct pci_dev *dev) |
2336 | { |
2337 | struct resource *r = &dev->resource[0]; |
2338 | |
2339 | if (r->start & 0x8) { |
2340 | r->flags |= IORESOURCE_UNSET; |
2341 | resource_set_range(res: r, start: 0, SZ_16); |
2342 | } |
2343 | } |
2344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, |
2345 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, |
2346 | quirk_tc86c001_ide); |
2347 | |
2348 | /* |
2349 | * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the |
2350 | * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) |
2351 | * being read correctly if bit 7 of the base address is set. |
2352 | * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). |
2353 | * Re-allocate the regions to a 256-byte boundary if necessary. |
2354 | */ |
2355 | static void quirk_plx_pci9050(struct pci_dev *dev) |
2356 | { |
2357 | unsigned int bar; |
2358 | |
2359 | /* Fixed in revision 2 (PCI 9052). */ |
2360 | if (dev->revision >= 2) |
2361 | return; |
2362 | for (bar = 0; bar <= 1; bar++) |
2363 | if (pci_resource_len(dev, bar) == 0x80 && |
2364 | (pci_resource_start(dev, bar) & 0x80)) { |
2365 | struct resource *r = &dev->resource[bar]; |
2366 | pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", |
2367 | bar); |
2368 | r->flags |= IORESOURCE_UNSET; |
2369 | resource_set_range(res: r, start: 0, SZ_256); |
2370 | } |
2371 | } |
2372 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
2373 | quirk_plx_pci9050); |
2374 | /* |
2375 | * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) |
2376 | * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, |
2377 | * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, |
2378 | * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. |
2379 | * |
2380 | * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" |
2381 | * driver. |
2382 | */ |
2383 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); |
2384 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); |
2385 | |
2386 | static void quirk_netmos(struct pci_dev *dev) |
2387 | { |
2388 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; |
2389 | unsigned int num_serial = dev->subsystem_device & 0xf; |
2390 | |
2391 | /* |
2392 | * These Netmos parts are multiport serial devices with optional |
2393 | * parallel ports. Even when parallel ports are present, they |
2394 | * are identified as class SERIAL, which means the serial driver |
2395 | * will claim them. To prevent this, mark them as class OTHER. |
2396 | * These combo devices should be claimed by parport_serial. |
2397 | * |
2398 | * The subdevice ID is of the form 0x00PS, where <P> is the number |
2399 | * of parallel ports and <S> is the number of serial ports. |
2400 | */ |
2401 | switch (dev->device) { |
2402 | case PCI_DEVICE_ID_NETMOS_9835: |
2403 | /* Well, this rule doesn't hold for the following 9835 device */ |
2404 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && |
2405 | dev->subsystem_device == 0x0299) |
2406 | return; |
2407 | fallthrough; |
2408 | case PCI_DEVICE_ID_NETMOS_9735: |
2409 | case PCI_DEVICE_ID_NETMOS_9745: |
2410 | case PCI_DEVICE_ID_NETMOS_9845: |
2411 | case PCI_DEVICE_ID_NETMOS_9855: |
2412 | if (num_parallel) { |
2413 | pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", |
2414 | dev->device, num_parallel, num_serial); |
2415 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | |
2416 | (dev->class & 0xff); |
2417 | } |
2418 | } |
2419 | } |
2420 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, |
2421 | PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); |
2422 | |
2423 | static void quirk_e100_interrupt(struct pci_dev *dev) |
2424 | { |
2425 | u16 command, pmcsr; |
2426 | u8 __iomem *csr; |
2427 | u8 cmd_hi; |
2428 | |
2429 | switch (dev->device) { |
2430 | /* PCI IDs taken from drivers/net/e100.c */ |
2431 | case 0x1029: |
2432 | case 0x1030 ... 0x1034: |
2433 | case 0x1038 ... 0x103E: |
2434 | case 0x1050 ... 0x1057: |
2435 | case 0x1059: |
2436 | case 0x1064 ... 0x106B: |
2437 | case 0x1091 ... 0x1095: |
2438 | case 0x1209: |
2439 | case 0x1229: |
2440 | case 0x2449: |
2441 | case 0x2459: |
2442 | case 0x245D: |
2443 | case 0x27DC: |
2444 | break; |
2445 | default: |
2446 | return; |
2447 | } |
2448 | |
2449 | /* |
2450 | * Some firmware hands off the e100 with interrupts enabled, |
2451 | * which can cause a flood of interrupts if packets are |
2452 | * received before the driver attaches to the device. So |
2453 | * disable all e100 interrupts here. The driver will |
2454 | * re-enable them when it's ready. |
2455 | */ |
2456 | pci_read_config_word(dev, PCI_COMMAND, val: &command); |
2457 | |
2458 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
2459 | return; |
2460 | |
2461 | /* |
2462 | * Check that the device is in the D0 power state. If it's not, |
2463 | * there is no point to look any further. |
2464 | */ |
2465 | if (dev->pm_cap) { |
2466 | pci_read_config_word(dev, where: dev->pm_cap + PCI_PM_CTRL, val: &pmcsr); |
2467 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) |
2468 | return; |
2469 | } |
2470 | |
2471 | /* Convert from PCI bus to resource space. */ |
2472 | csr = ioremap(pci_resource_start(dev, 0), size: 8); |
2473 | if (!csr) { |
2474 | pci_warn(dev, "Can't map e100 registers\n"); |
2475 | return; |
2476 | } |
2477 | |
2478 | cmd_hi = readb(addr: csr + 3); |
2479 | if (cmd_hi == 0) { |
2480 | pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); |
2481 | writeb(val: 1, addr: csr + 3); |
2482 | } |
2483 | |
2484 | iounmap(addr: csr); |
2485 | } |
2486 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
2487 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); |
2488 | |
2489 | /* |
2490 | * The 82575 and 82598 may experience data corruption issues when transitioning |
2491 | * out of L0S. To prevent this we need to disable L0S on the PCIe link. |
2492 | */ |
2493 | static void quirk_disable_aspm_l0s(struct pci_dev *dev) |
2494 | { |
2495 | pci_info(dev, "Disabling L0s\n"); |
2496 | pci_disable_link_state(pdev: dev, PCIE_LINK_STATE_L0S); |
2497 | } |
2498 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); |
2499 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); |
2500 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); |
2501 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); |
2502 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); |
2503 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); |
2504 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); |
2505 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); |
2506 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); |
2507 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); |
2508 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); |
2509 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); |
2510 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); |
2511 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); |
2512 | |
2513 | static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) |
2514 | { |
2515 | pci_info(dev, "Disabling ASPM L0s/L1\n"); |
2516 | pci_disable_link_state(pdev: dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
2517 | } |
2518 | |
2519 | /* |
2520 | * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the |
2521 | * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; |
2522 | * disable both L0s and L1 for now to be safe. |
2523 | */ |
2524 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); |
2525 | |
2526 | /* |
2527 | * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain |
2528 | * Link bit cleared after starting the link retrain process to allow this |
2529 | * process to finish. |
2530 | * |
2531 | * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the |
2532 | * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. |
2533 | */ |
2534 | static void quirk_enable_clear_retrain_link(struct pci_dev *dev) |
2535 | { |
2536 | dev->clear_retrain_link = 1; |
2537 | pci_info(dev, "Enable PCIe Retrain Link quirk\n"); |
2538 | } |
2539 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); |
2540 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); |
2541 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); |
2542 | |
2543 | static void fixup_rev1_53c810(struct pci_dev *dev) |
2544 | { |
2545 | u32 class = dev->class; |
2546 | |
2547 | /* |
2548 | * rev 1 ncr53c810 chips don't set the class at all which means |
2549 | * they don't get their resources remapped. Fix that here. |
2550 | */ |
2551 | if (class) |
2552 | return; |
2553 | |
2554 | dev->class = PCI_CLASS_STORAGE_SCSI << 8; |
2555 | pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", |
2556 | class, dev->class); |
2557 | } |
2558 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); |
2559 | |
2560 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
2561 | static void quirk_p64h2_1k_io(struct pci_dev *dev) |
2562 | { |
2563 | u16 en1k; |
2564 | |
2565 | pci_read_config_word(dev, where: 0x40, val: &en1k); |
2566 | |
2567 | if (en1k & 0x200) { |
2568 | pci_info(dev, "Enable I/O Space to 1KB granularity\n"); |
2569 | dev->io_window_1k = 1; |
2570 | } |
2571 | } |
2572 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
2573 | |
2574 | /* |
2575 | * Under some circumstances, AER is not linked with extended capabilities. |
2576 | * Force it to be linked by setting the corresponding control bit in the |
2577 | * config space. |
2578 | */ |
2579 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
2580 | { |
2581 | uint8_t b; |
2582 | |
2583 | if (pci_read_config_byte(dev, where: 0xf41, val: &b) == 0) { |
2584 | if (!(b & 0x20)) { |
2585 | pci_write_config_byte(dev, where: 0xf41, val: b | 0x20); |
2586 | pci_info(dev, "Linking AER extended capability\n"); |
2587 | } |
2588 | } |
2589 | } |
2590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
2591 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
2592 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
2593 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
2594 | |
2595 | static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
2596 | { |
2597 | /* |
2598 | * Disable PCI Bus Parking and PCI Master read caching on CX700 |
2599 | * which causes unspecified timing errors with a VT6212L on the PCI |
2600 | * bus leading to USB2.0 packet loss. |
2601 | * |
2602 | * This quirk is only enabled if a second (on the external PCI bus) |
2603 | * VT6212L is found -- the CX700 core itself also contains a USB |
2604 | * host controller with the same PCI ID as the VT6212L. |
2605 | */ |
2606 | |
2607 | /* Count VT6212L instances */ |
2608 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, |
2609 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); |
2610 | uint8_t b; |
2611 | |
2612 | /* |
2613 | * p should contain the first (internal) VT6212L -- see if we have |
2614 | * an external one by searching again. |
2615 | */ |
2616 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, from: p); |
2617 | if (!p) |
2618 | return; |
2619 | pci_dev_put(dev: p); |
2620 | |
2621 | if (pci_read_config_byte(dev, where: 0x76, val: &b) == 0) { |
2622 | if (b & 0x40) { |
2623 | /* Turn off PCI Bus Parking */ |
2624 | pci_write_config_byte(dev, where: 0x76, val: b ^ 0x40); |
2625 | |
2626 | pci_info(dev, "Disabling VIA CX700 PCI parking\n"); |
2627 | } |
2628 | } |
2629 | |
2630 | if (pci_read_config_byte(dev, where: 0x72, val: &b) == 0) { |
2631 | if (b != 0) { |
2632 | /* Turn off PCI Master read caching */ |
2633 | pci_write_config_byte(dev, where: 0x72, val: 0x0); |
2634 | |
2635 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ |
2636 | pci_write_config_byte(dev, where: 0x75, val: 0x1); |
2637 | |
2638 | /* Disable "Read FIFO Timer" */ |
2639 | pci_write_config_byte(dev, where: 0x77, val: 0x0); |
2640 | |
2641 | pci_info(dev, "Disabling VIA CX700 PCI caching\n"); |
2642 | } |
2643 | } |
2644 | } |
2645 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
2646 | |
2647 | static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) |
2648 | { |
2649 | u32 rev; |
2650 | |
2651 | pci_read_config_dword(dev, where: 0xf4, val: &rev); |
2652 | |
2653 | /* Only CAP the MRRS if the device is a 5719 A0 */ |
2654 | if (rev == 0x05719000) { |
2655 | int readrq = pcie_get_readrq(dev); |
2656 | if (readrq > 2048) |
2657 | pcie_set_readrq(dev, rq: 2048); |
2658 | } |
2659 | } |
2660 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, |
2661 | PCI_DEVICE_ID_TIGON3_5719, |
2662 | quirk_brcm_5719_limit_mrrs); |
2663 | |
2664 | /* |
2665 | * Originally in EDAC sources for i82875P: Intel tells BIOS developers to |
2666 | * hide device 6 which configures the overflow device access containing the |
2667 | * DRBs - this is where we expose device 6. |
2668 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm |
2669 | */ |
2670 | static void quirk_unhide_mch_dev6(struct pci_dev *dev) |
2671 | { |
2672 | u8 reg; |
2673 | |
2674 | if (pci_read_config_byte(dev, where: 0xF4, val: ®) == 0 && !(reg & 0x02)) { |
2675 | pci_info(dev, "Enabling MCH 'Overflow' Device\n"); |
2676 | pci_write_config_byte(dev, where: 0xF4, val: reg | 0x02); |
2677 | } |
2678 | } |
2679 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, |
2680 | quirk_unhide_mch_dev6); |
2681 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, |
2682 | quirk_unhide_mch_dev6); |
2683 | |
2684 | #ifdef CONFIG_PCI_MSI |
2685 | /* |
2686 | * Some chipsets do not support MSI. We cannot easily rely on setting |
2687 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some |
2688 | * other buses controlled by the chipset even if Linux is not aware of it. |
2689 | * Instead of setting the flag on all buses in the machine, simply disable |
2690 | * MSI globally. |
2691 | */ |
2692 | static void quirk_disable_all_msi(struct pci_dev *dev) |
2693 | { |
2694 | pci_no_msi(); |
2695 | pci_warn(dev, "MSI quirk detected; MSI disabled\n"); |
2696 | } |
2697 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2698 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); |
2699 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); |
2700 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
2701 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
2702 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
2703 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
2704 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); |
2705 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); |
2706 | |
2707 | /* Disable MSI on chipsets that are known to not support it */ |
2708 | static void quirk_disable_msi(struct pci_dev *dev) |
2709 | { |
2710 | if (dev->subordinate) { |
2711 | pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); |
2712 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2713 | } |
2714 | } |
2715 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); |
2716 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
2717 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
2718 | |
2719 | /* |
2720 | * The APC bridge device in AMD 780 family northbridges has some random |
2721 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead |
2722 | * we use the possible vendor/device IDs of the host bridge for the |
2723 | * declared quirk, and search for the APC bridge by slot number. |
2724 | */ |
2725 | static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) |
2726 | { |
2727 | struct pci_dev *apc_bridge; |
2728 | |
2729 | apc_bridge = pci_get_slot(bus: host_bridge->bus, PCI_DEVFN(1, 0)); |
2730 | if (apc_bridge) { |
2731 | if (apc_bridge->device == 0x9602) |
2732 | quirk_disable_msi(dev: apc_bridge); |
2733 | pci_dev_put(dev: apc_bridge); |
2734 | } |
2735 | } |
2736 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); |
2737 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); |
2738 | |
2739 | /* |
2740 | * Go through the list of HyperTransport capabilities and return 1 if a HT |
2741 | * MSI capability is found and enabled. |
2742 | */ |
2743 | static int msi_ht_cap_enabled(struct pci_dev *dev) |
2744 | { |
2745 | int pos, ttl = PCI_FIND_CAP_TTL; |
2746 | |
2747 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
2748 | while (pos && ttl--) { |
2749 | u8 flags; |
2750 | |
2751 | if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS, |
2752 | val: &flags) == 0) { |
2753 | pci_info(dev, "Found %s HT MSI Mapping\n", |
2754 | flags & HT_MSI_FLAGS_ENABLE ? |
2755 | "enabled": "disabled"); |
2756 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
2757 | } |
2758 | |
2759 | pos = pci_find_next_ht_capability(dev, pos, |
2760 | HT_CAPTYPE_MSI_MAPPING); |
2761 | } |
2762 | return 0; |
2763 | } |
2764 | |
2765 | /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ |
2766 | static void quirk_msi_ht_cap(struct pci_dev *dev) |
2767 | { |
2768 | if (!msi_ht_cap_enabled(dev)) |
2769 | quirk_disable_msi(dev); |
2770 | } |
2771 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, |
2772 | quirk_msi_ht_cap); |
2773 | |
2774 | /* |
2775 | * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported |
2776 | * if the MSI capability is set in any of these mappings. |
2777 | */ |
2778 | static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
2779 | { |
2780 | struct pci_dev *pdev; |
2781 | |
2782 | /* |
2783 | * Check HT MSI cap on this chipset and the root one. A single one |
2784 | * having MSI is enough to be sure that MSI is supported. |
2785 | */ |
2786 | pdev = pci_get_slot(bus: dev->bus, devfn: 0); |
2787 | if (!pdev) |
2788 | return; |
2789 | if (!msi_ht_cap_enabled(dev: pdev)) |
2790 | quirk_msi_ht_cap(dev); |
2791 | pci_dev_put(dev: pdev); |
2792 | } |
2793 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
2794 | quirk_nvidia_ck804_msi_ht_cap); |
2795 | |
2796 | /* Force enable MSI mapping capability on HT bridges */ |
2797 | static void ht_enable_msi_mapping(struct pci_dev *dev) |
2798 | { |
2799 | int pos, ttl = PCI_FIND_CAP_TTL; |
2800 | |
2801 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
2802 | while (pos && ttl--) { |
2803 | u8 flags; |
2804 | |
2805 | if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS, |
2806 | val: &flags) == 0) { |
2807 | pci_info(dev, "Enabling HT MSI Mapping\n"); |
2808 | |
2809 | pci_write_config_byte(dev, where: pos + HT_MSI_FLAGS, |
2810 | val: flags | HT_MSI_FLAGS_ENABLE); |
2811 | } |
2812 | pos = pci_find_next_ht_capability(dev, pos, |
2813 | HT_CAPTYPE_MSI_MAPPING); |
2814 | } |
2815 | } |
2816 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2817 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, |
2818 | ht_enable_msi_mapping); |
2819 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2820 | ht_enable_msi_mapping); |
2821 | |
2822 | /* |
2823 | * The P5N32-SLI motherboards from Asus have a problem with MSI |
2824 | * for the MCP55 NIC. It is not yet determined whether the MSI problem |
2825 | * also affects other devices. As for now, turn off MSI for this device. |
2826 | */ |
2827 | static void nvenet_msi_disable(struct pci_dev *dev) |
2828 | { |
2829 | const char *board_name = dmi_get_system_info(field: DMI_BOARD_NAME); |
2830 | |
2831 | if (board_name && |
2832 | (strstr(board_name, "P5N32-SLI PREMIUM") || |
2833 | strstr(board_name, "P5N32-E SLI"))) { |
2834 | pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); |
2835 | dev->no_msi = 1; |
2836 | } |
2837 | } |
2838 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2839 | PCI_DEVICE_ID_NVIDIA_NVENET_15, |
2840 | nvenet_msi_disable); |
2841 | |
2842 | /* |
2843 | * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device |
2844 | * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI |
2845 | * interrupts for PME and AER events; instead only INTx interrupts are |
2846 | * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts |
2847 | * for other events, since PCIe specification doesn't support using a mix of |
2848 | * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port |
2849 | * service drivers registering their respective ISRs for MSIs. |
2850 | */ |
2851 | static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) |
2852 | { |
2853 | dev->no_msi = 1; |
2854 | } |
2855 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, |
2856 | PCI_CLASS_BRIDGE_PCI, 8, |
2857 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2858 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, |
2859 | PCI_CLASS_BRIDGE_PCI, 8, |
2860 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2861 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, |
2862 | PCI_CLASS_BRIDGE_PCI, 8, |
2863 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2864 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, |
2865 | PCI_CLASS_BRIDGE_PCI, 8, |
2866 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2867 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, |
2868 | PCI_CLASS_BRIDGE_PCI, 8, |
2869 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2870 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, |
2871 | PCI_CLASS_BRIDGE_PCI, 8, |
2872 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2873 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, |
2874 | PCI_CLASS_BRIDGE_PCI, 8, |
2875 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2876 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, |
2877 | PCI_CLASS_BRIDGE_PCI, 8, |
2878 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2879 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, |
2880 | PCI_CLASS_BRIDGE_PCI, 8, |
2881 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2882 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, |
2883 | PCI_CLASS_BRIDGE_PCI, 8, |
2884 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2885 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, |
2886 | PCI_CLASS_BRIDGE_PCI, 8, |
2887 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2888 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, |
2889 | PCI_CLASS_BRIDGE_PCI, 8, |
2890 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2891 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, |
2892 | PCI_CLASS_BRIDGE_PCI, 8, |
2893 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2894 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, |
2895 | PCI_CLASS_BRIDGE_PCI, 8, |
2896 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2897 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, |
2898 | PCI_CLASS_BRIDGE_PCI, 8, |
2899 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2900 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, |
2901 | PCI_CLASS_BRIDGE_PCI, 8, |
2902 | pci_quirk_nvidia_tegra_disable_rp_msi); |
2903 | |
2904 | /* |
2905 | * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing |
2906 | * config register. This register controls the routing of legacy |
2907 | * interrupts from devices that route through the MCP55. If this register |
2908 | * is misprogrammed, interrupts are only sent to the BSP, unlike |
2909 | * conventional systems where the IRQ is broadcast to all online CPUs. Not |
2910 | * having this register set properly prevents kdump from booting up |
2911 | * properly, so let's make sure that we have it set correctly. |
2912 | * Note that this is an undocumented register. |
2913 | */ |
2914 | static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) |
2915 | { |
2916 | u32 cfg; |
2917 | |
2918 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
2919 | return; |
2920 | |
2921 | pci_read_config_dword(dev, where: 0x74, val: &cfg); |
2922 | |
2923 | if (cfg & ((1 << 2) | (1 << 15))) { |
2924 | pr_info("Rewriting IRQ routing register on MCP55\n"); |
2925 | cfg &= ~((1 << 2) | (1 << 15)); |
2926 | pci_write_config_dword(dev, where: 0x74, val: cfg); |
2927 | } |
2928 | } |
2929 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2930 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, |
2931 | nvbridge_check_legacy_irq_routing); |
2932 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2933 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, |
2934 | nvbridge_check_legacy_irq_routing); |
2935 | |
2936 | static int ht_check_msi_mapping(struct pci_dev *dev) |
2937 | { |
2938 | int pos, ttl = PCI_FIND_CAP_TTL; |
2939 | int found = 0; |
2940 | |
2941 | /* Check if there is HT MSI cap or enabled on this device */ |
2942 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
2943 | while (pos && ttl--) { |
2944 | u8 flags; |
2945 | |
2946 | if (found < 1) |
2947 | found = 1; |
2948 | if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS, |
2949 | val: &flags) == 0) { |
2950 | if (flags & HT_MSI_FLAGS_ENABLE) { |
2951 | if (found < 2) { |
2952 | found = 2; |
2953 | break; |
2954 | } |
2955 | } |
2956 | } |
2957 | pos = pci_find_next_ht_capability(dev, pos, |
2958 | HT_CAPTYPE_MSI_MAPPING); |
2959 | } |
2960 | |
2961 | return found; |
2962 | } |
2963 | |
2964 | static int host_bridge_with_leaf(struct pci_dev *host_bridge) |
2965 | { |
2966 | struct pci_dev *dev; |
2967 | int pos; |
2968 | int i, dev_no; |
2969 | int found = 0; |
2970 | |
2971 | dev_no = host_bridge->devfn >> 3; |
2972 | for (i = dev_no + 1; i < 0x20; i++) { |
2973 | dev = pci_get_slot(bus: host_bridge->bus, PCI_DEVFN(i, 0)); |
2974 | if (!dev) |
2975 | continue; |
2976 | |
2977 | /* found next host bridge? */ |
2978 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
2979 | if (pos != 0) { |
2980 | pci_dev_put(dev); |
2981 | break; |
2982 | } |
2983 | |
2984 | if (ht_check_msi_mapping(dev)) { |
2985 | found = 1; |
2986 | pci_dev_put(dev); |
2987 | break; |
2988 | } |
2989 | pci_dev_put(dev); |
2990 | } |
2991 | |
2992 | return found; |
2993 | } |
2994 | |
2995 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2996 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ |
2997 | |
2998 | static int is_end_of_ht_chain(struct pci_dev *dev) |
2999 | { |
3000 | int pos, ctrl_off; |
3001 | int end = 0; |
3002 | u16 flags, ctrl; |
3003 | |
3004 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
3005 | |
3006 | if (!pos) |
3007 | goto out; |
3008 | |
3009 | pci_read_config_word(dev, where: pos + PCI_CAP_FLAGS, val: &flags); |
3010 | |
3011 | ctrl_off = ((flags >> 10) & 1) ? |
3012 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; |
3013 | pci_read_config_word(dev, where: pos + ctrl_off, val: &ctrl); |
3014 | |
3015 | if (ctrl & (1 << 6)) |
3016 | end = 1; |
3017 | |
3018 | out: |
3019 | return end; |
3020 | } |
3021 | |
3022 | static void nv_ht_enable_msi_mapping(struct pci_dev *dev) |
3023 | { |
3024 | struct pci_dev *host_bridge; |
3025 | int pos; |
3026 | int i, dev_no; |
3027 | int found = 0; |
3028 | |
3029 | dev_no = dev->devfn >> 3; |
3030 | for (i = dev_no; i >= 0; i--) { |
3031 | host_bridge = pci_get_slot(bus: dev->bus, PCI_DEVFN(i, 0)); |
3032 | if (!host_bridge) |
3033 | continue; |
3034 | |
3035 | pos = pci_find_ht_capability(dev: host_bridge, HT_CAPTYPE_SLAVE); |
3036 | if (pos != 0) { |
3037 | found = 1; |
3038 | break; |
3039 | } |
3040 | pci_dev_put(dev: host_bridge); |
3041 | } |
3042 | |
3043 | if (!found) |
3044 | return; |
3045 | |
3046 | /* don't enable end_device/host_bridge with leaf directly here */ |
3047 | if (host_bridge == dev && is_end_of_ht_chain(dev: host_bridge) && |
3048 | host_bridge_with_leaf(host_bridge)) |
3049 | goto out; |
3050 | |
3051 | /* root did that ! */ |
3052 | if (msi_ht_cap_enabled(dev: host_bridge)) |
3053 | goto out; |
3054 | |
3055 | ht_enable_msi_mapping(dev); |
3056 | |
3057 | out: |
3058 | pci_dev_put(dev: host_bridge); |
3059 | } |
3060 | |
3061 | static void ht_disable_msi_mapping(struct pci_dev *dev) |
3062 | { |
3063 | int pos, ttl = PCI_FIND_CAP_TTL; |
3064 | |
3065 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
3066 | while (pos && ttl--) { |
3067 | u8 flags; |
3068 | |
3069 | if (pci_read_config_byte(dev, where: pos + HT_MSI_FLAGS, |
3070 | val: &flags) == 0) { |
3071 | pci_info(dev, "Disabling HT MSI Mapping\n"); |
3072 | |
3073 | pci_write_config_byte(dev, where: pos + HT_MSI_FLAGS, |
3074 | val: flags & ~HT_MSI_FLAGS_ENABLE); |
3075 | } |
3076 | pos = pci_find_next_ht_capability(dev, pos, |
3077 | HT_CAPTYPE_MSI_MAPPING); |
3078 | } |
3079 | } |
3080 | |
3081 | static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
3082 | { |
3083 | struct pci_dev *host_bridge; |
3084 | int pos; |
3085 | int found; |
3086 | |
3087 | if (!pci_msi_enabled()) |
3088 | return; |
3089 | |
3090 | /* check if there is HT MSI cap or enabled on this device */ |
3091 | found = ht_check_msi_mapping(dev); |
3092 | |
3093 | /* no HT MSI CAP */ |
3094 | if (found == 0) |
3095 | return; |
3096 | |
3097 | /* |
3098 | * HT MSI mapping should be disabled on devices that are below |
3099 | * a non-HyperTransport host bridge. Locate the host bridge. |
3100 | */ |
3101 | host_bridge = pci_get_domain_bus_and_slot(domain: pci_domain_nr(bus: dev->bus), bus: 0, |
3102 | PCI_DEVFN(0, 0)); |
3103 | if (host_bridge == NULL) { |
3104 | pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); |
3105 | return; |
3106 | } |
3107 | |
3108 | pos = pci_find_ht_capability(dev: host_bridge, HT_CAPTYPE_SLAVE); |
3109 | if (pos != 0) { |
3110 | /* Host bridge is to HT */ |
3111 | if (found == 1) { |
3112 | /* it is not enabled, try to enable it */ |
3113 | if (all) |
3114 | ht_enable_msi_mapping(dev); |
3115 | else |
3116 | nv_ht_enable_msi_mapping(dev); |
3117 | } |
3118 | goto out; |
3119 | } |
3120 | |
3121 | /* HT MSI is not enabled */ |
3122 | if (found == 1) |
3123 | goto out; |
3124 | |
3125 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
3126 | ht_disable_msi_mapping(dev); |
3127 | |
3128 | out: |
3129 | pci_dev_put(dev: host_bridge); |
3130 | } |
3131 | |
3132 | static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) |
3133 | { |
3134 | return __nv_msi_ht_cap_quirk(dev, all: 1); |
3135 | } |
3136 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
3137 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
3138 | |
3139 | static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) |
3140 | { |
3141 | return __nv_msi_ht_cap_quirk(dev, all: 0); |
3142 | } |
3143 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
3144 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
3145 | |
3146 | static void quirk_msi_intx_disable_bug(struct pci_dev *dev) |
3147 | { |
3148 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
3149 | } |
3150 | |
3151 | static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
3152 | { |
3153 | struct pci_dev *p; |
3154 | |
3155 | /* |
3156 | * SB700 MSI issue will be fixed at HW level from revision A21; |
3157 | * we need check PCI REVISION ID of SMBus controller to get SB700 |
3158 | * revision. |
3159 | */ |
3160 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
3161 | NULL); |
3162 | if (!p) |
3163 | return; |
3164 | |
3165 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) |
3166 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
3167 | pci_dev_put(dev: p); |
3168 | } |
3169 | |
3170 | static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) |
3171 | { |
3172 | /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ |
3173 | if (dev->revision < 0x18) { |
3174 | pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); |
3175 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
3176 | } |
3177 | } |
3178 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3179 | PCI_DEVICE_ID_TIGON3_5780, |
3180 | quirk_msi_intx_disable_bug); |
3181 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3182 | PCI_DEVICE_ID_TIGON3_5780S, |
3183 | quirk_msi_intx_disable_bug); |
3184 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3185 | PCI_DEVICE_ID_TIGON3_5714, |
3186 | quirk_msi_intx_disable_bug); |
3187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3188 | PCI_DEVICE_ID_TIGON3_5714S, |
3189 | quirk_msi_intx_disable_bug); |
3190 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3191 | PCI_DEVICE_ID_TIGON3_5715, |
3192 | quirk_msi_intx_disable_bug); |
3193 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3194 | PCI_DEVICE_ID_TIGON3_5715S, |
3195 | quirk_msi_intx_disable_bug); |
3196 | |
3197 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
3198 | quirk_msi_intx_disable_ati_bug); |
3199 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
3200 | quirk_msi_intx_disable_ati_bug); |
3201 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
3202 | quirk_msi_intx_disable_ati_bug); |
3203 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
3204 | quirk_msi_intx_disable_ati_bug); |
3205 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
3206 | quirk_msi_intx_disable_ati_bug); |
3207 | |
3208 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, |
3209 | quirk_msi_intx_disable_bug); |
3210 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, |
3211 | quirk_msi_intx_disable_bug); |
3212 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, |
3213 | quirk_msi_intx_disable_bug); |
3214 | |
3215 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, |
3216 | quirk_msi_intx_disable_bug); |
3217 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, |
3218 | quirk_msi_intx_disable_bug); |
3219 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, |
3220 | quirk_msi_intx_disable_bug); |
3221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, |
3222 | quirk_msi_intx_disable_bug); |
3223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, |
3224 | quirk_msi_intx_disable_bug); |
3225 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, |
3226 | quirk_msi_intx_disable_bug); |
3227 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, |
3228 | quirk_msi_intx_disable_qca_bug); |
3229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, |
3230 | quirk_msi_intx_disable_qca_bug); |
3231 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, |
3232 | quirk_msi_intx_disable_qca_bug); |
3233 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, |
3234 | quirk_msi_intx_disable_qca_bug); |
3235 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, |
3236 | quirk_msi_intx_disable_qca_bug); |
3237 | |
3238 | /* |
3239 | * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it |
3240 | * should be disabled on platforms where the device (mistakenly) advertises it. |
3241 | * |
3242 | * Notice that this quirk also disables MSI (which may work, but hasn't been |
3243 | * tested), since currently there is no standard way to disable only MSI-X. |
3244 | * |
3245 | * The 0031 device id is reused for other non Root Port device types, |
3246 | * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. |
3247 | */ |
3248 | static void quirk_al_msi_disable(struct pci_dev *dev) |
3249 | { |
3250 | dev->no_msi = 1; |
3251 | pci_warn(dev, "Disabling MSI/MSI-X\n"); |
3252 | } |
3253 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, |
3254 | PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); |
3255 | #endif /* CONFIG_PCI_MSI */ |
3256 | |
3257 | /* |
3258 | * Allow manual resource allocation for PCI hotplug bridges via |
3259 | * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI |
3260 | * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to |
3261 | * allocate resources when hotplug device is inserted and PCI bus is |
3262 | * rescanned. |
3263 | */ |
3264 | static void quirk_hotplug_bridge(struct pci_dev *dev) |
3265 | { |
3266 | dev->is_hotplug_bridge = 1; |
3267 | } |
3268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); |
3269 | |
3270 | /* |
3271 | * This is a quirk for the Ricoh MMC controller found as a part of some |
3272 | * multifunction chips. |
3273 | * |
3274 | * This is very similar and based on the ricoh_mmc driver written by |
3275 | * Philip Langdale. Thank you for these magic sequences. |
3276 | * |
3277 | * These chips implement the four main memory card controllers (SD, MMC, |
3278 | * MS, xD) and one or both of CardBus or FireWire. |
3279 | * |
3280 | * It happens that they implement SD and MMC support as separate |
3281 | * controllers (and PCI functions). The Linux SDHCI driver supports MMC |
3282 | * cards but the chip detects MMC cards in hardware and directs them to the |
3283 | * MMC controller - so the SDHCI driver never sees them. |
3284 | * |
3285 | * To get around this, we must disable the useless MMC controller. At that |
3286 | * point, the SDHCI controller will start seeing them. It seems to be the |
3287 | * case that the relevant PCI registers to deactivate the MMC controller |
3288 | * live on PCI function 0, which might be the CardBus controller or the |
3289 | * FireWire controller, depending on the particular chip in question |
3290 | * |
3291 | * This has to be done early, because as soon as we disable the MMC controller |
3292 | * other PCI functions shift up one level, e.g. function #2 becomes function |
3293 | * #1, and this will confuse the PCI core. |
3294 | */ |
3295 | #ifdef CONFIG_MMC_RICOH_MMC |
3296 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) |
3297 | { |
3298 | u8 write_enable; |
3299 | u8 write_target; |
3300 | u8 disable; |
3301 | |
3302 | /* |
3303 | * Disable via CardBus interface |
3304 | * |
3305 | * This must be done via function #0 |
3306 | */ |
3307 | if (PCI_FUNC(dev->devfn)) |
3308 | return; |
3309 | |
3310 | pci_read_config_byte(dev, where: 0xB7, val: &disable); |
3311 | if (disable & 0x02) |
3312 | return; |
3313 | |
3314 | pci_read_config_byte(dev, where: 0x8E, val: &write_enable); |
3315 | pci_write_config_byte(dev, where: 0x8E, val: 0xAA); |
3316 | pci_read_config_byte(dev, where: 0x8D, val: &write_target); |
3317 | pci_write_config_byte(dev, where: 0x8D, val: 0xB7); |
3318 | pci_write_config_byte(dev, where: 0xB7, val: disable | 0x02); |
3319 | pci_write_config_byte(dev, where: 0x8E, val: write_enable); |
3320 | pci_write_config_byte(dev, where: 0x8D, val: write_target); |
3321 | |
3322 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); |
3323 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
3324 | } |
3325 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); |
3326 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); |
3327 | |
3328 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) |
3329 | { |
3330 | u8 write_enable; |
3331 | u8 disable; |
3332 | |
3333 | /* |
3334 | * Disable via FireWire interface |
3335 | * |
3336 | * This must be done via function #0 |
3337 | */ |
3338 | if (PCI_FUNC(dev->devfn)) |
3339 | return; |
3340 | /* |
3341 | * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize |
3342 | * certain types of SD/MMC cards. Lowering the SD base clock |
3343 | * frequency from 200Mhz to 50Mhz fixes this issue. |
3344 | * |
3345 | * 0x150 - SD2.0 mode enable for changing base clock |
3346 | * frequency to 50Mhz |
3347 | * 0xe1 - Base clock frequency |
3348 | * 0x32 - 50Mhz new clock frequency |
3349 | * 0xf9 - Key register for 0x150 |
3350 | * 0xfc - key register for 0xe1 |
3351 | */ |
3352 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || |
3353 | dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { |
3354 | pci_write_config_byte(dev, where: 0xf9, val: 0xfc); |
3355 | pci_write_config_byte(dev, where: 0x150, val: 0x10); |
3356 | pci_write_config_byte(dev, where: 0xf9, val: 0x00); |
3357 | pci_write_config_byte(dev, where: 0xfc, val: 0x01); |
3358 | pci_write_config_byte(dev, where: 0xe1, val: 0x32); |
3359 | pci_write_config_byte(dev, where: 0xfc, val: 0x00); |
3360 | |
3361 | pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); |
3362 | } |
3363 | |
3364 | pci_read_config_byte(dev, where: 0xCB, val: &disable); |
3365 | |
3366 | if (disable & 0x02) |
3367 | return; |
3368 | |
3369 | pci_read_config_byte(dev, where: 0xCA, val: &write_enable); |
3370 | pci_write_config_byte(dev, where: 0xCA, val: 0x57); |
3371 | pci_write_config_byte(dev, where: 0xCB, val: disable | 0x02); |
3372 | pci_write_config_byte(dev, where: 0xCA, val: write_enable); |
3373 | |
3374 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); |
3375 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
3376 | |
3377 | } |
3378 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); |
3379 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); |
3380 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
3381 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
3382 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
3383 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
3384 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
3385 | |
3386 | #ifdef CONFIG_DMAR_TABLE |
3387 | #define VTUNCERRMSK_REG 0x1ac |
3388 | #define VTD_MSK_SPEC_ERRORS (1 << 31) |
3389 | /* |
3390 | * This is a quirk for masking VT-d spec-defined errors to platform error |
3391 | * handling logic. Without this, platforms using Intel 7500, 5500 chipsets |
3392 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based |
3393 | * on the RAS config settings of the platform) when a VT-d fault happens. |
3394 | * The resulting SMI caused the system to hang. |
3395 | * |
3396 | * VT-d spec-related errors are already handled by the VT-d OS code, so no |
3397 | * need to report the same error through other channels. |
3398 | */ |
3399 | static void vtd_mask_spec_errors(struct pci_dev *dev) |
3400 | { |
3401 | u32 word; |
3402 | |
3403 | pci_read_config_dword(dev, VTUNCERRMSK_REG, val: &word); |
3404 | pci_write_config_dword(dev, VTUNCERRMSK_REG, val: word | VTD_MSK_SPEC_ERRORS); |
3405 | } |
3406 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); |
3407 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); |
3408 | #endif |
3409 | |
3410 | static void fixup_ti816x_class(struct pci_dev *dev) |
3411 | { |
3412 | u32 class = dev->class; |
3413 | |
3414 | /* TI 816x devices do not have class code set when in PCIe boot mode */ |
3415 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; |
3416 | pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", |
3417 | class, dev->class); |
3418 | } |
3419 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, |
3420 | PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); |
3421 | |
3422 | /* |
3423 | * Some PCIe devices do not work reliably with the claimed maximum |
3424 | * payload size supported. |
3425 | */ |
3426 | static void fixup_mpss_256(struct pci_dev *dev) |
3427 | { |
3428 | dev->pcie_mpss = 1; /* 256 bytes */ |
3429 | } |
3430 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, |
3431 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); |
3432 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, |
3433 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); |
3434 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, |
3435 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); |
3436 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); |
3437 | |
3438 | /* |
3439 | * Intel 5000 and 5100 Memory controllers have an erratum with read completion |
3440 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. |
3441 | * Since there is no way of knowing what the PCIe MPS on each fabric will be |
3442 | * until all of the devices are discovered and buses walked, read completion |
3443 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because |
3444 | * it is possible to hotplug a device with MPS of 256B. |
3445 | */ |
3446 | static void quirk_intel_mc_errata(struct pci_dev *dev) |
3447 | { |
3448 | int err; |
3449 | u16 rcc; |
3450 | |
3451 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
3452 | pcie_bus_config == PCIE_BUS_DEFAULT) |
3453 | return; |
3454 | |
3455 | /* |
3456 | * Intel erratum specifies bits to change but does not say what |
3457 | * they are. Keeping them magical until such time as the registers |
3458 | * and values can be explained. |
3459 | */ |
3460 | err = pci_read_config_word(dev, where: 0x48, val: &rcc); |
3461 | if (err) { |
3462 | pci_err(dev, "Error attempting to read the read completion coalescing register\n"); |
3463 | return; |
3464 | } |
3465 | |
3466 | if (!(rcc & (1 << 10))) |
3467 | return; |
3468 | |
3469 | rcc &= ~(1 << 10); |
3470 | |
3471 | err = pci_write_config_word(dev, where: 0x48, val: rcc); |
3472 | if (err) { |
3473 | pci_err(dev, "Error attempting to write the read completion coalescing register\n"); |
3474 | return; |
3475 | } |
3476 | |
3477 | pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); |
3478 | } |
3479 | /* Intel 5000 series memory controllers and ports 2-7 */ |
3480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); |
3481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); |
3482 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); |
3483 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); |
3484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); |
3485 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); |
3486 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); |
3487 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); |
3488 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); |
3489 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); |
3490 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); |
3491 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); |
3492 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); |
3493 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); |
3494 | /* Intel 5100 series memory controllers and ports 2-7 */ |
3495 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); |
3496 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); |
3497 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); |
3498 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); |
3499 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); |
3500 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); |
3501 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); |
3502 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); |
3503 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); |
3504 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); |
3505 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); |
3506 | |
3507 | /* |
3508 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. |
3509 | * To work around this, query the size it should be configured to by the |
3510 | * device and modify the resource end to correspond to this new size. |
3511 | */ |
3512 | static void quirk_intel_ntb(struct pci_dev *dev) |
3513 | { |
3514 | int rc; |
3515 | u8 val; |
3516 | |
3517 | rc = pci_read_config_byte(dev, where: 0x00D0, val: &val); |
3518 | if (rc) |
3519 | return; |
3520 | |
3521 | resource_set_size(res: &dev->resource[2], size: (resource_size_t)1 << val); |
3522 | |
3523 | rc = pci_read_config_byte(dev, where: 0x00D1, val: &val); |
3524 | if (rc) |
3525 | return; |
3526 | |
3527 | resource_set_size(res: &dev->resource[4], size: (resource_size_t)1 << val); |
3528 | } |
3529 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); |
3530 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); |
3531 | |
3532 | /* |
3533 | * Some BIOS implementations leave the Intel GPU interrupts enabled, even |
3534 | * though no one is handling them (e.g., if the i915 driver is never |
3535 | * loaded). Additionally the interrupt destination is not set up properly |
3536 | * and the interrupt ends up -somewhere-. |
3537 | * |
3538 | * These spurious interrupts are "sticky" and the kernel disables the |
3539 | * (shared) interrupt line after 100,000+ generated interrupts. |
3540 | * |
3541 | * Fix it by disabling the still enabled interrupts. This resolves crashes |
3542 | * often seen on monitor unplug. |
3543 | */ |
3544 | #define I915_DEIER_REG 0x4400c |
3545 | static void disable_igfx_irq(struct pci_dev *dev) |
3546 | { |
3547 | void __iomem *regs = pci_iomap(dev, bar: 0, max: 0); |
3548 | if (regs == NULL) { |
3549 | pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); |
3550 | return; |
3551 | } |
3552 | |
3553 | /* Check if any interrupt line is still enabled */ |
3554 | if (readl(addr: regs + I915_DEIER_REG) != 0) { |
3555 | pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); |
3556 | |
3557 | writel(val: 0, addr: regs + I915_DEIER_REG); |
3558 | } |
3559 | |
3560 | pci_iounmap(dev, regs); |
3561 | } |
3562 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); |
3563 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); |
3564 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); |
3565 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); |
3566 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); |
3567 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); |
3568 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); |
3569 | |
3570 | /* |
3571 | * PCI devices which are on Intel chips can skip the 10ms delay |
3572 | * before entering D3 mode. |
3573 | */ |
3574 | static void quirk_remove_d3hot_delay(struct pci_dev *dev) |
3575 | { |
3576 | dev->d3hot_delay = 0; |
3577 | } |
3578 | /* C600 Series devices do not need 10ms d3hot_delay */ |
3579 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); |
3580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); |
3581 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); |
3582 | /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ |
3583 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); |
3584 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); |
3585 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); |
3586 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); |
3587 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); |
3588 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); |
3589 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); |
3590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); |
3591 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); |
3592 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); |
3593 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); |
3594 | /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ |
3595 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); |
3596 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); |
3597 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); |
3598 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); |
3599 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); |
3600 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); |
3601 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); |
3602 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); |
3603 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); |
3604 | |
3605 | /* |
3606 | * Some devices may pass our check in pci_intx_mask_supported() if |
3607 | * PCI_COMMAND_INTX_DISABLE works though they actually do not properly |
3608 | * support this feature. |
3609 | */ |
3610 | static void quirk_broken_intx_masking(struct pci_dev *dev) |
3611 | { |
3612 | dev->broken_intx_masking = 1; |
3613 | } |
3614 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, |
3615 | quirk_broken_intx_masking); |
3616 | DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ |
3617 | quirk_broken_intx_masking); |
3618 | DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ |
3619 | quirk_broken_intx_masking); |
3620 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, |
3621 | quirk_broken_intx_masking); |
3622 | |
3623 | /* |
3624 | * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) |
3625 | * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC |
3626 | * |
3627 | * RTL8110SC - Fails under PCI device assignment using DisINTx masking. |
3628 | */ |
3629 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, |
3630 | quirk_broken_intx_masking); |
3631 | |
3632 | /* |
3633 | * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, |
3634 | * DisINTx can be set but the interrupt status bit is non-functional. |
3635 | */ |
3636 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); |
3637 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); |
3638 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); |
3639 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); |
3640 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); |
3641 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); |
3642 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); |
3643 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); |
3644 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); |
3645 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); |
3646 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); |
3647 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); |
3648 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); |
3649 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); |
3650 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); |
3651 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); |
3652 | |
3653 | static u16 mellanox_broken_intx_devs[] = { |
3654 | PCI_DEVICE_ID_MELLANOX_HERMON_SDR, |
3655 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR, |
3656 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR, |
3657 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, |
3658 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, |
3659 | PCI_DEVICE_ID_MELLANOX_HERMON_EN, |
3660 | PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, |
3661 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, |
3662 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, |
3663 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, |
3664 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, |
3665 | PCI_DEVICE_ID_MELLANOX_CONNECTX2, |
3666 | PCI_DEVICE_ID_MELLANOX_CONNECTX3, |
3667 | PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, |
3668 | }; |
3669 | |
3670 | #define CONNECTX_4_CURR_MAX_MINOR 99 |
3671 | #define CONNECTX_4_INTX_SUPPORT_MINOR 14 |
3672 | |
3673 | /* |
3674 | * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. |
3675 | * If so, don't mark it as broken. |
3676 | * FW minor > 99 means older FW version format and no INTx masking support. |
3677 | * FW minor < 14 means new FW version format and no INTx masking support. |
3678 | */ |
3679 | static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) |
3680 | { |
3681 | __be32 __iomem *fw_ver; |
3682 | u16 fw_major; |
3683 | u16 fw_minor; |
3684 | u16 fw_subminor; |
3685 | u32 fw_maj_min; |
3686 | u32 fw_sub_min; |
3687 | int i; |
3688 | |
3689 | for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { |
3690 | if (pdev->device == mellanox_broken_intx_devs[i]) { |
3691 | pdev->broken_intx_masking = 1; |
3692 | return; |
3693 | } |
3694 | } |
3695 | |
3696 | /* |
3697 | * Getting here means Connect-IB cards and up. Connect-IB has no INTx |
3698 | * support so shouldn't be checked further |
3699 | */ |
3700 | if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) |
3701 | return; |
3702 | |
3703 | if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && |
3704 | pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) |
3705 | return; |
3706 | |
3707 | /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ |
3708 | if (pci_enable_device_mem(dev: pdev)) { |
3709 | pci_warn(pdev, "Can't enable device memory\n"); |
3710 | return; |
3711 | } |
3712 | |
3713 | fw_ver = ioremap(pci_resource_start(pdev, 0), size: 4); |
3714 | if (!fw_ver) { |
3715 | pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); |
3716 | goto out; |
3717 | } |
3718 | |
3719 | /* Reading from resource space should be 32b aligned */ |
3720 | fw_maj_min = ioread32be(fw_ver); |
3721 | fw_sub_min = ioread32be(fw_ver + 1); |
3722 | fw_major = fw_maj_min & 0xffff; |
3723 | fw_minor = fw_maj_min >> 16; |
3724 | fw_subminor = fw_sub_min & 0xffff; |
3725 | if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || |
3726 | fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { |
3727 | pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", |
3728 | fw_major, fw_minor, fw_subminor, pdev->device == |
3729 | PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); |
3730 | pdev->broken_intx_masking = 1; |
3731 | } |
3732 | |
3733 | iounmap(addr: fw_ver); |
3734 | |
3735 | out: |
3736 | pci_disable_device(dev: pdev); |
3737 | } |
3738 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, |
3739 | mellanox_check_broken_intx_masking); |
3740 | |
3741 | static void quirk_no_bus_reset(struct pci_dev *dev) |
3742 | { |
3743 | dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; |
3744 | } |
3745 | |
3746 | /* |
3747 | * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be |
3748 | * prevented for those affected devices. |
3749 | */ |
3750 | static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) |
3751 | { |
3752 | if ((dev->device & 0xffc0) == 0x2340) |
3753 | quirk_no_bus_reset(dev); |
3754 | } |
3755 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
3756 | quirk_nvidia_no_bus_reset); |
3757 | |
3758 | /* |
3759 | * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. |
3760 | * The device will throw a Link Down error on AER-capable systems and |
3761 | * regardless of AER, config space of the device is never accessible again |
3762 | * and typically causes the system to hang or reset when access is attempted. |
3763 | * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ |
3764 | */ |
3765 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); |
3766 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); |
3767 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); |
3768 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); |
3769 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); |
3770 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); |
3771 | |
3772 | /* |
3773 | * Root port on some Cavium CN8xxx chips do not successfully complete a bus |
3774 | * reset when used with certain child devices. After the reset, config |
3775 | * accesses to the child may fail. |
3776 | */ |
3777 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); |
3778 | |
3779 | /* |
3780 | * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS |
3781 | * automatically disables LTSSM when Secondary Bus Reset is received and |
3782 | * the device stops working. Prevent bus reset for these devices. With |
3783 | * this change, the device can be assigned to VMs with VFIO, but it will |
3784 | * leak state between VMs. Reference |
3785 | * https://e2e.ti.com/support/processors/f/791/t/954382 |
3786 | */ |
3787 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); |
3788 | |
3789 | static void quirk_no_pm_reset(struct pci_dev *dev) |
3790 | { |
3791 | /* |
3792 | * We can't do a bus reset on root bus devices, but an ineffective |
3793 | * PM reset may be better than nothing. |
3794 | */ |
3795 | if (!pci_is_root_bus(pbus: dev->bus)) |
3796 | dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; |
3797 | } |
3798 | |
3799 | /* |
3800 | * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition |
3801 | * causes a reset (i.e., they advertise NoSoftRst-). This transition seems |
3802 | * to have no effect on the device: it retains the framebuffer contents and |
3803 | * monitor sync. Advertising this support makes other layers, like VFIO, |
3804 | * assume pci_reset_function() is viable for this device. Mark it as |
3805 | * unavailable to skip it when testing reset methods. |
3806 | */ |
3807 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
3808 | PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); |
3809 | |
3810 | /* |
3811 | * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset |
3812 | * (i.e., they advertise NoSoftRst-). However, this transition does not have |
3813 | * any effect on the device: It continues to be operational and network ports |
3814 | * remain up. Advertising this support makes it seem as if a PM reset is viable |
3815 | * for these devices. Mark it as unavailable to skip it when testing reset |
3816 | * methods. |
3817 | */ |
3818 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); |
3819 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); |
3820 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); |
3821 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); |
3822 | |
3823 | /* |
3824 | * Thunderbolt controllers with broken MSI hotplug signaling: |
3825 | * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part |
3826 | * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). |
3827 | */ |
3828 | static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) |
3829 | { |
3830 | if (pdev->is_hotplug_bridge && |
3831 | (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || |
3832 | pdev->revision <= 1)) |
3833 | pdev->no_msi = 1; |
3834 | } |
3835 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, |
3836 | quirk_thunderbolt_hotplug_msi); |
3837 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, |
3838 | quirk_thunderbolt_hotplug_msi); |
3839 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, |
3840 | quirk_thunderbolt_hotplug_msi); |
3841 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, |
3842 | quirk_thunderbolt_hotplug_msi); |
3843 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, |
3844 | quirk_thunderbolt_hotplug_msi); |
3845 | |
3846 | #ifdef CONFIG_ACPI |
3847 | /* |
3848 | * Apple: Shutdown Cactus Ridge Thunderbolt controller. |
3849 | * |
3850 | * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be |
3851 | * shutdown before suspend. Otherwise the native host interface (NHI) will not |
3852 | * be present after resume if a device was plugged in before suspend. |
3853 | * |
3854 | * The Thunderbolt controller consists of a PCIe switch with downstream |
3855 | * bridges leading to the NHI and to the tunnel PCI bridges. |
3856 | * |
3857 | * This quirk cuts power to the whole chip. Therefore we have to apply it |
3858 | * during suspend_noirq of the upstream bridge. |
3859 | * |
3860 | * Power is automagically restored before resume. No action is needed. |
3861 | */ |
3862 | static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) |
3863 | { |
3864 | acpi_handle bridge, SXIO, SXFP, SXLV; |
3865 | |
3866 | if (!x86_apple_machine) |
3867 | return; |
3868 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) |
3869 | return; |
3870 | |
3871 | /* |
3872 | * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. |
3873 | * We don't know how to turn it back on again, but firmware does, |
3874 | * so we can only use SXIO/SXFP/SXLF if we're suspending via |
3875 | * firmware. |
3876 | */ |
3877 | if (!pm_suspend_via_firmware()) |
3878 | return; |
3879 | |
3880 | bridge = ACPI_HANDLE(&dev->dev); |
3881 | if (!bridge) |
3882 | return; |
3883 | |
3884 | /* |
3885 | * SXIO and SXLV are present only on machines requiring this quirk. |
3886 | * Thunderbolt bridges in external devices might have the same |
3887 | * device ID as those on the host, but they will not have the |
3888 | * associated ACPI methods. This implicitly checks that we are at |
3889 | * the right bridge. |
3890 | */ |
3891 | if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) |
3892 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) |
3893 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) |
3894 | return; |
3895 | pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); |
3896 | |
3897 | /* magic sequence */ |
3898 | acpi_execute_simple_method(handle: SXIO, NULL, arg: 1); |
3899 | acpi_execute_simple_method(handle: SXFP, NULL, arg: 0); |
3900 | msleep(msecs: 300); |
3901 | acpi_execute_simple_method(handle: SXLV, NULL, arg: 0); |
3902 | acpi_execute_simple_method(handle: SXIO, NULL, arg: 0); |
3903 | acpi_execute_simple_method(handle: SXLV, NULL, arg: 0); |
3904 | } |
3905 | DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, |
3906 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, |
3907 | quirk_apple_poweroff_thunderbolt); |
3908 | #endif |
3909 | |
3910 | /* |
3911 | * Following are device-specific reset methods which can be used to |
3912 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are |
3913 | * not available. |
3914 | */ |
3915 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) |
3916 | { |
3917 | /* |
3918 | * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf |
3919 | * |
3920 | * The 82599 supports FLR on VFs, but FLR support is reported only |
3921 | * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). |
3922 | * Thus we must call pcie_flr() directly without first checking if it is |
3923 | * supported. |
3924 | */ |
3925 | if (!probe) |
3926 | pcie_flr(dev); |
3927 | return 0; |
3928 | } |
3929 | |
3930 | #define SOUTH_CHICKEN2 0xc2004 |
3931 | #define PCH_PP_STATUS 0xc7200 |
3932 | #define PCH_PP_CONTROL 0xc7204 |
3933 | #define MSG_CTL 0x45010 |
3934 | #define NSDE_PWR_STATE 0xd0100 |
3935 | #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ |
3936 | |
3937 | static int reset_ivb_igd(struct pci_dev *dev, bool probe) |
3938 | { |
3939 | void __iomem *mmio_base; |
3940 | unsigned long timeout; |
3941 | u32 val; |
3942 | |
3943 | if (probe) |
3944 | return 0; |
3945 | |
3946 | mmio_base = pci_iomap(dev, bar: 0, max: 0); |
3947 | if (!mmio_base) |
3948 | return -ENOMEM; |
3949 | |
3950 | iowrite32(0x00000002, mmio_base + MSG_CTL); |
3951 | |
3952 | /* |
3953 | * Clobbering SOUTH_CHICKEN2 register is fine only if the next |
3954 | * driver loaded sets the right bits. However, this's a reset and |
3955 | * the bits have been set by i915 previously, so we clobber |
3956 | * SOUTH_CHICKEN2 register directly here. |
3957 | */ |
3958 | iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); |
3959 | |
3960 | val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; |
3961 | iowrite32(val, mmio_base + PCH_PP_CONTROL); |
3962 | |
3963 | timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); |
3964 | do { |
3965 | val = ioread32(mmio_base + PCH_PP_STATUS); |
3966 | if ((val & 0xb0000000) == 0) |
3967 | goto reset_complete; |
3968 | msleep(msecs: 10); |
3969 | } while (time_before(jiffies, timeout)); |
3970 | pci_warn(dev, "timeout during reset\n"); |
3971 | |
3972 | reset_complete: |
3973 | iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); |
3974 | |
3975 | pci_iounmap(dev, mmio_base); |
3976 | return 0; |
3977 | } |
3978 | |
3979 | /* Device-specific reset method for Chelsio T4-based adapters */ |
3980 | static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) |
3981 | { |
3982 | u16 old_command; |
3983 | u16 msix_flags; |
3984 | |
3985 | /* |
3986 | * If this isn't a Chelsio T4-based device, return -ENOTTY indicating |
3987 | * that we have no device-specific reset method. |
3988 | */ |
3989 | if ((dev->device & 0xf000) != 0x4000) |
3990 | return -ENOTTY; |
3991 | |
3992 | /* |
3993 | * If this is the "probe" phase, return 0 indicating that we can |
3994 | * reset this device. |
3995 | */ |
3996 | if (probe) |
3997 | return 0; |
3998 | |
3999 | /* |
4000 | * T4 can wedge if there are DMAs in flight within the chip and Bus |
4001 | * Master has been disabled. We need to have it on till the Function |
4002 | * Level Reset completes. (BUS_MASTER is disabled in |
4003 | * pci_reset_function()). |
4004 | */ |
4005 | pci_read_config_word(dev, PCI_COMMAND, val: &old_command); |
4006 | pci_write_config_word(dev, PCI_COMMAND, |
4007 | val: old_command | PCI_COMMAND_MASTER); |
4008 | |
4009 | /* |
4010 | * Perform the actual device function reset, saving and restoring |
4011 | * configuration information around the reset. |
4012 | */ |
4013 | pci_save_state(dev); |
4014 | |
4015 | /* |
4016 | * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts |
4017 | * are disabled when an MSI-X interrupt message needs to be delivered. |
4018 | * So we briefly re-enable MSI-X interrupts for the duration of the |
4019 | * FLR. The pci_restore_state() below will restore the original |
4020 | * MSI-X state. |
4021 | */ |
4022 | pci_read_config_word(dev, where: dev->msix_cap+PCI_MSIX_FLAGS, val: &msix_flags); |
4023 | if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) |
4024 | pci_write_config_word(dev, where: dev->msix_cap+PCI_MSIX_FLAGS, |
4025 | val: msix_flags | |
4026 | PCI_MSIX_FLAGS_ENABLE | |
4027 | PCI_MSIX_FLAGS_MASKALL); |
4028 | |
4029 | pcie_flr(dev); |
4030 | |
4031 | /* |
4032 | * Restore the configuration information (BAR values, etc.) including |
4033 | * the original PCI Configuration Space Command word, and return |
4034 | * success. |
4035 | */ |
4036 | pci_restore_state(dev); |
4037 | pci_write_config_word(dev, PCI_COMMAND, val: old_command); |
4038 | return 0; |
4039 | } |
4040 | |
4041 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
4042 | #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 |
4043 | #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 |
4044 | |
4045 | /* |
4046 | * The Samsung SM961/PM961 controller can sometimes enter a fatal state after |
4047 | * FLR where config space reads from the device return -1. We seem to be |
4048 | * able to avoid this condition if we disable the NVMe controller prior to |
4049 | * FLR. This quirk is generic for any NVMe class device requiring similar |
4050 | * assistance to quiesce the device prior to FLR. |
4051 | * |
4052 | * NVMe specification: https://nvmexpress.org/resources/specifications/ |
4053 | * Revision 1.0e: |
4054 | * Chapter 2: Required and optional PCI config registers |
4055 | * Chapter 3: NVMe control registers |
4056 | * Chapter 7.3: Reset behavior |
4057 | */ |
4058 | static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) |
4059 | { |
4060 | void __iomem *bar; |
4061 | u16 cmd; |
4062 | u32 cfg; |
4063 | |
4064 | if (dev->class != PCI_CLASS_STORAGE_EXPRESS || |
4065 | pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) |
4066 | return -ENOTTY; |
4067 | |
4068 | if (probe) |
4069 | return 0; |
4070 | |
4071 | bar = pci_iomap(dev, bar: 0, max: NVME_REG_CC + sizeof(cfg)); |
4072 | if (!bar) |
4073 | return -ENOTTY; |
4074 | |
4075 | pci_read_config_word(dev, PCI_COMMAND, val: &cmd); |
4076 | pci_write_config_word(dev, PCI_COMMAND, val: cmd | PCI_COMMAND_MEMORY); |
4077 | |
4078 | cfg = readl(addr: bar + NVME_REG_CC); |
4079 | |
4080 | /* Disable controller if enabled */ |
4081 | if (cfg & NVME_CC_ENABLE) { |
4082 | u32 cap = readl(addr: bar + NVME_REG_CAP); |
4083 | unsigned long timeout; |
4084 | |
4085 | /* |
4086 | * Per nvme_disable_ctrl() skip shutdown notification as it |
4087 | * could complete commands to the admin queue. We only intend |
4088 | * to quiesce the device before reset. |
4089 | */ |
4090 | cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); |
4091 | |
4092 | writel(val: cfg, addr: bar + NVME_REG_CC); |
4093 | |
4094 | /* |
4095 | * Some controllers require an additional delay here, see |
4096 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet |
4097 | * supported by this quirk. |
4098 | */ |
4099 | |
4100 | /* Cap register provides max timeout in 500ms increments */ |
4101 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; |
4102 | |
4103 | for (;;) { |
4104 | u32 status = readl(addr: bar + NVME_REG_CSTS); |
4105 | |
4106 | /* Ready status becomes zero on disable complete */ |
4107 | if (!(status & NVME_CSTS_RDY)) |
4108 | break; |
4109 | |
4110 | msleep(msecs: 100); |
4111 | |
4112 | if (time_after(jiffies, timeout)) { |
4113 | pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); |
4114 | break; |
4115 | } |
4116 | } |
4117 | } |
4118 | |
4119 | pci_iounmap(dev, bar); |
4120 | |
4121 | pcie_flr(dev); |
4122 | |
4123 | return 0; |
4124 | } |
4125 | |
4126 | /* |
4127 | * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will |
4128 | * timeout waiting for ready status to change after NVMe enable if the driver |
4129 | * starts interacting with the device too soon after FLR. A 250ms delay after |
4130 | * FLR has heuristically proven to produce reliably working results for device |
4131 | * assignment cases. |
4132 | */ |
4133 | static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) |
4134 | { |
4135 | if (probe) |
4136 | return pcie_reset_flr(dev, PCI_RESET_PROBE); |
4137 | |
4138 | pcie_reset_flr(dev, PCI_RESET_DO_RESET); |
4139 | |
4140 | msleep(msecs: 250); |
4141 | |
4142 | return 0; |
4143 | } |
4144 | |
4145 | #define PCI_DEVICE_ID_HINIC_VF 0x375E |
4146 | #define HINIC_VF_FLR_TYPE 0x1000 |
4147 | #define HINIC_VF_FLR_CAP_BIT (1UL << 30) |
4148 | #define HINIC_VF_OP 0xE80 |
4149 | #define HINIC_VF_FLR_PROC_BIT (1UL << 18) |
4150 | #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ |
4151 | |
4152 | /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ |
4153 | static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) |
4154 | { |
4155 | unsigned long timeout; |
4156 | void __iomem *bar; |
4157 | u32 val; |
4158 | |
4159 | if (probe) |
4160 | return 0; |
4161 | |
4162 | bar = pci_iomap(dev: pdev, bar: 0, max: 0); |
4163 | if (!bar) |
4164 | return -ENOTTY; |
4165 | |
4166 | /* Get and check firmware capabilities */ |
4167 | val = ioread32be(bar + HINIC_VF_FLR_TYPE); |
4168 | if (!(val & HINIC_VF_FLR_CAP_BIT)) { |
4169 | pci_iounmap(dev: pdev, bar); |
4170 | return -ENOTTY; |
4171 | } |
4172 | |
4173 | /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ |
4174 | val = ioread32be(bar + HINIC_VF_OP); |
4175 | val = val | HINIC_VF_FLR_PROC_BIT; |
4176 | iowrite32be(val, bar + HINIC_VF_OP); |
4177 | |
4178 | pcie_flr(dev: pdev); |
4179 | |
4180 | /* |
4181 | * The device must recapture its Bus and Device Numbers after FLR |
4182 | * in order generate Completions. Issue a config write to let the |
4183 | * device capture this information. |
4184 | */ |
4185 | pci_write_config_word(dev: pdev, PCI_VENDOR_ID, val: 0); |
4186 | |
4187 | /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ |
4188 | timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); |
4189 | do { |
4190 | val = ioread32be(bar + HINIC_VF_OP); |
4191 | if (!(val & HINIC_VF_FLR_PROC_BIT)) |
4192 | goto reset_complete; |
4193 | msleep(msecs: 20); |
4194 | } while (time_before(jiffies, timeout)); |
4195 | |
4196 | val = ioread32be(bar + HINIC_VF_OP); |
4197 | if (!(val & HINIC_VF_FLR_PROC_BIT)) |
4198 | goto reset_complete; |
4199 | |
4200 | pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); |
4201 | |
4202 | reset_complete: |
4203 | pci_iounmap(dev: pdev, bar); |
4204 | |
4205 | return 0; |
4206 | } |
4207 | |
4208 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
4209 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
4210 | reset_intel_82599_sfp_virtfn }, |
4211 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, |
4212 | reset_ivb_igd }, |
4213 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, |
4214 | reset_ivb_igd }, |
4215 | { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, |
4216 | { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, |
4217 | { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, |
4218 | { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, |
4219 | { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
4220 | reset_chelsio_generic_dev }, |
4221 | { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, |
4222 | reset_hinic_vf_dev }, |
4223 | { 0 } |
4224 | }; |
4225 | |
4226 | /* |
4227 | * These device-specific reset methods are here rather than in a driver |
4228 | * because when a host assigns a device to a guest VM, the host may need |
4229 | * to reset the device but probably doesn't have a driver for it. |
4230 | */ |
4231 | int pci_dev_specific_reset(struct pci_dev *dev, bool probe) |
4232 | { |
4233 | const struct pci_dev_reset_methods *i; |
4234 | |
4235 | for (i = pci_dev_reset_methods; i->reset; i++) { |
4236 | if ((i->vendor == dev->vendor || |
4237 | i->vendor == (u16)PCI_ANY_ID) && |
4238 | (i->device == dev->device || |
4239 | i->device == (u16)PCI_ANY_ID)) |
4240 | return i->reset(dev, probe); |
4241 | } |
4242 | |
4243 | return -ENOTTY; |
4244 | } |
4245 | |
4246 | static void quirk_dma_func0_alias(struct pci_dev *dev) |
4247 | { |
4248 | if (PCI_FUNC(dev->devfn) != 0) |
4249 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), nr_devfns: 1); |
4250 | } |
4251 | |
4252 | /* |
4253 | * https://bugzilla.redhat.com/show_bug.cgi?id=605888 |
4254 | * |
4255 | * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. |
4256 | */ |
4257 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); |
4258 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); |
4259 | |
4260 | /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ |
4261 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); |
4262 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); |
4263 | |
4264 | static void quirk_dma_func1_alias(struct pci_dev *dev) |
4265 | { |
4266 | if (PCI_FUNC(dev->devfn) != 1) |
4267 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), nr_devfns: 1); |
4268 | } |
4269 | |
4270 | /* |
4271 | * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some |
4272 | * SKUs function 1 is present and is a legacy IDE controller, in other |
4273 | * SKUs this function is not present, making this a ghost requester. |
4274 | * https://bugzilla.kernel.org/show_bug.cgi?id=42679 |
4275 | */ |
4276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, |
4277 | quirk_dma_func1_alias); |
4278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, |
4279 | quirk_dma_func1_alias); |
4280 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ |
4281 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, |
4282 | quirk_dma_func1_alias); |
4283 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, |
4284 | quirk_dma_func1_alias); |
4285 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ |
4286 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, |
4287 | quirk_dma_func1_alias); |
4288 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, |
4289 | quirk_dma_func1_alias); |
4290 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ |
4291 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, |
4292 | quirk_dma_func1_alias); |
4293 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ |
4294 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, |
4295 | quirk_dma_func1_alias); |
4296 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ |
4297 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, |
4298 | quirk_dma_func1_alias); |
4299 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ |
4300 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, |
4301 | quirk_dma_func1_alias); |
4302 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ |
4303 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, |
4304 | quirk_dma_func1_alias); |
4305 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ |
4306 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, |
4307 | quirk_dma_func1_alias); |
4308 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ |
4309 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, |
4310 | quirk_dma_func1_alias); |
4311 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ |
4312 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, |
4313 | quirk_dma_func1_alias); |
4314 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, |
4315 | quirk_dma_func1_alias); |
4316 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, |
4317 | quirk_dma_func1_alias); |
4318 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, |
4319 | quirk_dma_func1_alias); |
4320 | /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ |
4321 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, |
4322 | PCI_DEVICE_ID_JMICRON_JMB388_ESD, |
4323 | quirk_dma_func1_alias); |
4324 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ |
4325 | DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ |
4326 | 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ |
4327 | quirk_dma_func1_alias); |
4328 | |
4329 | /* |
4330 | * Some devices DMA with the wrong devfn, not just the wrong function. |
4331 | * quirk_fixed_dma_alias() uses this table to create fixed aliases, where |
4332 | * the alias is "fixed" and independent of the device devfn. |
4333 | * |
4334 | * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O |
4335 | * processor. To software, this appears as a PCIe-to-PCI/X bridge with a |
4336 | * single device on the secondary bus. In reality, the single exposed |
4337 | * device at 0e.0 is the Address Translation Unit (ATU) of the controller |
4338 | * that provides a bridge to the internal bus of the I/O processor. The |
4339 | * controller supports private devices, which can be hidden from PCI config |
4340 | * space. In the case of the Adaptec 3405, a private device at 01.0 |
4341 | * appears to be the DMA engine, which therefore needs to become a DMA |
4342 | * alias for the device. |
4343 | */ |
4344 | static const struct pci_device_id fixed_dma_alias_tbl[] = { |
4345 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, |
4346 | PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ |
4347 | .driver_data = PCI_DEVFN(1, 0) }, |
4348 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, |
4349 | PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ |
4350 | .driver_data = PCI_DEVFN(1, 0) }, |
4351 | { 0 } |
4352 | }; |
4353 | |
4354 | static void quirk_fixed_dma_alias(struct pci_dev *dev) |
4355 | { |
4356 | const struct pci_device_id *id; |
4357 | |
4358 | id = pci_match_id(ids: fixed_dma_alias_tbl, dev); |
4359 | if (id) |
4360 | pci_add_dma_alias(dev, devfn_from: id->driver_data, nr_devfns: 1); |
4361 | } |
4362 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); |
4363 | |
4364 | /* |
4365 | * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in |
4366 | * using the wrong DMA alias for the device. Some of these devices can be |
4367 | * used as either forward or reverse bridges, so we need to test whether the |
4368 | * device is operating in the correct mode. We could probably apply this |
4369 | * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test |
4370 | * is for a non-root, non-PCIe bridge where the upstream device is PCIe and |
4371 | * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. |
4372 | */ |
4373 | static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) |
4374 | { |
4375 | if (!pci_is_root_bus(pbus: pdev->bus) && |
4376 | pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && |
4377 | !pci_is_pcie(dev: pdev) && pci_is_pcie(dev: pdev->bus->self) && |
4378 | pci_pcie_type(dev: pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) |
4379 | pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; |
4380 | } |
4381 | /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ |
4382 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, |
4383 | quirk_use_pcie_bridge_dma_alias); |
4384 | /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ |
4385 | DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); |
4386 | /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ |
4387 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); |
4388 | /* ITE 8893 has the same problem as the 8892 */ |
4389 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); |
4390 | /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ |
4391 | DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); |
4392 | |
4393 | /* |
4394 | * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to |
4395 | * be added as aliases to the DMA device in order to allow buffer access |
4396 | * when IOMMU is enabled. Following devfns have to match RIT-LUT table |
4397 | * programmed in the EEPROM. |
4398 | */ |
4399 | static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) |
4400 | { |
4401 | pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x10, 0x0), nr_devfns: 1); |
4402 | pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x11, 0x0), nr_devfns: 1); |
4403 | pci_add_dma_alias(dev: pdev, PCI_DEVFN(0x12, 0x3), nr_devfns: 1); |
4404 | } |
4405 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); |
4406 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); |
4407 | |
4408 | /* |
4409 | * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices |
4410 | * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). |
4411 | * |
4412 | * Similarly to MIC x200, we need to add DMA aliases to allow buffer access |
4413 | * when IOMMU is enabled. These aliases allow computational unit access to |
4414 | * host memory. These aliases mark the whole VCA device as one IOMMU |
4415 | * group. |
4416 | * |
4417 | * All possible slot numbers (0x20) are used, since we are unable to tell |
4418 | * what slot is used on other side. This quirk is intended for both host |
4419 | * and computational unit sides. The VCA devices have up to five functions |
4420 | * (four for DMA channels and one additional). |
4421 | */ |
4422 | static void quirk_pex_vca_alias(struct pci_dev *pdev) |
4423 | { |
4424 | const unsigned int num_pci_slots = 0x20; |
4425 | unsigned int slot; |
4426 | |
4427 | for (slot = 0; slot < num_pci_slots; slot++) |
4428 | pci_add_dma_alias(dev: pdev, PCI_DEVFN(slot, 0x0), nr_devfns: 5); |
4429 | } |
4430 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); |
4431 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); |
4432 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); |
4433 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); |
4434 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); |
4435 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); |
4436 | |
4437 | /* |
4438 | * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are |
4439 | * associated not at the root bus, but at a bridge below. This quirk avoids |
4440 | * generating invalid DMA aliases. |
4441 | */ |
4442 | static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) |
4443 | { |
4444 | pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; |
4445 | } |
4446 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, |
4447 | quirk_bridge_cavm_thrx2_pcie_root); |
4448 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, |
4449 | quirk_bridge_cavm_thrx2_pcie_root); |
4450 | |
4451 | /* |
4452 | * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) |
4453 | * class code. Fix it. |
4454 | */ |
4455 | static void quirk_tw686x_class(struct pci_dev *pdev) |
4456 | { |
4457 | u32 class = pdev->class; |
4458 | |
4459 | /* Use "Multimedia controller" class */ |
4460 | pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; |
4461 | pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", |
4462 | class, pdev->class); |
4463 | } |
4464 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, |
4465 | quirk_tw686x_class); |
4466 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, |
4467 | quirk_tw686x_class); |
4468 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, |
4469 | quirk_tw686x_class); |
4470 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, |
4471 | quirk_tw686x_class); |
4472 | |
4473 | /* |
4474 | * Some devices have problems with Transaction Layer Packets with the Relaxed |
4475 | * Ordering Attribute set. Such devices should mark themselves and other |
4476 | * device drivers should check before sending TLPs with RO set. |
4477 | */ |
4478 | static void quirk_relaxedordering_disable(struct pci_dev *dev) |
4479 | { |
4480 | dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; |
4481 | pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); |
4482 | } |
4483 | |
4484 | /* |
4485 | * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root |
4486 | * Complex have a Flow Control Credit issue which can cause performance |
4487 | * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. |
4488 | */ |
4489 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, |
4490 | quirk_relaxedordering_disable); |
4491 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, |
4492 | quirk_relaxedordering_disable); |
4493 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, |
4494 | quirk_relaxedordering_disable); |
4495 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, |
4496 | quirk_relaxedordering_disable); |
4497 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, |
4498 | quirk_relaxedordering_disable); |
4499 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, |
4500 | quirk_relaxedordering_disable); |
4501 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, |
4502 | quirk_relaxedordering_disable); |
4503 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, |
4504 | quirk_relaxedordering_disable); |
4505 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, |
4506 | quirk_relaxedordering_disable); |
4507 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, |
4508 | quirk_relaxedordering_disable); |
4509 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, |
4510 | quirk_relaxedordering_disable); |
4511 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, |
4512 | quirk_relaxedordering_disable); |
4513 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, |
4514 | quirk_relaxedordering_disable); |
4515 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, |
4516 | quirk_relaxedordering_disable); |
4517 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, |
4518 | quirk_relaxedordering_disable); |
4519 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, |
4520 | quirk_relaxedordering_disable); |
4521 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, |
4522 | quirk_relaxedordering_disable); |
4523 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, |
4524 | quirk_relaxedordering_disable); |
4525 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, |
4526 | quirk_relaxedordering_disable); |
4527 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, |
4528 | quirk_relaxedordering_disable); |
4529 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, |
4530 | quirk_relaxedordering_disable); |
4531 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, |
4532 | quirk_relaxedordering_disable); |
4533 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, |
4534 | quirk_relaxedordering_disable); |
4535 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, |
4536 | quirk_relaxedordering_disable); |
4537 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, |
4538 | quirk_relaxedordering_disable); |
4539 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, |
4540 | quirk_relaxedordering_disable); |
4541 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, |
4542 | quirk_relaxedordering_disable); |
4543 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, |
4544 | quirk_relaxedordering_disable); |
4545 | |
4546 | /* |
4547 | * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex |
4548 | * where Upstream Transaction Layer Packets with the Relaxed Ordering |
4549 | * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering |
4550 | * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules |
4551 | * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 |
4552 | * November 10, 2010). As a result, on this platform we can't use Relaxed |
4553 | * Ordering for Upstream TLPs. |
4554 | */ |
4555 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, |
4556 | quirk_relaxedordering_disable); |
4557 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, |
4558 | quirk_relaxedordering_disable); |
4559 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, |
4560 | quirk_relaxedordering_disable); |
4561 | |
4562 | /* |
4563 | * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same |
4564 | * values for the Attribute as were supplied in the header of the |
4565 | * corresponding Request, except as explicitly allowed when IDO is used." |
4566 | * |
4567 | * If a non-compliant device generates a completion with a different |
4568 | * attribute than the request, the receiver may accept it (which itself |
4569 | * seems non-compliant based on sec 2.3.2), or it may handle it as a |
4570 | * Malformed TLP or an Unexpected Completion, which will probably lead to a |
4571 | * device access timeout. |
4572 | * |
4573 | * If the non-compliant device generates completions with zero attributes |
4574 | * (instead of copying the attributes from the request), we can work around |
4575 | * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in |
4576 | * upstream devices so they always generate requests with zero attributes. |
4577 | * |
4578 | * This affects other devices under the same Root Port, but since these |
4579 | * attributes are performance hints, there should be no functional problem. |
4580 | * |
4581 | * Note that Configuration Space accesses are never supposed to have TLP |
4582 | * Attributes, so we're safe waiting till after any Configuration Space |
4583 | * accesses to do the Root Port fixup. |
4584 | */ |
4585 | static void quirk_disable_root_port_attributes(struct pci_dev *pdev) |
4586 | { |
4587 | struct pci_dev *root_port = pcie_find_root_port(dev: pdev); |
4588 | |
4589 | if (!root_port) { |
4590 | pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); |
4591 | return; |
4592 | } |
4593 | |
4594 | pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", |
4595 | dev_name(&pdev->dev)); |
4596 | pcie_capability_clear_word(dev: root_port, PCI_EXP_DEVCTL, |
4597 | PCI_EXP_DEVCTL_RELAX_EN | |
4598 | PCI_EXP_DEVCTL_NOSNOOP_EN); |
4599 | } |
4600 | |
4601 | /* |
4602 | * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the |
4603 | * Completion it generates. |
4604 | */ |
4605 | static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) |
4606 | { |
4607 | /* |
4608 | * This mask/compare operation selects for Physical Function 4 on a |
4609 | * T5. We only need to fix up the Root Port once for any of the |
4610 | * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely |
4611 | * 0x54xx so we use that one. |
4612 | */ |
4613 | if ((pdev->device & 0xff00) == 0x5400) |
4614 | quirk_disable_root_port_attributes(pdev); |
4615 | } |
4616 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
4617 | quirk_chelsio_T5_disable_root_port_attributes); |
4618 | |
4619 | /* |
4620 | * pci_acs_ctrl_enabled - compare desired ACS controls with those provided |
4621 | * by a device |
4622 | * @acs_ctrl_req: Bitmask of desired ACS controls |
4623 | * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by |
4624 | * the hardware design |
4625 | * |
4626 | * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included |
4627 | * in @acs_ctrl_ena, i.e., the device provides all the access controls the |
4628 | * caller desires. Return 0 otherwise. |
4629 | */ |
4630 | static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) |
4631 | { |
4632 | if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) |
4633 | return 1; |
4634 | return 0; |
4635 | } |
4636 | |
4637 | /* |
4638 | * AMD has indicated that the devices below do not support peer-to-peer |
4639 | * in any system where they are found in the southbridge with an AMD |
4640 | * IOMMU in the system. Multifunction devices that do not support |
4641 | * peer-to-peer between functions can claim to support a subset of ACS. |
4642 | * Such devices effectively enable request redirect (RR) and completion |
4643 | * redirect (CR) since all transactions are redirected to the upstream |
4644 | * root complex. |
4645 | * |
4646 | * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ |
4647 | * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ |
4648 | * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ |
4649 | * |
4650 | * 1002:4385 SBx00 SMBus Controller |
4651 | * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller |
4652 | * 1002:4383 SBx00 Azalia (Intel HDA) |
4653 | * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller |
4654 | * 1002:4384 SBx00 PCI to PCI Bridge |
4655 | * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller |
4656 | * |
4657 | * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 |
4658 | * |
4659 | * 1022:780f [AMD] FCH PCI Bridge |
4660 | * 1022:7809 [AMD] FCH USB OHCI Controller |
4661 | */ |
4662 | static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) |
4663 | { |
4664 | #ifdef CONFIG_ACPI |
4665 | struct acpi_table_header *header = NULL; |
4666 | acpi_status status; |
4667 | |
4668 | /* Targeting multifunction devices on the SB (appears on root bus) */ |
4669 | if (!dev->multifunction || !pci_is_root_bus(pbus: dev->bus)) |
4670 | return -ENODEV; |
4671 | |
4672 | /* The IVRS table describes the AMD IOMMU */ |
4673 | status = acpi_get_table(signature: "IVRS", instance: 0, out_table: &header); |
4674 | if (ACPI_FAILURE(status)) |
4675 | return -ENODEV; |
4676 | |
4677 | acpi_put_table(table: header); |
4678 | |
4679 | /* Filter out flags not applicable to multifunction */ |
4680 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); |
4681 | |
4682 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, PCI_ACS_RR | PCI_ACS_CR); |
4683 | #else |
4684 | return -ENODEV; |
4685 | #endif |
4686 | } |
4687 | |
4688 | static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) |
4689 | { |
4690 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4691 | return false; |
4692 | |
4693 | switch (dev->device) { |
4694 | /* |
4695 | * Effectively selects all downstream ports for whole ThunderX1 |
4696 | * (which represents 8 SoCs). |
4697 | */ |
4698 | case 0xa000 ... 0xa7ff: /* ThunderX1 */ |
4699 | case 0xaf84: /* ThunderX2 */ |
4700 | case 0xb884: /* ThunderX3 */ |
4701 | return true; |
4702 | default: |
4703 | return false; |
4704 | } |
4705 | } |
4706 | |
4707 | static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) |
4708 | { |
4709 | if (!pci_quirk_cavium_acs_match(dev)) |
4710 | return -ENOTTY; |
4711 | |
4712 | /* |
4713 | * Cavium Root Ports don't advertise an ACS capability. However, |
4714 | * the RTL internally implements similar protection as if ACS had |
4715 | * Source Validation, Request Redirection, Completion Redirection, |
4716 | * and Upstream Forwarding features enabled. Assert that the |
4717 | * hardware implements and enables equivalent ACS functionality for |
4718 | * these flags. |
4719 | */ |
4720 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4721 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4722 | } |
4723 | |
4724 | static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) |
4725 | { |
4726 | /* |
4727 | * X-Gene Root Ports matching this quirk do not allow peer-to-peer |
4728 | * transactions with others, allowing masking out these bits as if they |
4729 | * were unimplemented in the ACS capability. |
4730 | */ |
4731 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4732 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4733 | } |
4734 | |
4735 | /* |
4736 | * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. |
4737 | * But the implementation could block peer-to-peer transactions between them |
4738 | * and provide ACS-like functionality. |
4739 | */ |
4740 | static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) |
4741 | { |
4742 | if (!pci_is_pcie(dev) || |
4743 | ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && |
4744 | (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) |
4745 | return -ENOTTY; |
4746 | |
4747 | /* |
4748 | * Future Zhaoxin Root Ports and Switch Downstream Ports will |
4749 | * implement ACS capability in accordance with the PCIe Spec. |
4750 | */ |
4751 | switch (dev->device) { |
4752 | case 0x0710 ... 0x071e: |
4753 | case 0x0721: |
4754 | case 0x0723 ... 0x0752: |
4755 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4756 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4757 | } |
4758 | |
4759 | return false; |
4760 | } |
4761 | |
4762 | /* |
4763 | * Many Intel PCH Root Ports do provide ACS-like features to disable peer |
4764 | * transactions and validate bus numbers in requests, but do not provide an |
4765 | * actual PCIe ACS capability. This is the list of device IDs known to fall |
4766 | * into that category as provided by Intel in Red Hat bugzilla 1037684. |
4767 | */ |
4768 | static const u16 pci_quirk_intel_pch_acs_ids[] = { |
4769 | /* Ibexpeak PCH */ |
4770 | 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, |
4771 | 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, |
4772 | /* Cougarpoint PCH */ |
4773 | 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, |
4774 | 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, |
4775 | /* Pantherpoint PCH */ |
4776 | 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, |
4777 | 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, |
4778 | /* Lynxpoint-H PCH */ |
4779 | 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, |
4780 | 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, |
4781 | /* Lynxpoint-LP PCH */ |
4782 | 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, |
4783 | 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, |
4784 | /* Wildcat PCH */ |
4785 | 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, |
4786 | 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, |
4787 | /* Patsburg (X79) PCH */ |
4788 | 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, |
4789 | /* Wellsburg (X99) PCH */ |
4790 | 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, |
4791 | 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, |
4792 | /* Lynx Point (9 series) PCH */ |
4793 | 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, |
4794 | }; |
4795 | |
4796 | static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) |
4797 | { |
4798 | int i; |
4799 | |
4800 | /* Filter out a few obvious non-matches first */ |
4801 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4802 | return false; |
4803 | |
4804 | for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) |
4805 | if (pci_quirk_intel_pch_acs_ids[i] == dev->device) |
4806 | return true; |
4807 | |
4808 | return false; |
4809 | } |
4810 | |
4811 | static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) |
4812 | { |
4813 | if (!pci_quirk_intel_pch_acs_match(dev)) |
4814 | return -ENOTTY; |
4815 | |
4816 | if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) |
4817 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4818 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4819 | |
4820 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, acs_ctrl_ena: 0); |
4821 | } |
4822 | |
4823 | /* |
4824 | * These QCOM Root Ports do provide ACS-like features to disable peer |
4825 | * transactions and validate bus numbers in requests, but do not provide an |
4826 | * actual PCIe ACS capability. Hardware supports source validation but it |
4827 | * will report the issue as Completer Abort instead of ACS Violation. |
4828 | * Hardware doesn't support peer-to-peer and each Root Port is a Root |
4829 | * Complex with unique segment numbers. It is not possible for one Root |
4830 | * Port to pass traffic to another Root Port. All PCIe transactions are |
4831 | * terminated inside the Root Port. |
4832 | */ |
4833 | static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) |
4834 | { |
4835 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4836 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4837 | } |
4838 | |
4839 | /* |
4840 | * Each of these NXP Root Ports is in a Root Complex with a unique segment |
4841 | * number and does provide isolation features to disable peer transactions |
4842 | * and validate bus numbers in requests, but does not provide an ACS |
4843 | * capability. |
4844 | */ |
4845 | static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) |
4846 | { |
4847 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4848 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4849 | } |
4850 | |
4851 | static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) |
4852 | { |
4853 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4854 | return -ENOTTY; |
4855 | |
4856 | /* |
4857 | * Amazon's Annapurna Labs root ports don't include an ACS capability, |
4858 | * but do include ACS-like functionality. The hardware doesn't support |
4859 | * peer-to-peer transactions via the root port and each has a unique |
4860 | * segment number. |
4861 | * |
4862 | * Additionally, the root ports cannot send traffic to each other. |
4863 | */ |
4864 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4865 | |
4866 | return acs_flags ? 0 : 1; |
4867 | } |
4868 | |
4869 | /* |
4870 | * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in |
4871 | * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, |
4872 | * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and |
4873 | * control registers whereas the PCIe spec packs them into words (Rev 3.0, |
4874 | * 7.16 ACS Extended Capability). The bit definitions are correct, but the |
4875 | * control register is at offset 8 instead of 6 and we should probably use |
4876 | * dword accesses to them. This applies to the following PCI Device IDs, as |
4877 | * found in volume 1 of the datasheet[2]: |
4878 | * |
4879 | * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} |
4880 | * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} |
4881 | * |
4882 | * N.B. This doesn't fix what lspci shows. |
4883 | * |
4884 | * The 100 series chipset specification update includes this as errata #23[3]. |
4885 | * |
4886 | * The 200 series chipset (Union Point) has the same bug according to the |
4887 | * specification update (Intel 200 Series Chipset Family Platform Controller |
4888 | * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, |
4889 | * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this |
4890 | * chipset include: |
4891 | * |
4892 | * 0xa290-0xa29f PCI Express Root port #{0-16} |
4893 | * 0xa2e7-0xa2ee PCI Express Root port #{17-24} |
4894 | * |
4895 | * Mobile chipsets are also affected, 7th & 8th Generation |
4896 | * Specification update confirms ACS errata 22, status no fix: (7th Generation |
4897 | * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel |
4898 | * Processor Family I/O for U Quad Core Platforms Specification Update, |
4899 | * August 2017, Revision 002, Document#: 334660-002)[6] |
4900 | * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O |
4901 | * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U |
4902 | * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] |
4903 | * |
4904 | * 0x9d10-0x9d1b PCI Express Root port #{1-12} |
4905 | * |
4906 | * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html |
4907 | * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html |
4908 | * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html |
4909 | * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html |
4910 | * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html |
4911 | * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html |
4912 | * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html |
4913 | */ |
4914 | static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) |
4915 | { |
4916 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4917 | return false; |
4918 | |
4919 | switch (dev->device) { |
4920 | case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ |
4921 | case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ |
4922 | case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ |
4923 | return true; |
4924 | } |
4925 | |
4926 | return false; |
4927 | } |
4928 | |
4929 | #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) |
4930 | |
4931 | static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) |
4932 | { |
4933 | int pos; |
4934 | u32 cap, ctrl; |
4935 | |
4936 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) |
4937 | return -ENOTTY; |
4938 | |
4939 | pos = dev->acs_cap; |
4940 | if (!pos) |
4941 | return -ENOTTY; |
4942 | |
4943 | /* see pci_acs_flags_enabled() */ |
4944 | pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap); |
4945 | acs_flags &= (cap | PCI_ACS_EC); |
4946 | |
4947 | pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl); |
4948 | |
4949 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, acs_ctrl_ena: ctrl); |
4950 | } |
4951 | |
4952 | static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) |
4953 | { |
4954 | /* |
4955 | * SV, TB, and UF are not relevant to multifunction endpoints. |
4956 | * |
4957 | * Multifunction devices are only required to implement RR, CR, and DT |
4958 | * in their ACS capability if they support peer-to-peer transactions. |
4959 | * Devices matching this quirk have been verified by the vendor to not |
4960 | * perform peer-to-peer with other functions, allowing us to mask out |
4961 | * these bits as if they were unimplemented in the ACS capability. |
4962 | */ |
4963 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4964 | PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | |
4965 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); |
4966 | } |
4967 | |
4968 | static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) |
4969 | { |
4970 | /* |
4971 | * Intel RCiEP's are required to allow p2p only on translated |
4972 | * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, |
4973 | * "Root-Complex Peer to Peer Considerations". |
4974 | */ |
4975 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) |
4976 | return -ENOTTY; |
4977 | |
4978 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4979 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4980 | } |
4981 | |
4982 | static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) |
4983 | { |
4984 | /* |
4985 | * iProc PAXB Root Ports don't advertise an ACS capability, but |
4986 | * they do not allow peer-to-peer transactions between Root Ports. |
4987 | * Allow each Root Port to be in a separate IOMMU group by masking |
4988 | * SV/RR/CR/UF bits. |
4989 | */ |
4990 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
4991 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
4992 | } |
4993 | |
4994 | static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) |
4995 | { |
4996 | /* |
4997 | * Loongson PCIe Root Ports don't advertise an ACS capability, but |
4998 | * they do not allow peer-to-peer transactions between Root Ports. |
4999 | * Allow each Root Port to be in a separate IOMMU group by masking |
5000 | * SV/RR/CR/UF bits. |
5001 | */ |
5002 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
5003 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
5004 | } |
5005 | |
5006 | /* |
5007 | * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on |
5008 | * multi-function devices, the hardware isolates the functions by |
5009 | * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and |
5010 | * PCI_ACS_CR were set. |
5011 | * SFxxx 1G NICs(em). |
5012 | * RP1000/RP2000 10G NICs(sp). |
5013 | * FF5xxx 40G/25G/10G NICs(aml). |
5014 | */ |
5015 | static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) |
5016 | { |
5017 | switch (dev->device) { |
5018 | case 0x0100 ... 0x010F: /* EM */ |
5019 | case 0x1001: case 0x2001: /* SP */ |
5020 | case 0x5010: case 0x5025: case 0x5040: /* AML */ |
5021 | case 0x5110: case 0x5125: case 0x5140: /* AML */ |
5022 | return pci_acs_ctrl_enabled(acs_ctrl_req: acs_flags, |
5023 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); |
5024 | } |
5025 | |
5026 | return false; |
5027 | } |
5028 | |
5029 | static const struct pci_dev_acs_enabled { |
5030 | u16 vendor; |
5031 | u16 device; |
5032 | int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); |
5033 | } pci_dev_acs_enabled[] = { |
5034 | { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, |
5035 | { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, |
5036 | { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, |
5037 | { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, |
5038 | { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, |
5039 | { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, |
5040 | { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, |
5041 | { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, |
5042 | { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, |
5043 | { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, |
5044 | { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, |
5045 | { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, |
5046 | { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, |
5047 | { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, |
5048 | { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, |
5049 | { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, |
5050 | { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, |
5051 | { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, |
5052 | { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, |
5053 | { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, |
5054 | { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, |
5055 | { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, |
5056 | { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, |
5057 | { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, |
5058 | { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, |
5059 | { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, |
5060 | { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, |
5061 | { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, |
5062 | { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, |
5063 | { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, |
5064 | { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, |
5065 | /* 82580 */ |
5066 | { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, |
5067 | { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, |
5068 | { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, |
5069 | { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, |
5070 | { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, |
5071 | { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, |
5072 | { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, |
5073 | /* 82576 */ |
5074 | { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, |
5075 | { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, |
5076 | { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, |
5077 | { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, |
5078 | { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, |
5079 | { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, |
5080 | { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, |
5081 | { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, |
5082 | /* 82575 */ |
5083 | { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, |
5084 | { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, |
5085 | { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, |
5086 | /* I350 */ |
5087 | { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, |
5088 | { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, |
5089 | { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, |
5090 | { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, |
5091 | /* 82571 (Quads omitted due to non-ACS switch) */ |
5092 | { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, |
5093 | { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, |
5094 | { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, |
5095 | { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, |
5096 | /* I219 */ |
5097 | { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, |
5098 | { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, |
5099 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, |
5100 | /* QCOM QDF2xxx root ports */ |
5101 | { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, |
5102 | { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, |
5103 | /* QCOM SA8775P root port */ |
5104 | { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, |
5105 | /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ |
5106 | { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, |
5107 | /* Intel PCH root ports */ |
5108 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, |
5109 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, |
5110 | { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ |
5111 | { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ |
5112 | /* Cavium ThunderX */ |
5113 | { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, |
5114 | /* Cavium multi-function devices */ |
5115 | { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, |
5116 | { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, |
5117 | { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, |
5118 | /* APM X-Gene */ |
5119 | { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, |
5120 | /* Ampere Computing */ |
5121 | { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, |
5122 | { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, |
5123 | { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, |
5124 | { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, |
5125 | { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, |
5126 | { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, |
5127 | { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, |
5128 | { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, |
5129 | /* Broadcom multi-function device */ |
5130 | { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, |
5131 | { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, |
5132 | { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, |
5133 | { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, |
5134 | { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, |
5135 | { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, |
5136 | { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, |
5137 | { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, |
5138 | { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, |
5139 | /* Loongson PCIe Root Ports */ |
5140 | { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, |
5141 | { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, |
5142 | { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, |
5143 | { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, |
5144 | { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, |
5145 | { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, |
5146 | { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, |
5147 | { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, |
5148 | { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, |
5149 | { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, |
5150 | /* Amazon Annapurna Labs */ |
5151 | { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, |
5152 | /* Zhaoxin multi-function devices */ |
5153 | { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, |
5154 | { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, |
5155 | { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, |
5156 | /* NXP root ports, xx=16, 12, or 08 cores */ |
5157 | /* LX2xx0A : without security features + CAN-FD */ |
5158 | { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, |
5159 | { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, |
5160 | { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, |
5161 | /* LX2xx0C : security features + CAN-FD */ |
5162 | { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, |
5163 | { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, |
5164 | { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, |
5165 | /* LX2xx0E : security features + CAN */ |
5166 | { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, |
5167 | { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, |
5168 | { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, |
5169 | /* LX2xx0N : without security features + CAN */ |
5170 | { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, |
5171 | { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, |
5172 | { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, |
5173 | /* LX2xx2A : without security features + CAN-FD */ |
5174 | { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, |
5175 | { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, |
5176 | { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, |
5177 | /* LX2xx2C : security features + CAN-FD */ |
5178 | { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, |
5179 | { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, |
5180 | { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, |
5181 | /* LX2xx2E : security features + CAN */ |
5182 | { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, |
5183 | { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, |
5184 | { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, |
5185 | /* LX2xx2N : without security features + CAN */ |
5186 | { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, |
5187 | { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, |
5188 | { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, |
5189 | /* Zhaoxin Root/Downstream Ports */ |
5190 | { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, |
5191 | /* Wangxun nics */ |
5192 | { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, |
5193 | { 0 } |
5194 | }; |
5195 | |
5196 | /* |
5197 | * pci_dev_specific_acs_enabled - check whether device provides ACS controls |
5198 | * @dev: PCI device |
5199 | * @acs_flags: Bitmask of desired ACS controls |
5200 | * |
5201 | * Returns: |
5202 | * -ENOTTY: No quirk applies to this device; we can't tell whether the |
5203 | * device provides the desired controls |
5204 | * 0: Device does not provide all the desired controls |
5205 | * >0: Device provides all the controls in @acs_flags |
5206 | */ |
5207 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) |
5208 | { |
5209 | const struct pci_dev_acs_enabled *i; |
5210 | int ret; |
5211 | |
5212 | /* |
5213 | * Allow devices that do not expose standard PCIe ACS capabilities |
5214 | * or control to indicate their support here. Multi-function express |
5215 | * devices which do not allow internal peer-to-peer between functions, |
5216 | * but do not implement PCIe ACS may wish to return true here. |
5217 | */ |
5218 | for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { |
5219 | if ((i->vendor == dev->vendor || |
5220 | i->vendor == (u16)PCI_ANY_ID) && |
5221 | (i->device == dev->device || |
5222 | i->device == (u16)PCI_ANY_ID)) { |
5223 | ret = i->acs_enabled(dev, acs_flags); |
5224 | if (ret >= 0) |
5225 | return ret; |
5226 | } |
5227 | } |
5228 | |
5229 | return -ENOTTY; |
5230 | } |
5231 | |
5232 | /* Config space offset of Root Complex Base Address register */ |
5233 | #define INTEL_LPC_RCBA_REG 0xf0 |
5234 | /* 31:14 RCBA address */ |
5235 | #define INTEL_LPC_RCBA_MASK 0xffffc000 |
5236 | /* RCBA Enable */ |
5237 | #define INTEL_LPC_RCBA_ENABLE (1 << 0) |
5238 | |
5239 | /* Backbone Scratch Pad Register */ |
5240 | #define INTEL_BSPR_REG 0x1104 |
5241 | /* Backbone Peer Non-Posted Disable */ |
5242 | #define INTEL_BSPR_REG_BPNPD (1 << 8) |
5243 | /* Backbone Peer Posted Disable */ |
5244 | #define INTEL_BSPR_REG_BPPD (1 << 9) |
5245 | |
5246 | /* Upstream Peer Decode Configuration Register */ |
5247 | #define INTEL_UPDCR_REG 0x1014 |
5248 | /* 5:0 Peer Decode Enable bits */ |
5249 | #define INTEL_UPDCR_REG_MASK 0x3f |
5250 | |
5251 | static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) |
5252 | { |
5253 | u32 rcba, bspr, updcr; |
5254 | void __iomem *rcba_mem; |
5255 | |
5256 | /* |
5257 | * Read the RCBA register from the LPC (D31:F0). PCH root ports |
5258 | * are D28:F* and therefore get probed before LPC, thus we can't |
5259 | * use pci_get_slot()/pci_read_config_dword() here. |
5260 | */ |
5261 | pci_bus_read_config_dword(bus: dev->bus, PCI_DEVFN(31, 0), |
5262 | INTEL_LPC_RCBA_REG, val: &rcba); |
5263 | if (!(rcba & INTEL_LPC_RCBA_ENABLE)) |
5264 | return -EINVAL; |
5265 | |
5266 | rcba_mem = ioremap(offset: rcba & INTEL_LPC_RCBA_MASK, |
5267 | PAGE_ALIGN(INTEL_UPDCR_REG)); |
5268 | if (!rcba_mem) |
5269 | return -ENOMEM; |
5270 | |
5271 | /* |
5272 | * The BSPR can disallow peer cycles, but it's set by soft strap and |
5273 | * therefore read-only. If both posted and non-posted peer cycles are |
5274 | * disallowed, we're ok. If either are allowed, then we need to use |
5275 | * the UPDCR to disable peer decodes for each port. This provides the |
5276 | * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF |
5277 | */ |
5278 | bspr = readl(addr: rcba_mem + INTEL_BSPR_REG); |
5279 | bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; |
5280 | if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { |
5281 | updcr = readl(addr: rcba_mem + INTEL_UPDCR_REG); |
5282 | if (updcr & INTEL_UPDCR_REG_MASK) { |
5283 | pci_info(dev, "Disabling UPDCR peer decodes\n"); |
5284 | updcr &= ~INTEL_UPDCR_REG_MASK; |
5285 | writel(val: updcr, addr: rcba_mem + INTEL_UPDCR_REG); |
5286 | } |
5287 | } |
5288 | |
5289 | iounmap(addr: rcba_mem); |
5290 | return 0; |
5291 | } |
5292 | |
5293 | /* Miscellaneous Port Configuration register */ |
5294 | #define INTEL_MPC_REG 0xd8 |
5295 | /* MPC: Invalid Receive Bus Number Check Enable */ |
5296 | #define INTEL_MPC_REG_IRBNCE (1 << 26) |
5297 | |
5298 | static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) |
5299 | { |
5300 | u32 mpc; |
5301 | |
5302 | /* |
5303 | * When enabled, the IRBNCE bit of the MPC register enables the |
5304 | * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which |
5305 | * ensures that requester IDs fall within the bus number range |
5306 | * of the bridge. Enable if not already. |
5307 | */ |
5308 | pci_read_config_dword(dev, INTEL_MPC_REG, val: &mpc); |
5309 | if (!(mpc & INTEL_MPC_REG_IRBNCE)) { |
5310 | pci_info(dev, "Enabling MPC IRBNCE\n"); |
5311 | mpc |= INTEL_MPC_REG_IRBNCE; |
5312 | pci_write_config_word(dev, INTEL_MPC_REG, val: mpc); |
5313 | } |
5314 | } |
5315 | |
5316 | /* |
5317 | * Currently this quirk does the equivalent of |
5318 | * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF |
5319 | * |
5320 | * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, |
5321 | * if dev->external_facing || dev->untrusted |
5322 | */ |
5323 | static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) |
5324 | { |
5325 | if (!pci_quirk_intel_pch_acs_match(dev)) |
5326 | return -ENOTTY; |
5327 | |
5328 | if (pci_quirk_enable_intel_lpc_acs(dev)) { |
5329 | pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); |
5330 | return 0; |
5331 | } |
5332 | |
5333 | pci_quirk_enable_intel_rp_mpc_acs(dev); |
5334 | |
5335 | dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; |
5336 | |
5337 | pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); |
5338 | |
5339 | return 0; |
5340 | } |
5341 | |
5342 | static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) |
5343 | { |
5344 | int pos; |
5345 | u32 cap, ctrl; |
5346 | |
5347 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) |
5348 | return -ENOTTY; |
5349 | |
5350 | pos = dev->acs_cap; |
5351 | if (!pos) |
5352 | return -ENOTTY; |
5353 | |
5354 | pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap); |
5355 | pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl); |
5356 | |
5357 | ctrl |= (cap & PCI_ACS_SV); |
5358 | ctrl |= (cap & PCI_ACS_RR); |
5359 | ctrl |= (cap & PCI_ACS_CR); |
5360 | ctrl |= (cap & PCI_ACS_UF); |
5361 | |
5362 | if (pci_ats_disabled() || dev->external_facing || dev->untrusted) |
5363 | ctrl |= (cap & PCI_ACS_TB); |
5364 | |
5365 | pci_write_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: ctrl); |
5366 | |
5367 | pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); |
5368 | |
5369 | return 0; |
5370 | } |
5371 | |
5372 | static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) |
5373 | { |
5374 | int pos; |
5375 | u32 cap, ctrl; |
5376 | |
5377 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) |
5378 | return -ENOTTY; |
5379 | |
5380 | pos = dev->acs_cap; |
5381 | if (!pos) |
5382 | return -ENOTTY; |
5383 | |
5384 | pci_read_config_dword(dev, where: pos + PCI_ACS_CAP, val: &cap); |
5385 | pci_read_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: &ctrl); |
5386 | |
5387 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); |
5388 | |
5389 | pci_write_config_dword(dev, where: pos + INTEL_SPT_ACS_CTRL, val: ctrl); |
5390 | |
5391 | pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); |
5392 | |
5393 | return 0; |
5394 | } |
5395 | |
5396 | static const struct pci_dev_acs_ops { |
5397 | u16 vendor; |
5398 | u16 device; |
5399 | int (*enable_acs)(struct pci_dev *dev); |
5400 | int (*disable_acs_redir)(struct pci_dev *dev); |
5401 | } pci_dev_acs_ops[] = { |
5402 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
5403 | .enable_acs = pci_quirk_enable_intel_pch_acs, |
5404 | }, |
5405 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
5406 | .enable_acs = pci_quirk_enable_intel_spt_pch_acs, |
5407 | .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, |
5408 | }, |
5409 | }; |
5410 | |
5411 | int pci_dev_specific_enable_acs(struct pci_dev *dev) |
5412 | { |
5413 | const struct pci_dev_acs_ops *p; |
5414 | int i, ret; |
5415 | |
5416 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { |
5417 | p = &pci_dev_acs_ops[i]; |
5418 | if ((p->vendor == dev->vendor || |
5419 | p->vendor == (u16)PCI_ANY_ID) && |
5420 | (p->device == dev->device || |
5421 | p->device == (u16)PCI_ANY_ID) && |
5422 | p->enable_acs) { |
5423 | ret = p->enable_acs(dev); |
5424 | if (ret >= 0) |
5425 | return ret; |
5426 | } |
5427 | } |
5428 | |
5429 | return -ENOTTY; |
5430 | } |
5431 | |
5432 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
5433 | { |
5434 | const struct pci_dev_acs_ops *p; |
5435 | int i, ret; |
5436 | |
5437 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { |
5438 | p = &pci_dev_acs_ops[i]; |
5439 | if ((p->vendor == dev->vendor || |
5440 | p->vendor == (u16)PCI_ANY_ID) && |
5441 | (p->device == dev->device || |
5442 | p->device == (u16)PCI_ANY_ID) && |
5443 | p->disable_acs_redir) { |
5444 | ret = p->disable_acs_redir(dev); |
5445 | if (ret >= 0) |
5446 | return ret; |
5447 | } |
5448 | } |
5449 | |
5450 | return -ENOTTY; |
5451 | } |
5452 | |
5453 | /* |
5454 | * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with |
5455 | * QuickAssist Technology (QAT) is prematurely terminated in hardware. The |
5456 | * Next Capability pointer in the MSI Capability Structure should point to |
5457 | * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating |
5458 | * the list. |
5459 | */ |
5460 | static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) |
5461 | { |
5462 | int pos, i = 0, ret; |
5463 | u8 next_cap; |
5464 | u16 reg16, *cap; |
5465 | struct pci_cap_saved_state *state; |
5466 | |
5467 | /* Bail if the hardware bug is fixed */ |
5468 | if (pdev->pcie_cap || pci_find_capability(dev: pdev, PCI_CAP_ID_EXP)) |
5469 | return; |
5470 | |
5471 | /* Bail if MSI Capability Structure is not found for some reason */ |
5472 | pos = pci_find_capability(dev: pdev, PCI_CAP_ID_MSI); |
5473 | if (!pos) |
5474 | return; |
5475 | |
5476 | /* |
5477 | * Bail if Next Capability pointer in the MSI Capability Structure |
5478 | * is not the expected incorrect 0x00. |
5479 | */ |
5480 | pci_read_config_byte(dev: pdev, where: pos + 1, val: &next_cap); |
5481 | if (next_cap) |
5482 | return; |
5483 | |
5484 | /* |
5485 | * PCIe Capability Structure is expected to be at 0x50 and should |
5486 | * terminate the list (Next Capability pointer is 0x00). Verify |
5487 | * Capability Id and Next Capability pointer is as expected. |
5488 | * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() |
5489 | * to correctly set kernel data structures which have already been |
5490 | * set incorrectly due to the hardware bug. |
5491 | */ |
5492 | pos = 0x50; |
5493 | pci_read_config_word(dev: pdev, where: pos, val: ®16); |
5494 | if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { |
5495 | u32 status; |
5496 | #ifndef PCI_EXP_SAVE_REGS |
5497 | #define PCI_EXP_SAVE_REGS 7 |
5498 | #endif |
5499 | int size = PCI_EXP_SAVE_REGS * sizeof(u16); |
5500 | |
5501 | pdev->pcie_cap = pos; |
5502 | pci_read_config_word(dev: pdev, where: pos + PCI_EXP_FLAGS, val: ®16); |
5503 | pdev->pcie_flags_reg = reg16; |
5504 | pci_read_config_word(dev: pdev, where: pos + PCI_EXP_DEVCAP, val: ®16); |
5505 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; |
5506 | |
5507 | pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; |
5508 | ret = pci_read_config_dword(dev: pdev, PCI_CFG_SPACE_SIZE, val: &status); |
5509 | if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) |
5510 | pdev->cfg_size = PCI_CFG_SPACE_SIZE; |
5511 | |
5512 | if (pci_find_saved_cap(dev: pdev, PCI_CAP_ID_EXP)) |
5513 | return; |
5514 | |
5515 | /* Save PCIe cap */ |
5516 | state = kzalloc(sizeof(*state) + size, GFP_KERNEL); |
5517 | if (!state) |
5518 | return; |
5519 | |
5520 | state->cap.cap_nr = PCI_CAP_ID_EXP; |
5521 | state->cap.cap_extended = 0; |
5522 | state->cap.size = size; |
5523 | cap = (u16 *)&state->cap.data[0]; |
5524 | pcie_capability_read_word(dev: pdev, PCI_EXP_DEVCTL, val: &cap[i++]); |
5525 | pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL, val: &cap[i++]); |
5526 | pcie_capability_read_word(dev: pdev, PCI_EXP_SLTCTL, val: &cap[i++]); |
5527 | pcie_capability_read_word(dev: pdev, PCI_EXP_RTCTL, val: &cap[i++]); |
5528 | pcie_capability_read_word(dev: pdev, PCI_EXP_DEVCTL2, val: &cap[i++]); |
5529 | pcie_capability_read_word(dev: pdev, PCI_EXP_LNKCTL2, val: &cap[i++]); |
5530 | pcie_capability_read_word(dev: pdev, PCI_EXP_SLTCTL2, val: &cap[i++]); |
5531 | hlist_add_head(n: &state->next, h: &pdev->saved_cap_space); |
5532 | } |
5533 | } |
5534 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); |
5535 | |
5536 | /* |
5537 | * FLR may cause the following to devices to hang: |
5538 | * |
5539 | * AMD Starship/Matisse HD Audio Controller 0x1487 |
5540 | * AMD Starship USB 3.0 Host Controller 0x148c |
5541 | * AMD Matisse USB 3.0 Host Controller 0x149c |
5542 | * Intel 82579LM Gigabit Ethernet Controller 0x1502 |
5543 | * Intel 82579V Gigabit Ethernet Controller 0x1503 |
5544 | * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter |
5545 | */ |
5546 | static void quirk_no_flr(struct pci_dev *dev) |
5547 | { |
5548 | dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; |
5549 | } |
5550 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); |
5551 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); |
5552 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); |
5553 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); |
5554 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); |
5555 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); |
5556 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); |
5557 | |
5558 | /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ |
5559 | static void quirk_no_flr_snet(struct pci_dev *dev) |
5560 | { |
5561 | if (dev->revision == 0x1) |
5562 | quirk_no_flr(dev); |
5563 | } |
5564 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); |
5565 | |
5566 | static void quirk_no_ext_tags(struct pci_dev *pdev) |
5567 | { |
5568 | struct pci_host_bridge *bridge = pci_find_host_bridge(bus: pdev->bus); |
5569 | |
5570 | if (!bridge) |
5571 | return; |
5572 | |
5573 | bridge->no_ext_tags = 1; |
5574 | pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); |
5575 | |
5576 | pci_walk_bus(top: bridge->bus, cb: pci_configure_extended_tags, NULL); |
5577 | } |
5578 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); |
5579 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); |
5580 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); |
5581 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); |
5582 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); |
5583 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); |
5584 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); |
5585 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); |
5586 | |
5587 | #ifdef CONFIG_PCI_ATS |
5588 | static void quirk_no_ats(struct pci_dev *pdev) |
5589 | { |
5590 | pci_info(pdev, "disabling ATS\n"); |
5591 | pdev->ats_cap = 0; |
5592 | } |
5593 | |
5594 | /* |
5595 | * Some devices require additional driver setup to enable ATS. Don't use |
5596 | * ATS for those devices as ATS will be enabled before the driver has had a |
5597 | * chance to load and configure the device. |
5598 | */ |
5599 | static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) |
5600 | { |
5601 | if (pdev->device == 0x15d8) { |
5602 | if (pdev->revision == 0xcf && |
5603 | pdev->subsystem_vendor == 0xea50 && |
5604 | (pdev->subsystem_device == 0xce19 || |
5605 | pdev->subsystem_device == 0xcc10 || |
5606 | pdev->subsystem_device == 0xcc08)) |
5607 | quirk_no_ats(pdev); |
5608 | } else { |
5609 | quirk_no_ats(pdev); |
5610 | } |
5611 | } |
5612 | |
5613 | /* AMD Stoney platform GPU */ |
5614 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); |
5615 | /* AMD Iceland dGPU */ |
5616 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); |
5617 | /* AMD Navi10 dGPU */ |
5618 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); |
5619 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); |
5620 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); |
5621 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); |
5622 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); |
5623 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); |
5624 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); |
5625 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); |
5626 | /* AMD Navi14 dGPU */ |
5627 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); |
5628 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); |
5629 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); |
5630 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); |
5631 | /* AMD Raven platform iGPU */ |
5632 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); |
5633 | |
5634 | /* |
5635 | * Intel IPU E2000 revisions before C0 implement incorrect endianness |
5636 | * in ATS Invalidate Request message body. Disable ATS for those devices. |
5637 | */ |
5638 | static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) |
5639 | { |
5640 | if (pdev->revision < 0x20) |
5641 | quirk_no_ats(pdev); |
5642 | } |
5643 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); |
5644 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); |
5645 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); |
5646 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); |
5647 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); |
5648 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); |
5649 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); |
5650 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); |
5651 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); |
5652 | #endif /* CONFIG_PCI_ATS */ |
5653 | |
5654 | /* Freescale PCIe doesn't support MSI in RC mode */ |
5655 | static void quirk_fsl_no_msi(struct pci_dev *pdev) |
5656 | { |
5657 | if (pci_pcie_type(dev: pdev) == PCI_EXP_TYPE_ROOT_PORT) |
5658 | pdev->no_msi = 1; |
5659 | } |
5660 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); |
5661 | |
5662 | /* |
5663 | * Although not allowed by the spec, some multi-function devices have |
5664 | * dependencies of one function (consumer) on another (supplier). For the |
5665 | * consumer to work in D0, the supplier must also be in D0. Create a |
5666 | * device link from the consumer to the supplier to enforce this |
5667 | * dependency. Runtime PM is allowed by default on the consumer to prevent |
5668 | * it from permanently keeping the supplier awake. |
5669 | */ |
5670 | static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, |
5671 | unsigned int supplier, unsigned int class, |
5672 | unsigned int class_shift) |
5673 | { |
5674 | struct pci_dev *supplier_pdev; |
5675 | |
5676 | if (PCI_FUNC(pdev->devfn) != consumer) |
5677 | return; |
5678 | |
5679 | supplier_pdev = pci_get_domain_bus_and_slot(domain: pci_domain_nr(bus: pdev->bus), |
5680 | bus: pdev->bus->number, |
5681 | PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); |
5682 | if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { |
5683 | pci_dev_put(dev: supplier_pdev); |
5684 | return; |
5685 | } |
5686 | |
5687 | if (device_link_add(consumer: &pdev->dev, supplier: &supplier_pdev->dev, |
5688 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) |
5689 | pci_info(pdev, "D0 power state depends on %s\n", |
5690 | pci_name(supplier_pdev)); |
5691 | else |
5692 | pci_err(pdev, "Cannot enforce power dependency on %s\n", |
5693 | pci_name(supplier_pdev)); |
5694 | |
5695 | pm_runtime_allow(dev: &pdev->dev); |
5696 | pci_dev_put(dev: supplier_pdev); |
5697 | } |
5698 | |
5699 | /* |
5700 | * Create device link for GPUs with integrated HDA controller for streaming |
5701 | * audio to attached displays. |
5702 | */ |
5703 | static void quirk_gpu_hda(struct pci_dev *hda) |
5704 | { |
5705 | pci_create_device_link(pdev: hda, consumer: 1, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16); |
5706 | } |
5707 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
5708 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); |
5709 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, |
5710 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); |
5711 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
5712 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); |
5713 | |
5714 | /* |
5715 | * Create device link for GPUs with integrated USB xHCI Host |
5716 | * controller to VGA. |
5717 | */ |
5718 | static void quirk_gpu_usb(struct pci_dev *usb) |
5719 | { |
5720 | pci_create_device_link(pdev: usb, consumer: 2, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16); |
5721 | } |
5722 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
5723 | PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); |
5724 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
5725 | PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); |
5726 | |
5727 | /* |
5728 | * Create device link for GPUs with integrated Type-C UCSI controller |
5729 | * to VGA. Currently there is no class code defined for UCSI device over PCI |
5730 | * so using UNKNOWN class for now and it will be updated when UCSI |
5731 | * over PCI gets a class code. |
5732 | */ |
5733 | #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 |
5734 | static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) |
5735 | { |
5736 | pci_create_device_link(pdev: ucsi, consumer: 3, supplier: 0, PCI_BASE_CLASS_DISPLAY, class_shift: 16); |
5737 | } |
5738 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
5739 | PCI_CLASS_SERIAL_UNKNOWN, 8, |
5740 | quirk_gpu_usb_typec_ucsi); |
5741 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
5742 | PCI_CLASS_SERIAL_UNKNOWN, 8, |
5743 | quirk_gpu_usb_typec_ucsi); |
5744 | |
5745 | /* |
5746 | * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it |
5747 | * disabled. https://devtalk.nvidia.com/default/topic/1024022 |
5748 | */ |
5749 | static void quirk_nvidia_hda(struct pci_dev *gpu) |
5750 | { |
5751 | u8 hdr_type; |
5752 | u32 val; |
5753 | |
5754 | /* There was no integrated HDA controller before MCP89 */ |
5755 | if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) |
5756 | return; |
5757 | |
5758 | /* Bit 25 at offset 0x488 enables the HDA controller */ |
5759 | pci_read_config_dword(dev: gpu, where: 0x488, val: &val); |
5760 | if (val & BIT(25)) |
5761 | return; |
5762 | |
5763 | pci_info(gpu, "Enabling HDA controller\n"); |
5764 | pci_write_config_dword(dev: gpu, where: 0x488, val: val | BIT(25)); |
5765 | |
5766 | /* The GPU becomes a multi-function device when the HDA is enabled */ |
5767 | pci_read_config_byte(dev: gpu, PCI_HEADER_TYPE, val: &hdr_type); |
5768 | gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); |
5769 | } |
5770 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
5771 | PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); |
5772 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
5773 | PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); |
5774 | |
5775 | /* |
5776 | * Some IDT switches incorrectly flag an ACS Source Validation error on |
5777 | * completions for config read requests even though PCIe r4.0, sec |
5778 | * 6.12.1.1, says that completions are never affected by ACS Source |
5779 | * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: |
5780 | * |
5781 | * Item #36 - Downstream port applies ACS Source Validation to Completions |
5782 | * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that |
5783 | * completions are never affected by ACS Source Validation. However, |
5784 | * completions received by a downstream port of the PCIe switch from a |
5785 | * device that has not yet captured a PCIe bus number are incorrectly |
5786 | * dropped by ACS Source Validation by the switch downstream port. |
5787 | * |
5788 | * The workaround suggested by IDT is to issue a config write to the |
5789 | * downstream device before issuing the first config read. This allows the |
5790 | * downstream device to capture its bus and device numbers (see PCIe r4.0, |
5791 | * sec 2.2.9), thus avoiding the ACS error on the completion. |
5792 | * |
5793 | * However, we don't know when the device is ready to accept the config |
5794 | * write, so we do config reads until we receive a non-Config Request Retry |
5795 | * Status, then do the config write. |
5796 | * |
5797 | * To avoid hitting the erratum when doing the config reads, we disable ACS |
5798 | * SV around this process. |
5799 | */ |
5800 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) |
5801 | { |
5802 | int pos; |
5803 | u16 ctrl = 0; |
5804 | bool found; |
5805 | struct pci_dev *bridge = bus->self; |
5806 | |
5807 | pos = bridge->acs_cap; |
5808 | |
5809 | /* Disable ACS SV before initial config reads */ |
5810 | if (pos) { |
5811 | pci_read_config_word(dev: bridge, where: pos + PCI_ACS_CTRL, val: &ctrl); |
5812 | if (ctrl & PCI_ACS_SV) |
5813 | pci_write_config_word(dev: bridge, where: pos + PCI_ACS_CTRL, |
5814 | val: ctrl & ~PCI_ACS_SV); |
5815 | } |
5816 | |
5817 | found = pci_bus_generic_read_dev_vendor_id(bus, devfn, pl: l, rrs_timeout: timeout); |
5818 | |
5819 | /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ |
5820 | if (found) |
5821 | pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, val: 0); |
5822 | |
5823 | /* Re-enable ACS_SV if it was previously enabled */ |
5824 | if (ctrl & PCI_ACS_SV) |
5825 | pci_write_config_word(dev: bridge, where: pos + PCI_ACS_CTRL, val: ctrl); |
5826 | |
5827 | return found; |
5828 | } |
5829 | |
5830 | /* |
5831 | * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between |
5832 | * NT endpoints via the internal switch fabric. These IDs replace the |
5833 | * originating Requester ID TLPs which access host memory on peer NTB |
5834 | * ports. Therefore, all proxy IDs must be aliased to the NTB device |
5835 | * to permit access when the IOMMU is turned on. |
5836 | */ |
5837 | static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) |
5838 | { |
5839 | void __iomem *mmio; |
5840 | struct ntb_info_regs __iomem *mmio_ntb; |
5841 | struct ntb_ctrl_regs __iomem *mmio_ctrl; |
5842 | u64 partition_map; |
5843 | u8 partition; |
5844 | int pp; |
5845 | |
5846 | if (pci_enable_device(dev: pdev)) { |
5847 | pci_err(pdev, "Cannot enable Switchtec device\n"); |
5848 | return; |
5849 | } |
5850 | |
5851 | mmio = pci_iomap(dev: pdev, bar: 0, max: 0); |
5852 | if (mmio == NULL) { |
5853 | pci_disable_device(dev: pdev); |
5854 | pci_err(pdev, "Cannot iomap Switchtec device\n"); |
5855 | return; |
5856 | } |
5857 | |
5858 | pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); |
5859 | |
5860 | mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; |
5861 | mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; |
5862 | |
5863 | partition = ioread8(&mmio_ntb->partition_id); |
5864 | |
5865 | partition_map = ioread32(&mmio_ntb->ep_map); |
5866 | partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; |
5867 | partition_map &= ~(1ULL << partition); |
5868 | |
5869 | for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { |
5870 | struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; |
5871 | u32 table_sz = 0; |
5872 | int te; |
5873 | |
5874 | if (!(partition_map & (1ULL << pp))) |
5875 | continue; |
5876 | |
5877 | pci_dbg(pdev, "Processing partition %d\n", pp); |
5878 | |
5879 | mmio_peer_ctrl = &mmio_ctrl[pp]; |
5880 | |
5881 | table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); |
5882 | if (!table_sz) { |
5883 | pci_warn(pdev, "Partition %d table_sz 0\n", pp); |
5884 | continue; |
5885 | } |
5886 | |
5887 | if (table_sz > 512) { |
5888 | pci_warn(pdev, |
5889 | "Invalid Switchtec partition %d table_sz %d\n", |
5890 | pp, table_sz); |
5891 | continue; |
5892 | } |
5893 | |
5894 | for (te = 0; te < table_sz; te++) { |
5895 | u32 rid_entry; |
5896 | u8 devfn; |
5897 | |
5898 | rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); |
5899 | devfn = (rid_entry >> 1) & 0xFF; |
5900 | pci_dbg(pdev, |
5901 | "Aliasing Partition %d Proxy ID %02x.%d\n", |
5902 | pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
5903 | pci_add_dma_alias(dev: pdev, devfn_from: devfn, nr_devfns: 1); |
5904 | } |
5905 | } |
5906 | |
5907 | pci_iounmap(dev: pdev, mmio); |
5908 | pci_disable_device(dev: pdev); |
5909 | } |
5910 | #define SWITCHTEC_QUIRK(vid) \ |
5911 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ |
5912 | PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) |
5913 | |
5914 | SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ |
5915 | SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ |
5916 | SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ |
5917 | SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ |
5918 | SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ |
5919 | SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ |
5920 | SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ |
5921 | SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ |
5922 | SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ |
5923 | SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ |
5924 | SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ |
5925 | SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ |
5926 | SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ |
5927 | SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ |
5928 | SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ |
5929 | SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ |
5930 | SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ |
5931 | SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ |
5932 | SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ |
5933 | SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ |
5934 | SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ |
5935 | SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ |
5936 | SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ |
5937 | SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ |
5938 | SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ |
5939 | SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ |
5940 | SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ |
5941 | SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ |
5942 | SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ |
5943 | SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ |
5944 | SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ |
5945 | SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ |
5946 | SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ |
5947 | SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ |
5948 | SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ |
5949 | SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ |
5950 | SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ |
5951 | SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ |
5952 | SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ |
5953 | SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ |
5954 | SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ |
5955 | SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ |
5956 | SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ |
5957 | SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ |
5958 | SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ |
5959 | SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ |
5960 | SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ |
5961 | SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ |
5962 | SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ |
5963 | SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ |
5964 | SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ |
5965 | SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ |
5966 | SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ |
5967 | SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ |
5968 | SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ |
5969 | SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ |
5970 | SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ |
5971 | SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ |
5972 | SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ |
5973 | SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ |
5974 | SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ |
5975 | SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ |
5976 | SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ |
5977 | SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ |
5978 | SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ |
5979 | SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ |
5980 | SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ |
5981 | SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ |
5982 | SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ |
5983 | SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ |
5984 | SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ |
5985 | SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ |
5986 | SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ |
5987 | SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ |
5988 | SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ |
5989 | SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ |
5990 | SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ |
5991 | SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ |
5992 | SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ |
5993 | SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ |
5994 | SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ |
5995 | SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ |
5996 | SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ |
5997 | SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ |
5998 | SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ |
5999 | SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ |
6000 | SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ |
6001 | SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ |
6002 | SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ |
6003 | SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ |
6004 | SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ |
6005 | SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ |
6006 | SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ |
6007 | |
6008 | #define SWITCHTEC_PCI100X_QUIRK(vid) \ |
6009 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ |
6010 | PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) |
6011 | SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ |
6012 | SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ |
6013 | SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ |
6014 | SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ |
6015 | SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ |
6016 | SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ |
6017 | |
6018 | |
6019 | /* |
6020 | * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. |
6021 | * These IDs are used to forward responses to the originator on the other |
6022 | * side of the NTB. Alias all possible IDs to the NTB to permit access when |
6023 | * the IOMMU is turned on. |
6024 | */ |
6025 | static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) |
6026 | { |
6027 | pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); |
6028 | /* PLX NTB may use all 256 devfns */ |
6029 | pci_add_dma_alias(dev: pdev, devfn_from: 0, nr_devfns: 256); |
6030 | } |
6031 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); |
6032 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); |
6033 | |
6034 | /* |
6035 | * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does |
6036 | * not always reset the secondary Nvidia GPU between reboots if the system |
6037 | * is configured to use Hybrid Graphics mode. This results in the GPU |
6038 | * being left in whatever state it was in during the *previous* boot, which |
6039 | * causes spurious interrupts from the GPU, which in turn causes us to |
6040 | * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, |
6041 | * this also completely breaks nouveau. |
6042 | * |
6043 | * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a |
6044 | * clean state and fixes all these issues. |
6045 | * |
6046 | * When the machine is configured in Dedicated display mode, the issue |
6047 | * doesn't occur. Fortunately the GPU advertises NoReset+ when in this |
6048 | * mode, so we can detect that and avoid resetting it. |
6049 | */ |
6050 | static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) |
6051 | { |
6052 | void __iomem *map; |
6053 | int ret; |
6054 | |
6055 | if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || |
6056 | pdev->subsystem_device != 0x222e || |
6057 | !pci_reset_supported(dev: pdev)) |
6058 | return; |
6059 | |
6060 | if (pci_enable_device_mem(dev: pdev)) |
6061 | return; |
6062 | |
6063 | /* |
6064 | * Based on nvkm_device_ctor() in |
6065 | * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c |
6066 | */ |
6067 | map = pci_iomap(dev: pdev, bar: 0, max: 0x23000); |
6068 | if (!map) { |
6069 | pci_err(pdev, "Can't map MMIO space\n"); |
6070 | goto out_disable; |
6071 | } |
6072 | |
6073 | /* |
6074 | * Make sure the GPU looks like it's been POSTed before resetting |
6075 | * it. |
6076 | */ |
6077 | if (ioread32(map + 0x2240c) & 0x2) { |
6078 | pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); |
6079 | ret = pci_reset_bus(dev: pdev); |
6080 | if (ret < 0) |
6081 | pci_err(pdev, "Failed to reset GPU: %d\n", ret); |
6082 | } |
6083 | |
6084 | iounmap(addr: map); |
6085 | out_disable: |
6086 | pci_disable_device(dev: pdev); |
6087 | } |
6088 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, |
6089 | PCI_CLASS_DISPLAY_VGA, 8, |
6090 | quirk_reset_lenovo_thinkpad_p50_nvgpu); |
6091 | |
6092 | /* |
6093 | * Device [1b21:2142] |
6094 | * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. |
6095 | */ |
6096 | static void pci_fixup_no_d0_pme(struct pci_dev *dev) |
6097 | { |
6098 | pci_info(dev, "PME# does not work under D0, disabling it\n"); |
6099 | dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); |
6100 | } |
6101 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); |
6102 | |
6103 | /* |
6104 | * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] |
6105 | * |
6106 | * These devices advertise PME# support in all power states but don't |
6107 | * reliably assert it. |
6108 | * |
6109 | * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) |
6110 | * says "The MSI Function is not implemented on this device" in chapters |
6111 | * 7.3.27, 7.3.29-7.3.31. |
6112 | */ |
6113 | static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) |
6114 | { |
6115 | #ifdef CONFIG_PCI_MSI |
6116 | pci_info(dev, "MSI is not implemented on this device, disabling it\n"); |
6117 | dev->no_msi = 1; |
6118 | #endif |
6119 | pci_info(dev, "PME# is unreliable, disabling it\n"); |
6120 | dev->pme_support = 0; |
6121 | } |
6122 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); |
6123 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); |
6124 | |
6125 | static void apex_pci_fixup_class(struct pci_dev *pdev) |
6126 | { |
6127 | pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; |
6128 | } |
6129 | DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, |
6130 | PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); |
6131 | |
6132 | /* |
6133 | * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - |
6134 | * ACS P2P Request Redirect is not functional |
6135 | * |
6136 | * When ACS P2P Request Redirect is enabled and bandwidth is not balanced |
6137 | * between upstream and downstream ports, packets are queued in an internal |
6138 | * buffer until CPLD packet. The workaround is to use the switch in store and |
6139 | * forward mode. |
6140 | */ |
6141 | #define PI7C9X2Gxxx_MODE_REG 0x74 |
6142 | #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) |
6143 | static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) |
6144 | { |
6145 | struct pci_dev *upstream; |
6146 | u16 val; |
6147 | |
6148 | /* Downstream ports only */ |
6149 | if (pci_pcie_type(dev: pdev) != PCI_EXP_TYPE_DOWNSTREAM) |
6150 | return; |
6151 | |
6152 | /* Check for ACS P2P Request Redirect use */ |
6153 | if (!pdev->acs_cap) |
6154 | return; |
6155 | pci_read_config_word(dev: pdev, where: pdev->acs_cap + PCI_ACS_CTRL, val: &val); |
6156 | if (!(val & PCI_ACS_RR)) |
6157 | return; |
6158 | |
6159 | upstream = pci_upstream_bridge(dev: pdev); |
6160 | if (!upstream) |
6161 | return; |
6162 | |
6163 | pci_read_config_word(dev: upstream, PI7C9X2Gxxx_MODE_REG, val: &val); |
6164 | if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { |
6165 | pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); |
6166 | pci_write_config_word(dev: upstream, PI7C9X2Gxxx_MODE_REG, val: val | |
6167 | PI7C9X2Gxxx_STORE_FORWARD_MODE); |
6168 | } |
6169 | } |
6170 | /* |
6171 | * Apply fixup on enable and on resume, in order to apply the fix up whenever |
6172 | * ACS configuration changes or switch mode is reset |
6173 | */ |
6174 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, |
6175 | pci_fixup_pericom_acs_store_forward); |
6176 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, |
6177 | pci_fixup_pericom_acs_store_forward); |
6178 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, |
6179 | pci_fixup_pericom_acs_store_forward); |
6180 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, |
6181 | pci_fixup_pericom_acs_store_forward); |
6182 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, |
6183 | pci_fixup_pericom_acs_store_forward); |
6184 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, |
6185 | pci_fixup_pericom_acs_store_forward); |
6186 | |
6187 | static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) |
6188 | { |
6189 | pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; |
6190 | } |
6191 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); |
6192 | |
6193 | static void rom_bar_overlap_defect(struct pci_dev *dev) |
6194 | { |
6195 | pci_info(dev, "working around ROM BAR overlap defect\n"); |
6196 | dev->rom_bar_overlap = 1; |
6197 | } |
6198 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); |
6199 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); |
6200 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); |
6201 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); |
6202 | |
6203 | #ifdef CONFIG_PCIEASPM |
6204 | /* |
6205 | * Several Intel DG2 graphics devices advertise that they can only tolerate |
6206 | * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 |
6207 | * from being enabled. But in fact these devices can tolerate unlimited |
6208 | * latency. Override their Device Capabilities value to allow ASPM L1 to |
6209 | * be enabled. |
6210 | */ |
6211 | static void aspm_l1_acceptable_latency(struct pci_dev *dev) |
6212 | { |
6213 | u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); |
6214 | |
6215 | if (l1_lat < 7) { |
6216 | dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); |
6217 | pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", |
6218 | l1_lat); |
6219 | } |
6220 | } |
6221 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); |
6222 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); |
6223 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); |
6224 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); |
6225 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); |
6226 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); |
6227 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); |
6228 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); |
6229 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); |
6230 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); |
6231 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); |
6232 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); |
6233 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); |
6234 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); |
6235 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); |
6236 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); |
6237 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); |
6238 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); |
6239 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); |
6240 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); |
6241 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); |
6242 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); |
6243 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); |
6244 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); |
6245 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); |
6246 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); |
6247 | #endif |
6248 | |
6249 | #ifdef CONFIG_PCIE_DPC |
6250 | /* |
6251 | * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears |
6252 | * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root |
6253 | * Ports. |
6254 | */ |
6255 | static void dpc_log_size(struct pci_dev *dev) |
6256 | { |
6257 | u16 dpc, val; |
6258 | |
6259 | dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); |
6260 | if (!dpc) |
6261 | return; |
6262 | |
6263 | pci_read_config_word(dev, where: dpc + PCI_EXP_DPC_CAP, val: &val); |
6264 | if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) |
6265 | return; |
6266 | |
6267 | if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { |
6268 | pci_info(dev, "Overriding RP PIO Log Size to %d\n", |
6269 | PCIE_STD_NUM_TLP_HEADERLOG); |
6270 | dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; |
6271 | } |
6272 | } |
6273 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); |
6274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); |
6275 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); |
6276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); |
6277 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); |
6278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); |
6279 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); |
6280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); |
6281 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); |
6282 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); |
6283 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); |
6284 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); |
6285 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); |
6286 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); |
6287 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); |
6288 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); |
6289 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); |
6290 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); |
6291 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); |
6292 | #endif |
6293 | |
6294 | /* |
6295 | * For a PCI device with multiple downstream devices, its driver may use |
6296 | * a flattened device tree to describe the downstream devices. |
6297 | * To overlay the flattened device tree, the PCI device and all its ancestor |
6298 | * devices need to have device tree nodes on system base device tree. Thus, |
6299 | * before driver probing, it might need to add a device tree node as the final |
6300 | * fixup. |
6301 | */ |
6302 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); |
6303 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); |
6304 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); |
6305 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); |
6306 | |
6307 | /* |
6308 | * Devices known to require a longer delay before first config space access |
6309 | * after reset recovery or resume from D3cold: |
6310 | * |
6311 | * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator |
6312 | */ |
6313 | static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) |
6314 | { |
6315 | pdev->d3cold_delay = 1000; |
6316 | } |
6317 | DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); |
6318 | |
6319 | #ifdef CONFIG_PCIEAER |
6320 | static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) |
6321 | { |
6322 | struct pci_dev *parent = pci_upstream_bridge(dev: pdev); |
6323 | u32 val; |
6324 | |
6325 | if (!parent || !parent->aer_cap) |
6326 | return; |
6327 | |
6328 | pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", |
6329 | pci_name(pdev)); |
6330 | |
6331 | pci_read_config_dword(dev: parent, where: parent->aer_cap + PCI_ERR_COR_MASK, val: &val); |
6332 | val |= PCI_ERR_COR_REP_TIMER; |
6333 | pci_write_config_dword(dev: parent, where: parent->aer_cap + PCI_ERR_COR_MASK, val); |
6334 | } |
6335 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); |
6336 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); |
6337 | #endif |
6338 |
Definitions
- pcie_lbms_seen
- pcie_failed_link_retrain
- fixup_debug_start
- fixup_debug_report
- pci_do_fixups
- pci_apply_fixup_final_quirks
- pci_fixup_device
- pci_apply_final_quirks
- quirk_mmio_always_on
- quirk_passive_release
- quirk_tigerpoint_bm_sts
- quirk_nopcipci
- quirk_nopciamd
- quirk_triton
- quirk_vialatency
- quirk_viaetbf
- quirk_vsfx
- quirk_alimagik
- quirk_natoma
- quirk_citrine
- quirk_nfp6000
- quirk_extend_bar_to_page
- quirk_s3_64M
- quirk_io
- quirk_cs5536_vsa
- quirk_io_region
- quirk_ati_exploding_mce
- quirk_amd_dwc_class
- quirk_synopsys_haps
- quirk_ali7101_acpi
- piix4_io_quirk
- piix4_mem_quirk
- quirk_piix4_acpi
- quirk_ich4_lpc_acpi
- ich6_lpc_acpi_gpio
- ich6_lpc_generic_decode
- quirk_ich6_lpc
- ich7_lpc_generic_decode
- quirk_ich7_lpc
- quirk_vt82c586_acpi
- quirk_vt82c686_acpi
- quirk_vt8235_acpi
- quirk_xio2000a
- quirk_via_ioapic
- quirk_via_vt8237_bypass_apic_deassert
- quirk_amd_ioapic
- quirk_amd_8131_mmrbc
- quirk_via_acpi
- via_vlink_dev_lo
- via_vlink_dev_hi
- quirk_via_bridge
- quirk_via_vlink
- quirk_vt82c598_id
- quirk_cardbus_legacy
- quirk_amd_ordering
- quirk_dunord
- quirk_transparent_bridge
- quirk_mediagx_master
- quirk_disable_pxb
- quirk_amd_ide_mode
- quirk_svwks_csb5ide
- quirk_ide_samemode
- quirk_no_ata_d3
- quirk_eisa_bridge
- asus_hides_smbus
- asus_hides_smbus_hostbridge
- asus_hides_smbus_lpc
- asus_rcba_base
- asus_hides_smbus_lpc_ich6_suspend
- asus_hides_smbus_lpc_ich6_resume_early
- asus_hides_smbus_lpc_ich6_resume
- asus_hides_smbus_lpc_ich6
- quirk_sis_96x_smbus
- quirk_sis_503
- asus_hides_ac97_lpc
- quirk_jmicron_ata
- quirk_jmicron_async_suspend
- quirk_alder_ioapic
- quirk_no_msi
- quirk_pcie_mch
- quirk_huawei_pcie_sva
- quirk_pcie_pxh
- quirk_intel_pcie_pm
- quirk_d3hot_delay
- quirk_radeon_pm
- quirk_nvidia_hda_pm
- quirk_ryzen_xhci_d3hot
- dmi_disable_ioapicreroute
- boot_interrupt_dmi_table
- quirk_reroute_to_boot_interrupts_intel
- quirk_disable_intel_boot_interrupt
- quirk_disable_broadcom_boot_interrupt
- quirk_disable_amd_813x_boot_interrupt
- quirk_disable_amd_8111_boot_interrupt
- quirk_tc86c001_ide
- quirk_plx_pci9050
- quirk_netmos
- quirk_e100_interrupt
- quirk_disable_aspm_l0s
- quirk_disable_aspm_l0s_l1
- quirk_enable_clear_retrain_link
- fixup_rev1_53c810
- quirk_p64h2_1k_io
- quirk_nvidia_ck804_pcie_aer_ext_cap
- quirk_via_cx700_pci_parking_caching
- quirk_brcm_5719_limit_mrrs
- quirk_unhide_mch_dev6
- quirk_disable_all_msi
- quirk_disable_msi
- quirk_amd_780_apc_msi
- msi_ht_cap_enabled
- quirk_msi_ht_cap
- quirk_nvidia_ck804_msi_ht_cap
- ht_enable_msi_mapping
- nvenet_msi_disable
- pci_quirk_nvidia_tegra_disable_rp_msi
- nvbridge_check_legacy_irq_routing
- ht_check_msi_mapping
- host_bridge_with_leaf
- is_end_of_ht_chain
- nv_ht_enable_msi_mapping
- ht_disable_msi_mapping
- __nv_msi_ht_cap_quirk
- nv_msi_ht_cap_quirk_all
- nv_msi_ht_cap_quirk_leaf
- quirk_msi_intx_disable_bug
- quirk_msi_intx_disable_ati_bug
- quirk_msi_intx_disable_qca_bug
- quirk_al_msi_disable
- quirk_hotplug_bridge
- ricoh_mmc_fixup_rl5c476
- ricoh_mmc_fixup_r5c832
- vtd_mask_spec_errors
- fixup_ti816x_class
- fixup_mpss_256
- quirk_intel_mc_errata
- quirk_intel_ntb
- disable_igfx_irq
- quirk_remove_d3hot_delay
- quirk_broken_intx_masking
- mellanox_broken_intx_devs
- mellanox_check_broken_intx_masking
- quirk_no_bus_reset
- quirk_nvidia_no_bus_reset
- quirk_no_pm_reset
- quirk_thunderbolt_hotplug_msi
- quirk_apple_poweroff_thunderbolt
- reset_intel_82599_sfp_virtfn
- reset_ivb_igd
- reset_chelsio_generic_dev
- nvme_disable_and_flr
- delay_250ms_after_flr
- reset_hinic_vf_dev
- pci_dev_reset_methods
- pci_dev_specific_reset
- quirk_dma_func0_alias
- quirk_dma_func1_alias
- fixed_dma_alias_tbl
- quirk_fixed_dma_alias
- quirk_use_pcie_bridge_dma_alias
- quirk_mic_x200_dma_alias
- quirk_pex_vca_alias
- quirk_bridge_cavm_thrx2_pcie_root
- quirk_tw686x_class
- quirk_relaxedordering_disable
- quirk_disable_root_port_attributes
- quirk_chelsio_T5_disable_root_port_attributes
- pci_acs_ctrl_enabled
- pci_quirk_amd_sb_acs
- pci_quirk_cavium_acs_match
- pci_quirk_cavium_acs
- pci_quirk_xgene_acs
- pci_quirk_zhaoxin_pcie_ports_acs
- pci_quirk_intel_pch_acs_ids
- pci_quirk_intel_pch_acs_match
- pci_quirk_intel_pch_acs
- pci_quirk_qcom_rp_acs
- pci_quirk_nxp_rp_acs
- pci_quirk_al_acs
- pci_quirk_intel_spt_pch_acs_match
- pci_quirk_intel_spt_pch_acs
- pci_quirk_mf_endpoint_acs
- pci_quirk_rciep_acs
- pci_quirk_brcm_acs
- pci_quirk_loongson_acs
- pci_quirk_wangxun_nic_acs
- pci_dev_acs_enabled
- pci_dev_acs_enabled
- pci_dev_specific_acs_enabled
- pci_quirk_enable_intel_lpc_acs
- pci_quirk_enable_intel_rp_mpc_acs
- pci_quirk_enable_intel_pch_acs
- pci_quirk_enable_intel_spt_pch_acs
- pci_quirk_disable_intel_spt_pch_acs_redir
- pci_dev_acs_ops
- pci_dev_acs_ops
- pci_dev_specific_enable_acs
- pci_dev_specific_disable_acs_redir
- quirk_intel_qat_vf_cap
- quirk_no_flr
- quirk_no_flr_snet
- quirk_no_ext_tags
- quirk_no_ats
- quirk_amd_harvest_no_ats
- quirk_intel_e2000_no_ats
- quirk_fsl_no_msi
- pci_create_device_link
- quirk_gpu_hda
- quirk_gpu_usb
- quirk_gpu_usb_typec_ucsi
- quirk_nvidia_hda
- pci_idt_bus_quirk
- quirk_switchtec_ntb_dma_alias
- quirk_plx_ntb_dma_alias
- quirk_reset_lenovo_thinkpad_p50_nvgpu
- pci_fixup_no_d0_pme
- pci_fixup_no_msi_no_pme
- apex_pci_fixup_class
- pci_fixup_pericom_acs_store_forward
- nvidia_ion_ahci_fixup
- rom_bar_overlap_defect
- aspm_l1_acceptable_latency
- dpc_log_size
- pci_fixup_d3cold_delay_1sec
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