1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright 2021 NXP */
3
4#include <dt-bindings/firmware/imx/rsrc.h>
5#include <linux/arm-smccc.h>
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/firmware.h>
9#include <linux/firmware/imx/sci.h>
10#include <linux/interrupt.h>
11#include <linux/kernel.h>
12#include <linux/mailbox_client.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_reserved_mem.h>
17#include <linux/platform_device.h>
18#include <linux/pm_domain.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21#include <linux/remoteproc.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24
25#include "imx_rproc.h"
26#include "remoteproc_elf_helpers.h"
27#include "remoteproc_internal.h"
28
29#define DSP_RPROC_CLK_MAX 5
30
31/*
32 * Module parameters
33 */
34static unsigned int no_mailboxes;
35module_param_named(no_mailboxes, no_mailboxes, int, 0644);
36MODULE_PARM_DESC(no_mailboxes,
37 "There is no mailbox between cores, so ignore remote proc reply after start, default is 0 (off).");
38
39/* Flag indicating that the remote is up and running */
40#define REMOTE_IS_READY BIT(0)
41/* Flag indicating that the host should wait for a firmware-ready response */
42#define WAIT_FW_READY BIT(1)
43#define REMOTE_READY_WAIT_MAX_RETRIES 500
44
45/*
46 * This flag is set in the DSP resource table's features field to indicate
47 * that the firmware requires the host NOT to wait for a FW_READY response.
48 */
49#define FEATURE_DONT_WAIT_FW_READY BIT(0)
50
51/* att flags */
52/* DSP own area */
53#define ATT_OWN BIT(31)
54/* DSP instruction area */
55#define ATT_IRAM BIT(30)
56
57/* Definitions for i.MX8MP */
58/* DAP registers */
59#define IMX8M_DAP_DEBUG 0x28800000
60#define IMX8M_DAP_DEBUG_SIZE (64 * 1024)
61#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)
62#define IMX8M_PWRCTL_CORERESET BIT(16)
63
64/* DSP audio mix registers */
65#define IMX8M_AudioDSP_REG0 0x100
66#define IMX8M_AudioDSP_REG1 0x104
67#define IMX8M_AudioDSP_REG2 0x108
68#define IMX8M_AudioDSP_REG3 0x10c
69
70#define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5)
71#define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1)
72
73/* Definitions for i.MX8ULP */
74#define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8
75#define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25)
76#define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19)
77#define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18)
78#define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17)
79#define IMX8ULP_SYSCTRL0_DSP_RST BIT(16)
80#define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14)
81#define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13)
82
83#define IMX8ULP_SIP_HIFI_XRDC 0xc200000e
84
85#define FW_RSC_NXP_S_MAGIC ((uint32_t)'n' << 24 | \
86 (uint32_t)'x' << 16 | \
87 (uint32_t)'p' << 8 | \
88 (uint32_t)'s')
89/*
90 * enum - Predefined Mailbox Messages
91 *
92 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor
93 *
94 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a
95 * suspend request
96 *
97 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor
98 *
99 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a
100 * resume request
101 */
102enum imx_dsp_rp_mbox_messages {
103 RP_MBOX_SUSPEND_SYSTEM = 0xFF11,
104 RP_MBOX_SUSPEND_ACK = 0xFF12,
105 RP_MBOX_RESUME_SYSTEM = 0xFF13,
106 RP_MBOX_RESUME_ACK = 0xFF14,
107};
108
109/**
110 * struct imx_dsp_rproc - DSP remote processor state
111 * @regmap: regmap handler
112 * @run_stall: reset control handle used for Run/Stall operation
113 * @rproc: rproc handler
114 * @dsp_dcfg: device configuration pointer
115 * @clks: clocks needed by this device
116 * @cl: mailbox client to request the mailbox channel
117 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell
118 * @tx_ch: mailbox tx channel handle
119 * @rx_ch: mailbox rx channel handle
120 * @rxdb_ch: mailbox rx doorbell channel handle
121 * @pd_list: power domain list
122 * @ipc_handle: System Control Unit ipc handle
123 * @rproc_work: work for processing virtio interrupts
124 * @pm_comp: completion primitive to sync for suspend response
125 * @flags: control flags
126 */
127struct imx_dsp_rproc {
128 struct regmap *regmap;
129 struct reset_control *run_stall;
130 struct rproc *rproc;
131 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
132 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX];
133 struct mbox_client cl;
134 struct mbox_client cl_rxdb;
135 struct mbox_chan *tx_ch;
136 struct mbox_chan *rx_ch;
137 struct mbox_chan *rxdb_ch;
138 struct dev_pm_domain_list *pd_list;
139 struct imx_sc_ipc *ipc_handle;
140 struct work_struct rproc_work;
141 struct completion pm_comp;
142 u32 flags;
143};
144
145/**
146 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration
147 * @dcfg: imx_rproc_dcfg handler
148 * @reset: reset callback function
149 */
150struct imx_dsp_rproc_dcfg {
151 const struct imx_rproc_dcfg *dcfg;
152 int (*reset)(struct imx_dsp_rproc *priv);
153};
154
155/**
156 * struct fw_rsc_imx_dsp - i.MX DSP specific info
157 *
158 * @len: length of the resource entry
159 * @magic_num: 32-bit magic number
160 * @version: version of data structure
161 * @features: feature flags supported by the i.MX DSP firmware
162 *
163 * This represents a DSP-specific resource in the firmware's
164 * resource table, providing information on supported features.
165 */
166struct fw_rsc_imx_dsp {
167 uint32_t len;
168 uint32_t magic_num;
169 uint32_t version;
170 uint32_t features;
171} __packed;
172
173static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = {
174 /* dev addr , sys addr , size , flags */
175 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN },
176 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN },
177 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM},
178 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN },
179 /* DDR (Data) */
180 { 0x80000000, 0x80000000, 0x60000000, 0},
181};
182
183static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = {
184 /* dev addr , sys addr , size , flags */
185 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN },
186 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN },
187 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM},
188 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN },
189 /* DDR (Data) */
190 { 0x80000000, 0x80000000, 0x60000000, 0},
191};
192
193static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = {
194 /* dev addr , sys addr , size , flags */
195 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN },
196 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN },
197 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM},
198 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN },
199 /* DDR (Data) */
200 { 0x40000000, 0x40000000, 0x80000000, 0},
201};
202
203static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = {
204 /* dev addr , sys addr , size , flags */
205 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM},
206 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN },
207 /* DDR (Data) */
208 { 0x0c000000, 0x80000000, 0x10000000, 0},
209 { 0x30000000, 0x90000000, 0x10000000, 0},
210};
211
212/* Initialize the mailboxes between cores, if exists */
213static int (*imx_dsp_rproc_mbox_init)(struct imx_dsp_rproc *priv);
214
215/* Reset function for DSP on i.MX8MP */
216static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv)
217{
218 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);
219 int pwrctl;
220
221 /* Put DSP into reset and stall */
222 pwrctl = readl(addr: dap + IMX8M_DAP_PWRCTL);
223 pwrctl |= IMX8M_PWRCTL_CORERESET;
224 writel(val: pwrctl, addr: dap + IMX8M_DAP_PWRCTL);
225
226 /* Keep reset asserted for 10 cycles */
227 usleep_range(min: 1, max: 2);
228
229 reset_control_assert(rstc: priv->run_stall);
230
231 /* Take the DSP out of reset and keep stalled for FW loading */
232 pwrctl = readl(addr: dap + IMX8M_DAP_PWRCTL);
233 pwrctl &= ~IMX8M_PWRCTL_CORERESET;
234 writel(val: pwrctl, addr: dap + IMX8M_DAP_PWRCTL);
235
236 iounmap(addr: dap);
237 return 0;
238}
239
240/* Reset function for DSP on i.MX8ULP */
241static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv)
242{
243 struct arm_smccc_res res;
244
245 /* Put DSP into reset and stall */
246 regmap_update_bits(map: priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
247 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST);
248 regmap_update_bits(map: priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
249 IMX8ULP_SYSCTRL0_DSP_STALL,
250 IMX8ULP_SYSCTRL0_DSP_STALL);
251
252 /* Configure resources of DSP through TFA */
253 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res);
254
255 /* Take the DSP out of reset and keep stalled for FW loading */
256 regmap_update_bits(map: priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
257 IMX8ULP_SYSCTRL0_DSP_RST, val: 0);
258 regmap_update_bits(map: priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
259 IMX8ULP_SYSCTRL0_DSP_DBG_RST, val: 0);
260
261 return 0;
262}
263
264/* Specific configuration for i.MX8MP */
265static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = {
266 .att = imx_dsp_rproc_att_imx8mp,
267 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp),
268 .method = IMX_RPROC_RESET_CONTROLLER,
269};
270
271static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = {
272 .dcfg = &dsp_rproc_cfg_imx8mp,
273 .reset = imx8mp_dsp_reset,
274};
275
276/* Specific configuration for i.MX8ULP */
277static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = {
278 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0,
279 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL,
280 .src_start = 0,
281 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL,
282 .att = imx_dsp_rproc_att_imx8ulp,
283 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp),
284 .method = IMX_RPROC_MMIO,
285};
286
287static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = {
288 .dcfg = &dsp_rproc_cfg_imx8ulp,
289 .reset = imx8ulp_dsp_reset,
290};
291
292/* Specific configuration for i.MX8QXP */
293static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = {
294 .att = imx_dsp_rproc_att_imx8qxp,
295 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp),
296 .method = IMX_RPROC_SCU_API,
297};
298
299static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = {
300 .dcfg = &dsp_rproc_cfg_imx8qxp,
301};
302
303/* Specific configuration for i.MX8QM */
304static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = {
305 .att = imx_dsp_rproc_att_imx8qm,
306 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm),
307 .method = IMX_RPROC_SCU_API,
308};
309
310static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = {
311 .dcfg = &dsp_rproc_cfg_imx8qm,
312};
313
314static int imx_dsp_rproc_ready(struct rproc *rproc)
315{
316 struct imx_dsp_rproc *priv = rproc->priv;
317 int i;
318
319 if (!priv->rxdb_ch)
320 return 0;
321
322 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) {
323 if (priv->flags & REMOTE_IS_READY)
324 return 0;
325 usleep_range(min: 100, max: 200);
326 }
327
328 return -ETIMEDOUT;
329}
330
331/**
332 * imx_dsp_rproc_handle_rsc() - Handle DSP-specific resource table entries
333 * @rproc: remote processor instance
334 * @rsc_type: resource type identifier
335 * @rsc: pointer to the resource entry
336 * @offset: offset of the resource entry
337 * @avail: available space in the resource table
338 *
339 * Parse the DSP-specific resource entry and update flags accordingly.
340 * If the WAIT_FW_READY feature is set, the host must wait for the firmware
341 * to signal readiness before proceeding with execution.
342 *
343 * Return: RSC_HANDLED if processed successfully, RSC_IGNORED otherwise.
344 */
345static int imx_dsp_rproc_handle_rsc(struct rproc *rproc, u32 rsc_type,
346 void *rsc, int offset, int avail)
347{
348 struct imx_dsp_rproc *priv = rproc->priv;
349 struct fw_rsc_imx_dsp *imx_dsp_rsc = rsc;
350 struct device *dev = rproc->dev.parent;
351
352 if (!imx_dsp_rsc) {
353 dev_dbg(dev, "Invalid fw_rsc_imx_dsp.\n");
354 return RSC_IGNORED;
355 }
356
357 /* Make sure resource isn't truncated */
358 if (sizeof(struct fw_rsc_imx_dsp) > avail ||
359 sizeof(struct fw_rsc_imx_dsp) != imx_dsp_rsc->len) {
360 dev_dbg(dev, "Resource fw_rsc_imx_dsp is truncated.\n");
361 return RSC_IGNORED;
362 }
363
364 /*
365 * If FW_RSC_NXP_S_MAGIC number is not found then
366 * wait for fw_ready reply (default work flow)
367 */
368 if (imx_dsp_rsc->magic_num != FW_RSC_NXP_S_MAGIC) {
369 dev_dbg(dev, "Invalid resource table magic number.\n");
370 return RSC_IGNORED;
371 }
372
373 /*
374 * For now, in struct fw_rsc_imx_dsp, version 0,
375 * only FEATURE_DONT_WAIT_FW_READY is valid.
376 *
377 * When adding new features, please upgrade version.
378 */
379 if (imx_dsp_rsc->version > 0) {
380 dev_warn(dev, "Unexpected fw_rsc_imx_dsp version %d.\n",
381 imx_dsp_rsc->version);
382 return RSC_IGNORED;
383 }
384
385 if (imx_dsp_rsc->features & FEATURE_DONT_WAIT_FW_READY)
386 priv->flags &= ~WAIT_FW_READY;
387
388 return RSC_HANDLED;
389}
390
391/*
392 * Start function for rproc_ops
393 *
394 * There is a handshake for start procedure: when DSP starts, it
395 * will send a doorbell message to this driver, then the
396 * REMOTE_IS_READY flags is set, then driver will kick
397 * a message to DSP.
398 */
399static int imx_dsp_rproc_start(struct rproc *rproc)
400{
401 struct imx_dsp_rproc *priv = rproc->priv;
402 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
403 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
404 struct device *dev = rproc->dev.parent;
405 int ret;
406
407 switch (dcfg->method) {
408 case IMX_RPROC_MMIO:
409 ret = regmap_update_bits(map: priv->regmap,
410 reg: dcfg->src_reg,
411 mask: dcfg->src_mask,
412 val: dcfg->src_start);
413 break;
414 case IMX_RPROC_SCU_API:
415 ret = imx_sc_pm_cpu_start(ipc: priv->ipc_handle,
416 IMX_SC_R_DSP,
417 enable: true,
418 phys_addr: rproc->bootaddr);
419 break;
420 case IMX_RPROC_RESET_CONTROLLER:
421 ret = reset_control_deassert(rstc: priv->run_stall);
422 break;
423 default:
424 return -EOPNOTSUPP;
425 }
426
427 if (ret)
428 dev_err(dev, "Failed to enable remote core!\n");
429 else if (priv->flags & WAIT_FW_READY)
430 return imx_dsp_rproc_ready(rproc);
431
432 return ret;
433}
434
435/*
436 * Stop function for rproc_ops
437 * It clears the REMOTE_IS_READY flags
438 */
439static int imx_dsp_rproc_stop(struct rproc *rproc)
440{
441 struct imx_dsp_rproc *priv = rproc->priv;
442 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
443 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
444 struct device *dev = rproc->dev.parent;
445 int ret = 0;
446
447 if (rproc->state == RPROC_CRASHED) {
448 priv->flags &= ~REMOTE_IS_READY;
449 return 0;
450 }
451
452 switch (dcfg->method) {
453 case IMX_RPROC_MMIO:
454 ret = regmap_update_bits(map: priv->regmap, reg: dcfg->src_reg, mask: dcfg->src_mask,
455 val: dcfg->src_stop);
456 break;
457 case IMX_RPROC_SCU_API:
458 ret = imx_sc_pm_cpu_start(ipc: priv->ipc_handle,
459 IMX_SC_R_DSP,
460 enable: false,
461 phys_addr: rproc->bootaddr);
462 break;
463 case IMX_RPROC_RESET_CONTROLLER:
464 ret = reset_control_assert(rstc: priv->run_stall);
465 break;
466 default:
467 return -EOPNOTSUPP;
468 }
469
470 if (ret)
471 dev_err(dev, "Failed to stop remote core\n");
472 else
473 priv->flags &= ~REMOTE_IS_READY;
474
475 return ret;
476}
477
478/**
479 * imx_dsp_rproc_sys_to_da() - internal memory translation helper
480 * @priv: private data pointer
481 * @sys: system address (DDR address)
482 * @len: length of the memory buffer
483 * @da: device address to translate
484 *
485 * Convert system address (DDR address) to device address (DSP)
486 * for there may be memory remap for device.
487 */
488static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys,
489 size_t len, u64 *da)
490{
491 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
492 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
493 int i;
494
495 /* Parse address translation table */
496 for (i = 0; i < dcfg->att_size; i++) {
497 const struct imx_rproc_att *att = &dcfg->att[i];
498
499 if (sys >= att->sa && sys + len <= att->sa + att->size) {
500 unsigned int offset = sys - att->sa;
501
502 *da = att->da + offset;
503 return 0;
504 }
505 }
506
507 return -ENOENT;
508}
509
510/* Main virtqueue message work function
511 *
512 * This function is executed upon scheduling of the i.MX DSP remoteproc
513 * driver's workqueue. The workqueue is scheduled by the mailbox rx
514 * handler.
515 *
516 * This work function processes both the Tx and Rx virtqueue indices on
517 * every invocation. The rproc_vq_interrupt function can detect if there
518 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED),
519 * but there is no need to check for these return values. The index 0
520 * triggering will process all pending Rx buffers, and the index 1 triggering
521 * will process all newly available Tx buffers and will wakeup any potentially
522 * blocked senders.
523 *
524 * NOTE:
525 * The current logic is based on an inherent design assumption of supporting
526 * only 2 vrings, but this can be changed if needed.
527 */
528static void imx_dsp_rproc_vq_work(struct work_struct *work)
529{
530 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc,
531 rproc_work);
532 struct rproc *rproc = priv->rproc;
533
534 mutex_lock(&rproc->lock);
535
536 if (rproc->state != RPROC_RUNNING)
537 goto unlock_mutex;
538
539 rproc_vq_interrupt(rproc: priv->rproc, vq_id: 0);
540 rproc_vq_interrupt(rproc: priv->rproc, vq_id: 1);
541
542unlock_mutex:
543 mutex_unlock(lock: &rproc->lock);
544}
545
546/**
547 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler
548 * @cl: mailbox client pointer used for requesting the mailbox channel
549 * @data: mailbox payload
550 *
551 * This handler is invoked by mailbox driver whenever a mailbox
552 * message is received. Usually, the SUSPEND and RESUME related messages
553 * are handled in this function, other messages are handled by remoteproc core
554 */
555static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data)
556{
557 struct rproc *rproc = dev_get_drvdata(dev: cl->dev);
558 struct imx_dsp_rproc *priv = rproc->priv;
559 struct device *dev = rproc->dev.parent;
560 u32 message = (u32)(*(u32 *)data);
561
562 dev_dbg(dev, "mbox msg: 0x%x\n", message);
563
564 switch (message) {
565 case RP_MBOX_SUSPEND_ACK:
566 complete(&priv->pm_comp);
567 break;
568 case RP_MBOX_RESUME_ACK:
569 complete(&priv->pm_comp);
570 break;
571 default:
572 schedule_work(work: &priv->rproc_work);
573 break;
574 }
575}
576
577/**
578 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler
579 * @cl: mailbox client pointer used for requesting the mailbox channel
580 * @data: mailbox payload
581 *
582 * For doorbell, there is no message specified, just set REMOTE_IS_READY
583 * flag.
584 */
585static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data)
586{
587 struct rproc *rproc = dev_get_drvdata(dev: cl->dev);
588 struct imx_dsp_rproc *priv = rproc->priv;
589
590 /* Remote is ready after firmware is loaded and running */
591 priv->flags |= REMOTE_IS_READY;
592}
593
594/**
595 * imx_dsp_rproc_mbox_alloc() - request mailbox channels
596 * @priv: private data pointer
597 *
598 * Request three mailbox channels (tx, rx, rxdb).
599 */
600static int imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc *priv)
601{
602 struct device *dev = priv->rproc->dev.parent;
603 struct mbox_client *cl;
604 int ret;
605
606 if (!of_property_present(np: dev->of_node, propname: "mbox-names"))
607 return 0;
608
609 cl = &priv->cl;
610 cl->dev = dev;
611 cl->tx_block = true;
612 cl->tx_tout = 100;
613 cl->knows_txdone = false;
614 cl->rx_callback = imx_dsp_rproc_rx_tx_callback;
615
616 /* Channel for sending message */
617 priv->tx_ch = mbox_request_channel_byname(cl, name: "tx");
618 if (IS_ERR(ptr: priv->tx_ch)) {
619 ret = PTR_ERR(ptr: priv->tx_ch);
620 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n",
621 ret);
622 return ret;
623 }
624
625 /* Channel for receiving message */
626 priv->rx_ch = mbox_request_channel_byname(cl, name: "rx");
627 if (IS_ERR(ptr: priv->rx_ch)) {
628 ret = PTR_ERR(ptr: priv->rx_ch);
629 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n",
630 ret);
631 goto free_channel_tx;
632 }
633
634 cl = &priv->cl_rxdb;
635 cl->dev = dev;
636 cl->rx_callback = imx_dsp_rproc_rxdb_callback;
637
638 /*
639 * RX door bell is used to receive the ready signal from remote
640 * after firmware loaded.
641 */
642 priv->rxdb_ch = mbox_request_channel_byname(cl, name: "rxdb");
643 if (IS_ERR(ptr: priv->rxdb_ch)) {
644 ret = PTR_ERR(ptr: priv->rxdb_ch);
645 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n",
646 ret);
647 goto free_channel_rx;
648 }
649
650 return 0;
651
652free_channel_rx:
653 mbox_free_channel(chan: priv->rx_ch);
654free_channel_tx:
655 mbox_free_channel(chan: priv->tx_ch);
656 return ret;
657}
658
659/*
660 * imx_dsp_rproc_mbox_no_alloc()
661 *
662 * Empty function for no mailbox between cores
663 *
664 * Always return 0
665 */
666static int imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc *priv)
667{
668 return 0;
669}
670
671static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv)
672{
673 mbox_free_channel(chan: priv->tx_ch);
674 mbox_free_channel(chan: priv->rx_ch);
675 mbox_free_channel(chan: priv->rxdb_ch);
676}
677
678/**
679 * imx_dsp_rproc_add_carveout() - request mailbox channels
680 * @priv: private data pointer
681 *
682 * This function registers specified memory entry in @rproc carveouts list
683 * The carveouts can help to mapping the memory address for DSP.
684 */
685static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv)
686{
687 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
688 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg;
689 struct rproc *rproc = priv->rproc;
690 struct device *dev = rproc->dev.parent;
691 struct device_node *np = dev->of_node;
692 struct of_phandle_iterator it;
693 struct rproc_mem_entry *mem;
694 struct reserved_mem *rmem;
695 void __iomem *cpu_addr;
696 int a;
697 u64 da;
698
699 /* Remap required addresses */
700 for (a = 0; a < dcfg->att_size; a++) {
701 const struct imx_rproc_att *att = &dcfg->att[a];
702
703 if (!(att->flags & ATT_OWN))
704 continue;
705
706 if (imx_dsp_rproc_sys_to_da(priv, sys: att->sa, len: att->size, da: &da))
707 return -EINVAL;
708
709 cpu_addr = devm_ioremap_wc(dev, offset: att->sa, size: att->size);
710 if (!cpu_addr) {
711 dev_err(dev, "failed to map memory %p\n", &att->sa);
712 return -ENOMEM;
713 }
714
715 /* Register memory region */
716 mem = rproc_mem_entry_init(dev, va: (void __force *)cpu_addr, dma: (dma_addr_t)att->sa,
717 len: att->size, da, NULL, NULL, name: "dsp_mem");
718
719 if (mem)
720 rproc_coredump_add_segment(rproc, da, size: att->size);
721 else
722 return -ENOMEM;
723
724 rproc_add_carveout(rproc, mem);
725 }
726
727 of_phandle_iterator_init(it: &it, np, list_name: "memory-region", NULL, cell_count: 0);
728 while (of_phandle_iterator_next(it: &it) == 0) {
729 /*
730 * Ignore the first memory region which will be used vdev buffer.
731 * No need to do extra handlings, rproc_add_virtio_dev will handle it.
732 */
733 if (!strcmp(it.node->name, "vdev0buffer"))
734 continue;
735
736 rmem = of_reserved_mem_lookup(np: it.node);
737 if (!rmem) {
738 of_node_put(node: it.node);
739 dev_err(dev, "unable to acquire memory-region\n");
740 return -EINVAL;
741 }
742
743 if (imx_dsp_rproc_sys_to_da(priv, sys: rmem->base, len: rmem->size, da: &da)) {
744 of_node_put(node: it.node);
745 return -EINVAL;
746 }
747
748 cpu_addr = devm_ioremap_wc(dev, offset: rmem->base, size: rmem->size);
749 if (!cpu_addr) {
750 of_node_put(node: it.node);
751 dev_err(dev, "failed to map memory %p\n", &rmem->base);
752 return -ENOMEM;
753 }
754
755 /* Register memory region */
756 mem = rproc_mem_entry_init(dev, va: (void __force *)cpu_addr, dma: (dma_addr_t)rmem->base,
757 len: rmem->size, da, NULL, NULL, name: it.node->name);
758
759 if (mem) {
760 rproc_coredump_add_segment(rproc, da, size: rmem->size);
761 } else {
762 of_node_put(node: it.node);
763 return -ENOMEM;
764 }
765
766 rproc_add_carveout(rproc, mem);
767 }
768
769 return 0;
770}
771
772/* Prepare function for rproc_ops */
773static int imx_dsp_rproc_prepare(struct rproc *rproc)
774{
775 struct imx_dsp_rproc *priv = rproc->priv;
776 struct device *dev = rproc->dev.parent;
777 struct rproc_mem_entry *carveout;
778 int ret;
779
780 ret = imx_dsp_rproc_add_carveout(priv);
781 if (ret) {
782 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n");
783 return ret;
784 }
785
786 pm_runtime_get_sync(dev);
787
788 /*
789 * Clear buffers after pm rumtime for internal ocram is not
790 * accessible if power and clock are not enabled.
791 */
792 list_for_each_entry(carveout, &rproc->carveouts, node) {
793 if (carveout->va)
794 memset(carveout->va, 0, carveout->len);
795 }
796
797 return 0;
798}
799
800/* Unprepare function for rproc_ops */
801static int imx_dsp_rproc_unprepare(struct rproc *rproc)
802{
803 pm_runtime_put_sync(dev: rproc->dev.parent);
804
805 return 0;
806}
807
808/* Kick function for rproc_ops */
809static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid)
810{
811 struct imx_dsp_rproc *priv = rproc->priv;
812 struct device *dev = rproc->dev.parent;
813 int err;
814 __u32 mmsg;
815
816 if (!priv->tx_ch) {
817 dev_err(dev, "No initialized mbox tx channel\n");
818 return;
819 }
820
821 /*
822 * Send the index of the triggered virtqueue as the mu payload.
823 * Let remote processor know which virtqueue is used.
824 */
825 mmsg = vqid;
826
827 err = mbox_send_message(chan: priv->tx_ch, mssg: (void *)&mmsg);
828 if (err < 0)
829 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err);
830}
831
832/*
833 * Custom memory copy implementation for i.MX DSP Cores
834 *
835 * The IRAM is part of the HiFi DSP.
836 * According to hw specs only 32-bits writes are allowed.
837 */
838static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size)
839{
840 void __iomem *dest = (void __iomem *)dst;
841 const u8 *src_byte = src;
842 const u32 *source = src;
843 u32 affected_mask;
844 int i, q, r;
845 u32 tmp;
846
847 /* destination must be 32bit aligned */
848 if (!IS_ALIGNED((uintptr_t)dest, 4))
849 return -EINVAL;
850
851 q = size / 4;
852 r = size % 4;
853
854 /* copy data in units of 32 bits at a time */
855 for (i = 0; i < q; i++)
856 writel(val: source[i], addr: dest + i * 4);
857
858 if (r) {
859 affected_mask = GENMASK(8 * r, 0);
860
861 /*
862 * first read the 32bit data of dest, then change affected
863 * bytes, and write back to dest.
864 * For unaffected bytes, it should not be changed
865 */
866 tmp = readl(addr: dest + q * 4);
867 tmp &= ~affected_mask;
868
869 /* avoid reading after end of source */
870 for (i = 0; i < r; i++)
871 tmp |= (src_byte[q * 4 + i] << (8 * i));
872
873 writel(val: tmp, addr: dest + q * 4);
874 }
875
876 return 0;
877}
878
879/*
880 * Custom memset implementation for i.MX DSP Cores
881 *
882 * The IRAM is part of the HiFi DSP.
883 * According to hw specs only 32-bits writes are allowed.
884 */
885static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size)
886{
887 void __iomem *tmp_dst = (void __iomem *)addr;
888 u32 tmp_val = value;
889 u32 affected_mask;
890 int q, r;
891 u32 tmp;
892
893 /* destination must be 32bit aligned */
894 if (!IS_ALIGNED((uintptr_t)addr, 4))
895 return -EINVAL;
896
897 tmp_val |= tmp_val << 8;
898 tmp_val |= tmp_val << 16;
899
900 q = size / 4;
901 r = size % 4;
902
903 while (q--)
904 writel(val: tmp_val, addr: tmp_dst++);
905
906 if (r) {
907 affected_mask = GENMASK(8 * r, 0);
908
909 /*
910 * first read the 32bit data of addr, then change affected
911 * bytes, and write back to addr.
912 * For unaffected bytes, it should not be changed
913 */
914 tmp = readl(addr: tmp_dst);
915 tmp &= ~affected_mask;
916
917 tmp |= (tmp_val & affected_mask);
918 writel(val: tmp, addr: tmp_dst);
919 }
920
921 return 0;
922}
923
924/*
925 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory
926 * @rproc: remote processor which will be booted using these fw segments
927 * @fw: the ELF firmware image
928 *
929 * This function loads the firmware segments to memory, where the remote
930 * processor expects them.
931 *
932 * Return: 0 on success and an appropriate error code otherwise
933 */
934static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw)
935{
936 struct device *dev = &rproc->dev;
937 const void *ehdr, *phdr;
938 int i, ret = 0;
939 u16 phnum;
940 const u8 *elf_data = fw->data;
941 u8 class = fw_elf_get_class(fw);
942 u32 elf_phdr_get_size = elf_size_of_phdr(class);
943
944 ehdr = elf_data;
945 phnum = elf_hdr_get_e_phnum(class, arg: ehdr);
946 phdr = elf_data + elf_hdr_get_e_phoff(class, arg: ehdr);
947
948 /* go through the available ELF segments */
949 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) {
950 u64 da = elf_phdr_get_p_paddr(class, arg: phdr);
951 u64 memsz = elf_phdr_get_p_memsz(class, arg: phdr);
952 u64 filesz = elf_phdr_get_p_filesz(class, arg: phdr);
953 u64 offset = elf_phdr_get_p_offset(class, arg: phdr);
954 u32 type = elf_phdr_get_p_type(class, arg: phdr);
955 void *ptr;
956
957 if (type != PT_LOAD || !memsz)
958 continue;
959
960 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n",
961 type, da, memsz, filesz);
962
963 if (filesz > memsz) {
964 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n",
965 filesz, memsz);
966 ret = -EINVAL;
967 break;
968 }
969
970 if (offset + filesz > fw->size) {
971 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n",
972 offset + filesz, fw->size);
973 ret = -EINVAL;
974 break;
975 }
976
977 if (!rproc_u64_fit_in_size_t(val: memsz)) {
978 dev_err(dev, "size (%llx) does not fit in size_t type\n",
979 memsz);
980 ret = -EOVERFLOW;
981 break;
982 }
983
984 /* grab the kernel address for this device address */
985 ptr = rproc_da_to_va(rproc, da, len: memsz, NULL);
986 if (!ptr) {
987 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da,
988 memsz);
989 ret = -EINVAL;
990 break;
991 }
992
993 /* put the segment where the remote processor expects it */
994 if (filesz) {
995 ret = imx_dsp_rproc_memcpy(dst: ptr, src: elf_data + offset, size: filesz);
996 if (ret) {
997 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n",
998 da, memsz);
999 break;
1000 }
1001 }
1002
1003 /* zero out remaining memory for this segment */
1004 if (memsz > filesz) {
1005 ret = imx_dsp_rproc_memset(addr: ptr + filesz, value: 0, size: memsz - filesz);
1006 if (ret) {
1007 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n",
1008 da, memsz);
1009 break;
1010 }
1011 }
1012 }
1013
1014 return ret;
1015}
1016
1017static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
1018{
1019 if (rproc_elf_load_rsc_table(rproc, fw))
1020 dev_warn(&rproc->dev, "no resource table found for this firmware\n");
1021
1022 return 0;
1023}
1024
1025static const struct rproc_ops imx_dsp_rproc_ops = {
1026 .prepare = imx_dsp_rproc_prepare,
1027 .unprepare = imx_dsp_rproc_unprepare,
1028 .start = imx_dsp_rproc_start,
1029 .stop = imx_dsp_rproc_stop,
1030 .kick = imx_dsp_rproc_kick,
1031 .load = imx_dsp_rproc_elf_load_segments,
1032 .parse_fw = imx_dsp_rproc_parse_fw,
1033 .handle_rsc = imx_dsp_rproc_handle_rsc,
1034 .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
1035 .sanity_check = rproc_elf_sanity_check,
1036 .get_boot_addr = rproc_elf_get_boot_addr,
1037};
1038
1039/**
1040 * imx_dsp_attach_pm_domains() - attach the power domains
1041 * @priv: private data pointer
1042 *
1043 * On i.MX8QM and i.MX8QXP there is multiple power domains
1044 * required, so need to link them.
1045 */
1046static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv)
1047{
1048 struct device *dev = priv->rproc->dev.parent;
1049 int ret;
1050
1051 /* A single PM domain is already attached. */
1052 if (dev->pm_domain)
1053 return 0;
1054
1055 ret = dev_pm_domain_attach_list(dev, NULL, list: &priv->pd_list);
1056 return ret < 0 ? ret : 0;
1057}
1058
1059/**
1060 * imx_dsp_rproc_detect_mode() - detect DSP control mode
1061 * @priv: private data pointer
1062 *
1063 * Different platform has different control method for DSP, which depends
1064 * on how the DSP is integrated in platform.
1065 *
1066 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System
1067 * Control Unit.
1068 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system
1069 * integration module.
1070 */
1071static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv)
1072{
1073 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
1074 struct device *dev = priv->rproc->dev.parent;
1075 struct regmap *regmap;
1076 int ret = 0;
1077
1078 switch (dsp_dcfg->dcfg->method) {
1079 case IMX_RPROC_SCU_API:
1080 ret = imx_scu_get_handle(ipc: &priv->ipc_handle);
1081 if (ret)
1082 return ret;
1083 break;
1084 case IMX_RPROC_MMIO:
1085 regmap = syscon_regmap_lookup_by_phandle(np: dev->of_node, property: "fsl,dsp-ctrl");
1086 if (IS_ERR(ptr: regmap)) {
1087 dev_err(dev, "failed to find syscon\n");
1088 return PTR_ERR(ptr: regmap);
1089 }
1090
1091 priv->regmap = regmap;
1092 break;
1093 case IMX_RPROC_RESET_CONTROLLER:
1094 priv->run_stall = devm_reset_control_get_exclusive(dev, id: "runstall");
1095 if (IS_ERR(ptr: priv->run_stall)) {
1096 dev_err(dev, "Failed to get DSP runstall reset control\n");
1097 return PTR_ERR(ptr: priv->run_stall);
1098 }
1099 break;
1100 default:
1101 ret = -EOPNOTSUPP;
1102 break;
1103 }
1104
1105 return ret;
1106}
1107
1108static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = {
1109 /* DSP clocks */
1110 "core", "ocram", "debug", "ipg", "mu",
1111};
1112
1113static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv)
1114{
1115 struct device *dev = priv->rproc->dev.parent;
1116 struct clk_bulk_data *clks = priv->clks;
1117 int i;
1118
1119 for (i = 0; i < DSP_RPROC_CLK_MAX; i++)
1120 clks[i].id = imx_dsp_clks_names[i];
1121
1122 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks);
1123}
1124
1125static int imx_dsp_rproc_probe(struct platform_device *pdev)
1126{
1127 const struct imx_dsp_rproc_dcfg *dsp_dcfg;
1128 struct device *dev = &pdev->dev;
1129 struct imx_dsp_rproc *priv;
1130 struct rproc *rproc;
1131 const char *fw_name;
1132 int ret;
1133
1134 dsp_dcfg = of_device_get_match_data(dev);
1135 if (!dsp_dcfg)
1136 return -ENODEV;
1137
1138 ret = rproc_of_parse_firmware(dev, index: 0, fw_name: &fw_name);
1139 if (ret) {
1140 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1141 ret);
1142 return ret;
1143 }
1144
1145 rproc = devm_rproc_alloc(dev, name: "imx-dsp-rproc", ops: &imx_dsp_rproc_ops,
1146 firmware: fw_name, len: sizeof(*priv));
1147 if (!rproc)
1148 return -ENOMEM;
1149
1150 priv = rproc->priv;
1151 priv->rproc = rproc;
1152 priv->dsp_dcfg = dsp_dcfg;
1153 /* By default, host waits for fw_ready reply */
1154 priv->flags |= WAIT_FW_READY;
1155
1156 if (no_mailboxes)
1157 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_no_alloc;
1158 else
1159 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_alloc;
1160
1161 dev_set_drvdata(dev, data: rproc);
1162
1163 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work);
1164
1165 ret = imx_dsp_rproc_detect_mode(priv);
1166 if (ret) {
1167 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n");
1168 return ret;
1169 }
1170
1171 /* There are multiple power domains required by DSP on some platform */
1172 ret = imx_dsp_attach_pm_domains(priv);
1173 if (ret) {
1174 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n");
1175 return ret;
1176 }
1177 /* Get clocks */
1178 ret = imx_dsp_rproc_clk_get(priv);
1179 if (ret) {
1180 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n");
1181 goto err_detach_domains;
1182 }
1183
1184 init_completion(x: &priv->pm_comp);
1185 rproc->auto_boot = false;
1186 ret = rproc_add(rproc);
1187 if (ret) {
1188 dev_err(dev, "rproc_add failed\n");
1189 goto err_detach_domains;
1190 }
1191
1192 pm_runtime_enable(dev);
1193
1194 return 0;
1195
1196err_detach_domains:
1197 dev_pm_domain_detach_list(list: priv->pd_list);
1198
1199 return ret;
1200}
1201
1202static void imx_dsp_rproc_remove(struct platform_device *pdev)
1203{
1204 struct rproc *rproc = platform_get_drvdata(pdev);
1205 struct imx_dsp_rproc *priv = rproc->priv;
1206
1207 pm_runtime_disable(dev: &pdev->dev);
1208 rproc_del(rproc);
1209 dev_pm_domain_detach_list(list: priv->pd_list);
1210}
1211
1212/* pm runtime functions */
1213static int imx_dsp_runtime_resume(struct device *dev)
1214{
1215 struct rproc *rproc = dev_get_drvdata(dev);
1216 struct imx_dsp_rproc *priv = rproc->priv;
1217 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg;
1218 int ret;
1219
1220 /*
1221 * There is power domain attached with mailbox, if setup mailbox
1222 * in probe(), then the power of mailbox is always enabled,
1223 * the power can't be saved.
1224 * So move setup of mailbox to runtime resume.
1225 */
1226 ret = imx_dsp_rproc_mbox_init(priv);
1227 if (ret) {
1228 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n");
1229 return ret;
1230 }
1231
1232 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, clks: priv->clks);
1233 if (ret) {
1234 dev_err(dev, "failed on clk_bulk_prepare_enable\n");
1235 return ret;
1236 }
1237
1238 /* Reset DSP if needed */
1239 if (dsp_dcfg->reset)
1240 dsp_dcfg->reset(priv);
1241
1242 return 0;
1243}
1244
1245static int imx_dsp_runtime_suspend(struct device *dev)
1246{
1247 struct rproc *rproc = dev_get_drvdata(dev);
1248 struct imx_dsp_rproc *priv = rproc->priv;
1249
1250 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, clks: priv->clks);
1251
1252 imx_dsp_rproc_free_mbox(priv);
1253
1254 return 0;
1255}
1256
1257static void imx_dsp_load_firmware(const struct firmware *fw, void *context)
1258{
1259 struct rproc *rproc = context;
1260 int ret;
1261
1262 /*
1263 * Same flow as start procedure.
1264 * Load the ELF segments to memory firstly.
1265 */
1266 ret = rproc_load_segments(rproc, fw);
1267 if (ret)
1268 goto out;
1269
1270 /* Start the remote processor */
1271 ret = rproc->ops->start(rproc);
1272 if (ret)
1273 goto out;
1274
1275 rproc->ops->kick(rproc, 0);
1276
1277out:
1278 release_firmware(fw);
1279}
1280
1281static int imx_dsp_suspend(struct device *dev)
1282{
1283 struct rproc *rproc = dev_get_drvdata(dev);
1284 struct imx_dsp_rproc *priv = rproc->priv;
1285 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM;
1286 int ret;
1287
1288 if (rproc->state != RPROC_RUNNING)
1289 goto out;
1290
1291 reinit_completion(x: &priv->pm_comp);
1292
1293 /* Tell DSP that suspend is happening */
1294 ret = mbox_send_message(chan: priv->tx_ch, mssg: (void *)&mmsg);
1295 if (ret < 0) {
1296 dev_err(dev, "PM mbox_send_message failed: %d\n", ret);
1297 return ret;
1298 }
1299
1300 /*
1301 * DSP need to save the context at suspend.
1302 * Here waiting the response for DSP, then power can be disabled.
1303 */
1304 if (!wait_for_completion_timeout(x: &priv->pm_comp, timeout: msecs_to_jiffies(m: 100)))
1305 return -EBUSY;
1306
1307out:
1308 /*
1309 * The power of DSP is disabled in suspend, so force pm runtime
1310 * to be suspend, then we can reenable the power and clocks at
1311 * resume stage.
1312 */
1313 return pm_runtime_force_suspend(dev);
1314}
1315
1316static int imx_dsp_resume(struct device *dev)
1317{
1318 struct rproc *rproc = dev_get_drvdata(dev);
1319 int ret = 0;
1320
1321 ret = pm_runtime_force_resume(dev);
1322 if (ret)
1323 return ret;
1324
1325 if (rproc->state != RPROC_RUNNING)
1326 return 0;
1327
1328 /*
1329 * The power of DSP is disabled at suspend, the memory of dsp
1330 * is reset, the image segments are lost. So need to reload
1331 * firmware and restart the DSP if it is in running state.
1332 */
1333 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
1334 name: rproc->firmware, device: dev, GFP_KERNEL,
1335 context: rproc, cont: imx_dsp_load_firmware);
1336 if (ret < 0) {
1337 dev_err(dev, "load firmware failed: %d\n", ret);
1338 goto err;
1339 }
1340
1341 return 0;
1342
1343err:
1344 pm_runtime_force_suspend(dev);
1345
1346 return ret;
1347}
1348
1349static const struct dev_pm_ops imx_dsp_rproc_pm_ops = {
1350 SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
1351 RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL)
1352};
1353
1354static const struct of_device_id imx_dsp_rproc_of_match[] = {
1355 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp },
1356 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm },
1357 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp },
1358 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp },
1359 {},
1360};
1361MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match);
1362
1363static struct platform_driver imx_dsp_rproc_driver = {
1364 .probe = imx_dsp_rproc_probe,
1365 .remove = imx_dsp_rproc_remove,
1366 .driver = {
1367 .name = "imx-dsp-rproc",
1368 .of_match_table = imx_dsp_rproc_of_match,
1369 .pm = pm_ptr(&imx_dsp_rproc_pm_ops),
1370 },
1371};
1372module_platform_driver(imx_dsp_rproc_driver);
1373
1374MODULE_LICENSE("GPL v2");
1375MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver");
1376MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>");
1377

source code of linux/drivers/remoteproc/imx_dsp_rproc.c