1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2019, Linaro Limited |
3 | |
4 | #include <linux/clk.h> |
5 | #include <linux/completion.h> |
6 | #include <linux/interrupt.h> |
7 | #include <linux/io.h> |
8 | #include <linux/kernel.h> |
9 | #include <linux/module.h> |
10 | #include <linux/debugfs.h> |
11 | #include <linux/of.h> |
12 | #include <linux/of_irq.h> |
13 | #include <linux/pm_runtime.h> |
14 | #include <linux/regmap.h> |
15 | #include <linux/reset.h> |
16 | #include <linux/slab.h> |
17 | #include <linux/pm_wakeirq.h> |
18 | #include <linux/slimbus.h> |
19 | #include <linux/soundwire/sdw.h> |
20 | #include <linux/soundwire/sdw_registers.h> |
21 | #include <sound/pcm_params.h> |
22 | #include <sound/soc.h> |
23 | #include "bus.h" |
24 | |
25 | #define SWRM_COMP_SW_RESET 0x008 |
26 | #define SWRM_COMP_STATUS 0x014 |
27 | #define SWRM_LINK_MANAGER_EE 0x018 |
28 | #define SWRM_EE_CPU 1 |
29 | #define SWRM_FRM_GEN_ENABLED BIT(0) |
30 | #define SWRM_VERSION_1_3_0 0x01030000 |
31 | #define SWRM_VERSION_1_5_1 0x01050001 |
32 | #define SWRM_VERSION_1_7_0 0x01070000 |
33 | #define SWRM_VERSION_2_0_0 0x02000000 |
34 | #define SWRM_COMP_HW_VERSION 0x00 |
35 | #define SWRM_COMP_CFG_ADDR 0x04 |
36 | #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) |
37 | #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) |
38 | #define SWRM_COMP_PARAMS 0x100 |
39 | #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) |
40 | #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) |
41 | #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) |
42 | #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) |
43 | #define SWRM_COMP_MASTER_ID 0x104 |
44 | #define SWRM_V1_3_INTERRUPT_STATUS 0x200 |
45 | #define SWRM_V2_0_INTERRUPT_STATUS 0x5000 |
46 | #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) |
47 | #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) |
48 | #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) |
49 | #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) |
50 | #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) |
51 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) |
52 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) |
53 | #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) |
54 | #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) |
55 | #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) |
56 | #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) |
57 | #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) |
58 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) |
59 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) |
60 | #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) |
61 | #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) |
62 | #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) |
63 | #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED BIT(19) |
64 | #define SWRM_INTERRUPT_MAX 17 |
65 | #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 |
66 | #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 |
67 | #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 |
68 | #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 |
69 | #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 |
70 | #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 |
71 | #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 |
72 | #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 |
73 | #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 |
74 | #define SWRM_CMD_FIFO_CMD 0x308 |
75 | #define SWRM_CMD_FIFO_FLUSH 0x1 |
76 | #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C |
77 | #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 |
78 | #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) |
79 | #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) |
80 | #define SWRM_CMD_FIFO_CFG_ADDR 0x314 |
81 | #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) |
82 | #define SWRM_RD_WR_CMD_RETRIES 0x7 |
83 | #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 |
84 | #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 |
85 | #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) |
86 | #define SWRM_ENUMERATOR_CFG_ADDR 0x500 |
87 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) |
88 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) |
89 | #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) |
90 | #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) |
91 | #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) |
92 | #define SWRM_MCP_BUS_CTRL 0x1044 |
93 | #define SWRM_MCP_BUS_CLK_START BIT(1) |
94 | #define SWRM_MCP_CFG_ADDR 0x1048 |
95 | #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) |
96 | #define SWRM_DEF_CMD_NO_PINGS 0x1f |
97 | #define SWRM_MCP_STATUS 0x104C |
98 | #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) |
99 | #define SWRM_MCP_SLV_STATUS 0x1090 |
100 | #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) |
101 | #define SWRM_MCP_SLV_STATUS_SZ 2 |
102 | #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) |
103 | #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) |
104 | #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) |
105 | #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) |
106 | #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) |
107 | #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) |
108 | #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) |
109 | #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) |
110 | #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 |
111 | #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac |
112 | |
113 | #define SWRM_V2_0_CLK_CTRL 0x5060 |
114 | #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) |
115 | #define SWRM_V2_0_LINK_STATUS 0x5064 |
116 | |
117 | #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 |
118 | #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 |
119 | #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 |
120 | #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 |
121 | #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 |
122 | #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d |
123 | #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 |
124 | |
125 | #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ |
126 | ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) |
127 | |
128 | #define MAX_FREQ_NUM 1 |
129 | #define TIMEOUT_MS 100 |
130 | #define QCOM_SWRM_MAX_RD_LEN 0x1 |
131 | #define QCOM_SDW_MAX_PORTS 14 |
132 | #define DEFAULT_CLK_FREQ 9600000 |
133 | #define SWRM_MAX_DAIS 0xF |
134 | #define SWR_INVALID_PARAM 0xFF |
135 | #define SWR_HSTOP_MAX_VAL 0xF |
136 | #define SWR_HSTART_MIN_VAL 0x0 |
137 | #define SWR_BROADCAST_CMD_ID 0x0F |
138 | #define SWR_MAX_CMD_ID 14 |
139 | #define MAX_FIFO_RD_RETRY 3 |
140 | #define SWR_OVERFLOW_RETRY_COUNT 30 |
141 | #define SWRM_LINK_STATUS_RETRY_CNT 100 |
142 | |
143 | enum { |
144 | MASTER_ID_WSA = 1, |
145 | MASTER_ID_RX, |
146 | MASTER_ID_TX |
147 | }; |
148 | |
149 | struct qcom_swrm_port_config { |
150 | u16 si; |
151 | u8 off1; |
152 | u8 off2; |
153 | u8 bp_mode; |
154 | u8 hstart; |
155 | u8 hstop; |
156 | u8 word_length; |
157 | u8 blk_group_count; |
158 | u8 lane_control; |
159 | }; |
160 | |
161 | /* |
162 | * Internal IDs for different register layouts. Only few registers differ per |
163 | * each variant, so the list of IDs below does not include all of registers. |
164 | */ |
165 | enum { |
166 | SWRM_REG_FRAME_GEN_ENABLED, |
167 | SWRM_REG_INTERRUPT_STATUS, |
168 | SWRM_REG_INTERRUPT_MASK_ADDR, |
169 | SWRM_REG_INTERRUPT_CLEAR, |
170 | SWRM_REG_INTERRUPT_CPU_EN, |
171 | SWRM_REG_CMD_FIFO_WR_CMD, |
172 | SWRM_REG_CMD_FIFO_RD_CMD, |
173 | SWRM_REG_CMD_FIFO_STATUS, |
174 | SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, |
175 | }; |
176 | |
177 | struct qcom_swrm_ctrl { |
178 | struct sdw_bus bus; |
179 | struct device *dev; |
180 | struct regmap *regmap; |
181 | u32 max_reg; |
182 | const unsigned int *reg_layout; |
183 | void __iomem *mmio; |
184 | struct reset_control *audio_cgcr; |
185 | #ifdef CONFIG_DEBUG_FS |
186 | struct dentry *debugfs; |
187 | #endif |
188 | struct completion broadcast; |
189 | struct completion enumeration; |
190 | /* Port alloc/free lock */ |
191 | struct mutex port_lock; |
192 | struct clk *hclk; |
193 | int irq; |
194 | unsigned int version; |
195 | int wake_irq; |
196 | int num_din_ports; |
197 | int num_dout_ports; |
198 | int cols_index; |
199 | int rows_index; |
200 | unsigned long dout_port_mask; |
201 | unsigned long din_port_mask; |
202 | u32 intr_mask; |
203 | u8 rcmd_id; |
204 | u8 wcmd_id; |
205 | /* Port numbers are 1 - 14 */ |
206 | struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1]; |
207 | struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; |
208 | enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; |
209 | int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); |
210 | int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); |
211 | u32 slave_status; |
212 | u32 wr_fifo_depth; |
213 | u32 rd_fifo_depth; |
214 | bool clock_stop_not_supported; |
215 | }; |
216 | |
217 | struct qcom_swrm_data { |
218 | u32 default_cols; |
219 | u32 default_rows; |
220 | bool sw_clk_gate_required; |
221 | u32 max_reg; |
222 | const unsigned int *reg_layout; |
223 | }; |
224 | |
225 | static const unsigned int swrm_v1_3_reg_layout[] = { |
226 | [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, |
227 | [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, |
228 | [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, |
229 | [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, |
230 | [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, |
231 | [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, |
232 | [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, |
233 | [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, |
234 | [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, |
235 | }; |
236 | |
237 | static const struct qcom_swrm_data swrm_v1_3_data = { |
238 | .default_rows = 48, |
239 | .default_cols = 16, |
240 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
241 | .reg_layout = swrm_v1_3_reg_layout, |
242 | }; |
243 | |
244 | static const struct qcom_swrm_data swrm_v1_5_data = { |
245 | .default_rows = 50, |
246 | .default_cols = 16, |
247 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
248 | .reg_layout = swrm_v1_3_reg_layout, |
249 | }; |
250 | |
251 | static const struct qcom_swrm_data swrm_v1_6_data = { |
252 | .default_rows = 50, |
253 | .default_cols = 16, |
254 | .sw_clk_gate_required = true, |
255 | .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, |
256 | .reg_layout = swrm_v1_3_reg_layout, |
257 | }; |
258 | |
259 | static const unsigned int swrm_v2_0_reg_layout[] = { |
260 | [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, |
261 | [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, |
262 | [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ |
263 | [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, |
264 | [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, |
265 | [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, |
266 | [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, |
267 | [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, |
268 | [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, |
269 | }; |
270 | |
271 | static const struct qcom_swrm_data swrm_v2_0_data = { |
272 | .default_rows = 50, |
273 | .default_cols = 16, |
274 | .sw_clk_gate_required = true, |
275 | .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, |
276 | .reg_layout = swrm_v2_0_reg_layout, |
277 | }; |
278 | |
279 | #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) |
280 | |
281 | static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
282 | u32 *val) |
283 | { |
284 | struct regmap *wcd_regmap = ctrl->regmap; |
285 | int ret; |
286 | |
287 | /* pg register + offset */ |
288 | ret = regmap_bulk_write(map: wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, |
289 | val: (u8 *)®, val_count: 4); |
290 | if (ret < 0) |
291 | return SDW_CMD_FAIL; |
292 | |
293 | ret = regmap_bulk_read(map: wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, |
294 | val, val_count: 4); |
295 | if (ret < 0) |
296 | return SDW_CMD_FAIL; |
297 | |
298 | return SDW_CMD_OK; |
299 | } |
300 | |
301 | static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, |
302 | int reg, int val) |
303 | { |
304 | struct regmap *wcd_regmap = ctrl->regmap; |
305 | int ret; |
306 | /* pg register + offset */ |
307 | ret = regmap_bulk_write(map: wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, |
308 | val: (u8 *)&val, val_count: 4); |
309 | if (ret) |
310 | return SDW_CMD_FAIL; |
311 | |
312 | /* write address register */ |
313 | ret = regmap_bulk_write(map: wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, |
314 | val: (u8 *)®, val_count: 4); |
315 | if (ret) |
316 | return SDW_CMD_FAIL; |
317 | |
318 | return SDW_CMD_OK; |
319 | } |
320 | |
321 | static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, |
322 | u32 *val) |
323 | { |
324 | *val = readl(addr: ctrl->mmio + reg); |
325 | return SDW_CMD_OK; |
326 | } |
327 | |
328 | static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, |
329 | int val) |
330 | { |
331 | writel(val, addr: ctrl->mmio + reg); |
332 | return SDW_CMD_OK; |
333 | } |
334 | |
335 | static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, |
336 | u8 dev_addr, u16 reg_addr) |
337 | { |
338 | u32 val; |
339 | u8 id = *cmd_id; |
340 | |
341 | if (id != SWR_BROADCAST_CMD_ID) { |
342 | if (id < SWR_MAX_CMD_ID) |
343 | id += 1; |
344 | else |
345 | id = 0; |
346 | *cmd_id = id; |
347 | } |
348 | val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); |
349 | |
350 | return val; |
351 | } |
352 | |
353 | static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) |
354 | { |
355 | u32 fifo_outstanding_data, value; |
356 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; |
357 | |
358 | do { |
359 | /* Check for fifo underflow during read */ |
360 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
361 | &value); |
362 | fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); |
363 | |
364 | /* Check if read data is available in read fifo */ |
365 | if (fifo_outstanding_data > 0) |
366 | return 0; |
367 | |
368 | usleep_range(min: 500, max: 510); |
369 | } while (fifo_retry_count--); |
370 | |
371 | if (fifo_outstanding_data == 0) { |
372 | dev_err_ratelimited(ctrl->dev, "%s err read underflow\n" , __func__); |
373 | return -EIO; |
374 | } |
375 | |
376 | return 0; |
377 | } |
378 | |
379 | static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) |
380 | { |
381 | u32 fifo_outstanding_cmds, value; |
382 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; |
383 | |
384 | do { |
385 | /* Check for fifo overflow during write */ |
386 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
387 | &value); |
388 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); |
389 | |
390 | /* Check for space in write fifo before writing */ |
391 | if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) |
392 | return 0; |
393 | |
394 | usleep_range(min: 500, max: 510); |
395 | } while (fifo_retry_count--); |
396 | |
397 | if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { |
398 | dev_err_ratelimited(ctrl->dev, "%s err write overflow\n" , __func__); |
399 | return -EIO; |
400 | } |
401 | |
402 | return 0; |
403 | } |
404 | |
405 | static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) |
406 | { |
407 | u32 fifo_outstanding_cmds, value; |
408 | int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; |
409 | |
410 | /* Check for fifo overflow during write */ |
411 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); |
412 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); |
413 | |
414 | if (fifo_outstanding_cmds) { |
415 | while (fifo_retry_count) { |
416 | usleep_range(min: 500, max: 510); |
417 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); |
418 | fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); |
419 | fifo_retry_count--; |
420 | if (fifo_outstanding_cmds == 0) |
421 | return true; |
422 | } |
423 | } else { |
424 | return true; |
425 | } |
426 | |
427 | |
428 | return false; |
429 | } |
430 | |
431 | static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, |
432 | u8 dev_addr, u16 reg_addr) |
433 | { |
434 | |
435 | u32 val; |
436 | int ret = 0; |
437 | u8 cmd_id = 0x0; |
438 | |
439 | if (dev_addr == SDW_BROADCAST_DEV_NUM) { |
440 | cmd_id = SWR_BROADCAST_CMD_ID; |
441 | val = swrm_get_packed_reg_val(cmd_id: &cmd_id, cmd_data, |
442 | dev_addr, reg_addr); |
443 | } else { |
444 | val = swrm_get_packed_reg_val(cmd_id: &ctrl->wcmd_id, cmd_data, |
445 | dev_addr, reg_addr); |
446 | } |
447 | |
448 | if (swrm_wait_for_wr_fifo_avail(ctrl)) |
449 | return SDW_CMD_FAIL_OTHER; |
450 | |
451 | if (cmd_id == SWR_BROADCAST_CMD_ID) |
452 | reinit_completion(x: &ctrl->broadcast); |
453 | |
454 | /* Its assumed that write is okay as we do not get any status back */ |
455 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); |
456 | |
457 | if (ctrl->version <= SWRM_VERSION_1_3_0) |
458 | usleep_range(min: 150, max: 155); |
459 | |
460 | if (cmd_id == SWR_BROADCAST_CMD_ID) { |
461 | swrm_wait_for_wr_fifo_done(ctrl); |
462 | /* |
463 | * sleep for 10ms for MSM soundwire variant to allow broadcast |
464 | * command to complete. |
465 | */ |
466 | ret = wait_for_completion_timeout(x: &ctrl->broadcast, |
467 | timeout: msecs_to_jiffies(TIMEOUT_MS)); |
468 | if (!ret) |
469 | ret = SDW_CMD_IGNORED; |
470 | else |
471 | ret = SDW_CMD_OK; |
472 | |
473 | } else { |
474 | ret = SDW_CMD_OK; |
475 | } |
476 | return ret; |
477 | } |
478 | |
479 | static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, |
480 | u8 dev_addr, u16 reg_addr, |
481 | u32 len, u8 *rval) |
482 | { |
483 | u32 cmd_data, cmd_id, val, retry_attempt = 0; |
484 | |
485 | val = swrm_get_packed_reg_val(cmd_id: &ctrl->rcmd_id, cmd_data: len, dev_addr, reg_addr); |
486 | |
487 | /* |
488 | * Check for outstanding cmd wrt. write fifo depth to avoid |
489 | * overflow as read will also increase write fifo cnt. |
490 | */ |
491 | swrm_wait_for_wr_fifo_avail(ctrl); |
492 | |
493 | /* wait for FIFO RD to complete to avoid overflow */ |
494 | usleep_range(min: 100, max: 105); |
495 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); |
496 | /* wait for FIFO RD CMD complete to avoid overflow */ |
497 | usleep_range(min: 250, max: 255); |
498 | |
499 | if (swrm_wait_for_rd_fifo_avail(ctrl)) |
500 | return SDW_CMD_FAIL_OTHER; |
501 | |
502 | do { |
503 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], |
504 | &cmd_data); |
505 | rval[0] = cmd_data & 0xFF; |
506 | cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); |
507 | |
508 | if (cmd_id != ctrl->rcmd_id) { |
509 | if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { |
510 | /* wait 500 us before retry on fifo read failure */ |
511 | usleep_range(min: 500, max: 505); |
512 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, |
513 | SWRM_CMD_FIFO_FLUSH); |
514 | ctrl->reg_write(ctrl, |
515 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], |
516 | val); |
517 | } |
518 | retry_attempt++; |
519 | } else { |
520 | return SDW_CMD_OK; |
521 | } |
522 | |
523 | } while (retry_attempt < MAX_FIFO_RD_RETRY); |
524 | |
525 | dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ |
526 | dev_num: 0x%x, cmd_data: 0x%x\n" , |
527 | reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); |
528 | |
529 | return SDW_CMD_IGNORED; |
530 | } |
531 | |
532 | static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) |
533 | { |
534 | u32 val, status; |
535 | int dev_num; |
536 | |
537 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); |
538 | |
539 | for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { |
540 | status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); |
541 | |
542 | if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { |
543 | ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; |
544 | return dev_num; |
545 | } |
546 | } |
547 | |
548 | return -EINVAL; |
549 | } |
550 | |
551 | static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) |
552 | { |
553 | u32 val; |
554 | int i; |
555 | |
556 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); |
557 | ctrl->slave_status = val; |
558 | |
559 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { |
560 | u32 s; |
561 | |
562 | s = (val >> (i * 2)); |
563 | s &= SWRM_MCP_SLV_STATUS_MASK; |
564 | ctrl->status[i] = s; |
565 | } |
566 | } |
567 | |
568 | static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, |
569 | struct sdw_slave *slave, int devnum) |
570 | { |
571 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
572 | u32 status; |
573 | |
574 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); |
575 | status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); |
576 | status &= SWRM_MCP_SLV_STATUS_MASK; |
577 | |
578 | if (status == SDW_SLAVE_ATTACHED) { |
579 | if (slave) |
580 | slave->dev_num = devnum; |
581 | mutex_lock(&bus->bus_lock); |
582 | set_bit(nr: devnum, addr: bus->assigned); |
583 | mutex_unlock(lock: &bus->bus_lock); |
584 | } |
585 | } |
586 | |
587 | static int qcom_swrm_enumerate(struct sdw_bus *bus) |
588 | { |
589 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
590 | struct sdw_slave *slave, *_s; |
591 | struct sdw_slave_id id; |
592 | u32 val1, val2; |
593 | bool found; |
594 | u64 addr; |
595 | int i; |
596 | char *buf1 = (char *)&val1, *buf2 = (char *)&val2; |
597 | |
598 | for (i = 1; i <= SDW_MAX_DEVICES; i++) { |
599 | /* do not continue if the status is Not Present */ |
600 | if (!ctrl->status[i]) |
601 | continue; |
602 | |
603 | /*SCP_Devid5 - Devid 4*/ |
604 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); |
605 | |
606 | /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ |
607 | ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); |
608 | |
609 | if (!val1 && !val2) |
610 | break; |
611 | |
612 | addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | |
613 | ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | |
614 | ((u64)buf1[0] << 40); |
615 | |
616 | sdw_extract_slave_id(bus, addr, id: &id); |
617 | found = false; |
618 | ctrl->clock_stop_not_supported = false; |
619 | /* Now compare with entries */ |
620 | list_for_each_entry_safe(slave, _s, &bus->slaves, node) { |
621 | if (sdw_compare_devid(slave, id) == 0) { |
622 | qcom_swrm_set_slave_dev_num(bus, slave, devnum: i); |
623 | if (slave->prop.clk_stop_mode1) |
624 | ctrl->clock_stop_not_supported = true; |
625 | |
626 | found = true; |
627 | break; |
628 | } |
629 | } |
630 | |
631 | if (!found) { |
632 | qcom_swrm_set_slave_dev_num(bus, NULL, devnum: i); |
633 | sdw_slave_add(bus, id: &id, NULL); |
634 | } |
635 | } |
636 | |
637 | complete(&ctrl->enumeration); |
638 | return 0; |
639 | } |
640 | |
641 | static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) |
642 | { |
643 | struct qcom_swrm_ctrl *ctrl = dev_id; |
644 | int ret; |
645 | |
646 | ret = pm_runtime_get_sync(dev: ctrl->dev); |
647 | if (ret < 0 && ret != -EACCES) { |
648 | dev_err_ratelimited(ctrl->dev, |
649 | "pm_runtime_get_sync failed in %s, ret %d\n" , |
650 | __func__, ret); |
651 | pm_runtime_put_noidle(dev: ctrl->dev); |
652 | return ret; |
653 | } |
654 | |
655 | if (ctrl->wake_irq > 0) { |
656 | if (!irqd_irq_disabled(d: irq_get_irq_data(irq: ctrl->wake_irq))) |
657 | disable_irq_nosync(irq: ctrl->wake_irq); |
658 | } |
659 | |
660 | pm_runtime_mark_last_busy(dev: ctrl->dev); |
661 | pm_runtime_put_autosuspend(dev: ctrl->dev); |
662 | |
663 | return IRQ_HANDLED; |
664 | } |
665 | |
666 | static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) |
667 | { |
668 | struct qcom_swrm_ctrl *ctrl = dev_id; |
669 | u32 value, intr_sts, intr_sts_masked, slave_status; |
670 | u32 i; |
671 | int devnum; |
672 | int ret = IRQ_HANDLED; |
673 | clk_prepare_enable(clk: ctrl->hclk); |
674 | |
675 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], |
676 | &intr_sts); |
677 | intr_sts_masked = intr_sts & ctrl->intr_mask; |
678 | |
679 | do { |
680 | for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { |
681 | value = intr_sts_masked & BIT(i); |
682 | if (!value) |
683 | continue; |
684 | |
685 | switch (value) { |
686 | case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: |
687 | devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); |
688 | if (devnum < 0) { |
689 | dev_err_ratelimited(ctrl->dev, |
690 | "no slave alert found.spurious interrupt\n" ); |
691 | } else { |
692 | sdw_handle_slave_status(bus: &ctrl->bus, status: ctrl->status); |
693 | } |
694 | |
695 | break; |
696 | case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: |
697 | case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: |
698 | dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n" ); |
699 | ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); |
700 | if (ctrl->slave_status == slave_status) { |
701 | dev_dbg(ctrl->dev, "Slave status not changed %x\n" , |
702 | slave_status); |
703 | } else { |
704 | qcom_swrm_get_device_status(ctrl); |
705 | qcom_swrm_enumerate(bus: &ctrl->bus); |
706 | sdw_handle_slave_status(bus: &ctrl->bus, status: ctrl->status); |
707 | } |
708 | break; |
709 | case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: |
710 | dev_err_ratelimited(ctrl->dev, |
711 | "%s: SWR bus clsh detected\n" , |
712 | __func__); |
713 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; |
714 | ctrl->reg_write(ctrl, |
715 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
716 | ctrl->intr_mask); |
717 | break; |
718 | case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: |
719 | ctrl->reg_read(ctrl, |
720 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
721 | &value); |
722 | dev_err_ratelimited(ctrl->dev, |
723 | "%s: SWR read FIFO overflow fifo status 0x%x\n" , |
724 | __func__, value); |
725 | break; |
726 | case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: |
727 | ctrl->reg_read(ctrl, |
728 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
729 | &value); |
730 | dev_err_ratelimited(ctrl->dev, |
731 | "%s: SWR read FIFO underflow fifo status 0x%x\n" , |
732 | __func__, value); |
733 | break; |
734 | case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: |
735 | ctrl->reg_read(ctrl, |
736 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
737 | &value); |
738 | dev_err(ctrl->dev, |
739 | "%s: SWR write FIFO overflow fifo status %x\n" , |
740 | __func__, value); |
741 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); |
742 | break; |
743 | case SWRM_INTERRUPT_STATUS_CMD_ERROR: |
744 | ctrl->reg_read(ctrl, |
745 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
746 | &value); |
747 | dev_err_ratelimited(ctrl->dev, |
748 | "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n" , |
749 | __func__, value); |
750 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); |
751 | break; |
752 | case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: |
753 | dev_err_ratelimited(ctrl->dev, |
754 | "%s: SWR Port collision detected\n" , |
755 | __func__); |
756 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; |
757 | ctrl->reg_write(ctrl, |
758 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
759 | ctrl->intr_mask); |
760 | break; |
761 | case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: |
762 | dev_err_ratelimited(ctrl->dev, |
763 | "%s: SWR read enable valid mismatch\n" , |
764 | __func__); |
765 | ctrl->intr_mask &= |
766 | ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; |
767 | ctrl->reg_write(ctrl, |
768 | ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
769 | ctrl->intr_mask); |
770 | break; |
771 | case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: |
772 | complete(&ctrl->broadcast); |
773 | break; |
774 | case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: |
775 | break; |
776 | case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: |
777 | break; |
778 | case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: |
779 | break; |
780 | case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED: |
781 | ctrl->reg_read(ctrl, |
782 | ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], |
783 | &value); |
784 | dev_err(ctrl->dev, |
785 | "%s: SWR CMD ignored, fifo status %x\n" , |
786 | __func__, value); |
787 | |
788 | /* Wait 3.5ms to clear */ |
789 | usleep_range(min: 3500, max: 3505); |
790 | break; |
791 | default: |
792 | dev_err_ratelimited(ctrl->dev, |
793 | "%s: SWR unknown interrupt value: %d\n" , |
794 | __func__, value); |
795 | ret = IRQ_NONE; |
796 | break; |
797 | } |
798 | } |
799 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], |
800 | intr_sts); |
801 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], |
802 | &intr_sts); |
803 | intr_sts_masked = intr_sts & ctrl->intr_mask; |
804 | } while (intr_sts_masked); |
805 | |
806 | clk_disable_unprepare(clk: ctrl->hclk); |
807 | return ret; |
808 | } |
809 | |
810 | static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) |
811 | { |
812 | int retry = SWRM_LINK_STATUS_RETRY_CNT; |
813 | int comp_sts; |
814 | |
815 | do { |
816 | ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], |
817 | &comp_sts); |
818 | if (comp_sts & SWRM_FRM_GEN_ENABLED) |
819 | return true; |
820 | |
821 | usleep_range(min: 500, max: 510); |
822 | } while (retry--); |
823 | |
824 | dev_err(ctrl->dev, "%s: link status not %s\n" , __func__, |
825 | comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected" ); |
826 | |
827 | return false; |
828 | } |
829 | |
830 | static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) |
831 | { |
832 | u32 val; |
833 | |
834 | /* Clear Rows and Cols */ |
835 | val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); |
836 | val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); |
837 | |
838 | reset_control_reset(rstc: ctrl->audio_cgcr); |
839 | |
840 | ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); |
841 | |
842 | /* Enable Auto enumeration */ |
843 | ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); |
844 | |
845 | ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; |
846 | /* Mask soundwire interrupts */ |
847 | if (ctrl->version < SWRM_VERSION_2_0_0) |
848 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], |
849 | SWRM_INTERRUPT_STATUS_RMSK); |
850 | |
851 | /* Configure No pings */ |
852 | ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); |
853 | u32p_replace_bits(p: &val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); |
854 | ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); |
855 | |
856 | if (ctrl->version == SWRM_VERSION_1_7_0) { |
857 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
858 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, |
859 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); |
860 | } else if (ctrl->version >= SWRM_VERSION_2_0_0) { |
861 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
862 | ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, |
863 | SWRM_V2_0_CLK_CTRL_CLK_START); |
864 | } else { |
865 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); |
866 | } |
867 | |
868 | /* Configure number of retries of a read/write cmd */ |
869 | if (ctrl->version >= SWRM_VERSION_1_5_1) { |
870 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, |
871 | SWRM_RD_WR_CMD_RETRIES | |
872 | SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); |
873 | } else { |
874 | ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, |
875 | SWRM_RD_WR_CMD_RETRIES); |
876 | } |
877 | |
878 | /* COMP Enable */ |
879 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); |
880 | |
881 | /* Set IRQ to PULSE */ |
882 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, |
883 | SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK); |
884 | |
885 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], |
886 | 0xFFFFFFFF); |
887 | |
888 | /* enable CPU IRQs */ |
889 | if (ctrl->mmio) { |
890 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
891 | SWRM_INTERRUPT_STATUS_RMSK); |
892 | } |
893 | |
894 | /* Set IRQ to PULSE */ |
895 | ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, |
896 | SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | |
897 | SWRM_COMP_CFG_ENABLE_MSK); |
898 | |
899 | swrm_wait_for_frame_gen_enabled(ctrl); |
900 | ctrl->slave_status = 0; |
901 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); |
902 | ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); |
903 | ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); |
904 | |
905 | return 0; |
906 | } |
907 | |
908 | static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, |
909 | struct sdw_msg *msg) |
910 | { |
911 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
912 | int ret, i, len; |
913 | |
914 | if (msg->flags == SDW_MSG_FLAG_READ) { |
915 | for (i = 0; i < msg->len;) { |
916 | if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) |
917 | len = msg->len - i; |
918 | else |
919 | len = QCOM_SWRM_MAX_RD_LEN; |
920 | |
921 | ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, dev_addr: msg->dev_num, |
922 | reg_addr: msg->addr + i, len, |
923 | rval: &msg->buf[i]); |
924 | if (ret) |
925 | return ret; |
926 | |
927 | i = i + len; |
928 | } |
929 | } else if (msg->flags == SDW_MSG_FLAG_WRITE) { |
930 | for (i = 0; i < msg->len; i++) { |
931 | ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, cmd_data: msg->buf[i], |
932 | dev_addr: msg->dev_num, |
933 | reg_addr: msg->addr + i); |
934 | if (ret) |
935 | return SDW_CMD_IGNORED; |
936 | } |
937 | } |
938 | |
939 | return SDW_CMD_OK; |
940 | } |
941 | |
942 | static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) |
943 | { |
944 | u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); |
945 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
946 | u32 val; |
947 | |
948 | ctrl->reg_read(ctrl, reg, &val); |
949 | |
950 | u32p_replace_bits(p: &val, val: ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); |
951 | u32p_replace_bits(p: &val, val: ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); |
952 | |
953 | return ctrl->reg_write(ctrl, reg, val); |
954 | } |
955 | |
956 | static int qcom_swrm_port_params(struct sdw_bus *bus, |
957 | struct sdw_port_params *p_params, |
958 | unsigned int bank) |
959 | { |
960 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
961 | |
962 | return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), |
963 | p_params->bps - 1); |
964 | |
965 | } |
966 | |
967 | static int qcom_swrm_transport_params(struct sdw_bus *bus, |
968 | struct sdw_transport_params *params, |
969 | enum sdw_reg_bank bank) |
970 | { |
971 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
972 | struct qcom_swrm_port_config *pcfg; |
973 | u32 value; |
974 | int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); |
975 | int ret; |
976 | |
977 | pcfg = &ctrl->pconfig[params->port_num]; |
978 | |
979 | value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; |
980 | value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; |
981 | value |= pcfg->si & 0xff; |
982 | |
983 | ret = ctrl->reg_write(ctrl, reg, value); |
984 | if (ret) |
985 | goto err; |
986 | |
987 | if (pcfg->si > 0xff) { |
988 | value = (pcfg->si >> 8) & 0xff; |
989 | reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); |
990 | ret = ctrl->reg_write(ctrl, reg, value); |
991 | if (ret) |
992 | goto err; |
993 | } |
994 | |
995 | if (pcfg->lane_control != SWR_INVALID_PARAM) { |
996 | reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); |
997 | value = pcfg->lane_control; |
998 | ret = ctrl->reg_write(ctrl, reg, value); |
999 | if (ret) |
1000 | goto err; |
1001 | } |
1002 | |
1003 | if (pcfg->blk_group_count != SWR_INVALID_PARAM) { |
1004 | reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); |
1005 | value = pcfg->blk_group_count; |
1006 | ret = ctrl->reg_write(ctrl, reg, value); |
1007 | if (ret) |
1008 | goto err; |
1009 | } |
1010 | |
1011 | if (pcfg->hstart != SWR_INVALID_PARAM |
1012 | && pcfg->hstop != SWR_INVALID_PARAM) { |
1013 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); |
1014 | value = (pcfg->hstop << 4) | pcfg->hstart; |
1015 | ret = ctrl->reg_write(ctrl, reg, value); |
1016 | } else { |
1017 | reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); |
1018 | value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; |
1019 | ret = ctrl->reg_write(ctrl, reg, value); |
1020 | } |
1021 | |
1022 | if (ret) |
1023 | goto err; |
1024 | |
1025 | if (pcfg->bp_mode != SWR_INVALID_PARAM) { |
1026 | reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); |
1027 | ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); |
1028 | } |
1029 | |
1030 | err: |
1031 | return ret; |
1032 | } |
1033 | |
1034 | static int qcom_swrm_port_enable(struct sdw_bus *bus, |
1035 | struct sdw_enable_ch *enable_ch, |
1036 | unsigned int bank) |
1037 | { |
1038 | u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); |
1039 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
1040 | u32 val; |
1041 | |
1042 | ctrl->reg_read(ctrl, reg, &val); |
1043 | |
1044 | if (enable_ch->enable) |
1045 | val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); |
1046 | else |
1047 | val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); |
1048 | |
1049 | return ctrl->reg_write(ctrl, reg, val); |
1050 | } |
1051 | |
1052 | static const struct sdw_master_port_ops qcom_swrm_port_ops = { |
1053 | .dpn_set_port_params = qcom_swrm_port_params, |
1054 | .dpn_set_port_transport_params = qcom_swrm_transport_params, |
1055 | .dpn_port_enable_ch = qcom_swrm_port_enable, |
1056 | }; |
1057 | |
1058 | static const struct sdw_master_ops qcom_swrm_ops = { |
1059 | .xfer_msg = qcom_swrm_xfer_msg, |
1060 | .pre_bank_switch = qcom_swrm_pre_bank_switch, |
1061 | }; |
1062 | |
1063 | static int qcom_swrm_compute_params(struct sdw_bus *bus) |
1064 | { |
1065 | struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); |
1066 | struct sdw_master_runtime *m_rt; |
1067 | struct sdw_slave_runtime *s_rt; |
1068 | struct sdw_port_runtime *p_rt; |
1069 | struct qcom_swrm_port_config *pcfg; |
1070 | struct sdw_slave *slave; |
1071 | unsigned int m_port; |
1072 | int i = 1; |
1073 | |
1074 | list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { |
1075 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) { |
1076 | pcfg = &ctrl->pconfig[p_rt->num]; |
1077 | p_rt->transport_params.port_num = p_rt->num; |
1078 | if (pcfg->word_length != SWR_INVALID_PARAM) { |
1079 | sdw_fill_port_params(params: &p_rt->port_params, |
1080 | port_num: p_rt->num, bps: pcfg->word_length + 1, |
1081 | SDW_PORT_FLOW_MODE_ISOCH, |
1082 | data_mode: SDW_PORT_DATA_MODE_NORMAL); |
1083 | } |
1084 | |
1085 | } |
1086 | |
1087 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { |
1088 | slave = s_rt->slave; |
1089 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
1090 | m_port = slave->m_port_map[p_rt->num]; |
1091 | /* port config starts at offset 0 so -1 from actual port number */ |
1092 | if (m_port) |
1093 | pcfg = &ctrl->pconfig[m_port]; |
1094 | else |
1095 | pcfg = &ctrl->pconfig[i]; |
1096 | p_rt->transport_params.port_num = p_rt->num; |
1097 | p_rt->transport_params.sample_interval = |
1098 | pcfg->si + 1; |
1099 | p_rt->transport_params.offset1 = pcfg->off1; |
1100 | p_rt->transport_params.offset2 = pcfg->off2; |
1101 | p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; |
1102 | p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; |
1103 | |
1104 | p_rt->transport_params.hstart = pcfg->hstart; |
1105 | p_rt->transport_params.hstop = pcfg->hstop; |
1106 | p_rt->transport_params.lane_ctrl = pcfg->lane_control; |
1107 | if (pcfg->word_length != SWR_INVALID_PARAM) { |
1108 | sdw_fill_port_params(params: &p_rt->port_params, |
1109 | port_num: p_rt->num, |
1110 | bps: pcfg->word_length + 1, |
1111 | SDW_PORT_FLOW_MODE_ISOCH, |
1112 | data_mode: SDW_PORT_DATA_MODE_NORMAL); |
1113 | } |
1114 | i++; |
1115 | } |
1116 | } |
1117 | } |
1118 | |
1119 | return 0; |
1120 | } |
1121 | |
1122 | static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { |
1123 | DEFAULT_CLK_FREQ, |
1124 | }; |
1125 | |
1126 | static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, |
1127 | struct sdw_stream_runtime *stream) |
1128 | { |
1129 | struct sdw_master_runtime *m_rt; |
1130 | struct sdw_port_runtime *p_rt; |
1131 | unsigned long *port_mask; |
1132 | |
1133 | mutex_lock(&ctrl->port_lock); |
1134 | |
1135 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { |
1136 | if (m_rt->direction == SDW_DATA_DIR_RX) |
1137 | port_mask = &ctrl->dout_port_mask; |
1138 | else |
1139 | port_mask = &ctrl->din_port_mask; |
1140 | |
1141 | list_for_each_entry(p_rt, &m_rt->port_list, port_node) |
1142 | clear_bit(nr: p_rt->num, addr: port_mask); |
1143 | } |
1144 | |
1145 | mutex_unlock(lock: &ctrl->port_lock); |
1146 | } |
1147 | |
1148 | static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, |
1149 | struct sdw_stream_runtime *stream, |
1150 | struct snd_pcm_hw_params *params, |
1151 | int direction) |
1152 | { |
1153 | struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; |
1154 | struct sdw_stream_config sconfig; |
1155 | struct sdw_master_runtime *m_rt; |
1156 | struct sdw_slave_runtime *s_rt; |
1157 | struct sdw_port_runtime *p_rt; |
1158 | struct sdw_slave *slave; |
1159 | unsigned long *port_mask; |
1160 | int maxport, pn, nports = 0, ret = 0; |
1161 | unsigned int m_port; |
1162 | |
1163 | if (direction == SNDRV_PCM_STREAM_CAPTURE) |
1164 | sconfig.direction = SDW_DATA_DIR_TX; |
1165 | else |
1166 | sconfig.direction = SDW_DATA_DIR_RX; |
1167 | |
1168 | /* hw parameters wil be ignored as we only support PDM */ |
1169 | sconfig.ch_count = 1; |
1170 | sconfig.frame_rate = params_rate(p: params); |
1171 | sconfig.type = stream->type; |
1172 | sconfig.bps = 1; |
1173 | |
1174 | mutex_lock(&ctrl->port_lock); |
1175 | list_for_each_entry(m_rt, &stream->master_list, stream_node) { |
1176 | if (m_rt->direction == SDW_DATA_DIR_RX) { |
1177 | maxport = ctrl->num_dout_ports; |
1178 | port_mask = &ctrl->dout_port_mask; |
1179 | } else { |
1180 | maxport = ctrl->num_din_ports; |
1181 | port_mask = &ctrl->din_port_mask; |
1182 | } |
1183 | |
1184 | list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { |
1185 | slave = s_rt->slave; |
1186 | list_for_each_entry(p_rt, &s_rt->port_list, port_node) { |
1187 | m_port = slave->m_port_map[p_rt->num]; |
1188 | /* Port numbers start from 1 - 14*/ |
1189 | if (m_port) |
1190 | pn = m_port; |
1191 | else |
1192 | pn = find_first_zero_bit(addr: port_mask, size: maxport); |
1193 | |
1194 | if (pn > maxport) { |
1195 | dev_err(ctrl->dev, "All ports busy\n" ); |
1196 | ret = -EBUSY; |
1197 | goto out; |
1198 | } |
1199 | set_bit(nr: pn, addr: port_mask); |
1200 | pconfig[nports].num = pn; |
1201 | pconfig[nports].ch_mask = p_rt->ch_mask; |
1202 | nports++; |
1203 | } |
1204 | } |
1205 | } |
1206 | |
1207 | sdw_stream_add_master(bus: &ctrl->bus, stream_config: &sconfig, port_config: pconfig, |
1208 | num_ports: nports, stream); |
1209 | out: |
1210 | mutex_unlock(lock: &ctrl->port_lock); |
1211 | |
1212 | return ret; |
1213 | } |
1214 | |
1215 | static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, |
1216 | struct snd_pcm_hw_params *params, |
1217 | struct snd_soc_dai *dai) |
1218 | { |
1219 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1220 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; |
1221 | int ret; |
1222 | |
1223 | ret = qcom_swrm_stream_alloc_ports(ctrl, stream: sruntime, params, |
1224 | direction: substream->stream); |
1225 | if (ret) |
1226 | qcom_swrm_stream_free_ports(ctrl, stream: sruntime); |
1227 | |
1228 | return ret; |
1229 | } |
1230 | |
1231 | static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, |
1232 | struct snd_soc_dai *dai) |
1233 | { |
1234 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1235 | struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; |
1236 | |
1237 | qcom_swrm_stream_free_ports(ctrl, stream: sruntime); |
1238 | sdw_stream_remove_master(bus: &ctrl->bus, stream: sruntime); |
1239 | |
1240 | return 0; |
1241 | } |
1242 | |
1243 | static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, |
1244 | void *stream, int direction) |
1245 | { |
1246 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1247 | |
1248 | ctrl->sruntime[dai->id] = stream; |
1249 | |
1250 | return 0; |
1251 | } |
1252 | |
1253 | static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) |
1254 | { |
1255 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1256 | |
1257 | return ctrl->sruntime[dai->id]; |
1258 | } |
1259 | |
1260 | static int qcom_swrm_startup(struct snd_pcm_substream *substream, |
1261 | struct snd_soc_dai *dai) |
1262 | { |
1263 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1264 | int ret; |
1265 | |
1266 | ret = pm_runtime_get_sync(dev: ctrl->dev); |
1267 | if (ret < 0 && ret != -EACCES) { |
1268 | dev_err_ratelimited(ctrl->dev, |
1269 | "pm_runtime_get_sync failed in %s, ret %d\n" , |
1270 | __func__, ret); |
1271 | pm_runtime_put_noidle(dev: ctrl->dev); |
1272 | return ret; |
1273 | } |
1274 | |
1275 | return 0; |
1276 | } |
1277 | |
1278 | static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, |
1279 | struct snd_soc_dai *dai) |
1280 | { |
1281 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: dai->dev); |
1282 | |
1283 | swrm_wait_for_wr_fifo_done(ctrl); |
1284 | pm_runtime_mark_last_busy(dev: ctrl->dev); |
1285 | pm_runtime_put_autosuspend(dev: ctrl->dev); |
1286 | |
1287 | } |
1288 | |
1289 | static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { |
1290 | .hw_params = qcom_swrm_hw_params, |
1291 | .hw_free = qcom_swrm_hw_free, |
1292 | .startup = qcom_swrm_startup, |
1293 | .shutdown = qcom_swrm_shutdown, |
1294 | .set_stream = qcom_swrm_set_sdw_stream, |
1295 | .get_stream = qcom_swrm_get_sdw_stream, |
1296 | }; |
1297 | |
1298 | static const struct snd_soc_component_driver qcom_swrm_dai_component = { |
1299 | .name = "soundwire" , |
1300 | }; |
1301 | |
1302 | static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) |
1303 | { |
1304 | int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; |
1305 | struct snd_soc_dai_driver *dais; |
1306 | struct snd_soc_pcm_stream *stream; |
1307 | struct device *dev = ctrl->dev; |
1308 | int i; |
1309 | |
1310 | /* PDM dais are only tested for now */ |
1311 | dais = devm_kcalloc(dev, n: num_dais, size: sizeof(*dais), GFP_KERNEL); |
1312 | if (!dais) |
1313 | return -ENOMEM; |
1314 | |
1315 | for (i = 0; i < num_dais; i++) { |
1316 | dais[i].name = devm_kasprintf(dev, GFP_KERNEL, fmt: "SDW Pin%d" , i); |
1317 | if (!dais[i].name) |
1318 | return -ENOMEM; |
1319 | |
1320 | if (i < ctrl->num_dout_ports) |
1321 | stream = &dais[i].playback; |
1322 | else |
1323 | stream = &dais[i].capture; |
1324 | |
1325 | stream->channels_min = 1; |
1326 | stream->channels_max = 1; |
1327 | stream->rates = SNDRV_PCM_RATE_48000; |
1328 | stream->formats = SNDRV_PCM_FMTBIT_S16_LE; |
1329 | |
1330 | dais[i].ops = &qcom_swrm_pdm_dai_ops; |
1331 | dais[i].id = i; |
1332 | } |
1333 | |
1334 | return devm_snd_soc_register_component(dev: ctrl->dev, |
1335 | component_driver: &qcom_swrm_dai_component, |
1336 | dai_drv: dais, num_dai: num_dais); |
1337 | } |
1338 | |
1339 | static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) |
1340 | { |
1341 | struct device_node *np = ctrl->dev->of_node; |
1342 | u8 off1[QCOM_SDW_MAX_PORTS]; |
1343 | u8 off2[QCOM_SDW_MAX_PORTS]; |
1344 | u16 si[QCOM_SDW_MAX_PORTS]; |
1345 | u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; |
1346 | u8 hstart[QCOM_SDW_MAX_PORTS]; |
1347 | u8 hstop[QCOM_SDW_MAX_PORTS]; |
1348 | u8 word_length[QCOM_SDW_MAX_PORTS]; |
1349 | u8 blk_group_count[QCOM_SDW_MAX_PORTS]; |
1350 | u8 lane_control[QCOM_SDW_MAX_PORTS]; |
1351 | int i, ret, nports, val; |
1352 | bool si_16 = false; |
1353 | |
1354 | ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); |
1355 | |
1356 | ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); |
1357 | ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); |
1358 | |
1359 | ret = of_property_read_u32(np, propname: "qcom,din-ports" , out_value: &val); |
1360 | if (ret) |
1361 | return ret; |
1362 | |
1363 | if (val > ctrl->num_din_ports) |
1364 | return -EINVAL; |
1365 | |
1366 | ctrl->num_din_ports = val; |
1367 | |
1368 | ret = of_property_read_u32(np, propname: "qcom,dout-ports" , out_value: &val); |
1369 | if (ret) |
1370 | return ret; |
1371 | |
1372 | if (val > ctrl->num_dout_ports) |
1373 | return -EINVAL; |
1374 | |
1375 | ctrl->num_dout_ports = val; |
1376 | |
1377 | nports = ctrl->num_dout_ports + ctrl->num_din_ports; |
1378 | if (nports > QCOM_SDW_MAX_PORTS) |
1379 | return -EINVAL; |
1380 | |
1381 | /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ |
1382 | set_bit(nr: 0, addr: &ctrl->dout_port_mask); |
1383 | set_bit(nr: 0, addr: &ctrl->din_port_mask); |
1384 | |
1385 | ret = of_property_read_u8_array(np, propname: "qcom,ports-offset1" , |
1386 | out_values: off1, sz: nports); |
1387 | if (ret) |
1388 | return ret; |
1389 | |
1390 | ret = of_property_read_u8_array(np, propname: "qcom,ports-offset2" , |
1391 | out_values: off2, sz: nports); |
1392 | if (ret) |
1393 | return ret; |
1394 | |
1395 | ret = of_property_read_u8_array(np, propname: "qcom,ports-sinterval-low" , |
1396 | out_values: (u8 *)si, sz: nports); |
1397 | if (ret) { |
1398 | ret = of_property_read_u16_array(np, propname: "qcom,ports-sinterval" , |
1399 | out_values: si, sz: nports); |
1400 | if (ret) |
1401 | return ret; |
1402 | si_16 = true; |
1403 | } |
1404 | |
1405 | ret = of_property_read_u8_array(np, propname: "qcom,ports-block-pack-mode" , |
1406 | out_values: bp_mode, sz: nports); |
1407 | if (ret) { |
1408 | if (ctrl->version <= SWRM_VERSION_1_3_0) |
1409 | memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1410 | else |
1411 | return ret; |
1412 | } |
1413 | |
1414 | memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1415 | of_property_read_u8_array(np, propname: "qcom,ports-hstart" , out_values: hstart, sz: nports); |
1416 | |
1417 | memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1418 | of_property_read_u8_array(np, propname: "qcom,ports-hstop" , out_values: hstop, sz: nports); |
1419 | |
1420 | memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1421 | of_property_read_u8_array(np, propname: "qcom,ports-word-length" , out_values: word_length, sz: nports); |
1422 | |
1423 | memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1424 | of_property_read_u8_array(np, propname: "qcom,ports-block-group-count" , out_values: blk_group_count, sz: nports); |
1425 | |
1426 | memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); |
1427 | of_property_read_u8_array(np, propname: "qcom,ports-lane-control" , out_values: lane_control, sz: nports); |
1428 | |
1429 | for (i = 0; i < nports; i++) { |
1430 | /* Valid port number range is from 1-14 */ |
1431 | if (si_16) |
1432 | ctrl->pconfig[i + 1].si = si[i]; |
1433 | else |
1434 | ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; |
1435 | ctrl->pconfig[i + 1].off1 = off1[i]; |
1436 | ctrl->pconfig[i + 1].off2 = off2[i]; |
1437 | ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; |
1438 | ctrl->pconfig[i + 1].hstart = hstart[i]; |
1439 | ctrl->pconfig[i + 1].hstop = hstop[i]; |
1440 | ctrl->pconfig[i + 1].word_length = word_length[i]; |
1441 | ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; |
1442 | ctrl->pconfig[i + 1].lane_control = lane_control[i]; |
1443 | } |
1444 | |
1445 | return 0; |
1446 | } |
1447 | |
1448 | #ifdef CONFIG_DEBUG_FS |
1449 | static int swrm_reg_show(struct seq_file *s_file, void *data) |
1450 | { |
1451 | struct qcom_swrm_ctrl *ctrl = s_file->private; |
1452 | int reg, reg_val, ret; |
1453 | |
1454 | ret = pm_runtime_get_sync(dev: ctrl->dev); |
1455 | if (ret < 0 && ret != -EACCES) { |
1456 | dev_err_ratelimited(ctrl->dev, |
1457 | "pm_runtime_get_sync failed in %s, ret %d\n" , |
1458 | __func__, ret); |
1459 | pm_runtime_put_noidle(dev: ctrl->dev); |
1460 | return ret; |
1461 | } |
1462 | |
1463 | for (reg = 0; reg <= ctrl->max_reg; reg += 4) { |
1464 | ctrl->reg_read(ctrl, reg, ®_val); |
1465 | seq_printf(m: s_file, fmt: "0x%.3x: 0x%.2x\n" , reg, reg_val); |
1466 | } |
1467 | pm_runtime_mark_last_busy(dev: ctrl->dev); |
1468 | pm_runtime_put_autosuspend(dev: ctrl->dev); |
1469 | |
1470 | |
1471 | return 0; |
1472 | } |
1473 | DEFINE_SHOW_ATTRIBUTE(swrm_reg); |
1474 | #endif |
1475 | |
1476 | static int qcom_swrm_probe(struct platform_device *pdev) |
1477 | { |
1478 | struct device *dev = &pdev->dev; |
1479 | struct sdw_master_prop *prop; |
1480 | struct sdw_bus_params *params; |
1481 | struct qcom_swrm_ctrl *ctrl; |
1482 | const struct qcom_swrm_data *data; |
1483 | int ret; |
1484 | u32 val; |
1485 | |
1486 | ctrl = devm_kzalloc(dev, size: sizeof(*ctrl), GFP_KERNEL); |
1487 | if (!ctrl) |
1488 | return -ENOMEM; |
1489 | |
1490 | data = of_device_get_match_data(dev); |
1491 | ctrl->max_reg = data->max_reg; |
1492 | ctrl->reg_layout = data->reg_layout; |
1493 | ctrl->rows_index = sdw_find_row_index(row: data->default_rows); |
1494 | ctrl->cols_index = sdw_find_col_index(col: data->default_cols); |
1495 | #if IS_REACHABLE(CONFIG_SLIMBUS) |
1496 | if (dev->parent->bus == &slimbus_bus) { |
1497 | #else |
1498 | if (false) { |
1499 | #endif |
1500 | ctrl->reg_read = qcom_swrm_ahb_reg_read; |
1501 | ctrl->reg_write = qcom_swrm_ahb_reg_write; |
1502 | ctrl->regmap = dev_get_regmap(dev: dev->parent, NULL); |
1503 | if (!ctrl->regmap) |
1504 | return -EINVAL; |
1505 | } else { |
1506 | ctrl->reg_read = qcom_swrm_cpu_reg_read; |
1507 | ctrl->reg_write = qcom_swrm_cpu_reg_write; |
1508 | ctrl->mmio = devm_platform_ioremap_resource(pdev, index: 0); |
1509 | if (IS_ERR(ptr: ctrl->mmio)) |
1510 | return PTR_ERR(ptr: ctrl->mmio); |
1511 | } |
1512 | |
1513 | if (data->sw_clk_gate_required) { |
1514 | ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, id: "swr_audio_cgcr" ); |
1515 | if (IS_ERR(ptr: ctrl->audio_cgcr)) { |
1516 | dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n" ); |
1517 | ret = PTR_ERR(ptr: ctrl->audio_cgcr); |
1518 | goto err_init; |
1519 | } |
1520 | } |
1521 | |
1522 | ctrl->irq = of_irq_get(dev: dev->of_node, index: 0); |
1523 | if (ctrl->irq < 0) { |
1524 | ret = ctrl->irq; |
1525 | goto err_init; |
1526 | } |
1527 | |
1528 | ctrl->hclk = devm_clk_get(dev, id: "iface" ); |
1529 | if (IS_ERR(ptr: ctrl->hclk)) { |
1530 | ret = dev_err_probe(dev, err: PTR_ERR(ptr: ctrl->hclk), fmt: "unable to get iface clock\n" ); |
1531 | goto err_init; |
1532 | } |
1533 | |
1534 | clk_prepare_enable(clk: ctrl->hclk); |
1535 | |
1536 | ctrl->dev = dev; |
1537 | dev_set_drvdata(dev: &pdev->dev, data: ctrl); |
1538 | mutex_init(&ctrl->port_lock); |
1539 | init_completion(x: &ctrl->broadcast); |
1540 | init_completion(x: &ctrl->enumeration); |
1541 | |
1542 | ctrl->bus.ops = &qcom_swrm_ops; |
1543 | ctrl->bus.port_ops = &qcom_swrm_port_ops; |
1544 | ctrl->bus.compute_params = &qcom_swrm_compute_params; |
1545 | ctrl->bus.clk_stop_timeout = 300; |
1546 | |
1547 | ret = qcom_swrm_get_port_config(ctrl); |
1548 | if (ret) |
1549 | goto err_clk; |
1550 | |
1551 | params = &ctrl->bus.params; |
1552 | params->max_dr_freq = DEFAULT_CLK_FREQ; |
1553 | params->curr_dr_freq = DEFAULT_CLK_FREQ; |
1554 | params->col = data->default_cols; |
1555 | params->row = data->default_rows; |
1556 | ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); |
1557 | params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; |
1558 | params->next_bank = !params->curr_bank; |
1559 | |
1560 | prop = &ctrl->bus.prop; |
1561 | prop->max_clk_freq = DEFAULT_CLK_FREQ; |
1562 | prop->num_clk_gears = 0; |
1563 | prop->num_clk_freq = MAX_FREQ_NUM; |
1564 | prop->clk_freq = &qcom_swrm_freq_tbl[0]; |
1565 | prop->default_col = data->default_cols; |
1566 | prop->default_row = data->default_rows; |
1567 | |
1568 | ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); |
1569 | |
1570 | ret = devm_request_threaded_irq(dev, irq: ctrl->irq, NULL, |
1571 | thread_fn: qcom_swrm_irq_handler, |
1572 | IRQF_TRIGGER_RISING | |
1573 | IRQF_ONESHOT, |
1574 | devname: "soundwire" , dev_id: ctrl); |
1575 | if (ret) { |
1576 | dev_err(dev, "Failed to request soundwire irq\n" ); |
1577 | goto err_clk; |
1578 | } |
1579 | |
1580 | ctrl->wake_irq = of_irq_get(dev: dev->of_node, index: 1); |
1581 | if (ctrl->wake_irq > 0) { |
1582 | ret = devm_request_threaded_irq(dev, irq: ctrl->wake_irq, NULL, |
1583 | thread_fn: qcom_swrm_wake_irq_handler, |
1584 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
1585 | devname: "swr_wake_irq" , dev_id: ctrl); |
1586 | if (ret) { |
1587 | dev_err(dev, "Failed to request soundwire wake irq\n" ); |
1588 | goto err_init; |
1589 | } |
1590 | } |
1591 | |
1592 | ctrl->bus.controller_id = -1; |
1593 | |
1594 | if (ctrl->version > SWRM_VERSION_1_3_0) { |
1595 | ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); |
1596 | ctrl->bus.controller_id = val; |
1597 | } |
1598 | |
1599 | ret = sdw_bus_master_add(bus: &ctrl->bus, parent: dev, fwnode: dev->fwnode); |
1600 | if (ret) { |
1601 | dev_err(dev, "Failed to register Soundwire controller (%d)\n" , |
1602 | ret); |
1603 | goto err_clk; |
1604 | } |
1605 | |
1606 | qcom_swrm_init(ctrl); |
1607 | wait_for_completion_timeout(x: &ctrl->enumeration, |
1608 | timeout: msecs_to_jiffies(TIMEOUT_MS)); |
1609 | ret = qcom_swrm_register_dais(ctrl); |
1610 | if (ret) |
1611 | goto err_master_add; |
1612 | |
1613 | dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n" , |
1614 | (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, |
1615 | ctrl->version & 0xffff); |
1616 | |
1617 | pm_runtime_set_autosuspend_delay(dev, delay: 3000); |
1618 | pm_runtime_use_autosuspend(dev); |
1619 | pm_runtime_mark_last_busy(dev); |
1620 | pm_runtime_set_active(dev); |
1621 | pm_runtime_enable(dev); |
1622 | |
1623 | #ifdef CONFIG_DEBUG_FS |
1624 | ctrl->debugfs = debugfs_create_dir(name: "qualcomm-sdw" , parent: ctrl->bus.debugfs); |
1625 | debugfs_create_file(name: "qualcomm-registers" , mode: 0400, parent: ctrl->debugfs, data: ctrl, |
1626 | fops: &swrm_reg_fops); |
1627 | #endif |
1628 | |
1629 | return 0; |
1630 | |
1631 | err_master_add: |
1632 | sdw_bus_master_delete(bus: &ctrl->bus); |
1633 | err_clk: |
1634 | clk_disable_unprepare(clk: ctrl->hclk); |
1635 | err_init: |
1636 | return ret; |
1637 | } |
1638 | |
1639 | static int qcom_swrm_remove(struct platform_device *pdev) |
1640 | { |
1641 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev: &pdev->dev); |
1642 | |
1643 | sdw_bus_master_delete(bus: &ctrl->bus); |
1644 | clk_disable_unprepare(clk: ctrl->hclk); |
1645 | |
1646 | return 0; |
1647 | } |
1648 | |
1649 | static int __maybe_unused swrm_runtime_resume(struct device *dev) |
1650 | { |
1651 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); |
1652 | int ret; |
1653 | |
1654 | if (ctrl->wake_irq > 0) { |
1655 | if (!irqd_irq_disabled(d: irq_get_irq_data(irq: ctrl->wake_irq))) |
1656 | disable_irq_nosync(irq: ctrl->wake_irq); |
1657 | } |
1658 | |
1659 | clk_prepare_enable(clk: ctrl->hclk); |
1660 | |
1661 | if (ctrl->clock_stop_not_supported) { |
1662 | reinit_completion(x: &ctrl->enumeration); |
1663 | ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); |
1664 | usleep_range(min: 100, max: 105); |
1665 | |
1666 | qcom_swrm_init(ctrl); |
1667 | |
1668 | usleep_range(min: 100, max: 105); |
1669 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) |
1670 | dev_err(ctrl->dev, "link failed to connect\n" ); |
1671 | |
1672 | /* wait for hw enumeration to complete */ |
1673 | wait_for_completion_timeout(x: &ctrl->enumeration, |
1674 | timeout: msecs_to_jiffies(TIMEOUT_MS)); |
1675 | qcom_swrm_get_device_status(ctrl); |
1676 | sdw_handle_slave_status(bus: &ctrl->bus, status: ctrl->status); |
1677 | } else { |
1678 | reset_control_reset(rstc: ctrl->audio_cgcr); |
1679 | |
1680 | if (ctrl->version == SWRM_VERSION_1_7_0) { |
1681 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
1682 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, |
1683 | SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); |
1684 | } else if (ctrl->version >= SWRM_VERSION_2_0_0) { |
1685 | ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); |
1686 | ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, |
1687 | SWRM_V2_0_CLK_CTRL_CLK_START); |
1688 | } else { |
1689 | ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); |
1690 | } |
1691 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], |
1692 | SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); |
1693 | |
1694 | ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; |
1695 | if (ctrl->version < SWRM_VERSION_2_0_0) |
1696 | ctrl->reg_write(ctrl, |
1697 | ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], |
1698 | ctrl->intr_mask); |
1699 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
1700 | ctrl->intr_mask); |
1701 | |
1702 | usleep_range(min: 100, max: 105); |
1703 | if (!swrm_wait_for_frame_gen_enabled(ctrl)) |
1704 | dev_err(ctrl->dev, "link failed to connect\n" ); |
1705 | |
1706 | ret = sdw_bus_exit_clk_stop(bus: &ctrl->bus); |
1707 | if (ret < 0) |
1708 | dev_err(ctrl->dev, "bus failed to exit clock stop %d\n" , ret); |
1709 | } |
1710 | |
1711 | return 0; |
1712 | } |
1713 | |
1714 | static int __maybe_unused swrm_runtime_suspend(struct device *dev) |
1715 | { |
1716 | struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); |
1717 | int ret; |
1718 | |
1719 | swrm_wait_for_wr_fifo_done(ctrl); |
1720 | if (!ctrl->clock_stop_not_supported) { |
1721 | /* Mask bus clash interrupt */ |
1722 | ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; |
1723 | if (ctrl->version < SWRM_VERSION_2_0_0) |
1724 | ctrl->reg_write(ctrl, |
1725 | ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], |
1726 | ctrl->intr_mask); |
1727 | ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], |
1728 | ctrl->intr_mask); |
1729 | /* Prepare slaves for clock stop */ |
1730 | ret = sdw_bus_prep_clk_stop(bus: &ctrl->bus); |
1731 | if (ret < 0 && ret != -ENODATA) { |
1732 | dev_err(dev, "prepare clock stop failed %d" , ret); |
1733 | return ret; |
1734 | } |
1735 | |
1736 | ret = sdw_bus_clk_stop(bus: &ctrl->bus); |
1737 | if (ret < 0 && ret != -ENODATA) { |
1738 | dev_err(dev, "bus clock stop failed %d" , ret); |
1739 | return ret; |
1740 | } |
1741 | } |
1742 | |
1743 | clk_disable_unprepare(clk: ctrl->hclk); |
1744 | |
1745 | usleep_range(min: 300, max: 305); |
1746 | |
1747 | if (ctrl->wake_irq > 0) { |
1748 | if (irqd_irq_disabled(d: irq_get_irq_data(irq: ctrl->wake_irq))) |
1749 | enable_irq(irq: ctrl->wake_irq); |
1750 | } |
1751 | |
1752 | return 0; |
1753 | } |
1754 | |
1755 | static const struct dev_pm_ops swrm_dev_pm_ops = { |
1756 | SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) |
1757 | }; |
1758 | |
1759 | static const struct of_device_id qcom_swrm_of_match[] = { |
1760 | { .compatible = "qcom,soundwire-v1.3.0" , .data = &swrm_v1_3_data }, |
1761 | { .compatible = "qcom,soundwire-v1.5.1" , .data = &swrm_v1_5_data }, |
1762 | { .compatible = "qcom,soundwire-v1.6.0" , .data = &swrm_v1_6_data }, |
1763 | { .compatible = "qcom,soundwire-v1.7.0" , .data = &swrm_v1_5_data }, |
1764 | { .compatible = "qcom,soundwire-v2.0.0" , .data = &swrm_v2_0_data }, |
1765 | {/* sentinel */}, |
1766 | }; |
1767 | |
1768 | MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); |
1769 | |
1770 | static struct platform_driver qcom_swrm_driver = { |
1771 | .probe = &qcom_swrm_probe, |
1772 | .remove = &qcom_swrm_remove, |
1773 | .driver = { |
1774 | .name = "qcom-soundwire" , |
1775 | .of_match_table = qcom_swrm_of_match, |
1776 | .pm = &swrm_dev_pm_ops, |
1777 | } |
1778 | }; |
1779 | module_platform_driver(qcom_swrm_driver); |
1780 | |
1781 | MODULE_DESCRIPTION("Qualcomm soundwire driver" ); |
1782 | MODULE_LICENSE("GPL v2" ); |
1783 | |