1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs |
4 | * |
5 | * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
6 | * |
7 | * This driver has been based on the spi-gpio.c: |
8 | * Copyright (C) 2006,2008 David Brownell |
9 | */ |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/spinlock.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/io.h> |
17 | #include <linux/spi/spi.h> |
18 | #include <linux/spi/spi-mem.h> |
19 | #include <linux/spi/spi_bitbang.h> |
20 | #include <linux/bitops.h> |
21 | #include <linux/clk.h> |
22 | #include <linux/err.h> |
23 | |
24 | #define DRV_NAME "ath79-spi" |
25 | |
26 | #define ATH79_SPI_RRW_DELAY_FACTOR 12000 |
27 | #define MHZ (1000 * 1000) |
28 | |
29 | #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ |
30 | #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ |
31 | #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ |
32 | #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ |
33 | |
34 | #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ |
35 | |
36 | #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ |
37 | #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ |
38 | #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) |
39 | |
40 | struct ath79_spi { |
41 | struct spi_bitbang bitbang; |
42 | u32 ioc_base; |
43 | u32 reg_ctrl; |
44 | void __iomem *base; |
45 | struct clk *clk; |
46 | unsigned int rrw_delay; |
47 | }; |
48 | |
49 | static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg) |
50 | { |
51 | return ioread32(sp->base + reg); |
52 | } |
53 | |
54 | static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) |
55 | { |
56 | iowrite32(val, sp->base + reg); |
57 | } |
58 | |
59 | static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) |
60 | { |
61 | return spi_controller_get_devdata(ctlr: spi->controller); |
62 | } |
63 | |
64 | static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs) |
65 | { |
66 | if (nsecs > sp->rrw_delay) |
67 | ndelay(nsecs - sp->rrw_delay); |
68 | } |
69 | |
70 | static void ath79_spi_chipselect(struct spi_device *spi, int is_active) |
71 | { |
72 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); |
73 | int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; |
74 | u32 cs_bit = AR71XX_SPI_IOC_CS(spi_get_chipselect(spi, 0)); |
75 | |
76 | if (cs_high) |
77 | sp->ioc_base |= cs_bit; |
78 | else |
79 | sp->ioc_base &= ~cs_bit; |
80 | |
81 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, val: sp->ioc_base); |
82 | } |
83 | |
84 | static void ath79_spi_enable(struct ath79_spi *sp) |
85 | { |
86 | /* enable GPIO mode */ |
87 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); |
88 | |
89 | /* save CTRL register */ |
90 | sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); |
91 | sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); |
92 | |
93 | /* clear clk and mosi in the base state */ |
94 | sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK); |
95 | |
96 | /* TODO: setup speed? */ |
97 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, val: 0x43); |
98 | } |
99 | |
100 | static void ath79_spi_disable(struct ath79_spi *sp) |
101 | { |
102 | /* restore CTRL register */ |
103 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, val: sp->reg_ctrl); |
104 | /* disable GPIO mode */ |
105 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, val: 0); |
106 | } |
107 | |
108 | static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs, |
109 | u32 word, u8 bits, unsigned flags) |
110 | { |
111 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); |
112 | u32 ioc = sp->ioc_base; |
113 | |
114 | /* clock starts at inactive polarity */ |
115 | for (word <<= (32 - bits); likely(bits); bits--) { |
116 | u32 out; |
117 | |
118 | if (word & (1 << 31)) |
119 | out = ioc | AR71XX_SPI_IOC_DO; |
120 | else |
121 | out = ioc & ~AR71XX_SPI_IOC_DO; |
122 | |
123 | /* setup MSB (to target) on trailing edge */ |
124 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, val: out); |
125 | ath79_spi_delay(sp, nsecs); |
126 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, val: out | AR71XX_SPI_IOC_CLK); |
127 | ath79_spi_delay(sp, nsecs); |
128 | if (bits == 1) |
129 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, val: out); |
130 | |
131 | word <<= 1; |
132 | } |
133 | |
134 | return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); |
135 | } |
136 | |
137 | static int ath79_exec_mem_op(struct spi_mem *mem, |
138 | const struct spi_mem_op *op) |
139 | { |
140 | struct ath79_spi *sp = ath79_spidev_to_sp(spi: mem->spi); |
141 | |
142 | /* Ensures that reading is performed on device connected to hardware cs0 */ |
143 | if (spi_get_chipselect(spi: mem->spi, idx: 0) || spi_get_csgpiod(spi: mem->spi, idx: 0)) |
144 | return -ENOTSUPP; |
145 | |
146 | /* Only use for fast-read op. */ |
147 | if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN || |
148 | op->addr.nbytes != 3 || op->dummy.nbytes != 1) |
149 | return -EOPNOTSUPP; |
150 | |
151 | /* disable GPIO mode */ |
152 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, val: 0); |
153 | |
154 | memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes); |
155 | |
156 | /* enable GPIO mode */ |
157 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); |
158 | |
159 | /* restore IOC register */ |
160 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, val: sp->ioc_base); |
161 | |
162 | return 0; |
163 | } |
164 | |
165 | static const struct spi_controller_mem_ops ath79_mem_ops = { |
166 | .exec_op = ath79_exec_mem_op, |
167 | }; |
168 | |
169 | static int ath79_spi_probe(struct platform_device *pdev) |
170 | { |
171 | struct spi_controller *host; |
172 | struct ath79_spi *sp; |
173 | unsigned long rate; |
174 | int ret; |
175 | |
176 | host = spi_alloc_host(dev: &pdev->dev, size: sizeof(*sp)); |
177 | if (host == NULL) { |
178 | dev_err(&pdev->dev, "failed to allocate spi host\n" ); |
179 | return -ENOMEM; |
180 | } |
181 | |
182 | sp = spi_controller_get_devdata(ctlr: host); |
183 | host->dev.of_node = pdev->dev.of_node; |
184 | platform_set_drvdata(pdev, data: sp); |
185 | |
186 | host->use_gpio_descriptors = true; |
187 | host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
188 | host->flags = SPI_CONTROLLER_GPIO_SS; |
189 | host->num_chipselect = 3; |
190 | host->mem_ops = &ath79_mem_ops; |
191 | |
192 | sp->bitbang.ctlr = host; |
193 | sp->bitbang.chipselect = ath79_spi_chipselect; |
194 | sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; |
195 | sp->bitbang.flags = SPI_CS_HIGH; |
196 | |
197 | sp->base = devm_platform_ioremap_resource(pdev, index: 0); |
198 | if (IS_ERR(ptr: sp->base)) { |
199 | ret = PTR_ERR(ptr: sp->base); |
200 | goto err_put_host; |
201 | } |
202 | |
203 | sp->clk = devm_clk_get_enabled(dev: &pdev->dev, id: "ahb" ); |
204 | if (IS_ERR(ptr: sp->clk)) { |
205 | ret = PTR_ERR(ptr: sp->clk); |
206 | goto err_put_host; |
207 | } |
208 | |
209 | rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); |
210 | if (!rate) { |
211 | ret = -EINVAL; |
212 | goto err_put_host; |
213 | } |
214 | |
215 | sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; |
216 | dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n" , |
217 | sp->rrw_delay); |
218 | |
219 | ath79_spi_enable(sp); |
220 | ret = spi_bitbang_start(spi: &sp->bitbang); |
221 | if (ret) |
222 | goto err_disable; |
223 | |
224 | return 0; |
225 | |
226 | err_disable: |
227 | ath79_spi_disable(sp); |
228 | err_put_host: |
229 | spi_controller_put(ctlr: host); |
230 | |
231 | return ret; |
232 | } |
233 | |
234 | static void ath79_spi_remove(struct platform_device *pdev) |
235 | { |
236 | struct ath79_spi *sp = platform_get_drvdata(pdev); |
237 | |
238 | spi_bitbang_stop(spi: &sp->bitbang); |
239 | ath79_spi_disable(sp); |
240 | spi_controller_put(ctlr: sp->bitbang.ctlr); |
241 | } |
242 | |
243 | static void ath79_spi_shutdown(struct platform_device *pdev) |
244 | { |
245 | ath79_spi_remove(pdev); |
246 | } |
247 | |
248 | static const struct of_device_id ath79_spi_of_match[] = { |
249 | { .compatible = "qca,ar7100-spi" , }, |
250 | { }, |
251 | }; |
252 | MODULE_DEVICE_TABLE(of, ath79_spi_of_match); |
253 | |
254 | static struct platform_driver ath79_spi_driver = { |
255 | .probe = ath79_spi_probe, |
256 | .remove_new = ath79_spi_remove, |
257 | .shutdown = ath79_spi_shutdown, |
258 | .driver = { |
259 | .name = DRV_NAME, |
260 | .of_match_table = ath79_spi_of_match, |
261 | }, |
262 | }; |
263 | module_platform_driver(ath79_spi_driver); |
264 | |
265 | MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X" ); |
266 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>" ); |
267 | MODULE_LICENSE("GPL v2" ); |
268 | MODULE_ALIAS("platform:" DRV_NAME); |
269 | |