1// SPDX-License-Identifier: GPL-2.0+
2
3/*
4 * NXP FlexSPI(FSPI) controller driver.
5 *
6 * Copyright 2019-2020 NXP
7 * Copyright 2020 Puresoftware Ltd.
8 *
9 * FlexSPI is a flexsible SPI host controller which supports two SPI
10 * channels and up to 4 external devices. Each channel supports
11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
12 * data lines).
13 *
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
16 * A valid sequence consists of four LUT registers.
17 * Maximum 32 LUT sequences can be programmed simultaneously.
18 *
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
21 *
22 * Software triggered Flash read/write access by IP Bus.
23 *
24 * Memory mapped read access by AHB Bus.
25 *
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
27 *
28 * Author:
29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
30 * Boris Brezillon <bbrezillon@kernel.org>
31 * Frieder Schrempf <frieder.schrempf@kontron.de>
32 */
33
34#include <linux/acpi.h>
35#include <linux/bitops.h>
36#include <linux/bitfield.h>
37#include <linux/clk.h>
38#include <linux/completion.h>
39#include <linux/delay.h>
40#include <linux/err.h>
41#include <linux/errno.h>
42#include <linux/interrupt.h>
43#include <linux/io.h>
44#include <linux/iopoll.h>
45#include <linux/jiffies.h>
46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/mutex.h>
49#include <linux/of.h>
50#include <linux/platform_device.h>
51#include <linux/pinctrl/consumer.h>
52#include <linux/pm_runtime.h>
53#include <linux/pm_qos.h>
54#include <linux/regmap.h>
55#include <linux/sizes.h>
56#include <linux/sys_soc.h>
57
58#include <linux/mfd/syscon.h>
59#include <linux/spi/spi.h>
60#include <linux/spi/spi-mem.h>
61
62/* runtime pm timeout */
63#define FSPI_RPM_TIMEOUT 50 /* 50ms */
64
65/* Registers used by the driver */
66#define FSPI_MCR0 0x00
67#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
68#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
69#define FSPI_MCR0_LEARN_EN BIT(15)
70#define FSPI_MCR0_SCRFRUN_EN BIT(14)
71#define FSPI_MCR0_OCTCOMB_EN BIT(13)
72#define FSPI_MCR0_DOZE_EN BIT(12)
73#define FSPI_MCR0_HSEN BIT(11)
74#define FSPI_MCR0_SERCLKDIV BIT(8)
75#define FSPI_MCR0_ATDF_EN BIT(7)
76#define FSPI_MCR0_ARDF_EN BIT(6)
77#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
78#define FSPI_MCR0_END_CFG(x) ((x) << 2)
79#define FSPI_MCR0_MDIS BIT(1)
80#define FSPI_MCR0_SWRST BIT(0)
81
82#define FSPI_MCR1 0x04
83#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
84#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
85
86#define FSPI_MCR2 0x08
87#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
88#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
89#define FSPI_MCR2_CLRLRPHS BIT(14)
90#define FSPI_MCR2_ABRDATSZ BIT(8)
91#define FSPI_MCR2_ABRLEARN BIT(7)
92#define FSPI_MCR2_ABR_READ BIT(6)
93#define FSPI_MCR2_ABRWRITE BIT(5)
94#define FSPI_MCR2_ABRDUMMY BIT(4)
95#define FSPI_MCR2_ABR_MODE BIT(3)
96#define FSPI_MCR2_ABRCADDR BIT(2)
97#define FSPI_MCR2_ABRRADDR BIT(1)
98#define FSPI_MCR2_ABR_CMD BIT(0)
99
100#define FSPI_AHBCR 0x0c
101#define FSPI_AHBCR_RDADDROPT BIT(6)
102#define FSPI_AHBCR_PREF_EN BIT(5)
103#define FSPI_AHBCR_BUFF_EN BIT(4)
104#define FSPI_AHBCR_CACH_EN BIT(3)
105#define FSPI_AHBCR_CLRTXBUF BIT(2)
106#define FSPI_AHBCR_CLRRXBUF BIT(1)
107#define FSPI_AHBCR_PAR_EN BIT(0)
108
109#define FSPI_INTEN 0x10
110#define FSPI_INTEN_SCLKSBWR BIT(9)
111#define FSPI_INTEN_SCLKSBRD BIT(8)
112#define FSPI_INTEN_DATALRNFL BIT(7)
113#define FSPI_INTEN_IPTXWE BIT(6)
114#define FSPI_INTEN_IPRXWA BIT(5)
115#define FSPI_INTEN_AHBCMDERR BIT(4)
116#define FSPI_INTEN_IPCMDERR BIT(3)
117#define FSPI_INTEN_AHBCMDGE BIT(2)
118#define FSPI_INTEN_IPCMDGE BIT(1)
119#define FSPI_INTEN_IPCMDDONE BIT(0)
120
121#define FSPI_INTR 0x14
122#define FSPI_INTR_SCLKSBWR BIT(9)
123#define FSPI_INTR_SCLKSBRD BIT(8)
124#define FSPI_INTR_DATALRNFL BIT(7)
125#define FSPI_INTR_IPTXWE BIT(6)
126#define FSPI_INTR_IPRXWA BIT(5)
127#define FSPI_INTR_AHBCMDERR BIT(4)
128#define FSPI_INTR_IPCMDERR BIT(3)
129#define FSPI_INTR_AHBCMDGE BIT(2)
130#define FSPI_INTR_IPCMDGE BIT(1)
131#define FSPI_INTR_IPCMDDONE BIT(0)
132
133#define FSPI_LUTKEY 0x18
134#define FSPI_LUTKEY_VALUE 0x5AF05AF0
135
136#define FSPI_LCKCR 0x1C
137
138#define FSPI_LCKER_LOCK 0x1
139#define FSPI_LCKER_UNLOCK 0x2
140
141#define FSPI_BUFXCR_INVALID_MSTRID 0xE
142#define FSPI_AHBRX_BUF0CR0 0x20
143#define FSPI_AHBRX_BUF1CR0 0x24
144#define FSPI_AHBRX_BUF2CR0 0x28
145#define FSPI_AHBRX_BUF3CR0 0x2C
146#define FSPI_AHBRX_BUF4CR0 0x30
147#define FSPI_AHBRX_BUF5CR0 0x34
148#define FSPI_AHBRX_BUF6CR0 0x38
149#define FSPI_AHBRX_BUF7CR0 0x3C
150#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
151
152#define FSPI_AHBRX_BUF0CR1 0x40
153#define FSPI_AHBRX_BUF1CR1 0x44
154#define FSPI_AHBRX_BUF2CR1 0x48
155#define FSPI_AHBRX_BUF3CR1 0x4C
156#define FSPI_AHBRX_BUF4CR1 0x50
157#define FSPI_AHBRX_BUF5CR1 0x54
158#define FSPI_AHBRX_BUF6CR1 0x58
159#define FSPI_AHBRX_BUF7CR1 0x5C
160
161#define FSPI_FLSHA1CR0 0x60
162#define FSPI_FLSHA2CR0 0x64
163#define FSPI_FLSHB1CR0 0x68
164#define FSPI_FLSHB2CR0 0x6C
165#define FSPI_FLSHXCR0_SZ_KB 10
166#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
167
168#define FSPI_FLSHA1CR1 0x70
169#define FSPI_FLSHA2CR1 0x74
170#define FSPI_FLSHB1CR1 0x78
171#define FSPI_FLSHB2CR1 0x7C
172#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
173#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
174#define FSPI_FLSHXCR1_WA BIT(10)
175#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
176#define FSPI_FLSHXCR1_TCSS(x) (x)
177
178#define FSPI_FLSHA1CR2 0x80
179#define FSPI_FLSHA2CR2 0x84
180#define FSPI_FLSHB1CR2 0x88
181#define FSPI_FLSHB2CR2 0x8C
182#define FSPI_FLSHXCR2_CLRINSP BIT(24)
183#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
184#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
185#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
186#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
187#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
188
189#define FSPI_IPCR0 0xA0
190
191#define FSPI_IPCR1 0xA4
192#define FSPI_IPCR1_IPAREN BIT(31)
193#define FSPI_IPCR1_SEQNUM_SHIFT 24
194#define FSPI_IPCR1_SEQID_SHIFT 16
195#define FSPI_IPCR1_IDATSZ(x) (x)
196
197#define FSPI_IPCMD 0xB0
198#define FSPI_IPCMD_TRG BIT(0)
199
200#define FSPI_DLPR 0xB4
201
202#define FSPI_IPRXFCR 0xB8
203#define FSPI_IPRXFCR_CLR BIT(0)
204#define FSPI_IPRXFCR_DMA_EN BIT(1)
205#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
206
207#define FSPI_IPTXFCR 0xBC
208#define FSPI_IPTXFCR_CLR BIT(0)
209#define FSPI_IPTXFCR_DMA_EN BIT(1)
210#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
211
212#define FSPI_DLLACR 0xC0
213#define FSPI_DLLACR_OVRDEN BIT(8)
214#define FSPI_DLLACR_SLVDLY(x) ((x) << 3)
215#define FSPI_DLLACR_DLLRESET BIT(1)
216#define FSPI_DLLACR_DLLEN BIT(0)
217
218#define FSPI_DLLBCR 0xC4
219#define FSPI_DLLBCR_OVRDEN BIT(8)
220#define FSPI_DLLBCR_SLVDLY(x) ((x) << 3)
221#define FSPI_DLLBCR_DLLRESET BIT(1)
222#define FSPI_DLLBCR_DLLEN BIT(0)
223
224#define FSPI_STS0 0xE0
225#define FSPI_STS0_DLPHB(x) ((x) << 8)
226#define FSPI_STS0_DLPHA(x) ((x) << 4)
227#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
228#define FSPI_STS0_ARB_IDLE BIT(1)
229#define FSPI_STS0_SEQ_IDLE BIT(0)
230
231#define FSPI_STS1 0xE4
232#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
233#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
234#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
235#define FSPI_STS1_AHB_ERRID(x) (x)
236
237#define FSPI_STS2 0xE8
238#define FSPI_STS2_BREFLOCK BIT(17)
239#define FSPI_STS2_BSLVLOCK BIT(16)
240#define FSPI_STS2_AREFLOCK BIT(1)
241#define FSPI_STS2_ASLVLOCK BIT(0)
242#define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \
243 FSPI_STS2_BSLVLOCK | \
244 FSPI_STS2_AREFLOCK | \
245 FSPI_STS2_ASLVLOCK)
246
247#define FSPI_AHBSPNST 0xEC
248#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
249#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
250#define FSPI_AHBSPNST_ACTIVE BIT(0)
251
252#define FSPI_IPRXFSTS 0xF0
253#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
254#define FSPI_IPRXFSTS_FILL(x) (x)
255
256#define FSPI_IPTXFSTS 0xF4
257#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
258#define FSPI_IPTXFSTS_FILL(x) (x)
259
260#define FSPI_RFDR 0x100
261#define FSPI_TFDR 0x180
262
263#define FSPI_LUT_BASE 0x200
264
265/* register map end */
266
267/* Instruction set for the LUT register. */
268#define LUT_STOP 0x00
269#define LUT_CMD 0x01
270#define LUT_ADDR 0x02
271#define LUT_CADDR_SDR 0x03
272#define LUT_MODE 0x04
273#define LUT_MODE2 0x05
274#define LUT_MODE4 0x06
275#define LUT_MODE8 0x07
276#define LUT_NXP_WRITE 0x08
277#define LUT_NXP_READ 0x09
278#define LUT_LEARN_SDR 0x0A
279#define LUT_DATSZ_SDR 0x0B
280#define LUT_DUMMY 0x0C
281#define LUT_DUMMY_RWDS_SDR 0x0D
282#define LUT_JMP_ON_CS 0x1F
283#define LUT_CMD_DDR 0x21
284#define LUT_ADDR_DDR 0x22
285#define LUT_CADDR_DDR 0x23
286#define LUT_MODE_DDR 0x24
287#define LUT_MODE2_DDR 0x25
288#define LUT_MODE4_DDR 0x26
289#define LUT_MODE8_DDR 0x27
290#define LUT_WRITE_DDR 0x28
291#define LUT_READ_DDR 0x29
292#define LUT_LEARN_DDR 0x2A
293#define LUT_DATSZ_DDR 0x2B
294#define LUT_DUMMY_DDR 0x2C
295#define LUT_DUMMY_RWDS_DDR 0x2D
296
297/*
298 * Calculate number of required PAD bits for LUT register.
299 *
300 * The pad stands for the number of IO lines [0:7].
301 * For example, the octal read needs eight IO lines,
302 * so you should use LUT_PAD(8). This macro
303 * returns 3 i.e. use eight (2^3) IP lines for read.
304 */
305#define LUT_PAD(x) (fls(x) - 1)
306
307/*
308 * Macro for constructing the LUT entries with the following
309 * register layout:
310 *
311 * ---------------------------------------------------
312 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
313 * ---------------------------------------------------
314 */
315#define PAD_SHIFT 8
316#define INSTR_SHIFT 10
317#define OPRND_SHIFT 16
318
319/* Macros for constructing the LUT register. */
320#define LUT_DEF(idx, ins, pad, opr) \
321 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
322 (opr)) << (((idx) % 2) * OPRND_SHIFT))
323
324#define POLL_TOUT 5000
325#define NXP_FSPI_MAX_CHIPSELECT 4
326#define NXP_FSPI_MIN_IOMAP SZ_4M
327
328#define DCFG_RCWSR1 0x100
329#define SYS_PLL_RAT GENMASK(6, 2)
330
331/* Access flash memory using IP bus only */
332#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
333
334struct nxp_fspi_devtype_data {
335 unsigned int rxfifo;
336 unsigned int txfifo;
337 unsigned int ahb_buf_size;
338 unsigned int quirks;
339 unsigned int lut_num;
340 bool little_endian;
341};
342
343static struct nxp_fspi_devtype_data lx2160a_data = {
344 .rxfifo = SZ_512, /* (64 * 64 bits) */
345 .txfifo = SZ_1K, /* (128 * 64 bits) */
346 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
347 .quirks = 0,
348 .lut_num = 32,
349 .little_endian = true, /* little-endian */
350};
351
352static struct nxp_fspi_devtype_data imx8mm_data = {
353 .rxfifo = SZ_512, /* (64 * 64 bits) */
354 .txfifo = SZ_1K, /* (128 * 64 bits) */
355 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
356 .quirks = 0,
357 .lut_num = 32,
358 .little_endian = true, /* little-endian */
359};
360
361static struct nxp_fspi_devtype_data imx8qxp_data = {
362 .rxfifo = SZ_512, /* (64 * 64 bits) */
363 .txfifo = SZ_1K, /* (128 * 64 bits) */
364 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
365 .quirks = 0,
366 .lut_num = 32,
367 .little_endian = true, /* little-endian */
368};
369
370static struct nxp_fspi_devtype_data imx8dxl_data = {
371 .rxfifo = SZ_512, /* (64 * 64 bits) */
372 .txfifo = SZ_1K, /* (128 * 64 bits) */
373 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
374 .quirks = FSPI_QUIRK_USE_IP_ONLY,
375 .lut_num = 32,
376 .little_endian = true, /* little-endian */
377};
378
379static struct nxp_fspi_devtype_data imx8ulp_data = {
380 .rxfifo = SZ_512, /* (64 * 64 bits) */
381 .txfifo = SZ_1K, /* (128 * 64 bits) */
382 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
383 .quirks = 0,
384 .lut_num = 16,
385 .little_endian = true, /* little-endian */
386};
387
388struct nxp_fspi {
389 void __iomem *iobase;
390 void __iomem *ahb_addr;
391 u32 memmap_phy;
392 u32 memmap_phy_size;
393 u32 memmap_start;
394 u32 memmap_len;
395 struct clk *clk, *clk_en;
396 struct device *dev;
397 struct completion c;
398 struct nxp_fspi_devtype_data *devtype_data;
399 struct mutex lock;
400 struct pm_qos_request pm_qos_req;
401 int selected;
402#define FSPI_NEED_INIT (1 << 0)
403 int flags;
404};
405
406static inline int needs_ip_only(struct nxp_fspi *f)
407{
408 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY;
409}
410
411/*
412 * R/W functions for big- or little-endian registers:
413 * The FSPI controller's endianness is independent of
414 * the CPU core's endianness. So far, although the CPU
415 * core is little-endian the FSPI controller can use
416 * big-endian or little-endian.
417 */
418static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
419{
420 if (f->devtype_data->little_endian)
421 iowrite32(val, addr);
422 else
423 iowrite32be(val, addr);
424}
425
426static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
427{
428 if (f->devtype_data->little_endian)
429 return ioread32(addr);
430 else
431 return ioread32be(addr);
432}
433
434static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
435{
436 struct nxp_fspi *f = dev_id;
437 u32 reg;
438
439 /* clear interrupt */
440 reg = fspi_readl(f, addr: f->iobase + FSPI_INTR);
441 fspi_writel(f, FSPI_INTR_IPCMDDONE, addr: f->iobase + FSPI_INTR);
442
443 if (reg & FSPI_INTR_IPCMDDONE)
444 complete(&f->c);
445
446 return IRQ_HANDLED;
447}
448
449static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
450{
451 switch (width) {
452 case 1:
453 case 2:
454 case 4:
455 case 8:
456 return 0;
457 }
458
459 return -ENOTSUPP;
460}
461
462static bool nxp_fspi_supports_op(struct spi_mem *mem,
463 const struct spi_mem_op *op)
464{
465 struct nxp_fspi *f = spi_controller_get_devdata(ctlr: mem->spi->controller);
466 int ret;
467
468 ret = nxp_fspi_check_buswidth(f, width: op->cmd.buswidth);
469
470 if (op->addr.nbytes)
471 ret |= nxp_fspi_check_buswidth(f, width: op->addr.buswidth);
472
473 if (op->dummy.nbytes)
474 ret |= nxp_fspi_check_buswidth(f, width: op->dummy.buswidth);
475
476 if (op->data.nbytes)
477 ret |= nxp_fspi_check_buswidth(f, width: op->data.buswidth);
478
479 if (ret)
480 return false;
481
482 /*
483 * The number of address bytes should be equal to or less than 4 bytes.
484 */
485 if (op->addr.nbytes > 4)
486 return false;
487
488 /*
489 * If requested address value is greater than controller assigned
490 * memory mapped space, return error as it didn't fit in the range
491 * of assigned address space.
492 */
493 if (op->addr.val >= f->memmap_phy_size)
494 return false;
495
496 /* Max 64 dummy clock cycles supported */
497 if (op->dummy.buswidth &&
498 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
499 return false;
500
501 /* Max data length, check controller limits and alignment */
502 if (op->data.dir == SPI_MEM_DATA_IN &&
503 (op->data.nbytes > f->devtype_data->ahb_buf_size ||
504 (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
505 !IS_ALIGNED(op->data.nbytes, 8))))
506 return false;
507
508 if (op->data.dir == SPI_MEM_DATA_OUT &&
509 op->data.nbytes > f->devtype_data->txfifo)
510 return false;
511
512 return spi_mem_default_supports_op(mem, op);
513}
514
515/* Instead of busy looping invoke readl_poll_timeout functionality. */
516static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
517 u32 mask, u32 delay_us,
518 u32 timeout_us, bool c)
519{
520 u32 reg;
521
522 if (!f->devtype_data->little_endian)
523 mask = (u32)cpu_to_be32(mask);
524
525 if (c)
526 return readl_poll_timeout(base, reg, (reg & mask),
527 delay_us, timeout_us);
528 else
529 return readl_poll_timeout(base, reg, !(reg & mask),
530 delay_us, timeout_us);
531}
532
533/*
534 * If the target device content being changed by Write/Erase, need to
535 * invalidate the AHB buffer. This can be achieved by doing the reset
536 * of controller after setting MCR0[SWRESET] bit.
537 */
538static inline void nxp_fspi_invalid(struct nxp_fspi *f)
539{
540 u32 reg;
541 int ret;
542
543 reg = fspi_readl(f, addr: f->iobase + FSPI_MCR0);
544 fspi_writel(f, val: reg | FSPI_MCR0_SWRST, addr: f->iobase + FSPI_MCR0);
545
546 /* w1c register, wait unit clear */
547 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_MCR0,
548 FSPI_MCR0_SWRST, delay_us: 0, POLL_TOUT, c: false);
549 WARN_ON(ret);
550}
551
552static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
553 const struct spi_mem_op *op)
554{
555 void __iomem *base = f->iobase;
556 u32 lutval[4] = {};
557 int lutidx = 1, i;
558 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4;
559 u32 target_lut_reg;
560
561 /* cmd */
562 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
563 op->cmd.opcode);
564
565 /* addr bytes */
566 if (op->addr.nbytes) {
567 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
568 LUT_PAD(op->addr.buswidth),
569 op->addr.nbytes * 8);
570 lutidx++;
571 }
572
573 /* dummy bytes, if needed */
574 if (op->dummy.nbytes) {
575 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
576 /*
577 * Due to FlexSPI controller limitation number of PAD for dummy
578 * buswidth needs to be programmed as equal to data buswidth.
579 */
580 LUT_PAD(op->data.buswidth),
581 op->dummy.nbytes * 8 /
582 op->dummy.buswidth);
583 lutidx++;
584 }
585
586 /* read/write data bytes */
587 if (op->data.nbytes) {
588 lutval[lutidx / 2] |= LUT_DEF(lutidx,
589 op->data.dir == SPI_MEM_DATA_IN ?
590 LUT_NXP_READ : LUT_NXP_WRITE,
591 LUT_PAD(op->data.buswidth),
592 0);
593 lutidx++;
594 }
595
596 /* stop condition. */
597 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
598
599 /* unlock LUT */
600 fspi_writel(f, FSPI_LUTKEY_VALUE, addr: f->iobase + FSPI_LUTKEY);
601 fspi_writel(f, FSPI_LCKER_UNLOCK, addr: f->iobase + FSPI_LCKCR);
602
603 /* fill LUT */
604 for (i = 0; i < ARRAY_SIZE(lutval); i++) {
605 target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4;
606 fspi_writel(f, val: lutval[i], addr: base + target_lut_reg);
607 }
608
609 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n",
610 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes);
611
612 /* lock LUT */
613 fspi_writel(f, FSPI_LUTKEY_VALUE, addr: f->iobase + FSPI_LUTKEY);
614 fspi_writel(f, FSPI_LCKER_LOCK, addr: f->iobase + FSPI_LCKCR);
615}
616
617static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
618{
619 int ret;
620
621 if (is_acpi_node(dev_fwnode(f->dev)))
622 return 0;
623
624 ret = clk_prepare_enable(clk: f->clk_en);
625 if (ret)
626 return ret;
627
628 ret = clk_prepare_enable(clk: f->clk);
629 if (ret) {
630 clk_disable_unprepare(clk: f->clk_en);
631 return ret;
632 }
633
634 return 0;
635}
636
637static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
638{
639 if (is_acpi_node(dev_fwnode(f->dev)))
640 return;
641
642 clk_disable_unprepare(clk: f->clk);
643 clk_disable_unprepare(clk: f->clk_en);
644
645 return;
646}
647
648static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
649{
650 int ret;
651
652 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */
653 fspi_writel(f, FSPI_DLLACR_DLLRESET, addr: f->iobase + FSPI_DLLACR);
654 fspi_writel(f, FSPI_DLLBCR_DLLRESET, addr: f->iobase + FSPI_DLLBCR);
655 fspi_writel(f, val: 0, addr: f->iobase + FSPI_DLLACR);
656 fspi_writel(f, val: 0, addr: f->iobase + FSPI_DLLBCR);
657
658 /*
659 * Enable the DLL calibration mode.
660 * The delay target for slave delay line is:
661 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock.
662 * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which
663 * means half of clock cycle of reference clock.
664 */
665 fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF),
666 addr: f->iobase + FSPI_DLLACR);
667 fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF),
668 addr: f->iobase + FSPI_DLLBCR);
669
670 /* Wait to get REF/SLV lock */
671 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK,
672 delay_us: 0, POLL_TOUT, c: true);
673 if (ret)
674 dev_warn(f->dev, "DLL lock failed, please fix it!\n");
675}
676
677/*
678 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
679 * register and start base address of the target device.
680 *
681 * (Higher address)
682 * -------- <-- FLSHB2CR0
683 * | B2 |
684 * | |
685 * B2 start address --> -------- <-- FLSHB1CR0
686 * | B1 |
687 * | |
688 * B1 start address --> -------- <-- FLSHA2CR0
689 * | A2 |
690 * | |
691 * A2 start address --> -------- <-- FLSHA1CR0
692 * | A1 |
693 * | |
694 * A1 start address --> -------- (Lower address)
695 *
696 *
697 * Start base address defines the starting address range for given CS and
698 * FSPI_FLSHXXCR0 defines the size of the target device connected at given CS.
699 *
700 * But, different targets are having different combinations of number of CS,
701 * some targets only have single CS or two CS covering controller's full
702 * memory mapped space area.
703 * Thus, implementation is being done as independent of the size and number
704 * of the connected target device.
705 * Assign controller memory mapped space size as the size to the connected
706 * target device.
707 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
708 * chip-select Flash configuration register.
709 *
710 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
711 * memory mapped size of the controller.
712 * Value for rest of the CS FLSHxxCR0 register would be zero.
713 *
714 */
715static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
716 const struct spi_mem_op *op)
717{
718 unsigned long rate = op->max_freq;
719 int ret;
720 uint64_t size_kb;
721
722 /*
723 * Return, if previously selected target device is same as current
724 * requested target device.
725 */
726 if (f->selected == spi_get_chipselect(spi, idx: 0))
727 return;
728
729 /* Reset FLSHxxCR0 registers */
730 fspi_writel(f, val: 0, addr: f->iobase + FSPI_FLSHA1CR0);
731 fspi_writel(f, val: 0, addr: f->iobase + FSPI_FLSHA2CR0);
732 fspi_writel(f, val: 0, addr: f->iobase + FSPI_FLSHB1CR0);
733 fspi_writel(f, val: 0, addr: f->iobase + FSPI_FLSHB2CR0);
734
735 /* Assign controller memory mapped space as size, KBytes, of flash. */
736 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
737
738 fspi_writel(f, val: size_kb, addr: f->iobase + FSPI_FLSHA1CR0 +
739 4 * spi_get_chipselect(spi, idx: 0));
740
741 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
742
743 nxp_fspi_clk_disable_unprep(f);
744
745 ret = clk_set_rate(clk: f->clk, rate);
746 if (ret)
747 return;
748
749 ret = nxp_fspi_clk_prep_enable(f);
750 if (ret)
751 return;
752
753 /*
754 * If clock rate > 100MHz, then switch from DLL override mode to
755 * DLL calibration mode.
756 */
757 if (rate > 100000000)
758 nxp_fspi_dll_calibration(f);
759
760 f->selected = spi_get_chipselect(spi, idx: 0);
761}
762
763static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
764{
765 u32 start = op->addr.val;
766 u32 len = op->data.nbytes;
767
768 /* if necessary, ioremap before AHB read */
769 if ((!f->ahb_addr) || start < f->memmap_start ||
770 start + len > f->memmap_start + f->memmap_len) {
771 if (f->ahb_addr)
772 iounmap(addr: f->ahb_addr);
773
774 f->memmap_start = start;
775 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP);
776
777 f->ahb_addr = ioremap(offset: f->memmap_phy + f->memmap_start,
778 size: f->memmap_len);
779
780 if (!f->ahb_addr) {
781 dev_err(f->dev, "failed to alloc memory\n");
782 return -ENOMEM;
783 }
784 }
785
786 /* Read out the data directly from the AHB buffer. */
787 memcpy_fromio(op->data.buf.in,
788 f->ahb_addr + start - f->memmap_start, len);
789
790 return 0;
791}
792
793static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
794 const struct spi_mem_op *op)
795{
796 void __iomem *base = f->iobase;
797 int i, ret;
798 u8 *buf = (u8 *) op->data.buf.out;
799
800 /* clear the TX FIFO. */
801 fspi_writel(f, FSPI_IPTXFCR_CLR, addr: base + FSPI_IPTXFCR);
802
803 /*
804 * Default value of water mark level is 8 bytes, hence in single
805 * write request controller can write max 8 bytes of data.
806 */
807
808 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
809 /* Wait for TXFIFO empty */
810 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_INTR,
811 FSPI_INTR_IPTXWE, delay_us: 0,
812 POLL_TOUT, c: true);
813 WARN_ON(ret);
814
815 fspi_writel(f, val: *(u32 *) (buf + i), addr: base + FSPI_TFDR);
816 fspi_writel(f, val: *(u32 *) (buf + i + 4), addr: base + FSPI_TFDR + 4);
817 fspi_writel(f, FSPI_INTR_IPTXWE, addr: base + FSPI_INTR);
818 }
819
820 if (i < op->data.nbytes) {
821 u32 data = 0;
822 int j;
823 int remaining = op->data.nbytes - i;
824 /* Wait for TXFIFO empty */
825 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_INTR,
826 FSPI_INTR_IPTXWE, delay_us: 0,
827 POLL_TOUT, c: true);
828 WARN_ON(ret);
829
830 for (j = 0; j < ALIGN(remaining, 4); j += 4) {
831 memcpy(&data, buf + i + j, min_t(int, 4, remaining - j));
832 fspi_writel(f, val: data, addr: base + FSPI_TFDR + j);
833 }
834 fspi_writel(f, FSPI_INTR_IPTXWE, addr: base + FSPI_INTR);
835 }
836}
837
838static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
839 const struct spi_mem_op *op)
840{
841 void __iomem *base = f->iobase;
842 int i, ret;
843 int len = op->data.nbytes;
844 u8 *buf = (u8 *) op->data.buf.in;
845
846 /*
847 * Default value of water mark level is 8 bytes, hence in single
848 * read request controller can read max 8 bytes of data.
849 */
850 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
851 /* Wait for RXFIFO available */
852 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_INTR,
853 FSPI_INTR_IPRXWA, delay_us: 0,
854 POLL_TOUT, c: true);
855 WARN_ON(ret);
856
857 *(u32 *)(buf + i) = fspi_readl(f, addr: base + FSPI_RFDR);
858 *(u32 *)(buf + i + 4) = fspi_readl(f, addr: base + FSPI_RFDR + 4);
859 /* move the FIFO pointer */
860 fspi_writel(f, FSPI_INTR_IPRXWA, addr: base + FSPI_INTR);
861 }
862
863 if (i < len) {
864 u32 tmp;
865 int size, j;
866
867 buf = op->data.buf.in + i;
868 /* Wait for RXFIFO available */
869 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_INTR,
870 FSPI_INTR_IPRXWA, delay_us: 0,
871 POLL_TOUT, c: true);
872 WARN_ON(ret);
873
874 len = op->data.nbytes - i;
875 for (j = 0; j < op->data.nbytes - i; j += 4) {
876 tmp = fspi_readl(f, addr: base + FSPI_RFDR + j);
877 size = min(len, 4);
878 memcpy(buf + j, &tmp, size);
879 len -= size;
880 }
881 }
882
883 /* invalid the RXFIFO */
884 fspi_writel(f, FSPI_IPRXFCR_CLR, addr: base + FSPI_IPRXFCR);
885 /* move the FIFO pointer */
886 fspi_writel(f, FSPI_INTR_IPRXWA, addr: base + FSPI_INTR);
887}
888
889static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
890{
891 void __iomem *base = f->iobase;
892 int seqnum = 0;
893 int err = 0;
894 u32 reg, seqid_lut;
895
896 reg = fspi_readl(f, addr: base + FSPI_IPRXFCR);
897 /* invalid RXFIFO first */
898 reg &= ~FSPI_IPRXFCR_DMA_EN;
899 reg = reg | FSPI_IPRXFCR_CLR;
900 fspi_writel(f, val: reg, addr: base + FSPI_IPRXFCR);
901
902 init_completion(x: &f->c);
903
904 fspi_writel(f, val: op->addr.val, addr: base + FSPI_IPCR0);
905 /*
906 * Always start the sequence at the same index since we update
907 * the LUT at each exec_op() call. And also specify the DATA
908 * length, since it's has not been specified in the LUT.
909 */
910 seqid_lut = f->devtype_data->lut_num - 1;
911 fspi_writel(f, val: op->data.nbytes |
912 (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) |
913 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
914 addr: base + FSPI_IPCR1);
915
916 /* Trigger the LUT now. */
917 fspi_writel(f, FSPI_IPCMD_TRG, addr: base + FSPI_IPCMD);
918
919 /* Wait for the interrupt. */
920 if (!wait_for_completion_timeout(x: &f->c, timeout: msecs_to_jiffies(m: 1000)))
921 err = -ETIMEDOUT;
922
923 /* Invoke IP data read, if request is of data read. */
924 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
925 nxp_fspi_read_rxfifo(f, op);
926
927 return err;
928}
929
930static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
931{
932 struct nxp_fspi *f = spi_controller_get_devdata(ctlr: mem->spi->controller);
933 int err = 0;
934
935 guard(mutex)(T: &f->lock);
936
937 err = pm_runtime_get_sync(dev: f->dev);
938 if (err < 0) {
939 dev_err(f->dev, "Failed to enable clock %d\n", __LINE__);
940 return err;
941 }
942
943 /* Wait for controller being ready. */
944 err = fspi_readl_poll_tout(f, base: f->iobase + FSPI_STS0,
945 FSPI_STS0_ARB_IDLE, delay_us: 1, POLL_TOUT, c: true);
946 WARN_ON(err);
947
948 nxp_fspi_select_mem(f, spi: mem->spi, op);
949
950 nxp_fspi_prepare_lut(f, op);
951 /*
952 * If we have large chunks of data, we read them through the AHB bus by
953 * accessing the mapped memory. In all other cases we use IP commands
954 * to access the flash. Read via AHB bus may be corrupted due to
955 * existence of an errata and therefore discard AHB read in such cases.
956 */
957 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
958 op->data.dir == SPI_MEM_DATA_IN &&
959 !needs_ip_only(f)) {
960 err = nxp_fspi_read_ahb(f, op);
961 } else {
962 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
963 nxp_fspi_fill_txfifo(f, op);
964
965 err = nxp_fspi_do_op(f, op);
966 }
967
968 /* Invalidate the data in the AHB buffer. */
969 nxp_fspi_invalid(f);
970
971 pm_runtime_mark_last_busy(dev: f->dev);
972 pm_runtime_put_autosuspend(dev: f->dev);
973
974 return err;
975}
976
977static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
978{
979 struct nxp_fspi *f = spi_controller_get_devdata(ctlr: mem->spi->controller);
980
981 if (op->data.dir == SPI_MEM_DATA_OUT) {
982 if (op->data.nbytes > f->devtype_data->txfifo)
983 op->data.nbytes = f->devtype_data->txfifo;
984 } else {
985 if (op->data.nbytes > f->devtype_data->ahb_buf_size)
986 op->data.nbytes = f->devtype_data->ahb_buf_size;
987 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
988 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
989 }
990
991 /* Limit data bytes to RX FIFO in case of IP read only */
992 if (op->data.dir == SPI_MEM_DATA_IN &&
993 needs_ip_only(f) &&
994 op->data.nbytes > f->devtype_data->rxfifo)
995 op->data.nbytes = f->devtype_data->rxfifo;
996
997 return 0;
998}
999
1000static void erratum_err050568(struct nxp_fspi *f)
1001{
1002 static const struct soc_device_attribute ls1028a_soc_attr[] = {
1003 { .family = "QorIQ LS1028A" },
1004 { /* sentinel */ }
1005 };
1006 struct regmap *map;
1007 u32 val, sys_pll_ratio;
1008 int ret;
1009
1010 /* Check for LS1028A family */
1011 if (!soc_device_match(matches: ls1028a_soc_attr)) {
1012 dev_dbg(f->dev, "Errata applicable only for LS1028A\n");
1013 return;
1014 }
1015
1016 map = syscon_regmap_lookup_by_compatible(s: "fsl,ls1028a-dcfg");
1017 if (IS_ERR(ptr: map)) {
1018 dev_err(f->dev, "No syscon regmap\n");
1019 goto err;
1020 }
1021
1022 ret = regmap_read(map, DCFG_RCWSR1, val: &val);
1023 if (ret < 0)
1024 goto err;
1025
1026 sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val);
1027 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio);
1028
1029 /* Use IP bus only if platform clock is 300MHz */
1030 if (sys_pll_ratio == 3)
1031 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY;
1032
1033 return;
1034
1035err:
1036 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n");
1037}
1038
1039static int nxp_fspi_default_setup(struct nxp_fspi *f)
1040{
1041 void __iomem *base = f->iobase;
1042 int ret, i;
1043 u32 reg, seqid_lut;
1044
1045 /* disable and unprepare clock to avoid glitch pass to controller */
1046 nxp_fspi_clk_disable_unprep(f);
1047
1048 /* the default frequency, we will change it later if necessary. */
1049 ret = clk_set_rate(clk: f->clk, rate: 20000000);
1050 if (ret)
1051 return ret;
1052
1053 ret = nxp_fspi_clk_prep_enable(f);
1054 if (ret)
1055 return ret;
1056
1057 /*
1058 * ERR050568: Flash access by FlexSPI AHB command may not work with
1059 * platform frequency equal to 300 MHz on LS1028A.
1060 * LS1028A reuses LX2160A compatible entry. Make errata applicable for
1061 * Layerscape LS1028A platform.
1062 */
1063 if (of_device_is_compatible(device: f->dev->of_node, "nxp,lx2160a-fspi"))
1064 erratum_err050568(f);
1065
1066 /* Reset the module */
1067 /* w1c register, wait unit clear */
1068 ret = fspi_readl_poll_tout(f, base: f->iobase + FSPI_MCR0,
1069 FSPI_MCR0_SWRST, delay_us: 0, POLL_TOUT, c: false);
1070 WARN_ON(ret);
1071
1072 /* Disable the module */
1073 fspi_writel(f, FSPI_MCR0_MDIS, addr: base + FSPI_MCR0);
1074
1075 /*
1076 * Config the DLL register to default value, enable the target clock delay
1077 * line delay cell override mode, and use 1 fixed delay cell in DLL delay
1078 * chain, this is the suggested setting when clock rate < 100MHz.
1079 */
1080 fspi_writel(f, FSPI_DLLACR_OVRDEN, addr: base + FSPI_DLLACR);
1081 fspi_writel(f, FSPI_DLLBCR_OVRDEN, addr: base + FSPI_DLLBCR);
1082
1083 /* enable module */
1084 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
1085 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN,
1086 addr: base + FSPI_MCR0);
1087
1088 /*
1089 * Disable same device enable bit and configure all target devices
1090 * independently.
1091 */
1092 reg = fspi_readl(f, addr: f->iobase + FSPI_MCR2);
1093 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
1094 fspi_writel(f, val: reg, addr: base + FSPI_MCR2);
1095
1096 /* AHB configuration for access buffer 0~7. */
1097 for (i = 0; i < 7; i++)
1098 fspi_writel(f, val: 0, addr: base + FSPI_AHBRX_BUF0CR0 + 4 * i);
1099
1100 /*
1101 * Set ADATSZ with the maximum AHB buffer size to improve the read
1102 * performance.
1103 */
1104 fspi_writel(f, val: (f->devtype_data->ahb_buf_size / 8 |
1105 FSPI_AHBRXBUF0CR7_PREF), addr: base + FSPI_AHBRX_BUF7CR0);
1106
1107 /* prefetch and no start address alignment limitation */
1108 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
1109 addr: base + FSPI_AHBCR);
1110
1111 /* Reset the FLSHxCR1 registers. */
1112 reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3);
1113 fspi_writel(f, val: reg, addr: base + FSPI_FLSHA1CR1);
1114 fspi_writel(f, val: reg, addr: base + FSPI_FLSHA2CR1);
1115 fspi_writel(f, val: reg, addr: base + FSPI_FLSHB1CR1);
1116 fspi_writel(f, val: reg, addr: base + FSPI_FLSHB2CR1);
1117
1118 /*
1119 * The driver only uses one single LUT entry, that is updated on
1120 * each call of exec_op(). Index 0 is preset at boot with a basic
1121 * read operation, so let's use the last entry.
1122 */
1123 seqid_lut = f->devtype_data->lut_num - 1;
1124 /* AHB Read - Set lut sequence ID for all CS. */
1125 fspi_writel(f, val: seqid_lut, addr: base + FSPI_FLSHA1CR2);
1126 fspi_writel(f, val: seqid_lut, addr: base + FSPI_FLSHA2CR2);
1127 fspi_writel(f, val: seqid_lut, addr: base + FSPI_FLSHB1CR2);
1128 fspi_writel(f, val: seqid_lut, addr: base + FSPI_FLSHB2CR2);
1129
1130 f->selected = -1;
1131
1132 /* enable the interrupt */
1133 fspi_writel(f, FSPI_INTEN_IPCMDDONE, addr: base + FSPI_INTEN);
1134
1135 return 0;
1136}
1137
1138static const char *nxp_fspi_get_name(struct spi_mem *mem)
1139{
1140 struct nxp_fspi *f = spi_controller_get_devdata(ctlr: mem->spi->controller);
1141 struct device *dev = &mem->spi->dev;
1142 const char *name;
1143
1144 // Set custom name derived from the platform_device of the controller.
1145 if (of_get_available_child_count(np: f->dev->of_node) == 1)
1146 return dev_name(dev: f->dev);
1147
1148 name = devm_kasprintf(dev, GFP_KERNEL,
1149 fmt: "%s-%d", dev_name(dev: f->dev),
1150 spi_get_chipselect(spi: mem->spi, idx: 0));
1151
1152 if (!name) {
1153 dev_err(dev, "failed to get memory for custom flash name\n");
1154 return ERR_PTR(error: -ENOMEM);
1155 }
1156
1157 return name;
1158}
1159
1160static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
1161 .adjust_op_size = nxp_fspi_adjust_op_size,
1162 .supports_op = nxp_fspi_supports_op,
1163 .exec_op = nxp_fspi_exec_op,
1164 .get_name = nxp_fspi_get_name,
1165};
1166
1167static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
1168 .per_op_freq = true,
1169};
1170
1171static void nxp_fspi_cleanup(void *data)
1172{
1173 struct nxp_fspi *f = data;
1174
1175 /* enable clock first since there is register access */
1176 pm_runtime_get_sync(dev: f->dev);
1177
1178 /* disable the hardware */
1179 fspi_writel(f, FSPI_MCR0_MDIS, addr: f->iobase + FSPI_MCR0);
1180
1181 pm_runtime_disable(dev: f->dev);
1182 pm_runtime_put_noidle(dev: f->dev);
1183 nxp_fspi_clk_disable_unprep(f);
1184
1185 if (f->ahb_addr)
1186 iounmap(addr: f->ahb_addr);
1187}
1188
1189static int nxp_fspi_probe(struct platform_device *pdev)
1190{
1191 struct spi_controller *ctlr;
1192 struct device *dev = &pdev->dev;
1193 struct device_node *np = dev->of_node;
1194 struct resource *res;
1195 struct nxp_fspi *f;
1196 int ret, irq;
1197 u32 reg;
1198
1199 ctlr = devm_spi_alloc_host(dev: &pdev->dev, size: sizeof(*f));
1200 if (!ctlr)
1201 return -ENOMEM;
1202
1203 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
1204 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
1205
1206 f = spi_controller_get_devdata(ctlr);
1207 f->dev = dev;
1208 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev);
1209 if (!f->devtype_data)
1210 return -ENODEV;
1211
1212 platform_set_drvdata(pdev, data: f);
1213
1214 /* find the resources - configuration register address space */
1215 if (is_acpi_node(dev_fwnode(f->dev)))
1216 f->iobase = devm_platform_ioremap_resource(pdev, index: 0);
1217 else
1218 f->iobase = devm_platform_ioremap_resource_byname(pdev, name: "fspi_base");
1219 if (IS_ERR(ptr: f->iobase))
1220 return PTR_ERR(ptr: f->iobase);
1221
1222 /* find the resources - controller memory mapped space */
1223 if (is_acpi_node(dev_fwnode(f->dev)))
1224 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1225 else
1226 res = platform_get_resource_byname(pdev,
1227 IORESOURCE_MEM, "fspi_mmap");
1228 if (!res)
1229 return -ENODEV;
1230
1231 /* assign memory mapped starting address and mapped size. */
1232 f->memmap_phy = res->start;
1233 f->memmap_phy_size = resource_size(res);
1234
1235 /* find the clocks */
1236 if (dev_of_node(dev: &pdev->dev)) {
1237 f->clk_en = devm_clk_get(dev, id: "fspi_en");
1238 if (IS_ERR(ptr: f->clk_en))
1239 return PTR_ERR(ptr: f->clk_en);
1240
1241 f->clk = devm_clk_get(dev, id: "fspi");
1242 if (IS_ERR(ptr: f->clk))
1243 return PTR_ERR(ptr: f->clk);
1244 }
1245
1246 /* find the irq */
1247 irq = platform_get_irq(pdev, 0);
1248 if (irq < 0)
1249 return dev_err_probe(dev, err: irq, fmt: "Failed to get irq source");
1250
1251 pm_runtime_enable(dev);
1252 pm_runtime_set_autosuspend_delay(dev, FSPI_RPM_TIMEOUT);
1253 pm_runtime_use_autosuspend(dev);
1254
1255 /* enable clock */
1256 ret = pm_runtime_get_sync(dev: f->dev);
1257 if (ret < 0)
1258 return dev_err_probe(dev, err: ret, fmt: "Failed to enable clock");
1259
1260 /* Clear potential interrupts */
1261 reg = fspi_readl(f, addr: f->iobase + FSPI_INTR);
1262 if (reg)
1263 fspi_writel(f, val: reg, addr: f->iobase + FSPI_INTR);
1264
1265 nxp_fspi_default_setup(f);
1266
1267 ret = pm_runtime_put_sync(dev);
1268 if (ret < 0)
1269 return dev_err_probe(dev, err: ret, fmt: "Failed to disable clock");
1270
1271 ret = devm_request_irq(dev, irq,
1272 handler: nxp_fspi_irq_handler, irqflags: 0, devname: pdev->name, dev_id: f);
1273 if (ret)
1274 return dev_err_probe(dev, err: ret, fmt: "Failed to request irq\n");
1275
1276 devm_mutex_init(dev, &f->lock);
1277
1278 ctlr->bus_num = -1;
1279 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
1280 ctlr->mem_ops = &nxp_fspi_mem_ops;
1281 ctlr->mem_caps = &nxp_fspi_mem_caps;
1282 ctlr->dev.of_node = np;
1283
1284 ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f);
1285 if (ret)
1286 return dev_err_probe(dev, err: ret, fmt: "Failed to register nxp_fspi_cleanup\n");
1287
1288 return devm_spi_register_controller(dev: &pdev->dev, ctlr);
1289}
1290
1291static int nxp_fspi_runtime_suspend(struct device *dev)
1292{
1293 struct nxp_fspi *f = dev_get_drvdata(dev);
1294
1295 nxp_fspi_clk_disable_unprep(f);
1296
1297 return 0;
1298}
1299
1300static int nxp_fspi_runtime_resume(struct device *dev)
1301{
1302 struct nxp_fspi *f = dev_get_drvdata(dev);
1303 int ret;
1304
1305 ret = nxp_fspi_clk_prep_enable(f);
1306 if (ret)
1307 return ret;
1308
1309 if (f->flags & FSPI_NEED_INIT) {
1310 nxp_fspi_default_setup(f);
1311 ret = pinctrl_pm_select_default_state(dev);
1312 if (ret)
1313 dev_err(dev, "select flexspi default pinctrl failed!\n");
1314 f->flags &= ~FSPI_NEED_INIT;
1315 }
1316
1317 return ret;
1318}
1319
1320static int nxp_fspi_suspend(struct device *dev)
1321{
1322 struct nxp_fspi *f = dev_get_drvdata(dev);
1323 int ret;
1324
1325 ret = pinctrl_pm_select_sleep_state(dev);
1326 if (ret) {
1327 dev_err(dev, "select flexspi sleep pinctrl failed!\n");
1328 return ret;
1329 }
1330
1331 f->flags |= FSPI_NEED_INIT;
1332
1333 return pm_runtime_force_suspend(dev);
1334}
1335
1336static const struct dev_pm_ops nxp_fspi_pm_ops = {
1337 RUNTIME_PM_OPS(nxp_fspi_runtime_suspend, nxp_fspi_runtime_resume, NULL)
1338 SYSTEM_SLEEP_PM_OPS(nxp_fspi_suspend, pm_runtime_force_resume)
1339};
1340
1341static const struct of_device_id nxp_fspi_dt_ids[] = {
1342 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1343 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, },
1344 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, },
1345 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, },
1346 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, },
1347 { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, },
1348 { /* sentinel */ }
1349};
1350MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
1351
1352#ifdef CONFIG_ACPI
1353static const struct acpi_device_id nxp_fspi_acpi_ids[] = {
1354 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, },
1355 {}
1356};
1357MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids);
1358#endif
1359
1360static struct platform_driver nxp_fspi_driver = {
1361 .driver = {
1362 .name = "nxp-fspi",
1363 .of_match_table = nxp_fspi_dt_ids,
1364 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids),
1365 .pm = pm_ptr(&nxp_fspi_pm_ops),
1366 },
1367 .probe = nxp_fspi_probe,
1368};
1369module_platform_driver(nxp_fspi_driver);
1370
1371MODULE_DESCRIPTION("NXP FSPI Controller Driver");
1372MODULE_AUTHOR("NXP Semiconductor");
1373MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
1374MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
1375MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
1376MODULE_LICENSE("GPL v2");
1377

source code of linux/drivers/spi/spi-nxp-fspi.c