1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Intel PXA25x and IXP4xx on-chip full speed USB device controllers |
4 | * |
5 | * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) |
6 | * Copyright (C) 2003 Robert Schwebel, Pengutronix |
7 | * Copyright (C) 2003 Benedikt Spranger, Pengutronix |
8 | * Copyright (C) 2003 David Brownell |
9 | * Copyright (C) 2003 Joshua Wise |
10 | */ |
11 | |
12 | /* #define VERBOSE_DEBUG */ |
13 | |
14 | #include <linux/device.h> |
15 | #include <linux/gpio.h> |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/ioport.h> |
19 | #include <linux/types.h> |
20 | #include <linux/errno.h> |
21 | #include <linux/err.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/slab.h> |
24 | #include <linux/timer.h> |
25 | #include <linux/list.h> |
26 | #include <linux/interrupt.h> |
27 | #include <linux/mm.h> |
28 | #include <linux/platform_data/pxa2xx_udc.h> |
29 | #include <linux/platform_device.h> |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/irq.h> |
32 | #include <linux/clk.h> |
33 | #include <linux/seq_file.h> |
34 | #include <linux/debugfs.h> |
35 | #include <linux/io.h> |
36 | #include <linux/prefetch.h> |
37 | |
38 | #include <asm/byteorder.h> |
39 | #include <asm/dma.h> |
40 | #include <asm/mach-types.h> |
41 | #include <asm/unaligned.h> |
42 | |
43 | #include <linux/usb/ch9.h> |
44 | #include <linux/usb/gadget.h> |
45 | #include <linux/usb/otg.h> |
46 | |
47 | #define UDCCR 0x0000 /* UDC Control Register */ |
48 | #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */ |
49 | #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */ |
50 | #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */ |
51 | #define UDCCS0 0x0010 /* UDC Endpoint 0 Control/Status Register */ |
52 | #define UDCCS1 0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */ |
53 | #define UDCCS2 0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */ |
54 | #define UDCCS3 0x001C /* UDC Endpoint 3 (IN) Control/Status Register */ |
55 | #define UDCCS4 0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */ |
56 | #define UDCCS5 0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ |
57 | #define UDCCS6 0x0028 /* UDC Endpoint 6 (IN) Control/Status Register */ |
58 | #define UDCCS7 0x002C /* UDC Endpoint 7 (OUT) Control/Status Register */ |
59 | #define UDCCS8 0x0030 /* UDC Endpoint 8 (IN) Control/Status Register */ |
60 | #define UDCCS9 0x0034 /* UDC Endpoint 9 (OUT) Control/Status Register */ |
61 | #define UDCCS10 0x0038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ |
62 | #define UDCCS11 0x003C /* UDC Endpoint 11 (IN) Control/Status Register */ |
63 | #define UDCCS12 0x0040 /* UDC Endpoint 12 (OUT) Control/Status Register */ |
64 | #define UDCCS13 0x0044 /* UDC Endpoint 13 (IN) Control/Status Register */ |
65 | #define UDCCS14 0x0048 /* UDC Endpoint 14 (OUT) Control/Status Register */ |
66 | #define UDCCS15 0x004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ |
67 | #define UFNRH 0x0060 /* UDC Frame Number Register High */ |
68 | #define UFNRL 0x0064 /* UDC Frame Number Register Low */ |
69 | #define UBCR2 0x0068 /* UDC Byte Count Reg 2 */ |
70 | #define UBCR4 0x006c /* UDC Byte Count Reg 4 */ |
71 | #define UBCR7 0x0070 /* UDC Byte Count Reg 7 */ |
72 | #define UBCR9 0x0074 /* UDC Byte Count Reg 9 */ |
73 | #define UBCR12 0x0078 /* UDC Byte Count Reg 12 */ |
74 | #define UBCR14 0x007c /* UDC Byte Count Reg 14 */ |
75 | #define UDDR0 0x0080 /* UDC Endpoint 0 Data Register */ |
76 | #define UDDR1 0x0100 /* UDC Endpoint 1 Data Register */ |
77 | #define UDDR2 0x0180 /* UDC Endpoint 2 Data Register */ |
78 | #define UDDR3 0x0200 /* UDC Endpoint 3 Data Register */ |
79 | #define UDDR4 0x0400 /* UDC Endpoint 4 Data Register */ |
80 | #define UDDR5 0x00A0 /* UDC Endpoint 5 Data Register */ |
81 | #define UDDR6 0x0600 /* UDC Endpoint 6 Data Register */ |
82 | #define UDDR7 0x0680 /* UDC Endpoint 7 Data Register */ |
83 | #define UDDR8 0x0700 /* UDC Endpoint 8 Data Register */ |
84 | #define UDDR9 0x0900 /* UDC Endpoint 9 Data Register */ |
85 | #define UDDR10 0x00C0 /* UDC Endpoint 10 Data Register */ |
86 | #define UDDR11 0x0B00 /* UDC Endpoint 11 Data Register */ |
87 | #define UDDR12 0x0B80 /* UDC Endpoint 12 Data Register */ |
88 | #define UDDR13 0x0C00 /* UDC Endpoint 13 Data Register */ |
89 | #define UDDR14 0x0E00 /* UDC Endpoint 14 Data Register */ |
90 | #define UDDR15 0x00E0 /* UDC Endpoint 15 Data Register */ |
91 | |
92 | #define UICR0 0x0050 /* UDC Interrupt Control Register 0 */ |
93 | #define UICR1 0x0054 /* UDC Interrupt Control Register 1 */ |
94 | |
95 | #define USIR0 0x0058 /* UDC Status Interrupt Register 0 */ |
96 | #define USIR1 0x005C /* UDC Status Interrupt Register 1 */ |
97 | |
98 | #define UDCCR_UDE (1 << 0) /* UDC enable */ |
99 | #define UDCCR_UDA (1 << 1) /* UDC active */ |
100 | #define UDCCR_RSM (1 << 2) /* Device resume */ |
101 | #define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ |
102 | #define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ |
103 | #define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ |
104 | #define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ |
105 | #define UDCCR_REM (1 << 7) /* Reset interrupt mask */ |
106 | |
107 | #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ |
108 | #define UDCCS0_IPR (1 << 1) /* IN packet ready */ |
109 | #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ |
110 | #define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ |
111 | #define UDCCS0_SST (1 << 4) /* Sent stall */ |
112 | #define UDCCS0_FST (1 << 5) /* Force stall */ |
113 | #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ |
114 | #define UDCCS0_SA (1 << 7) /* Setup active */ |
115 | |
116 | #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ |
117 | #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ |
118 | #define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ |
119 | #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ |
120 | #define UDCCS_BI_SST (1 << 4) /* Sent stall */ |
121 | #define UDCCS_BI_FST (1 << 5) /* Force stall */ |
122 | #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ |
123 | |
124 | #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ |
125 | #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ |
126 | #define UDCCS_BO_DME (1 << 3) /* DMA enable */ |
127 | #define UDCCS_BO_SST (1 << 4) /* Sent stall */ |
128 | #define UDCCS_BO_FST (1 << 5) /* Force stall */ |
129 | #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ |
130 | #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ |
131 | |
132 | #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ |
133 | #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ |
134 | #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ |
135 | #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ |
136 | #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ |
137 | |
138 | #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ |
139 | #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ |
140 | #ifdef CONFIG_ARCH_IXP4XX /* FIXME: is this right?, datasheed says '2' */ |
141 | #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ |
142 | #endif |
143 | #ifdef CONFIG_ARCH_PXA |
144 | #define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ |
145 | #endif |
146 | #define UDCCS_IO_DME (1 << 3) /* DMA enable */ |
147 | #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ |
148 | #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ |
149 | |
150 | #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ |
151 | #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ |
152 | #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ |
153 | #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ |
154 | #define UDCCS_INT_SST (1 << 4) /* Sent stall */ |
155 | #define UDCCS_INT_FST (1 << 5) /* Force stall */ |
156 | #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ |
157 | |
158 | #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ |
159 | #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ |
160 | #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ |
161 | #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ |
162 | #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ |
163 | #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ |
164 | #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ |
165 | #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ |
166 | |
167 | #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ |
168 | #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ |
169 | #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ |
170 | #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ |
171 | #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ |
172 | #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ |
173 | #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ |
174 | #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ |
175 | |
176 | #define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ |
177 | #define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ |
178 | #define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ |
179 | #define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ |
180 | #define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ |
181 | #define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ |
182 | #define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ |
183 | #define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ |
184 | |
185 | #define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ |
186 | #define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ |
187 | #define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ |
188 | #define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ |
189 | #define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ |
190 | #define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ |
191 | #define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ |
192 | #define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ |
193 | |
194 | /* |
195 | * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x |
196 | * series processors. The UDC for the IXP 4xx series is very similar. |
197 | * There are fifteen endpoints, in addition to ep0. |
198 | * |
199 | * Such controller drivers work with a gadget driver. The gadget driver |
200 | * returns descriptors, implements configuration and data protocols used |
201 | * by the host to interact with this device, and allocates endpoints to |
202 | * the different protocol interfaces. The controller driver virtualizes |
203 | * usb hardware so that the gadget drivers will be more portable. |
204 | * |
205 | * This UDC hardware wants to implement a bit too much USB protocol, so |
206 | * it constrains the sorts of USB configuration change events that work. |
207 | * The errata for these chips are misleading; some "fixed" bugs from |
208 | * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. |
209 | * |
210 | * Note that the UDC hardware supports DMA (except on IXP) but that's |
211 | * not used here. IN-DMA (to host) is simple enough, when the data is |
212 | * suitably aligned (16 bytes) ... the network stack doesn't do that, |
213 | * other software can. OUT-DMA is buggy in most chip versions, as well |
214 | * as poorly designed (data toggle not automatic). So this driver won't |
215 | * bother using DMA. (Mostly-working IN-DMA support was available in |
216 | * kernels before 2.6.23, but was never enabled or well tested.) |
217 | */ |
218 | |
219 | #define DRIVER_VERSION "30-June-2007" |
220 | #define DRIVER_DESC "PXA 25x USB Device Controller driver" |
221 | |
222 | |
223 | static const char driver_name [] = "pxa25x_udc" ; |
224 | |
225 | static const char ep0name [] = "ep0" ; |
226 | |
227 | |
228 | #ifdef CONFIG_ARCH_IXP4XX |
229 | |
230 | /* cpu-specific register addresses are compiled in to this code */ |
231 | #ifdef CONFIG_ARCH_PXA |
232 | #error "Can't configure both IXP and PXA" |
233 | #endif |
234 | |
235 | /* IXP doesn't yet support <linux/clk.h> */ |
236 | #define clk_get(dev,name) NULL |
237 | #define clk_enable(clk) do { } while (0) |
238 | #define clk_disable(clk) do { } while (0) |
239 | #define clk_put(clk) do { } while (0) |
240 | |
241 | #endif |
242 | |
243 | #include "pxa25x_udc.h" |
244 | |
245 | |
246 | #ifdef CONFIG_USB_PXA25X_SMALL |
247 | #define SIZE_STR " (small)" |
248 | #else |
249 | #define SIZE_STR "" |
250 | #endif |
251 | |
252 | /* --------------------------------------------------------------------------- |
253 | * endpoint related parts of the api to the usb controller hardware, |
254 | * used by gadget driver; and the inner talker-to-hardware core. |
255 | * --------------------------------------------------------------------------- |
256 | */ |
257 | |
258 | static void pxa25x_ep_fifo_flush (struct usb_ep *ep); |
259 | static void nuke (struct pxa25x_ep *, int status); |
260 | |
261 | /* one GPIO should control a D+ pullup, so host sees this device (or not) */ |
262 | static void pullup_off(void) |
263 | { |
264 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; |
265 | int off_level = mach->gpio_pullup_inverted; |
266 | |
267 | if (gpio_is_valid(number: mach->gpio_pullup)) |
268 | gpio_set_value(gpio: mach->gpio_pullup, value: off_level); |
269 | else if (mach->udc_command) |
270 | mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); |
271 | } |
272 | |
273 | static void pullup_on(void) |
274 | { |
275 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; |
276 | int on_level = !mach->gpio_pullup_inverted; |
277 | |
278 | if (gpio_is_valid(number: mach->gpio_pullup)) |
279 | gpio_set_value(gpio: mach->gpio_pullup, value: on_level); |
280 | else if (mach->udc_command) |
281 | mach->udc_command(PXA2XX_UDC_CMD_CONNECT); |
282 | } |
283 | |
284 | #if defined(CONFIG_CPU_BIG_ENDIAN) |
285 | /* |
286 | * IXP4xx has its buses wired up in a way that relies on never doing any |
287 | * byte swaps, independent of whether it runs in big-endian or little-endian |
288 | * mode, as explained by Krzysztof HaĆasa. |
289 | * |
290 | * We only support pxa25x in little-endian mode, but it is very likely |
291 | * that it works the same way. |
292 | */ |
293 | static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) |
294 | { |
295 | iowrite32be(val, dev->regs + reg); |
296 | } |
297 | |
298 | static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) |
299 | { |
300 | return ioread32be(dev->regs + reg); |
301 | } |
302 | #else |
303 | static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) |
304 | { |
305 | writel(val, addr: dev->regs + reg); |
306 | } |
307 | |
308 | static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) |
309 | { |
310 | return readl(addr: dev->regs + reg); |
311 | } |
312 | #endif |
313 | |
314 | static void pio_irq_enable(struct pxa25x_ep *ep) |
315 | { |
316 | u32 bEndpointAddress = ep->bEndpointAddress & 0xf; |
317 | |
318 | if (bEndpointAddress < 8) |
319 | udc_set_reg(dev: ep->dev, UICR0, val: udc_get_reg(dev: ep->dev, UICR0) & |
320 | ~(1 << bEndpointAddress)); |
321 | else { |
322 | bEndpointAddress -= 8; |
323 | udc_set_reg(dev: ep->dev, UICR1, val: udc_get_reg(dev: ep->dev, UICR1) & |
324 | ~(1 << bEndpointAddress)); |
325 | } |
326 | } |
327 | |
328 | static void pio_irq_disable(struct pxa25x_ep *ep) |
329 | { |
330 | u32 bEndpointAddress = ep->bEndpointAddress & 0xf; |
331 | |
332 | if (bEndpointAddress < 8) |
333 | udc_set_reg(dev: ep->dev, UICR0, val: udc_get_reg(dev: ep->dev, UICR0) | |
334 | (1 << bEndpointAddress)); |
335 | else { |
336 | bEndpointAddress -= 8; |
337 | udc_set_reg(dev: ep->dev, UICR1, val: udc_get_reg(dev: ep->dev, UICR1) | |
338 | (1 << bEndpointAddress)); |
339 | } |
340 | } |
341 | |
342 | /* The UDCCR reg contains mask and interrupt status bits, |
343 | * so using '|=' isn't safe as it may ack an interrupt. |
344 | */ |
345 | #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE) |
346 | |
347 | static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask) |
348 | { |
349 | u32 udccr = udc_get_reg(dev, UDCCR); |
350 | |
351 | udc_set_reg(dev, reg: (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR); |
352 | } |
353 | |
354 | static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask) |
355 | { |
356 | u32 udccr = udc_get_reg(dev, UDCCR); |
357 | |
358 | udc_set_reg(dev, reg: (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR); |
359 | } |
360 | |
361 | static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask) |
362 | { |
363 | /* udccr contains the bits we dont want to change */ |
364 | u32 udccr = udc_get_reg(dev, UDCCR) & UDCCR_MASK_BITS; |
365 | |
366 | udc_set_reg(dev, reg: udccr | (mask & ~UDCCR_MASK_BITS), UDCCR); |
367 | } |
368 | |
369 | static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *ep) |
370 | { |
371 | return udc_get_reg(dev: ep->dev, reg: ep->regoff_udccs); |
372 | } |
373 | |
374 | static inline void udc_ep_set_UDCCS(struct pxa25x_ep *ep, u32 data) |
375 | { |
376 | udc_set_reg(dev: ep->dev, reg: data, val: ep->regoff_udccs); |
377 | } |
378 | |
379 | static inline u32 udc_ep0_get_UDCCS(struct pxa25x_udc *dev) |
380 | { |
381 | return udc_get_reg(dev, UDCCS0); |
382 | } |
383 | |
384 | static inline void udc_ep0_set_UDCCS(struct pxa25x_udc *dev, u32 data) |
385 | { |
386 | udc_set_reg(dev, reg: data, UDCCS0); |
387 | } |
388 | |
389 | static inline u32 udc_ep_get_UDDR(struct pxa25x_ep *ep) |
390 | { |
391 | return udc_get_reg(dev: ep->dev, reg: ep->regoff_uddr); |
392 | } |
393 | |
394 | static inline void udc_ep_set_UDDR(struct pxa25x_ep *ep, u32 data) |
395 | { |
396 | udc_set_reg(dev: ep->dev, reg: data, val: ep->regoff_uddr); |
397 | } |
398 | |
399 | static inline u32 udc_ep_get_UBCR(struct pxa25x_ep *ep) |
400 | { |
401 | return udc_get_reg(dev: ep->dev, reg: ep->regoff_ubcr); |
402 | } |
403 | |
404 | /* |
405 | * endpoint enable/disable |
406 | * |
407 | * we need to verify the descriptors used to enable endpoints. since pxa25x |
408 | * endpoint configurations are fixed, and are pretty much always enabled, |
409 | * there's not a lot to manage here. |
410 | * |
411 | * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, |
412 | * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except |
413 | * for a single interface (with only the default altsetting) and for gadget |
414 | * drivers that don't halt endpoints (not reset by set_interface). that also |
415 | * means that if you use ISO, you must violate the USB spec rule that all |
416 | * iso endpoints must be in non-default altsettings. |
417 | */ |
418 | static int pxa25x_ep_enable (struct usb_ep *_ep, |
419 | const struct usb_endpoint_descriptor *desc) |
420 | { |
421 | struct pxa25x_ep *ep; |
422 | struct pxa25x_udc *dev; |
423 | |
424 | ep = container_of (_ep, struct pxa25x_ep, ep); |
425 | if (!_ep || !desc || _ep->name == ep0name |
426 | || desc->bDescriptorType != USB_DT_ENDPOINT |
427 | || ep->bEndpointAddress != desc->bEndpointAddress |
428 | || ep->fifo_size < usb_endpoint_maxp (epd: desc)) { |
429 | DMSG("%s, bad ep or descriptor\n" , __func__); |
430 | return -EINVAL; |
431 | } |
432 | |
433 | /* xfer types must match, except that interrupt ~= bulk */ |
434 | if (ep->bmAttributes != desc->bmAttributes |
435 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK |
436 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { |
437 | DMSG("%s, %s type mismatch\n" , __func__, _ep->name); |
438 | return -EINVAL; |
439 | } |
440 | |
441 | /* hardware _could_ do smaller, but driver doesn't */ |
442 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK |
443 | && usb_endpoint_maxp (epd: desc) |
444 | != BULK_FIFO_SIZE) |
445 | || !desc->wMaxPacketSize) { |
446 | DMSG("%s, bad %s maxpacket\n" , __func__, _ep->name); |
447 | return -ERANGE; |
448 | } |
449 | |
450 | dev = ep->dev; |
451 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { |
452 | DMSG("%s, bogus device state\n" , __func__); |
453 | return -ESHUTDOWN; |
454 | } |
455 | |
456 | ep->ep.desc = desc; |
457 | ep->stopped = 0; |
458 | ep->pio_irqs = 0; |
459 | ep->ep.maxpacket = usb_endpoint_maxp (epd: desc); |
460 | |
461 | /* flush fifo (mostly for OUT buffers) */ |
462 | pxa25x_ep_fifo_flush (ep: _ep); |
463 | |
464 | /* ... reset halt state too, if we could ... */ |
465 | |
466 | DBG(DBG_VERBOSE, "enabled %s\n" , _ep->name); |
467 | return 0; |
468 | } |
469 | |
470 | static int pxa25x_ep_disable (struct usb_ep *_ep) |
471 | { |
472 | struct pxa25x_ep *ep; |
473 | unsigned long flags; |
474 | |
475 | ep = container_of (_ep, struct pxa25x_ep, ep); |
476 | if (!_ep || !ep->ep.desc) { |
477 | DMSG("%s, %s not enabled\n" , __func__, |
478 | _ep ? ep->ep.name : NULL); |
479 | return -EINVAL; |
480 | } |
481 | local_irq_save(flags); |
482 | |
483 | nuke (ep, status: -ESHUTDOWN); |
484 | |
485 | /* flush fifo (mostly for IN buffers) */ |
486 | pxa25x_ep_fifo_flush (ep: _ep); |
487 | |
488 | ep->ep.desc = NULL; |
489 | ep->stopped = 1; |
490 | |
491 | local_irq_restore(flags); |
492 | DBG(DBG_VERBOSE, "%s disabled\n" , _ep->name); |
493 | return 0; |
494 | } |
495 | |
496 | /*-------------------------------------------------------------------------*/ |
497 | |
498 | /* for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers |
499 | * must still pass correctly initialized endpoints, since other controller |
500 | * drivers may care about how it's currently set up (dma issues etc). |
501 | */ |
502 | |
503 | /* |
504 | * pxa25x_ep_alloc_request - allocate a request data structure |
505 | */ |
506 | static struct usb_request * |
507 | pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) |
508 | { |
509 | struct pxa25x_request *req; |
510 | |
511 | req = kzalloc(size: sizeof(*req), flags: gfp_flags); |
512 | if (!req) |
513 | return NULL; |
514 | |
515 | INIT_LIST_HEAD (list: &req->queue); |
516 | return &req->req; |
517 | } |
518 | |
519 | |
520 | /* |
521 | * pxa25x_ep_free_request - deallocate a request data structure |
522 | */ |
523 | static void |
524 | pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) |
525 | { |
526 | struct pxa25x_request *req; |
527 | |
528 | req = container_of (_req, struct pxa25x_request, req); |
529 | WARN_ON(!list_empty (&req->queue)); |
530 | kfree(objp: req); |
531 | } |
532 | |
533 | /*-------------------------------------------------------------------------*/ |
534 | |
535 | /* |
536 | * done - retire a request; caller blocked irqs |
537 | */ |
538 | static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) |
539 | { |
540 | unsigned stopped = ep->stopped; |
541 | |
542 | list_del_init(entry: &req->queue); |
543 | |
544 | if (likely (req->req.status == -EINPROGRESS)) |
545 | req->req.status = status; |
546 | else |
547 | status = req->req.status; |
548 | |
549 | if (status && status != -ESHUTDOWN) |
550 | DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n" , |
551 | ep->ep.name, &req->req, status, |
552 | req->req.actual, req->req.length); |
553 | |
554 | /* don't modify queue heads during completion callback */ |
555 | ep->stopped = 1; |
556 | usb_gadget_giveback_request(ep: &ep->ep, req: &req->req); |
557 | ep->stopped = stopped; |
558 | } |
559 | |
560 | |
561 | static inline void ep0_idle (struct pxa25x_udc *dev) |
562 | { |
563 | dev->ep0state = EP0_IDLE; |
564 | } |
565 | |
566 | static int |
567 | write_packet(struct pxa25x_ep *ep, struct pxa25x_request *req, unsigned max) |
568 | { |
569 | u8 *buf; |
570 | unsigned length, count; |
571 | |
572 | buf = req->req.buf + req->req.actual; |
573 | prefetch(buf); |
574 | |
575 | /* how big will this packet be? */ |
576 | length = min(req->req.length - req->req.actual, max); |
577 | req->req.actual += length; |
578 | |
579 | count = length; |
580 | while (likely(count--)) |
581 | udc_ep_set_UDDR(ep, data: *buf++); |
582 | |
583 | return length; |
584 | } |
585 | |
586 | /* |
587 | * write to an IN endpoint fifo, as many packets as possible. |
588 | * irqs will use this to write the rest later. |
589 | * caller guarantees at least one packet buffer is ready (or a zlp). |
590 | */ |
591 | static int |
592 | write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
593 | { |
594 | unsigned max; |
595 | |
596 | max = usb_endpoint_maxp(epd: ep->ep.desc); |
597 | do { |
598 | unsigned count; |
599 | int is_last, is_short; |
600 | |
601 | count = write_packet(ep, req, max); |
602 | |
603 | /* last packet is usually short (or a zlp) */ |
604 | if (unlikely (count != max)) |
605 | is_last = is_short = 1; |
606 | else { |
607 | if (likely(req->req.length != req->req.actual) |
608 | || req->req.zero) |
609 | is_last = 0; |
610 | else |
611 | is_last = 1; |
612 | /* interrupt/iso maxpacket may not fill the fifo */ |
613 | is_short = unlikely (max < ep->fifo_size); |
614 | } |
615 | |
616 | DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n" , |
617 | ep->ep.name, count, |
618 | is_last ? "/L" : "" , is_short ? "/S" : "" , |
619 | req->req.length - req->req.actual, req); |
620 | |
621 | /* let loose that packet. maybe try writing another one, |
622 | * double buffering might work. TSP, TPC, and TFS |
623 | * bit values are the same for all normal IN endpoints. |
624 | */ |
625 | udc_ep_set_UDCCS(ep, UDCCS_BI_TPC); |
626 | if (is_short) |
627 | udc_ep_set_UDCCS(ep, UDCCS_BI_TSP); |
628 | |
629 | /* requests complete when all IN data is in the FIFO */ |
630 | if (is_last) { |
631 | done (ep, req, status: 0); |
632 | if (list_empty(head: &ep->queue)) |
633 | pio_irq_disable(ep); |
634 | return 1; |
635 | } |
636 | |
637 | // TODO experiment: how robust can fifo mode tweaking be? |
638 | // double buffering is off in the default fifo mode, which |
639 | // prevents TFS from being set here. |
640 | |
641 | } while (udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS); |
642 | return 0; |
643 | } |
644 | |
645 | /* caller asserts req->pending (ep0 irq status nyet cleared); starts |
646 | * ep0 data stage. these chips want very simple state transitions. |
647 | */ |
648 | static inline |
649 | void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) |
650 | { |
651 | udc_ep0_set_UDCCS(dev, data: flags|UDCCS0_SA|UDCCS0_OPR); |
652 | udc_set_reg(dev, USIR0, USIR0_IR0); |
653 | dev->req_pending = 0; |
654 | DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n" , |
655 | __func__, tag, udc_ep0_get_UDCCS(dev), flags); |
656 | } |
657 | |
658 | static int |
659 | write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
660 | { |
661 | struct pxa25x_udc *dev = ep->dev; |
662 | unsigned count; |
663 | int is_short; |
664 | |
665 | count = write_packet(ep: &dev->ep[0], req, EP0_FIFO_SIZE); |
666 | ep->dev->stats.write.bytes += count; |
667 | |
668 | /* last packet "must be" short (or a zlp) */ |
669 | is_short = (count != EP0_FIFO_SIZE); |
670 | |
671 | DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n" , count, |
672 | req->req.length - req->req.actual, req); |
673 | |
674 | if (unlikely (is_short)) { |
675 | if (ep->dev->req_pending) |
676 | ep0start(dev: ep->dev, UDCCS0_IPR, tag: "short IN" ); |
677 | else |
678 | udc_ep0_set_UDCCS(dev, UDCCS0_IPR); |
679 | |
680 | count = req->req.length; |
681 | done (ep, req, status: 0); |
682 | ep0_idle(dev: ep->dev); |
683 | #ifndef CONFIG_ARCH_IXP4XX |
684 | #if 1 |
685 | /* This seems to get rid of lost status irqs in some cases: |
686 | * host responds quickly, or next request involves config |
687 | * change automagic, or should have been hidden, or ... |
688 | * |
689 | * FIXME get rid of all udelays possible... |
690 | */ |
691 | if (count >= EP0_FIFO_SIZE) { |
692 | count = 100; |
693 | do { |
694 | if ((udc_ep0_get_UDCCS(dev) & UDCCS0_OPR) != 0) { |
695 | /* clear OPR, generate ack */ |
696 | udc_ep0_set_UDCCS(dev, UDCCS0_OPR); |
697 | break; |
698 | } |
699 | count--; |
700 | udelay(1); |
701 | } while (count); |
702 | } |
703 | #endif |
704 | #endif |
705 | } else if (ep->dev->req_pending) |
706 | ep0start(dev: ep->dev, flags: 0, tag: "IN" ); |
707 | return is_short; |
708 | } |
709 | |
710 | |
711 | /* |
712 | * read_fifo - unload packet(s) from the fifo we use for usb OUT |
713 | * transfers and put them into the request. caller should have made |
714 | * sure there's at least one packet ready. |
715 | * |
716 | * returns true if the request completed because of short packet or the |
717 | * request buffer having filled (and maybe overran till end-of-packet). |
718 | */ |
719 | static int |
720 | read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
721 | { |
722 | for (;;) { |
723 | u32 udccs; |
724 | u8 *buf; |
725 | unsigned bufferspace, count, is_short; |
726 | |
727 | /* make sure there's a packet in the FIFO. |
728 | * UDCCS_{BO,IO}_RPC are all the same bit value. |
729 | * UDCCS_{BO,IO}_RNE are all the same bit value. |
730 | */ |
731 | udccs = udc_ep_get_UDCCS(ep); |
732 | if (unlikely ((udccs & UDCCS_BO_RPC) == 0)) |
733 | break; |
734 | buf = req->req.buf + req->req.actual; |
735 | prefetchw(x: buf); |
736 | bufferspace = req->req.length - req->req.actual; |
737 | |
738 | /* read all bytes from this packet */ |
739 | if (likely (udccs & UDCCS_BO_RNE)) { |
740 | count = 1 + (0x0ff & udc_ep_get_UBCR(ep)); |
741 | req->req.actual += min (count, bufferspace); |
742 | } else /* zlp */ |
743 | count = 0; |
744 | is_short = (count < ep->ep.maxpacket); |
745 | DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n" , |
746 | ep->ep.name, udccs, count, |
747 | is_short ? "/S" : "" , |
748 | req, req->req.actual, req->req.length); |
749 | while (likely (count-- != 0)) { |
750 | u8 byte = (u8) udc_ep_get_UDDR(ep); |
751 | |
752 | if (unlikely (bufferspace == 0)) { |
753 | /* this happens when the driver's buffer |
754 | * is smaller than what the host sent. |
755 | * discard the extra data. |
756 | */ |
757 | if (req->req.status != -EOVERFLOW) |
758 | DMSG("%s overflow %d\n" , |
759 | ep->ep.name, count); |
760 | req->req.status = -EOVERFLOW; |
761 | } else { |
762 | *buf++ = byte; |
763 | bufferspace--; |
764 | } |
765 | } |
766 | udc_ep_set_UDCCS(ep, UDCCS_BO_RPC); |
767 | /* RPC/RSP/RNE could now reflect the other packet buffer */ |
768 | |
769 | /* iso is one request per packet */ |
770 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { |
771 | if (udccs & UDCCS_IO_ROF) |
772 | req->req.status = -EHOSTUNREACH; |
773 | /* more like "is_done" */ |
774 | is_short = 1; |
775 | } |
776 | |
777 | /* completion */ |
778 | if (is_short || req->req.actual == req->req.length) { |
779 | done (ep, req, status: 0); |
780 | if (list_empty(head: &ep->queue)) |
781 | pio_irq_disable(ep); |
782 | return 1; |
783 | } |
784 | |
785 | /* finished that packet. the next one may be waiting... */ |
786 | } |
787 | return 0; |
788 | } |
789 | |
790 | /* |
791 | * special ep0 version of the above. no UBCR0 or double buffering; status |
792 | * handshaking is magic. most device protocols don't need control-OUT. |
793 | * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other |
794 | * protocols do use them. |
795 | */ |
796 | static int |
797 | read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
798 | { |
799 | u8 *buf, byte; |
800 | unsigned bufferspace; |
801 | |
802 | buf = req->req.buf + req->req.actual; |
803 | bufferspace = req->req.length - req->req.actual; |
804 | |
805 | while (udc_ep_get_UDCCS(ep) & UDCCS0_RNE) { |
806 | byte = (u8) UDDR0; |
807 | |
808 | if (unlikely (bufferspace == 0)) { |
809 | /* this happens when the driver's buffer |
810 | * is smaller than what the host sent. |
811 | * discard the extra data. |
812 | */ |
813 | if (req->req.status != -EOVERFLOW) |
814 | DMSG("%s overflow\n" , ep->ep.name); |
815 | req->req.status = -EOVERFLOW; |
816 | } else { |
817 | *buf++ = byte; |
818 | req->req.actual++; |
819 | bufferspace--; |
820 | } |
821 | } |
822 | |
823 | udc_ep_set_UDCCS(ep, UDCCS0_OPR | UDCCS0_IPR); |
824 | |
825 | /* completion */ |
826 | if (req->req.actual >= req->req.length) |
827 | return 1; |
828 | |
829 | /* finished that packet. the next one may be waiting... */ |
830 | return 0; |
831 | } |
832 | |
833 | /*-------------------------------------------------------------------------*/ |
834 | |
835 | static int |
836 | pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
837 | { |
838 | struct pxa25x_request *req; |
839 | struct pxa25x_ep *ep; |
840 | struct pxa25x_udc *dev; |
841 | unsigned long flags; |
842 | |
843 | req = container_of(_req, struct pxa25x_request, req); |
844 | if (unlikely (!_req || !_req->complete || !_req->buf |
845 | || !list_empty(&req->queue))) { |
846 | DMSG("%s, bad params\n" , __func__); |
847 | return -EINVAL; |
848 | } |
849 | |
850 | ep = container_of(_ep, struct pxa25x_ep, ep); |
851 | if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) { |
852 | DMSG("%s, bad ep\n" , __func__); |
853 | return -EINVAL; |
854 | } |
855 | |
856 | dev = ep->dev; |
857 | if (unlikely (!dev->driver |
858 | || dev->gadget.speed == USB_SPEED_UNKNOWN)) { |
859 | DMSG("%s, bogus device state\n" , __func__); |
860 | return -ESHUTDOWN; |
861 | } |
862 | |
863 | /* iso is always one packet per request, that's the only way |
864 | * we can report per-packet status. that also helps with dma. |
865 | */ |
866 | if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC |
867 | && req->req.length > usb_endpoint_maxp(ep->ep.desc))) |
868 | return -EMSGSIZE; |
869 | |
870 | DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n" , |
871 | _ep->name, _req, _req->length, _req->buf); |
872 | |
873 | local_irq_save(flags); |
874 | |
875 | _req->status = -EINPROGRESS; |
876 | _req->actual = 0; |
877 | |
878 | /* kickstart this i/o queue? */ |
879 | if (list_empty(head: &ep->queue) && !ep->stopped) { |
880 | if (ep->ep.desc == NULL/* ep0 */) { |
881 | unsigned length = _req->length; |
882 | |
883 | switch (dev->ep0state) { |
884 | case EP0_IN_DATA_PHASE: |
885 | dev->stats.write.ops++; |
886 | if (write_ep0_fifo(ep, req)) |
887 | req = NULL; |
888 | break; |
889 | |
890 | case EP0_OUT_DATA_PHASE: |
891 | dev->stats.read.ops++; |
892 | /* messy ... */ |
893 | if (dev->req_config) { |
894 | DBG(DBG_VERBOSE, "ep0 config ack%s\n" , |
895 | dev->has_cfr ? "" : " raced" ); |
896 | if (dev->has_cfr) |
897 | udc_set_reg(dev, UDCCFR, UDCCFR_AREN | |
898 | UDCCFR_ACM | UDCCFR_MB1); |
899 | done(ep, req, status: 0); |
900 | dev->ep0state = EP0_END_XFER; |
901 | local_irq_restore (flags); |
902 | return 0; |
903 | } |
904 | if (dev->req_pending) |
905 | ep0start(dev, UDCCS0_IPR, tag: "OUT" ); |
906 | if (length == 0 || ((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0 |
907 | && read_ep0_fifo(ep, req))) { |
908 | ep0_idle(dev); |
909 | done(ep, req, status: 0); |
910 | req = NULL; |
911 | } |
912 | break; |
913 | |
914 | default: |
915 | DMSG("ep0 i/o, odd state %d\n" , dev->ep0state); |
916 | local_irq_restore (flags); |
917 | return -EL2HLT; |
918 | } |
919 | /* can the FIFO can satisfy the request immediately? */ |
920 | } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { |
921 | if ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) != 0 |
922 | && write_fifo(ep, req)) |
923 | req = NULL; |
924 | } else if ((udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) != 0 |
925 | && read_fifo(ep, req)) { |
926 | req = NULL; |
927 | } |
928 | |
929 | if (likely(req && ep->ep.desc)) |
930 | pio_irq_enable(ep); |
931 | } |
932 | |
933 | /* pio or dma irq handler advances the queue. */ |
934 | if (likely(req != NULL)) |
935 | list_add_tail(new: &req->queue, head: &ep->queue); |
936 | local_irq_restore(flags); |
937 | |
938 | return 0; |
939 | } |
940 | |
941 | |
942 | /* |
943 | * nuke - dequeue ALL requests |
944 | */ |
945 | static void nuke(struct pxa25x_ep *ep, int status) |
946 | { |
947 | struct pxa25x_request *req; |
948 | |
949 | /* called with irqs blocked */ |
950 | while (!list_empty(head: &ep->queue)) { |
951 | req = list_entry(ep->queue.next, |
952 | struct pxa25x_request, |
953 | queue); |
954 | done(ep, req, status); |
955 | } |
956 | if (ep->ep.desc) |
957 | pio_irq_disable(ep); |
958 | } |
959 | |
960 | |
961 | /* dequeue JUST ONE request */ |
962 | static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
963 | { |
964 | struct pxa25x_ep *ep; |
965 | struct pxa25x_request *req = NULL; |
966 | struct pxa25x_request *iter; |
967 | unsigned long flags; |
968 | |
969 | ep = container_of(_ep, struct pxa25x_ep, ep); |
970 | if (!_ep || ep->ep.name == ep0name) |
971 | return -EINVAL; |
972 | |
973 | local_irq_save(flags); |
974 | |
975 | /* make sure it's actually queued on this endpoint */ |
976 | list_for_each_entry(iter, &ep->queue, queue) { |
977 | if (&iter->req != _req) |
978 | continue; |
979 | req = iter; |
980 | break; |
981 | } |
982 | if (!req) { |
983 | local_irq_restore(flags); |
984 | return -EINVAL; |
985 | } |
986 | |
987 | done(ep, req, status: -ECONNRESET); |
988 | |
989 | local_irq_restore(flags); |
990 | return 0; |
991 | } |
992 | |
993 | /*-------------------------------------------------------------------------*/ |
994 | |
995 | static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) |
996 | { |
997 | struct pxa25x_ep *ep; |
998 | unsigned long flags; |
999 | |
1000 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1001 | if (unlikely (!_ep |
1002 | || (!ep->ep.desc && ep->ep.name != ep0name)) |
1003 | || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { |
1004 | DMSG("%s, bad ep\n" , __func__); |
1005 | return -EINVAL; |
1006 | } |
1007 | if (value == 0) { |
1008 | /* this path (reset toggle+halt) is needed to implement |
1009 | * SET_INTERFACE on normal hardware. but it can't be |
1010 | * done from software on the PXA UDC, and the hardware |
1011 | * forgets to do it as part of SET_INTERFACE automagic. |
1012 | */ |
1013 | DMSG("only host can clear %s halt\n" , _ep->name); |
1014 | return -EROFS; |
1015 | } |
1016 | |
1017 | local_irq_save(flags); |
1018 | |
1019 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0 |
1020 | && ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) == 0 |
1021 | || !list_empty(head: &ep->queue))) { |
1022 | local_irq_restore(flags); |
1023 | return -EAGAIN; |
1024 | } |
1025 | |
1026 | /* FST bit is the same for control, bulk in, bulk out, interrupt in */ |
1027 | udc_ep_set_UDCCS(ep, UDCCS_BI_FST|UDCCS_BI_FTF); |
1028 | |
1029 | /* ep0 needs special care */ |
1030 | if (!ep->ep.desc) { |
1031 | start_watchdog(ep->dev); |
1032 | ep->dev->req_pending = 0; |
1033 | ep->dev->ep0state = EP0_STALL; |
1034 | |
1035 | /* and bulk/intr endpoints like dropping stalls too */ |
1036 | } else { |
1037 | unsigned i; |
1038 | for (i = 0; i < 1000; i += 20) { |
1039 | if (udc_ep_get_UDCCS(ep) & UDCCS_BI_SST) |
1040 | break; |
1041 | udelay(20); |
1042 | } |
1043 | } |
1044 | local_irq_restore(flags); |
1045 | |
1046 | DBG(DBG_VERBOSE, "%s halt\n" , _ep->name); |
1047 | return 0; |
1048 | } |
1049 | |
1050 | static int pxa25x_ep_fifo_status(struct usb_ep *_ep) |
1051 | { |
1052 | struct pxa25x_ep *ep; |
1053 | |
1054 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1055 | if (!_ep) { |
1056 | DMSG("%s, bad ep\n" , __func__); |
1057 | return -ENODEV; |
1058 | } |
1059 | /* pxa can't report unclaimed bytes from IN fifos */ |
1060 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0) |
1061 | return -EOPNOTSUPP; |
1062 | if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN |
1063 | || (udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) == 0) |
1064 | return 0; |
1065 | else |
1066 | return (udc_ep_get_UBCR(ep) & 0xfff) + 1; |
1067 | } |
1068 | |
1069 | static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) |
1070 | { |
1071 | struct pxa25x_ep *ep; |
1072 | |
1073 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1074 | if (!_ep || ep->ep.name == ep0name || !list_empty(head: &ep->queue)) { |
1075 | DMSG("%s, bad ep\n" , __func__); |
1076 | return; |
1077 | } |
1078 | |
1079 | /* toggle and halt bits stay unchanged */ |
1080 | |
1081 | /* for OUT, just read and discard the FIFO contents. */ |
1082 | if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { |
1083 | while (((udc_ep_get_UDCCS(ep)) & UDCCS_BO_RNE) != 0) |
1084 | (void)udc_ep_get_UDDR(ep); |
1085 | return; |
1086 | } |
1087 | |
1088 | /* most IN status is the same, but ISO can't stall */ |
1089 | udc_ep_set_UDCCS(ep, UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR |
1090 | | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC |
1091 | ? 0 : UDCCS_BI_SST)); |
1092 | } |
1093 | |
1094 | |
1095 | static const struct usb_ep_ops pxa25x_ep_ops = { |
1096 | .enable = pxa25x_ep_enable, |
1097 | .disable = pxa25x_ep_disable, |
1098 | |
1099 | .alloc_request = pxa25x_ep_alloc_request, |
1100 | .free_request = pxa25x_ep_free_request, |
1101 | |
1102 | .queue = pxa25x_ep_queue, |
1103 | .dequeue = pxa25x_ep_dequeue, |
1104 | |
1105 | .set_halt = pxa25x_ep_set_halt, |
1106 | .fifo_status = pxa25x_ep_fifo_status, |
1107 | .fifo_flush = pxa25x_ep_fifo_flush, |
1108 | }; |
1109 | |
1110 | |
1111 | /* --------------------------------------------------------------------------- |
1112 | * device-scoped parts of the api to the usb controller hardware |
1113 | * --------------------------------------------------------------------------- |
1114 | */ |
1115 | |
1116 | static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) |
1117 | { |
1118 | struct pxa25x_udc *dev; |
1119 | |
1120 | dev = container_of(_gadget, struct pxa25x_udc, gadget); |
1121 | return ((udc_get_reg(dev, UFNRH) & 0x07) << 8) | |
1122 | (udc_get_reg(dev, UFNRL) & 0xff); |
1123 | } |
1124 | |
1125 | static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) |
1126 | { |
1127 | struct pxa25x_udc *udc; |
1128 | |
1129 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
1130 | |
1131 | /* host may not have enabled remote wakeup */ |
1132 | if ((udc_ep0_get_UDCCS(dev: udc) & UDCCS0_DRWF) == 0) |
1133 | return -EHOSTUNREACH; |
1134 | udc_set_mask_UDCCR(dev: udc, UDCCR_RSM); |
1135 | return 0; |
1136 | } |
1137 | |
1138 | static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); |
1139 | static void udc_enable (struct pxa25x_udc *); |
1140 | static void udc_disable(struct pxa25x_udc *); |
1141 | |
1142 | /* We disable the UDC -- and its 48 MHz clock -- whenever it's not |
1143 | * in active use. |
1144 | */ |
1145 | static int pullup(struct pxa25x_udc *udc) |
1146 | { |
1147 | int is_active = udc->vbus && udc->pullup && !udc->suspended; |
1148 | DMSG("%s\n" , is_active ? "active" : "inactive" ); |
1149 | if (is_active) { |
1150 | if (!udc->active) { |
1151 | udc->active = 1; |
1152 | /* Enable clock for USB device */ |
1153 | clk_enable(clk: udc->clk); |
1154 | udc_enable(udc); |
1155 | } |
1156 | } else { |
1157 | if (udc->active) { |
1158 | if (udc->gadget.speed != USB_SPEED_UNKNOWN) { |
1159 | DMSG("disconnect %s\n" , udc->driver |
1160 | ? udc->driver->driver.name |
1161 | : "(no driver)" ); |
1162 | stop_activity(udc, udc->driver); |
1163 | } |
1164 | udc_disable(udc); |
1165 | /* Disable clock for USB device */ |
1166 | clk_disable(clk: udc->clk); |
1167 | udc->active = 0; |
1168 | } |
1169 | |
1170 | } |
1171 | return 0; |
1172 | } |
1173 | |
1174 | /* VBUS reporting logically comes from a transceiver */ |
1175 | static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) |
1176 | { |
1177 | struct pxa25x_udc *udc; |
1178 | |
1179 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
1180 | udc->vbus = is_active; |
1181 | DMSG("vbus %s\n" , is_active ? "supplied" : "inactive" ); |
1182 | pullup(udc); |
1183 | return 0; |
1184 | } |
1185 | |
1186 | /* drivers may have software control over D+ pullup */ |
1187 | static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) |
1188 | { |
1189 | struct pxa25x_udc *udc; |
1190 | |
1191 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
1192 | |
1193 | /* not all boards support pullup control */ |
1194 | if (!gpio_is_valid(number: udc->mach->gpio_pullup) && !udc->mach->udc_command) |
1195 | return -EOPNOTSUPP; |
1196 | |
1197 | udc->pullup = (is_active != 0); |
1198 | pullup(udc); |
1199 | return 0; |
1200 | } |
1201 | |
1202 | /* boards may consume current from VBUS, up to 100-500mA based on config. |
1203 | * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs |
1204 | * violate USB specs. |
1205 | */ |
1206 | static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) |
1207 | { |
1208 | struct pxa25x_udc *udc; |
1209 | |
1210 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
1211 | |
1212 | if (!IS_ERR_OR_NULL(ptr: udc->transceiver)) |
1213 | return usb_phy_set_power(x: udc->transceiver, mA); |
1214 | return -EOPNOTSUPP; |
1215 | } |
1216 | |
1217 | static int pxa25x_udc_start(struct usb_gadget *g, |
1218 | struct usb_gadget_driver *driver); |
1219 | static int pxa25x_udc_stop(struct usb_gadget *g); |
1220 | |
1221 | static const struct usb_gadget_ops pxa25x_udc_ops = { |
1222 | .get_frame = pxa25x_udc_get_frame, |
1223 | .wakeup = pxa25x_udc_wakeup, |
1224 | .vbus_session = pxa25x_udc_vbus_session, |
1225 | .pullup = pxa25x_udc_pullup, |
1226 | .vbus_draw = pxa25x_udc_vbus_draw, |
1227 | .udc_start = pxa25x_udc_start, |
1228 | .udc_stop = pxa25x_udc_stop, |
1229 | }; |
1230 | |
1231 | /*-------------------------------------------------------------------------*/ |
1232 | |
1233 | #ifdef CONFIG_USB_GADGET_DEBUG_FS |
1234 | |
1235 | static int udc_debug_show(struct seq_file *m, void *_d) |
1236 | { |
1237 | struct pxa25x_udc *dev = m->private; |
1238 | unsigned long flags; |
1239 | int i; |
1240 | u32 tmp; |
1241 | |
1242 | local_irq_save(flags); |
1243 | |
1244 | /* basic device status */ |
1245 | seq_printf(m, DRIVER_DESC "\n" |
1246 | "%s version: %s\nGadget driver: %s\nHost %s\n\n" , |
1247 | driver_name, DRIVER_VERSION SIZE_STR "(pio)" , |
1248 | dev->driver ? dev->driver->driver.name : "(none)" , |
1249 | dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected" ); |
1250 | |
1251 | /* registers for device and ep0 */ |
1252 | seq_printf(m, |
1253 | fmt: "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n" , |
1254 | udc_get_reg(dev, UICR1), udc_get_reg(dev, UICR0), |
1255 | udc_get_reg(dev, USIR1), udc_get_reg(dev, USIR0), |
1256 | udc_get_reg(dev, UFNRH), udc_get_reg(dev, UFNRL)); |
1257 | |
1258 | tmp = udc_get_reg(dev, UDCCR); |
1259 | seq_printf(m, |
1260 | fmt: "udccr %02X =%s%s%s%s%s%s%s%s\n" , tmp, |
1261 | (tmp & UDCCR_REM) ? " rem" : "" , |
1262 | (tmp & UDCCR_RSTIR) ? " rstir" : "" , |
1263 | (tmp & UDCCR_SRM) ? " srm" : "" , |
1264 | (tmp & UDCCR_SUSIR) ? " susir" : "" , |
1265 | (tmp & UDCCR_RESIR) ? " resir" : "" , |
1266 | (tmp & UDCCR_RSM) ? " rsm" : "" , |
1267 | (tmp & UDCCR_UDA) ? " uda" : "" , |
1268 | (tmp & UDCCR_UDE) ? " ude" : "" ); |
1269 | |
1270 | tmp = udc_ep0_get_UDCCS(dev); |
1271 | seq_printf(m, |
1272 | fmt: "udccs0 %02X =%s%s%s%s%s%s%s%s\n" , tmp, |
1273 | (tmp & UDCCS0_SA) ? " sa" : "" , |
1274 | (tmp & UDCCS0_RNE) ? " rne" : "" , |
1275 | (tmp & UDCCS0_FST) ? " fst" : "" , |
1276 | (tmp & UDCCS0_SST) ? " sst" : "" , |
1277 | (tmp & UDCCS0_DRWF) ? " dwrf" : "" , |
1278 | (tmp & UDCCS0_FTF) ? " ftf" : "" , |
1279 | (tmp & UDCCS0_IPR) ? " ipr" : "" , |
1280 | (tmp & UDCCS0_OPR) ? " opr" : "" ); |
1281 | |
1282 | if (dev->has_cfr) { |
1283 | tmp = udc_get_reg(dev, UDCCFR); |
1284 | seq_printf(m, |
1285 | fmt: "udccfr %02X =%s%s\n" , tmp, |
1286 | (tmp & UDCCFR_AREN) ? " aren" : "" , |
1287 | (tmp & UDCCFR_ACM) ? " acm" : "" ); |
1288 | } |
1289 | |
1290 | if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver) |
1291 | goto done; |
1292 | |
1293 | seq_printf(m, fmt: "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n" , |
1294 | dev->stats.write.bytes, dev->stats.write.ops, |
1295 | dev->stats.read.bytes, dev->stats.read.ops, |
1296 | dev->stats.irqs); |
1297 | |
1298 | /* dump endpoint queues */ |
1299 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1300 | struct pxa25x_ep *ep = &dev->ep [i]; |
1301 | struct pxa25x_request *req; |
1302 | |
1303 | if (i != 0) { |
1304 | const struct usb_endpoint_descriptor *desc; |
1305 | |
1306 | desc = ep->ep.desc; |
1307 | if (!desc) |
1308 | continue; |
1309 | tmp = udc_ep_get_UDCCS(ep: &dev->ep[i]); |
1310 | seq_printf(m, |
1311 | fmt: "%s max %d %s udccs %02x irqs %lu\n" , |
1312 | ep->ep.name, usb_endpoint_maxp(epd: desc), |
1313 | "pio" , tmp, ep->pio_irqs); |
1314 | /* TODO translate all five groups of udccs bits! */ |
1315 | |
1316 | } else /* ep0 should only have one transfer queued */ |
1317 | seq_printf(m, fmt: "ep0 max 16 pio irqs %lu\n" , |
1318 | ep->pio_irqs); |
1319 | |
1320 | if (list_empty(head: &ep->queue)) { |
1321 | seq_printf(m, fmt: "\t(nothing queued)\n" ); |
1322 | continue; |
1323 | } |
1324 | list_for_each_entry(req, &ep->queue, queue) { |
1325 | seq_printf(m, |
1326 | fmt: "\treq %p len %d/%d buf %p\n" , |
1327 | &req->req, req->req.actual, |
1328 | req->req.length, req->req.buf); |
1329 | } |
1330 | } |
1331 | |
1332 | done: |
1333 | local_irq_restore(flags); |
1334 | return 0; |
1335 | } |
1336 | DEFINE_SHOW_ATTRIBUTE(udc_debug); |
1337 | |
1338 | #define create_debug_files(dev) \ |
1339 | do { \ |
1340 | debugfs_create_file(dev->gadget.name, \ |
1341 | S_IRUGO, NULL, dev, &udc_debug_fops); \ |
1342 | } while (0) |
1343 | #define remove_debug_files(dev) debugfs_lookup_and_remove(dev->gadget.name, NULL) |
1344 | |
1345 | #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ |
1346 | |
1347 | #define create_debug_files(dev) do {} while (0) |
1348 | #define remove_debug_files(dev) do {} while (0) |
1349 | |
1350 | #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ |
1351 | |
1352 | /*-------------------------------------------------------------------------*/ |
1353 | |
1354 | /* |
1355 | * udc_disable - disable USB device controller |
1356 | */ |
1357 | static void udc_disable(struct pxa25x_udc *dev) |
1358 | { |
1359 | /* block all irqs */ |
1360 | udc_set_mask_UDCCR(dev, UDCCR_SRM|UDCCR_REM); |
1361 | udc_set_reg(dev, UICR0, val: 0xff); |
1362 | udc_set_reg(dev, UICR1, val: 0xff); |
1363 | udc_set_reg(dev, UFNRH, UFNRH_SIM); |
1364 | |
1365 | /* if hardware supports it, disconnect from usb */ |
1366 | pullup_off(); |
1367 | |
1368 | udc_clear_mask_UDCCR(dev, UDCCR_UDE); |
1369 | |
1370 | ep0_idle (dev); |
1371 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
1372 | } |
1373 | |
1374 | |
1375 | /* |
1376 | * udc_reinit - initialize software state |
1377 | */ |
1378 | static void udc_reinit(struct pxa25x_udc *dev) |
1379 | { |
1380 | u32 i; |
1381 | |
1382 | /* device/ep0 records init */ |
1383 | INIT_LIST_HEAD (list: &dev->gadget.ep_list); |
1384 | INIT_LIST_HEAD (list: &dev->gadget.ep0->ep_list); |
1385 | dev->ep0state = EP0_IDLE; |
1386 | dev->gadget.quirk_altset_not_supp = 1; |
1387 | |
1388 | /* basic endpoint records init */ |
1389 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1390 | struct pxa25x_ep *ep = &dev->ep[i]; |
1391 | |
1392 | if (i != 0) |
1393 | list_add_tail (new: &ep->ep.ep_list, head: &dev->gadget.ep_list); |
1394 | |
1395 | ep->ep.desc = NULL; |
1396 | ep->stopped = 0; |
1397 | INIT_LIST_HEAD (list: &ep->queue); |
1398 | ep->pio_irqs = 0; |
1399 | usb_ep_set_maxpacket_limit(ep: &ep->ep, maxpacket_limit: ep->ep.maxpacket); |
1400 | } |
1401 | |
1402 | /* the rest was statically initialized, and is read-only */ |
1403 | } |
1404 | |
1405 | /* until it's enabled, this UDC should be completely invisible |
1406 | * to any USB host. |
1407 | */ |
1408 | static void udc_enable (struct pxa25x_udc *dev) |
1409 | { |
1410 | udc_clear_mask_UDCCR(dev, UDCCR_UDE); |
1411 | |
1412 | /* try to clear these bits before we enable the udc */ |
1413 | udc_ack_int_UDCCR(dev, UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); |
1414 | |
1415 | ep0_idle(dev); |
1416 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
1417 | dev->stats.irqs = 0; |
1418 | |
1419 | /* |
1420 | * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: |
1421 | * - enable UDC |
1422 | * - if RESET is already in progress, ack interrupt |
1423 | * - unmask reset interrupt |
1424 | */ |
1425 | udc_set_mask_UDCCR(dev, UDCCR_UDE); |
1426 | if (!(udc_get_reg(dev, UDCCR) & UDCCR_UDA)) |
1427 | udc_ack_int_UDCCR(dev, UDCCR_RSTIR); |
1428 | |
1429 | if (dev->has_cfr /* UDC_RES2 is defined */) { |
1430 | /* pxa255 (a0+) can avoid a set_config race that could |
1431 | * prevent gadget drivers from configuring correctly |
1432 | */ |
1433 | udc_set_reg(dev, UDCCFR, UDCCFR_ACM | UDCCFR_MB1); |
1434 | } else { |
1435 | /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1) |
1436 | * which could result in missing packets and interrupts. |
1437 | * supposedly one bit per endpoint, controlling whether it |
1438 | * double buffers or not; ACM/AREN bits fit into the holes. |
1439 | * zero bits (like USIR0_IRx) disable double buffering. |
1440 | */ |
1441 | udc_set_reg(dev, UDC_RES1, val: 0x00); |
1442 | udc_set_reg(dev, UDC_RES2, val: 0x00); |
1443 | } |
1444 | |
1445 | /* enable suspend/resume and reset irqs */ |
1446 | udc_clear_mask_UDCCR(dev, UDCCR_SRM | UDCCR_REM); |
1447 | |
1448 | /* enable ep0 irqs */ |
1449 | udc_set_reg(dev, UICR0, val: udc_get_reg(dev, UICR0) & ~UICR0_IM0); |
1450 | |
1451 | /* if hardware supports it, pullup D+ and wait for reset */ |
1452 | pullup_on(); |
1453 | } |
1454 | |
1455 | |
1456 | /* when a driver is successfully registered, it will receive |
1457 | * control requests including set_configuration(), which enables |
1458 | * non-control requests. then usb traffic follows until a |
1459 | * disconnect is reported. then a host may connect again, or |
1460 | * the driver might get unbound. |
1461 | */ |
1462 | static int pxa25x_udc_start(struct usb_gadget *g, |
1463 | struct usb_gadget_driver *driver) |
1464 | { |
1465 | struct pxa25x_udc *dev = to_pxa25x(g); |
1466 | int retval; |
1467 | |
1468 | /* first hook up the driver ... */ |
1469 | dev->driver = driver; |
1470 | dev->pullup = 1; |
1471 | |
1472 | /* ... then enable host detection and ep0; and we're ready |
1473 | * for set_configuration as well as eventual disconnect. |
1474 | */ |
1475 | /* connect to bus through transceiver */ |
1476 | if (!IS_ERR_OR_NULL(ptr: dev->transceiver)) { |
1477 | retval = otg_set_peripheral(otg: dev->transceiver->otg, |
1478 | periph: &dev->gadget); |
1479 | if (retval) |
1480 | goto bind_fail; |
1481 | } |
1482 | |
1483 | dump_state(dev); |
1484 | return 0; |
1485 | bind_fail: |
1486 | return retval; |
1487 | } |
1488 | |
1489 | static void |
1490 | reset_gadget(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) |
1491 | { |
1492 | int i; |
1493 | |
1494 | /* don't disconnect drivers more than once */ |
1495 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
1496 | driver = NULL; |
1497 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
1498 | |
1499 | /* prevent new request submissions, kill any outstanding requests */ |
1500 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1501 | struct pxa25x_ep *ep = &dev->ep[i]; |
1502 | |
1503 | ep->stopped = 1; |
1504 | nuke(ep, status: -ESHUTDOWN); |
1505 | } |
1506 | del_timer_sync(timer: &dev->timer); |
1507 | |
1508 | /* report reset; the driver is already quiesced */ |
1509 | if (driver) |
1510 | usb_gadget_udc_reset(gadget: &dev->gadget, driver); |
1511 | |
1512 | /* re-init driver-visible data structures */ |
1513 | udc_reinit(dev); |
1514 | } |
1515 | |
1516 | static void |
1517 | stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) |
1518 | { |
1519 | int i; |
1520 | |
1521 | /* don't disconnect drivers more than once */ |
1522 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) |
1523 | driver = NULL; |
1524 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
1525 | |
1526 | /* prevent new request submissions, kill any outstanding requests */ |
1527 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1528 | struct pxa25x_ep *ep = &dev->ep[i]; |
1529 | |
1530 | ep->stopped = 1; |
1531 | nuke(ep, status: -ESHUTDOWN); |
1532 | } |
1533 | del_timer_sync(timer: &dev->timer); |
1534 | |
1535 | /* report disconnect; the driver is already quiesced */ |
1536 | if (driver) |
1537 | driver->disconnect(&dev->gadget); |
1538 | |
1539 | /* re-init driver-visible data structures */ |
1540 | udc_reinit(dev); |
1541 | } |
1542 | |
1543 | static int pxa25x_udc_stop(struct usb_gadget*g) |
1544 | { |
1545 | struct pxa25x_udc *dev = to_pxa25x(g); |
1546 | |
1547 | local_irq_disable(); |
1548 | dev->pullup = 0; |
1549 | stop_activity(dev, NULL); |
1550 | local_irq_enable(); |
1551 | |
1552 | if (!IS_ERR_OR_NULL(ptr: dev->transceiver)) |
1553 | (void) otg_set_peripheral(otg: dev->transceiver->otg, NULL); |
1554 | |
1555 | dev->driver = NULL; |
1556 | |
1557 | dump_state(dev); |
1558 | |
1559 | return 0; |
1560 | } |
1561 | |
1562 | /*-------------------------------------------------------------------------*/ |
1563 | |
1564 | static inline void clear_ep_state (struct pxa25x_udc *dev) |
1565 | { |
1566 | unsigned i; |
1567 | |
1568 | /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint |
1569 | * fifos, and pending transactions mustn't be continued in any case. |
1570 | */ |
1571 | for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) |
1572 | nuke(ep: &dev->ep[i], status: -ECONNABORTED); |
1573 | } |
1574 | |
1575 | static void udc_watchdog(struct timer_list *t) |
1576 | { |
1577 | struct pxa25x_udc *dev = from_timer(dev, t, timer); |
1578 | |
1579 | local_irq_disable(); |
1580 | if (dev->ep0state == EP0_STALL |
1581 | && (udc_ep0_get_UDCCS(dev) & UDCCS0_FST) == 0 |
1582 | && (udc_ep0_get_UDCCS(dev) & UDCCS0_SST) == 0) { |
1583 | udc_ep0_set_UDCCS(dev, UDCCS0_FST|UDCCS0_FTF); |
1584 | DBG(DBG_VERBOSE, "ep0 re-stall\n" ); |
1585 | start_watchdog(dev); |
1586 | } |
1587 | local_irq_enable(); |
1588 | } |
1589 | |
1590 | static void handle_ep0 (struct pxa25x_udc *dev) |
1591 | { |
1592 | u32 udccs0 = udc_ep0_get_UDCCS(dev); |
1593 | struct pxa25x_ep *ep = &dev->ep [0]; |
1594 | struct pxa25x_request *req; |
1595 | union { |
1596 | struct usb_ctrlrequest r; |
1597 | u8 raw [8]; |
1598 | u32 word [2]; |
1599 | } u; |
1600 | |
1601 | if (list_empty(head: &ep->queue)) |
1602 | req = NULL; |
1603 | else |
1604 | req = list_entry(ep->queue.next, struct pxa25x_request, queue); |
1605 | |
1606 | /* clear stall status */ |
1607 | if (udccs0 & UDCCS0_SST) { |
1608 | nuke(ep, status: -EPIPE); |
1609 | udc_ep0_set_UDCCS(dev, UDCCS0_SST); |
1610 | del_timer(timer: &dev->timer); |
1611 | ep0_idle(dev); |
1612 | } |
1613 | |
1614 | /* previous request unfinished? non-error iff back-to-back ... */ |
1615 | if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { |
1616 | nuke(ep, status: 0); |
1617 | del_timer(timer: &dev->timer); |
1618 | ep0_idle(dev); |
1619 | } |
1620 | |
1621 | switch (dev->ep0state) { |
1622 | case EP0_IDLE: |
1623 | /* late-breaking status? */ |
1624 | udccs0 = udc_ep0_get_UDCCS(dev); |
1625 | |
1626 | /* start control request? */ |
1627 | if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) |
1628 | == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { |
1629 | int i; |
1630 | |
1631 | nuke (ep, status: -EPROTO); |
1632 | |
1633 | /* read SETUP packet */ |
1634 | for (i = 0; i < 8; i++) { |
1635 | if (unlikely(!(udc_ep0_get_UDCCS(dev) & UDCCS0_RNE))) { |
1636 | bad_setup: |
1637 | DMSG("SETUP %d!\n" , i); |
1638 | goto stall; |
1639 | } |
1640 | u.raw [i] = (u8) UDDR0; |
1641 | } |
1642 | if (unlikely((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0)) |
1643 | goto bad_setup; |
1644 | |
1645 | got_setup: |
1646 | DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n" , |
1647 | u.r.bRequestType, u.r.bRequest, |
1648 | le16_to_cpu(u.r.wValue), |
1649 | le16_to_cpu(u.r.wIndex), |
1650 | le16_to_cpu(u.r.wLength)); |
1651 | |
1652 | /* cope with automagic for some standard requests. */ |
1653 | dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) |
1654 | == USB_TYPE_STANDARD; |
1655 | dev->req_config = 0; |
1656 | dev->req_pending = 1; |
1657 | switch (u.r.bRequest) { |
1658 | /* hardware restricts gadget drivers here! */ |
1659 | case USB_REQ_SET_CONFIGURATION: |
1660 | if (u.r.bRequestType == USB_RECIP_DEVICE) { |
1661 | /* reflect hardware's automagic |
1662 | * up to the gadget driver. |
1663 | */ |
1664 | config_change: |
1665 | dev->req_config = 1; |
1666 | clear_ep_state(dev); |
1667 | /* if !has_cfr, there's no synch |
1668 | * else use AREN (later) not SA|OPR |
1669 | * USIR0_IR0 acts edge sensitive |
1670 | */ |
1671 | } |
1672 | break; |
1673 | /* ... and here, even more ... */ |
1674 | case USB_REQ_SET_INTERFACE: |
1675 | if (u.r.bRequestType == USB_RECIP_INTERFACE) { |
1676 | /* udc hardware is broken by design: |
1677 | * - altsetting may only be zero; |
1678 | * - hw resets all interfaces' eps; |
1679 | * - ep reset doesn't include halt(?). |
1680 | */ |
1681 | DMSG("broken set_interface (%d/%d)\n" , |
1682 | le16_to_cpu(u.r.wIndex), |
1683 | le16_to_cpu(u.r.wValue)); |
1684 | goto config_change; |
1685 | } |
1686 | break; |
1687 | /* hardware was supposed to hide this */ |
1688 | case USB_REQ_SET_ADDRESS: |
1689 | if (u.r.bRequestType == USB_RECIP_DEVICE) { |
1690 | ep0start(dev, flags: 0, tag: "address" ); |
1691 | return; |
1692 | } |
1693 | break; |
1694 | } |
1695 | |
1696 | if (u.r.bRequestType & USB_DIR_IN) |
1697 | dev->ep0state = EP0_IN_DATA_PHASE; |
1698 | else |
1699 | dev->ep0state = EP0_OUT_DATA_PHASE; |
1700 | |
1701 | i = dev->driver->setup(&dev->gadget, &u.r); |
1702 | if (i < 0) { |
1703 | /* hardware automagic preventing STALL... */ |
1704 | if (dev->req_config) { |
1705 | /* hardware sometimes neglects to tell |
1706 | * tell us about config change events, |
1707 | * so later ones may fail... |
1708 | */ |
1709 | WARNING("config change %02x fail %d?\n" , |
1710 | u.r.bRequest, i); |
1711 | return; |
1712 | /* TODO experiment: if has_cfr, |
1713 | * hardware didn't ACK; maybe we |
1714 | * could actually STALL! |
1715 | */ |
1716 | } |
1717 | DBG(DBG_VERBOSE, "protocol STALL, " |
1718 | "%02x err %d\n" , udc_ep0_get_UDCCS(dev), i); |
1719 | stall: |
1720 | /* the watchdog timer helps deal with cases |
1721 | * where udc seems to clear FST wrongly, and |
1722 | * then NAKs instead of STALLing. |
1723 | */ |
1724 | ep0start(dev, UDCCS0_FST|UDCCS0_FTF, tag: "stall" ); |
1725 | start_watchdog(dev); |
1726 | dev->ep0state = EP0_STALL; |
1727 | |
1728 | /* deferred i/o == no response yet */ |
1729 | } else if (dev->req_pending) { |
1730 | if (likely(dev->ep0state == EP0_IN_DATA_PHASE |
1731 | || dev->req_std || u.r.wLength)) |
1732 | ep0start(dev, flags: 0, tag: "defer" ); |
1733 | else |
1734 | ep0start(dev, UDCCS0_IPR, tag: "defer/IPR" ); |
1735 | } |
1736 | |
1737 | /* expect at least one data or status stage irq */ |
1738 | return; |
1739 | |
1740 | } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) |
1741 | == (UDCCS0_OPR|UDCCS0_SA))) { |
1742 | unsigned i; |
1743 | |
1744 | /* pxa210/250 erratum 131 for B0/B1 says RNE lies. |
1745 | * still observed on a pxa255 a0. |
1746 | */ |
1747 | DBG(DBG_VERBOSE, "e131\n" ); |
1748 | nuke(ep, status: -EPROTO); |
1749 | |
1750 | /* read SETUP data, but don't trust it too much */ |
1751 | for (i = 0; i < 8; i++) |
1752 | u.raw [i] = (u8) UDDR0; |
1753 | if ((u.r.bRequestType & USB_RECIP_MASK) |
1754 | > USB_RECIP_OTHER) |
1755 | goto stall; |
1756 | if (u.word [0] == 0 && u.word [1] == 0) |
1757 | goto stall; |
1758 | goto got_setup; |
1759 | } else { |
1760 | /* some random early IRQ: |
1761 | * - we acked FST |
1762 | * - IPR cleared |
1763 | * - OPR got set, without SA (likely status stage) |
1764 | */ |
1765 | udc_ep0_set_UDCCS(dev, data: udccs0 & (UDCCS0_SA|UDCCS0_OPR)); |
1766 | } |
1767 | break; |
1768 | case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ |
1769 | if (udccs0 & UDCCS0_OPR) { |
1770 | udc_ep0_set_UDCCS(dev, UDCCS0_OPR|UDCCS0_FTF); |
1771 | DBG(DBG_VERBOSE, "ep0in premature status\n" ); |
1772 | if (req) |
1773 | done(ep, req, status: 0); |
1774 | ep0_idle(dev); |
1775 | } else /* irq was IPR clearing */ { |
1776 | if (req) { |
1777 | /* this IN packet might finish the request */ |
1778 | (void) write_ep0_fifo(ep, req); |
1779 | } /* else IN token before response was written */ |
1780 | } |
1781 | break; |
1782 | case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ |
1783 | if (udccs0 & UDCCS0_OPR) { |
1784 | if (req) { |
1785 | /* this OUT packet might finish the request */ |
1786 | if (read_ep0_fifo(ep, req)) |
1787 | done(ep, req, status: 0); |
1788 | /* else more OUT packets expected */ |
1789 | } /* else OUT token before read was issued */ |
1790 | } else /* irq was IPR clearing */ { |
1791 | DBG(DBG_VERBOSE, "ep0out premature status\n" ); |
1792 | if (req) |
1793 | done(ep, req, status: 0); |
1794 | ep0_idle(dev); |
1795 | } |
1796 | break; |
1797 | case EP0_END_XFER: |
1798 | if (req) |
1799 | done(ep, req, status: 0); |
1800 | /* ack control-IN status (maybe in-zlp was skipped) |
1801 | * also appears after some config change events. |
1802 | */ |
1803 | if (udccs0 & UDCCS0_OPR) |
1804 | udc_ep0_set_UDCCS(dev, UDCCS0_OPR); |
1805 | ep0_idle(dev); |
1806 | break; |
1807 | case EP0_STALL: |
1808 | udc_ep0_set_UDCCS(dev, UDCCS0_FST); |
1809 | break; |
1810 | } |
1811 | udc_set_reg(dev, USIR0, USIR0_IR0); |
1812 | } |
1813 | |
1814 | static void handle_ep(struct pxa25x_ep *ep) |
1815 | { |
1816 | struct pxa25x_request *req; |
1817 | int is_in = ep->bEndpointAddress & USB_DIR_IN; |
1818 | int completed; |
1819 | u32 udccs, tmp; |
1820 | |
1821 | do { |
1822 | completed = 0; |
1823 | if (likely (!list_empty(&ep->queue))) |
1824 | req = list_entry(ep->queue.next, |
1825 | struct pxa25x_request, queue); |
1826 | else |
1827 | req = NULL; |
1828 | |
1829 | // TODO check FST handling |
1830 | |
1831 | udccs = udc_ep_get_UDCCS(ep); |
1832 | if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ |
1833 | tmp = UDCCS_BI_TUR; |
1834 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) |
1835 | tmp |= UDCCS_BI_SST; |
1836 | tmp &= udccs; |
1837 | if (likely (tmp)) |
1838 | udc_ep_set_UDCCS(ep, data: tmp); |
1839 | if (req && likely ((udccs & UDCCS_BI_TFS) != 0)) |
1840 | completed = write_fifo(ep, req); |
1841 | |
1842 | } else { /* irq from RPC (or for ISO, ROF) */ |
1843 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) |
1844 | tmp = UDCCS_BO_SST | UDCCS_BO_DME; |
1845 | else |
1846 | tmp = UDCCS_IO_ROF | UDCCS_IO_DME; |
1847 | tmp &= udccs; |
1848 | if (likely(tmp)) |
1849 | udc_ep_set_UDCCS(ep, data: tmp); |
1850 | |
1851 | /* fifos can hold packets, ready for reading... */ |
1852 | if (likely(req)) { |
1853 | completed = read_fifo(ep, req); |
1854 | } else |
1855 | pio_irq_disable(ep); |
1856 | } |
1857 | ep->pio_irqs++; |
1858 | } while (completed); |
1859 | } |
1860 | |
1861 | /* |
1862 | * pxa25x_udc_irq - interrupt handler |
1863 | * |
1864 | * avoid delays in ep0 processing. the control handshaking isn't always |
1865 | * under software control (pxa250c0 and the pxa255 are better), and delays |
1866 | * could cause usb protocol errors. |
1867 | */ |
1868 | static irqreturn_t |
1869 | pxa25x_udc_irq(int irq, void *_dev) |
1870 | { |
1871 | struct pxa25x_udc *dev = _dev; |
1872 | int handled; |
1873 | |
1874 | dev->stats.irqs++; |
1875 | do { |
1876 | u32 udccr = udc_get_reg(dev, UDCCR); |
1877 | |
1878 | handled = 0; |
1879 | |
1880 | /* SUSpend Interrupt Request */ |
1881 | if (unlikely(udccr & UDCCR_SUSIR)) { |
1882 | udc_ack_int_UDCCR(dev, UDCCR_SUSIR); |
1883 | handled = 1; |
1884 | DBG(DBG_VERBOSE, "USB suspend\n" ); |
1885 | |
1886 | if (dev->gadget.speed != USB_SPEED_UNKNOWN |
1887 | && dev->driver |
1888 | && dev->driver->suspend) |
1889 | dev->driver->suspend(&dev->gadget); |
1890 | ep0_idle (dev); |
1891 | } |
1892 | |
1893 | /* RESume Interrupt Request */ |
1894 | if (unlikely(udccr & UDCCR_RESIR)) { |
1895 | udc_ack_int_UDCCR(dev, UDCCR_RESIR); |
1896 | handled = 1; |
1897 | DBG(DBG_VERBOSE, "USB resume\n" ); |
1898 | |
1899 | if (dev->gadget.speed != USB_SPEED_UNKNOWN |
1900 | && dev->driver |
1901 | && dev->driver->resume) |
1902 | dev->driver->resume(&dev->gadget); |
1903 | } |
1904 | |
1905 | /* ReSeT Interrupt Request - USB reset */ |
1906 | if (unlikely(udccr & UDCCR_RSTIR)) { |
1907 | udc_ack_int_UDCCR(dev, UDCCR_RSTIR); |
1908 | handled = 1; |
1909 | |
1910 | if ((udc_get_reg(dev, UDCCR) & UDCCR_UDA) == 0) { |
1911 | DBG(DBG_VERBOSE, "USB reset start\n" ); |
1912 | |
1913 | /* reset driver and endpoints, |
1914 | * in case that's not yet done |
1915 | */ |
1916 | reset_gadget(dev, driver: dev->driver); |
1917 | |
1918 | } else { |
1919 | DBG(DBG_VERBOSE, "USB reset end\n" ); |
1920 | dev->gadget.speed = USB_SPEED_FULL; |
1921 | memset(&dev->stats, 0, sizeof dev->stats); |
1922 | /* driver and endpoints are still reset */ |
1923 | } |
1924 | |
1925 | } else { |
1926 | u32 usir0 = udc_get_reg(dev, USIR0) & |
1927 | ~udc_get_reg(dev, UICR0); |
1928 | u32 usir1 = udc_get_reg(dev, USIR1) & |
1929 | ~udc_get_reg(dev, UICR1); |
1930 | int i; |
1931 | |
1932 | if (unlikely (!usir0 && !usir1)) |
1933 | continue; |
1934 | |
1935 | DBG(DBG_VERY_NOISY, "irq %02x.%02x\n" , usir1, usir0); |
1936 | |
1937 | /* control traffic */ |
1938 | if (usir0 & USIR0_IR0) { |
1939 | dev->ep[0].pio_irqs++; |
1940 | handle_ep0(dev); |
1941 | handled = 1; |
1942 | } |
1943 | |
1944 | /* endpoint data transfers */ |
1945 | for (i = 0; i < 8; i++) { |
1946 | u32 tmp = 1 << i; |
1947 | |
1948 | if (i && (usir0 & tmp)) { |
1949 | handle_ep(ep: &dev->ep[i]); |
1950 | udc_set_reg(dev, USIR0, |
1951 | val: udc_get_reg(dev, USIR0) | tmp); |
1952 | handled = 1; |
1953 | } |
1954 | #ifndef CONFIG_USB_PXA25X_SMALL |
1955 | if (usir1 & tmp) { |
1956 | handle_ep(ep: &dev->ep[i+8]); |
1957 | udc_set_reg(dev, USIR1, |
1958 | val: udc_get_reg(dev, USIR1) | tmp); |
1959 | handled = 1; |
1960 | } |
1961 | #endif |
1962 | } |
1963 | } |
1964 | |
1965 | /* we could also ask for 1 msec SOF (SIR) interrupts */ |
1966 | |
1967 | } while (handled); |
1968 | return IRQ_HANDLED; |
1969 | } |
1970 | |
1971 | /*-------------------------------------------------------------------------*/ |
1972 | |
1973 | static void nop_release (struct device *dev) |
1974 | { |
1975 | DMSG("%s %s\n" , __func__, dev_name(dev)); |
1976 | } |
1977 | |
1978 | /* this uses load-time allocation and initialization (instead of |
1979 | * doing it at run-time) to save code, eliminate fault paths, and |
1980 | * be more obviously correct. |
1981 | */ |
1982 | static struct pxa25x_udc memory = { |
1983 | .gadget = { |
1984 | .ops = &pxa25x_udc_ops, |
1985 | .ep0 = &memory.ep[0].ep, |
1986 | .name = driver_name, |
1987 | .dev = { |
1988 | .init_name = "gadget" , |
1989 | .release = nop_release, |
1990 | }, |
1991 | }, |
1992 | |
1993 | /* control endpoint */ |
1994 | .ep[0] = { |
1995 | .ep = { |
1996 | .name = ep0name, |
1997 | .ops = &pxa25x_ep_ops, |
1998 | .maxpacket = EP0_FIFO_SIZE, |
1999 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, |
2000 | USB_EP_CAPS_DIR_ALL), |
2001 | }, |
2002 | .dev = &memory, |
2003 | .regoff_udccs = UDCCS0, |
2004 | .regoff_uddr = UDDR0, |
2005 | }, |
2006 | |
2007 | /* first group of endpoints */ |
2008 | .ep[1] = { |
2009 | .ep = { |
2010 | .name = "ep1in-bulk" , |
2011 | .ops = &pxa25x_ep_ops, |
2012 | .maxpacket = BULK_FIFO_SIZE, |
2013 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2014 | USB_EP_CAPS_DIR_IN), |
2015 | }, |
2016 | .dev = &memory, |
2017 | .fifo_size = BULK_FIFO_SIZE, |
2018 | .bEndpointAddress = USB_DIR_IN | 1, |
2019 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2020 | .regoff_udccs = UDCCS1, |
2021 | .regoff_uddr = UDDR1, |
2022 | }, |
2023 | .ep[2] = { |
2024 | .ep = { |
2025 | .name = "ep2out-bulk" , |
2026 | .ops = &pxa25x_ep_ops, |
2027 | .maxpacket = BULK_FIFO_SIZE, |
2028 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2029 | USB_EP_CAPS_DIR_OUT), |
2030 | }, |
2031 | .dev = &memory, |
2032 | .fifo_size = BULK_FIFO_SIZE, |
2033 | .bEndpointAddress = 2, |
2034 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2035 | .regoff_udccs = UDCCS2, |
2036 | .regoff_ubcr = UBCR2, |
2037 | .regoff_uddr = UDDR2, |
2038 | }, |
2039 | #ifndef CONFIG_USB_PXA25X_SMALL |
2040 | .ep[3] = { |
2041 | .ep = { |
2042 | .name = "ep3in-iso" , |
2043 | .ops = &pxa25x_ep_ops, |
2044 | .maxpacket = ISO_FIFO_SIZE, |
2045 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2046 | USB_EP_CAPS_DIR_IN), |
2047 | }, |
2048 | .dev = &memory, |
2049 | .fifo_size = ISO_FIFO_SIZE, |
2050 | .bEndpointAddress = USB_DIR_IN | 3, |
2051 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2052 | .regoff_udccs = UDCCS3, |
2053 | .regoff_uddr = UDDR3, |
2054 | }, |
2055 | .ep[4] = { |
2056 | .ep = { |
2057 | .name = "ep4out-iso" , |
2058 | .ops = &pxa25x_ep_ops, |
2059 | .maxpacket = ISO_FIFO_SIZE, |
2060 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2061 | USB_EP_CAPS_DIR_OUT), |
2062 | }, |
2063 | .dev = &memory, |
2064 | .fifo_size = ISO_FIFO_SIZE, |
2065 | .bEndpointAddress = 4, |
2066 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2067 | .regoff_udccs = UDCCS4, |
2068 | .regoff_ubcr = UBCR4, |
2069 | .regoff_uddr = UDDR4, |
2070 | }, |
2071 | .ep[5] = { |
2072 | .ep = { |
2073 | .name = "ep5in-int" , |
2074 | .ops = &pxa25x_ep_ops, |
2075 | .maxpacket = INT_FIFO_SIZE, |
2076 | .caps = USB_EP_CAPS(0, 0), |
2077 | }, |
2078 | .dev = &memory, |
2079 | .fifo_size = INT_FIFO_SIZE, |
2080 | .bEndpointAddress = USB_DIR_IN | 5, |
2081 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2082 | .regoff_udccs = UDCCS5, |
2083 | .regoff_uddr = UDDR5, |
2084 | }, |
2085 | |
2086 | /* second group of endpoints */ |
2087 | .ep[6] = { |
2088 | .ep = { |
2089 | .name = "ep6in-bulk" , |
2090 | .ops = &pxa25x_ep_ops, |
2091 | .maxpacket = BULK_FIFO_SIZE, |
2092 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2093 | USB_EP_CAPS_DIR_IN), |
2094 | }, |
2095 | .dev = &memory, |
2096 | .fifo_size = BULK_FIFO_SIZE, |
2097 | .bEndpointAddress = USB_DIR_IN | 6, |
2098 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2099 | .regoff_udccs = UDCCS6, |
2100 | .regoff_uddr = UDDR6, |
2101 | }, |
2102 | .ep[7] = { |
2103 | .ep = { |
2104 | .name = "ep7out-bulk" , |
2105 | .ops = &pxa25x_ep_ops, |
2106 | .maxpacket = BULK_FIFO_SIZE, |
2107 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2108 | USB_EP_CAPS_DIR_OUT), |
2109 | }, |
2110 | .dev = &memory, |
2111 | .fifo_size = BULK_FIFO_SIZE, |
2112 | .bEndpointAddress = 7, |
2113 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2114 | .regoff_udccs = UDCCS7, |
2115 | .regoff_ubcr = UBCR7, |
2116 | .regoff_uddr = UDDR7, |
2117 | }, |
2118 | .ep[8] = { |
2119 | .ep = { |
2120 | .name = "ep8in-iso" , |
2121 | .ops = &pxa25x_ep_ops, |
2122 | .maxpacket = ISO_FIFO_SIZE, |
2123 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2124 | USB_EP_CAPS_DIR_IN), |
2125 | }, |
2126 | .dev = &memory, |
2127 | .fifo_size = ISO_FIFO_SIZE, |
2128 | .bEndpointAddress = USB_DIR_IN | 8, |
2129 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2130 | .regoff_udccs = UDCCS8, |
2131 | .regoff_uddr = UDDR8, |
2132 | }, |
2133 | .ep[9] = { |
2134 | .ep = { |
2135 | .name = "ep9out-iso" , |
2136 | .ops = &pxa25x_ep_ops, |
2137 | .maxpacket = ISO_FIFO_SIZE, |
2138 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2139 | USB_EP_CAPS_DIR_OUT), |
2140 | }, |
2141 | .dev = &memory, |
2142 | .fifo_size = ISO_FIFO_SIZE, |
2143 | .bEndpointAddress = 9, |
2144 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2145 | .regoff_udccs = UDCCS9, |
2146 | .regoff_ubcr = UBCR9, |
2147 | .regoff_uddr = UDDR9, |
2148 | }, |
2149 | .ep[10] = { |
2150 | .ep = { |
2151 | .name = "ep10in-int" , |
2152 | .ops = &pxa25x_ep_ops, |
2153 | .maxpacket = INT_FIFO_SIZE, |
2154 | .caps = USB_EP_CAPS(0, 0), |
2155 | }, |
2156 | .dev = &memory, |
2157 | .fifo_size = INT_FIFO_SIZE, |
2158 | .bEndpointAddress = USB_DIR_IN | 10, |
2159 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2160 | .regoff_udccs = UDCCS10, |
2161 | .regoff_uddr = UDDR10, |
2162 | }, |
2163 | |
2164 | /* third group of endpoints */ |
2165 | .ep[11] = { |
2166 | .ep = { |
2167 | .name = "ep11in-bulk" , |
2168 | .ops = &pxa25x_ep_ops, |
2169 | .maxpacket = BULK_FIFO_SIZE, |
2170 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2171 | USB_EP_CAPS_DIR_IN), |
2172 | }, |
2173 | .dev = &memory, |
2174 | .fifo_size = BULK_FIFO_SIZE, |
2175 | .bEndpointAddress = USB_DIR_IN | 11, |
2176 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2177 | .regoff_udccs = UDCCS11, |
2178 | .regoff_uddr = UDDR11, |
2179 | }, |
2180 | .ep[12] = { |
2181 | .ep = { |
2182 | .name = "ep12out-bulk" , |
2183 | .ops = &pxa25x_ep_ops, |
2184 | .maxpacket = BULK_FIFO_SIZE, |
2185 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, |
2186 | USB_EP_CAPS_DIR_OUT), |
2187 | }, |
2188 | .dev = &memory, |
2189 | .fifo_size = BULK_FIFO_SIZE, |
2190 | .bEndpointAddress = 12, |
2191 | .bmAttributes = USB_ENDPOINT_XFER_BULK, |
2192 | .regoff_udccs = UDCCS12, |
2193 | .regoff_ubcr = UBCR12, |
2194 | .regoff_uddr = UDDR12, |
2195 | }, |
2196 | .ep[13] = { |
2197 | .ep = { |
2198 | .name = "ep13in-iso" , |
2199 | .ops = &pxa25x_ep_ops, |
2200 | .maxpacket = ISO_FIFO_SIZE, |
2201 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2202 | USB_EP_CAPS_DIR_IN), |
2203 | }, |
2204 | .dev = &memory, |
2205 | .fifo_size = ISO_FIFO_SIZE, |
2206 | .bEndpointAddress = USB_DIR_IN | 13, |
2207 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2208 | .regoff_udccs = UDCCS13, |
2209 | .regoff_uddr = UDDR13, |
2210 | }, |
2211 | .ep[14] = { |
2212 | .ep = { |
2213 | .name = "ep14out-iso" , |
2214 | .ops = &pxa25x_ep_ops, |
2215 | .maxpacket = ISO_FIFO_SIZE, |
2216 | .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, |
2217 | USB_EP_CAPS_DIR_OUT), |
2218 | }, |
2219 | .dev = &memory, |
2220 | .fifo_size = ISO_FIFO_SIZE, |
2221 | .bEndpointAddress = 14, |
2222 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, |
2223 | .regoff_udccs = UDCCS14, |
2224 | .regoff_ubcr = UBCR14, |
2225 | .regoff_uddr = UDDR14, |
2226 | }, |
2227 | .ep[15] = { |
2228 | .ep = { |
2229 | .name = "ep15in-int" , |
2230 | .ops = &pxa25x_ep_ops, |
2231 | .maxpacket = INT_FIFO_SIZE, |
2232 | .caps = USB_EP_CAPS(0, 0), |
2233 | }, |
2234 | .dev = &memory, |
2235 | .fifo_size = INT_FIFO_SIZE, |
2236 | .bEndpointAddress = USB_DIR_IN | 15, |
2237 | .bmAttributes = USB_ENDPOINT_XFER_INT, |
2238 | .regoff_udccs = UDCCS15, |
2239 | .regoff_uddr = UDDR15, |
2240 | }, |
2241 | #endif /* !CONFIG_USB_PXA25X_SMALL */ |
2242 | }; |
2243 | |
2244 | #define CP15R0_VENDOR_MASK 0xffffe000 |
2245 | |
2246 | #if defined(CONFIG_ARCH_PXA) |
2247 | #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */ |
2248 | |
2249 | #elif defined(CONFIG_ARCH_IXP4XX) |
2250 | #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */ |
2251 | |
2252 | #endif |
2253 | |
2254 | #define CP15R0_PROD_MASK 0x000003f0 |
2255 | #define PXA25x 0x00000100 /* and PXA26x */ |
2256 | #define PXA210 0x00000120 |
2257 | |
2258 | #define CP15R0_REV_MASK 0x0000000f |
2259 | |
2260 | #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK) |
2261 | |
2262 | #define PXA255_A0 0x00000106 /* or PXA260_B1 */ |
2263 | #define PXA250_C0 0x00000105 /* or PXA26x_B0 */ |
2264 | #define PXA250_B2 0x00000104 |
2265 | #define PXA250_B1 0x00000103 /* or PXA260_A0 */ |
2266 | #define PXA250_B0 0x00000102 |
2267 | #define PXA250_A1 0x00000101 |
2268 | #define PXA250_A0 0x00000100 |
2269 | |
2270 | #define PXA210_C0 0x00000125 |
2271 | #define PXA210_B2 0x00000124 |
2272 | #define PXA210_B1 0x00000123 |
2273 | #define PXA210_B0 0x00000122 |
2274 | #define IXP425_A0 0x000001c1 |
2275 | #define IXP425_B0 0x000001f1 |
2276 | #define IXP465_AD 0x00000200 |
2277 | |
2278 | /* |
2279 | * probe - binds to the platform device |
2280 | */ |
2281 | static int pxa25x_udc_probe(struct platform_device *pdev) |
2282 | { |
2283 | struct pxa25x_udc *dev = &memory; |
2284 | int retval, irq; |
2285 | u32 chiprev; |
2286 | |
2287 | pr_info("%s: version %s\n" , driver_name, DRIVER_VERSION); |
2288 | |
2289 | /* insist on Intel/ARM/XScale */ |
2290 | asm("mrc p15, 0, %0, c0, c0" : "=r" (chiprev)); |
2291 | if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { |
2292 | pr_err("%s: not XScale!\n" , driver_name); |
2293 | return -ENODEV; |
2294 | } |
2295 | |
2296 | /* trigger chiprev-specific logic */ |
2297 | switch (chiprev & CP15R0_PRODREV_MASK) { |
2298 | #if defined(CONFIG_ARCH_PXA) |
2299 | case PXA255_A0: |
2300 | dev->has_cfr = 1; |
2301 | break; |
2302 | case PXA250_A0: |
2303 | case PXA250_A1: |
2304 | /* A0/A1 "not released"; ep 13, 15 unusable */ |
2305 | fallthrough; |
2306 | case PXA250_B2: case PXA210_B2: |
2307 | case PXA250_B1: case PXA210_B1: |
2308 | case PXA250_B0: case PXA210_B0: |
2309 | /* OUT-DMA is broken ... */ |
2310 | fallthrough; |
2311 | case PXA250_C0: case PXA210_C0: |
2312 | break; |
2313 | #elif defined(CONFIG_ARCH_IXP4XX) |
2314 | case IXP425_A0: |
2315 | case IXP425_B0: |
2316 | case IXP465_AD: |
2317 | dev->has_cfr = 1; |
2318 | break; |
2319 | #endif |
2320 | default: |
2321 | pr_err("%s: unrecognized processor: %08x\n" , |
2322 | driver_name, chiprev); |
2323 | /* iop3xx, ixp4xx, ... */ |
2324 | return -ENODEV; |
2325 | } |
2326 | |
2327 | irq = platform_get_irq(pdev, 0); |
2328 | if (irq < 0) |
2329 | return irq; |
2330 | |
2331 | dev->regs = devm_platform_ioremap_resource(pdev, index: 0); |
2332 | if (IS_ERR(ptr: dev->regs)) |
2333 | return PTR_ERR(ptr: dev->regs); |
2334 | |
2335 | dev->clk = devm_clk_get(dev: &pdev->dev, NULL); |
2336 | if (IS_ERR(ptr: dev->clk)) |
2337 | return PTR_ERR(ptr: dev->clk); |
2338 | |
2339 | pr_debug("%s: IRQ %d%s%s\n" , driver_name, irq, |
2340 | dev->has_cfr ? "" : " (!cfr)" , |
2341 | SIZE_STR "(pio)" |
2342 | ); |
2343 | |
2344 | /* other non-static parts of init */ |
2345 | dev->dev = &pdev->dev; |
2346 | dev->mach = dev_get_platdata(dev: &pdev->dev); |
2347 | |
2348 | dev->transceiver = devm_usb_get_phy(dev: &pdev->dev, type: USB_PHY_TYPE_USB2); |
2349 | |
2350 | if (gpio_is_valid(number: dev->mach->gpio_pullup)) { |
2351 | retval = devm_gpio_request(dev: &pdev->dev, gpio: dev->mach->gpio_pullup, |
2352 | label: "pca25x_udc GPIO PULLUP" ); |
2353 | if (retval) { |
2354 | dev_dbg(&pdev->dev, |
2355 | "can't get pullup gpio %d, err: %d\n" , |
2356 | dev->mach->gpio_pullup, retval); |
2357 | goto err; |
2358 | } |
2359 | gpio_direction_output(gpio: dev->mach->gpio_pullup, value: 0); |
2360 | } |
2361 | |
2362 | timer_setup(&dev->timer, udc_watchdog, 0); |
2363 | |
2364 | the_controller = dev; |
2365 | platform_set_drvdata(pdev, data: dev); |
2366 | |
2367 | udc_disable(dev); |
2368 | udc_reinit(dev); |
2369 | |
2370 | dev->vbus = 0; |
2371 | |
2372 | /* irq setup after old hardware state is cleaned up */ |
2373 | retval = devm_request_irq(dev: &pdev->dev, irq, handler: pxa25x_udc_irq, irqflags: 0, |
2374 | devname: driver_name, dev_id: dev); |
2375 | if (retval != 0) { |
2376 | pr_err("%s: can't get irq %d, err %d\n" , |
2377 | driver_name, irq, retval); |
2378 | goto err; |
2379 | } |
2380 | dev->got_irq = 1; |
2381 | |
2382 | create_debug_files(dev); |
2383 | |
2384 | retval = usb_add_gadget_udc(parent: &pdev->dev, gadget: &dev->gadget); |
2385 | if (!retval) |
2386 | return retval; |
2387 | |
2388 | remove_debug_files(dev); |
2389 | err: |
2390 | if (!IS_ERR_OR_NULL(ptr: dev->transceiver)) |
2391 | dev->transceiver = NULL; |
2392 | return retval; |
2393 | } |
2394 | |
2395 | static void pxa25x_udc_shutdown(struct platform_device *_dev) |
2396 | { |
2397 | pullup_off(); |
2398 | } |
2399 | |
2400 | static void pxa25x_udc_remove(struct platform_device *pdev) |
2401 | { |
2402 | struct pxa25x_udc *dev = platform_get_drvdata(pdev); |
2403 | |
2404 | if (dev->driver) { |
2405 | dev_err(&pdev->dev, |
2406 | "Driver still in use but removing anyhow\n" ); |
2407 | return; |
2408 | } |
2409 | |
2410 | usb_del_gadget_udc(gadget: &dev->gadget); |
2411 | dev->pullup = 0; |
2412 | pullup(udc: dev); |
2413 | |
2414 | remove_debug_files(dev); |
2415 | |
2416 | if (!IS_ERR_OR_NULL(ptr: dev->transceiver)) |
2417 | dev->transceiver = NULL; |
2418 | |
2419 | the_controller = NULL; |
2420 | } |
2421 | |
2422 | /*-------------------------------------------------------------------------*/ |
2423 | |
2424 | #ifdef CONFIG_PM |
2425 | |
2426 | /* USB suspend (controlled by the host) and system suspend (controlled |
2427 | * by the PXA) don't necessarily work well together. If USB is active, |
2428 | * the 48 MHz clock is required; so the system can't enter 33 MHz idle |
2429 | * mode, or any deeper PM saving state. |
2430 | * |
2431 | * For now, we punt and forcibly disconnect from the USB host when PXA |
2432 | * enters any suspend state. While we're disconnected, we always disable |
2433 | * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states. |
2434 | * Boards without software pullup control shouldn't use those states. |
2435 | * VBUS IRQs should probably be ignored so that the PXA device just acts |
2436 | * "dead" to USB hosts until system resume. |
2437 | */ |
2438 | static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state) |
2439 | { |
2440 | struct pxa25x_udc *udc = platform_get_drvdata(pdev: dev); |
2441 | unsigned long flags; |
2442 | |
2443 | if (!gpio_is_valid(number: udc->mach->gpio_pullup) && !udc->mach->udc_command) |
2444 | WARNING("USB host won't detect disconnect!\n" ); |
2445 | udc->suspended = 1; |
2446 | |
2447 | local_irq_save(flags); |
2448 | pullup(udc); |
2449 | local_irq_restore(flags); |
2450 | |
2451 | return 0; |
2452 | } |
2453 | |
2454 | static int pxa25x_udc_resume(struct platform_device *dev) |
2455 | { |
2456 | struct pxa25x_udc *udc = platform_get_drvdata(pdev: dev); |
2457 | unsigned long flags; |
2458 | |
2459 | udc->suspended = 0; |
2460 | local_irq_save(flags); |
2461 | pullup(udc); |
2462 | local_irq_restore(flags); |
2463 | |
2464 | return 0; |
2465 | } |
2466 | |
2467 | #else |
2468 | #define pxa25x_udc_suspend NULL |
2469 | #define pxa25x_udc_resume NULL |
2470 | #endif |
2471 | |
2472 | /*-------------------------------------------------------------------------*/ |
2473 | |
2474 | static struct platform_driver udc_driver = { |
2475 | .shutdown = pxa25x_udc_shutdown, |
2476 | .probe = pxa25x_udc_probe, |
2477 | .remove_new = pxa25x_udc_remove, |
2478 | .suspend = pxa25x_udc_suspend, |
2479 | .resume = pxa25x_udc_resume, |
2480 | .driver = { |
2481 | .name = "pxa25x-udc" , |
2482 | }, |
2483 | }; |
2484 | |
2485 | module_platform_driver(udc_driver); |
2486 | |
2487 | MODULE_DESCRIPTION(DRIVER_DESC); |
2488 | MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell" ); |
2489 | MODULE_LICENSE("GPL" ); |
2490 | MODULE_ALIAS("platform:pxa25x-udc" ); |
2491 | |