1//=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// When the compiler is invoked with no small data, for instance, with the -G0
10// command line option, then all CONST* opcodes should be broken down into
11// appropriate LO and HI instructions. This splitting is done by this pass.
12// The only reason this is not done in the DAG lowering itself is that there
13// is no simple way of getting the register allocator to allot the same hard
14// register to the result of LO and HI instructions. This pass is always
15// scheduled after register allocation.
16//
17//===----------------------------------------------------------------------===//
18
19#include "HexagonSubtarget.h"
20#include "HexagonTargetMachine.h"
21#include "HexagonTargetObjectFile.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/Passes.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetRegisterInfo.h"
27
28using namespace llvm;
29
30#define DEBUG_TYPE "xfer"
31
32namespace llvm {
33 FunctionPass *createHexagonSplitConst32AndConst64();
34 void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&);
35}
36
37namespace {
38 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
39 public:
40 static char ID;
41 HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {
42 PassRegistry &R = *PassRegistry::getPassRegistry();
43 initializeHexagonSplitConst32AndConst64Pass(R);
44 }
45 StringRef getPassName() const override {
46 return "Hexagon Split Const32s and Const64s";
47 }
48 bool runOnMachineFunction(MachineFunction &Fn) override;
49 MachineFunctionProperties getRequiredProperties() const override {
50 return MachineFunctionProperties().set(
51 MachineFunctionProperties::Property::NoVRegs);
52 }
53 };
54}
55
56char HexagonSplitConst32AndConst64::ID = 0;
57
58INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
59 "Hexagon Split Const32s and Const64s", false, false)
60
61bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
62 auto &HST = Fn.getSubtarget<HexagonSubtarget>();
63 auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
64 auto &TLOF = *HTM.getObjFileLowering();
65 if (HST.useSmallData() && TLOF.isSmallDataEnabled(HTM))
66 return false;
67
68 const TargetInstrInfo *TII = HST.getInstrInfo();
69 const TargetRegisterInfo *TRI = HST.getRegisterInfo();
70
71 // Loop over all of the basic blocks
72 for (MachineBasicBlock &B : Fn) {
73 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: B)) {
74 unsigned Opc = MI.getOpcode();
75
76 if (Opc == Hexagon::CONST32) {
77 Register DestReg = MI.getOperand(i: 0).getReg();
78 uint64_t ImmValue = MI.getOperand(i: 1).getImm();
79 const DebugLoc &DL = MI.getDebugLoc();
80 BuildMI(B, MI, DL, TII->get(Hexagon::Opcode: A2_tfrsi), DestReg)
81 .addImm(ImmValue);
82 B.erase(I: &MI);
83 } else if (Opc == Hexagon::CONST64) {
84 Register DestReg = MI.getOperand(i: 0).getReg();
85 int64_t ImmValue = MI.getOperand(i: 1).getImm();
86 const DebugLoc &DL = MI.getDebugLoc();
87 Register DestLo = TRI->getSubReg(Reg: DestReg, Idx: Hexagon::isub_lo);
88 Register DestHi = TRI->getSubReg(Reg: DestReg, Idx: Hexagon::isub_hi);
89
90 int32_t LowWord = (ImmValue & 0xFFFFFFFF);
91 int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
92
93 BuildMI(B, MI, DL, TII->get(Hexagon::Opcode: A2_tfrsi), DestLo)
94 .addImm(LowWord);
95 BuildMI(B, MI, DL, TII->get(Hexagon::Opcode: A2_tfrsi), DestHi)
96 .addImm(HighWord);
97 B.erase(I: &MI);
98 }
99 }
100 }
101
102 return true;
103}
104
105
106//===----------------------------------------------------------------------===//
107// Public Constructor Functions
108//===----------------------------------------------------------------------===//
109FunctionPass *llvm::createHexagonSplitConst32AndConst64() {
110 return new HexagonSplitConst32AndConst64();
111}
112

source code of llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp