1 | //===- SPIRVBuiltins.cpp - SPIR-V Built-in Functions ------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file implements lowering builtin function calls and types using their |
10 | // demangled names and TableGen records. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #include "SPIRVBuiltins.h" |
15 | #include "SPIRV.h" |
16 | #include "SPIRVSubtarget.h" |
17 | #include "SPIRVUtils.h" |
18 | #include "llvm/ADT/StringExtras.h" |
19 | #include "llvm/Analysis/ValueTracking.h" |
20 | #include "llvm/IR/IntrinsicsSPIRV.h" |
21 | #include <string> |
22 | #include <tuple> |
23 | |
24 | #define DEBUG_TYPE "spirv-builtins" |
25 | |
26 | namespace llvm { |
27 | namespace SPIRV { |
28 | #define GET_BuiltinGroup_DECL |
29 | #include "SPIRVGenTables.inc" |
30 | |
31 | struct DemangledBuiltin { |
32 | StringRef Name; |
33 | InstructionSet::InstructionSet Set; |
34 | BuiltinGroup Group; |
35 | uint8_t MinNumArgs; |
36 | uint8_t MaxNumArgs; |
37 | }; |
38 | |
39 | #define GET_DemangledBuiltins_DECL |
40 | #define GET_DemangledBuiltins_IMPL |
41 | |
42 | struct IncomingCall { |
43 | const std::string BuiltinName; |
44 | const DemangledBuiltin *Builtin; |
45 | |
46 | const Register ReturnRegister; |
47 | const SPIRVType *ReturnType; |
48 | const SmallVectorImpl<Register> &Arguments; |
49 | |
50 | IncomingCall(const std::string BuiltinName, const DemangledBuiltin *Builtin, |
51 | const Register ReturnRegister, const SPIRVType *ReturnType, |
52 | const SmallVectorImpl<Register> &Arguments) |
53 | : BuiltinName(BuiltinName), Builtin(Builtin), |
54 | ReturnRegister(ReturnRegister), ReturnType(ReturnType), |
55 | Arguments(Arguments) {} |
56 | |
57 | bool isSpirvOp() const { return BuiltinName.rfind(s: "__spirv_" , pos: 0) == 0; } |
58 | }; |
59 | |
60 | struct NativeBuiltin { |
61 | StringRef Name; |
62 | InstructionSet::InstructionSet Set; |
63 | uint32_t Opcode; |
64 | }; |
65 | |
66 | #define GET_NativeBuiltins_DECL |
67 | #define GET_NativeBuiltins_IMPL |
68 | |
69 | struct GroupBuiltin { |
70 | StringRef Name; |
71 | uint32_t Opcode; |
72 | uint32_t GroupOperation; |
73 | bool IsElect; |
74 | bool IsAllOrAny; |
75 | bool IsAllEqual; |
76 | bool IsBallot; |
77 | bool IsInverseBallot; |
78 | bool ; |
79 | bool IsBallotFindBit; |
80 | bool IsLogical; |
81 | bool NoGroupOperation; |
82 | bool HasBoolArg; |
83 | }; |
84 | |
85 | #define GET_GroupBuiltins_DECL |
86 | #define GET_GroupBuiltins_IMPL |
87 | |
88 | struct IntelSubgroupsBuiltin { |
89 | StringRef Name; |
90 | uint32_t Opcode; |
91 | bool IsBlock; |
92 | bool IsWrite; |
93 | }; |
94 | |
95 | #define GET_IntelSubgroupsBuiltins_DECL |
96 | #define GET_IntelSubgroupsBuiltins_IMPL |
97 | |
98 | struct AtomicFloatingBuiltin { |
99 | StringRef Name; |
100 | uint32_t Opcode; |
101 | }; |
102 | |
103 | #define GET_AtomicFloatingBuiltins_DECL |
104 | #define GET_AtomicFloatingBuiltins_IMPL |
105 | struct GroupUniformBuiltin { |
106 | StringRef Name; |
107 | uint32_t Opcode; |
108 | bool IsLogical; |
109 | }; |
110 | |
111 | #define GET_GroupUniformBuiltins_DECL |
112 | #define GET_GroupUniformBuiltins_IMPL |
113 | |
114 | struct GetBuiltin { |
115 | StringRef Name; |
116 | InstructionSet::InstructionSet Set; |
117 | BuiltIn::BuiltIn Value; |
118 | }; |
119 | |
120 | using namespace BuiltIn; |
121 | #define GET_GetBuiltins_DECL |
122 | #define GET_GetBuiltins_IMPL |
123 | |
124 | struct ImageQueryBuiltin { |
125 | StringRef Name; |
126 | InstructionSet::InstructionSet Set; |
127 | uint32_t Component; |
128 | }; |
129 | |
130 | #define GET_ImageQueryBuiltins_DECL |
131 | #define GET_ImageQueryBuiltins_IMPL |
132 | |
133 | struct ConvertBuiltin { |
134 | StringRef Name; |
135 | InstructionSet::InstructionSet Set; |
136 | bool IsDestinationSigned; |
137 | bool IsSaturated; |
138 | bool IsRounded; |
139 | bool IsBfloat16; |
140 | FPRoundingMode::FPRoundingMode RoundingMode; |
141 | }; |
142 | |
143 | struct VectorLoadStoreBuiltin { |
144 | StringRef Name; |
145 | InstructionSet::InstructionSet Set; |
146 | uint32_t Number; |
147 | uint32_t ElementCount; |
148 | bool IsRounded; |
149 | FPRoundingMode::FPRoundingMode RoundingMode; |
150 | }; |
151 | |
152 | using namespace FPRoundingMode; |
153 | #define GET_ConvertBuiltins_DECL |
154 | #define GET_ConvertBuiltins_IMPL |
155 | |
156 | using namespace InstructionSet; |
157 | #define GET_VectorLoadStoreBuiltins_DECL |
158 | #define GET_VectorLoadStoreBuiltins_IMPL |
159 | |
160 | #define GET_CLMemoryScope_DECL |
161 | #define GET_CLSamplerAddressingMode_DECL |
162 | #define GET_CLMemoryFenceFlags_DECL |
163 | #define GET_ExtendedBuiltins_DECL |
164 | #include "SPIRVGenTables.inc" |
165 | } // namespace SPIRV |
166 | |
167 | //===----------------------------------------------------------------------===// |
168 | // Misc functions for looking up builtins and veryfying requirements using |
169 | // TableGen records |
170 | //===----------------------------------------------------------------------===// |
171 | |
172 | /// Looks up the demangled builtin call in the SPIRVBuiltins.td records using |
173 | /// the provided \p DemangledCall and specified \p Set. |
174 | /// |
175 | /// The lookup follows the following algorithm, returning the first successful |
176 | /// match: |
177 | /// 1. Search with the plain demangled name (expecting a 1:1 match). |
178 | /// 2. Search with the prefix before or suffix after the demangled name |
179 | /// signyfying the type of the first argument. |
180 | /// |
181 | /// \returns Wrapper around the demangled call and found builtin definition. |
182 | static std::unique_ptr<const SPIRV::IncomingCall> |
183 | lookupBuiltin(StringRef DemangledCall, |
184 | SPIRV::InstructionSet::InstructionSet Set, |
185 | Register ReturnRegister, const SPIRVType *ReturnType, |
186 | const SmallVectorImpl<Register> &Arguments) { |
187 | // Extract the builtin function name and types of arguments from the call |
188 | // skeleton. |
189 | std::string BuiltinName = |
190 | DemangledCall.substr(Start: 0, N: DemangledCall.find(C: '(')).str(); |
191 | |
192 | // Check if the extracted name contains type information between angle |
193 | // brackets. If so, the builtin is an instantiated template - needs to have |
194 | // the information after angle brackets and return type removed. |
195 | if (BuiltinName.find('<') && BuiltinName.back() == '>') { |
196 | BuiltinName = BuiltinName.substr(pos: 0, n: BuiltinName.find('<')); |
197 | BuiltinName = BuiltinName.substr(BuiltinName.find_last_of(' ') + 1); |
198 | } |
199 | |
200 | // Check if the extracted name begins with "__spirv_ImageSampleExplicitLod" |
201 | // contains return type information at the end "_R<type>", if so extract the |
202 | // plain builtin name without the type information. |
203 | if (StringRef(BuiltinName).contains(Other: "__spirv_ImageSampleExplicitLod" ) && |
204 | StringRef(BuiltinName).contains(Other: "_R" )) { |
205 | BuiltinName = BuiltinName.substr(pos: 0, n: BuiltinName.find("_R" )); |
206 | } |
207 | |
208 | SmallVector<StringRef, 10> BuiltinArgumentTypes; |
209 | StringRef BuiltinArgs = |
210 | DemangledCall.slice(Start: DemangledCall.find(C: '(') + 1, End: DemangledCall.find(C: ')')); |
211 | BuiltinArgs.split(BuiltinArgumentTypes, ',', -1, false); |
212 | |
213 | // Look up the builtin in the defined set. Start with the plain demangled |
214 | // name, expecting a 1:1 match in the defined builtin set. |
215 | const SPIRV::DemangledBuiltin *Builtin; |
216 | if ((Builtin = SPIRV::lookupBuiltin(BuiltinName, Set))) |
217 | return std::make_unique<SPIRV::IncomingCall>( |
218 | BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments); |
219 | |
220 | // If the initial look up was unsuccessful and the demangled call takes at |
221 | // least 1 argument, add a prefix or suffix signifying the type of the first |
222 | // argument and repeat the search. |
223 | if (BuiltinArgumentTypes.size() >= 1) { |
224 | char FirstArgumentType = BuiltinArgumentTypes[0][0]; |
225 | // Prefix to be added to the builtin's name for lookup. |
226 | // For example, OpenCL "abs" taking an unsigned value has a prefix "u_". |
227 | std::string Prefix; |
228 | |
229 | switch (FirstArgumentType) { |
230 | // Unsigned: |
231 | case 'u': |
232 | if (Set == SPIRV::InstructionSet::OpenCL_std) |
233 | Prefix = "u_" ; |
234 | else if (Set == SPIRV::InstructionSet::GLSL_std_450) |
235 | Prefix = "u" ; |
236 | break; |
237 | // Signed: |
238 | case 'c': |
239 | case 's': |
240 | case 'i': |
241 | case 'l': |
242 | if (Set == SPIRV::InstructionSet::OpenCL_std) |
243 | Prefix = "s_" ; |
244 | else if (Set == SPIRV::InstructionSet::GLSL_std_450) |
245 | Prefix = "s" ; |
246 | break; |
247 | // Floating-point: |
248 | case 'f': |
249 | case 'd': |
250 | case 'h': |
251 | if (Set == SPIRV::InstructionSet::OpenCL_std || |
252 | Set == SPIRV::InstructionSet::GLSL_std_450) |
253 | Prefix = "f" ; |
254 | break; |
255 | } |
256 | |
257 | // If argument-type name prefix was added, look up the builtin again. |
258 | if (!Prefix.empty() && |
259 | (Builtin = SPIRV::lookupBuiltin(Prefix + BuiltinName, Set))) |
260 | return std::make_unique<SPIRV::IncomingCall>( |
261 | BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments); |
262 | |
263 | // If lookup with a prefix failed, find a suffix to be added to the |
264 | // builtin's name for lookup. For example, OpenCL "group_reduce_max" taking |
265 | // an unsigned value has a suffix "u". |
266 | std::string Suffix; |
267 | |
268 | switch (FirstArgumentType) { |
269 | // Unsigned: |
270 | case 'u': |
271 | Suffix = "u" ; |
272 | break; |
273 | // Signed: |
274 | case 'c': |
275 | case 's': |
276 | case 'i': |
277 | case 'l': |
278 | Suffix = "s" ; |
279 | break; |
280 | // Floating-point: |
281 | case 'f': |
282 | case 'd': |
283 | case 'h': |
284 | Suffix = "f" ; |
285 | break; |
286 | } |
287 | |
288 | // If argument-type name suffix was added, look up the builtin again. |
289 | if (!Suffix.empty() && |
290 | (Builtin = SPIRV::lookupBuiltin(BuiltinName + Suffix, Set))) |
291 | return std::make_unique<SPIRV::IncomingCall>( |
292 | BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments); |
293 | } |
294 | |
295 | // No builtin with such name was found in the set. |
296 | return nullptr; |
297 | } |
298 | |
299 | //===----------------------------------------------------------------------===// |
300 | // Helper functions for building misc instructions |
301 | //===----------------------------------------------------------------------===// |
302 | |
303 | /// Helper function building either a resulting scalar or vector bool register |
304 | /// depending on the expected \p ResultType. |
305 | /// |
306 | /// \returns Tuple of the resulting register and its type. |
307 | static std::tuple<Register, SPIRVType *> |
308 | buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType, |
309 | SPIRVGlobalRegistry *GR) { |
310 | LLT Type; |
311 | SPIRVType *BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder); |
312 | |
313 | if (ResultType->getOpcode() == SPIRV::OpTypeVector) { |
314 | unsigned VectorElements = ResultType->getOperand(i: 2).getImm(); |
315 | BoolType = |
316 | GR->getOrCreateSPIRVVectorType(BaseType: BoolType, NumElements: VectorElements, MIRBuilder); |
317 | const FixedVectorType *LLVMVectorType = |
318 | cast<FixedVectorType>(GR->getTypeForSPIRVType(Ty: BoolType)); |
319 | Type = LLT::vector(EC: LLVMVectorType->getElementCount(), ScalarSizeInBits: 1); |
320 | } else { |
321 | Type = LLT::scalar(SizeInBits: 1); |
322 | } |
323 | |
324 | Register ResultRegister = |
325 | MIRBuilder.getMRI()->createGenericVirtualRegister(Ty: Type); |
326 | MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass); |
327 | GR->assignSPIRVTypeToVReg(Type: BoolType, VReg: ResultRegister, MF&: MIRBuilder.getMF()); |
328 | return std::make_tuple(ResultRegister, BoolType); |
329 | } |
330 | |
331 | /// Helper function for building either a vector or scalar select instruction |
332 | /// depending on the expected \p ResultType. |
333 | static bool buildSelectInst(MachineIRBuilder &MIRBuilder, |
334 | Register ReturnRegister, Register SourceRegister, |
335 | const SPIRVType *ReturnType, |
336 | SPIRVGlobalRegistry *GR) { |
337 | Register TrueConst, FalseConst; |
338 | |
339 | if (ReturnType->getOpcode() == SPIRV::OpTypeVector) { |
340 | unsigned Bits = GR->getScalarOrVectorBitWidth(Type: ReturnType); |
341 | uint64_t AllOnes = APInt::getAllOnes(numBits: Bits).getZExtValue(); |
342 | TrueConst = GR->getOrCreateConsIntVector(Val: AllOnes, MIRBuilder, SpvType: ReturnType); |
343 | FalseConst = GR->getOrCreateConsIntVector(Val: 0, MIRBuilder, SpvType: ReturnType); |
344 | } else { |
345 | TrueConst = GR->buildConstantInt(Val: 1, MIRBuilder, SpvType: ReturnType); |
346 | FalseConst = GR->buildConstantInt(Val: 0, MIRBuilder, SpvType: ReturnType); |
347 | } |
348 | return MIRBuilder.buildSelect(Res: ReturnRegister, Tst: SourceRegister, Op0: TrueConst, |
349 | Op1: FalseConst); |
350 | } |
351 | |
352 | /// Helper function for building a load instruction loading into the |
353 | /// \p DestinationReg. |
354 | static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister, |
355 | MachineIRBuilder &MIRBuilder, |
356 | SPIRVGlobalRegistry *GR, LLT LowLevelType, |
357 | Register DestinationReg = Register(0)) { |
358 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
359 | if (!DestinationReg.isValid()) { |
360 | DestinationReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); |
361 | MRI->setType(VReg: DestinationReg, Ty: LLT::scalar(SizeInBits: 32)); |
362 | GR->assignSPIRVTypeToVReg(Type: BaseType, VReg: DestinationReg, MF&: MIRBuilder.getMF()); |
363 | } |
364 | // TODO: consider using correct address space and alignment (p0 is canonical |
365 | // type for selection though). |
366 | MachinePointerInfo PtrInfo = MachinePointerInfo(); |
367 | MIRBuilder.buildLoad(Res: DestinationReg, Addr: PtrRegister, PtrInfo, Alignment: Align()); |
368 | return DestinationReg; |
369 | } |
370 | |
371 | /// Helper function for building a load instruction for loading a builtin global |
372 | /// variable of \p BuiltinValue value. |
373 | static Register buildBuiltinVariableLoad( |
374 | MachineIRBuilder &MIRBuilder, SPIRVType *VariableType, |
375 | SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType, |
376 | Register Reg = Register(0), bool isConst = true, bool hasLinkageTy = true) { |
377 | Register NewRegister = |
378 | MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass); |
379 | MIRBuilder.getMRI()->setType(VReg: NewRegister, |
380 | Ty: LLT::pointer(AddressSpace: 0, SizeInBits: GR->getPointerSize())); |
381 | SPIRVType *PtrType = GR->getOrCreateSPIRVPointerType( |
382 | VariableType, MIRBuilder, SPIRV::StorageClass::Input); |
383 | GR->assignSPIRVTypeToVReg(Type: PtrType, VReg: NewRegister, MF&: MIRBuilder.getMF()); |
384 | |
385 | // Set up the global OpVariable with the necessary builtin decorations. |
386 | Register Variable = GR->buildGlobalVariable( |
387 | NewRegister, PtrType, getLinkStringForBuiltIn(BuiltinValue), nullptr, |
388 | SPIRV::StorageClass::Input, nullptr, /* isConst= */ isConst, |
389 | /* HasLinkageTy */ hasLinkageTy, SPIRV::LinkageType::Import, MIRBuilder, |
390 | false); |
391 | |
392 | // Load the value from the global variable. |
393 | Register LoadedRegister = |
394 | buildLoadInst(BaseType: VariableType, PtrRegister: Variable, MIRBuilder, GR, LowLevelType: LLType, DestinationReg: Reg); |
395 | MIRBuilder.getMRI()->setType(VReg: LoadedRegister, Ty: LLType); |
396 | return LoadedRegister; |
397 | } |
398 | |
399 | /// Helper external function for inserting ASSIGN_TYPE instuction between \p Reg |
400 | /// and its definition, set the new register as a destination of the definition, |
401 | /// assign SPIRVType to both registers. If SpirvTy is provided, use it as |
402 | /// SPIRVType in ASSIGN_TYPE, otherwise create it from \p Ty. Defined in |
403 | /// SPIRVPreLegalizer.cpp. |
404 | extern Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, |
405 | SPIRVGlobalRegistry *GR, |
406 | MachineIRBuilder &MIB, |
407 | MachineRegisterInfo &MRI); |
408 | |
409 | // TODO: Move to TableGen. |
410 | static SPIRV::MemorySemantics::MemorySemantics |
411 | getSPIRVMemSemantics(std::memory_order MemOrder) { |
412 | switch (MemOrder) { |
413 | case std::memory_order::memory_order_relaxed: |
414 | return SPIRV::MemorySemantics::None; |
415 | case std::memory_order::memory_order_acquire: |
416 | return SPIRV::MemorySemantics::Acquire; |
417 | case std::memory_order::memory_order_release: |
418 | return SPIRV::MemorySemantics::Release; |
419 | case std::memory_order::memory_order_acq_rel: |
420 | return SPIRV::MemorySemantics::AcquireRelease; |
421 | case std::memory_order::memory_order_seq_cst: |
422 | return SPIRV::MemorySemantics::SequentiallyConsistent; |
423 | default: |
424 | report_fatal_error(reason: "Unknown CL memory scope" ); |
425 | } |
426 | } |
427 | |
428 | static SPIRV::Scope::Scope getSPIRVScope(SPIRV::CLMemoryScope ClScope) { |
429 | switch (ClScope) { |
430 | case SPIRV::CLMemoryScope::memory_scope_work_item: |
431 | return SPIRV::Scope::Invocation; |
432 | case SPIRV::CLMemoryScope::memory_scope_work_group: |
433 | return SPIRV::Scope::Workgroup; |
434 | case SPIRV::CLMemoryScope::memory_scope_device: |
435 | return SPIRV::Scope::Device; |
436 | case SPIRV::CLMemoryScope::memory_scope_all_svm_devices: |
437 | return SPIRV::Scope::CrossDevice; |
438 | case SPIRV::CLMemoryScope::memory_scope_sub_group: |
439 | return SPIRV::Scope::Subgroup; |
440 | } |
441 | report_fatal_error(reason: "Unknown CL memory scope" ); |
442 | } |
443 | |
444 | static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder, |
445 | SPIRVGlobalRegistry *GR, |
446 | unsigned BitWidth = 32) { |
447 | SPIRVType *IntType = GR->getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder); |
448 | return GR->buildConstantInt(Val, MIRBuilder, SpvType: IntType); |
449 | } |
450 | |
451 | static Register buildScopeReg(Register CLScopeRegister, |
452 | SPIRV::Scope::Scope Scope, |
453 | MachineIRBuilder &MIRBuilder, |
454 | SPIRVGlobalRegistry *GR, |
455 | MachineRegisterInfo *MRI) { |
456 | if (CLScopeRegister.isValid()) { |
457 | auto CLScope = |
458 | static_cast<SPIRV::CLMemoryScope>(getIConstVal(ConstReg: CLScopeRegister, MRI)); |
459 | Scope = getSPIRVScope(CLScope); |
460 | |
461 | if (CLScope == static_cast<unsigned>(Scope)) { |
462 | MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass); |
463 | return CLScopeRegister; |
464 | } |
465 | } |
466 | return buildConstantIntReg(Scope, MIRBuilder, GR); |
467 | } |
468 | |
469 | static Register buildMemSemanticsReg(Register SemanticsRegister, |
470 | Register PtrRegister, unsigned &Semantics, |
471 | MachineIRBuilder &MIRBuilder, |
472 | SPIRVGlobalRegistry *GR) { |
473 | if (SemanticsRegister.isValid()) { |
474 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
475 | std::memory_order Order = |
476 | static_cast<std::memory_order>(getIConstVal(ConstReg: SemanticsRegister, MRI)); |
477 | Semantics = |
478 | getSPIRVMemSemantics(Order) | |
479 | getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); |
480 | |
481 | if (Order == Semantics) { |
482 | MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass); |
483 | return SemanticsRegister; |
484 | } |
485 | } |
486 | return buildConstantIntReg(Val: Semantics, MIRBuilder, GR); |
487 | } |
488 | |
489 | static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode, |
490 | const SPIRV::IncomingCall *Call, |
491 | Register TypeReg = Register(0)) { |
492 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
493 | auto MIB = MIRBuilder.buildInstr(Opcode); |
494 | if (TypeReg.isValid()) |
495 | MIB.addDef(RegNo: Call->ReturnRegister).addUse(RegNo: TypeReg); |
496 | for (Register ArgReg : Call->Arguments) { |
497 | if (!MRI->getRegClassOrNull(ArgReg)) |
498 | MRI->setRegClass(ArgReg, &SPIRV::IDRegClass); |
499 | MIB.addUse(RegNo: ArgReg); |
500 | } |
501 | return true; |
502 | } |
503 | |
504 | /// Helper function for translating atomic init to OpStore. |
505 | static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call, |
506 | MachineIRBuilder &MIRBuilder) { |
507 | if (Call->isSpirvOp()) |
508 | return buildOpFromWrapper(MIRBuilder, SPIRV::OpStore, Call); |
509 | |
510 | assert(Call->Arguments.size() == 2 && |
511 | "Need 2 arguments for atomic init translation" ); |
512 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
513 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
514 | MIRBuilder.buildInstr(SPIRV::OpStore) |
515 | .addUse(Call->Arguments[0]) |
516 | .addUse(Call->Arguments[1]); |
517 | return true; |
518 | } |
519 | |
520 | /// Helper function for building an atomic load instruction. |
521 | static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call, |
522 | MachineIRBuilder &MIRBuilder, |
523 | SPIRVGlobalRegistry *GR) { |
524 | Register TypeReg = GR->getSPIRVTypeID(SpirvType: Call->ReturnType); |
525 | if (Call->isSpirvOp()) |
526 | return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicLoad, Call, TypeReg); |
527 | |
528 | Register PtrRegister = Call->Arguments[0]; |
529 | MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass); |
530 | // TODO: if true insert call to __translate_ocl_memory_sccope before |
531 | // OpAtomicLoad and the function implementation. We can use Translator's |
532 | // output for transcoding/atomic_explicit_arguments.cl as an example. |
533 | Register ScopeRegister; |
534 | if (Call->Arguments.size() > 1) { |
535 | ScopeRegister = Call->Arguments[1]; |
536 | MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass); |
537 | } else |
538 | ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR); |
539 | |
540 | Register MemSemanticsReg; |
541 | if (Call->Arguments.size() > 2) { |
542 | // TODO: Insert call to __translate_ocl_memory_order before OpAtomicLoad. |
543 | MemSemanticsReg = Call->Arguments[2]; |
544 | MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass); |
545 | } else { |
546 | int Semantics = |
547 | SPIRV::MemorySemantics::SequentiallyConsistent | |
548 | getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); |
549 | MemSemanticsReg = buildConstantIntReg(Val: Semantics, MIRBuilder, GR); |
550 | } |
551 | |
552 | MIRBuilder.buildInstr(SPIRV::OpAtomicLoad) |
553 | .addDef(Call->ReturnRegister) |
554 | .addUse(TypeReg) |
555 | .addUse(PtrRegister) |
556 | .addUse(ScopeRegister) |
557 | .addUse(MemSemanticsReg); |
558 | return true; |
559 | } |
560 | |
561 | /// Helper function for building an atomic store instruction. |
562 | static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call, |
563 | MachineIRBuilder &MIRBuilder, |
564 | SPIRVGlobalRegistry *GR) { |
565 | if (Call->isSpirvOp()) |
566 | return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call); |
567 | |
568 | Register ScopeRegister = |
569 | buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR); |
570 | Register PtrRegister = Call->Arguments[0]; |
571 | MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass); |
572 | int Semantics = |
573 | SPIRV::MemorySemantics::SequentiallyConsistent | |
574 | getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister)); |
575 | Register MemSemanticsReg = buildConstantIntReg(Val: Semantics, MIRBuilder, GR); |
576 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
577 | MIRBuilder.buildInstr(SPIRV::OpAtomicStore) |
578 | .addUse(PtrRegister) |
579 | .addUse(ScopeRegister) |
580 | .addUse(MemSemanticsReg) |
581 | .addUse(Call->Arguments[1]); |
582 | return true; |
583 | } |
584 | |
585 | /// Helper function for building an atomic compare-exchange instruction. |
586 | static bool buildAtomicCompareExchangeInst( |
587 | const SPIRV::IncomingCall *Call, const SPIRV::DemangledBuiltin *Builtin, |
588 | unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { |
589 | if (Call->isSpirvOp()) |
590 | return buildOpFromWrapper(MIRBuilder, Opcode, Call, |
591 | TypeReg: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
592 | |
593 | bool IsCmpxchg = Call->Builtin->Name.contains(Other: "cmpxchg" ); |
594 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
595 | |
596 | Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.) |
597 | Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected). |
598 | Register Desired = Call->Arguments[2]; // Value (C Desired). |
599 | MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass); |
600 | MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass); |
601 | MRI->setRegClass(Desired, &SPIRV::IDRegClass); |
602 | SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(VReg: Desired); |
603 | LLT DesiredLLT = MRI->getType(Reg: Desired); |
604 | |
605 | assert(GR->getSPIRVTypeForVReg(ObjectPtr)->getOpcode() == |
606 | SPIRV::OpTypePointer); |
607 | unsigned ExpectedType = GR->getSPIRVTypeForVReg(VReg: ExpectedArg)->getOpcode(); |
608 | (void)ExpectedType; |
609 | assert(IsCmpxchg ? ExpectedType == SPIRV::OpTypeInt |
610 | : ExpectedType == SPIRV::OpTypePointer); |
611 | assert(GR->isScalarOfType(Desired, SPIRV::OpTypeInt)); |
612 | |
613 | SPIRVType *SpvObjectPtrTy = GR->getSPIRVTypeForVReg(VReg: ObjectPtr); |
614 | assert(SpvObjectPtrTy->getOperand(2).isReg() && "SPIRV type is expected" ); |
615 | auto StorageClass = static_cast<SPIRV::StorageClass::StorageClass>( |
616 | SpvObjectPtrTy->getOperand(i: 1).getImm()); |
617 | auto MemSemStorage = getMemSemanticsForStorageClass(StorageClass); |
618 | |
619 | Register MemSemEqualReg; |
620 | Register MemSemUnequalReg; |
621 | uint64_t MemSemEqual = |
622 | IsCmpxchg |
623 | ? SPIRV::MemorySemantics::None |
624 | : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage; |
625 | uint64_t MemSemUnequal = |
626 | IsCmpxchg |
627 | ? SPIRV::MemorySemantics::None |
628 | : SPIRV::MemorySemantics::SequentiallyConsistent | MemSemStorage; |
629 | if (Call->Arguments.size() >= 4) { |
630 | assert(Call->Arguments.size() >= 5 && |
631 | "Need 5+ args for explicit atomic cmpxchg" ); |
632 | auto MemOrdEq = |
633 | static_cast<std::memory_order>(getIConstVal(ConstReg: Call->Arguments[3], MRI)); |
634 | auto MemOrdNeq = |
635 | static_cast<std::memory_order>(getIConstVal(ConstReg: Call->Arguments[4], MRI)); |
636 | MemSemEqual = getSPIRVMemSemantics(MemOrdEq) | MemSemStorage; |
637 | MemSemUnequal = getSPIRVMemSemantics(MemOrdNeq) | MemSemStorage; |
638 | if (MemOrdEq == MemSemEqual) |
639 | MemSemEqualReg = Call->Arguments[3]; |
640 | if (MemOrdNeq == MemSemEqual) |
641 | MemSemUnequalReg = Call->Arguments[4]; |
642 | MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass); |
643 | MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass); |
644 | } |
645 | if (!MemSemEqualReg.isValid()) |
646 | MemSemEqualReg = buildConstantIntReg(Val: MemSemEqual, MIRBuilder, GR); |
647 | if (!MemSemUnequalReg.isValid()) |
648 | MemSemUnequalReg = buildConstantIntReg(Val: MemSemUnequal, MIRBuilder, GR); |
649 | |
650 | Register ScopeReg; |
651 | auto Scope = IsCmpxchg ? SPIRV::Scope::Workgroup : SPIRV::Scope::Device; |
652 | if (Call->Arguments.size() >= 6) { |
653 | assert(Call->Arguments.size() == 6 && |
654 | "Extra args for explicit atomic cmpxchg" ); |
655 | auto ClScope = static_cast<SPIRV::CLMemoryScope>( |
656 | getIConstVal(ConstReg: Call->Arguments[5], MRI)); |
657 | Scope = getSPIRVScope(ClScope); |
658 | if (ClScope == static_cast<unsigned>(Scope)) |
659 | ScopeReg = Call->Arguments[5]; |
660 | MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass); |
661 | } |
662 | if (!ScopeReg.isValid()) |
663 | ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR); |
664 | |
665 | Register Expected = IsCmpxchg |
666 | ? ExpectedArg |
667 | : buildLoadInst(BaseType: SpvDesiredTy, PtrRegister: ExpectedArg, MIRBuilder, |
668 | GR, LowLevelType: LLT::scalar(SizeInBits: 32)); |
669 | MRI->setType(VReg: Expected, Ty: DesiredLLT); |
670 | Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(Ty: DesiredLLT) |
671 | : Call->ReturnRegister; |
672 | if (!MRI->getRegClassOrNull(Tmp)) |
673 | MRI->setRegClass(Tmp, &SPIRV::IDRegClass); |
674 | GR->assignSPIRVTypeToVReg(Type: SpvDesiredTy, VReg: Tmp, MF&: MIRBuilder.getMF()); |
675 | |
676 | SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder); |
677 | MIRBuilder.buildInstr(Opcode) |
678 | .addDef(RegNo: Tmp) |
679 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: IntTy)) |
680 | .addUse(RegNo: ObjectPtr) |
681 | .addUse(RegNo: ScopeReg) |
682 | .addUse(RegNo: MemSemEqualReg) |
683 | .addUse(RegNo: MemSemUnequalReg) |
684 | .addUse(RegNo: Desired) |
685 | .addUse(RegNo: Expected); |
686 | if (!IsCmpxchg) { |
687 | MIRBuilder.buildInstr(SPIRV::OpStore).addUse(ExpectedArg).addUse(Tmp); |
688 | MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: Call->ReturnRegister, Op0: Tmp, Op1: Expected); |
689 | } |
690 | return true; |
691 | } |
692 | |
693 | /// Helper function for building an atomic load instruction. |
694 | static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode, |
695 | MachineIRBuilder &MIRBuilder, |
696 | SPIRVGlobalRegistry *GR) { |
697 | if (Call->isSpirvOp()) |
698 | return buildOpFromWrapper(MIRBuilder, Opcode, Call, |
699 | TypeReg: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
700 | |
701 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
702 | Register ScopeRegister = |
703 | Call->Arguments.size() >= 4 ? Call->Arguments[3] : Register(); |
704 | |
705 | assert(Call->Arguments.size() <= 4 && |
706 | "Too many args for explicit atomic RMW" ); |
707 | ScopeRegister = buildScopeReg(ScopeRegister, SPIRV::Scope::Workgroup, |
708 | MIRBuilder, GR, MRI); |
709 | |
710 | Register PtrRegister = Call->Arguments[0]; |
711 | unsigned Semantics = SPIRV::MemorySemantics::None; |
712 | MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass); |
713 | Register MemSemanticsReg = |
714 | Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register(); |
715 | MemSemanticsReg = buildMemSemanticsReg(SemanticsRegister: MemSemanticsReg, PtrRegister, |
716 | Semantics, MIRBuilder, GR); |
717 | MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
718 | MIRBuilder.buildInstr(Opcode) |
719 | .addDef(RegNo: Call->ReturnRegister) |
720 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
721 | .addUse(RegNo: PtrRegister) |
722 | .addUse(RegNo: ScopeRegister) |
723 | .addUse(RegNo: MemSemanticsReg) |
724 | .addUse(RegNo: Call->Arguments[1]); |
725 | return true; |
726 | } |
727 | |
728 | /// Helper function for building an atomic floating-type instruction. |
729 | static bool buildAtomicFloatingRMWInst(const SPIRV::IncomingCall *Call, |
730 | unsigned Opcode, |
731 | MachineIRBuilder &MIRBuilder, |
732 | SPIRVGlobalRegistry *GR) { |
733 | assert(Call->Arguments.size() == 4 && |
734 | "Wrong number of atomic floating-type builtin" ); |
735 | |
736 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
737 | |
738 | Register PtrReg = Call->Arguments[0]; |
739 | MRI->setRegClass(PtrReg, &SPIRV::IDRegClass); |
740 | |
741 | Register ScopeReg = Call->Arguments[1]; |
742 | MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass); |
743 | |
744 | Register MemSemanticsReg = Call->Arguments[2]; |
745 | MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass); |
746 | |
747 | Register ValueReg = Call->Arguments[3]; |
748 | MRI->setRegClass(ValueReg, &SPIRV::IDRegClass); |
749 | |
750 | MIRBuilder.buildInstr(Opcode) |
751 | .addDef(RegNo: Call->ReturnRegister) |
752 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
753 | .addUse(RegNo: PtrReg) |
754 | .addUse(RegNo: ScopeReg) |
755 | .addUse(RegNo: MemSemanticsReg) |
756 | .addUse(RegNo: ValueReg); |
757 | return true; |
758 | } |
759 | |
760 | /// Helper function for building atomic flag instructions (e.g. |
761 | /// OpAtomicFlagTestAndSet). |
762 | static bool buildAtomicFlagInst(const SPIRV::IncomingCall *Call, |
763 | unsigned Opcode, MachineIRBuilder &MIRBuilder, |
764 | SPIRVGlobalRegistry *GR) { |
765 | bool IsSet = Opcode == SPIRV::OpAtomicFlagTestAndSet; |
766 | Register TypeReg = GR->getSPIRVTypeID(SpirvType: Call->ReturnType); |
767 | if (Call->isSpirvOp()) |
768 | return buildOpFromWrapper(MIRBuilder, Opcode, Call, |
769 | TypeReg: IsSet ? TypeReg : Register(0)); |
770 | |
771 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
772 | Register PtrRegister = Call->Arguments[0]; |
773 | unsigned Semantics = SPIRV::MemorySemantics::SequentiallyConsistent; |
774 | Register MemSemanticsReg = |
775 | Call->Arguments.size() >= 2 ? Call->Arguments[1] : Register(); |
776 | MemSemanticsReg = buildMemSemanticsReg(SemanticsRegister: MemSemanticsReg, PtrRegister, |
777 | Semantics, MIRBuilder, GR); |
778 | |
779 | assert((Opcode != SPIRV::OpAtomicFlagClear || |
780 | (Semantics != SPIRV::MemorySemantics::Acquire && |
781 | Semantics != SPIRV::MemorySemantics::AcquireRelease)) && |
782 | "Invalid memory order argument!" ); |
783 | |
784 | Register ScopeRegister = |
785 | Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register(); |
786 | ScopeRegister = |
787 | buildScopeReg(ScopeRegister, SPIRV::Scope::Device, MIRBuilder, GR, MRI); |
788 | |
789 | auto MIB = MIRBuilder.buildInstr(Opcode); |
790 | if (IsSet) |
791 | MIB.addDef(RegNo: Call->ReturnRegister).addUse(RegNo: TypeReg); |
792 | |
793 | MIB.addUse(RegNo: PtrRegister).addUse(RegNo: ScopeRegister).addUse(RegNo: MemSemanticsReg); |
794 | return true; |
795 | } |
796 | |
797 | /// Helper function for building barriers, i.e., memory/control ordering |
798 | /// operations. |
799 | static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode, |
800 | MachineIRBuilder &MIRBuilder, |
801 | SPIRVGlobalRegistry *GR) { |
802 | if (Call->isSpirvOp()) |
803 | return buildOpFromWrapper(MIRBuilder, Opcode, Call); |
804 | |
805 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
806 | unsigned MemFlags = getIConstVal(ConstReg: Call->Arguments[0], MRI); |
807 | unsigned MemSemantics = SPIRV::MemorySemantics::None; |
808 | |
809 | if (MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) |
810 | MemSemantics |= SPIRV::MemorySemantics::WorkgroupMemory; |
811 | |
812 | if (MemFlags & SPIRV::CLK_GLOBAL_MEM_FENCE) |
813 | MemSemantics |= SPIRV::MemorySemantics::CrossWorkgroupMemory; |
814 | |
815 | if (MemFlags & SPIRV::CLK_IMAGE_MEM_FENCE) |
816 | MemSemantics |= SPIRV::MemorySemantics::ImageMemory; |
817 | |
818 | if (Opcode == SPIRV::OpMemoryBarrier) { |
819 | std::memory_order MemOrder = |
820 | static_cast<std::memory_order>(getIConstVal(ConstReg: Call->Arguments[1], MRI)); |
821 | MemSemantics = getSPIRVMemSemantics(MemOrder) | MemSemantics; |
822 | } else { |
823 | MemSemantics |= SPIRV::MemorySemantics::SequentiallyConsistent; |
824 | } |
825 | |
826 | Register MemSemanticsReg; |
827 | if (MemFlags == MemSemantics) { |
828 | MemSemanticsReg = Call->Arguments[0]; |
829 | MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass); |
830 | } else |
831 | MemSemanticsReg = buildConstantIntReg(Val: MemSemantics, MIRBuilder, GR); |
832 | |
833 | Register ScopeReg; |
834 | SPIRV::Scope::Scope Scope = SPIRV::Scope::Workgroup; |
835 | SPIRV::Scope::Scope MemScope = Scope; |
836 | if (Call->Arguments.size() >= 2) { |
837 | assert( |
838 | ((Opcode != SPIRV::OpMemoryBarrier && Call->Arguments.size() == 2) || |
839 | (Opcode == SPIRV::OpMemoryBarrier && Call->Arguments.size() == 3)) && |
840 | "Extra args for explicitly scoped barrier" ); |
841 | Register ScopeArg = (Opcode == SPIRV::OpMemoryBarrier) ? Call->Arguments[2] |
842 | : Call->Arguments[1]; |
843 | SPIRV::CLMemoryScope CLScope = |
844 | static_cast<SPIRV::CLMemoryScope>(getIConstVal(ScopeArg, MRI)); |
845 | MemScope = getSPIRVScope(CLScope); |
846 | if (!(MemFlags & SPIRV::CLK_LOCAL_MEM_FENCE) || |
847 | (Opcode == SPIRV::OpMemoryBarrier)) |
848 | Scope = MemScope; |
849 | |
850 | if (CLScope == static_cast<unsigned>(Scope)) { |
851 | ScopeReg = Call->Arguments[1]; |
852 | MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass); |
853 | } |
854 | } |
855 | |
856 | if (!ScopeReg.isValid()) |
857 | ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR); |
858 | |
859 | auto MIB = MIRBuilder.buildInstr(Opcode).addUse(RegNo: ScopeReg); |
860 | if (Opcode != SPIRV::OpMemoryBarrier) |
861 | MIB.addUse(RegNo: buildConstantIntReg(MemScope, MIRBuilder, GR)); |
862 | MIB.addUse(RegNo: MemSemanticsReg); |
863 | return true; |
864 | } |
865 | |
866 | static unsigned getNumComponentsForDim(SPIRV::Dim::Dim dim) { |
867 | switch (dim) { |
868 | case SPIRV::Dim::DIM_1D: |
869 | case SPIRV::Dim::DIM_Buffer: |
870 | return 1; |
871 | case SPIRV::Dim::DIM_2D: |
872 | case SPIRV::Dim::DIM_Cube: |
873 | case SPIRV::Dim::DIM_Rect: |
874 | return 2; |
875 | case SPIRV::Dim::DIM_3D: |
876 | return 3; |
877 | default: |
878 | report_fatal_error(reason: "Cannot get num components for given Dim" ); |
879 | } |
880 | } |
881 | |
882 | /// Helper function for obtaining the number of size components. |
883 | static unsigned getNumSizeComponents(SPIRVType *imgType) { |
884 | assert(imgType->getOpcode() == SPIRV::OpTypeImage); |
885 | auto dim = static_cast<SPIRV::Dim::Dim>(imgType->getOperand(i: 2).getImm()); |
886 | unsigned numComps = getNumComponentsForDim(dim); |
887 | bool arrayed = imgType->getOperand(i: 4).getImm() == 1; |
888 | return arrayed ? numComps + 1 : numComps; |
889 | } |
890 | |
891 | //===----------------------------------------------------------------------===// |
892 | // Implementation functions for each builtin group |
893 | //===----------------------------------------------------------------------===// |
894 | |
895 | static bool generateExtInst(const SPIRV::IncomingCall *Call, |
896 | MachineIRBuilder &MIRBuilder, |
897 | SPIRVGlobalRegistry *GR) { |
898 | // Lookup the extended instruction number in the TableGen records. |
899 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
900 | uint32_t Number = |
901 | SPIRV::lookupExtendedBuiltin(Builtin->Name, Builtin->Set)->Number; |
902 | |
903 | // Build extended instruction. |
904 | auto MIB = |
905 | MIRBuilder.buildInstr(SPIRV::OpExtInst) |
906 | .addDef(Call->ReturnRegister) |
907 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
908 | .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std)) |
909 | .addImm(Number); |
910 | |
911 | for (auto Argument : Call->Arguments) |
912 | MIB.addUse(Argument); |
913 | return true; |
914 | } |
915 | |
916 | static bool generateRelationalInst(const SPIRV::IncomingCall *Call, |
917 | MachineIRBuilder &MIRBuilder, |
918 | SPIRVGlobalRegistry *GR) { |
919 | // Lookup the instruction opcode in the TableGen records. |
920 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
921 | unsigned Opcode = |
922 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
923 | |
924 | Register CompareRegister; |
925 | SPIRVType *RelationType; |
926 | std::tie(CompareRegister, RelationType) = |
927 | buildBoolRegister(MIRBuilder, Call->ReturnType, GR); |
928 | |
929 | // Build relational instruction. |
930 | auto MIB = MIRBuilder.buildInstr(Opcode) |
931 | .addDef(RegNo: CompareRegister) |
932 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: RelationType)); |
933 | |
934 | for (auto Argument : Call->Arguments) |
935 | MIB.addUse(RegNo: Argument); |
936 | |
937 | // Build select instruction. |
938 | return buildSelectInst(MIRBuilder, ReturnRegister: Call->ReturnRegister, SourceRegister: CompareRegister, |
939 | ReturnType: Call->ReturnType, GR); |
940 | } |
941 | |
942 | static bool generateGroupInst(const SPIRV::IncomingCall *Call, |
943 | MachineIRBuilder &MIRBuilder, |
944 | SPIRVGlobalRegistry *GR) { |
945 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
946 | const SPIRV::GroupBuiltin *GroupBuiltin = |
947 | SPIRV::lookupGroupBuiltin(Builtin->Name); |
948 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
949 | Register Arg0; |
950 | if (GroupBuiltin->HasBoolArg) { |
951 | Register ConstRegister = Call->Arguments[0]; |
952 | auto ArgInstruction = getDefInstrMaybeConstant(ConstReg&: ConstRegister, MRI); |
953 | (void)ArgInstruction; |
954 | // TODO: support non-constant bool values. |
955 | assert(ArgInstruction->getOpcode() == TargetOpcode::G_CONSTANT && |
956 | "Only constant bool value args are supported" ); |
957 | if (GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode() != |
958 | SPIRV::OpTypeBool) |
959 | Arg0 = GR->buildConstantInt(Val: getIConstVal(ConstReg: ConstRegister, MRI), MIRBuilder, |
960 | SpvType: GR->getOrCreateSPIRVBoolType(MIRBuilder)); |
961 | } |
962 | |
963 | Register GroupResultRegister = Call->ReturnRegister; |
964 | SPIRVType *GroupResultType = Call->ReturnType; |
965 | |
966 | // TODO: maybe we need to check whether the result type is already boolean |
967 | // and in this case do not insert select instruction. |
968 | const bool HasBoolReturnTy = |
969 | GroupBuiltin->IsElect || GroupBuiltin->IsAllOrAny || |
970 | GroupBuiltin->IsAllEqual || GroupBuiltin->IsLogical || |
971 | GroupBuiltin->IsInverseBallot || GroupBuiltin->IsBallotBitExtract; |
972 | |
973 | if (HasBoolReturnTy) |
974 | std::tie(GroupResultRegister, GroupResultType) = |
975 | buildBoolRegister(MIRBuilder, Call->ReturnType, GR); |
976 | |
977 | auto Scope = Builtin->Name.starts_with("sub_group" ) ? SPIRV::Scope::Subgroup |
978 | : SPIRV::Scope::Workgroup; |
979 | Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR); |
980 | |
981 | // Build work/sub group instruction. |
982 | auto MIB = MIRBuilder.buildInstr(Opcode: GroupBuiltin->Opcode) |
983 | .addDef(RegNo: GroupResultRegister) |
984 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: GroupResultType)) |
985 | .addUse(RegNo: ScopeRegister); |
986 | |
987 | if (!GroupBuiltin->NoGroupOperation) |
988 | MIB.addImm(GroupBuiltin->GroupOperation); |
989 | if (Call->Arguments.size() > 0) { |
990 | MIB.addUse(Arg0.isValid() ? Arg0 : Call->Arguments[0]); |
991 | MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
992 | for (unsigned i = 1; i < Call->Arguments.size(); i++) { |
993 | MIB.addUse(Call->Arguments[i]); |
994 | MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass); |
995 | } |
996 | } |
997 | |
998 | // Build select instruction. |
999 | if (HasBoolReturnTy) |
1000 | buildSelectInst(MIRBuilder, ReturnRegister: Call->ReturnRegister, SourceRegister: GroupResultRegister, |
1001 | ReturnType: Call->ReturnType, GR); |
1002 | return true; |
1003 | } |
1004 | |
1005 | static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call, |
1006 | MachineIRBuilder &MIRBuilder, |
1007 | SPIRVGlobalRegistry *GR) { |
1008 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1009 | MachineFunction &MF = MIRBuilder.getMF(); |
1010 | const auto *ST = static_cast<const SPIRVSubtarget *>(&MF.getSubtarget()); |
1011 | if (!ST->canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) { |
1012 | std::string DiagMsg = std::string(Builtin->Name) + |
1013 | ": the builtin requires the following SPIR-V " |
1014 | "extension: SPV_INTEL_subgroups" ; |
1015 | report_fatal_error(reason: DiagMsg.c_str(), gen_crash_diag: false); |
1016 | } |
1017 | const SPIRV::IntelSubgroupsBuiltin *IntelSubgroups = |
1018 | SPIRV::lookupIntelSubgroupsBuiltin(Builtin->Name); |
1019 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1020 | |
1021 | uint32_t OpCode = IntelSubgroups->Opcode; |
1022 | if (IntelSubgroups->IsBlock) { |
1023 | // Minimal number or arguments set in TableGen records is 1 |
1024 | if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(VReg: Call->Arguments[0])) { |
1025 | if (Arg0Type->getOpcode() == SPIRV::OpTypeImage) { |
1026 | // TODO: add required validation from the specification: |
1027 | // "'Image' must be an object whose type is OpTypeImage with a 'Sampled' |
1028 | // operand of 0 or 2. If the 'Sampled' operand is 2, then some |
1029 | // dimensions require a capability." |
1030 | switch (OpCode) { |
1031 | case SPIRV::OpSubgroupBlockReadINTEL: |
1032 | OpCode = SPIRV::OpSubgroupImageBlockReadINTEL; |
1033 | break; |
1034 | case SPIRV::OpSubgroupBlockWriteINTEL: |
1035 | OpCode = SPIRV::OpSubgroupImageBlockWriteINTEL; |
1036 | break; |
1037 | } |
1038 | } |
1039 | } |
1040 | } |
1041 | |
1042 | // TODO: opaque pointers types should be eventually resolved in such a way |
1043 | // that validation of block read is enabled with respect to the following |
1044 | // specification requirement: |
1045 | // "'Result Type' may be a scalar or vector type, and its component type must |
1046 | // be equal to the type pointed to by 'Ptr'." |
1047 | // For example, function parameter type should not be default i8 pointer, but |
1048 | // depend on the result type of the instruction where it is used as a pointer |
1049 | // argument of OpSubgroupBlockReadINTEL |
1050 | |
1051 | // Build Intel subgroups instruction |
1052 | MachineInstrBuilder MIB = |
1053 | IntelSubgroups->IsWrite |
1054 | ? MIRBuilder.buildInstr(Opcode: OpCode) |
1055 | : MIRBuilder.buildInstr(Opcode: OpCode) |
1056 | .addDef(RegNo: Call->ReturnRegister) |
1057 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
1058 | for (size_t i = 0; i < Call->Arguments.size(); ++i) { |
1059 | MIB.addUse(RegNo: Call->Arguments[i]); |
1060 | MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass); |
1061 | } |
1062 | |
1063 | return true; |
1064 | } |
1065 | |
1066 | static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call, |
1067 | MachineIRBuilder &MIRBuilder, |
1068 | SPIRVGlobalRegistry *GR) { |
1069 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1070 | MachineFunction &MF = MIRBuilder.getMF(); |
1071 | const auto *ST = static_cast<const SPIRVSubtarget *>(&MF.getSubtarget()); |
1072 | if (!ST->canUseExtension( |
1073 | SPIRV::Extension::SPV_KHR_uniform_group_instructions)) { |
1074 | std::string DiagMsg = std::string(Builtin->Name) + |
1075 | ": the builtin requires the following SPIR-V " |
1076 | "extension: SPV_KHR_uniform_group_instructions" ; |
1077 | report_fatal_error(reason: DiagMsg.c_str(), gen_crash_diag: false); |
1078 | } |
1079 | const SPIRV::GroupUniformBuiltin *GroupUniform = |
1080 | SPIRV::lookupGroupUniformBuiltin(Builtin->Name); |
1081 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1082 | |
1083 | Register GroupResultReg = Call->ReturnRegister; |
1084 | MRI->setRegClass(GroupResultReg, &SPIRV::IDRegClass); |
1085 | |
1086 | // Scope |
1087 | Register ScopeReg = Call->Arguments[0]; |
1088 | MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass); |
1089 | |
1090 | // Group Operation |
1091 | Register ConstGroupOpReg = Call->Arguments[1]; |
1092 | const MachineInstr *Const = getDefInstrMaybeConstant(ConstReg&: ConstGroupOpReg, MRI); |
1093 | if (!Const || Const->getOpcode() != TargetOpcode::G_CONSTANT) |
1094 | report_fatal_error( |
1095 | reason: "expect a constant group operation for a uniform group instruction" , |
1096 | gen_crash_diag: false); |
1097 | const MachineOperand &ConstOperand = Const->getOperand(i: 1); |
1098 | if (!ConstOperand.isCImm()) |
1099 | report_fatal_error(reason: "uniform group instructions: group operation must be an " |
1100 | "integer constant" , |
1101 | gen_crash_diag: false); |
1102 | |
1103 | // Value |
1104 | Register ValueReg = Call->Arguments[2]; |
1105 | MRI->setRegClass(ValueReg, &SPIRV::IDRegClass); |
1106 | |
1107 | auto MIB = MIRBuilder.buildInstr(Opcode: GroupUniform->Opcode) |
1108 | .addDef(RegNo: GroupResultReg) |
1109 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
1110 | .addUse(RegNo: ScopeReg); |
1111 | addNumImm(Imm: ConstOperand.getCImm()->getValue(), MIB); |
1112 | MIB.addUse(RegNo: ValueReg); |
1113 | |
1114 | return true; |
1115 | } |
1116 | |
1117 | // These queries ask for a single size_t result for a given dimension index, e.g |
1118 | // size_t get_global_id(uint dimindex). In SPIR-V, the builtins corresonding to |
1119 | // these values are all vec3 types, so we need to extract the correct index or |
1120 | // return defaultVal (0 or 1 depending on the query). We also handle extending |
1121 | // or tuncating in case size_t does not match the expected result type's |
1122 | // bitwidth. |
1123 | // |
1124 | // For a constant index >= 3 we generate: |
1125 | // %res = OpConstant %SizeT 0 |
1126 | // |
1127 | // For other indices we generate: |
1128 | // %g = OpVariable %ptr_V3_SizeT Input |
1129 | // OpDecorate %g BuiltIn XXX |
1130 | // OpDecorate %g LinkageAttributes "__spirv_BuiltInXXX" |
1131 | // OpDecorate %g Constant |
1132 | // %loadedVec = OpLoad %V3_SizeT %g |
1133 | // |
1134 | // Then, if the index is constant < 3, we generate: |
1135 | // %res = OpCompositeExtract %SizeT %loadedVec idx |
1136 | // If the index is dynamic, we generate: |
1137 | // %tmp = OpVectorExtractDynamic %SizeT %loadedVec %idx |
1138 | // %cmp = OpULessThan %bool %idx %const_3 |
1139 | // %res = OpSelect %SizeT %cmp %tmp %const_0 |
1140 | // |
1141 | // If the bitwidth of %res does not match the expected return type, we add an |
1142 | // extend or truncate. |
1143 | static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call, |
1144 | MachineIRBuilder &MIRBuilder, |
1145 | SPIRVGlobalRegistry *GR, |
1146 | SPIRV::BuiltIn::BuiltIn BuiltinValue, |
1147 | uint64_t DefaultValue) { |
1148 | Register IndexRegister = Call->Arguments[0]; |
1149 | const unsigned ResultWidth = Call->ReturnType->getOperand(i: 1).getImm(); |
1150 | const unsigned PointerSize = GR->getPointerSize(); |
1151 | const SPIRVType *PointerSizeType = |
1152 | GR->getOrCreateSPIRVIntegerType(BitWidth: PointerSize, MIRBuilder); |
1153 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1154 | auto IndexInstruction = getDefInstrMaybeConstant(ConstReg&: IndexRegister, MRI); |
1155 | |
1156 | // Set up the final register to do truncation or extension on at the end. |
1157 | Register ToTruncate = Call->ReturnRegister; |
1158 | |
1159 | // If the index is constant, we can statically determine if it is in range. |
1160 | bool IsConstantIndex = |
1161 | IndexInstruction->getOpcode() == TargetOpcode::G_CONSTANT; |
1162 | |
1163 | // If it's out of range (max dimension is 3), we can just return the constant |
1164 | // default value (0 or 1 depending on which query function). |
1165 | if (IsConstantIndex && getIConstVal(ConstReg: IndexRegister, MRI) >= 3) { |
1166 | Register DefaultReg = Call->ReturnRegister; |
1167 | if (PointerSize != ResultWidth) { |
1168 | DefaultReg = MRI->createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: PointerSize)); |
1169 | MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass); |
1170 | GR->assignSPIRVTypeToVReg(Type: PointerSizeType, VReg: DefaultReg, |
1171 | MF&: MIRBuilder.getMF()); |
1172 | ToTruncate = DefaultReg; |
1173 | } |
1174 | auto NewRegister = |
1175 | GR->buildConstantInt(Val: DefaultValue, MIRBuilder, SpvType: PointerSizeType); |
1176 | MIRBuilder.buildCopy(Res: DefaultReg, Op: NewRegister); |
1177 | } else { // If it could be in range, we need to load from the given builtin. |
1178 | auto Vec3Ty = |
1179 | GR->getOrCreateSPIRVVectorType(BaseType: PointerSizeType, NumElements: 3, MIRBuilder); |
1180 | Register LoadedVector = |
1181 | buildBuiltinVariableLoad(MIRBuilder, Vec3Ty, GR, BuiltinValue, |
1182 | LLT::fixed_vector(3, PointerSize)); |
1183 | // Set up the vreg to extract the result to (possibly a new temporary one). |
1184 | Register = Call->ReturnRegister; |
1185 | if (!IsConstantIndex || PointerSize != ResultWidth) { |
1186 | Extracted = MRI->createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: PointerSize)); |
1187 | MRI->setRegClass(Extracted, &SPIRV::IDRegClass); |
1188 | GR->assignSPIRVTypeToVReg(Type: PointerSizeType, VReg: Extracted, MF&: MIRBuilder.getMF()); |
1189 | } |
1190 | // Use Intrinsic::spv_extractelt so dynamic vs static extraction is |
1191 | // handled later: extr = spv_extractelt LoadedVector, IndexRegister. |
1192 | MachineInstrBuilder = MIRBuilder.buildIntrinsic( |
1193 | Intrinsic::spv_extractelt, ArrayRef<Register>{Extracted}, true, false); |
1194 | ExtractInst.addUse(RegNo: LoadedVector).addUse(RegNo: IndexRegister); |
1195 | |
1196 | // If the index is dynamic, need check if it's < 3, and then use a select. |
1197 | if (!IsConstantIndex) { |
1198 | insertAssignInstr(Reg: Extracted, Ty: nullptr, SpirvTy: PointerSizeType, GR, MIB&: MIRBuilder, |
1199 | MRI&: *MRI); |
1200 | |
1201 | auto IndexType = GR->getSPIRVTypeForVReg(VReg: IndexRegister); |
1202 | auto BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder); |
1203 | |
1204 | Register CompareRegister = |
1205 | MRI->createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: 1)); |
1206 | MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass); |
1207 | GR->assignSPIRVTypeToVReg(Type: BoolType, VReg: CompareRegister, MF&: MIRBuilder.getMF()); |
1208 | |
1209 | // Use G_ICMP to check if idxVReg < 3. |
1210 | MIRBuilder.buildICmp(Pred: CmpInst::ICMP_ULT, Res: CompareRegister, Op0: IndexRegister, |
1211 | Op1: GR->buildConstantInt(Val: 3, MIRBuilder, SpvType: IndexType)); |
1212 | |
1213 | // Get constant for the default value (0 or 1 depending on which |
1214 | // function). |
1215 | Register DefaultRegister = |
1216 | GR->buildConstantInt(Val: DefaultValue, MIRBuilder, SpvType: PointerSizeType); |
1217 | |
1218 | // Get a register for the selection result (possibly a new temporary one). |
1219 | Register SelectionResult = Call->ReturnRegister; |
1220 | if (PointerSize != ResultWidth) { |
1221 | SelectionResult = |
1222 | MRI->createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: PointerSize)); |
1223 | MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass); |
1224 | GR->assignSPIRVTypeToVReg(Type: PointerSizeType, VReg: SelectionResult, |
1225 | MF&: MIRBuilder.getMF()); |
1226 | } |
1227 | // Create the final G_SELECT to return the extracted value or the default. |
1228 | MIRBuilder.buildSelect(Res: SelectionResult, Tst: CompareRegister, Op0: Extracted, |
1229 | Op1: DefaultRegister); |
1230 | ToTruncate = SelectionResult; |
1231 | } else { |
1232 | ToTruncate = Extracted; |
1233 | } |
1234 | } |
1235 | // Alter the result's bitwidth if it does not match the SizeT value extracted. |
1236 | if (PointerSize != ResultWidth) |
1237 | MIRBuilder.buildZExtOrTrunc(Res: Call->ReturnRegister, Op: ToTruncate); |
1238 | return true; |
1239 | } |
1240 | |
1241 | static bool generateBuiltinVar(const SPIRV::IncomingCall *Call, |
1242 | MachineIRBuilder &MIRBuilder, |
1243 | SPIRVGlobalRegistry *GR) { |
1244 | // Lookup the builtin variable record. |
1245 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1246 | SPIRV::BuiltIn::BuiltIn Value = |
1247 | SPIRV::lookupGetBuiltin(Builtin->Name, Builtin->Set)->Value; |
1248 | |
1249 | if (Value == SPIRV::BuiltIn::GlobalInvocationId) |
1250 | return genWorkgroupQuery(Call, MIRBuilder, GR, Value, 0); |
1251 | |
1252 | // Build a load instruction for the builtin variable. |
1253 | unsigned BitWidth = GR->getScalarOrVectorBitWidth(Type: Call->ReturnType); |
1254 | LLT LLType; |
1255 | if (Call->ReturnType->getOpcode() == SPIRV::OpTypeVector) |
1256 | LLType = |
1257 | LLT::fixed_vector(NumElements: Call->ReturnType->getOperand(i: 2).getImm(), ScalarSizeInBits: BitWidth); |
1258 | else |
1259 | LLType = LLT::scalar(SizeInBits: BitWidth); |
1260 | |
1261 | return buildBuiltinVariableLoad(MIRBuilder, Call->ReturnType, GR, Value, |
1262 | LLType, Call->ReturnRegister); |
1263 | } |
1264 | |
1265 | static bool generateAtomicInst(const SPIRV::IncomingCall *Call, |
1266 | MachineIRBuilder &MIRBuilder, |
1267 | SPIRVGlobalRegistry *GR) { |
1268 | // Lookup the instruction opcode in the TableGen records. |
1269 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1270 | unsigned Opcode = |
1271 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
1272 | |
1273 | switch (Opcode) { |
1274 | case SPIRV::OpStore: |
1275 | return buildAtomicInitInst(Call, MIRBuilder); |
1276 | case SPIRV::OpAtomicLoad: |
1277 | return buildAtomicLoadInst(Call, MIRBuilder, GR); |
1278 | case SPIRV::OpAtomicStore: |
1279 | return buildAtomicStoreInst(Call, MIRBuilder, GR); |
1280 | case SPIRV::OpAtomicCompareExchange: |
1281 | case SPIRV::OpAtomicCompareExchangeWeak: |
1282 | return buildAtomicCompareExchangeInst(Call, Builtin, Opcode, MIRBuilder, |
1283 | GR); |
1284 | case SPIRV::OpAtomicIAdd: |
1285 | case SPIRV::OpAtomicISub: |
1286 | case SPIRV::OpAtomicOr: |
1287 | case SPIRV::OpAtomicXor: |
1288 | case SPIRV::OpAtomicAnd: |
1289 | case SPIRV::OpAtomicExchange: |
1290 | return buildAtomicRMWInst(Call, Opcode, MIRBuilder, GR); |
1291 | case SPIRV::OpMemoryBarrier: |
1292 | return buildBarrierInst(Call, SPIRV::OpMemoryBarrier, MIRBuilder, GR); |
1293 | case SPIRV::OpAtomicFlagTestAndSet: |
1294 | case SPIRV::OpAtomicFlagClear: |
1295 | return buildAtomicFlagInst(Call, Opcode, MIRBuilder, GR); |
1296 | default: |
1297 | return false; |
1298 | } |
1299 | } |
1300 | |
1301 | static bool generateAtomicFloatingInst(const SPIRV::IncomingCall *Call, |
1302 | MachineIRBuilder &MIRBuilder, |
1303 | SPIRVGlobalRegistry *GR) { |
1304 | // Lookup the instruction opcode in the TableGen records. |
1305 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1306 | unsigned Opcode = SPIRV::lookupAtomicFloatingBuiltin(Builtin->Name)->Opcode; |
1307 | |
1308 | switch (Opcode) { |
1309 | case SPIRV::OpAtomicFAddEXT: |
1310 | case SPIRV::OpAtomicFMinEXT: |
1311 | case SPIRV::OpAtomicFMaxEXT: |
1312 | return buildAtomicFloatingRMWInst(Call, Opcode, MIRBuilder, GR); |
1313 | default: |
1314 | return false; |
1315 | } |
1316 | } |
1317 | |
1318 | static bool generateBarrierInst(const SPIRV::IncomingCall *Call, |
1319 | MachineIRBuilder &MIRBuilder, |
1320 | SPIRVGlobalRegistry *GR) { |
1321 | // Lookup the instruction opcode in the TableGen records. |
1322 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1323 | unsigned Opcode = |
1324 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
1325 | |
1326 | return buildBarrierInst(Call, Opcode, MIRBuilder, GR); |
1327 | } |
1328 | |
1329 | static bool generateDotOrFMulInst(const SPIRV::IncomingCall *Call, |
1330 | MachineIRBuilder &MIRBuilder, |
1331 | SPIRVGlobalRegistry *GR) { |
1332 | unsigned Opcode = GR->getSPIRVTypeForVReg(VReg: Call->Arguments[0])->getOpcode(); |
1333 | bool IsVec = Opcode == SPIRV::OpTypeVector; |
1334 | // Use OpDot only in case of vector args and OpFMul in case of scalar args. |
1335 | MIRBuilder.buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS) |
1336 | .addDef(Call->ReturnRegister) |
1337 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1338 | .addUse(Call->Arguments[0]) |
1339 | .addUse(Call->Arguments[1]); |
1340 | return true; |
1341 | } |
1342 | |
1343 | static bool generateWaveInst(const SPIRV::IncomingCall *Call, |
1344 | MachineIRBuilder &MIRBuilder, |
1345 | SPIRVGlobalRegistry *GR) { |
1346 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1347 | SPIRV::BuiltIn::BuiltIn Value = |
1348 | SPIRV::lookupGetBuiltin(Builtin->Name, Builtin->Set)->Value; |
1349 | |
1350 | // For now, we only support a single Wave intrinsic with a single return type. |
1351 | assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt); |
1352 | LLT LLType = LLT::scalar(SizeInBits: GR->getScalarOrVectorBitWidth(Type: Call->ReturnType)); |
1353 | |
1354 | return buildBuiltinVariableLoad( |
1355 | MIRBuilder, Call->ReturnType, GR, Value, LLType, Call->ReturnRegister, |
1356 | /* isConst= */ false, /* hasLinkageTy= */ false); |
1357 | } |
1358 | |
1359 | static bool generateGetQueryInst(const SPIRV::IncomingCall *Call, |
1360 | MachineIRBuilder &MIRBuilder, |
1361 | SPIRVGlobalRegistry *GR) { |
1362 | // Lookup the builtin record. |
1363 | SPIRV::BuiltIn::BuiltIn Value = |
1364 | SPIRV::lookupGetBuiltin(Call->Builtin->Name, Call->Builtin->Set)->Value; |
1365 | uint64_t IsDefault = (Value == SPIRV::BuiltIn::GlobalSize || |
1366 | Value == SPIRV::BuiltIn::WorkgroupSize || |
1367 | Value == SPIRV::BuiltIn::EnqueuedWorkgroupSize); |
1368 | return genWorkgroupQuery(Call, MIRBuilder, GR, Value, IsDefault ? 1 : 0); |
1369 | } |
1370 | |
1371 | static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call, |
1372 | MachineIRBuilder &MIRBuilder, |
1373 | SPIRVGlobalRegistry *GR) { |
1374 | // Lookup the image size query component number in the TableGen records. |
1375 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1376 | uint32_t Component = |
1377 | SPIRV::lookupImageQueryBuiltin(Builtin->Name, Builtin->Set)->Component; |
1378 | // Query result may either be a vector or a scalar. If return type is not a |
1379 | // vector, expect only a single size component. Otherwise get the number of |
1380 | // expected components. |
1381 | SPIRVType *RetTy = Call->ReturnType; |
1382 | unsigned NumExpectedRetComponents = RetTy->getOpcode() == SPIRV::OpTypeVector |
1383 | ? RetTy->getOperand(2).getImm() |
1384 | : 1; |
1385 | // Get the actual number of query result/size components. |
1386 | SPIRVType *ImgType = GR->getSPIRVTypeForVReg(VReg: Call->Arguments[0]); |
1387 | unsigned NumActualRetComponents = getNumSizeComponents(imgType: ImgType); |
1388 | Register QueryResult = Call->ReturnRegister; |
1389 | SPIRVType *QueryResultType = Call->ReturnType; |
1390 | if (NumExpectedRetComponents != NumActualRetComponents) { |
1391 | QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister( |
1392 | Ty: LLT::fixed_vector(NumElements: NumActualRetComponents, ScalarSizeInBits: 32)); |
1393 | MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::IDRegClass); |
1394 | SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder); |
1395 | QueryResultType = GR->getOrCreateSPIRVVectorType( |
1396 | BaseType: IntTy, NumElements: NumActualRetComponents, MIRBuilder); |
1397 | GR->assignSPIRVTypeToVReg(Type: QueryResultType, VReg: QueryResult, MF&: MIRBuilder.getMF()); |
1398 | } |
1399 | bool IsDimBuf = ImgType->getOperand(2).getImm() == SPIRV::Dim::DIM_Buffer; |
1400 | unsigned Opcode = |
1401 | IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod; |
1402 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1403 | auto MIB = MIRBuilder.buildInstr(Opcode) |
1404 | .addDef(RegNo: QueryResult) |
1405 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: QueryResultType)) |
1406 | .addUse(RegNo: Call->Arguments[0]); |
1407 | if (!IsDimBuf) |
1408 | MIB.addUse(RegNo: buildConstantIntReg(Val: 0, MIRBuilder, GR)); // Lod id. |
1409 | if (NumExpectedRetComponents == NumActualRetComponents) |
1410 | return true; |
1411 | if (NumExpectedRetComponents == 1) { |
1412 | // Only 1 component is expected, build OpCompositeExtract instruction. |
1413 | unsigned = |
1414 | Component == 3 ? NumActualRetComponents - 1 : Component; |
1415 | assert(ExtractedComposite < NumActualRetComponents && |
1416 | "Invalid composite index!" ); |
1417 | MIRBuilder.buildInstr(SPIRV::OpCompositeExtract) |
1418 | .addDef(Call->ReturnRegister) |
1419 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1420 | .addUse(QueryResult) |
1421 | .addImm(ExtractedComposite); |
1422 | } else { |
1423 | // More than 1 component is expected, fill a new vector. |
1424 | auto MIB = MIRBuilder.buildInstr(SPIRV::OpVectorShuffle) |
1425 | .addDef(Call->ReturnRegister) |
1426 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1427 | .addUse(QueryResult) |
1428 | .addUse(QueryResult); |
1429 | for (unsigned i = 0; i < NumExpectedRetComponents; ++i) |
1430 | MIB.addImm(i < NumActualRetComponents ? i : 0xffffffff); |
1431 | } |
1432 | return true; |
1433 | } |
1434 | |
1435 | static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call, |
1436 | MachineIRBuilder &MIRBuilder, |
1437 | SPIRVGlobalRegistry *GR) { |
1438 | assert(Call->ReturnType->getOpcode() == SPIRV::OpTypeInt && |
1439 | "Image samples query result must be of int type!" ); |
1440 | |
1441 | // Lookup the instruction opcode in the TableGen records. |
1442 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1443 | unsigned Opcode = |
1444 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
1445 | |
1446 | Register Image = Call->Arguments[0]; |
1447 | MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::IDRegClass); |
1448 | SPIRV::Dim::Dim ImageDimensionality = static_cast<SPIRV::Dim::Dim>( |
1449 | GR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm()); |
1450 | (void)ImageDimensionality; |
1451 | |
1452 | switch (Opcode) { |
1453 | case SPIRV::OpImageQuerySamples: |
1454 | assert(ImageDimensionality == SPIRV::Dim::DIM_2D && |
1455 | "Image must be of 2D dimensionality" ); |
1456 | break; |
1457 | case SPIRV::OpImageQueryLevels: |
1458 | assert((ImageDimensionality == SPIRV::Dim::DIM_1D || |
1459 | ImageDimensionality == SPIRV::Dim::DIM_2D || |
1460 | ImageDimensionality == SPIRV::Dim::DIM_3D || |
1461 | ImageDimensionality == SPIRV::Dim::DIM_Cube) && |
1462 | "Image must be of 1D/2D/3D/Cube dimensionality" ); |
1463 | break; |
1464 | } |
1465 | |
1466 | MIRBuilder.buildInstr(Opcode) |
1467 | .addDef(RegNo: Call->ReturnRegister) |
1468 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
1469 | .addUse(RegNo: Image); |
1470 | return true; |
1471 | } |
1472 | |
1473 | // TODO: Move to TableGen. |
1474 | static SPIRV::SamplerAddressingMode::SamplerAddressingMode |
1475 | getSamplerAddressingModeFromBitmask(unsigned Bitmask) { |
1476 | switch (Bitmask & SPIRV::CLK_ADDRESS_MODE_MASK) { |
1477 | case SPIRV::CLK_ADDRESS_CLAMP: |
1478 | return SPIRV::SamplerAddressingMode::Clamp; |
1479 | case SPIRV::CLK_ADDRESS_CLAMP_TO_EDGE: |
1480 | return SPIRV::SamplerAddressingMode::ClampToEdge; |
1481 | case SPIRV::CLK_ADDRESS_REPEAT: |
1482 | return SPIRV::SamplerAddressingMode::Repeat; |
1483 | case SPIRV::CLK_ADDRESS_MIRRORED_REPEAT: |
1484 | return SPIRV::SamplerAddressingMode::RepeatMirrored; |
1485 | case SPIRV::CLK_ADDRESS_NONE: |
1486 | return SPIRV::SamplerAddressingMode::None; |
1487 | default: |
1488 | report_fatal_error(reason: "Unknown CL address mode" ); |
1489 | } |
1490 | } |
1491 | |
1492 | static unsigned getSamplerParamFromBitmask(unsigned Bitmask) { |
1493 | return (Bitmask & SPIRV::CLK_NORMALIZED_COORDS_TRUE) ? 1 : 0; |
1494 | } |
1495 | |
1496 | static SPIRV::SamplerFilterMode::SamplerFilterMode |
1497 | getSamplerFilterModeFromBitmask(unsigned Bitmask) { |
1498 | if (Bitmask & SPIRV::CLK_FILTER_LINEAR) |
1499 | return SPIRV::SamplerFilterMode::Linear; |
1500 | if (Bitmask & SPIRV::CLK_FILTER_NEAREST) |
1501 | return SPIRV::SamplerFilterMode::Nearest; |
1502 | return SPIRV::SamplerFilterMode::Nearest; |
1503 | } |
1504 | |
1505 | static bool generateReadImageInst(const StringRef DemangledCall, |
1506 | const SPIRV::IncomingCall *Call, |
1507 | MachineIRBuilder &MIRBuilder, |
1508 | SPIRVGlobalRegistry *GR) { |
1509 | Register Image = Call->Arguments[0]; |
1510 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1511 | MRI->setRegClass(Image, &SPIRV::IDRegClass); |
1512 | MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
1513 | bool HasOclSampler = DemangledCall.contains_insensitive(Other: "ocl_sampler" ); |
1514 | bool HasMsaa = DemangledCall.contains_insensitive(Other: "msaa" ); |
1515 | if (HasOclSampler || HasMsaa) |
1516 | MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass); |
1517 | if (HasOclSampler) { |
1518 | Register Sampler = Call->Arguments[1]; |
1519 | |
1520 | if (!GR->isScalarOfType(Sampler, SPIRV::OpTypeSampler) && |
1521 | getDefInstrMaybeConstant(Sampler, MRI)->getOperand(1).isCImm()) { |
1522 | uint64_t SamplerMask = getIConstVal(ConstReg: Sampler, MRI); |
1523 | Sampler = GR->buildConstantSampler( |
1524 | Register(), getSamplerAddressingModeFromBitmask(SamplerMask), |
1525 | getSamplerParamFromBitmask(SamplerMask), |
1526 | getSamplerFilterModeFromBitmask(SamplerMask), MIRBuilder, |
1527 | GR->getSPIRVTypeForVReg(Sampler)); |
1528 | } |
1529 | SPIRVType *ImageType = GR->getSPIRVTypeForVReg(VReg: Image); |
1530 | SPIRVType *SampledImageType = |
1531 | GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); |
1532 | Register SampledImage = MRI->createVirtualRegister(&SPIRV::IDRegClass); |
1533 | |
1534 | MIRBuilder.buildInstr(SPIRV::OpSampledImage) |
1535 | .addDef(SampledImage) |
1536 | .addUse(GR->getSPIRVTypeID(SampledImageType)) |
1537 | .addUse(Image) |
1538 | .addUse(Sampler); |
1539 | |
1540 | Register Lod = GR->buildConstantFP(Val: APFloat::getZero(Sem: APFloat::IEEEsingle()), |
1541 | MIRBuilder); |
1542 | SPIRVType *TempType = Call->ReturnType; |
1543 | bool = false; |
1544 | if (TempType->getOpcode() != SPIRV::OpTypeVector) { |
1545 | TempType = |
1546 | GR->getOrCreateSPIRVVectorType(BaseType: Call->ReturnType, NumElements: 4, MIRBuilder); |
1547 | NeedsExtraction = true; |
1548 | } |
1549 | LLT LLType = LLT::scalar(SizeInBits: GR->getScalarOrVectorBitWidth(Type: TempType)); |
1550 | Register TempRegister = MRI->createGenericVirtualRegister(Ty: LLType); |
1551 | MRI->setRegClass(TempRegister, &SPIRV::IDRegClass); |
1552 | GR->assignSPIRVTypeToVReg(Type: TempType, VReg: TempRegister, MF&: MIRBuilder.getMF()); |
1553 | |
1554 | MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod) |
1555 | .addDef(NeedsExtraction ? TempRegister : Call->ReturnRegister) |
1556 | .addUse(GR->getSPIRVTypeID(TempType)) |
1557 | .addUse(SampledImage) |
1558 | .addUse(Call->Arguments[2]) // Coordinate. |
1559 | .addImm(SPIRV::ImageOperand::Lod) |
1560 | .addUse(Lod); |
1561 | |
1562 | if (NeedsExtraction) |
1563 | MIRBuilder.buildInstr(SPIRV::OpCompositeExtract) |
1564 | .addDef(Call->ReturnRegister) |
1565 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1566 | .addUse(TempRegister) |
1567 | .addImm(0); |
1568 | } else if (HasMsaa) { |
1569 | MIRBuilder.buildInstr(SPIRV::OpImageRead) |
1570 | .addDef(Call->ReturnRegister) |
1571 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1572 | .addUse(Image) |
1573 | .addUse(Call->Arguments[1]) // Coordinate. |
1574 | .addImm(SPIRV::ImageOperand::Sample) |
1575 | .addUse(Call->Arguments[2]); |
1576 | } else { |
1577 | MIRBuilder.buildInstr(SPIRV::OpImageRead) |
1578 | .addDef(Call->ReturnRegister) |
1579 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
1580 | .addUse(Image) |
1581 | .addUse(Call->Arguments[1]); // Coordinate. |
1582 | } |
1583 | return true; |
1584 | } |
1585 | |
1586 | static bool generateWriteImageInst(const SPIRV::IncomingCall *Call, |
1587 | MachineIRBuilder &MIRBuilder, |
1588 | SPIRVGlobalRegistry *GR) { |
1589 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1590 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
1591 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass); |
1592 | MIRBuilder.buildInstr(SPIRV::OpImageWrite) |
1593 | .addUse(Call->Arguments[0]) // Image. |
1594 | .addUse(Call->Arguments[1]) // Coordinate. |
1595 | .addUse(Call->Arguments[2]); // Texel. |
1596 | return true; |
1597 | } |
1598 | |
1599 | static bool generateSampleImageInst(const StringRef DemangledCall, |
1600 | const SPIRV::IncomingCall *Call, |
1601 | MachineIRBuilder &MIRBuilder, |
1602 | SPIRVGlobalRegistry *GR) { |
1603 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1604 | if (Call->Builtin->Name.contains_insensitive( |
1605 | Other: "__translate_sampler_initializer" )) { |
1606 | // Build sampler literal. |
1607 | uint64_t Bitmask = getIConstVal(ConstReg: Call->Arguments[0], MRI); |
1608 | Register Sampler = GR->buildConstantSampler( |
1609 | Call->ReturnRegister, getSamplerAddressingModeFromBitmask(Bitmask), |
1610 | getSamplerParamFromBitmask(Bitmask), |
1611 | getSamplerFilterModeFromBitmask(Bitmask), MIRBuilder, Call->ReturnType); |
1612 | return Sampler.isValid(); |
1613 | } else if (Call->Builtin->Name.contains_insensitive(Other: "__spirv_SampledImage" )) { |
1614 | // Create OpSampledImage. |
1615 | Register Image = Call->Arguments[0]; |
1616 | SPIRVType *ImageType = GR->getSPIRVTypeForVReg(VReg: Image); |
1617 | SPIRVType *SampledImageType = |
1618 | GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder); |
1619 | Register SampledImage = |
1620 | Call->ReturnRegister.isValid() |
1621 | ? Call->ReturnRegister |
1622 | : MRI->createVirtualRegister(&SPIRV::IDRegClass); |
1623 | MIRBuilder.buildInstr(SPIRV::OpSampledImage) |
1624 | .addDef(SampledImage) |
1625 | .addUse(GR->getSPIRVTypeID(SampledImageType)) |
1626 | .addUse(Image) |
1627 | .addUse(Call->Arguments[1]); // Sampler. |
1628 | return true; |
1629 | } else if (Call->Builtin->Name.contains_insensitive( |
1630 | Other: "__spirv_ImageSampleExplicitLod" )) { |
1631 | // Sample an image using an explicit level of detail. |
1632 | std::string ReturnType = DemangledCall.str(); |
1633 | if (DemangledCall.contains(Other: "_R" )) { |
1634 | ReturnType = ReturnType.substr(ReturnType.find("_R" ) + 2); |
1635 | ReturnType = ReturnType.substr(pos: 0, n: ReturnType.find('(')); |
1636 | } |
1637 | SPIRVType *Type = |
1638 | Call->ReturnType |
1639 | ? Call->ReturnType |
1640 | : GR->getOrCreateSPIRVTypeByName(ReturnType, MIRBuilder); |
1641 | if (!Type) { |
1642 | std::string DiagMsg = |
1643 | "Unable to recognize SPIRV type name: " + ReturnType; |
1644 | report_fatal_error(reason: DiagMsg.c_str()); |
1645 | } |
1646 | MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1647 | MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
1648 | MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass); |
1649 | |
1650 | MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod) |
1651 | .addDef(Call->ReturnRegister) |
1652 | .addUse(GR->getSPIRVTypeID(Type)) |
1653 | .addUse(Call->Arguments[0]) // Image. |
1654 | .addUse(Call->Arguments[1]) // Coordinate. |
1655 | .addImm(SPIRV::ImageOperand::Lod) |
1656 | .addUse(Call->Arguments[3]); |
1657 | return true; |
1658 | } |
1659 | return false; |
1660 | } |
1661 | |
1662 | static bool generateSelectInst(const SPIRV::IncomingCall *Call, |
1663 | MachineIRBuilder &MIRBuilder) { |
1664 | MIRBuilder.buildSelect(Res: Call->ReturnRegister, Tst: Call->Arguments[0], |
1665 | Op0: Call->Arguments[1], Op1: Call->Arguments[2]); |
1666 | return true; |
1667 | } |
1668 | |
1669 | static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call, |
1670 | MachineIRBuilder &MIRBuilder, |
1671 | SPIRVGlobalRegistry *GR) { |
1672 | // Lookup the instruction opcode in the TableGen records. |
1673 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1674 | unsigned Opcode = |
1675 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
1676 | const MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1677 | |
1678 | switch (Opcode) { |
1679 | case SPIRV::OpSpecConstant: { |
1680 | // Build the SpecID decoration. |
1681 | unsigned SpecId = |
1682 | static_cast<unsigned>(getIConstVal(ConstReg: Call->Arguments[0], MRI)); |
1683 | buildOpDecorate(Call->ReturnRegister, MIRBuilder, SPIRV::Decoration::SpecId, |
1684 | {SpecId}); |
1685 | // Determine the constant MI. |
1686 | Register ConstRegister = Call->Arguments[1]; |
1687 | const MachineInstr *Const = getDefInstrMaybeConstant(ConstReg&: ConstRegister, MRI); |
1688 | assert(Const && |
1689 | (Const->getOpcode() == TargetOpcode::G_CONSTANT || |
1690 | Const->getOpcode() == TargetOpcode::G_FCONSTANT) && |
1691 | "Argument should be either an int or floating-point constant" ); |
1692 | // Determine the opcode and built the OpSpec MI. |
1693 | const MachineOperand &ConstOperand = Const->getOperand(i: 1); |
1694 | if (Call->ReturnType->getOpcode() == SPIRV::OpTypeBool) { |
1695 | assert(ConstOperand.isCImm() && "Int constant operand is expected" ); |
1696 | Opcode = ConstOperand.getCImm()->getValue().getZExtValue() |
1697 | ? SPIRV::OpSpecConstantTrue |
1698 | : SPIRV::OpSpecConstantFalse; |
1699 | } |
1700 | auto MIB = MIRBuilder.buildInstr(Opcode) |
1701 | .addDef(RegNo: Call->ReturnRegister) |
1702 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
1703 | |
1704 | if (Call->ReturnType->getOpcode() != SPIRV::OpTypeBool) { |
1705 | if (Const->getOpcode() == TargetOpcode::G_CONSTANT) |
1706 | addNumImm(Imm: ConstOperand.getCImm()->getValue(), MIB); |
1707 | else |
1708 | addNumImm(Imm: ConstOperand.getFPImm()->getValueAPF().bitcastToAPInt(), MIB); |
1709 | } |
1710 | return true; |
1711 | } |
1712 | case SPIRV::OpSpecConstantComposite: { |
1713 | auto MIB = MIRBuilder.buildInstr(Opcode) |
1714 | .addDef(RegNo: Call->ReturnRegister) |
1715 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
1716 | for (unsigned i = 0; i < Call->Arguments.size(); i++) |
1717 | MIB.addUse(RegNo: Call->Arguments[i]); |
1718 | return true; |
1719 | } |
1720 | default: |
1721 | return false; |
1722 | } |
1723 | } |
1724 | |
1725 | static bool buildNDRange(const SPIRV::IncomingCall *Call, |
1726 | MachineIRBuilder &MIRBuilder, |
1727 | SPIRVGlobalRegistry *GR) { |
1728 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1729 | MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1730 | SPIRVType *PtrType = GR->getSPIRVTypeForVReg(VReg: Call->Arguments[0]); |
1731 | assert(PtrType->getOpcode() == SPIRV::OpTypePointer && |
1732 | PtrType->getOperand(2).isReg()); |
1733 | Register TypeReg = PtrType->getOperand(i: 2).getReg(); |
1734 | SPIRVType *StructType = GR->getSPIRVTypeForVReg(VReg: TypeReg); |
1735 | MachineFunction &MF = MIRBuilder.getMF(); |
1736 | Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass); |
1737 | GR->assignSPIRVTypeToVReg(Type: StructType, VReg: TmpReg, MF); |
1738 | // Skip the first arg, it's the destination pointer. OpBuildNDRange takes |
1739 | // three other arguments, so pass zero constant on absence. |
1740 | unsigned NumArgs = Call->Arguments.size(); |
1741 | assert(NumArgs >= 2); |
1742 | Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2]; |
1743 | MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass); |
1744 | Register LocalWorkSize = |
1745 | NumArgs == 2 ? Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3]; |
1746 | if (LocalWorkSize.isValid()) |
1747 | MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass); |
1748 | Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1]; |
1749 | if (GlobalWorkOffset.isValid()) |
1750 | MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass); |
1751 | if (NumArgs < 4) { |
1752 | Register Const; |
1753 | SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(VReg: GlobalWorkSize); |
1754 | if (SpvTy->getOpcode() == SPIRV::OpTypePointer) { |
1755 | MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg: GlobalWorkSize); |
1756 | assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && |
1757 | DefInstr->getOperand(3).isReg()); |
1758 | Register GWSPtr = DefInstr->getOperand(i: 3).getReg(); |
1759 | if (!MRI->getRegClassOrNull(GWSPtr)) |
1760 | MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass); |
1761 | // TODO: Maybe simplify generation of the type of the fields. |
1762 | unsigned Size = Call->Builtin->Name.equals(RHS: "ndrange_3D" ) ? 3 : 2; |
1763 | unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32; |
1764 | Type *BaseTy = IntegerType::get(C&: MF.getFunction().getContext(), NumBits: BitWidth); |
1765 | Type *FieldTy = ArrayType::get(ElementType: BaseTy, NumElements: Size); |
1766 | SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType(FieldTy, MIRBuilder); |
1767 | GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::IDRegClass); |
1768 | GR->assignSPIRVTypeToVReg(Type: SpvFieldTy, VReg: GlobalWorkSize, MF); |
1769 | MIRBuilder.buildInstr(SPIRV::OpLoad) |
1770 | .addDef(GlobalWorkSize) |
1771 | .addUse(GR->getSPIRVTypeID(SpvFieldTy)) |
1772 | .addUse(GWSPtr); |
1773 | Const = GR->getOrCreateConsIntArray(Val: 0, MIRBuilder, SpvType: SpvFieldTy); |
1774 | } else { |
1775 | Const = GR->buildConstantInt(Val: 0, MIRBuilder, SpvType: SpvTy); |
1776 | } |
1777 | if (!LocalWorkSize.isValid()) |
1778 | LocalWorkSize = Const; |
1779 | if (!GlobalWorkOffset.isValid()) |
1780 | GlobalWorkOffset = Const; |
1781 | } |
1782 | assert(LocalWorkSize.isValid() && GlobalWorkOffset.isValid()); |
1783 | MIRBuilder.buildInstr(SPIRV::OpBuildNDRange) |
1784 | .addDef(TmpReg) |
1785 | .addUse(TypeReg) |
1786 | .addUse(GlobalWorkSize) |
1787 | .addUse(LocalWorkSize) |
1788 | .addUse(GlobalWorkOffset); |
1789 | return MIRBuilder.buildInstr(SPIRV::OpStore) |
1790 | .addUse(Call->Arguments[0]) |
1791 | .addUse(TmpReg); |
1792 | } |
1793 | |
1794 | static MachineInstr *getBlockStructInstr(Register ParamReg, |
1795 | MachineRegisterInfo *MRI) { |
1796 | // We expect the following sequence of instructions: |
1797 | // %0:_(pN) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.alloca) |
1798 | // or = G_GLOBAL_VALUE @block_literal_global |
1799 | // %1:_(pN) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.spv.bitcast), %0 |
1800 | // %2:_(p4) = G_ADDRSPACE_CAST %1:_(pN) |
1801 | MachineInstr *MI = MRI->getUniqueVRegDef(Reg: ParamReg); |
1802 | assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST && |
1803 | MI->getOperand(1).isReg()); |
1804 | Register BitcastReg = MI->getOperand(i: 1).getReg(); |
1805 | MachineInstr *BitcastMI = MRI->getUniqueVRegDef(Reg: BitcastReg); |
1806 | assert(isSpvIntrinsic(*BitcastMI, Intrinsic::spv_bitcast) && |
1807 | BitcastMI->getOperand(2).isReg()); |
1808 | Register ValueReg = BitcastMI->getOperand(i: 2).getReg(); |
1809 | MachineInstr *ValueMI = MRI->getUniqueVRegDef(Reg: ValueReg); |
1810 | return ValueMI; |
1811 | } |
1812 | |
1813 | // Return an integer constant corresponding to the given register and |
1814 | // defined in spv_track_constant. |
1815 | // TODO: maybe unify with prelegalizer pass. |
1816 | static unsigned getConstFromIntrinsic(Register Reg, MachineRegisterInfo *MRI) { |
1817 | MachineInstr *DefMI = MRI->getUniqueVRegDef(Reg); |
1818 | assert(isSpvIntrinsic(*DefMI, Intrinsic::spv_track_constant) && |
1819 | DefMI->getOperand(2).isReg()); |
1820 | MachineInstr *DefMI2 = MRI->getUniqueVRegDef(Reg: DefMI->getOperand(i: 2).getReg()); |
1821 | assert(DefMI2->getOpcode() == TargetOpcode::G_CONSTANT && |
1822 | DefMI2->getOperand(1).isCImm()); |
1823 | return DefMI2->getOperand(i: 1).getCImm()->getValue().getZExtValue(); |
1824 | } |
1825 | |
1826 | // Return type of the instruction result from spv_assign_type intrinsic. |
1827 | // TODO: maybe unify with prelegalizer pass. |
1828 | static const Type *getMachineInstrType(MachineInstr *MI) { |
1829 | MachineInstr *NextMI = MI->getNextNode(); |
1830 | if (isSpvIntrinsic(*NextMI, Intrinsic::spv_assign_name)) |
1831 | NextMI = NextMI->getNextNode(); |
1832 | Register ValueReg = MI->getOperand(i: 0).getReg(); |
1833 | if (!isSpvIntrinsic(*NextMI, Intrinsic::spv_assign_type) || |
1834 | NextMI->getOperand(1).getReg() != ValueReg) |
1835 | return nullptr; |
1836 | Type *Ty = getMDOperandAsType(N: NextMI->getOperand(i: 2).getMetadata(), I: 0); |
1837 | assert(Ty && "Type is expected" ); |
1838 | return Ty; |
1839 | } |
1840 | |
1841 | static const Type *getBlockStructType(Register ParamReg, |
1842 | MachineRegisterInfo *MRI) { |
1843 | // In principle, this information should be passed to us from Clang via |
1844 | // an elementtype attribute. However, said attribute requires that |
1845 | // the function call be an intrinsic, which is not. Instead, we rely on being |
1846 | // able to trace this to the declaration of a variable: OpenCL C specification |
1847 | // section 6.12.5 should guarantee that we can do this. |
1848 | MachineInstr *MI = getBlockStructInstr(ParamReg, MRI); |
1849 | if (MI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE) |
1850 | return MI->getOperand(i: 1).getGlobal()->getType(); |
1851 | assert(isSpvIntrinsic(*MI, Intrinsic::spv_alloca) && |
1852 | "Blocks in OpenCL C must be traceable to allocation site" ); |
1853 | return getMachineInstrType(MI); |
1854 | } |
1855 | |
1856 | // TODO: maybe move to the global register. |
1857 | static SPIRVType * |
1858 | getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder, |
1859 | SPIRVGlobalRegistry *GR) { |
1860 | LLVMContext &Context = MIRBuilder.getMF().getFunction().getContext(); |
1861 | Type *OpaqueType = StructType::getTypeByName(C&: Context, Name: "spirv.DeviceEvent" ); |
1862 | if (!OpaqueType) |
1863 | OpaqueType = StructType::getTypeByName(C&: Context, Name: "opencl.clk_event_t" ); |
1864 | if (!OpaqueType) |
1865 | OpaqueType = StructType::create(Context, Name: "spirv.DeviceEvent" ); |
1866 | unsigned SC0 = storageClassToAddressSpace(SPIRV::StorageClass::Function); |
1867 | unsigned SC1 = storageClassToAddressSpace(SPIRV::StorageClass::Generic); |
1868 | Type *PtrType = PointerType::get(ElementType: PointerType::get(ElementType: OpaqueType, AddressSpace: SC0), AddressSpace: SC1); |
1869 | return GR->getOrCreateSPIRVType(PtrType, MIRBuilder); |
1870 | } |
1871 | |
1872 | static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call, |
1873 | MachineIRBuilder &MIRBuilder, |
1874 | SPIRVGlobalRegistry *GR) { |
1875 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
1876 | const DataLayout &DL = MIRBuilder.getDataLayout(); |
1877 | bool IsSpirvOp = Call->isSpirvOp(); |
1878 | bool HasEvents = Call->Builtin->Name.contains(Other: "events" ) || IsSpirvOp; |
1879 | const SPIRVType *Int32Ty = GR->getOrCreateSPIRVIntegerType(BitWidth: 32, MIRBuilder); |
1880 | |
1881 | // Make vararg instructions before OpEnqueueKernel. |
1882 | // Local sizes arguments: Sizes of block invoke arguments. Clang generates |
1883 | // local size operands as an array, so we need to unpack them. |
1884 | SmallVector<Register, 16> LocalSizes; |
1885 | if (Call->Builtin->Name.find(Str: "_varargs" ) != StringRef::npos || IsSpirvOp) { |
1886 | const unsigned LocalSizeArrayIdx = HasEvents ? 9 : 6; |
1887 | Register GepReg = Call->Arguments[LocalSizeArrayIdx]; |
1888 | MachineInstr *GepMI = MRI->getUniqueVRegDef(Reg: GepReg); |
1889 | assert(isSpvIntrinsic(*GepMI, Intrinsic::spv_gep) && |
1890 | GepMI->getOperand(3).isReg()); |
1891 | Register ArrayReg = GepMI->getOperand(i: 3).getReg(); |
1892 | MachineInstr *ArrayMI = MRI->getUniqueVRegDef(Reg: ArrayReg); |
1893 | const Type *LocalSizeTy = getMachineInstrType(MI: ArrayMI); |
1894 | assert(LocalSizeTy && "Local size type is expected" ); |
1895 | const uint64_t LocalSizeNum = |
1896 | cast<ArrayType>(LocalSizeTy)->getNumElements(); |
1897 | unsigned SC = storageClassToAddressSpace(SPIRV::StorageClass::Generic); |
1898 | const LLT LLType = LLT::pointer(AddressSpace: SC, SizeInBits: GR->getPointerSize()); |
1899 | const SPIRVType *PointerSizeTy = GR->getOrCreateSPIRVPointerType( |
1900 | Int32Ty, MIRBuilder, SPIRV::StorageClass::Function); |
1901 | for (unsigned I = 0; I < LocalSizeNum; ++I) { |
1902 | Register Reg = MRI->createVirtualRegister(&SPIRV::IDRegClass); |
1903 | MRI->setType(VReg: Reg, Ty: LLType); |
1904 | GR->assignSPIRVTypeToVReg(Type: PointerSizeTy, VReg: Reg, MF&: MIRBuilder.getMF()); |
1905 | auto GEPInst = MIRBuilder.buildIntrinsic( |
1906 | Intrinsic::spv_gep, ArrayRef<Register>{Reg}, true, false); |
1907 | GEPInst |
1908 | .addImm(GepMI->getOperand(i: 2).getImm()) // In bound. |
1909 | .addUse(ArrayMI->getOperand(i: 0).getReg()) // Alloca. |
1910 | .addUse(buildConstantIntReg(Val: 0, MIRBuilder, GR)) // Indices. |
1911 | .addUse(buildConstantIntReg(Val: I, MIRBuilder, GR)); |
1912 | LocalSizes.push_back(Reg); |
1913 | } |
1914 | } |
1915 | |
1916 | // SPIRV OpEnqueueKernel instruction has 10+ arguments. |
1917 | auto MIB = MIRBuilder.buildInstr(SPIRV::OpEnqueueKernel) |
1918 | .addDef(Call->ReturnRegister) |
1919 | .addUse(GR->getSPIRVTypeID(Int32Ty)); |
1920 | |
1921 | // Copy all arguments before block invoke function pointer. |
1922 | const unsigned BlockFIdx = HasEvents ? 6 : 3; |
1923 | for (unsigned i = 0; i < BlockFIdx; i++) |
1924 | MIB.addUse(Call->Arguments[i]); |
1925 | |
1926 | // If there are no event arguments in the original call, add dummy ones. |
1927 | if (!HasEvents) { |
1928 | MIB.addUse(buildConstantIntReg(Val: 0, MIRBuilder, GR)); // Dummy num events. |
1929 | Register NullPtr = GR->getOrCreateConstNullPtr( |
1930 | MIRBuilder, SpvType: getOrCreateSPIRVDeviceEventPointer(MIRBuilder, GR)); |
1931 | MIB.addUse(NullPtr); // Dummy wait events. |
1932 | MIB.addUse(NullPtr); // Dummy ret event. |
1933 | } |
1934 | |
1935 | MachineInstr *BlockMI = getBlockStructInstr(ParamReg: Call->Arguments[BlockFIdx], MRI); |
1936 | assert(BlockMI->getOpcode() == TargetOpcode::G_GLOBAL_VALUE); |
1937 | // Invoke: Pointer to invoke function. |
1938 | MIB.addGlobalAddress(BlockMI->getOperand(i: 1).getGlobal()); |
1939 | |
1940 | Register BlockLiteralReg = Call->Arguments[BlockFIdx + 1]; |
1941 | // Param: Pointer to block literal. |
1942 | MIB.addUse(BlockLiteralReg); |
1943 | |
1944 | Type *PType = const_cast<Type *>(getBlockStructType(ParamReg: BlockLiteralReg, MRI)); |
1945 | // TODO: these numbers should be obtained from block literal structure. |
1946 | // Param Size: Size of block literal structure. |
1947 | MIB.addUse(buildConstantIntReg(Val: DL.getTypeStoreSize(Ty: PType), MIRBuilder, GR)); |
1948 | // Param Aligment: Aligment of block literal structure. |
1949 | MIB.addUse( |
1950 | buildConstantIntReg(Val: DL.getPrefTypeAlign(Ty: PType).value(), MIRBuilder, GR)); |
1951 | |
1952 | for (unsigned i = 0; i < LocalSizes.size(); i++) |
1953 | MIB.addUse(LocalSizes[i]); |
1954 | return true; |
1955 | } |
1956 | |
1957 | static bool generateEnqueueInst(const SPIRV::IncomingCall *Call, |
1958 | MachineIRBuilder &MIRBuilder, |
1959 | SPIRVGlobalRegistry *GR) { |
1960 | // Lookup the instruction opcode in the TableGen records. |
1961 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
1962 | unsigned Opcode = |
1963 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
1964 | |
1965 | switch (Opcode) { |
1966 | case SPIRV::OpRetainEvent: |
1967 | case SPIRV::OpReleaseEvent: |
1968 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1969 | return MIRBuilder.buildInstr(Opcode).addUse(RegNo: Call->Arguments[0]); |
1970 | case SPIRV::OpCreateUserEvent: |
1971 | case SPIRV::OpGetDefaultQueue: |
1972 | return MIRBuilder.buildInstr(Opcode) |
1973 | .addDef(RegNo: Call->ReturnRegister) |
1974 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
1975 | case SPIRV::OpIsValidEvent: |
1976 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1977 | return MIRBuilder.buildInstr(Opcode) |
1978 | .addDef(RegNo: Call->ReturnRegister) |
1979 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
1980 | .addUse(RegNo: Call->Arguments[0]); |
1981 | case SPIRV::OpSetUserEventStatus: |
1982 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1983 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
1984 | return MIRBuilder.buildInstr(Opcode) |
1985 | .addUse(RegNo: Call->Arguments[0]) |
1986 | .addUse(RegNo: Call->Arguments[1]); |
1987 | case SPIRV::OpCaptureEventProfilingInfo: |
1988 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
1989 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
1990 | MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass); |
1991 | return MIRBuilder.buildInstr(Opcode) |
1992 | .addUse(RegNo: Call->Arguments[0]) |
1993 | .addUse(RegNo: Call->Arguments[1]) |
1994 | .addUse(RegNo: Call->Arguments[2]); |
1995 | case SPIRV::OpBuildNDRange: |
1996 | return buildNDRange(Call, MIRBuilder, GR); |
1997 | case SPIRV::OpEnqueueKernel: |
1998 | return buildEnqueueKernel(Call, MIRBuilder, GR); |
1999 | default: |
2000 | return false; |
2001 | } |
2002 | } |
2003 | |
2004 | static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, |
2005 | MachineIRBuilder &MIRBuilder, |
2006 | SPIRVGlobalRegistry *GR) { |
2007 | // Lookup the instruction opcode in the TableGen records. |
2008 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
2009 | unsigned Opcode = |
2010 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
2011 | auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GR); |
2012 | |
2013 | switch (Opcode) { |
2014 | case SPIRV::OpGroupAsyncCopy: |
2015 | return MIRBuilder.buildInstr(Opcode) |
2016 | .addDef(RegNo: Call->ReturnRegister) |
2017 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
2018 | .addUse(RegNo: Scope) |
2019 | .addUse(Call->Arguments[0]) |
2020 | .addUse(Call->Arguments[1]) |
2021 | .addUse(Call->Arguments[2]) |
2022 | .addUse(buildConstantIntReg(Val: 1, MIRBuilder, GR)) |
2023 | .addUse(Call->Arguments[3]); |
2024 | case SPIRV::OpGroupWaitEvents: |
2025 | return MIRBuilder.buildInstr(Opcode) |
2026 | .addUse(RegNo: Scope) |
2027 | .addUse(Call->Arguments[0]) |
2028 | .addUse(Call->Arguments[1]); |
2029 | default: |
2030 | return false; |
2031 | } |
2032 | } |
2033 | |
2034 | static bool generateConvertInst(const StringRef DemangledCall, |
2035 | const SPIRV::IncomingCall *Call, |
2036 | MachineIRBuilder &MIRBuilder, |
2037 | SPIRVGlobalRegistry *GR) { |
2038 | // Lookup the conversion builtin in the TableGen records. |
2039 | const SPIRV::ConvertBuiltin *Builtin = |
2040 | SPIRV::lookupConvertBuiltin(Call->Builtin->Name, Call->Builtin->Set); |
2041 | |
2042 | if (Builtin->IsSaturated) |
2043 | buildOpDecorate(Call->ReturnRegister, MIRBuilder, |
2044 | SPIRV::Decoration::SaturatedConversion, {}); |
2045 | if (Builtin->IsRounded) |
2046 | buildOpDecorate(Call->ReturnRegister, MIRBuilder, |
2047 | SPIRV::Decoration::FPRoundingMode, |
2048 | {(unsigned)Builtin->RoundingMode}); |
2049 | |
2050 | std::string NeedExtMsg; // no errors if empty |
2051 | bool IsRightComponentsNumber = true; // check if input/output accepts vectors |
2052 | unsigned Opcode = SPIRV::OpNop; |
2053 | if (GR->isScalarOrVectorOfType(Call->Arguments[0], SPIRV::OpTypeInt)) { |
2054 | // Int -> ... |
2055 | if (GR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) { |
2056 | // Int -> Int |
2057 | if (Builtin->IsSaturated) |
2058 | Opcode = Builtin->IsDestinationSigned ? SPIRV::OpSatConvertUToS |
2059 | : SPIRV::OpSatConvertSToU; |
2060 | else |
2061 | Opcode = Builtin->IsDestinationSigned ? SPIRV::OpUConvert |
2062 | : SPIRV::OpSConvert; |
2063 | } else if (GR->isScalarOrVectorOfType(Call->ReturnRegister, |
2064 | SPIRV::OpTypeFloat)) { |
2065 | // Int -> Float |
2066 | if (Builtin->IsBfloat16) { |
2067 | const auto *ST = static_cast<const SPIRVSubtarget *>( |
2068 | &MIRBuilder.getMF().getSubtarget()); |
2069 | if (!ST->canUseExtension( |
2070 | SPIRV::Extension::SPV_INTEL_bfloat16_conversion)) |
2071 | NeedExtMsg = "SPV_INTEL_bfloat16_conversion" ; |
2072 | IsRightComponentsNumber = |
2073 | GR->getScalarOrVectorComponentCount(VReg: Call->Arguments[0]) == |
2074 | GR->getScalarOrVectorComponentCount(VReg: Call->ReturnRegister); |
2075 | Opcode = SPIRV::OpConvertBF16ToFINTEL; |
2076 | } else { |
2077 | bool IsSourceSigned = |
2078 | DemangledCall[DemangledCall.find_first_of(C: '(') + 1] != 'u'; |
2079 | Opcode = IsSourceSigned ? SPIRV::OpConvertSToF : SPIRV::OpConvertUToF; |
2080 | } |
2081 | } |
2082 | } else if (GR->isScalarOrVectorOfType(Call->Arguments[0], |
2083 | SPIRV::OpTypeFloat)) { |
2084 | // Float -> ... |
2085 | if (GR->isScalarOrVectorOfType(Call->ReturnRegister, SPIRV::OpTypeInt)) { |
2086 | // Float -> Int |
2087 | if (Builtin->IsBfloat16) { |
2088 | const auto *ST = static_cast<const SPIRVSubtarget *>( |
2089 | &MIRBuilder.getMF().getSubtarget()); |
2090 | if (!ST->canUseExtension( |
2091 | SPIRV::Extension::SPV_INTEL_bfloat16_conversion)) |
2092 | NeedExtMsg = "SPV_INTEL_bfloat16_conversion" ; |
2093 | IsRightComponentsNumber = |
2094 | GR->getScalarOrVectorComponentCount(VReg: Call->Arguments[0]) == |
2095 | GR->getScalarOrVectorComponentCount(VReg: Call->ReturnRegister); |
2096 | Opcode = SPIRV::OpConvertFToBF16INTEL; |
2097 | } else { |
2098 | Opcode = Builtin->IsDestinationSigned ? SPIRV::OpConvertFToS |
2099 | : SPIRV::OpConvertFToU; |
2100 | } |
2101 | } else if (GR->isScalarOrVectorOfType(Call->ReturnRegister, |
2102 | SPIRV::OpTypeFloat)) { |
2103 | // Float -> Float |
2104 | Opcode = SPIRV::OpFConvert; |
2105 | } |
2106 | } |
2107 | |
2108 | if (!NeedExtMsg.empty()) { |
2109 | std::string DiagMsg = std::string(Builtin->Name) + |
2110 | ": the builtin requires the following SPIR-V " |
2111 | "extension: " + |
2112 | NeedExtMsg; |
2113 | report_fatal_error(reason: DiagMsg.c_str(), gen_crash_diag: false); |
2114 | } |
2115 | if (!IsRightComponentsNumber) { |
2116 | std::string DiagMsg = |
2117 | std::string(Builtin->Name) + |
2118 | ": result and argument must have the same number of components" ; |
2119 | report_fatal_error(reason: DiagMsg.c_str(), gen_crash_diag: false); |
2120 | } |
2121 | assert(Opcode != SPIRV::OpNop && |
2122 | "Conversion between the types not implemented!" ); |
2123 | |
2124 | MIRBuilder.buildInstr(Opcode) |
2125 | .addDef(RegNo: Call->ReturnRegister) |
2126 | .addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)) |
2127 | .addUse(RegNo: Call->Arguments[0]); |
2128 | return true; |
2129 | } |
2130 | |
2131 | static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, |
2132 | MachineIRBuilder &MIRBuilder, |
2133 | SPIRVGlobalRegistry *GR) { |
2134 | // Lookup the vector load/store builtin in the TableGen records. |
2135 | const SPIRV::VectorLoadStoreBuiltin *Builtin = |
2136 | SPIRV::lookupVectorLoadStoreBuiltin(Call->Builtin->Name, |
2137 | Call->Builtin->Set); |
2138 | // Build extended instruction. |
2139 | auto MIB = |
2140 | MIRBuilder.buildInstr(SPIRV::OpExtInst) |
2141 | .addDef(Call->ReturnRegister) |
2142 | .addUse(GR->getSPIRVTypeID(Call->ReturnType)) |
2143 | .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::OpenCL_std)) |
2144 | .addImm(Builtin->Number); |
2145 | for (auto Argument : Call->Arguments) |
2146 | MIB.addUse(Argument); |
2147 | if (Builtin->Name.contains(Other: "load" ) && Builtin->ElementCount > 1) |
2148 | MIB.addImm(Builtin->ElementCount); |
2149 | |
2150 | // Rounding mode should be passed as a last argument in the MI for builtins |
2151 | // like "vstorea_halfn_r". |
2152 | if (Builtin->IsRounded) |
2153 | MIB.addImm(static_cast<uint32_t>(Builtin->RoundingMode)); |
2154 | return true; |
2155 | } |
2156 | |
2157 | static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, |
2158 | MachineIRBuilder &MIRBuilder, |
2159 | SPIRVGlobalRegistry *GR) { |
2160 | // Lookup the instruction opcode in the TableGen records. |
2161 | const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; |
2162 | unsigned Opcode = |
2163 | SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; |
2164 | bool IsLoad = Opcode == SPIRV::OpLoad; |
2165 | // Build the instruction. |
2166 | auto MIB = MIRBuilder.buildInstr(Opcode); |
2167 | if (IsLoad) { |
2168 | MIB.addDef(RegNo: Call->ReturnRegister); |
2169 | MIB.addUse(RegNo: GR->getSPIRVTypeID(SpirvType: Call->ReturnType)); |
2170 | } |
2171 | // Add a pointer to the value to load/store. |
2172 | MIB.addUse(RegNo: Call->Arguments[0]); |
2173 | MachineRegisterInfo *MRI = MIRBuilder.getMRI(); |
2174 | MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass); |
2175 | // Add a value to store. |
2176 | if (!IsLoad) { |
2177 | MIB.addUse(RegNo: Call->Arguments[1]); |
2178 | MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass); |
2179 | } |
2180 | // Add optional memory attributes and an alignment. |
2181 | unsigned NumArgs = Call->Arguments.size(); |
2182 | if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) { |
2183 | MIB.addImm(Val: getConstFromIntrinsic(Reg: Call->Arguments[IsLoad ? 1 : 2], MRI)); |
2184 | MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass); |
2185 | } |
2186 | if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) { |
2187 | MIB.addImm(Val: getConstFromIntrinsic(Reg: Call->Arguments[IsLoad ? 2 : 3], MRI)); |
2188 | MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass); |
2189 | } |
2190 | return true; |
2191 | } |
2192 | |
2193 | /// Lowers a builtin funtion call using the provided \p DemangledCall skeleton |
2194 | /// and external instruction \p Set. |
2195 | namespace SPIRV { |
2196 | std::optional<bool> lowerBuiltin(const StringRef DemangledCall, |
2197 | SPIRV::InstructionSet::InstructionSet Set, |
2198 | MachineIRBuilder &MIRBuilder, |
2199 | const Register OrigRet, const Type *OrigRetTy, |
2200 | const SmallVectorImpl<Register> &Args, |
2201 | SPIRVGlobalRegistry *GR) { |
2202 | LLVM_DEBUG(dbgs() << "Lowering builtin call: " << DemangledCall << "\n" ); |
2203 | |
2204 | // SPIR-V type and return register. |
2205 | Register ReturnRegister = OrigRet; |
2206 | SPIRVType *ReturnType = nullptr; |
2207 | if (OrigRetTy && !OrigRetTy->isVoidTy()) { |
2208 | ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder); |
2209 | if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister)) |
2210 | MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::IDRegClass); |
2211 | } else if (OrigRetTy && OrigRetTy->isVoidTy()) { |
2212 | ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass); |
2213 | MIRBuilder.getMRI()->setType(VReg: ReturnRegister, Ty: LLT::scalar(SizeInBits: 32)); |
2214 | ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder); |
2215 | } |
2216 | |
2217 | // Lookup the builtin in the TableGen records. |
2218 | std::unique_ptr<const IncomingCall> Call = |
2219 | lookupBuiltin(DemangledCall, Set, ReturnRegister, ReturnType, Args); |
2220 | |
2221 | if (!Call) { |
2222 | LLVM_DEBUG(dbgs() << "Builtin record was not found!\n" ); |
2223 | return std::nullopt; |
2224 | } |
2225 | |
2226 | // TODO: check if the provided args meet the builtin requirments. |
2227 | assert(Args.size() >= Call->Builtin->MinNumArgs && |
2228 | "Too few arguments to generate the builtin" ); |
2229 | if (Call->Builtin->MaxNumArgs && Args.size() > Call->Builtin->MaxNumArgs) |
2230 | LLVM_DEBUG(dbgs() << "More arguments provided than required!\n" ); |
2231 | |
2232 | // Match the builtin with implementation based on the grouping. |
2233 | switch (Call->Builtin->Group) { |
2234 | case SPIRV::Extended: |
2235 | return generateExtInst(Call.get(), MIRBuilder, GR); |
2236 | case SPIRV::Relational: |
2237 | return generateRelationalInst(Call.get(), MIRBuilder, GR); |
2238 | case SPIRV::Group: |
2239 | return generateGroupInst(Call.get(), MIRBuilder, GR); |
2240 | case SPIRV::Variable: |
2241 | return generateBuiltinVar(Call.get(), MIRBuilder, GR); |
2242 | case SPIRV::Atomic: |
2243 | return generateAtomicInst(Call.get(), MIRBuilder, GR); |
2244 | case SPIRV::AtomicFloating: |
2245 | return generateAtomicFloatingInst(Call.get(), MIRBuilder, GR); |
2246 | case SPIRV::Barrier: |
2247 | return generateBarrierInst(Call.get(), MIRBuilder, GR); |
2248 | case SPIRV::Dot: |
2249 | return generateDotOrFMulInst(Call.get(), MIRBuilder, GR); |
2250 | case SPIRV::Wave: |
2251 | return generateWaveInst(Call.get(), MIRBuilder, GR); |
2252 | case SPIRV::GetQuery: |
2253 | return generateGetQueryInst(Call.get(), MIRBuilder, GR); |
2254 | case SPIRV::ImageSizeQuery: |
2255 | return generateImageSizeQueryInst(Call.get(), MIRBuilder, GR); |
2256 | case SPIRV::ImageMiscQuery: |
2257 | return generateImageMiscQueryInst(Call.get(), MIRBuilder, GR); |
2258 | case SPIRV::ReadImage: |
2259 | return generateReadImageInst(DemangledCall, Call.get(), MIRBuilder, GR); |
2260 | case SPIRV::WriteImage: |
2261 | return generateWriteImageInst(Call.get(), MIRBuilder, GR); |
2262 | case SPIRV::SampleImage: |
2263 | return generateSampleImageInst(DemangledCall, Call.get(), MIRBuilder, GR); |
2264 | case SPIRV::Select: |
2265 | return generateSelectInst(Call.get(), MIRBuilder); |
2266 | case SPIRV::SpecConstant: |
2267 | return generateSpecConstantInst(Call.get(), MIRBuilder, GR); |
2268 | case SPIRV::Enqueue: |
2269 | return generateEnqueueInst(Call.get(), MIRBuilder, GR); |
2270 | case SPIRV::AsyncCopy: |
2271 | return generateAsyncCopy(Call.get(), MIRBuilder, GR); |
2272 | case SPIRV::Convert: |
2273 | return generateConvertInst(DemangledCall, Call.get(), MIRBuilder, GR); |
2274 | case SPIRV::VectorLoadStore: |
2275 | return generateVectorLoadStoreInst(Call.get(), MIRBuilder, GR); |
2276 | case SPIRV::LoadStore: |
2277 | return generateLoadStoreInst(Call.get(), MIRBuilder, GR); |
2278 | case SPIRV::IntelSubgroups: |
2279 | return generateIntelSubgroupsInst(Call.get(), MIRBuilder, GR); |
2280 | case SPIRV::GroupUniform: |
2281 | return generateGroupUniformInst(Call.get(), MIRBuilder, GR); |
2282 | } |
2283 | return false; |
2284 | } |
2285 | |
2286 | Type *parseBuiltinCallArgumentBaseType(const StringRef DemangledCall, |
2287 | unsigned ArgIdx, LLVMContext &Ctx) { |
2288 | SmallVector<StringRef, 10> BuiltinArgsTypeStrs; |
2289 | StringRef BuiltinArgs = |
2290 | DemangledCall.slice(Start: DemangledCall.find(C: '(') + 1, End: DemangledCall.find(C: ')')); |
2291 | BuiltinArgs.split(BuiltinArgsTypeStrs, ',', -1, false); |
2292 | if (ArgIdx >= BuiltinArgsTypeStrs.size()) |
2293 | return nullptr; |
2294 | StringRef TypeStr = BuiltinArgsTypeStrs[ArgIdx].trim(); |
2295 | |
2296 | // Parse strings representing OpenCL builtin types. |
2297 | if (hasBuiltinTypePrefix(Name: TypeStr)) { |
2298 | // OpenCL builtin types in demangled call strings have the following format: |
2299 | // e.g. ocl_image2d_ro |
2300 | bool IsOCLBuiltinType = TypeStr.consume_front(Prefix: "ocl_" ); |
2301 | assert(IsOCLBuiltinType && "Invalid OpenCL builtin prefix" ); |
2302 | |
2303 | // Check if this is pointer to a builtin type and not just pointer |
2304 | // representing a builtin type. In case it is a pointer to builtin type, |
2305 | // this will require additional handling in the method calling |
2306 | // parseBuiltinCallArgumentBaseType(...) as this function only retrieves the |
2307 | // base types. |
2308 | if (TypeStr.ends_with(Suffix: "*" )) |
2309 | TypeStr = TypeStr.slice(Start: 0, End: TypeStr.find_first_of(Chars: " " )); |
2310 | |
2311 | return parseBuiltinTypeNameToTargetExtType("opencl." + TypeStr.str() + "_t" , |
2312 | Ctx); |
2313 | } |
2314 | |
2315 | // Parse type name in either "typeN" or "type vector[N]" format, where |
2316 | // N is the number of elements of the vector. |
2317 | Type *BaseType; |
2318 | unsigned VecElts = 0; |
2319 | |
2320 | BaseType = parseBasicTypeName(TypeName&: TypeStr, Ctx); |
2321 | if (!BaseType) |
2322 | // Unable to recognize SPIRV type name. |
2323 | return nullptr; |
2324 | |
2325 | if (BaseType->isVoidTy()) |
2326 | BaseType = Type::getInt8Ty(C&: Ctx); |
2327 | |
2328 | // Handle "typeN*" or "type vector[N]*". |
2329 | TypeStr.consume_back(Suffix: "*" ); |
2330 | |
2331 | if (TypeStr.consume_front(Prefix: " vector[" )) |
2332 | TypeStr = TypeStr.substr(Start: 0, N: TypeStr.find(C: ']')); |
2333 | |
2334 | TypeStr.getAsInteger(10, VecElts); |
2335 | if (VecElts > 0) |
2336 | BaseType = VectorType::get(ElementType: BaseType, NumElements: VecElts, Scalable: false); |
2337 | |
2338 | return BaseType; |
2339 | } |
2340 | |
2341 | struct BuiltinType { |
2342 | StringRef Name; |
2343 | uint32_t Opcode; |
2344 | }; |
2345 | |
2346 | #define GET_BuiltinTypes_DECL |
2347 | #define GET_BuiltinTypes_IMPL |
2348 | |
2349 | struct OpenCLType { |
2350 | StringRef Name; |
2351 | StringRef SpirvTypeLiteral; |
2352 | }; |
2353 | |
2354 | #define GET_OpenCLTypes_DECL |
2355 | #define GET_OpenCLTypes_IMPL |
2356 | |
2357 | #include "SPIRVGenTables.inc" |
2358 | } // namespace SPIRV |
2359 | |
2360 | //===----------------------------------------------------------------------===// |
2361 | // Misc functions for parsing builtin types. |
2362 | //===----------------------------------------------------------------------===// |
2363 | |
2364 | static Type *parseTypeString(const StringRef Name, LLVMContext &Context) { |
2365 | if (Name.starts_with(Prefix: "void" )) |
2366 | return Type::getVoidTy(C&: Context); |
2367 | else if (Name.starts_with(Prefix: "int" ) || Name.starts_with(Prefix: "uint" )) |
2368 | return Type::getInt32Ty(C&: Context); |
2369 | else if (Name.starts_with(Prefix: "float" )) |
2370 | return Type::getFloatTy(C&: Context); |
2371 | else if (Name.starts_with(Prefix: "half" )) |
2372 | return Type::getHalfTy(C&: Context); |
2373 | report_fatal_error(reason: "Unable to recognize type!" ); |
2374 | } |
2375 | |
2376 | //===----------------------------------------------------------------------===// |
2377 | // Implementation functions for builtin types. |
2378 | //===----------------------------------------------------------------------===// |
2379 | |
2380 | static SPIRVType *getNonParameterizedType(const TargetExtType *ExtensionType, |
2381 | const SPIRV::BuiltinType *TypeRecord, |
2382 | MachineIRBuilder &MIRBuilder, |
2383 | SPIRVGlobalRegistry *GR) { |
2384 | unsigned Opcode = TypeRecord->Opcode; |
2385 | // Create or get an existing type from GlobalRegistry. |
2386 | return GR->getOrCreateOpTypeByOpcode(Ty: ExtensionType, MIRBuilder, Opcode); |
2387 | } |
2388 | |
2389 | static SPIRVType *getSamplerType(MachineIRBuilder &MIRBuilder, |
2390 | SPIRVGlobalRegistry *GR) { |
2391 | // Create or get an existing type from GlobalRegistry. |
2392 | return GR->getOrCreateOpTypeSampler(MIRBuilder); |
2393 | } |
2394 | |
2395 | static SPIRVType *getPipeType(const TargetExtType *ExtensionType, |
2396 | MachineIRBuilder &MIRBuilder, |
2397 | SPIRVGlobalRegistry *GR) { |
2398 | assert(ExtensionType->getNumIntParameters() == 1 && |
2399 | "Invalid number of parameters for SPIR-V pipe builtin!" ); |
2400 | // Create or get an existing type from GlobalRegistry. |
2401 | return GR->getOrCreateOpTypePipe(MIRBuilder, |
2402 | SPIRV::AccessQualifier::AccessQualifier( |
2403 | ExtensionType->getIntParameter(0))); |
2404 | } |
2405 | |
2406 | static SPIRVType * |
2407 | getImageType(const TargetExtType *ExtensionType, |
2408 | const SPIRV::AccessQualifier::AccessQualifier Qualifier, |
2409 | MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { |
2410 | assert(ExtensionType->getNumTypeParameters() == 1 && |
2411 | "SPIR-V image builtin type must have sampled type parameter!" ); |
2412 | const SPIRVType *SampledType = |
2413 | GR->getOrCreateSPIRVType(ExtensionType->getTypeParameter(i: 0), MIRBuilder); |
2414 | assert(ExtensionType->getNumIntParameters() == 7 && |
2415 | "Invalid number of parameters for SPIR-V image builtin!" ); |
2416 | // Create or get an existing type from GlobalRegistry. |
2417 | return GR->getOrCreateOpTypeImage( |
2418 | MIRBuilder, SampledType, |
2419 | SPIRV::Dim::Dim(ExtensionType->getIntParameter(0)), |
2420 | ExtensionType->getIntParameter(1), ExtensionType->getIntParameter(2), |
2421 | ExtensionType->getIntParameter(3), ExtensionType->getIntParameter(4), |
2422 | SPIRV::ImageFormat::ImageFormat(ExtensionType->getIntParameter(5)), |
2423 | Qualifier == SPIRV::AccessQualifier::WriteOnly |
2424 | ? SPIRV::AccessQualifier::WriteOnly |
2425 | : SPIRV::AccessQualifier::AccessQualifier( |
2426 | ExtensionType->getIntParameter(6))); |
2427 | } |
2428 | |
2429 | static SPIRVType *getSampledImageType(const TargetExtType *OpaqueType, |
2430 | MachineIRBuilder &MIRBuilder, |
2431 | SPIRVGlobalRegistry *GR) { |
2432 | SPIRVType *OpaqueImageType = getImageType( |
2433 | OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR); |
2434 | // Create or get an existing type from GlobalRegistry. |
2435 | return GR->getOrCreateOpTypeSampledImage(ImageType: OpaqueImageType, MIRBuilder); |
2436 | } |
2437 | |
2438 | namespace SPIRV { |
2439 | TargetExtType *parseBuiltinTypeNameToTargetExtType(std::string TypeName, |
2440 | LLVMContext &Context) { |
2441 | StringRef NameWithParameters = TypeName; |
2442 | |
2443 | // Pointers-to-opaque-structs representing OpenCL types are first translated |
2444 | // to equivalent SPIR-V types. OpenCL builtin type names should have the |
2445 | // following format: e.g. %opencl.event_t |
2446 | if (NameWithParameters.starts_with(Prefix: "opencl." )) { |
2447 | const SPIRV::OpenCLType *OCLTypeRecord = |
2448 | SPIRV::lookupOpenCLType(NameWithParameters); |
2449 | if (!OCLTypeRecord) |
2450 | report_fatal_error(reason: "Missing TableGen record for OpenCL type: " + |
2451 | NameWithParameters); |
2452 | NameWithParameters = OCLTypeRecord->SpirvTypeLiteral; |
2453 | // Continue with the SPIR-V builtin type... |
2454 | } |
2455 | |
2456 | // Names of the opaque structs representing a SPIR-V builtins without |
2457 | // parameters should have the following format: e.g. %spirv.Event |
2458 | assert(NameWithParameters.starts_with("spirv." ) && |
2459 | "Unknown builtin opaque type!" ); |
2460 | |
2461 | // Parameterized SPIR-V builtins names follow this format: |
2462 | // e.g. %spirv.Image._void_1_0_0_0_0_0_0, %spirv.Pipe._0 |
2463 | if (!NameWithParameters.contains(C: '_')) |
2464 | return TargetExtType::get(Context, Name: NameWithParameters); |
2465 | |
2466 | SmallVector<StringRef> Parameters; |
2467 | unsigned BaseNameLength = NameWithParameters.find(C: '_') - 1; |
2468 | SplitString(NameWithParameters.substr(Start: BaseNameLength + 1), Parameters, "_" ); |
2469 | |
2470 | SmallVector<Type *, 1> TypeParameters; |
2471 | bool HasTypeParameter = !isDigit(Parameters[0][0]); |
2472 | if (HasTypeParameter) |
2473 | TypeParameters.push_back(parseTypeString(Parameters[0], Context)); |
2474 | SmallVector<unsigned> IntParameters; |
2475 | for (unsigned i = HasTypeParameter ? 1 : 0; i < Parameters.size(); i++) { |
2476 | unsigned IntParameter = 0; |
2477 | bool ValidLiteral = !Parameters[i].getAsInteger(10, IntParameter); |
2478 | (void)ValidLiteral; |
2479 | assert(ValidLiteral && |
2480 | "Invalid format of SPIR-V builtin parameter literal!" ); |
2481 | IntParameters.push_back(IntParameter); |
2482 | } |
2483 | return TargetExtType::get(Context, |
2484 | Name: NameWithParameters.substr(Start: 0, N: BaseNameLength), |
2485 | Types: TypeParameters, Ints: IntParameters); |
2486 | } |
2487 | |
2488 | SPIRVType *lowerBuiltinType(const Type *OpaqueType, |
2489 | SPIRV::AccessQualifier::AccessQualifier AccessQual, |
2490 | MachineIRBuilder &MIRBuilder, |
2491 | SPIRVGlobalRegistry *GR) { |
2492 | // In LLVM IR, SPIR-V and OpenCL builtin types are represented as either |
2493 | // target(...) target extension types or pointers-to-opaque-structs. The |
2494 | // approach relying on structs is deprecated and works only in the non-opaque |
2495 | // pointer mode (-opaque-pointers=0). |
2496 | // In order to maintain compatibility with LLVM IR generated by older versions |
2497 | // of Clang and LLVM/SPIR-V Translator, the pointers-to-opaque-structs are |
2498 | // "translated" to target extension types. This translation is temporary and |
2499 | // will be removed in the future release of LLVM. |
2500 | const TargetExtType *BuiltinType = dyn_cast<TargetExtType>(OpaqueType); |
2501 | if (!BuiltinType) |
2502 | BuiltinType = parseBuiltinTypeNameToTargetExtType( |
2503 | TypeName: OpaqueType->getStructName().str(), Context&: MIRBuilder.getContext()); |
2504 | |
2505 | unsigned NumStartingVRegs = MIRBuilder.getMRI()->getNumVirtRegs(); |
2506 | |
2507 | const StringRef Name = BuiltinType->getName(); |
2508 | LLVM_DEBUG(dbgs() << "Lowering builtin type: " << Name << "\n" ); |
2509 | |
2510 | // Lookup the demangled builtin type in the TableGen records. |
2511 | const SPIRV::BuiltinType *TypeRecord = SPIRV::lookupBuiltinType(Name); |
2512 | if (!TypeRecord) |
2513 | report_fatal_error(reason: "Missing TableGen record for builtin type: " + Name); |
2514 | |
2515 | // "Lower" the BuiltinType into TargetType. The following get<...>Type methods |
2516 | // use the implementation details from TableGen records or TargetExtType |
2517 | // parameters to either create a new OpType<...> machine instruction or get an |
2518 | // existing equivalent SPIRVType from GlobalRegistry. |
2519 | SPIRVType *TargetType; |
2520 | switch (TypeRecord->Opcode) { |
2521 | case SPIRV::OpTypeImage: |
2522 | TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GR); |
2523 | break; |
2524 | case SPIRV::OpTypePipe: |
2525 | TargetType = getPipeType(ExtensionType: BuiltinType, MIRBuilder, GR); |
2526 | break; |
2527 | case SPIRV::OpTypeDeviceEvent: |
2528 | TargetType = GR->getOrCreateOpTypeDeviceEvent(MIRBuilder); |
2529 | break; |
2530 | case SPIRV::OpTypeSampler: |
2531 | TargetType = getSamplerType(MIRBuilder, GR); |
2532 | break; |
2533 | case SPIRV::OpTypeSampledImage: |
2534 | TargetType = getSampledImageType(OpaqueType: BuiltinType, MIRBuilder, GR); |
2535 | break; |
2536 | default: |
2537 | TargetType = |
2538 | getNonParameterizedType(ExtensionType: BuiltinType, TypeRecord, MIRBuilder, GR); |
2539 | break; |
2540 | } |
2541 | |
2542 | // Emit OpName instruction if a new OpType<...> instruction was added |
2543 | // (equivalent type was not found in GlobalRegistry). |
2544 | if (NumStartingVRegs < MIRBuilder.getMRI()->getNumVirtRegs()) |
2545 | buildOpName(Target: GR->getSPIRVTypeID(SpirvType: TargetType), Name, MIRBuilder); |
2546 | |
2547 | return TargetType; |
2548 | } |
2549 | } // namespace SPIRV |
2550 | } // namespace llvm |
2551 | |