1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * srmmu.c: SRMMU specific routines for memory management. |
4 | * |
5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
6 | * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) |
7 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) |
8 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
9 | * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) |
10 | */ |
11 | |
12 | #include <linux/seq_file.h> |
13 | #include <linux/spinlock.h> |
14 | #include <linux/memblock.h> |
15 | #include <linux/pagemap.h> |
16 | #include <linux/vmalloc.h> |
17 | #include <linux/kdebug.h> |
18 | #include <linux/export.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> |
21 | #include <linux/log2.h> |
22 | #include <linux/gfp.h> |
23 | #include <linux/fs.h> |
24 | #include <linux/mm.h> |
25 | |
26 | #include <asm/mmu_context.h> |
27 | #include <asm/cacheflush.h> |
28 | #include <asm/tlbflush.h> |
29 | #include <asm/io-unit.h> |
30 | #include <asm/pgalloc.h> |
31 | #include <asm/pgtable.h> |
32 | #include <asm/bitext.h> |
33 | #include <asm/vaddrs.h> |
34 | #include <asm/cache.h> |
35 | #include <asm/traps.h> |
36 | #include <asm/oplib.h> |
37 | #include <asm/mbus.h> |
38 | #include <asm/page.h> |
39 | #include <asm/asi.h> |
40 | #include <asm/smp.h> |
41 | #include <asm/io.h> |
42 | |
43 | /* Now the cpu specific definitions. */ |
44 | #include <asm/turbosparc.h> |
45 | #include <asm/tsunami.h> |
46 | #include <asm/viking.h> |
47 | #include <asm/swift.h> |
48 | #include <asm/leon.h> |
49 | #include <asm/mxcc.h> |
50 | #include <asm/ross.h> |
51 | |
52 | #include "mm_32.h" |
53 | |
54 | enum mbus_module srmmu_modtype; |
55 | static unsigned int hwbug_bitmask; |
56 | int vac_cache_size; |
57 | EXPORT_SYMBOL(vac_cache_size); |
58 | int vac_line_size; |
59 | |
60 | extern struct resource sparc_iomap; |
61 | |
62 | extern unsigned long last_valid_pfn; |
63 | |
64 | static pgd_t *srmmu_swapper_pg_dir; |
65 | |
66 | const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; |
67 | EXPORT_SYMBOL(sparc32_cachetlb_ops); |
68 | |
69 | #ifdef CONFIG_SMP |
70 | const struct sparc32_cachetlb_ops *local_ops; |
71 | |
72 | #define FLUSH_BEGIN(mm) |
73 | #define FLUSH_END |
74 | #else |
75 | #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) { |
76 | #define FLUSH_END } |
77 | #endif |
78 | |
79 | int flush_page_for_dma_global = 1; |
80 | |
81 | char *srmmu_name; |
82 | |
83 | ctxd_t *srmmu_ctx_table_phys; |
84 | static ctxd_t *srmmu_context_table; |
85 | |
86 | int viking_mxcc_present; |
87 | static DEFINE_SPINLOCK(srmmu_context_spinlock); |
88 | |
89 | static int is_hypersparc; |
90 | |
91 | static int srmmu_cache_pagetables; |
92 | |
93 | /* these will be initialized in srmmu_nocache_calcsize() */ |
94 | static unsigned long srmmu_nocache_size; |
95 | static unsigned long srmmu_nocache_end; |
96 | |
97 | /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */ |
98 | #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4) |
99 | |
100 | /* The context table is a nocache user with the biggest alignment needs. */ |
101 | #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS) |
102 | |
103 | void *srmmu_nocache_pool; |
104 | static struct bit_map srmmu_nocache_map; |
105 | |
106 | static inline int srmmu_pmd_none(pmd_t pmd) |
107 | { return !(pmd_val(pmd) & 0xFFFFFFF); } |
108 | |
109 | /* XXX should we hyper_flush_whole_icache here - Anton */ |
110 | static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) |
111 | { |
112 | pte_t pte; |
113 | |
114 | pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4))); |
115 | set_pte(ptep: (pte_t *)ctxp, pte); |
116 | } |
117 | |
118 | /* |
119 | * Locations of MSI Registers. |
120 | */ |
121 | #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */ |
122 | |
123 | /* |
124 | * Useful bits in the MSI Registers. |
125 | */ |
126 | #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */ |
127 | |
128 | static void msi_set_sync(void) |
129 | { |
130 | __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t" |
131 | "andn %%g3, %2, %%g3\n\t" |
132 | "sta %%g3, [%0] %1\n\t" : : |
133 | "r" (MSI_MBUS_ARBEN), |
134 | "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3" ); |
135 | } |
136 | |
137 | void pmd_set(pmd_t *pmdp, pte_t *ptep) |
138 | { |
139 | unsigned long ptp = __nocache_pa(ptep) >> 4; |
140 | set_pte(ptep: (pte_t *)&pmd_val(pmd: *pmdp), pte: __pte(val: SRMMU_ET_PTD | ptp)); |
141 | } |
142 | |
143 | /* |
144 | * size: bytes to allocate in the nocache area. |
145 | * align: bytes, number to align at. |
146 | * Returns the virtual address of the allocated area. |
147 | */ |
148 | static void *__srmmu_get_nocache(int size, int align) |
149 | { |
150 | int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT; |
151 | unsigned long addr; |
152 | |
153 | if (size < minsz) { |
154 | printk(KERN_ERR "Size 0x%x too small for nocache request\n" , |
155 | size); |
156 | size = minsz; |
157 | } |
158 | if (size & (minsz - 1)) { |
159 | printk(KERN_ERR "Size 0x%x unaligned in nocache request\n" , |
160 | size); |
161 | size += minsz - 1; |
162 | } |
163 | BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX); |
164 | |
165 | offset = bit_map_string_get(&srmmu_nocache_map, |
166 | size >> SRMMU_NOCACHE_BITMAP_SHIFT, |
167 | align >> SRMMU_NOCACHE_BITMAP_SHIFT); |
168 | if (offset == -1) { |
169 | printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n" , |
170 | size, (int) srmmu_nocache_size, |
171 | srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); |
172 | return NULL; |
173 | } |
174 | |
175 | addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT); |
176 | return (void *)addr; |
177 | } |
178 | |
179 | void *srmmu_get_nocache(int size, int align) |
180 | { |
181 | void *tmp; |
182 | |
183 | tmp = __srmmu_get_nocache(size, align); |
184 | |
185 | if (tmp) |
186 | memset(tmp, 0, size); |
187 | |
188 | return tmp; |
189 | } |
190 | |
191 | void srmmu_free_nocache(void *addr, int size) |
192 | { |
193 | unsigned long vaddr; |
194 | int offset; |
195 | |
196 | vaddr = (unsigned long)addr; |
197 | if (vaddr < SRMMU_NOCACHE_VADDR) { |
198 | printk("Vaddr %lx is smaller than nocache base 0x%lx\n" , |
199 | vaddr, (unsigned long)SRMMU_NOCACHE_VADDR); |
200 | BUG(); |
201 | } |
202 | if (vaddr + size > srmmu_nocache_end) { |
203 | printk("Vaddr %lx is bigger than nocache end 0x%lx\n" , |
204 | vaddr, srmmu_nocache_end); |
205 | BUG(); |
206 | } |
207 | if (!is_power_of_2(n: size)) { |
208 | printk("Size 0x%x is not a power of 2\n" , size); |
209 | BUG(); |
210 | } |
211 | if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { |
212 | printk("Size 0x%x is too small\n" , size); |
213 | BUG(); |
214 | } |
215 | if (vaddr & (size - 1)) { |
216 | printk("Vaddr %lx is not aligned to size 0x%x\n" , vaddr, size); |
217 | BUG(); |
218 | } |
219 | |
220 | offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; |
221 | size = size >> SRMMU_NOCACHE_BITMAP_SHIFT; |
222 | |
223 | bit_map_clear(&srmmu_nocache_map, offset, size); |
224 | } |
225 | |
226 | static void srmmu_early_allocate_ptable_skeleton(unsigned long start, |
227 | unsigned long end); |
228 | |
229 | /* Return how much physical memory we have. */ |
230 | static unsigned long __init probe_memory(void) |
231 | { |
232 | unsigned long total = 0; |
233 | int i; |
234 | |
235 | for (i = 0; sp_banks[i].num_bytes; i++) |
236 | total += sp_banks[i].num_bytes; |
237 | |
238 | return total; |
239 | } |
240 | |
241 | /* |
242 | * Reserve nocache dynamically proportionally to the amount of |
243 | * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 |
244 | */ |
245 | static void __init srmmu_nocache_calcsize(void) |
246 | { |
247 | unsigned long sysmemavail = probe_memory() / 1024; |
248 | int srmmu_nocache_npages; |
249 | |
250 | srmmu_nocache_npages = |
251 | sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; |
252 | |
253 | /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */ |
254 | // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256; |
255 | if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES) |
256 | srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES; |
257 | |
258 | /* anything above 1280 blows up */ |
259 | if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES) |
260 | srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES; |
261 | |
262 | srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE; |
263 | srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size; |
264 | } |
265 | |
266 | static void __init srmmu_nocache_init(void) |
267 | { |
268 | void *srmmu_nocache_bitmap; |
269 | unsigned int bitmap_bits; |
270 | pgd_t *pgd; |
271 | p4d_t *p4d; |
272 | pud_t *pud; |
273 | pmd_t *pmd; |
274 | pte_t *pte; |
275 | unsigned long paddr, vaddr; |
276 | unsigned long pteval; |
277 | |
278 | bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT; |
279 | |
280 | srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size, |
281 | SRMMU_NOCACHE_ALIGN_MAX); |
282 | if (!srmmu_nocache_pool) |
283 | panic("%s: Failed to allocate %lu bytes align=0x%x\n" , |
284 | __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX); |
285 | memset(srmmu_nocache_pool, 0, srmmu_nocache_size); |
286 | |
287 | srmmu_nocache_bitmap = |
288 | memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long), |
289 | SMP_CACHE_BYTES); |
290 | if (!srmmu_nocache_bitmap) |
291 | panic(fmt: "%s: Failed to allocate %zu bytes\n" , __func__, |
292 | BITS_TO_LONGS(bitmap_bits) * sizeof(long)); |
293 | bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits); |
294 | |
295 | srmmu_swapper_pg_dir = __srmmu_get_nocache(size: SRMMU_PGD_TABLE_SIZE, align: SRMMU_PGD_TABLE_SIZE); |
296 | memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE); |
297 | init_mm.pgd = srmmu_swapper_pg_dir; |
298 | |
299 | srmmu_early_allocate_ptable_skeleton(start: SRMMU_NOCACHE_VADDR, end: srmmu_nocache_end); |
300 | |
301 | paddr = __pa((unsigned long)srmmu_nocache_pool); |
302 | vaddr = SRMMU_NOCACHE_VADDR; |
303 | |
304 | while (vaddr < srmmu_nocache_end) { |
305 | pgd = pgd_offset_k(vaddr); |
306 | p4d = p4d_offset(pgd, address: vaddr); |
307 | pud = pud_offset(p4d, address: vaddr); |
308 | pmd = pmd_offset(pud: __nocache_fix(pud), address: vaddr); |
309 | pte = pte_offset_kernel(pmd: __nocache_fix(pmd), address: vaddr); |
310 | |
311 | pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); |
312 | |
313 | if (srmmu_cache_pagetables) |
314 | pteval |= SRMMU_CACHE; |
315 | |
316 | set_pte(ptep: __nocache_fix(pte), pte: __pte(val: pteval)); |
317 | |
318 | vaddr += PAGE_SIZE; |
319 | paddr += PAGE_SIZE; |
320 | } |
321 | |
322 | flush_cache_all(); |
323 | flush_tlb_all(); |
324 | } |
325 | |
326 | pgd_t *get_pgd_fast(void) |
327 | { |
328 | pgd_t *pgd = NULL; |
329 | |
330 | pgd = __srmmu_get_nocache(size: SRMMU_PGD_TABLE_SIZE, align: SRMMU_PGD_TABLE_SIZE); |
331 | if (pgd) { |
332 | pgd_t *init = pgd_offset_k(0); |
333 | memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); |
334 | memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, |
335 | (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); |
336 | } |
337 | |
338 | return pgd; |
339 | } |
340 | |
341 | /* |
342 | * Hardware needs alignment to 256 only, but we align to whole page size |
343 | * to reduce fragmentation problems due to the buddy principle. |
344 | * XXX Provide actual fragmentation statistics in /proc. |
345 | * |
346 | * Alignments up to the page size are the same for physical and virtual |
347 | * addresses of the nocache area. |
348 | */ |
349 | pgtable_t pte_alloc_one(struct mm_struct *mm) |
350 | { |
351 | pte_t *ptep; |
352 | struct page *page; |
353 | |
354 | if (!(ptep = pte_alloc_one_kernel(mm))) |
355 | return NULL; |
356 | page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT); |
357 | spin_lock(lock: &mm->page_table_lock); |
358 | if (page_ref_inc_return(page) == 2 && |
359 | !pagetable_pte_ctor(page_ptdesc(page))) { |
360 | page_ref_dec(page); |
361 | ptep = NULL; |
362 | } |
363 | spin_unlock(lock: &mm->page_table_lock); |
364 | |
365 | return ptep; |
366 | } |
367 | |
368 | void pte_free(struct mm_struct *mm, pgtable_t ptep) |
369 | { |
370 | struct page *page; |
371 | |
372 | page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT); |
373 | spin_lock(lock: &mm->page_table_lock); |
374 | if (page_ref_dec_return(page) == 1) |
375 | pagetable_pte_dtor(page_ptdesc(page)); |
376 | spin_unlock(lock: &mm->page_table_lock); |
377 | |
378 | srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE); |
379 | } |
380 | |
381 | /* context handling - a dynamically sized pool is used */ |
382 | #define NO_CONTEXT -1 |
383 | |
384 | struct ctx_list { |
385 | struct ctx_list *next; |
386 | struct ctx_list *prev; |
387 | unsigned int ctx_number; |
388 | struct mm_struct *ctx_mm; |
389 | }; |
390 | |
391 | static struct ctx_list *ctx_list_pool; |
392 | static struct ctx_list ctx_free; |
393 | static struct ctx_list ctx_used; |
394 | |
395 | /* At boot time we determine the number of contexts */ |
396 | static int num_contexts; |
397 | |
398 | static inline void remove_from_ctx_list(struct ctx_list *entry) |
399 | { |
400 | entry->next->prev = entry->prev; |
401 | entry->prev->next = entry->next; |
402 | } |
403 | |
404 | static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry) |
405 | { |
406 | entry->next = head; |
407 | (entry->prev = head->prev)->next = entry; |
408 | head->prev = entry; |
409 | } |
410 | #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry) |
411 | #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry) |
412 | |
413 | |
414 | static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) |
415 | { |
416 | struct ctx_list *ctxp; |
417 | |
418 | ctxp = ctx_free.next; |
419 | if (ctxp != &ctx_free) { |
420 | remove_from_ctx_list(entry: ctxp); |
421 | add_to_used_ctxlist(ctxp); |
422 | mm->context = ctxp->ctx_number; |
423 | ctxp->ctx_mm = mm; |
424 | return; |
425 | } |
426 | ctxp = ctx_used.next; |
427 | if (ctxp->ctx_mm == old_mm) |
428 | ctxp = ctxp->next; |
429 | if (ctxp == &ctx_used) |
430 | panic(fmt: "out of mmu contexts" ); |
431 | flush_cache_mm(mm: ctxp->ctx_mm); |
432 | flush_tlb_mm(ctxp->ctx_mm); |
433 | remove_from_ctx_list(entry: ctxp); |
434 | add_to_used_ctxlist(ctxp); |
435 | ctxp->ctx_mm->context = NO_CONTEXT; |
436 | ctxp->ctx_mm = mm; |
437 | mm->context = ctxp->ctx_number; |
438 | } |
439 | |
440 | static inline void free_context(int context) |
441 | { |
442 | struct ctx_list *ctx_old; |
443 | |
444 | ctx_old = ctx_list_pool + context; |
445 | remove_from_ctx_list(entry: ctx_old); |
446 | add_to_free_ctxlist(ctx_old); |
447 | } |
448 | |
449 | static void __init sparc_context_init(int numctx) |
450 | { |
451 | int ctx; |
452 | unsigned long size; |
453 | |
454 | size = numctx * sizeof(struct ctx_list); |
455 | ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES); |
456 | if (!ctx_list_pool) |
457 | panic(fmt: "%s: Failed to allocate %lu bytes\n" , __func__, size); |
458 | |
459 | for (ctx = 0; ctx < numctx; ctx++) { |
460 | struct ctx_list *clist; |
461 | |
462 | clist = (ctx_list_pool + ctx); |
463 | clist->ctx_number = ctx; |
464 | clist->ctx_mm = NULL; |
465 | } |
466 | ctx_free.next = ctx_free.prev = &ctx_free; |
467 | ctx_used.next = ctx_used.prev = &ctx_used; |
468 | for (ctx = 0; ctx < numctx; ctx++) |
469 | add_to_free_ctxlist(ctx_list_pool + ctx); |
470 | } |
471 | |
472 | void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, |
473 | struct task_struct *tsk) |
474 | { |
475 | unsigned long flags; |
476 | |
477 | if (mm->context == NO_CONTEXT) { |
478 | spin_lock_irqsave(&srmmu_context_spinlock, flags); |
479 | alloc_context(old_mm, mm); |
480 | spin_unlock_irqrestore(lock: &srmmu_context_spinlock, flags); |
481 | srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd); |
482 | } |
483 | |
484 | if (sparc_cpu_model == sparc_leon) |
485 | leon_switch_mm(); |
486 | |
487 | if (is_hypersparc) |
488 | hyper_flush_whole_icache(); |
489 | |
490 | srmmu_set_context(mm->context); |
491 | } |
492 | |
493 | /* Low level IO area allocation on the SRMMU. */ |
494 | static inline void srmmu_mapioaddr(unsigned long physaddr, |
495 | unsigned long virt_addr, int bus_type) |
496 | { |
497 | pgd_t *pgdp; |
498 | p4d_t *p4dp; |
499 | pud_t *pudp; |
500 | pmd_t *pmdp; |
501 | pte_t *ptep; |
502 | unsigned long tmp; |
503 | |
504 | physaddr &= PAGE_MASK; |
505 | pgdp = pgd_offset_k(virt_addr); |
506 | p4dp = p4d_offset(pgd: pgdp, address: virt_addr); |
507 | pudp = pud_offset(p4d: p4dp, address: virt_addr); |
508 | pmdp = pmd_offset(pud: pudp, address: virt_addr); |
509 | ptep = pte_offset_kernel(pmd: pmdp, address: virt_addr); |
510 | tmp = (physaddr >> 4) | SRMMU_ET_PTE; |
511 | |
512 | /* I need to test whether this is consistent over all |
513 | * sun4m's. The bus_type represents the upper 4 bits of |
514 | * 36-bit physical address on the I/O space lines... |
515 | */ |
516 | tmp |= (bus_type << 28); |
517 | tmp |= SRMMU_PRIV; |
518 | __flush_page_to_ram(virt_addr); |
519 | set_pte(ptep, pte: __pte(val: tmp)); |
520 | } |
521 | |
522 | void srmmu_mapiorange(unsigned int bus, unsigned long xpa, |
523 | unsigned long xva, unsigned int len) |
524 | { |
525 | while (len != 0) { |
526 | len -= PAGE_SIZE; |
527 | srmmu_mapioaddr(physaddr: xpa, virt_addr: xva, bus_type: bus); |
528 | xva += PAGE_SIZE; |
529 | xpa += PAGE_SIZE; |
530 | } |
531 | flush_tlb_all(); |
532 | } |
533 | |
534 | static inline void srmmu_unmapioaddr(unsigned long virt_addr) |
535 | { |
536 | pgd_t *pgdp; |
537 | p4d_t *p4dp; |
538 | pud_t *pudp; |
539 | pmd_t *pmdp; |
540 | pte_t *ptep; |
541 | |
542 | |
543 | pgdp = pgd_offset_k(virt_addr); |
544 | p4dp = p4d_offset(pgd: pgdp, address: virt_addr); |
545 | pudp = pud_offset(p4d: p4dp, address: virt_addr); |
546 | pmdp = pmd_offset(pud: pudp, address: virt_addr); |
547 | ptep = pte_offset_kernel(pmd: pmdp, address: virt_addr); |
548 | |
549 | /* No need to flush uncacheable page. */ |
550 | __pte_clear(ptep); |
551 | } |
552 | |
553 | void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) |
554 | { |
555 | while (len != 0) { |
556 | len -= PAGE_SIZE; |
557 | srmmu_unmapioaddr(virt_addr); |
558 | virt_addr += PAGE_SIZE; |
559 | } |
560 | flush_tlb_all(); |
561 | } |
562 | |
563 | /* tsunami.S */ |
564 | extern void tsunami_flush_cache_all(void); |
565 | extern void tsunami_flush_cache_mm(struct mm_struct *mm); |
566 | extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
567 | extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page); |
568 | extern void tsunami_flush_page_to_ram(unsigned long page); |
569 | extern void tsunami_flush_page_for_dma(unsigned long page); |
570 | extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); |
571 | extern void tsunami_flush_tlb_all(void); |
572 | extern void tsunami_flush_tlb_mm(struct mm_struct *mm); |
573 | extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
574 | extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); |
575 | extern void tsunami_setup_blockops(void); |
576 | |
577 | /* swift.S */ |
578 | extern void swift_flush_cache_all(void); |
579 | extern void swift_flush_cache_mm(struct mm_struct *mm); |
580 | extern void swift_flush_cache_range(struct vm_area_struct *vma, |
581 | unsigned long start, unsigned long end); |
582 | extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page); |
583 | extern void swift_flush_page_to_ram(unsigned long page); |
584 | extern void swift_flush_page_for_dma(unsigned long page); |
585 | extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); |
586 | extern void swift_flush_tlb_all(void); |
587 | extern void swift_flush_tlb_mm(struct mm_struct *mm); |
588 | extern void swift_flush_tlb_range(struct vm_area_struct *vma, |
589 | unsigned long start, unsigned long end); |
590 | extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); |
591 | |
592 | #if 0 /* P3: deadwood to debug precise flushes on Swift. */ |
593 | void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
594 | { |
595 | int cctx, ctx1; |
596 | |
597 | page &= PAGE_MASK; |
598 | if ((ctx1 = vma->vm_mm->context) != -1) { |
599 | cctx = srmmu_get_context(); |
600 | /* Is context # ever different from current context? P3 */ |
601 | if (cctx != ctx1) { |
602 | printk("flush ctx %02x curr %02x\n" , ctx1, cctx); |
603 | srmmu_set_context(ctx1); |
604 | swift_flush_page(page); |
605 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : |
606 | "r" (page), "i" (ASI_M_FLUSH_PROBE)); |
607 | srmmu_set_context(cctx); |
608 | } else { |
609 | /* Rm. prot. bits from virt. c. */ |
610 | /* swift_flush_cache_all(); */ |
611 | /* swift_flush_cache_page(vma, page); */ |
612 | swift_flush_page(page); |
613 | |
614 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : |
615 | "r" (page), "i" (ASI_M_FLUSH_PROBE)); |
616 | /* same as above: srmmu_flush_tlb_page() */ |
617 | } |
618 | } |
619 | } |
620 | #endif |
621 | |
622 | /* |
623 | * The following are all MBUS based SRMMU modules, and therefore could |
624 | * be found in a multiprocessor configuration. On the whole, these |
625 | * chips seems to be much more touchy about DVMA and page tables |
626 | * with respect to cache coherency. |
627 | */ |
628 | |
629 | /* viking.S */ |
630 | extern void viking_flush_cache_all(void); |
631 | extern void viking_flush_cache_mm(struct mm_struct *mm); |
632 | extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start, |
633 | unsigned long end); |
634 | extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page); |
635 | extern void viking_flush_page_to_ram(unsigned long page); |
636 | extern void viking_flush_page_for_dma(unsigned long page); |
637 | extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr); |
638 | extern void viking_flush_page(unsigned long page); |
639 | extern void viking_mxcc_flush_page(unsigned long page); |
640 | extern void viking_flush_tlb_all(void); |
641 | extern void viking_flush_tlb_mm(struct mm_struct *mm); |
642 | extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
643 | unsigned long end); |
644 | extern void viking_flush_tlb_page(struct vm_area_struct *vma, |
645 | unsigned long page); |
646 | extern void sun4dsmp_flush_tlb_all(void); |
647 | extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm); |
648 | extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
649 | unsigned long end); |
650 | extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma, |
651 | unsigned long page); |
652 | |
653 | /* hypersparc.S */ |
654 | extern void hypersparc_flush_cache_all(void); |
655 | extern void hypersparc_flush_cache_mm(struct mm_struct *mm); |
656 | extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
657 | extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page); |
658 | extern void hypersparc_flush_page_to_ram(unsigned long page); |
659 | extern void hypersparc_flush_page_for_dma(unsigned long page); |
660 | extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); |
661 | extern void hypersparc_flush_tlb_all(void); |
662 | extern void hypersparc_flush_tlb_mm(struct mm_struct *mm); |
663 | extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); |
664 | extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); |
665 | extern void hypersparc_setup_blockops(void); |
666 | |
667 | /* |
668 | * NOTE: All of this startup code assumes the low 16mb (approx.) of |
669 | * kernel mappings are done with one single contiguous chunk of |
670 | * ram. On small ram machines (classics mainly) we only get |
671 | * around 8mb mapped for us. |
672 | */ |
673 | |
674 | static void __init early_pgtable_allocfail(char *type) |
675 | { |
676 | prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n" , type); |
677 | prom_halt(); |
678 | } |
679 | |
680 | static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, |
681 | unsigned long end) |
682 | { |
683 | pgd_t *pgdp; |
684 | p4d_t *p4dp; |
685 | pud_t *pudp; |
686 | pmd_t *pmdp; |
687 | pte_t *ptep; |
688 | |
689 | while (start < end) { |
690 | pgdp = pgd_offset_k(start); |
691 | p4dp = p4d_offset(pgd: pgdp, address: start); |
692 | pudp = pud_offset(p4d: p4dp, address: start); |
693 | if (pud_none(pud: *__nocache_fix(pudp))) { |
694 | pmdp = __srmmu_get_nocache( |
695 | SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); |
696 | if (pmdp == NULL) |
697 | early_pgtable_allocfail(type: "pmd" ); |
698 | memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); |
699 | pud_set(__nocache_fix(pudp), pmdp); |
700 | } |
701 | pmdp = pmd_offset(pud: __nocache_fix(pudp), address: start); |
702 | if (srmmu_pmd_none(pmd: *__nocache_fix(pmdp))) { |
703 | ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); |
704 | if (ptep == NULL) |
705 | early_pgtable_allocfail(type: "pte" ); |
706 | memset(__nocache_fix(ptep), 0, PTE_SIZE); |
707 | pmd_set(pmdp: __nocache_fix(pmdp), ptep); |
708 | } |
709 | if (start > (0xffffffffUL - PMD_SIZE)) |
710 | break; |
711 | start = (start + PMD_SIZE) & PMD_MASK; |
712 | } |
713 | } |
714 | |
715 | static void __init srmmu_allocate_ptable_skeleton(unsigned long start, |
716 | unsigned long end) |
717 | { |
718 | pgd_t *pgdp; |
719 | p4d_t *p4dp; |
720 | pud_t *pudp; |
721 | pmd_t *pmdp; |
722 | pte_t *ptep; |
723 | |
724 | while (start < end) { |
725 | pgdp = pgd_offset_k(start); |
726 | p4dp = p4d_offset(pgd: pgdp, address: start); |
727 | pudp = pud_offset(p4d: p4dp, address: start); |
728 | if (pud_none(pud: *pudp)) { |
729 | pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); |
730 | if (pmdp == NULL) |
731 | early_pgtable_allocfail(type: "pmd" ); |
732 | memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); |
733 | pud_set((pud_t *)pgdp, pmdp); |
734 | } |
735 | pmdp = pmd_offset(pud: pudp, address: start); |
736 | if (srmmu_pmd_none(pmd: *pmdp)) { |
737 | ptep = __srmmu_get_nocache(PTE_SIZE, |
738 | PTE_SIZE); |
739 | if (ptep == NULL) |
740 | early_pgtable_allocfail(type: "pte" ); |
741 | memset(ptep, 0, PTE_SIZE); |
742 | pmd_set(pmdp, ptep); |
743 | } |
744 | if (start > (0xffffffffUL - PMD_SIZE)) |
745 | break; |
746 | start = (start + PMD_SIZE) & PMD_MASK; |
747 | } |
748 | } |
749 | |
750 | /* These flush types are not available on all chips... */ |
751 | static inline unsigned long srmmu_probe(unsigned long vaddr) |
752 | { |
753 | unsigned long retval; |
754 | |
755 | if (sparc_cpu_model != sparc_leon) { |
756 | |
757 | vaddr &= PAGE_MASK; |
758 | __asm__ __volatile__("lda [%1] %2, %0\n\t" : |
759 | "=r" (retval) : |
760 | "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE)); |
761 | } else { |
762 | retval = leon_swprobe(vaddr, NULL); |
763 | } |
764 | return retval; |
765 | } |
766 | |
767 | /* |
768 | * This is much cleaner than poking around physical address space |
769 | * looking at the prom's page table directly which is what most |
770 | * other OS's do. Yuck... this is much better. |
771 | */ |
772 | static void __init srmmu_inherit_prom_mappings(unsigned long start, |
773 | unsigned long end) |
774 | { |
775 | unsigned long probed; |
776 | unsigned long addr; |
777 | pgd_t *pgdp; |
778 | p4d_t *p4dp; |
779 | pud_t *pudp; |
780 | pmd_t *pmdp; |
781 | pte_t *ptep; |
782 | int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */ |
783 | |
784 | while (start <= end) { |
785 | if (start == 0) |
786 | break; /* probably wrap around */ |
787 | if (start == 0xfef00000) |
788 | start = KADB_DEBUGGER_BEGVM; |
789 | probed = srmmu_probe(vaddr: start); |
790 | if (!probed) { |
791 | /* continue probing until we find an entry */ |
792 | start += PAGE_SIZE; |
793 | continue; |
794 | } |
795 | |
796 | /* A red snapper, see what it really is. */ |
797 | what = 0; |
798 | addr = start - PAGE_SIZE; |
799 | |
800 | if (!(start & ~(PMD_MASK))) { |
801 | if (srmmu_probe(vaddr: addr + PMD_SIZE) == probed) |
802 | what = 1; |
803 | } |
804 | |
805 | if (!(start & ~(PGDIR_MASK))) { |
806 | if (srmmu_probe(vaddr: addr + PGDIR_SIZE) == probed) |
807 | what = 2; |
808 | } |
809 | |
810 | pgdp = pgd_offset_k(start); |
811 | p4dp = p4d_offset(pgd: pgdp, address: start); |
812 | pudp = pud_offset(p4d: p4dp, address: start); |
813 | if (what == 2) { |
814 | *__nocache_fix(pgdp) = __pgd(val: probed); |
815 | start += PGDIR_SIZE; |
816 | continue; |
817 | } |
818 | if (pud_none(pud: *__nocache_fix(pudp))) { |
819 | pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, |
820 | SRMMU_PMD_TABLE_SIZE); |
821 | if (pmdp == NULL) |
822 | early_pgtable_allocfail(type: "pmd" ); |
823 | memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); |
824 | pud_set(__nocache_fix(pudp), pmdp); |
825 | } |
826 | pmdp = pmd_offset(pud: __nocache_fix(pudp), address: start); |
827 | if (what == 1) { |
828 | *(pmd_t *)__nocache_fix(pmdp) = __pmd(val: probed); |
829 | start += PMD_SIZE; |
830 | continue; |
831 | } |
832 | if (srmmu_pmd_none(pmd: *__nocache_fix(pmdp))) { |
833 | ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); |
834 | if (ptep == NULL) |
835 | early_pgtable_allocfail(type: "pte" ); |
836 | memset(__nocache_fix(ptep), 0, PTE_SIZE); |
837 | pmd_set(pmdp: __nocache_fix(pmdp), ptep); |
838 | } |
839 | ptep = pte_offset_kernel(pmd: __nocache_fix(pmdp), address: start); |
840 | *__nocache_fix(ptep) = __pte(val: probed); |
841 | start += PAGE_SIZE; |
842 | } |
843 | } |
844 | |
845 | #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID) |
846 | |
847 | /* Create a third-level SRMMU 16MB page mapping. */ |
848 | static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base) |
849 | { |
850 | pgd_t *pgdp = pgd_offset_k(vaddr); |
851 | unsigned long big_pte; |
852 | |
853 | big_pte = KERNEL_PTE(phys_base >> 4); |
854 | *__nocache_fix(pgdp) = __pgd(val: big_pte); |
855 | } |
856 | |
857 | /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */ |
858 | static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) |
859 | { |
860 | unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK); |
861 | unsigned long vstart = (vbase & PGDIR_MASK); |
862 | unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes); |
863 | /* Map "low" memory only */ |
864 | const unsigned long min_vaddr = PAGE_OFFSET; |
865 | const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM; |
866 | |
867 | if (vstart < min_vaddr || vstart >= max_vaddr) |
868 | return vstart; |
869 | |
870 | if (vend > max_vaddr || vend < min_vaddr) |
871 | vend = max_vaddr; |
872 | |
873 | while (vstart < vend) { |
874 | do_large_mapping(vaddr: vstart, phys_base: pstart); |
875 | vstart += PGDIR_SIZE; pstart += PGDIR_SIZE; |
876 | } |
877 | return vstart; |
878 | } |
879 | |
880 | static void __init map_kernel(void) |
881 | { |
882 | int i; |
883 | |
884 | if (phys_base > 0) { |
885 | do_large_mapping(PAGE_OFFSET, phys_base); |
886 | } |
887 | |
888 | for (i = 0; sp_banks[i].num_bytes != 0; i++) { |
889 | map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); |
890 | } |
891 | } |
892 | |
893 | void (*poke_srmmu)(void) = NULL; |
894 | |
895 | void __init srmmu_paging_init(void) |
896 | { |
897 | int i; |
898 | phandle cpunode; |
899 | char node_str[128]; |
900 | pgd_t *pgd; |
901 | p4d_t *p4d; |
902 | pud_t *pud; |
903 | pmd_t *pmd; |
904 | pte_t *pte; |
905 | unsigned long pages_avail; |
906 | |
907 | init_mm.context = (unsigned long) NO_CONTEXT; |
908 | sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */ |
909 | |
910 | if (sparc_cpu_model == sun4d) |
911 | num_contexts = 65536; /* We know it is Viking */ |
912 | else { |
913 | /* Find the number of contexts on the srmmu. */ |
914 | cpunode = prom_getchild(prom_root_node); |
915 | num_contexts = 0; |
916 | while (cpunode != 0) { |
917 | prom_getstring(cpunode, "device_type" , node_str, sizeof(node_str)); |
918 | if (!strcmp(node_str, "cpu" )) { |
919 | num_contexts = prom_getintdefault(cpunode, "mmu-nctx" , 0x8); |
920 | break; |
921 | } |
922 | cpunode = prom_getsibling(cpunode); |
923 | } |
924 | } |
925 | |
926 | if (!num_contexts) { |
927 | prom_printf("Something wrong, can't find cpu node in paging_init.\n" ); |
928 | prom_halt(); |
929 | } |
930 | |
931 | pages_avail = 0; |
932 | last_valid_pfn = bootmem_init(&pages_avail); |
933 | |
934 | srmmu_nocache_calcsize(); |
935 | srmmu_nocache_init(); |
936 | srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE)); |
937 | map_kernel(); |
938 | |
939 | /* ctx table has to be physically aligned to its size */ |
940 | srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t)); |
941 | srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table); |
942 | |
943 | for (i = 0; i < num_contexts; i++) |
944 | srmmu_ctxd_set(__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir); |
945 | |
946 | flush_cache_all(); |
947 | srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); |
948 | #ifdef CONFIG_SMP |
949 | /* Stop from hanging here... */ |
950 | local_ops->tlb_all(); |
951 | #else |
952 | flush_tlb_all(); |
953 | #endif |
954 | poke_srmmu(); |
955 | |
956 | srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END); |
957 | srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END); |
958 | |
959 | srmmu_allocate_ptable_skeleton( |
960 | __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP); |
961 | srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); |
962 | |
963 | pgd = pgd_offset_k(PKMAP_BASE); |
964 | p4d = p4d_offset(pgd, PKMAP_BASE); |
965 | pud = pud_offset(p4d, PKMAP_BASE); |
966 | pmd = pmd_offset(pud, PKMAP_BASE); |
967 | pte = pte_offset_kernel(pmd, PKMAP_BASE); |
968 | pkmap_page_table = pte; |
969 | |
970 | flush_cache_all(); |
971 | flush_tlb_all(); |
972 | |
973 | sparc_context_init(numctx: num_contexts); |
974 | |
975 | { |
976 | unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; |
977 | |
978 | max_zone_pfn[ZONE_DMA] = max_low_pfn; |
979 | max_zone_pfn[ZONE_NORMAL] = max_low_pfn; |
980 | max_zone_pfn[ZONE_HIGHMEM] = highend_pfn; |
981 | |
982 | free_area_init(max_zone_pfn: max_zone_pfn); |
983 | } |
984 | } |
985 | |
986 | void mmu_info(struct seq_file *m) |
987 | { |
988 | seq_printf(m, |
989 | fmt: "MMU type\t: %s\n" |
990 | "contexts\t: %d\n" |
991 | "nocache total\t: %ld\n" |
992 | "nocache used\t: %d\n" , |
993 | srmmu_name, |
994 | num_contexts, |
995 | srmmu_nocache_size, |
996 | srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); |
997 | } |
998 | |
999 | int init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
1000 | { |
1001 | mm->context = NO_CONTEXT; |
1002 | return 0; |
1003 | } |
1004 | |
1005 | void destroy_context(struct mm_struct *mm) |
1006 | { |
1007 | unsigned long flags; |
1008 | |
1009 | if (mm->context != NO_CONTEXT) { |
1010 | flush_cache_mm(mm); |
1011 | srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir); |
1012 | flush_tlb_mm(mm); |
1013 | spin_lock_irqsave(&srmmu_context_spinlock, flags); |
1014 | free_context(mm->context); |
1015 | spin_unlock_irqrestore(lock: &srmmu_context_spinlock, flags); |
1016 | mm->context = NO_CONTEXT; |
1017 | } |
1018 | } |
1019 | |
1020 | /* Init various srmmu chip types. */ |
1021 | static void __init srmmu_is_bad(void) |
1022 | { |
1023 | prom_printf("Could not determine SRMMU chip type.\n" ); |
1024 | prom_halt(); |
1025 | } |
1026 | |
1027 | static void __init init_vac_layout(void) |
1028 | { |
1029 | phandle nd; |
1030 | int cache_lines; |
1031 | char node_str[128]; |
1032 | #ifdef CONFIG_SMP |
1033 | int cpu = 0; |
1034 | unsigned long max_size = 0; |
1035 | unsigned long min_line_size = 0x10000000; |
1036 | #endif |
1037 | |
1038 | nd = prom_getchild(prom_root_node); |
1039 | while ((nd = prom_getsibling(nd)) != 0) { |
1040 | prom_getstring(nd, "device_type" , node_str, sizeof(node_str)); |
1041 | if (!strcmp(node_str, "cpu" )) { |
1042 | vac_line_size = prom_getint(nd, "cache-line-size" ); |
1043 | if (vac_line_size == -1) { |
1044 | prom_printf("can't determine cache-line-size, halting.\n" ); |
1045 | prom_halt(); |
1046 | } |
1047 | cache_lines = prom_getint(nd, "cache-nlines" ); |
1048 | if (cache_lines == -1) { |
1049 | prom_printf("can't determine cache-nlines, halting.\n" ); |
1050 | prom_halt(); |
1051 | } |
1052 | |
1053 | vac_cache_size = cache_lines * vac_line_size; |
1054 | #ifdef CONFIG_SMP |
1055 | if (vac_cache_size > max_size) |
1056 | max_size = vac_cache_size; |
1057 | if (vac_line_size < min_line_size) |
1058 | min_line_size = vac_line_size; |
1059 | //FIXME: cpus not contiguous!! |
1060 | cpu++; |
1061 | if (cpu >= nr_cpu_ids || !cpu_online(cpu)) |
1062 | break; |
1063 | #else |
1064 | break; |
1065 | #endif |
1066 | } |
1067 | } |
1068 | if (nd == 0) { |
1069 | prom_printf("No CPU nodes found, halting.\n" ); |
1070 | prom_halt(); |
1071 | } |
1072 | #ifdef CONFIG_SMP |
1073 | vac_cache_size = max_size; |
1074 | vac_line_size = min_line_size; |
1075 | #endif |
1076 | printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n" , |
1077 | (int)vac_cache_size, (int)vac_line_size); |
1078 | } |
1079 | |
1080 | static void poke_hypersparc(void) |
1081 | { |
1082 | volatile unsigned long clear; |
1083 | unsigned long mreg = srmmu_get_mmureg(); |
1084 | |
1085 | hyper_flush_unconditional_combined(); |
1086 | |
1087 | mreg &= ~(HYPERSPARC_CWENABLE); |
1088 | mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE); |
1089 | mreg |= (HYPERSPARC_CMODE); |
1090 | |
1091 | srmmu_set_mmureg(mreg); |
1092 | |
1093 | #if 0 /* XXX I think this is bad news... -DaveM */ |
1094 | hyper_clear_all_tags(); |
1095 | #endif |
1096 | |
1097 | put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE); |
1098 | hyper_flush_whole_icache(); |
1099 | clear = srmmu_get_faddr(); |
1100 | clear = srmmu_get_fstatus(); |
1101 | } |
1102 | |
1103 | static const struct sparc32_cachetlb_ops hypersparc_ops = { |
1104 | .cache_all = hypersparc_flush_cache_all, |
1105 | .cache_mm = hypersparc_flush_cache_mm, |
1106 | .cache_page = hypersparc_flush_cache_page, |
1107 | .cache_range = hypersparc_flush_cache_range, |
1108 | .tlb_all = hypersparc_flush_tlb_all, |
1109 | .tlb_mm = hypersparc_flush_tlb_mm, |
1110 | .tlb_page = hypersparc_flush_tlb_page, |
1111 | .tlb_range = hypersparc_flush_tlb_range, |
1112 | .page_to_ram = hypersparc_flush_page_to_ram, |
1113 | .sig_insns = hypersparc_flush_sig_insns, |
1114 | .page_for_dma = hypersparc_flush_page_for_dma, |
1115 | }; |
1116 | |
1117 | static void __init init_hypersparc(void) |
1118 | { |
1119 | srmmu_name = "ROSS HyperSparc" ; |
1120 | srmmu_modtype = HyperSparc; |
1121 | |
1122 | init_vac_layout(); |
1123 | |
1124 | is_hypersparc = 1; |
1125 | sparc32_cachetlb_ops = &hypersparc_ops; |
1126 | |
1127 | poke_srmmu = poke_hypersparc; |
1128 | |
1129 | hypersparc_setup_blockops(); |
1130 | } |
1131 | |
1132 | static void poke_swift(void) |
1133 | { |
1134 | unsigned long mreg; |
1135 | |
1136 | /* Clear any crap from the cache or else... */ |
1137 | swift_flush_cache_all(); |
1138 | |
1139 | /* Enable I & D caches */ |
1140 | mreg = srmmu_get_mmureg(); |
1141 | mreg |= (SWIFT_IE | SWIFT_DE); |
1142 | /* |
1143 | * The Swift branch folding logic is completely broken. At |
1144 | * trap time, if things are just right, if can mistakenly |
1145 | * think that a trap is coming from kernel mode when in fact |
1146 | * it is coming from user mode (it mis-executes the branch in |
1147 | * the trap code). So you see things like crashme completely |
1148 | * hosing your machine which is completely unacceptable. Turn |
1149 | * this shit off... nice job Fujitsu. |
1150 | */ |
1151 | mreg &= ~(SWIFT_BF); |
1152 | srmmu_set_mmureg(mreg); |
1153 | } |
1154 | |
1155 | static const struct sparc32_cachetlb_ops swift_ops = { |
1156 | .cache_all = swift_flush_cache_all, |
1157 | .cache_mm = swift_flush_cache_mm, |
1158 | .cache_page = swift_flush_cache_page, |
1159 | .cache_range = swift_flush_cache_range, |
1160 | .tlb_all = swift_flush_tlb_all, |
1161 | .tlb_mm = swift_flush_tlb_mm, |
1162 | .tlb_page = swift_flush_tlb_page, |
1163 | .tlb_range = swift_flush_tlb_range, |
1164 | .page_to_ram = swift_flush_page_to_ram, |
1165 | .sig_insns = swift_flush_sig_insns, |
1166 | .page_for_dma = swift_flush_page_for_dma, |
1167 | }; |
1168 | |
1169 | #define SWIFT_MASKID_ADDR 0x10003018 |
1170 | static void __init init_swift(void) |
1171 | { |
1172 | unsigned long swift_rev; |
1173 | |
1174 | __asm__ __volatile__("lda [%1] %2, %0\n\t" |
1175 | "srl %0, 0x18, %0\n\t" : |
1176 | "=r" (swift_rev) : |
1177 | "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS)); |
1178 | srmmu_name = "Fujitsu Swift" ; |
1179 | switch (swift_rev) { |
1180 | case 0x11: |
1181 | case 0x20: |
1182 | case 0x23: |
1183 | case 0x30: |
1184 | srmmu_modtype = Swift_lots_o_bugs; |
1185 | hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN); |
1186 | /* |
1187 | * Gee george, I wonder why Sun is so hush hush about |
1188 | * this hardware bug... really braindamage stuff going |
1189 | * on here. However I think we can find a way to avoid |
1190 | * all of the workaround overhead under Linux. Basically, |
1191 | * any page fault can cause kernel pages to become user |
1192 | * accessible (the mmu gets confused and clears some of |
1193 | * the ACC bits in kernel ptes). Aha, sounds pretty |
1194 | * horrible eh? But wait, after extensive testing it appears |
1195 | * that if you use pgd_t level large kernel pte's (like the |
1196 | * 4MB pages on the Pentium) the bug does not get tripped |
1197 | * at all. This avoids almost all of the major overhead. |
1198 | * Welcome to a world where your vendor tells you to, |
1199 | * "apply this kernel patch" instead of "sorry for the |
1200 | * broken hardware, send it back and we'll give you |
1201 | * properly functioning parts" |
1202 | */ |
1203 | break; |
1204 | case 0x25: |
1205 | case 0x31: |
1206 | srmmu_modtype = Swift_bad_c; |
1207 | hwbug_bitmask |= HWBUG_KERN_CBITBROKEN; |
1208 | /* |
1209 | * You see Sun allude to this hardware bug but never |
1210 | * admit things directly, they'll say things like, |
1211 | * "the Swift chip cache problems" or similar. |
1212 | */ |
1213 | break; |
1214 | default: |
1215 | srmmu_modtype = Swift_ok; |
1216 | break; |
1217 | } |
1218 | |
1219 | sparc32_cachetlb_ops = &swift_ops; |
1220 | flush_page_for_dma_global = 0; |
1221 | |
1222 | /* |
1223 | * Are you now convinced that the Swift is one of the |
1224 | * biggest VLSI abortions of all time? Bravo Fujitsu! |
1225 | * Fujitsu, the !#?!%$'d up processor people. I bet if |
1226 | * you examined the microcode of the Swift you'd find |
1227 | * XXX's all over the place. |
1228 | */ |
1229 | poke_srmmu = poke_swift; |
1230 | } |
1231 | |
1232 | static void turbosparc_flush_cache_all(void) |
1233 | { |
1234 | flush_user_windows(); |
1235 | turbosparc_idflash_clear(); |
1236 | } |
1237 | |
1238 | static void turbosparc_flush_cache_mm(struct mm_struct *mm) |
1239 | { |
1240 | FLUSH_BEGIN(mm) |
1241 | flush_user_windows(); |
1242 | turbosparc_idflash_clear(); |
1243 | FLUSH_END |
1244 | } |
1245 | |
1246 | static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
1247 | { |
1248 | FLUSH_BEGIN(vma->vm_mm) |
1249 | flush_user_windows(); |
1250 | turbosparc_idflash_clear(); |
1251 | FLUSH_END |
1252 | } |
1253 | |
1254 | static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page) |
1255 | { |
1256 | FLUSH_BEGIN(vma->vm_mm) |
1257 | flush_user_windows(); |
1258 | if (vma->vm_flags & VM_EXEC) |
1259 | turbosparc_flush_icache(); |
1260 | turbosparc_flush_dcache(); |
1261 | FLUSH_END |
1262 | } |
1263 | |
1264 | /* TurboSparc is copy-back, if we turn it on, but this does not work. */ |
1265 | static void turbosparc_flush_page_to_ram(unsigned long page) |
1266 | { |
1267 | #ifdef TURBOSPARC_WRITEBACK |
1268 | volatile unsigned long clear; |
1269 | |
1270 | if (srmmu_probe(page)) |
1271 | turbosparc_flush_page_cache(page); |
1272 | clear = srmmu_get_fstatus(); |
1273 | #endif |
1274 | } |
1275 | |
1276 | static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) |
1277 | { |
1278 | } |
1279 | |
1280 | static void turbosparc_flush_page_for_dma(unsigned long page) |
1281 | { |
1282 | turbosparc_flush_dcache(); |
1283 | } |
1284 | |
1285 | static void turbosparc_flush_tlb_all(void) |
1286 | { |
1287 | srmmu_flush_whole_tlb(); |
1288 | } |
1289 | |
1290 | static void turbosparc_flush_tlb_mm(struct mm_struct *mm) |
1291 | { |
1292 | FLUSH_BEGIN(mm) |
1293 | srmmu_flush_whole_tlb(); |
1294 | FLUSH_END |
1295 | } |
1296 | |
1297 | static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) |
1298 | { |
1299 | FLUSH_BEGIN(vma->vm_mm) |
1300 | srmmu_flush_whole_tlb(); |
1301 | FLUSH_END |
1302 | } |
1303 | |
1304 | static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
1305 | { |
1306 | FLUSH_BEGIN(vma->vm_mm) |
1307 | srmmu_flush_whole_tlb(); |
1308 | FLUSH_END |
1309 | } |
1310 | |
1311 | |
1312 | static void poke_turbosparc(void) |
1313 | { |
1314 | unsigned long mreg = srmmu_get_mmureg(); |
1315 | unsigned long ccreg; |
1316 | |
1317 | /* Clear any crap from the cache or else... */ |
1318 | turbosparc_flush_cache_all(); |
1319 | /* Temporarily disable I & D caches */ |
1320 | mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); |
1321 | mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */ |
1322 | srmmu_set_mmureg(mreg); |
1323 | |
1324 | ccreg = turbosparc_get_ccreg(); |
1325 | |
1326 | #ifdef TURBOSPARC_WRITEBACK |
1327 | ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */ |
1328 | ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE); |
1329 | /* Write-back D-cache, emulate VLSI |
1330 | * abortion number three, not number one */ |
1331 | #else |
1332 | /* For now let's play safe, optimize later */ |
1333 | ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE); |
1334 | /* Do DVMA snooping in Dcache, Write-thru D-cache */ |
1335 | ccreg &= ~(TURBOSPARC_uS2); |
1336 | /* Emulate VLSI abortion number three, not number one */ |
1337 | #endif |
1338 | |
1339 | switch (ccreg & 7) { |
1340 | case 0: /* No SE cache */ |
1341 | case 7: /* Test mode */ |
1342 | break; |
1343 | default: |
1344 | ccreg |= (TURBOSPARC_SCENABLE); |
1345 | } |
1346 | turbosparc_set_ccreg(ccreg); |
1347 | |
1348 | mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */ |
1349 | mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */ |
1350 | srmmu_set_mmureg(mreg); |
1351 | } |
1352 | |
1353 | static const struct sparc32_cachetlb_ops turbosparc_ops = { |
1354 | .cache_all = turbosparc_flush_cache_all, |
1355 | .cache_mm = turbosparc_flush_cache_mm, |
1356 | .cache_page = turbosparc_flush_cache_page, |
1357 | .cache_range = turbosparc_flush_cache_range, |
1358 | .tlb_all = turbosparc_flush_tlb_all, |
1359 | .tlb_mm = turbosparc_flush_tlb_mm, |
1360 | .tlb_page = turbosparc_flush_tlb_page, |
1361 | .tlb_range = turbosparc_flush_tlb_range, |
1362 | .page_to_ram = turbosparc_flush_page_to_ram, |
1363 | .sig_insns = turbosparc_flush_sig_insns, |
1364 | .page_for_dma = turbosparc_flush_page_for_dma, |
1365 | }; |
1366 | |
1367 | static void __init init_turbosparc(void) |
1368 | { |
1369 | srmmu_name = "Fujitsu TurboSparc" ; |
1370 | srmmu_modtype = TurboSparc; |
1371 | sparc32_cachetlb_ops = &turbosparc_ops; |
1372 | poke_srmmu = poke_turbosparc; |
1373 | } |
1374 | |
1375 | static void poke_tsunami(void) |
1376 | { |
1377 | unsigned long mreg = srmmu_get_mmureg(); |
1378 | |
1379 | tsunami_flush_icache(); |
1380 | tsunami_flush_dcache(); |
1381 | mreg &= ~TSUNAMI_ITD; |
1382 | mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB); |
1383 | srmmu_set_mmureg(mreg); |
1384 | } |
1385 | |
1386 | static const struct sparc32_cachetlb_ops tsunami_ops = { |
1387 | .cache_all = tsunami_flush_cache_all, |
1388 | .cache_mm = tsunami_flush_cache_mm, |
1389 | .cache_page = tsunami_flush_cache_page, |
1390 | .cache_range = tsunami_flush_cache_range, |
1391 | .tlb_all = tsunami_flush_tlb_all, |
1392 | .tlb_mm = tsunami_flush_tlb_mm, |
1393 | .tlb_page = tsunami_flush_tlb_page, |
1394 | .tlb_range = tsunami_flush_tlb_range, |
1395 | .page_to_ram = tsunami_flush_page_to_ram, |
1396 | .sig_insns = tsunami_flush_sig_insns, |
1397 | .page_for_dma = tsunami_flush_page_for_dma, |
1398 | }; |
1399 | |
1400 | static void __init init_tsunami(void) |
1401 | { |
1402 | /* |
1403 | * Tsunami's pretty sane, Sun and TI actually got it |
1404 | * somewhat right this time. Fujitsu should have |
1405 | * taken some lessons from them. |
1406 | */ |
1407 | |
1408 | srmmu_name = "TI Tsunami" ; |
1409 | srmmu_modtype = Tsunami; |
1410 | sparc32_cachetlb_ops = &tsunami_ops; |
1411 | poke_srmmu = poke_tsunami; |
1412 | |
1413 | tsunami_setup_blockops(); |
1414 | } |
1415 | |
1416 | static void poke_viking(void) |
1417 | { |
1418 | unsigned long mreg = srmmu_get_mmureg(); |
1419 | static int smp_catch; |
1420 | |
1421 | if (viking_mxcc_present) { |
1422 | unsigned long mxcc_control = mxcc_get_creg(); |
1423 | |
1424 | mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); |
1425 | mxcc_control &= ~(MXCC_CTL_RRC); |
1426 | mxcc_set_creg(mxcc_control); |
1427 | |
1428 | /* |
1429 | * We don't need memory parity checks. |
1430 | * XXX This is a mess, have to dig out later. ecd. |
1431 | viking_mxcc_turn_off_parity(&mreg, &mxcc_control); |
1432 | */ |
1433 | |
1434 | /* We do cache ptables on MXCC. */ |
1435 | mreg |= VIKING_TCENABLE; |
1436 | } else { |
1437 | unsigned long bpreg; |
1438 | |
1439 | mreg &= ~(VIKING_TCENABLE); |
1440 | if (smp_catch++) { |
1441 | /* Must disable mixed-cmd mode here for other cpu's. */ |
1442 | bpreg = viking_get_bpreg(); |
1443 | bpreg &= ~(VIKING_ACTION_MIX); |
1444 | viking_set_bpreg(bpreg); |
1445 | |
1446 | /* Just in case PROM does something funny. */ |
1447 | msi_set_sync(); |
1448 | } |
1449 | } |
1450 | |
1451 | mreg |= VIKING_SPENABLE; |
1452 | mreg |= (VIKING_ICENABLE | VIKING_DCENABLE); |
1453 | mreg |= VIKING_SBENABLE; |
1454 | mreg &= ~(VIKING_ACENABLE); |
1455 | srmmu_set_mmureg(mreg); |
1456 | } |
1457 | |
1458 | static struct sparc32_cachetlb_ops viking_ops __ro_after_init = { |
1459 | .cache_all = viking_flush_cache_all, |
1460 | .cache_mm = viking_flush_cache_mm, |
1461 | .cache_page = viking_flush_cache_page, |
1462 | .cache_range = viking_flush_cache_range, |
1463 | .tlb_all = viking_flush_tlb_all, |
1464 | .tlb_mm = viking_flush_tlb_mm, |
1465 | .tlb_page = viking_flush_tlb_page, |
1466 | .tlb_range = viking_flush_tlb_range, |
1467 | .page_to_ram = viking_flush_page_to_ram, |
1468 | .sig_insns = viking_flush_sig_insns, |
1469 | .page_for_dma = viking_flush_page_for_dma, |
1470 | }; |
1471 | |
1472 | #ifdef CONFIG_SMP |
1473 | /* On sun4d the cpu broadcasts local TLB flushes, so we can just |
1474 | * perform the local TLB flush and all the other cpus will see it. |
1475 | * But, unfortunately, there is a bug in the sun4d XBUS backplane |
1476 | * that requires that we add some synchronization to these flushes. |
1477 | * |
1478 | * The bug is that the fifo which keeps track of all the pending TLB |
1479 | * broadcasts in the system is an entry or two too small, so if we |
1480 | * have too many going at once we'll overflow that fifo and lose a TLB |
1481 | * flush resulting in corruption. |
1482 | * |
1483 | * Our workaround is to take a global spinlock around the TLB flushes, |
1484 | * which guarentees we won't ever have too many pending. It's a big |
1485 | * hammer, but a semaphore like system to make sure we only have N TLB |
1486 | * flushes going at once will require SMP locking anyways so there's |
1487 | * no real value in trying any harder than this. |
1488 | */ |
1489 | static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = { |
1490 | .cache_all = viking_flush_cache_all, |
1491 | .cache_mm = viking_flush_cache_mm, |
1492 | .cache_page = viking_flush_cache_page, |
1493 | .cache_range = viking_flush_cache_range, |
1494 | .tlb_all = sun4dsmp_flush_tlb_all, |
1495 | .tlb_mm = sun4dsmp_flush_tlb_mm, |
1496 | .tlb_page = sun4dsmp_flush_tlb_page, |
1497 | .tlb_range = sun4dsmp_flush_tlb_range, |
1498 | .page_to_ram = viking_flush_page_to_ram, |
1499 | .sig_insns = viking_flush_sig_insns, |
1500 | .page_for_dma = viking_flush_page_for_dma, |
1501 | }; |
1502 | #endif |
1503 | |
1504 | static void __init init_viking(void) |
1505 | { |
1506 | unsigned long mreg = srmmu_get_mmureg(); |
1507 | |
1508 | /* Ahhh, the viking. SRMMU VLSI abortion number two... */ |
1509 | if (mreg & VIKING_MMODE) { |
1510 | srmmu_name = "TI Viking" ; |
1511 | viking_mxcc_present = 0; |
1512 | msi_set_sync(); |
1513 | |
1514 | /* |
1515 | * We need this to make sure old viking takes no hits |
1516 | * on its cache for dma snoops to workaround the |
1517 | * "load from non-cacheable memory" interrupt bug. |
1518 | * This is only necessary because of the new way in |
1519 | * which we use the IOMMU. |
1520 | */ |
1521 | viking_ops.page_for_dma = viking_flush_page; |
1522 | #ifdef CONFIG_SMP |
1523 | viking_sun4d_smp_ops.page_for_dma = viking_flush_page; |
1524 | #endif |
1525 | flush_page_for_dma_global = 0; |
1526 | } else { |
1527 | srmmu_name = "TI Viking/MXCC" ; |
1528 | viking_mxcc_present = 1; |
1529 | srmmu_cache_pagetables = 1; |
1530 | } |
1531 | |
1532 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) |
1533 | &viking_ops; |
1534 | #ifdef CONFIG_SMP |
1535 | if (sparc_cpu_model == sun4d) |
1536 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) |
1537 | &viking_sun4d_smp_ops; |
1538 | #endif |
1539 | |
1540 | poke_srmmu = poke_viking; |
1541 | } |
1542 | |
1543 | /* Probe for the srmmu chip version. */ |
1544 | static void __init get_srmmu_type(void) |
1545 | { |
1546 | unsigned long mreg, psr; |
1547 | unsigned long mod_typ, mod_rev, psr_typ, psr_vers; |
1548 | |
1549 | srmmu_modtype = SRMMU_INVAL_MOD; |
1550 | hwbug_bitmask = 0; |
1551 | |
1552 | mreg = srmmu_get_mmureg(); psr = get_psr(); |
1553 | mod_typ = (mreg & 0xf0000000) >> 28; |
1554 | mod_rev = (mreg & 0x0f000000) >> 24; |
1555 | psr_typ = (psr >> 28) & 0xf; |
1556 | psr_vers = (psr >> 24) & 0xf; |
1557 | |
1558 | /* First, check for sparc-leon. */ |
1559 | if (sparc_cpu_model == sparc_leon) { |
1560 | init_leon(); |
1561 | return; |
1562 | } |
1563 | |
1564 | /* Second, check for HyperSparc or Cypress. */ |
1565 | if (mod_typ == 1) { |
1566 | switch (mod_rev) { |
1567 | case 7: |
1568 | /* UP or MP Hypersparc */ |
1569 | init_hypersparc(); |
1570 | break; |
1571 | case 0: |
1572 | case 2: |
1573 | case 10: |
1574 | case 11: |
1575 | case 12: |
1576 | case 13: |
1577 | case 14: |
1578 | case 15: |
1579 | default: |
1580 | prom_printf("Sparc-Linux Cypress support does not longer exit.\n" ); |
1581 | prom_halt(); |
1582 | break; |
1583 | } |
1584 | return; |
1585 | } |
1586 | |
1587 | /* Now Fujitsu TurboSparc. It might happen that it is |
1588 | * in Swift emulation mode, so we will check later... |
1589 | */ |
1590 | if (psr_typ == 0 && psr_vers == 5) { |
1591 | init_turbosparc(); |
1592 | return; |
1593 | } |
1594 | |
1595 | /* Next check for Fujitsu Swift. */ |
1596 | if (psr_typ == 0 && psr_vers == 4) { |
1597 | phandle cpunode; |
1598 | char node_str[128]; |
1599 | |
1600 | /* Look if it is not a TurboSparc emulating Swift... */ |
1601 | cpunode = prom_getchild(prom_root_node); |
1602 | while ((cpunode = prom_getsibling(cpunode)) != 0) { |
1603 | prom_getstring(cpunode, "device_type" , node_str, sizeof(node_str)); |
1604 | if (!strcmp(node_str, "cpu" )) { |
1605 | if (!prom_getintdefault(cpunode, "psr-implementation" , 1) && |
1606 | prom_getintdefault(cpunode, "psr-version" , 1) == 5) { |
1607 | init_turbosparc(); |
1608 | return; |
1609 | } |
1610 | break; |
1611 | } |
1612 | } |
1613 | |
1614 | init_swift(); |
1615 | return; |
1616 | } |
1617 | |
1618 | /* Now the Viking family of srmmu. */ |
1619 | if (psr_typ == 4 && |
1620 | ((psr_vers == 0) || |
1621 | ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) { |
1622 | init_viking(); |
1623 | return; |
1624 | } |
1625 | |
1626 | /* Finally the Tsunami. */ |
1627 | if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) { |
1628 | init_tsunami(); |
1629 | return; |
1630 | } |
1631 | |
1632 | /* Oh well */ |
1633 | srmmu_is_bad(); |
1634 | } |
1635 | |
1636 | #ifdef CONFIG_SMP |
1637 | /* Local cross-calls. */ |
1638 | static void smp_flush_page_for_dma(unsigned long page) |
1639 | { |
1640 | xc1(local_ops->page_for_dma, page); |
1641 | local_ops->page_for_dma(page); |
1642 | } |
1643 | |
1644 | static void smp_flush_cache_all(void) |
1645 | { |
1646 | xc0(local_ops->cache_all); |
1647 | local_ops->cache_all(); |
1648 | } |
1649 | |
1650 | static void smp_flush_tlb_all(void) |
1651 | { |
1652 | xc0(local_ops->tlb_all); |
1653 | local_ops->tlb_all(); |
1654 | } |
1655 | |
1656 | static void smp_flush_cache_mm(struct mm_struct *mm) |
1657 | { |
1658 | if (mm->context != NO_CONTEXT) { |
1659 | cpumask_t cpu_mask; |
1660 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1661 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1662 | if (!cpumask_empty(srcp: &cpu_mask)) |
1663 | xc1(local_ops->cache_mm, (unsigned long)mm); |
1664 | local_ops->cache_mm(mm); |
1665 | } |
1666 | } |
1667 | |
1668 | static void smp_flush_tlb_mm(struct mm_struct *mm) |
1669 | { |
1670 | if (mm->context != NO_CONTEXT) { |
1671 | cpumask_t cpu_mask; |
1672 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1673 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1674 | if (!cpumask_empty(srcp: &cpu_mask)) { |
1675 | xc1(local_ops->tlb_mm, (unsigned long)mm); |
1676 | if (atomic_read(v: &mm->mm_users) == 1 && current->active_mm == mm) |
1677 | cpumask_copy(dstp: mm_cpumask(mm), |
1678 | cpumask_of(smp_processor_id())); |
1679 | } |
1680 | local_ops->tlb_mm(mm); |
1681 | } |
1682 | } |
1683 | |
1684 | static void smp_flush_cache_range(struct vm_area_struct *vma, |
1685 | unsigned long start, |
1686 | unsigned long end) |
1687 | { |
1688 | struct mm_struct *mm = vma->vm_mm; |
1689 | |
1690 | if (mm->context != NO_CONTEXT) { |
1691 | cpumask_t cpu_mask; |
1692 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1693 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1694 | if (!cpumask_empty(srcp: &cpu_mask)) |
1695 | xc3(local_ops->cache_range, (unsigned long)vma, start, |
1696 | end); |
1697 | local_ops->cache_range(vma, start, end); |
1698 | } |
1699 | } |
1700 | |
1701 | static void smp_flush_tlb_range(struct vm_area_struct *vma, |
1702 | unsigned long start, |
1703 | unsigned long end) |
1704 | { |
1705 | struct mm_struct *mm = vma->vm_mm; |
1706 | |
1707 | if (mm->context != NO_CONTEXT) { |
1708 | cpumask_t cpu_mask; |
1709 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1710 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1711 | if (!cpumask_empty(srcp: &cpu_mask)) |
1712 | xc3(local_ops->tlb_range, (unsigned long)vma, start, |
1713 | end); |
1714 | local_ops->tlb_range(vma, start, end); |
1715 | } |
1716 | } |
1717 | |
1718 | static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) |
1719 | { |
1720 | struct mm_struct *mm = vma->vm_mm; |
1721 | |
1722 | if (mm->context != NO_CONTEXT) { |
1723 | cpumask_t cpu_mask; |
1724 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1725 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1726 | if (!cpumask_empty(srcp: &cpu_mask)) |
1727 | xc2(local_ops->cache_page, (unsigned long)vma, page); |
1728 | local_ops->cache_page(vma, page); |
1729 | } |
1730 | } |
1731 | |
1732 | static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
1733 | { |
1734 | struct mm_struct *mm = vma->vm_mm; |
1735 | |
1736 | if (mm->context != NO_CONTEXT) { |
1737 | cpumask_t cpu_mask; |
1738 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1739 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1740 | if (!cpumask_empty(srcp: &cpu_mask)) |
1741 | xc2(local_ops->tlb_page, (unsigned long)vma, page); |
1742 | local_ops->tlb_page(vma, page); |
1743 | } |
1744 | } |
1745 | |
1746 | static void smp_flush_page_to_ram(unsigned long page) |
1747 | { |
1748 | /* Current theory is that those who call this are the one's |
1749 | * who have just dirtied their cache with the pages contents |
1750 | * in kernel space, therefore we only run this on local cpu. |
1751 | * |
1752 | * XXX This experiment failed, research further... -DaveM |
1753 | */ |
1754 | #if 1 |
1755 | xc1(local_ops->page_to_ram, page); |
1756 | #endif |
1757 | local_ops->page_to_ram(page); |
1758 | } |
1759 | |
1760 | static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) |
1761 | { |
1762 | cpumask_t cpu_mask; |
1763 | cpumask_copy(dstp: &cpu_mask, srcp: mm_cpumask(mm)); |
1764 | cpumask_clear_cpu(smp_processor_id(), dstp: &cpu_mask); |
1765 | if (!cpumask_empty(srcp: &cpu_mask)) |
1766 | xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr); |
1767 | local_ops->sig_insns(mm, insn_addr); |
1768 | } |
1769 | |
1770 | static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = { |
1771 | .cache_all = smp_flush_cache_all, |
1772 | .cache_mm = smp_flush_cache_mm, |
1773 | .cache_page = smp_flush_cache_page, |
1774 | .cache_range = smp_flush_cache_range, |
1775 | .tlb_all = smp_flush_tlb_all, |
1776 | .tlb_mm = smp_flush_tlb_mm, |
1777 | .tlb_page = smp_flush_tlb_page, |
1778 | .tlb_range = smp_flush_tlb_range, |
1779 | .page_to_ram = smp_flush_page_to_ram, |
1780 | .sig_insns = smp_flush_sig_insns, |
1781 | .page_for_dma = smp_flush_page_for_dma, |
1782 | }; |
1783 | #endif |
1784 | |
1785 | /* Load up routines and constants for sun4m and sun4d mmu */ |
1786 | void __init load_mmu(void) |
1787 | { |
1788 | /* Functions */ |
1789 | get_srmmu_type(); |
1790 | |
1791 | #ifdef CONFIG_SMP |
1792 | /* El switcheroo... */ |
1793 | local_ops = sparc32_cachetlb_ops; |
1794 | |
1795 | if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) { |
1796 | smp_cachetlb_ops.tlb_all = local_ops->tlb_all; |
1797 | smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm; |
1798 | smp_cachetlb_ops.tlb_range = local_ops->tlb_range; |
1799 | smp_cachetlb_ops.tlb_page = local_ops->tlb_page; |
1800 | } |
1801 | |
1802 | if (poke_srmmu == poke_viking) { |
1803 | /* Avoid unnecessary cross calls. */ |
1804 | smp_cachetlb_ops.cache_all = local_ops->cache_all; |
1805 | smp_cachetlb_ops.cache_mm = local_ops->cache_mm; |
1806 | smp_cachetlb_ops.cache_range = local_ops->cache_range; |
1807 | smp_cachetlb_ops.cache_page = local_ops->cache_page; |
1808 | |
1809 | smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; |
1810 | smp_cachetlb_ops.sig_insns = local_ops->sig_insns; |
1811 | smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; |
1812 | } |
1813 | |
1814 | /* It really is const after this point. */ |
1815 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) |
1816 | &smp_cachetlb_ops; |
1817 | #endif |
1818 | |
1819 | if (sparc_cpu_model != sun4d) |
1820 | ld_mmu_iommu(); |
1821 | #ifdef CONFIG_SMP |
1822 | if (sparc_cpu_model == sun4d) |
1823 | sun4d_init_smp(); |
1824 | else if (sparc_cpu_model == sparc_leon) |
1825 | leon_init_smp(); |
1826 | else |
1827 | sun4m_init_smp(); |
1828 | #endif |
1829 | } |
1830 | |