1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/stddef.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/export.h>
16#include <linux/nmi.h>
17#include <linux/kvm_host.h>
18
19#include <asm/cpufeature.h>
20#include <asm/hardirq.h>
21#include <asm/intel-family.h>
22#include <asm/intel_pt.h>
23#include <asm/apic.h>
24#include <asm/cpu_device_id.h>
25
26#include "../perf_event.h"
27
28/*
29 * Intel PerfMon, used on Core and later.
30 */
31static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
32{
33 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
34 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
35 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
36 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
37 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
38 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
39 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
40 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
41};
42
43static struct event_constraint intel_core_event_constraints[] __read_mostly =
44{
45 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
46 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
47 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
48 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
49 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
50 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
51 EVENT_CONSTRAINT_END
52};
53
54static struct event_constraint intel_core2_event_constraints[] __read_mostly =
55{
56 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
57 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
58 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
59 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
60 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
61 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
62 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
63 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
64 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
65 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
66 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
67 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
68 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
69 EVENT_CONSTRAINT_END
70};
71
72static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
73{
74 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
75 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
76 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
77 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
78 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
79 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
80 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
81 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
82 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
83 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
84 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
85 EVENT_CONSTRAINT_END
86};
87
88static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
89{
90 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
91 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
92 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
93 EVENT_EXTRA_END
94};
95
96static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
97{
98 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
99 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
100 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
101 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
102 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
103 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
104 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
105 EVENT_CONSTRAINT_END
106};
107
108static struct event_constraint intel_snb_event_constraints[] __read_mostly =
109{
110 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
111 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
112 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
114 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
116 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
117 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
118 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
119 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
120 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
121 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
122
123 /*
124 * When HT is off these events can only run on the bottom 4 counters
125 * When HT is on, they are impacted by the HT bug and require EXCL access
126 */
127 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
131
132 EVENT_CONSTRAINT_END
133};
134
135static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
136{
137 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
138 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
139 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
140 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
141 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
142 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
143 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
145 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
150
151 /*
152 * When HT is off these events can only run on the bottom 4 counters
153 * When HT is on, they are impacted by the HT bug and require EXCL access
154 */
155 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
159
160 EVENT_CONSTRAINT_END
161};
162
163static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
164{
165 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
166 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
167 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
169 EVENT_EXTRA_END
170};
171
172static struct event_constraint intel_v1_event_constraints[] __read_mostly =
173{
174 EVENT_CONSTRAINT_END
175};
176
177static struct event_constraint intel_gen_event_constraints[] __read_mostly =
178{
179 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
180 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
181 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
182 EVENT_CONSTRAINT_END
183};
184
185static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
186{
187 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
188 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
189 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
190 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
191 FIXED_EVENT_CONSTRAINT(0x0500, 4),
192 FIXED_EVENT_CONSTRAINT(0x0600, 5),
193 FIXED_EVENT_CONSTRAINT(0x0700, 6),
194 FIXED_EVENT_CONSTRAINT(0x0800, 7),
195 FIXED_EVENT_CONSTRAINT(0x0900, 8),
196 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
197 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
198 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
199 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
200 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
201 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
202 FIXED_EVENT_CONSTRAINT(0x1000, 15),
203 EVENT_CONSTRAINT_END
204};
205
206static struct event_constraint intel_slm_event_constraints[] __read_mostly =
207{
208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
211 EVENT_CONSTRAINT_END
212};
213
214static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
215 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
216 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
217 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
218 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
219 EVENT_CONSTRAINT_END
220};
221
222static struct event_constraint intel_skl_event_constraints[] = {
223 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
224 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
225 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
226 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
227
228 /*
229 * when HT is off, these can only run on the bottom 4 counters
230 */
231 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
232 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
233 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
234 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
235 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
236
237 EVENT_CONSTRAINT_END
238};
239
240static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
241 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
242 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
243 EVENT_EXTRA_END
244};
245
246static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
247 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
248 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
249 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
250 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
251 EVENT_EXTRA_END
252};
253
254static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
255 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
256 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
257 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
258 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
259 EVENT_EXTRA_END
260};
261
262static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
263 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
264 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
265 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
266 /*
267 * Note the low 8 bits eventsel code is not a continuous field, containing
268 * some #GPing bits. These are masked out.
269 */
270 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
271 EVENT_EXTRA_END
272};
273
274static struct event_constraint intel_icl_event_constraints[] = {
275 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
276 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
277 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
278 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
279 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
280 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
281 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
282 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
283 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
284 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
285 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
286 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
287 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
288 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
289 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
290 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
291 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
292 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
293 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
294 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
295 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
296 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
297 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
298 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
299 EVENT_CONSTRAINT_END
300};
301
302static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
303 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
304 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
305 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
306 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
307 EVENT_EXTRA_END
308};
309
310static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
311 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
312 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
313 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
314 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
315 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
316 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
317 EVENT_EXTRA_END
318};
319
320static struct event_constraint intel_glc_event_constraints[] = {
321 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
322 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
323 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
324 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
325 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
326 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
327 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
328 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
329 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
330 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
331 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
332 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
333 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
334 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
335
336 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
337 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
338 /*
339 * Generally event codes < 0x90 are restricted to counters 0-3.
340 * The 0x2E and 0x3C are exception, which has no restriction.
341 */
342 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
343
344 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
345 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
346 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
347 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
348 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
349 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
350 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
351 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
352 /*
353 * Generally event codes >= 0x90 are likely to have no restrictions.
354 * The exception are defined as above.
355 */
356 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
357
358 EVENT_CONSTRAINT_END
359};
360
361static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
362 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
363 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
364 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
365 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
366 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
367 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
368 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
369 EVENT_EXTRA_END
370};
371
372EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
373EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
374EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
375
376static struct attribute *nhm_mem_events_attrs[] = {
377 EVENT_PTR(mem_ld_nhm),
378 NULL,
379};
380
381/*
382 * topdown events for Intel Core CPUs.
383 *
384 * The events are all in slots, which is a free slot in a 4 wide
385 * pipeline. Some events are already reported in slots, for cycle
386 * events we multiply by the pipeline width (4).
387 *
388 * With Hyper Threading on, topdown metrics are either summed or averaged
389 * between the threads of a core: (count_t0 + count_t1).
390 *
391 * For the average case the metric is always scaled to pipeline width,
392 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
393 */
394
395EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
396 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
397 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
398EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
399EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
400 "event=0xe,umask=0x1"); /* uops_issued.any */
401EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
402 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
403EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
404 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
405EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
406 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
407 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
408EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
409 "4", "2");
410
411EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
412EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
413EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
414EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
415EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
416EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
417EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
418EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
419EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
420
421static struct attribute *snb_events_attrs[] = {
422 EVENT_PTR(td_slots_issued),
423 EVENT_PTR(td_slots_retired),
424 EVENT_PTR(td_fetch_bubbles),
425 EVENT_PTR(td_total_slots),
426 EVENT_PTR(td_total_slots_scale),
427 EVENT_PTR(td_recovery_bubbles),
428 EVENT_PTR(td_recovery_bubbles_scale),
429 NULL,
430};
431
432static struct attribute *snb_mem_events_attrs[] = {
433 EVENT_PTR(mem_ld_snb),
434 EVENT_PTR(mem_st_snb),
435 NULL,
436};
437
438static struct event_constraint intel_hsw_event_constraints[] = {
439 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
440 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
441 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
442 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
443 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
444 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
445 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
446 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
447 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
448 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
449 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
450 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
451
452 /*
453 * When HT is off these events can only run on the bottom 4 counters
454 * When HT is on, they are impacted by the HT bug and require EXCL access
455 */
456 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
457 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
458 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
459 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
460
461 EVENT_CONSTRAINT_END
462};
463
464static struct event_constraint intel_bdw_event_constraints[] = {
465 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
466 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
467 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
468 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
469 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
470 /*
471 * when HT is off, these can only run on the bottom 4 counters
472 */
473 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
474 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
475 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
476 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
477 EVENT_CONSTRAINT_END
478};
479
480static u64 intel_pmu_event_map(int hw_event)
481{
482 return intel_perfmon_event_map[hw_event];
483}
484
485static __initconst const u64 glc_hw_cache_event_ids
486 [PERF_COUNT_HW_CACHE_MAX]
487 [PERF_COUNT_HW_CACHE_OP_MAX]
488 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
489{
490 [ C(L1D ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x81d0,
493 [ C(RESULT_MISS) ] = 0xe124,
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = 0x82d0,
497 },
498 },
499 [ C(L1I ) ] = {
500 [ C(OP_READ) ] = {
501 [ C(RESULT_MISS) ] = 0xe424,
502 },
503 [ C(OP_WRITE) ] = {
504 [ C(RESULT_ACCESS) ] = -1,
505 [ C(RESULT_MISS) ] = -1,
506 },
507 },
508 [ C(LL ) ] = {
509 [ C(OP_READ) ] = {
510 [ C(RESULT_ACCESS) ] = 0x12a,
511 [ C(RESULT_MISS) ] = 0x12a,
512 },
513 [ C(OP_WRITE) ] = {
514 [ C(RESULT_ACCESS) ] = 0x12a,
515 [ C(RESULT_MISS) ] = 0x12a,
516 },
517 },
518 [ C(DTLB) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = 0x81d0,
521 [ C(RESULT_MISS) ] = 0xe12,
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = 0x82d0,
525 [ C(RESULT_MISS) ] = 0xe13,
526 },
527 },
528 [ C(ITLB) ] = {
529 [ C(OP_READ) ] = {
530 [ C(RESULT_ACCESS) ] = -1,
531 [ C(RESULT_MISS) ] = 0xe11,
532 },
533 [ C(OP_WRITE) ] = {
534 [ C(RESULT_ACCESS) ] = -1,
535 [ C(RESULT_MISS) ] = -1,
536 },
537 [ C(OP_PREFETCH) ] = {
538 [ C(RESULT_ACCESS) ] = -1,
539 [ C(RESULT_MISS) ] = -1,
540 },
541 },
542 [ C(BPU ) ] = {
543 [ C(OP_READ) ] = {
544 [ C(RESULT_ACCESS) ] = 0x4c4,
545 [ C(RESULT_MISS) ] = 0x4c5,
546 },
547 [ C(OP_WRITE) ] = {
548 [ C(RESULT_ACCESS) ] = -1,
549 [ C(RESULT_MISS) ] = -1,
550 },
551 [ C(OP_PREFETCH) ] = {
552 [ C(RESULT_ACCESS) ] = -1,
553 [ C(RESULT_MISS) ] = -1,
554 },
555 },
556 [ C(NODE) ] = {
557 [ C(OP_READ) ] = {
558 [ C(RESULT_ACCESS) ] = 0x12a,
559 [ C(RESULT_MISS) ] = 0x12a,
560 },
561 },
562};
563
564static __initconst const u64 glc_hw_cache_extra_regs
565 [PERF_COUNT_HW_CACHE_MAX]
566 [PERF_COUNT_HW_CACHE_OP_MAX]
567 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
568{
569 [ C(LL ) ] = {
570 [ C(OP_READ) ] = {
571 [ C(RESULT_ACCESS) ] = 0x10001,
572 [ C(RESULT_MISS) ] = 0x3fbfc00001,
573 },
574 [ C(OP_WRITE) ] = {
575 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
576 [ C(RESULT_MISS) ] = 0x3f3fc00002,
577 },
578 },
579 [ C(NODE) ] = {
580 [ C(OP_READ) ] = {
581 [ C(RESULT_ACCESS) ] = 0x10c000001,
582 [ C(RESULT_MISS) ] = 0x3fb3000001,
583 },
584 },
585};
586
587/*
588 * Notes on the events:
589 * - data reads do not include code reads (comparable to earlier tables)
590 * - data counts include speculative execution (except L1 write, dtlb, bpu)
591 * - remote node access includes remote memory, remote cache, remote mmio.
592 * - prefetches are not included in the counts.
593 * - icache miss does not include decoded icache
594 */
595
596#define SKL_DEMAND_DATA_RD BIT_ULL(0)
597#define SKL_DEMAND_RFO BIT_ULL(1)
598#define SKL_ANY_RESPONSE BIT_ULL(16)
599#define SKL_SUPPLIER_NONE BIT_ULL(17)
600#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
601#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
602#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
603#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
604#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
605 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
606 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
607 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
608#define SKL_SPL_HIT BIT_ULL(30)
609#define SKL_SNOOP_NONE BIT_ULL(31)
610#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
611#define SKL_SNOOP_MISS BIT_ULL(33)
612#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
613#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
614#define SKL_SNOOP_HITM BIT_ULL(36)
615#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
616#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
617 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
618 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
619 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
620#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
621#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
622 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
623 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
624 SKL_SNOOP_HITM|SKL_SPL_HIT)
625#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
626#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
627#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
628 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
629 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
630
631static __initconst const u64 skl_hw_cache_event_ids
632 [PERF_COUNT_HW_CACHE_MAX]
633 [PERF_COUNT_HW_CACHE_OP_MAX]
634 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
635{
636 [ C(L1D ) ] = {
637 [ C(OP_READ) ] = {
638 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
639 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
640 },
641 [ C(OP_WRITE) ] = {
642 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
643 [ C(RESULT_MISS) ] = 0x0,
644 },
645 [ C(OP_PREFETCH) ] = {
646 [ C(RESULT_ACCESS) ] = 0x0,
647 [ C(RESULT_MISS) ] = 0x0,
648 },
649 },
650 [ C(L1I ) ] = {
651 [ C(OP_READ) ] = {
652 [ C(RESULT_ACCESS) ] = 0x0,
653 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
654 },
655 [ C(OP_WRITE) ] = {
656 [ C(RESULT_ACCESS) ] = -1,
657 [ C(RESULT_MISS) ] = -1,
658 },
659 [ C(OP_PREFETCH) ] = {
660 [ C(RESULT_ACCESS) ] = 0x0,
661 [ C(RESULT_MISS) ] = 0x0,
662 },
663 },
664 [ C(LL ) ] = {
665 [ C(OP_READ) ] = {
666 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
667 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
668 },
669 [ C(OP_WRITE) ] = {
670 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
671 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
672 },
673 [ C(OP_PREFETCH) ] = {
674 [ C(RESULT_ACCESS) ] = 0x0,
675 [ C(RESULT_MISS) ] = 0x0,
676 },
677 },
678 [ C(DTLB) ] = {
679 [ C(OP_READ) ] = {
680 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
681 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
682 },
683 [ C(OP_WRITE) ] = {
684 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
685 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
686 },
687 [ C(OP_PREFETCH) ] = {
688 [ C(RESULT_ACCESS) ] = 0x0,
689 [ C(RESULT_MISS) ] = 0x0,
690 },
691 },
692 [ C(ITLB) ] = {
693 [ C(OP_READ) ] = {
694 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
695 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
696 },
697 [ C(OP_WRITE) ] = {
698 [ C(RESULT_ACCESS) ] = -1,
699 [ C(RESULT_MISS) ] = -1,
700 },
701 [ C(OP_PREFETCH) ] = {
702 [ C(RESULT_ACCESS) ] = -1,
703 [ C(RESULT_MISS) ] = -1,
704 },
705 },
706 [ C(BPU ) ] = {
707 [ C(OP_READ) ] = {
708 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
709 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
710 },
711 [ C(OP_WRITE) ] = {
712 [ C(RESULT_ACCESS) ] = -1,
713 [ C(RESULT_MISS) ] = -1,
714 },
715 [ C(OP_PREFETCH) ] = {
716 [ C(RESULT_ACCESS) ] = -1,
717 [ C(RESULT_MISS) ] = -1,
718 },
719 },
720 [ C(NODE) ] = {
721 [ C(OP_READ) ] = {
722 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
723 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
724 },
725 [ C(OP_WRITE) ] = {
726 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
727 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
728 },
729 [ C(OP_PREFETCH) ] = {
730 [ C(RESULT_ACCESS) ] = 0x0,
731 [ C(RESULT_MISS) ] = 0x0,
732 },
733 },
734};
735
736static __initconst const u64 skl_hw_cache_extra_regs
737 [PERF_COUNT_HW_CACHE_MAX]
738 [PERF_COUNT_HW_CACHE_OP_MAX]
739 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
740{
741 [ C(LL ) ] = {
742 [ C(OP_READ) ] = {
743 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
744 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
745 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
746 SKL_L3_MISS|SKL_ANY_SNOOP|
747 SKL_SUPPLIER_NONE,
748 },
749 [ C(OP_WRITE) ] = {
750 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
751 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
752 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
753 SKL_L3_MISS|SKL_ANY_SNOOP|
754 SKL_SUPPLIER_NONE,
755 },
756 [ C(OP_PREFETCH) ] = {
757 [ C(RESULT_ACCESS) ] = 0x0,
758 [ C(RESULT_MISS) ] = 0x0,
759 },
760 },
761 [ C(NODE) ] = {
762 [ C(OP_READ) ] = {
763 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
764 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
765 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
766 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
767 },
768 [ C(OP_WRITE) ] = {
769 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
770 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
771 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
772 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
773 },
774 [ C(OP_PREFETCH) ] = {
775 [ C(RESULT_ACCESS) ] = 0x0,
776 [ C(RESULT_MISS) ] = 0x0,
777 },
778 },
779};
780
781#define SNB_DMND_DATA_RD (1ULL << 0)
782#define SNB_DMND_RFO (1ULL << 1)
783#define SNB_DMND_IFETCH (1ULL << 2)
784#define SNB_DMND_WB (1ULL << 3)
785#define SNB_PF_DATA_RD (1ULL << 4)
786#define SNB_PF_RFO (1ULL << 5)
787#define SNB_PF_IFETCH (1ULL << 6)
788#define SNB_LLC_DATA_RD (1ULL << 7)
789#define SNB_LLC_RFO (1ULL << 8)
790#define SNB_LLC_IFETCH (1ULL << 9)
791#define SNB_BUS_LOCKS (1ULL << 10)
792#define SNB_STRM_ST (1ULL << 11)
793#define SNB_OTHER (1ULL << 15)
794#define SNB_RESP_ANY (1ULL << 16)
795#define SNB_NO_SUPP (1ULL << 17)
796#define SNB_LLC_HITM (1ULL << 18)
797#define SNB_LLC_HITE (1ULL << 19)
798#define SNB_LLC_HITS (1ULL << 20)
799#define SNB_LLC_HITF (1ULL << 21)
800#define SNB_LOCAL (1ULL << 22)
801#define SNB_REMOTE (0xffULL << 23)
802#define SNB_SNP_NONE (1ULL << 31)
803#define SNB_SNP_NOT_NEEDED (1ULL << 32)
804#define SNB_SNP_MISS (1ULL << 33)
805#define SNB_NO_FWD (1ULL << 34)
806#define SNB_SNP_FWD (1ULL << 35)
807#define SNB_HITM (1ULL << 36)
808#define SNB_NON_DRAM (1ULL << 37)
809
810#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
811#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
812#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
813
814#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
815 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
816 SNB_HITM)
817
818#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
819#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
820
821#define SNB_L3_ACCESS SNB_RESP_ANY
822#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
823
824static __initconst const u64 snb_hw_cache_extra_regs
825 [PERF_COUNT_HW_CACHE_MAX]
826 [PERF_COUNT_HW_CACHE_OP_MAX]
827 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
828{
829 [ C(LL ) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
832 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
836 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
840 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
841 },
842 },
843 [ C(NODE) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
846 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
850 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
854 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
855 },
856 },
857};
858
859static __initconst const u64 snb_hw_cache_event_ids
860 [PERF_COUNT_HW_CACHE_MAX]
861 [PERF_COUNT_HW_CACHE_OP_MAX]
862 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
863{
864 [ C(L1D) ] = {
865 [ C(OP_READ) ] = {
866 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
867 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
868 },
869 [ C(OP_WRITE) ] = {
870 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
871 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
872 },
873 [ C(OP_PREFETCH) ] = {
874 [ C(RESULT_ACCESS) ] = 0x0,
875 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
876 },
877 },
878 [ C(L1I ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = 0x0,
881 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
882 },
883 [ C(OP_WRITE) ] = {
884 [ C(RESULT_ACCESS) ] = -1,
885 [ C(RESULT_MISS) ] = -1,
886 },
887 [ C(OP_PREFETCH) ] = {
888 [ C(RESULT_ACCESS) ] = 0x0,
889 [ C(RESULT_MISS) ] = 0x0,
890 },
891 },
892 [ C(LL ) ] = {
893 [ C(OP_READ) ] = {
894 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
895 [ C(RESULT_ACCESS) ] = 0x01b7,
896 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
897 [ C(RESULT_MISS) ] = 0x01b7,
898 },
899 [ C(OP_WRITE) ] = {
900 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
901 [ C(RESULT_ACCESS) ] = 0x01b7,
902 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
903 [ C(RESULT_MISS) ] = 0x01b7,
904 },
905 [ C(OP_PREFETCH) ] = {
906 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
907 [ C(RESULT_ACCESS) ] = 0x01b7,
908 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
909 [ C(RESULT_MISS) ] = 0x01b7,
910 },
911 },
912 [ C(DTLB) ] = {
913 [ C(OP_READ) ] = {
914 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
915 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
916 },
917 [ C(OP_WRITE) ] = {
918 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
919 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
920 },
921 [ C(OP_PREFETCH) ] = {
922 [ C(RESULT_ACCESS) ] = 0x0,
923 [ C(RESULT_MISS) ] = 0x0,
924 },
925 },
926 [ C(ITLB) ] = {
927 [ C(OP_READ) ] = {
928 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
929 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = -1,
933 [ C(RESULT_MISS) ] = -1,
934 },
935 [ C(OP_PREFETCH) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 },
940 [ C(BPU ) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
943 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = -1,
951 [ C(RESULT_MISS) ] = -1,
952 },
953 },
954 [ C(NODE) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957 [ C(RESULT_MISS) ] = 0x01b7,
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = 0x01b7,
961 [ C(RESULT_MISS) ] = 0x01b7,
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0x01b7,
965 [ C(RESULT_MISS) ] = 0x01b7,
966 },
967 },
968
969};
970
971/*
972 * Notes on the events:
973 * - data reads do not include code reads (comparable to earlier tables)
974 * - data counts include speculative execution (except L1 write, dtlb, bpu)
975 * - remote node access includes remote memory, remote cache, remote mmio.
976 * - prefetches are not included in the counts because they are not
977 * reliably counted.
978 */
979
980#define HSW_DEMAND_DATA_RD BIT_ULL(0)
981#define HSW_DEMAND_RFO BIT_ULL(1)
982#define HSW_ANY_RESPONSE BIT_ULL(16)
983#define HSW_SUPPLIER_NONE BIT_ULL(17)
984#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
985#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
986#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
987#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
988#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
989 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
990 HSW_L3_MISS_REMOTE_HOP2P)
991#define HSW_SNOOP_NONE BIT_ULL(31)
992#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
993#define HSW_SNOOP_MISS BIT_ULL(33)
994#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
995#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
996#define HSW_SNOOP_HITM BIT_ULL(36)
997#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
998#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
999 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1000 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1001 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1002#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1003#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1004#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1005#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1006 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1007#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1008
1009#define BDW_L3_MISS_LOCAL BIT(26)
1010#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1011 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1012 HSW_L3_MISS_REMOTE_HOP2P)
1013
1014
1015static __initconst const u64 hsw_hw_cache_event_ids
1016 [PERF_COUNT_HW_CACHE_MAX]
1017 [PERF_COUNT_HW_CACHE_OP_MAX]
1018 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1019{
1020 [ C(L1D ) ] = {
1021 [ C(OP_READ) ] = {
1022 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1023 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1024 },
1025 [ C(OP_WRITE) ] = {
1026 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1027 [ C(RESULT_MISS) ] = 0x0,
1028 },
1029 [ C(OP_PREFETCH) ] = {
1030 [ C(RESULT_ACCESS) ] = 0x0,
1031 [ C(RESULT_MISS) ] = 0x0,
1032 },
1033 },
1034 [ C(L1I ) ] = {
1035 [ C(OP_READ) ] = {
1036 [ C(RESULT_ACCESS) ] = 0x0,
1037 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1038 },
1039 [ C(OP_WRITE) ] = {
1040 [ C(RESULT_ACCESS) ] = -1,
1041 [ C(RESULT_MISS) ] = -1,
1042 },
1043 [ C(OP_PREFETCH) ] = {
1044 [ C(RESULT_ACCESS) ] = 0x0,
1045 [ C(RESULT_MISS) ] = 0x0,
1046 },
1047 },
1048 [ C(LL ) ] = {
1049 [ C(OP_READ) ] = {
1050 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1051 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1052 },
1053 [ C(OP_WRITE) ] = {
1054 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1055 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1056 },
1057 [ C(OP_PREFETCH) ] = {
1058 [ C(RESULT_ACCESS) ] = 0x0,
1059 [ C(RESULT_MISS) ] = 0x0,
1060 },
1061 },
1062 [ C(DTLB) ] = {
1063 [ C(OP_READ) ] = {
1064 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1065 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1066 },
1067 [ C(OP_WRITE) ] = {
1068 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1069 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1070 },
1071 [ C(OP_PREFETCH) ] = {
1072 [ C(RESULT_ACCESS) ] = 0x0,
1073 [ C(RESULT_MISS) ] = 0x0,
1074 },
1075 },
1076 [ C(ITLB) ] = {
1077 [ C(OP_READ) ] = {
1078 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1079 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1080 },
1081 [ C(OP_WRITE) ] = {
1082 [ C(RESULT_ACCESS) ] = -1,
1083 [ C(RESULT_MISS) ] = -1,
1084 },
1085 [ C(OP_PREFETCH) ] = {
1086 [ C(RESULT_ACCESS) ] = -1,
1087 [ C(RESULT_MISS) ] = -1,
1088 },
1089 },
1090 [ C(BPU ) ] = {
1091 [ C(OP_READ) ] = {
1092 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1093 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1094 },
1095 [ C(OP_WRITE) ] = {
1096 [ C(RESULT_ACCESS) ] = -1,
1097 [ C(RESULT_MISS) ] = -1,
1098 },
1099 [ C(OP_PREFETCH) ] = {
1100 [ C(RESULT_ACCESS) ] = -1,
1101 [ C(RESULT_MISS) ] = -1,
1102 },
1103 },
1104 [ C(NODE) ] = {
1105 [ C(OP_READ) ] = {
1106 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1107 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1108 },
1109 [ C(OP_WRITE) ] = {
1110 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1111 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1112 },
1113 [ C(OP_PREFETCH) ] = {
1114 [ C(RESULT_ACCESS) ] = 0x0,
1115 [ C(RESULT_MISS) ] = 0x0,
1116 },
1117 },
1118};
1119
1120static __initconst const u64 hsw_hw_cache_extra_regs
1121 [PERF_COUNT_HW_CACHE_MAX]
1122 [PERF_COUNT_HW_CACHE_OP_MAX]
1123 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1124{
1125 [ C(LL ) ] = {
1126 [ C(OP_READ) ] = {
1127 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1128 HSW_LLC_ACCESS,
1129 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1130 HSW_L3_MISS|HSW_ANY_SNOOP,
1131 },
1132 [ C(OP_WRITE) ] = {
1133 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1134 HSW_LLC_ACCESS,
1135 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1136 HSW_L3_MISS|HSW_ANY_SNOOP,
1137 },
1138 [ C(OP_PREFETCH) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x0,
1140 [ C(RESULT_MISS) ] = 0x0,
1141 },
1142 },
1143 [ C(NODE) ] = {
1144 [ C(OP_READ) ] = {
1145 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1146 HSW_L3_MISS_LOCAL_DRAM|
1147 HSW_SNOOP_DRAM,
1148 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1149 HSW_L3_MISS_REMOTE|
1150 HSW_SNOOP_DRAM,
1151 },
1152 [ C(OP_WRITE) ] = {
1153 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1154 HSW_L3_MISS_LOCAL_DRAM|
1155 HSW_SNOOP_DRAM,
1156 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1157 HSW_L3_MISS_REMOTE|
1158 HSW_SNOOP_DRAM,
1159 },
1160 [ C(OP_PREFETCH) ] = {
1161 [ C(RESULT_ACCESS) ] = 0x0,
1162 [ C(RESULT_MISS) ] = 0x0,
1163 },
1164 },
1165};
1166
1167static __initconst const u64 westmere_hw_cache_event_ids
1168 [PERF_COUNT_HW_CACHE_MAX]
1169 [PERF_COUNT_HW_CACHE_OP_MAX]
1170 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1171{
1172 [ C(L1D) ] = {
1173 [ C(OP_READ) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1175 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1176 },
1177 [ C(OP_WRITE) ] = {
1178 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1179 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1180 },
1181 [ C(OP_PREFETCH) ] = {
1182 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1183 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1184 },
1185 },
1186 [ C(L1I ) ] = {
1187 [ C(OP_READ) ] = {
1188 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1189 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1190 },
1191 [ C(OP_WRITE) ] = {
1192 [ C(RESULT_ACCESS) ] = -1,
1193 [ C(RESULT_MISS) ] = -1,
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 [ C(RESULT_ACCESS) ] = 0x0,
1197 [ C(RESULT_MISS) ] = 0x0,
1198 },
1199 },
1200 [ C(LL ) ] = {
1201 [ C(OP_READ) ] = {
1202 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1203 [ C(RESULT_ACCESS) ] = 0x01b7,
1204 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 /*
1208 * Use RFO, not WRITEBACK, because a write miss would typically occur
1209 * on RFO.
1210 */
1211 [ C(OP_WRITE) ] = {
1212 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1213 [ C(RESULT_ACCESS) ] = 0x01b7,
1214 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1215 [ C(RESULT_MISS) ] = 0x01b7,
1216 },
1217 [ C(OP_PREFETCH) ] = {
1218 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1219 [ C(RESULT_ACCESS) ] = 0x01b7,
1220 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1221 [ C(RESULT_MISS) ] = 0x01b7,
1222 },
1223 },
1224 [ C(DTLB) ] = {
1225 [ C(OP_READ) ] = {
1226 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1227 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1228 },
1229 [ C(OP_WRITE) ] = {
1230 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1231 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1232 },
1233 [ C(OP_PREFETCH) ] = {
1234 [ C(RESULT_ACCESS) ] = 0x0,
1235 [ C(RESULT_MISS) ] = 0x0,
1236 },
1237 },
1238 [ C(ITLB) ] = {
1239 [ C(OP_READ) ] = {
1240 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1241 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1242 },
1243 [ C(OP_WRITE) ] = {
1244 [ C(RESULT_ACCESS) ] = -1,
1245 [ C(RESULT_MISS) ] = -1,
1246 },
1247 [ C(OP_PREFETCH) ] = {
1248 [ C(RESULT_ACCESS) ] = -1,
1249 [ C(RESULT_MISS) ] = -1,
1250 },
1251 },
1252 [ C(BPU ) ] = {
1253 [ C(OP_READ) ] = {
1254 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1255 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1256 },
1257 [ C(OP_WRITE) ] = {
1258 [ C(RESULT_ACCESS) ] = -1,
1259 [ C(RESULT_MISS) ] = -1,
1260 },
1261 [ C(OP_PREFETCH) ] = {
1262 [ C(RESULT_ACCESS) ] = -1,
1263 [ C(RESULT_MISS) ] = -1,
1264 },
1265 },
1266 [ C(NODE) ] = {
1267 [ C(OP_READ) ] = {
1268 [ C(RESULT_ACCESS) ] = 0x01b7,
1269 [ C(RESULT_MISS) ] = 0x01b7,
1270 },
1271 [ C(OP_WRITE) ] = {
1272 [ C(RESULT_ACCESS) ] = 0x01b7,
1273 [ C(RESULT_MISS) ] = 0x01b7,
1274 },
1275 [ C(OP_PREFETCH) ] = {
1276 [ C(RESULT_ACCESS) ] = 0x01b7,
1277 [ C(RESULT_MISS) ] = 0x01b7,
1278 },
1279 },
1280};
1281
1282/*
1283 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1284 * See IA32 SDM Vol 3B 30.6.1.3
1285 */
1286
1287#define NHM_DMND_DATA_RD (1 << 0)
1288#define NHM_DMND_RFO (1 << 1)
1289#define NHM_DMND_IFETCH (1 << 2)
1290#define NHM_DMND_WB (1 << 3)
1291#define NHM_PF_DATA_RD (1 << 4)
1292#define NHM_PF_DATA_RFO (1 << 5)
1293#define NHM_PF_IFETCH (1 << 6)
1294#define NHM_OFFCORE_OTHER (1 << 7)
1295#define NHM_UNCORE_HIT (1 << 8)
1296#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1297#define NHM_OTHER_CORE_HITM (1 << 10)
1298 /* reserved */
1299#define NHM_REMOTE_CACHE_FWD (1 << 12)
1300#define NHM_REMOTE_DRAM (1 << 13)
1301#define NHM_LOCAL_DRAM (1 << 14)
1302#define NHM_NON_DRAM (1 << 15)
1303
1304#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1305#define NHM_REMOTE (NHM_REMOTE_DRAM)
1306
1307#define NHM_DMND_READ (NHM_DMND_DATA_RD)
1308#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1309#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1310
1311#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1312#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1313#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1314
1315static __initconst const u64 nehalem_hw_cache_extra_regs
1316 [PERF_COUNT_HW_CACHE_MAX]
1317 [PERF_COUNT_HW_CACHE_OP_MAX]
1318 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1319{
1320 [ C(LL ) ] = {
1321 [ C(OP_READ) ] = {
1322 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1323 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1324 },
1325 [ C(OP_WRITE) ] = {
1326 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1327 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1328 },
1329 [ C(OP_PREFETCH) ] = {
1330 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1331 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1332 },
1333 },
1334 [ C(NODE) ] = {
1335 [ C(OP_READ) ] = {
1336 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1337 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1338 },
1339 [ C(OP_WRITE) ] = {
1340 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1341 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1342 },
1343 [ C(OP_PREFETCH) ] = {
1344 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1345 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1346 },
1347 },
1348};
1349
1350static __initconst const u64 nehalem_hw_cache_event_ids
1351 [PERF_COUNT_HW_CACHE_MAX]
1352 [PERF_COUNT_HW_CACHE_OP_MAX]
1353 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1354{
1355 [ C(L1D) ] = {
1356 [ C(OP_READ) ] = {
1357 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1358 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1359 },
1360 [ C(OP_WRITE) ] = {
1361 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1362 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1363 },
1364 [ C(OP_PREFETCH) ] = {
1365 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1366 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1367 },
1368 },
1369 [ C(L1I ) ] = {
1370 [ C(OP_READ) ] = {
1371 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1372 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1373 },
1374 [ C(OP_WRITE) ] = {
1375 [ C(RESULT_ACCESS) ] = -1,
1376 [ C(RESULT_MISS) ] = -1,
1377 },
1378 [ C(OP_PREFETCH) ] = {
1379 [ C(RESULT_ACCESS) ] = 0x0,
1380 [ C(RESULT_MISS) ] = 0x0,
1381 },
1382 },
1383 [ C(LL ) ] = {
1384 [ C(OP_READ) ] = {
1385 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1386 [ C(RESULT_ACCESS) ] = 0x01b7,
1387 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1388 [ C(RESULT_MISS) ] = 0x01b7,
1389 },
1390 /*
1391 * Use RFO, not WRITEBACK, because a write miss would typically occur
1392 * on RFO.
1393 */
1394 [ C(OP_WRITE) ] = {
1395 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1396 [ C(RESULT_ACCESS) ] = 0x01b7,
1397 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1398 [ C(RESULT_MISS) ] = 0x01b7,
1399 },
1400 [ C(OP_PREFETCH) ] = {
1401 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1402 [ C(RESULT_ACCESS) ] = 0x01b7,
1403 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1404 [ C(RESULT_MISS) ] = 0x01b7,
1405 },
1406 },
1407 [ C(DTLB) ] = {
1408 [ C(OP_READ) ] = {
1409 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1410 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1411 },
1412 [ C(OP_WRITE) ] = {
1413 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1414 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1415 },
1416 [ C(OP_PREFETCH) ] = {
1417 [ C(RESULT_ACCESS) ] = 0x0,
1418 [ C(RESULT_MISS) ] = 0x0,
1419 },
1420 },
1421 [ C(ITLB) ] = {
1422 [ C(OP_READ) ] = {
1423 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1424 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1425 },
1426 [ C(OP_WRITE) ] = {
1427 [ C(RESULT_ACCESS) ] = -1,
1428 [ C(RESULT_MISS) ] = -1,
1429 },
1430 [ C(OP_PREFETCH) ] = {
1431 [ C(RESULT_ACCESS) ] = -1,
1432 [ C(RESULT_MISS) ] = -1,
1433 },
1434 },
1435 [ C(BPU ) ] = {
1436 [ C(OP_READ) ] = {
1437 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1438 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1439 },
1440 [ C(OP_WRITE) ] = {
1441 [ C(RESULT_ACCESS) ] = -1,
1442 [ C(RESULT_MISS) ] = -1,
1443 },
1444 [ C(OP_PREFETCH) ] = {
1445 [ C(RESULT_ACCESS) ] = -1,
1446 [ C(RESULT_MISS) ] = -1,
1447 },
1448 },
1449 [ C(NODE) ] = {
1450 [ C(OP_READ) ] = {
1451 [ C(RESULT_ACCESS) ] = 0x01b7,
1452 [ C(RESULT_MISS) ] = 0x01b7,
1453 },
1454 [ C(OP_WRITE) ] = {
1455 [ C(RESULT_ACCESS) ] = 0x01b7,
1456 [ C(RESULT_MISS) ] = 0x01b7,
1457 },
1458 [ C(OP_PREFETCH) ] = {
1459 [ C(RESULT_ACCESS) ] = 0x01b7,
1460 [ C(RESULT_MISS) ] = 0x01b7,
1461 },
1462 },
1463};
1464
1465static __initconst const u64 core2_hw_cache_event_ids
1466 [PERF_COUNT_HW_CACHE_MAX]
1467 [PERF_COUNT_HW_CACHE_OP_MAX]
1468 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1469{
1470 [ C(L1D) ] = {
1471 [ C(OP_READ) ] = {
1472 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1473 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1474 },
1475 [ C(OP_WRITE) ] = {
1476 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1477 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1478 },
1479 [ C(OP_PREFETCH) ] = {
1480 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1481 [ C(RESULT_MISS) ] = 0,
1482 },
1483 },
1484 [ C(L1I ) ] = {
1485 [ C(OP_READ) ] = {
1486 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1487 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1488 },
1489 [ C(OP_WRITE) ] = {
1490 [ C(RESULT_ACCESS) ] = -1,
1491 [ C(RESULT_MISS) ] = -1,
1492 },
1493 [ C(OP_PREFETCH) ] = {
1494 [ C(RESULT_ACCESS) ] = 0,
1495 [ C(RESULT_MISS) ] = 0,
1496 },
1497 },
1498 [ C(LL ) ] = {
1499 [ C(OP_READ) ] = {
1500 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1501 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1502 },
1503 [ C(OP_WRITE) ] = {
1504 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1505 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1506 },
1507 [ C(OP_PREFETCH) ] = {
1508 [ C(RESULT_ACCESS) ] = 0,
1509 [ C(RESULT_MISS) ] = 0,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1515 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1519 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1529 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554};
1555
1556static __initconst const u64 atom_hw_cache_event_ids
1557 [PERF_COUNT_HW_CACHE_MAX]
1558 [PERF_COUNT_HW_CACHE_OP_MAX]
1559 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1560{
1561 [ C(L1D) ] = {
1562 [ C(OP_READ) ] = {
1563 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1564 [ C(RESULT_MISS) ] = 0,
1565 },
1566 [ C(OP_WRITE) ] = {
1567 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1568 [ C(RESULT_MISS) ] = 0,
1569 },
1570 [ C(OP_PREFETCH) ] = {
1571 [ C(RESULT_ACCESS) ] = 0x0,
1572 [ C(RESULT_MISS) ] = 0,
1573 },
1574 },
1575 [ C(L1I ) ] = {
1576 [ C(OP_READ) ] = {
1577 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1578 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1579 },
1580 [ C(OP_WRITE) ] = {
1581 [ C(RESULT_ACCESS) ] = -1,
1582 [ C(RESULT_MISS) ] = -1,
1583 },
1584 [ C(OP_PREFETCH) ] = {
1585 [ C(RESULT_ACCESS) ] = 0,
1586 [ C(RESULT_MISS) ] = 0,
1587 },
1588 },
1589 [ C(LL ) ] = {
1590 [ C(OP_READ) ] = {
1591 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1592 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1593 },
1594 [ C(OP_WRITE) ] = {
1595 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1596 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1597 },
1598 [ C(OP_PREFETCH) ] = {
1599 [ C(RESULT_ACCESS) ] = 0,
1600 [ C(RESULT_MISS) ] = 0,
1601 },
1602 },
1603 [ C(DTLB) ] = {
1604 [ C(OP_READ) ] = {
1605 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1606 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1607 },
1608 [ C(OP_WRITE) ] = {
1609 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1610 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1611 },
1612 [ C(OP_PREFETCH) ] = {
1613 [ C(RESULT_ACCESS) ] = 0,
1614 [ C(RESULT_MISS) ] = 0,
1615 },
1616 },
1617 [ C(ITLB) ] = {
1618 [ C(OP_READ) ] = {
1619 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1620 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1621 },
1622 [ C(OP_WRITE) ] = {
1623 [ C(RESULT_ACCESS) ] = -1,
1624 [ C(RESULT_MISS) ] = -1,
1625 },
1626 [ C(OP_PREFETCH) ] = {
1627 [ C(RESULT_ACCESS) ] = -1,
1628 [ C(RESULT_MISS) ] = -1,
1629 },
1630 },
1631 [ C(BPU ) ] = {
1632 [ C(OP_READ) ] = {
1633 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1634 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1635 },
1636 [ C(OP_WRITE) ] = {
1637 [ C(RESULT_ACCESS) ] = -1,
1638 [ C(RESULT_MISS) ] = -1,
1639 },
1640 [ C(OP_PREFETCH) ] = {
1641 [ C(RESULT_ACCESS) ] = -1,
1642 [ C(RESULT_MISS) ] = -1,
1643 },
1644 },
1645};
1646
1647EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1648EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1649/* no_alloc_cycles.not_delivered */
1650EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1651 "event=0xca,umask=0x50");
1652EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1653/* uops_retired.all */
1654EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1655 "event=0xc2,umask=0x10");
1656/* uops_retired.all */
1657EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1658 "event=0xc2,umask=0x10");
1659
1660static struct attribute *slm_events_attrs[] = {
1661 EVENT_PTR(td_total_slots_slm),
1662 EVENT_PTR(td_total_slots_scale_slm),
1663 EVENT_PTR(td_fetch_bubbles_slm),
1664 EVENT_PTR(td_fetch_bubbles_scale_slm),
1665 EVENT_PTR(td_slots_issued_slm),
1666 EVENT_PTR(td_slots_retired_slm),
1667 NULL
1668};
1669
1670static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1671{
1672 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1673 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1674 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1675 EVENT_EXTRA_END
1676};
1677
1678#define SLM_DMND_READ SNB_DMND_DATA_RD
1679#define SLM_DMND_WRITE SNB_DMND_RFO
1680#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1681
1682#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1683#define SLM_LLC_ACCESS SNB_RESP_ANY
1684#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1685
1686static __initconst const u64 slm_hw_cache_extra_regs
1687 [PERF_COUNT_HW_CACHE_MAX]
1688 [PERF_COUNT_HW_CACHE_OP_MAX]
1689 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1690{
1691 [ C(LL ) ] = {
1692 [ C(OP_READ) ] = {
1693 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1694 [ C(RESULT_MISS) ] = 0,
1695 },
1696 [ C(OP_WRITE) ] = {
1697 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1698 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1699 },
1700 [ C(OP_PREFETCH) ] = {
1701 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1702 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1703 },
1704 },
1705};
1706
1707static __initconst const u64 slm_hw_cache_event_ids
1708 [PERF_COUNT_HW_CACHE_MAX]
1709 [PERF_COUNT_HW_CACHE_OP_MAX]
1710 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1711{
1712 [ C(L1D) ] = {
1713 [ C(OP_READ) ] = {
1714 [ C(RESULT_ACCESS) ] = 0,
1715 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1716 },
1717 [ C(OP_WRITE) ] = {
1718 [ C(RESULT_ACCESS) ] = 0,
1719 [ C(RESULT_MISS) ] = 0,
1720 },
1721 [ C(OP_PREFETCH) ] = {
1722 [ C(RESULT_ACCESS) ] = 0,
1723 [ C(RESULT_MISS) ] = 0,
1724 },
1725 },
1726 [ C(L1I ) ] = {
1727 [ C(OP_READ) ] = {
1728 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1729 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1730 },
1731 [ C(OP_WRITE) ] = {
1732 [ C(RESULT_ACCESS) ] = -1,
1733 [ C(RESULT_MISS) ] = -1,
1734 },
1735 [ C(OP_PREFETCH) ] = {
1736 [ C(RESULT_ACCESS) ] = 0,
1737 [ C(RESULT_MISS) ] = 0,
1738 },
1739 },
1740 [ C(LL ) ] = {
1741 [ C(OP_READ) ] = {
1742 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1743 [ C(RESULT_ACCESS) ] = 0x01b7,
1744 [ C(RESULT_MISS) ] = 0,
1745 },
1746 [ C(OP_WRITE) ] = {
1747 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1748 [ C(RESULT_ACCESS) ] = 0x01b7,
1749 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1750 [ C(RESULT_MISS) ] = 0x01b7,
1751 },
1752 [ C(OP_PREFETCH) ] = {
1753 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1754 [ C(RESULT_ACCESS) ] = 0x01b7,
1755 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1756 [ C(RESULT_MISS) ] = 0x01b7,
1757 },
1758 },
1759 [ C(DTLB) ] = {
1760 [ C(OP_READ) ] = {
1761 [ C(RESULT_ACCESS) ] = 0,
1762 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1763 },
1764 [ C(OP_WRITE) ] = {
1765 [ C(RESULT_ACCESS) ] = 0,
1766 [ C(RESULT_MISS) ] = 0,
1767 },
1768 [ C(OP_PREFETCH) ] = {
1769 [ C(RESULT_ACCESS) ] = 0,
1770 [ C(RESULT_MISS) ] = 0,
1771 },
1772 },
1773 [ C(ITLB) ] = {
1774 [ C(OP_READ) ] = {
1775 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1776 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1777 },
1778 [ C(OP_WRITE) ] = {
1779 [ C(RESULT_ACCESS) ] = -1,
1780 [ C(RESULT_MISS) ] = -1,
1781 },
1782 [ C(OP_PREFETCH) ] = {
1783 [ C(RESULT_ACCESS) ] = -1,
1784 [ C(RESULT_MISS) ] = -1,
1785 },
1786 },
1787 [ C(BPU ) ] = {
1788 [ C(OP_READ) ] = {
1789 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1790 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1791 },
1792 [ C(OP_WRITE) ] = {
1793 [ C(RESULT_ACCESS) ] = -1,
1794 [ C(RESULT_MISS) ] = -1,
1795 },
1796 [ C(OP_PREFETCH) ] = {
1797 [ C(RESULT_ACCESS) ] = -1,
1798 [ C(RESULT_MISS) ] = -1,
1799 },
1800 },
1801};
1802
1803EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1804EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1805/* UOPS_NOT_DELIVERED.ANY */
1806EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1807/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1808EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1809/* UOPS_RETIRED.ANY */
1810EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1811/* UOPS_ISSUED.ANY */
1812EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1813
1814static struct attribute *glm_events_attrs[] = {
1815 EVENT_PTR(td_total_slots_glm),
1816 EVENT_PTR(td_total_slots_scale_glm),
1817 EVENT_PTR(td_fetch_bubbles_glm),
1818 EVENT_PTR(td_recovery_bubbles_glm),
1819 EVENT_PTR(td_slots_issued_glm),
1820 EVENT_PTR(td_slots_retired_glm),
1821 NULL
1822};
1823
1824static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1825 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1826 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1827 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1828 EVENT_EXTRA_END
1829};
1830
1831#define GLM_DEMAND_DATA_RD BIT_ULL(0)
1832#define GLM_DEMAND_RFO BIT_ULL(1)
1833#define GLM_ANY_RESPONSE BIT_ULL(16)
1834#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1835#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1836#define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1837#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1838#define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1839#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1840#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1841
1842static __initconst const u64 glm_hw_cache_event_ids
1843 [PERF_COUNT_HW_CACHE_MAX]
1844 [PERF_COUNT_HW_CACHE_OP_MAX]
1845 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1846 [C(L1D)] = {
1847 [C(OP_READ)] = {
1848 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1849 [C(RESULT_MISS)] = 0x0,
1850 },
1851 [C(OP_WRITE)] = {
1852 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1853 [C(RESULT_MISS)] = 0x0,
1854 },
1855 [C(OP_PREFETCH)] = {
1856 [C(RESULT_ACCESS)] = 0x0,
1857 [C(RESULT_MISS)] = 0x0,
1858 },
1859 },
1860 [C(L1I)] = {
1861 [C(OP_READ)] = {
1862 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1863 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1864 },
1865 [C(OP_WRITE)] = {
1866 [C(RESULT_ACCESS)] = -1,
1867 [C(RESULT_MISS)] = -1,
1868 },
1869 [C(OP_PREFETCH)] = {
1870 [C(RESULT_ACCESS)] = 0x0,
1871 [C(RESULT_MISS)] = 0x0,
1872 },
1873 },
1874 [C(LL)] = {
1875 [C(OP_READ)] = {
1876 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1877 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1878 },
1879 [C(OP_WRITE)] = {
1880 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1881 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1882 },
1883 [C(OP_PREFETCH)] = {
1884 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1885 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1886 },
1887 },
1888 [C(DTLB)] = {
1889 [C(OP_READ)] = {
1890 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1891 [C(RESULT_MISS)] = 0x0,
1892 },
1893 [C(OP_WRITE)] = {
1894 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1895 [C(RESULT_MISS)] = 0x0,
1896 },
1897 [C(OP_PREFETCH)] = {
1898 [C(RESULT_ACCESS)] = 0x0,
1899 [C(RESULT_MISS)] = 0x0,
1900 },
1901 },
1902 [C(ITLB)] = {
1903 [C(OP_READ)] = {
1904 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1905 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1906 },
1907 [C(OP_WRITE)] = {
1908 [C(RESULT_ACCESS)] = -1,
1909 [C(RESULT_MISS)] = -1,
1910 },
1911 [C(OP_PREFETCH)] = {
1912 [C(RESULT_ACCESS)] = -1,
1913 [C(RESULT_MISS)] = -1,
1914 },
1915 },
1916 [C(BPU)] = {
1917 [C(OP_READ)] = {
1918 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1919 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1920 },
1921 [C(OP_WRITE)] = {
1922 [C(RESULT_ACCESS)] = -1,
1923 [C(RESULT_MISS)] = -1,
1924 },
1925 [C(OP_PREFETCH)] = {
1926 [C(RESULT_ACCESS)] = -1,
1927 [C(RESULT_MISS)] = -1,
1928 },
1929 },
1930};
1931
1932static __initconst const u64 glm_hw_cache_extra_regs
1933 [PERF_COUNT_HW_CACHE_MAX]
1934 [PERF_COUNT_HW_CACHE_OP_MAX]
1935 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1936 [C(LL)] = {
1937 [C(OP_READ)] = {
1938 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1939 GLM_LLC_ACCESS,
1940 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1941 GLM_LLC_MISS,
1942 },
1943 [C(OP_WRITE)] = {
1944 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1945 GLM_LLC_ACCESS,
1946 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1947 GLM_LLC_MISS,
1948 },
1949 [C(OP_PREFETCH)] = {
1950 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1951 GLM_LLC_ACCESS,
1952 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1953 GLM_LLC_MISS,
1954 },
1955 },
1956};
1957
1958static __initconst const u64 glp_hw_cache_event_ids
1959 [PERF_COUNT_HW_CACHE_MAX]
1960 [PERF_COUNT_HW_CACHE_OP_MAX]
1961 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1962 [C(L1D)] = {
1963 [C(OP_READ)] = {
1964 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1965 [C(RESULT_MISS)] = 0x0,
1966 },
1967 [C(OP_WRITE)] = {
1968 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1969 [C(RESULT_MISS)] = 0x0,
1970 },
1971 [C(OP_PREFETCH)] = {
1972 [C(RESULT_ACCESS)] = 0x0,
1973 [C(RESULT_MISS)] = 0x0,
1974 },
1975 },
1976 [C(L1I)] = {
1977 [C(OP_READ)] = {
1978 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1979 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1980 },
1981 [C(OP_WRITE)] = {
1982 [C(RESULT_ACCESS)] = -1,
1983 [C(RESULT_MISS)] = -1,
1984 },
1985 [C(OP_PREFETCH)] = {
1986 [C(RESULT_ACCESS)] = 0x0,
1987 [C(RESULT_MISS)] = 0x0,
1988 },
1989 },
1990 [C(LL)] = {
1991 [C(OP_READ)] = {
1992 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1993 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1994 },
1995 [C(OP_WRITE)] = {
1996 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1997 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1998 },
1999 [C(OP_PREFETCH)] = {
2000 [C(RESULT_ACCESS)] = 0x0,
2001 [C(RESULT_MISS)] = 0x0,
2002 },
2003 },
2004 [C(DTLB)] = {
2005 [C(OP_READ)] = {
2006 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2007 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2008 },
2009 [C(OP_WRITE)] = {
2010 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2011 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2012 },
2013 [C(OP_PREFETCH)] = {
2014 [C(RESULT_ACCESS)] = 0x0,
2015 [C(RESULT_MISS)] = 0x0,
2016 },
2017 },
2018 [C(ITLB)] = {
2019 [C(OP_READ)] = {
2020 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2021 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2022 },
2023 [C(OP_WRITE)] = {
2024 [C(RESULT_ACCESS)] = -1,
2025 [C(RESULT_MISS)] = -1,
2026 },
2027 [C(OP_PREFETCH)] = {
2028 [C(RESULT_ACCESS)] = -1,
2029 [C(RESULT_MISS)] = -1,
2030 },
2031 },
2032 [C(BPU)] = {
2033 [C(OP_READ)] = {
2034 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2035 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2036 },
2037 [C(OP_WRITE)] = {
2038 [C(RESULT_ACCESS)] = -1,
2039 [C(RESULT_MISS)] = -1,
2040 },
2041 [C(OP_PREFETCH)] = {
2042 [C(RESULT_ACCESS)] = -1,
2043 [C(RESULT_MISS)] = -1,
2044 },
2045 },
2046};
2047
2048static __initconst const u64 glp_hw_cache_extra_regs
2049 [PERF_COUNT_HW_CACHE_MAX]
2050 [PERF_COUNT_HW_CACHE_OP_MAX]
2051 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2052 [C(LL)] = {
2053 [C(OP_READ)] = {
2054 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2055 GLM_LLC_ACCESS,
2056 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2057 GLM_LLC_MISS,
2058 },
2059 [C(OP_WRITE)] = {
2060 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2061 GLM_LLC_ACCESS,
2062 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2063 GLM_LLC_MISS,
2064 },
2065 [C(OP_PREFETCH)] = {
2066 [C(RESULT_ACCESS)] = 0x0,
2067 [C(RESULT_MISS)] = 0x0,
2068 },
2069 },
2070};
2071
2072#define TNT_LOCAL_DRAM BIT_ULL(26)
2073#define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2074#define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2075#define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2076#define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2077 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2078#define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2079
2080static __initconst const u64 tnt_hw_cache_extra_regs
2081 [PERF_COUNT_HW_CACHE_MAX]
2082 [PERF_COUNT_HW_CACHE_OP_MAX]
2083 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2084 [C(LL)] = {
2085 [C(OP_READ)] = {
2086 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2087 TNT_LLC_ACCESS,
2088 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2089 TNT_LLC_MISS,
2090 },
2091 [C(OP_WRITE)] = {
2092 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2093 TNT_LLC_ACCESS,
2094 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2095 TNT_LLC_MISS,
2096 },
2097 [C(OP_PREFETCH)] = {
2098 [C(RESULT_ACCESS)] = 0x0,
2099 [C(RESULT_MISS)] = 0x0,
2100 },
2101 },
2102};
2103
2104EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2105EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2106EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2107EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2108
2109static struct attribute *tnt_events_attrs[] = {
2110 EVENT_PTR(td_fe_bound_tnt),
2111 EVENT_PTR(td_retiring_tnt),
2112 EVENT_PTR(td_bad_spec_tnt),
2113 EVENT_PTR(td_be_bound_tnt),
2114 NULL,
2115};
2116
2117static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2118 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2119 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2120 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2121 EVENT_EXTRA_END
2122};
2123
2124EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2125EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2126
2127static struct attribute *grt_mem_attrs[] = {
2128 EVENT_PTR(mem_ld_grt),
2129 EVENT_PTR(mem_st_grt),
2130 NULL
2131};
2132
2133static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2134 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2135 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2136 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2137 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2138 EVENT_EXTRA_END
2139};
2140
2141EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2142EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2143
2144static struct attribute *cmt_events_attrs[] = {
2145 EVENT_PTR(td_fe_bound_tnt),
2146 EVENT_PTR(td_retiring_cmt),
2147 EVENT_PTR(td_bad_spec_cmt),
2148 EVENT_PTR(td_be_bound_tnt),
2149 NULL
2150};
2151
2152static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2153 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2154 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2155 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2156 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2157 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2158 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2159 EVENT_EXTRA_END
2160};
2161
2162#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2163#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2164#define KNL_MCDRAM_LOCAL BIT_ULL(21)
2165#define KNL_MCDRAM_FAR BIT_ULL(22)
2166#define KNL_DDR_LOCAL BIT_ULL(23)
2167#define KNL_DDR_FAR BIT_ULL(24)
2168#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2169 KNL_DDR_LOCAL | KNL_DDR_FAR)
2170#define KNL_L2_READ SLM_DMND_READ
2171#define KNL_L2_WRITE SLM_DMND_WRITE
2172#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2173#define KNL_L2_ACCESS SLM_LLC_ACCESS
2174#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2175 KNL_DRAM_ANY | SNB_SNP_ANY | \
2176 SNB_NON_DRAM)
2177
2178static __initconst const u64 knl_hw_cache_extra_regs
2179 [PERF_COUNT_HW_CACHE_MAX]
2180 [PERF_COUNT_HW_CACHE_OP_MAX]
2181 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2182 [C(LL)] = {
2183 [C(OP_READ)] = {
2184 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2185 [C(RESULT_MISS)] = 0,
2186 },
2187 [C(OP_WRITE)] = {
2188 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2189 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2190 },
2191 [C(OP_PREFETCH)] = {
2192 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2193 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2194 },
2195 },
2196};
2197
2198/*
2199 * Used from PMIs where the LBRs are already disabled.
2200 *
2201 * This function could be called consecutively. It is required to remain in
2202 * disabled state if called consecutively.
2203 *
2204 * During consecutive calls, the same disable value will be written to related
2205 * registers, so the PMU state remains unchanged.
2206 *
2207 * intel_bts events don't coexist with intel PMU's BTS events because of
2208 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2209 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2210 *
2211 * Avoid PEBS_ENABLE MSR access in PMIs.
2212 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2213 * It doesn't matter if the PEBS is enabled or not.
2214 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2215 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2216 * However, there are some cases which may change PEBS status, e.g. PMI
2217 * throttle. The PEBS_ENABLE should be updated where the status changes.
2218 */
2219static __always_inline void __intel_pmu_disable_all(bool bts)
2220{
2221 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2222
2223 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val: 0);
2224
2225 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2226 intel_pmu_disable_bts();
2227}
2228
2229static __always_inline void intel_pmu_disable_all(void)
2230{
2231 __intel_pmu_disable_all(bts: true);
2232 intel_pmu_pebs_disable_all();
2233 intel_pmu_lbr_disable_all();
2234}
2235
2236static void __intel_pmu_enable_all(int added, bool pmi)
2237{
2238 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2239 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2240
2241 intel_pmu_lbr_enable_all(pmi);
2242
2243 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2244 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, val: cpuc->fixed_ctrl_val);
2245 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2246 }
2247
2248 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2249 val: intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2250
2251 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2252 struct perf_event *event =
2253 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2254
2255 if (WARN_ON_ONCE(!event))
2256 return;
2257
2258 intel_pmu_enable_bts(config: event->hw.config);
2259 }
2260}
2261
2262static void intel_pmu_enable_all(int added)
2263{
2264 intel_pmu_pebs_enable_all();
2265 __intel_pmu_enable_all(added, pmi: false);
2266}
2267
2268static noinline int
2269__intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2270 unsigned int cnt, unsigned long flags)
2271{
2272 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2273
2274 intel_pmu_lbr_read();
2275 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2276
2277 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2278 intel_pmu_enable_all(added: 0);
2279 local_irq_restore(flags);
2280 return cnt;
2281}
2282
2283static int
2284intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2285{
2286 unsigned long flags;
2287
2288 /* must not have branches... */
2289 local_irq_save(flags);
2290 __intel_pmu_disable_all(bts: false); /* we don't care about BTS */
2291 __intel_pmu_lbr_disable();
2292 /* ... until here */
2293 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2294}
2295
2296static int
2297intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2298{
2299 unsigned long flags;
2300
2301 /* must not have branches... */
2302 local_irq_save(flags);
2303 __intel_pmu_disable_all(bts: false); /* we don't care about BTS */
2304 __intel_pmu_arch_lbr_disable();
2305 /* ... until here */
2306 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2307}
2308
2309/*
2310 * Workaround for:
2311 * Intel Errata AAK100 (model 26)
2312 * Intel Errata AAP53 (model 30)
2313 * Intel Errata BD53 (model 44)
2314 *
2315 * The official story:
2316 * These chips need to be 'reset' when adding counters by programming the
2317 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2318 * in sequence on the same PMC or on different PMCs.
2319 *
2320 * In practice it appears some of these events do in fact count, and
2321 * we need to program all 4 events.
2322 */
2323static void intel_pmu_nhm_workaround(void)
2324{
2325 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2326 static const unsigned long nhm_magic[4] = {
2327 0x4300B5,
2328 0x4300D2,
2329 0x4300B1,
2330 0x4300B1
2331 };
2332 struct perf_event *event;
2333 int i;
2334
2335 /*
2336 * The Errata requires below steps:
2337 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2338 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2339 * the corresponding PMCx;
2340 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2341 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2342 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2343 */
2344
2345 /*
2346 * The real steps we choose are a little different from above.
2347 * A) To reduce MSR operations, we don't run step 1) as they
2348 * are already cleared before this function is called;
2349 * B) Call x86_perf_event_update to save PMCx before configuring
2350 * PERFEVTSELx with magic number;
2351 * C) With step 5), we do clear only when the PERFEVTSELx is
2352 * not used currently.
2353 * D) Call x86_perf_event_set_period to restore PMCx;
2354 */
2355
2356 /* We always operate 4 pairs of PERF Counters */
2357 for (i = 0; i < 4; i++) {
2358 event = cpuc->events[i];
2359 if (event)
2360 static_call(x86_pmu_update)(event);
2361 }
2362
2363 for (i = 0; i < 4; i++) {
2364 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, val: nhm_magic[i]);
2365 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, val: 0x0);
2366 }
2367
2368 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val: 0xf);
2369 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val: 0x0);
2370
2371 for (i = 0; i < 4; i++) {
2372 event = cpuc->events[i];
2373
2374 if (event) {
2375 static_call(x86_pmu_set_period)(event);
2376 __x86_pmu_enable_event(hwc: &event->hw,
2377 ARCH_PERFMON_EVENTSEL_ENABLE);
2378 } else
2379 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, val: 0x0);
2380 }
2381}
2382
2383static void intel_pmu_nhm_enable_all(int added)
2384{
2385 if (added)
2386 intel_pmu_nhm_workaround();
2387 intel_pmu_enable_all(added);
2388}
2389
2390static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2391{
2392 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2393
2394 if (cpuc->tfa_shadow != val) {
2395 cpuc->tfa_shadow = val;
2396 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2397 }
2398}
2399
2400static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2401{
2402 /*
2403 * We're going to use PMC3, make sure TFA is set before we touch it.
2404 */
2405 if (cntr == 3)
2406 intel_set_tfa(cpuc, on: true);
2407}
2408
2409static void intel_tfa_pmu_enable_all(int added)
2410{
2411 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2412
2413 /*
2414 * If we find PMC3 is no longer used when we enable the PMU, we can
2415 * clear TFA.
2416 */
2417 if (!test_bit(3, cpuc->active_mask))
2418 intel_set_tfa(cpuc, on: false);
2419
2420 intel_pmu_enable_all(added);
2421}
2422
2423static inline u64 intel_pmu_get_status(void)
2424{
2425 u64 status;
2426
2427 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2428
2429 return status;
2430}
2431
2432static inline void intel_pmu_ack_status(u64 ack)
2433{
2434 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, val: ack);
2435}
2436
2437static inline bool event_is_checkpointed(struct perf_event *event)
2438{
2439 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2440}
2441
2442static inline void intel_set_masks(struct perf_event *event, int idx)
2443{
2444 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2445
2446 if (event->attr.exclude_host)
2447 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2448 if (event->attr.exclude_guest)
2449 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2450 if (event_is_checkpointed(event))
2451 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2452}
2453
2454static inline void intel_clear_masks(struct perf_event *event, int idx)
2455{
2456 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2457
2458 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2459 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2460 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2461}
2462
2463static void intel_pmu_disable_fixed(struct perf_event *event)
2464{
2465 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2466 struct hw_perf_event *hwc = &event->hw;
2467 int idx = hwc->idx;
2468 u64 mask;
2469
2470 if (is_topdown_idx(idx)) {
2471 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2472
2473 /*
2474 * When there are other active TopDown events,
2475 * don't disable the fixed counter 3.
2476 */
2477 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2478 return;
2479 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2480 }
2481
2482 intel_clear_masks(event, idx);
2483
2484 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
2485 cpuc->fixed_ctrl_val &= ~mask;
2486}
2487
2488static void intel_pmu_disable_event(struct perf_event *event)
2489{
2490 struct hw_perf_event *hwc = &event->hw;
2491 int idx = hwc->idx;
2492
2493 switch (idx) {
2494 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2495 intel_clear_masks(event, idx);
2496 x86_pmu_disable_event(event);
2497 break;
2498 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2499 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2500 intel_pmu_disable_fixed(event);
2501 break;
2502 case INTEL_PMC_IDX_FIXED_BTS:
2503 intel_pmu_disable_bts();
2504 intel_pmu_drain_bts_buffer();
2505 return;
2506 case INTEL_PMC_IDX_FIXED_VLBR:
2507 intel_clear_masks(event, idx);
2508 break;
2509 default:
2510 intel_clear_masks(event, idx);
2511 pr_warn("Failed to disable the event with invalid index %d\n",
2512 idx);
2513 return;
2514 }
2515
2516 /*
2517 * Needs to be called after x86_pmu_disable_event,
2518 * so we don't trigger the event without PEBS bit set.
2519 */
2520 if (unlikely(event->attr.precise_ip))
2521 intel_pmu_pebs_disable(event);
2522}
2523
2524static void intel_pmu_assign_event(struct perf_event *event, int idx)
2525{
2526 if (is_pebs_pt(event))
2527 perf_report_aux_output_id(event, hw_id: idx);
2528}
2529
2530static void intel_pmu_del_event(struct perf_event *event)
2531{
2532 if (needs_branch_stack(event))
2533 intel_pmu_lbr_del(event);
2534 if (event->attr.precise_ip)
2535 intel_pmu_pebs_del(event);
2536}
2537
2538static int icl_set_topdown_event_period(struct perf_event *event)
2539{
2540 struct hw_perf_event *hwc = &event->hw;
2541 s64 left = local64_read(&hwc->period_left);
2542
2543 /*
2544 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2545 * Software should start both registers, PERF_METRICS and fixed
2546 * counter 3, from zero.
2547 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2548 * After that, both MSRs will be cleared for each read.
2549 * Don't need to clear them again.
2550 */
2551 if (left == x86_pmu.max_period) {
2552 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, val: 0);
2553 wrmsrl(MSR_PERF_METRICS, val: 0);
2554 hwc->saved_slots = 0;
2555 hwc->saved_metric = 0;
2556 }
2557
2558 if ((hwc->saved_slots) && is_slots_event(event)) {
2559 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, val: hwc->saved_slots);
2560 wrmsrl(MSR_PERF_METRICS, val: hwc->saved_metric);
2561 }
2562
2563 perf_event_update_userpage(event);
2564
2565 return 0;
2566}
2567
2568DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2569
2570static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2571{
2572 u32 val;
2573
2574 /*
2575 * The metric is reported as an 8bit integer fraction
2576 * summing up to 0xff.
2577 * slots-in-metric = (Metric / 0xff) * slots
2578 */
2579 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2580 return mul_u64_u32_div(a: slots, mul: val, div: 0xff);
2581}
2582
2583static u64 icl_get_topdown_value(struct perf_event *event,
2584 u64 slots, u64 metrics)
2585{
2586 int idx = event->hw.idx;
2587 u64 delta;
2588
2589 if (is_metric_idx(idx))
2590 delta = icl_get_metrics_event_value(metric: metrics, slots, idx);
2591 else
2592 delta = slots;
2593
2594 return delta;
2595}
2596
2597static void __icl_update_topdown_event(struct perf_event *event,
2598 u64 slots, u64 metrics,
2599 u64 last_slots, u64 last_metrics)
2600{
2601 u64 delta, last = 0;
2602
2603 delta = icl_get_topdown_value(event, slots, metrics);
2604 if (last_slots)
2605 last = icl_get_topdown_value(event, slots: last_slots, metrics: last_metrics);
2606
2607 /*
2608 * The 8bit integer fraction of metric may be not accurate,
2609 * especially when the changes is very small.
2610 * For example, if only a few bad_spec happens, the fraction
2611 * may be reduced from 1 to 0. If so, the bad_spec event value
2612 * will be 0 which is definitely less than the last value.
2613 * Avoid update event->count for this case.
2614 */
2615 if (delta > last) {
2616 delta -= last;
2617 local64_add(delta, &event->count);
2618 }
2619}
2620
2621static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2622 u64 metrics, int metric_end)
2623{
2624 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2625 struct perf_event *other;
2626 int idx;
2627
2628 event->hw.saved_slots = slots;
2629 event->hw.saved_metric = metrics;
2630
2631 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2632 if (!is_topdown_idx(idx))
2633 continue;
2634 other = cpuc->events[idx];
2635 other->hw.saved_slots = slots;
2636 other->hw.saved_metric = metrics;
2637 }
2638}
2639
2640/*
2641 * Update all active Topdown events.
2642 *
2643 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2644 * modify by a NMI. PMU has to be disabled before calling this function.
2645 */
2646
2647static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2648{
2649 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2650 struct perf_event *other;
2651 u64 slots, metrics;
2652 bool reset = true;
2653 int idx;
2654
2655 /* read Fixed counter 3 */
2656 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2657 if (!slots)
2658 return 0;
2659
2660 /* read PERF_METRICS */
2661 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2662
2663 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2664 if (!is_topdown_idx(idx))
2665 continue;
2666 other = cpuc->events[idx];
2667 __icl_update_topdown_event(event: other, slots, metrics,
2668 last_slots: event ? event->hw.saved_slots : 0,
2669 last_metrics: event ? event->hw.saved_metric : 0);
2670 }
2671
2672 /*
2673 * Check and update this event, which may have been cleared
2674 * in active_mask e.g. x86_pmu_stop()
2675 */
2676 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2677 __icl_update_topdown_event(event, slots, metrics,
2678 last_slots: event->hw.saved_slots,
2679 last_metrics: event->hw.saved_metric);
2680
2681 /*
2682 * In x86_pmu_stop(), the event is cleared in active_mask first,
2683 * then drain the delta, which indicates context switch for
2684 * counting.
2685 * Save metric and slots for context switch.
2686 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2687 * Because the values will be restored in next schedule in.
2688 */
2689 update_saved_topdown_regs(event, slots, metrics, metric_end);
2690 reset = false;
2691 }
2692
2693 if (reset) {
2694 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2695 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, val: 0);
2696 wrmsrl(MSR_PERF_METRICS, val: 0);
2697 if (event)
2698 update_saved_topdown_regs(event, slots: 0, metrics: 0, metric_end);
2699 }
2700
2701 return slots;
2702}
2703
2704static u64 icl_update_topdown_event(struct perf_event *event)
2705{
2706 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2707 x86_pmu.num_topdown_events - 1);
2708}
2709
2710DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);
2711
2712static void intel_pmu_read_topdown_event(struct perf_event *event)
2713{
2714 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2715
2716 /* Only need to call update_topdown_event() once for group read. */
2717 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2718 !is_slots_event(event))
2719 return;
2720
2721 perf_pmu_disable(pmu: event->pmu);
2722 static_call(intel_pmu_update_topdown_event)(event);
2723 perf_pmu_enable(pmu: event->pmu);
2724}
2725
2726static void intel_pmu_read_event(struct perf_event *event)
2727{
2728 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2729 intel_pmu_auto_reload_read(event);
2730 else if (is_topdown_count(event))
2731 intel_pmu_read_topdown_event(event);
2732 else
2733 x86_perf_event_update(event);
2734}
2735
2736static void intel_pmu_enable_fixed(struct perf_event *event)
2737{
2738 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2739 struct hw_perf_event *hwc = &event->hw;
2740 u64 mask, bits = 0;
2741 int idx = hwc->idx;
2742
2743 if (is_topdown_idx(idx)) {
2744 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2745 /*
2746 * When there are other active TopDown events,
2747 * don't enable the fixed counter 3 again.
2748 */
2749 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2750 return;
2751
2752 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2753 }
2754
2755 intel_set_masks(event, idx);
2756
2757 /*
2758 * Enable IRQ generation (0x8), if not PEBS,
2759 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2760 * if requested:
2761 */
2762 if (!event->attr.precise_ip)
2763 bits |= INTEL_FIXED_0_ENABLE_PMI;
2764 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2765 bits |= INTEL_FIXED_0_USER;
2766 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2767 bits |= INTEL_FIXED_0_KERNEL;
2768
2769 /*
2770 * ANY bit is supported in v3 and up
2771 */
2772 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2773 bits |= INTEL_FIXED_0_ANYTHREAD;
2774
2775 idx -= INTEL_PMC_IDX_FIXED;
2776 bits = intel_fixed_bits_by_idx(idx, bits);
2777 mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
2778
2779 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2780 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2781 mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
2782 }
2783
2784 cpuc->fixed_ctrl_val &= ~mask;
2785 cpuc->fixed_ctrl_val |= bits;
2786}
2787
2788static void intel_pmu_enable_event(struct perf_event *event)
2789{
2790 struct hw_perf_event *hwc = &event->hw;
2791 int idx = hwc->idx;
2792
2793 if (unlikely(event->attr.precise_ip))
2794 intel_pmu_pebs_enable(event);
2795
2796 switch (idx) {
2797 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2798 intel_set_masks(event, idx);
2799 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2800 break;
2801 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2802 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2803 intel_pmu_enable_fixed(event);
2804 break;
2805 case INTEL_PMC_IDX_FIXED_BTS:
2806 if (!__this_cpu_read(cpu_hw_events.enabled))
2807 return;
2808 intel_pmu_enable_bts(config: hwc->config);
2809 break;
2810 case INTEL_PMC_IDX_FIXED_VLBR:
2811 intel_set_masks(event, idx);
2812 break;
2813 default:
2814 pr_warn("Failed to enable the event with invalid index %d\n",
2815 idx);
2816 }
2817}
2818
2819static void intel_pmu_add_event(struct perf_event *event)
2820{
2821 if (event->attr.precise_ip)
2822 intel_pmu_pebs_add(event);
2823 if (needs_branch_stack(event))
2824 intel_pmu_lbr_add(event);
2825}
2826
2827/*
2828 * Save and restart an expired event. Called by NMI contexts,
2829 * so it has to be careful about preempting normal event ops:
2830 */
2831int intel_pmu_save_and_restart(struct perf_event *event)
2832{
2833 static_call(x86_pmu_update)(event);
2834 /*
2835 * For a checkpointed counter always reset back to 0. This
2836 * avoids a situation where the counter overflows, aborts the
2837 * transaction and is then set back to shortly before the
2838 * overflow, and overflows and aborts again.
2839 */
2840 if (unlikely(event_is_checkpointed(event))) {
2841 /* No race with NMIs because the counter should not be armed */
2842 wrmsrl(msr: event->hw.event_base, val: 0);
2843 local64_set(&event->hw.prev_count, 0);
2844 }
2845 return static_call(x86_pmu_set_period)(event);
2846}
2847
2848static int intel_pmu_set_period(struct perf_event *event)
2849{
2850 if (unlikely(is_topdown_count(event)))
2851 return static_call(intel_pmu_set_topdown_event_period)(event);
2852
2853 return x86_perf_event_set_period(event);
2854}
2855
2856static u64 intel_pmu_update(struct perf_event *event)
2857{
2858 if (unlikely(is_topdown_count(event)))
2859 return static_call(intel_pmu_update_topdown_event)(event);
2860
2861 return x86_perf_event_update(event);
2862}
2863
2864static void intel_pmu_reset(void)
2865{
2866 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2867 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2868 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2869 int num_counters = hybrid(cpuc->pmu, num_counters);
2870 unsigned long flags;
2871 int idx;
2872
2873 if (!num_counters)
2874 return;
2875
2876 local_irq_save(flags);
2877
2878 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2879
2880 for (idx = 0; idx < num_counters; idx++) {
2881 wrmsrl_safe(msr: x86_pmu_config_addr(index: idx), val: 0ull);
2882 wrmsrl_safe(msr: x86_pmu_event_addr(index: idx), val: 0ull);
2883 }
2884 for (idx = 0; idx < num_counters_fixed; idx++) {
2885 if (fixed_counter_disabled(i: idx, pmu: cpuc->pmu))
2886 continue;
2887 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, val: 0ull);
2888 }
2889
2890 if (ds)
2891 ds->bts_index = ds->bts_buffer_base;
2892
2893 /* Ack all overflows and disable fixed counters */
2894 if (x86_pmu.version >= 2) {
2895 intel_pmu_ack_status(ack: intel_pmu_get_status());
2896 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, val: 0);
2897 }
2898
2899 /* Reset LBRs and LBR freezing */
2900 if (x86_pmu.lbr_nr) {
2901 update_debugctlmsr(debugctlmsr: get_debugctlmsr() &
2902 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2903 }
2904
2905 local_irq_restore(flags);
2906}
2907
2908/*
2909 * We may be running with guest PEBS events created by KVM, and the
2910 * PEBS records are logged into the guest's DS and invisible to host.
2911 *
2912 * In the case of guest PEBS overflow, we only trigger a fake event
2913 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
2914 * The guest will then vm-entry and check the guest DS area to read
2915 * the guest PEBS records.
2916 *
2917 * The contents and other behavior of the guest event do not matter.
2918 */
2919static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
2920 struct perf_sample_data *data)
2921{
2922 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2923 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
2924 struct perf_event *event = NULL;
2925 int bit;
2926
2927 if (!unlikely(perf_guest_state()))
2928 return;
2929
2930 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
2931 !guest_pebs_idxs)
2932 return;
2933
2934 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs,
2935 INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) {
2936 event = cpuc->events[bit];
2937 if (!event->attr.precise_ip)
2938 continue;
2939
2940 perf_sample_data_init(data, addr: 0, period: event->hw.last_period);
2941 if (perf_event_overflow(event, data, regs))
2942 x86_pmu_stop(event, flags: 0);
2943
2944 /* Inject one fake event is enough. */
2945 break;
2946 }
2947}
2948
2949static int handle_pmi_common(struct pt_regs *regs, u64 status)
2950{
2951 struct perf_sample_data data;
2952 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2953 int bit;
2954 int handled = 0;
2955 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2956
2957 inc_irq_stat(apic_perf_irqs);
2958
2959 /*
2960 * Ignore a range of extra bits in status that do not indicate
2961 * overflow by themselves.
2962 */
2963 status &= ~(GLOBAL_STATUS_COND_CHG |
2964 GLOBAL_STATUS_ASIF |
2965 GLOBAL_STATUS_LBRS_FROZEN);
2966 if (!status)
2967 return 0;
2968 /*
2969 * In case multiple PEBS events are sampled at the same time,
2970 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2971 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2972 * having their bits set in the status register. This is a sign
2973 * that there was at least one PEBS record pending at the time
2974 * of the PMU interrupt. PEBS counters must only be processed
2975 * via the drain_pebs() calls and not via the regular sample
2976 * processing loop coming after that the function, otherwise
2977 * phony regular samples may be generated in the sampling buffer
2978 * not marked with the EXACT tag. Another possibility is to have
2979 * one PEBS event and at least one non-PEBS event which overflows
2980 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2981 * not be set, yet the overflow status bit for the PEBS counter will
2982 * be on Skylake.
2983 *
2984 * To avoid this problem, we systematically ignore the PEBS-enabled
2985 * counters from the GLOBAL_STATUS mask and we always process PEBS
2986 * events via drain_pebs().
2987 */
2988 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
2989
2990 /*
2991 * PEBS overflow sets bit 62 in the global status register
2992 */
2993 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2994 u64 pebs_enabled = cpuc->pebs_enabled;
2995
2996 handled++;
2997 x86_pmu_handle_guest_pebs(regs, data: &data);
2998 x86_pmu.drain_pebs(regs, &data);
2999 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
3000
3001 /*
3002 * PMI throttle may be triggered, which stops the PEBS event.
3003 * Although cpuc->pebs_enabled is updated accordingly, the
3004 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3005 * cpuc->enabled has been forced to 0 in PMI.
3006 * Update the MSR if pebs_enabled is changed.
3007 */
3008 if (pebs_enabled != cpuc->pebs_enabled)
3009 wrmsrl(MSR_IA32_PEBS_ENABLE, val: cpuc->pebs_enabled);
3010 }
3011
3012 /*
3013 * Intel PT
3014 */
3015 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3016 handled++;
3017 if (!perf_guest_handle_intel_pt_intr())
3018 intel_pt_interrupt();
3019 }
3020
3021 /*
3022 * Intel Perf metrics
3023 */
3024 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3025 handled++;
3026 static_call(intel_pmu_update_topdown_event)(NULL);
3027 }
3028
3029 /*
3030 * Checkpointed counters can lead to 'spurious' PMIs because the
3031 * rollback caused by the PMI will have cleared the overflow status
3032 * bit. Therefore always force probe these counters.
3033 */
3034 status |= cpuc->intel_cp_status;
3035
3036 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3037 struct perf_event *event = cpuc->events[bit];
3038
3039 handled++;
3040
3041 if (!test_bit(bit, cpuc->active_mask))
3042 continue;
3043
3044 if (!intel_pmu_save_and_restart(event))
3045 continue;
3046
3047 perf_sample_data_init(data: &data, addr: 0, period: event->hw.last_period);
3048
3049 if (has_branch_stack(event))
3050 perf_sample_save_brstack(data: &data, event, brs: &cpuc->lbr_stack);
3051
3052 if (perf_event_overflow(event, data: &data, regs))
3053 x86_pmu_stop(event, flags: 0);
3054 }
3055
3056 return handled;
3057}
3058
3059/*
3060 * This handler is triggered by the local APIC, so the APIC IRQ handling
3061 * rules apply:
3062 */
3063static int intel_pmu_handle_irq(struct pt_regs *regs)
3064{
3065 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3066 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3067 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3068 int loops;
3069 u64 status;
3070 int handled;
3071 int pmu_enabled;
3072
3073 /*
3074 * Save the PMU state.
3075 * It needs to be restored when leaving the handler.
3076 */
3077 pmu_enabled = cpuc->enabled;
3078 /*
3079 * In general, the early ACK is only applied for old platforms.
3080 * For the big core starts from Haswell, the late ACK should be
3081 * applied.
3082 * For the small core after Tremont, we have to do the ACK right
3083 * before re-enabling counters, which is in the middle of the
3084 * NMI handler.
3085 */
3086 if (!late_ack && !mid_ack)
3087 apic_write(APIC_LVTPC, APIC_DM_NMI);
3088 intel_bts_disable_local();
3089 cpuc->enabled = 0;
3090 __intel_pmu_disable_all(bts: true);
3091 handled = intel_pmu_drain_bts_buffer();
3092 handled += intel_bts_interrupt();
3093 status = intel_pmu_get_status();
3094 if (!status)
3095 goto done;
3096
3097 loops = 0;
3098again:
3099 intel_pmu_lbr_read();
3100 intel_pmu_ack_status(ack: status);
3101 if (++loops > 100) {
3102 static bool warned;
3103
3104 if (!warned) {
3105 WARN(1, "perfevents: irq loop stuck!\n");
3106 perf_event_print_debug();
3107 warned = true;
3108 }
3109 intel_pmu_reset();
3110 goto done;
3111 }
3112
3113 handled += handle_pmi_common(regs, status);
3114
3115 /*
3116 * Repeat if there is more work to be done:
3117 */
3118 status = intel_pmu_get_status();
3119 if (status)
3120 goto again;
3121
3122done:
3123 if (mid_ack)
3124 apic_write(APIC_LVTPC, APIC_DM_NMI);
3125 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3126 cpuc->enabled = pmu_enabled;
3127 if (pmu_enabled)
3128 __intel_pmu_enable_all(added: 0, pmi: true);
3129 intel_bts_enable_local();
3130
3131 /*
3132 * Only unmask the NMI after the overflow counters
3133 * have been reset. This avoids spurious NMIs on
3134 * Haswell CPUs.
3135 */
3136 if (late_ack)
3137 apic_write(APIC_LVTPC, APIC_DM_NMI);
3138 return handled;
3139}
3140
3141static struct event_constraint *
3142intel_bts_constraints(struct perf_event *event)
3143{
3144 if (unlikely(intel_pmu_has_bts(event)))
3145 return &bts_constraint;
3146
3147 return NULL;
3148}
3149
3150/*
3151 * Note: matches a fake event, like Fixed2.
3152 */
3153static struct event_constraint *
3154intel_vlbr_constraints(struct perf_event *event)
3155{
3156 struct event_constraint *c = &vlbr_constraint;
3157
3158 if (unlikely(constraint_match(c, event->hw.config))) {
3159 event->hw.flags |= c->flags;
3160 return c;
3161 }
3162
3163 return NULL;
3164}
3165
3166static int intel_alt_er(struct cpu_hw_events *cpuc,
3167 int idx, u64 config)
3168{
3169 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3170 int alt_idx = idx;
3171
3172 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3173 return idx;
3174
3175 if (idx == EXTRA_REG_RSP_0)
3176 alt_idx = EXTRA_REG_RSP_1;
3177
3178 if (idx == EXTRA_REG_RSP_1)
3179 alt_idx = EXTRA_REG_RSP_0;
3180
3181 if (config & ~extra_regs[alt_idx].valid_mask)
3182 return idx;
3183
3184 return alt_idx;
3185}
3186
3187static void intel_fixup_er(struct perf_event *event, int idx)
3188{
3189 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3190 event->hw.extra_reg.idx = idx;
3191
3192 if (idx == EXTRA_REG_RSP_0) {
3193 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3194 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3195 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3196 } else if (idx == EXTRA_REG_RSP_1) {
3197 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3198 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3199 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3200 }
3201}
3202
3203/*
3204 * manage allocation of shared extra msr for certain events
3205 *
3206 * sharing can be:
3207 * per-cpu: to be shared between the various events on a single PMU
3208 * per-core: per-cpu + shared by HT threads
3209 */
3210static struct event_constraint *
3211__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3212 struct perf_event *event,
3213 struct hw_perf_event_extra *reg)
3214{
3215 struct event_constraint *c = &emptyconstraint;
3216 struct er_account *era;
3217 unsigned long flags;
3218 int idx = reg->idx;
3219
3220 /*
3221 * reg->alloc can be set due to existing state, so for fake cpuc we
3222 * need to ignore this, otherwise we might fail to allocate proper fake
3223 * state for this extra reg constraint. Also see the comment below.
3224 */
3225 if (reg->alloc && !cpuc->is_fake)
3226 return NULL; /* call x86_get_event_constraint() */
3227
3228again:
3229 era = &cpuc->shared_regs->regs[idx];
3230 /*
3231 * we use spin_lock_irqsave() to avoid lockdep issues when
3232 * passing a fake cpuc
3233 */
3234 raw_spin_lock_irqsave(&era->lock, flags);
3235
3236 if (!atomic_read(v: &era->ref) || era->config == reg->config) {
3237
3238 /*
3239 * If its a fake cpuc -- as per validate_{group,event}() we
3240 * shouldn't touch event state and we can avoid doing so
3241 * since both will only call get_event_constraints() once
3242 * on each event, this avoids the need for reg->alloc.
3243 *
3244 * Not doing the ER fixup will only result in era->reg being
3245 * wrong, but since we won't actually try and program hardware
3246 * this isn't a problem either.
3247 */
3248 if (!cpuc->is_fake) {
3249 if (idx != reg->idx)
3250 intel_fixup_er(event, idx);
3251
3252 /*
3253 * x86_schedule_events() can call get_event_constraints()
3254 * multiple times on events in the case of incremental
3255 * scheduling(). reg->alloc ensures we only do the ER
3256 * allocation once.
3257 */
3258 reg->alloc = 1;
3259 }
3260
3261 /* lock in msr value */
3262 era->config = reg->config;
3263 era->reg = reg->reg;
3264
3265 /* one more user */
3266 atomic_inc(v: &era->ref);
3267
3268 /*
3269 * need to call x86_get_event_constraint()
3270 * to check if associated event has constraints
3271 */
3272 c = NULL;
3273 } else {
3274 idx = intel_alt_er(cpuc, idx, config: reg->config);
3275 if (idx != reg->idx) {
3276 raw_spin_unlock_irqrestore(&era->lock, flags);
3277 goto again;
3278 }
3279 }
3280 raw_spin_unlock_irqrestore(&era->lock, flags);
3281
3282 return c;
3283}
3284
3285static void
3286__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3287 struct hw_perf_event_extra *reg)
3288{
3289 struct er_account *era;
3290
3291 /*
3292 * Only put constraint if extra reg was actually allocated. Also takes
3293 * care of event which do not use an extra shared reg.
3294 *
3295 * Also, if this is a fake cpuc we shouldn't touch any event state
3296 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3297 * either since it'll be thrown out.
3298 */
3299 if (!reg->alloc || cpuc->is_fake)
3300 return;
3301
3302 era = &cpuc->shared_regs->regs[reg->idx];
3303
3304 /* one fewer user */
3305 atomic_dec(v: &era->ref);
3306
3307 /* allocate again next time */
3308 reg->alloc = 0;
3309}
3310
3311static struct event_constraint *
3312intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3313 struct perf_event *event)
3314{
3315 struct event_constraint *c = NULL, *d;
3316 struct hw_perf_event_extra *xreg, *breg;
3317
3318 xreg = &event->hw.extra_reg;
3319 if (xreg->idx != EXTRA_REG_NONE) {
3320 c = __intel_shared_reg_get_constraints(cpuc, event, reg: xreg);
3321 if (c == &emptyconstraint)
3322 return c;
3323 }
3324 breg = &event->hw.branch_reg;
3325 if (breg->idx != EXTRA_REG_NONE) {
3326 d = __intel_shared_reg_get_constraints(cpuc, event, reg: breg);
3327 if (d == &emptyconstraint) {
3328 __intel_shared_reg_put_constraints(cpuc, reg: xreg);
3329 c = d;
3330 }
3331 }
3332 return c;
3333}
3334
3335struct event_constraint *
3336x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3337 struct perf_event *event)
3338{
3339 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3340 struct event_constraint *c;
3341
3342 if (event_constraints) {
3343 for_each_event_constraint(c, event_constraints) {
3344 if (constraint_match(c, ecode: event->hw.config)) {
3345 event->hw.flags |= c->flags;
3346 return c;
3347 }
3348 }
3349 }
3350
3351 return &hybrid_var(cpuc->pmu, unconstrained);
3352}
3353
3354static struct event_constraint *
3355__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3356 struct perf_event *event)
3357{
3358 struct event_constraint *c;
3359
3360 c = intel_vlbr_constraints(event);
3361 if (c)
3362 return c;
3363
3364 c = intel_bts_constraints(event);
3365 if (c)
3366 return c;
3367
3368 c = intel_shared_regs_constraints(cpuc, event);
3369 if (c)
3370 return c;
3371
3372 c = intel_pebs_constraints(event);
3373 if (c)
3374 return c;
3375
3376 return x86_get_event_constraints(cpuc, idx, event);
3377}
3378
3379static void
3380intel_start_scheduling(struct cpu_hw_events *cpuc)
3381{
3382 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3383 struct intel_excl_states *xl;
3384 int tid = cpuc->excl_thread_id;
3385
3386 /*
3387 * nothing needed if in group validation mode
3388 */
3389 if (cpuc->is_fake || !is_ht_workaround_enabled())
3390 return;
3391
3392 /*
3393 * no exclusion needed
3394 */
3395 if (WARN_ON_ONCE(!excl_cntrs))
3396 return;
3397
3398 xl = &excl_cntrs->states[tid];
3399
3400 xl->sched_started = true;
3401 /*
3402 * lock shared state until we are done scheduling
3403 * in stop_event_scheduling()
3404 * makes scheduling appear as a transaction
3405 */
3406 raw_spin_lock(&excl_cntrs->lock);
3407}
3408
3409static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3410{
3411 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3412 struct event_constraint *c = cpuc->event_constraint[idx];
3413 struct intel_excl_states *xl;
3414 int tid = cpuc->excl_thread_id;
3415
3416 if (cpuc->is_fake || !is_ht_workaround_enabled())
3417 return;
3418
3419 if (WARN_ON_ONCE(!excl_cntrs))
3420 return;
3421
3422 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3423 return;
3424
3425 xl = &excl_cntrs->states[tid];
3426
3427 lockdep_assert_held(&excl_cntrs->lock);
3428
3429 if (c->flags & PERF_X86_EVENT_EXCL)
3430 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3431 else
3432 xl->state[cntr] = INTEL_EXCL_SHARED;
3433}
3434
3435static void
3436intel_stop_scheduling(struct cpu_hw_events *cpuc)
3437{
3438 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3439 struct intel_excl_states *xl;
3440 int tid = cpuc->excl_thread_id;
3441
3442 /*
3443 * nothing needed if in group validation mode
3444 */
3445 if (cpuc->is_fake || !is_ht_workaround_enabled())
3446 return;
3447 /*
3448 * no exclusion needed
3449 */
3450 if (WARN_ON_ONCE(!excl_cntrs))
3451 return;
3452
3453 xl = &excl_cntrs->states[tid];
3454
3455 xl->sched_started = false;
3456 /*
3457 * release shared state lock (acquired in intel_start_scheduling())
3458 */
3459 raw_spin_unlock(&excl_cntrs->lock);
3460}
3461
3462static struct event_constraint *
3463dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3464{
3465 WARN_ON_ONCE(!cpuc->constraint_list);
3466
3467 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3468 struct event_constraint *cx;
3469
3470 /*
3471 * grab pre-allocated constraint entry
3472 */
3473 cx = &cpuc->constraint_list[idx];
3474
3475 /*
3476 * initialize dynamic constraint
3477 * with static constraint
3478 */
3479 *cx = *c;
3480
3481 /*
3482 * mark constraint as dynamic
3483 */
3484 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3485 c = cx;
3486 }
3487
3488 return c;
3489}
3490
3491static struct event_constraint *
3492intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3493 int idx, struct event_constraint *c)
3494{
3495 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3496 struct intel_excl_states *xlo;
3497 int tid = cpuc->excl_thread_id;
3498 int is_excl, i, w;
3499
3500 /*
3501 * validating a group does not require
3502 * enforcing cross-thread exclusion
3503 */
3504 if (cpuc->is_fake || !is_ht_workaround_enabled())
3505 return c;
3506
3507 /*
3508 * no exclusion needed
3509 */
3510 if (WARN_ON_ONCE(!excl_cntrs))
3511 return c;
3512
3513 /*
3514 * because we modify the constraint, we need
3515 * to make a copy. Static constraints come
3516 * from static const tables.
3517 *
3518 * only needed when constraint has not yet
3519 * been cloned (marked dynamic)
3520 */
3521 c = dyn_constraint(cpuc, c, idx);
3522
3523 /*
3524 * From here on, the constraint is dynamic.
3525 * Either it was just allocated above, or it
3526 * was allocated during a earlier invocation
3527 * of this function
3528 */
3529
3530 /*
3531 * state of sibling HT
3532 */
3533 xlo = &excl_cntrs->states[tid ^ 1];
3534
3535 /*
3536 * event requires exclusive counter access
3537 * across HT threads
3538 */
3539 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3540 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3541 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3542 if (!cpuc->n_excl++)
3543 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3544 }
3545
3546 /*
3547 * Modify static constraint with current dynamic
3548 * state of thread
3549 *
3550 * EXCLUSIVE: sibling counter measuring exclusive event
3551 * SHARED : sibling counter measuring non-exclusive event
3552 * UNUSED : sibling counter unused
3553 */
3554 w = c->weight;
3555 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3556 /*
3557 * exclusive event in sibling counter
3558 * our corresponding counter cannot be used
3559 * regardless of our event
3560 */
3561 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3562 __clear_bit(i, c->idxmsk);
3563 w--;
3564 continue;
3565 }
3566 /*
3567 * if measuring an exclusive event, sibling
3568 * measuring non-exclusive, then counter cannot
3569 * be used
3570 */
3571 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3572 __clear_bit(i, c->idxmsk);
3573 w--;
3574 continue;
3575 }
3576 }
3577
3578 /*
3579 * if we return an empty mask, then switch
3580 * back to static empty constraint to avoid
3581 * the cost of freeing later on
3582 */
3583 if (!w)
3584 c = &emptyconstraint;
3585
3586 c->weight = w;
3587
3588 return c;
3589}
3590
3591static struct event_constraint *
3592intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3593 struct perf_event *event)
3594{
3595 struct event_constraint *c1, *c2;
3596
3597 c1 = cpuc->event_constraint[idx];
3598
3599 /*
3600 * first time only
3601 * - static constraint: no change across incremental scheduling calls
3602 * - dynamic constraint: handled by intel_get_excl_constraints()
3603 */
3604 c2 = __intel_get_event_constraints(cpuc, idx, event);
3605 if (c1) {
3606 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3607 bitmap_copy(dst: c1->idxmsk, src: c2->idxmsk, X86_PMC_IDX_MAX);
3608 c1->weight = c2->weight;
3609 c2 = c1;
3610 }
3611
3612 if (cpuc->excl_cntrs)
3613 return intel_get_excl_constraints(cpuc, event, idx, c: c2);
3614
3615 return c2;
3616}
3617
3618static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3619 struct perf_event *event)
3620{
3621 struct hw_perf_event *hwc = &event->hw;
3622 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3623 int tid = cpuc->excl_thread_id;
3624 struct intel_excl_states *xl;
3625
3626 /*
3627 * nothing needed if in group validation mode
3628 */
3629 if (cpuc->is_fake)
3630 return;
3631
3632 if (WARN_ON_ONCE(!excl_cntrs))
3633 return;
3634
3635 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3636 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3637 if (!--cpuc->n_excl)
3638 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3639 }
3640
3641 /*
3642 * If event was actually assigned, then mark the counter state as
3643 * unused now.
3644 */
3645 if (hwc->idx >= 0) {
3646 xl = &excl_cntrs->states[tid];
3647
3648 /*
3649 * put_constraint may be called from x86_schedule_events()
3650 * which already has the lock held so here make locking
3651 * conditional.
3652 */
3653 if (!xl->sched_started)
3654 raw_spin_lock(&excl_cntrs->lock);
3655
3656 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3657
3658 if (!xl->sched_started)
3659 raw_spin_unlock(&excl_cntrs->lock);
3660 }
3661}
3662
3663static void
3664intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3665 struct perf_event *event)
3666{
3667 struct hw_perf_event_extra *reg;
3668
3669 reg = &event->hw.extra_reg;
3670 if (reg->idx != EXTRA_REG_NONE)
3671 __intel_shared_reg_put_constraints(cpuc, reg);
3672
3673 reg = &event->hw.branch_reg;
3674 if (reg->idx != EXTRA_REG_NONE)
3675 __intel_shared_reg_put_constraints(cpuc, reg);
3676}
3677
3678static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3679 struct perf_event *event)
3680{
3681 intel_put_shared_regs_event_constraints(cpuc, event);
3682
3683 /*
3684 * is PMU has exclusive counter restrictions, then
3685 * all events are subject to and must call the
3686 * put_excl_constraints() routine
3687 */
3688 if (cpuc->excl_cntrs)
3689 intel_put_excl_constraints(cpuc, event);
3690}
3691
3692static void intel_pebs_aliases_core2(struct perf_event *event)
3693{
3694 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3695 /*
3696 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3697 * (0x003c) so that we can use it with PEBS.
3698 *
3699 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3700 * PEBS capable. However we can use INST_RETIRED.ANY_P
3701 * (0x00c0), which is a PEBS capable event, to get the same
3702 * count.
3703 *
3704 * INST_RETIRED.ANY_P counts the number of cycles that retires
3705 * CNTMASK instructions. By setting CNTMASK to a value (16)
3706 * larger than the maximum number of instructions that can be
3707 * retired per cycle (4) and then inverting the condition, we
3708 * count all cycles that retire 16 or less instructions, which
3709 * is every cycle.
3710 *
3711 * Thereby we gain a PEBS capable cycle counter.
3712 */
3713 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3714
3715 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3716 event->hw.config = alt_config;
3717 }
3718}
3719
3720static void intel_pebs_aliases_snb(struct perf_event *event)
3721{
3722 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3723 /*
3724 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3725 * (0x003c) so that we can use it with PEBS.
3726 *
3727 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3728 * PEBS capable. However we can use UOPS_RETIRED.ALL
3729 * (0x01c2), which is a PEBS capable event, to get the same
3730 * count.
3731 *
3732 * UOPS_RETIRED.ALL counts the number of cycles that retires
3733 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3734 * larger than the maximum number of micro-ops that can be
3735 * retired per cycle (4) and then inverting the condition, we
3736 * count all cycles that retire 16 or less micro-ops, which
3737 * is every cycle.
3738 *
3739 * Thereby we gain a PEBS capable cycle counter.
3740 */
3741 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3742
3743 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3744 event->hw.config = alt_config;
3745 }
3746}
3747
3748static void intel_pebs_aliases_precdist(struct perf_event *event)
3749{
3750 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3751 /*
3752 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3753 * (0x003c) so that we can use it with PEBS.
3754 *
3755 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3756 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3757 * (0x01c0), which is a PEBS capable event, to get the same
3758 * count.
3759 *
3760 * The PREC_DIST event has special support to minimize sample
3761 * shadowing effects. One drawback is that it can be
3762 * only programmed on counter 1, but that seems like an
3763 * acceptable trade off.
3764 */
3765 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3766
3767 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3768 event->hw.config = alt_config;
3769 }
3770}
3771
3772static void intel_pebs_aliases_ivb(struct perf_event *event)
3773{
3774 if (event->attr.precise_ip < 3)
3775 return intel_pebs_aliases_snb(event);
3776 return intel_pebs_aliases_precdist(event);
3777}
3778
3779static void intel_pebs_aliases_skl(struct perf_event *event)
3780{
3781 if (event->attr.precise_ip < 3)
3782 return intel_pebs_aliases_core2(event);
3783 return intel_pebs_aliases_precdist(event);
3784}
3785
3786static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3787{
3788 unsigned long flags = x86_pmu.large_pebs_flags;
3789
3790 if (event->attr.use_clockid)
3791 flags &= ~PERF_SAMPLE_TIME;
3792 if (!event->attr.exclude_kernel)
3793 flags &= ~PERF_SAMPLE_REGS_USER;
3794 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3795 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3796 return flags;
3797}
3798
3799static int intel_pmu_bts_config(struct perf_event *event)
3800{
3801 struct perf_event_attr *attr = &event->attr;
3802
3803 if (unlikely(intel_pmu_has_bts(event))) {
3804 /* BTS is not supported by this architecture. */
3805 if (!x86_pmu.bts_active)
3806 return -EOPNOTSUPP;
3807
3808 /* BTS is currently only allowed for user-mode. */
3809 if (!attr->exclude_kernel)
3810 return -EOPNOTSUPP;
3811
3812 /* BTS is not allowed for precise events. */
3813 if (attr->precise_ip)
3814 return -EOPNOTSUPP;
3815
3816 /* disallow bts if conflicting events are present */
3817 if (x86_add_exclusive(what: x86_lbr_exclusive_lbr))
3818 return -EBUSY;
3819
3820 event->destroy = hw_perf_lbr_event_destroy;
3821 }
3822
3823 return 0;
3824}
3825
3826static int core_pmu_hw_config(struct perf_event *event)
3827{
3828 int ret = x86_pmu_hw_config(event);
3829
3830 if (ret)
3831 return ret;
3832
3833 return intel_pmu_bts_config(event);
3834}
3835
3836#define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3837 ((x86_pmu.num_topdown_events - 1) << 8))
3838
3839static bool is_available_metric_event(struct perf_event *event)
3840{
3841 return is_metric_event(event) &&
3842 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3843}
3844
3845static inline bool is_mem_loads_event(struct perf_event *event)
3846{
3847 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3848}
3849
3850static inline bool is_mem_loads_aux_event(struct perf_event *event)
3851{
3852 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3853}
3854
3855static inline bool require_mem_loads_aux_event(struct perf_event *event)
3856{
3857 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3858 return false;
3859
3860 if (is_hybrid())
3861 return hybrid_pmu(pmu: event->pmu)->pmu_type == hybrid_big;
3862
3863 return true;
3864}
3865
3866static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3867{
3868 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3869
3870 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3871}
3872
3873static int intel_pmu_hw_config(struct perf_event *event)
3874{
3875 int ret = x86_pmu_hw_config(event);
3876
3877 if (ret)
3878 return ret;
3879
3880 ret = intel_pmu_bts_config(event);
3881 if (ret)
3882 return ret;
3883
3884 if (event->attr.precise_ip) {
3885 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3886 return -EINVAL;
3887
3888 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3889 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3890 if (!(event->attr.sample_type &
3891 ~intel_pmu_large_pebs_flags(event))) {
3892 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3893 event->attach_state |= PERF_ATTACH_SCHED_CB;
3894 }
3895 }
3896 if (x86_pmu.pebs_aliases)
3897 x86_pmu.pebs_aliases(event);
3898 }
3899
3900 if (needs_branch_stack(event)) {
3901 ret = intel_pmu_setup_lbr_filter(event);
3902 if (ret)
3903 return ret;
3904 event->attach_state |= PERF_ATTACH_SCHED_CB;
3905
3906 /*
3907 * BTS is set up earlier in this path, so don't account twice
3908 */
3909 if (!unlikely(intel_pmu_has_bts(event))) {
3910 /* disallow lbr if conflicting events are present */
3911 if (x86_add_exclusive(what: x86_lbr_exclusive_lbr))
3912 return -EBUSY;
3913
3914 event->destroy = hw_perf_lbr_event_destroy;
3915 }
3916 }
3917
3918 if (event->attr.aux_output) {
3919 if (!event->attr.precise_ip)
3920 return -EINVAL;
3921
3922 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3923 }
3924
3925 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
3926 (event->attr.type == PERF_TYPE_HW_CACHE))
3927 return 0;
3928
3929 /*
3930 * Config Topdown slots and metric events
3931 *
3932 * The slots event on Fixed Counter 3 can support sampling,
3933 * which will be handled normally in x86_perf_event_update().
3934 *
3935 * Metric events don't support sampling and require being paired
3936 * with a slots event as group leader. When the slots event
3937 * is used in a metrics group, it too cannot support sampling.
3938 */
3939 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3940 if (event->attr.config1 || event->attr.config2)
3941 return -EINVAL;
3942
3943 /*
3944 * The TopDown metrics events and slots event don't
3945 * support any filters.
3946 */
3947 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3948 return -EINVAL;
3949
3950 if (is_available_metric_event(event)) {
3951 struct perf_event *leader = event->group_leader;
3952
3953 /* The metric events don't support sampling. */
3954 if (is_sampling_event(event))
3955 return -EINVAL;
3956
3957 /* The metric events require a slots group leader. */
3958 if (!is_slots_event(event: leader))
3959 return -EINVAL;
3960
3961 /*
3962 * The leader/SLOTS must not be a sampling event for
3963 * metric use; hardware requires it starts at 0 when used
3964 * in conjunction with MSR_PERF_METRICS.
3965 */
3966 if (is_sampling_event(event: leader))
3967 return -EINVAL;
3968
3969 event->event_caps |= PERF_EV_CAP_SIBLING;
3970 /*
3971 * Only once we have a METRICs sibling do we
3972 * need TopDown magic.
3973 */
3974 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3975 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3976 }
3977 }
3978
3979 /*
3980 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3981 * doesn't function quite right. As a work-around it needs to always be
3982 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3983 * The actual count of this second event is irrelevant it just needs
3984 * to be active to make the first event function correctly.
3985 *
3986 * In a group, the auxiliary event must be in front of the load latency
3987 * event. The rule is to simplify the implementation of the check.
3988 * That's because perf cannot have a complete group at the moment.
3989 */
3990 if (require_mem_loads_aux_event(event) &&
3991 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3992 is_mem_loads_event(event)) {
3993 struct perf_event *leader = event->group_leader;
3994 struct perf_event *sibling = NULL;
3995
3996 /*
3997 * When this memload event is also the first event (no group
3998 * exists yet), then there is no aux event before it.
3999 */
4000 if (leader == event)
4001 return -ENODATA;
4002
4003 if (!is_mem_loads_aux_event(event: leader)) {
4004 for_each_sibling_event(sibling, leader) {
4005 if (is_mem_loads_aux_event(event: sibling))
4006 break;
4007 }
4008 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
4009 return -ENODATA;
4010 }
4011 }
4012
4013 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
4014 return 0;
4015
4016 if (x86_pmu.version < 3)
4017 return -EINVAL;
4018
4019 ret = perf_allow_cpu(attr: &event->attr);
4020 if (ret)
4021 return ret;
4022
4023 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
4024
4025 return 0;
4026}
4027
4028/*
4029 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4030 * The host perf conext helps to prepare the values of the real hardware for
4031 * a set of msrs that need to be switched atomically in a vmx transaction.
4032 *
4033 * For example, the pseudocode needed to add a new msr should look like:
4034 *
4035 * arr[(*nr)++] = (struct perf_guest_switch_msr){
4036 * .msr = the hardware msr address,
4037 * .host = the value the hardware has when it doesn't run a guest,
4038 * .guest = the value the hardware has when it runs a guest,
4039 * };
4040 *
4041 * These values have nothing to do with the emulated values the guest sees
4042 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4043 * specifically in the intel_pmu_{get,set}_msr().
4044 */
4045static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4046{
4047 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4048 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4049 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4050 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4051 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4052 int global_ctrl, pebs_enable;
4053
4054 *nr = 0;
4055 global_ctrl = (*nr)++;
4056 arr[global_ctrl] = (struct perf_guest_switch_msr){
4057 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4058 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4059 .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),
4060 };
4061
4062 if (!x86_pmu.pebs)
4063 return arr;
4064
4065 /*
4066 * If PMU counter has PEBS enabled it is not enough to
4067 * disable counter on a guest entry since PEBS memory
4068 * write can overshoot guest entry and corrupt guest
4069 * memory. Disabling PEBS solves the problem.
4070 *
4071 * Don't do this if the CPU already enforces it.
4072 */
4073 if (x86_pmu.pebs_no_isolation) {
4074 arr[(*nr)++] = (struct perf_guest_switch_msr){
4075 .msr = MSR_IA32_PEBS_ENABLE,
4076 .host = cpuc->pebs_enabled,
4077 .guest = 0,
4078 };
4079 return arr;
4080 }
4081
4082 if (!kvm_pmu || !x86_pmu.pebs_ept)
4083 return arr;
4084
4085 arr[(*nr)++] = (struct perf_guest_switch_msr){
4086 .msr = MSR_IA32_DS_AREA,
4087 .host = (unsigned long)cpuc->ds,
4088 .guest = kvm_pmu->ds_area,
4089 };
4090
4091 if (x86_pmu.intel_cap.pebs_baseline) {
4092 arr[(*nr)++] = (struct perf_guest_switch_msr){
4093 .msr = MSR_PEBS_DATA_CFG,
4094 .host = cpuc->active_pebs_data_cfg,
4095 .guest = kvm_pmu->pebs_data_cfg,
4096 };
4097 }
4098
4099 pebs_enable = (*nr)++;
4100 arr[pebs_enable] = (struct perf_guest_switch_msr){
4101 .msr = MSR_IA32_PEBS_ENABLE,
4102 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4103 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
4104 };
4105
4106 if (arr[pebs_enable].host) {
4107 /* Disable guest PEBS if host PEBS is enabled. */
4108 arr[pebs_enable].guest = 0;
4109 } else {
4110 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4111 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4112 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4113 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4114 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4115 }
4116
4117 return arr;
4118}
4119
4120static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4121{
4122 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4123 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4124 int idx;
4125
4126 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4127 struct perf_event *event = cpuc->events[idx];
4128
4129 arr[idx].msr = x86_pmu_config_addr(index: idx);
4130 arr[idx].host = arr[idx].guest = 0;
4131
4132 if (!test_bit(idx, cpuc->active_mask))
4133 continue;
4134
4135 arr[idx].host = arr[idx].guest =
4136 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4137
4138 if (event->attr.exclude_host)
4139 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4140 else if (event->attr.exclude_guest)
4141 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4142 }
4143
4144 *nr = x86_pmu.num_counters;
4145 return arr;
4146}
4147
4148static void core_pmu_enable_event(struct perf_event *event)
4149{
4150 if (!event->attr.exclude_host)
4151 x86_pmu_enable_event(event);
4152}
4153
4154static void core_pmu_enable_all(int added)
4155{
4156 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4157 int idx;
4158
4159 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4160 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4161
4162 if (!test_bit(idx, cpuc->active_mask) ||
4163 cpuc->events[idx]->attr.exclude_host)
4164 continue;
4165
4166 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4167 }
4168}
4169
4170static int hsw_hw_config(struct perf_event *event)
4171{
4172 int ret = intel_pmu_hw_config(event);
4173
4174 if (ret)
4175 return ret;
4176 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4177 return 0;
4178 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4179
4180 /*
4181 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4182 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4183 * this combination.
4184 */
4185 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4186 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4187 event->attr.precise_ip > 0))
4188 return -EOPNOTSUPP;
4189
4190 if (event_is_checkpointed(event)) {
4191 /*
4192 * Sampling of checkpointed events can cause situations where
4193 * the CPU constantly aborts because of a overflow, which is
4194 * then checkpointed back and ignored. Forbid checkpointing
4195 * for sampling.
4196 *
4197 * But still allow a long sampling period, so that perf stat
4198 * from KVM works.
4199 */
4200 if (event->attr.sample_period > 0 &&
4201 event->attr.sample_period < 0x7fffffff)
4202 return -EOPNOTSUPP;
4203 }
4204 return 0;
4205}
4206
4207static struct event_constraint counter0_constraint =
4208 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4209
4210static struct event_constraint counter1_constraint =
4211 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
4212
4213static struct event_constraint counter0_1_constraint =
4214 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
4215
4216static struct event_constraint counter2_constraint =
4217 EVENT_CONSTRAINT(0, 0x4, 0);
4218
4219static struct event_constraint fixed0_constraint =
4220 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4221
4222static struct event_constraint fixed0_counter0_constraint =
4223 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4224
4225static struct event_constraint fixed0_counter0_1_constraint =
4226 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
4227
4228static struct event_constraint counters_1_7_constraint =
4229 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
4230
4231static struct event_constraint *
4232hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4233 struct perf_event *event)
4234{
4235 struct event_constraint *c;
4236
4237 c = intel_get_event_constraints(cpuc, idx, event);
4238
4239 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4240 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4241 if (c->idxmsk64 & (1U << 2))
4242 return &counter2_constraint;
4243 return &emptyconstraint;
4244 }
4245
4246 return c;
4247}
4248
4249static struct event_constraint *
4250icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4251 struct perf_event *event)
4252{
4253 /*
4254 * Fixed counter 0 has less skid.
4255 * Force instruction:ppp in Fixed counter 0
4256 */
4257 if ((event->attr.precise_ip == 3) &&
4258 constraint_match(c: &fixed0_constraint, ecode: event->hw.config))
4259 return &fixed0_constraint;
4260
4261 return hsw_get_event_constraints(cpuc, idx, event);
4262}
4263
4264static struct event_constraint *
4265glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4266 struct perf_event *event)
4267{
4268 struct event_constraint *c;
4269
4270 c = icl_get_event_constraints(cpuc, idx, event);
4271
4272 /*
4273 * The :ppp indicates the Precise Distribution (PDist) facility, which
4274 * is only supported on the GP counter 0. If a :ppp event which is not
4275 * available on the GP counter 0, error out.
4276 * Exception: Instruction PDIR is only available on the fixed counter 0.
4277 */
4278 if ((event->attr.precise_ip == 3) &&
4279 !constraint_match(c: &fixed0_constraint, ecode: event->hw.config)) {
4280 if (c->idxmsk64 & BIT_ULL(0))
4281 return &counter0_constraint;
4282
4283 return &emptyconstraint;
4284 }
4285
4286 return c;
4287}
4288
4289static struct event_constraint *
4290glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4291 struct perf_event *event)
4292{
4293 struct event_constraint *c;
4294
4295 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4296 if (event->attr.precise_ip == 3)
4297 return &counter0_constraint;
4298
4299 c = intel_get_event_constraints(cpuc, idx, event);
4300
4301 return c;
4302}
4303
4304static struct event_constraint *
4305tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4306 struct perf_event *event)
4307{
4308 struct event_constraint *c;
4309
4310 c = intel_get_event_constraints(cpuc, idx, event);
4311
4312 /*
4313 * :ppp means to do reduced skid PEBS,
4314 * which is available on PMC0 and fixed counter 0.
4315 */
4316 if (event->attr.precise_ip == 3) {
4317 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4318 if (constraint_match(c: &fixed0_constraint, ecode: event->hw.config))
4319 return &fixed0_counter0_constraint;
4320
4321 return &counter0_constraint;
4322 }
4323
4324 return c;
4325}
4326
4327static bool allow_tsx_force_abort = true;
4328
4329static struct event_constraint *
4330tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4331 struct perf_event *event)
4332{
4333 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4334
4335 /*
4336 * Without TFA we must not use PMC3.
4337 */
4338 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4339 c = dyn_constraint(cpuc, c, idx);
4340 c->idxmsk64 &= ~(1ULL << 3);
4341 c->weight--;
4342 }
4343
4344 return c;
4345}
4346
4347static struct event_constraint *
4348adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4349 struct perf_event *event)
4350{
4351 struct x86_hybrid_pmu *pmu = hybrid_pmu(pmu: event->pmu);
4352
4353 if (pmu->pmu_type == hybrid_big)
4354 return glc_get_event_constraints(cpuc, idx, event);
4355 else if (pmu->pmu_type == hybrid_small)
4356 return tnt_get_event_constraints(cpuc, idx, event);
4357
4358 WARN_ON(1);
4359 return &emptyconstraint;
4360}
4361
4362static struct event_constraint *
4363cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4364 struct perf_event *event)
4365{
4366 struct event_constraint *c;
4367
4368 c = intel_get_event_constraints(cpuc, idx, event);
4369
4370 /*
4371 * The :ppp indicates the Precise Distribution (PDist) facility, which
4372 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
4373 * If a :ppp event which is not available on the above eligible counters,
4374 * error out.
4375 */
4376 if (event->attr.precise_ip == 3) {
4377 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
4378 if (constraint_match(c: &fixed0_constraint, ecode: event->hw.config))
4379 return &fixed0_counter0_1_constraint;
4380
4381 switch (c->idxmsk64 & 0x3ull) {
4382 case 0x1:
4383 return &counter0_constraint;
4384 case 0x2:
4385 return &counter1_constraint;
4386 case 0x3:
4387 return &counter0_1_constraint;
4388 }
4389 return &emptyconstraint;
4390 }
4391
4392 return c;
4393}
4394
4395static struct event_constraint *
4396rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4397 struct perf_event *event)
4398{
4399 struct event_constraint *c;
4400
4401 c = glc_get_event_constraints(cpuc, idx, event);
4402
4403 /* The Retire Latency is not supported by the fixed counter 0. */
4404 if (event->attr.precise_ip &&
4405 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
4406 constraint_match(c: &fixed0_constraint, ecode: event->hw.config)) {
4407 /*
4408 * The Instruction PDIR is only available
4409 * on the fixed counter 0. Error out for this case.
4410 */
4411 if (event->attr.precise_ip == 3)
4412 return &emptyconstraint;
4413 return &counters_1_7_constraint;
4414 }
4415
4416 return c;
4417}
4418
4419static struct event_constraint *
4420mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4421 struct perf_event *event)
4422{
4423 struct x86_hybrid_pmu *pmu = hybrid_pmu(pmu: event->pmu);
4424
4425 if (pmu->pmu_type == hybrid_big)
4426 return rwc_get_event_constraints(cpuc, idx, event);
4427 if (pmu->pmu_type == hybrid_small)
4428 return cmt_get_event_constraints(cpuc, idx, event);
4429
4430 WARN_ON(1);
4431 return &emptyconstraint;
4432}
4433
4434static int adl_hw_config(struct perf_event *event)
4435{
4436 struct x86_hybrid_pmu *pmu = hybrid_pmu(pmu: event->pmu);
4437
4438 if (pmu->pmu_type == hybrid_big)
4439 return hsw_hw_config(event);
4440 else if (pmu->pmu_type == hybrid_small)
4441 return intel_pmu_hw_config(event);
4442
4443 WARN_ON(1);
4444 return -EOPNOTSUPP;
4445}
4446
4447static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
4448{
4449 return HYBRID_INTEL_CORE;
4450}
4451
4452/*
4453 * Broadwell:
4454 *
4455 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4456 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4457 * the two to enforce a minimum period of 128 (the smallest value that has bits
4458 * 0-5 cleared and >= 100).
4459 *
4460 * Because of how the code in x86_perf_event_set_period() works, the truncation
4461 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4462 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4463 *
4464 * Therefore the effective (average) period matches the requested period,
4465 * despite coarser hardware granularity.
4466 */
4467static void bdw_limit_period(struct perf_event *event, s64 *left)
4468{
4469 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4470 X86_CONFIG(.event=0xc0, .umask=0x01)) {
4471 if (*left < 128)
4472 *left = 128;
4473 *left &= ~0x3fULL;
4474 }
4475}
4476
4477static void nhm_limit_period(struct perf_event *event, s64 *left)
4478{
4479 *left = max(*left, 32LL);
4480}
4481
4482static void glc_limit_period(struct perf_event *event, s64 *left)
4483{
4484 if (event->attr.precise_ip == 3)
4485 *left = max(*left, 128LL);
4486}
4487
4488PMU_FORMAT_ATTR(event, "config:0-7" );
4489PMU_FORMAT_ATTR(umask, "config:8-15" );
4490PMU_FORMAT_ATTR(edge, "config:18" );
4491PMU_FORMAT_ATTR(pc, "config:19" );
4492PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4493PMU_FORMAT_ATTR(inv, "config:23" );
4494PMU_FORMAT_ATTR(cmask, "config:24-31" );
4495PMU_FORMAT_ATTR(in_tx, "config:32");
4496PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4497
4498static struct attribute *intel_arch_formats_attr[] = {
4499 &format_attr_event.attr,
4500 &format_attr_umask.attr,
4501 &format_attr_edge.attr,
4502 &format_attr_pc.attr,
4503 &format_attr_inv.attr,
4504 &format_attr_cmask.attr,
4505 NULL,
4506};
4507
4508ssize_t intel_event_sysfs_show(char *page, u64 config)
4509{
4510 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4511
4512 return x86_event_sysfs_show(page, config, event);
4513}
4514
4515static struct intel_shared_regs *allocate_shared_regs(int cpu)
4516{
4517 struct intel_shared_regs *regs;
4518 int i;
4519
4520 regs = kzalloc_node(size: sizeof(struct intel_shared_regs),
4521 GFP_KERNEL, cpu_to_node(cpu));
4522 if (regs) {
4523 /*
4524 * initialize the locks to keep lockdep happy
4525 */
4526 for (i = 0; i < EXTRA_REG_MAX; i++)
4527 raw_spin_lock_init(&regs->regs[i].lock);
4528
4529 regs->core_id = -1;
4530 }
4531 return regs;
4532}
4533
4534static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4535{
4536 struct intel_excl_cntrs *c;
4537
4538 c = kzalloc_node(size: sizeof(struct intel_excl_cntrs),
4539 GFP_KERNEL, cpu_to_node(cpu));
4540 if (c) {
4541 raw_spin_lock_init(&c->lock);
4542 c->core_id = -1;
4543 }
4544 return c;
4545}
4546
4547
4548int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4549{
4550 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4551
4552 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4553 cpuc->shared_regs = allocate_shared_regs(cpu);
4554 if (!cpuc->shared_regs)
4555 goto err;
4556 }
4557
4558 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4559 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4560
4561 cpuc->constraint_list = kzalloc_node(size: sz, GFP_KERNEL, cpu_to_node(cpu));
4562 if (!cpuc->constraint_list)
4563 goto err_shared_regs;
4564 }
4565
4566 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4567 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4568 if (!cpuc->excl_cntrs)
4569 goto err_constraint_list;
4570
4571 cpuc->excl_thread_id = 0;
4572 }
4573
4574 return 0;
4575
4576err_constraint_list:
4577 kfree(objp: cpuc->constraint_list);
4578 cpuc->constraint_list = NULL;
4579
4580err_shared_regs:
4581 kfree(objp: cpuc->shared_regs);
4582 cpuc->shared_regs = NULL;
4583
4584err:
4585 return -ENOMEM;
4586}
4587
4588static int intel_pmu_cpu_prepare(int cpu)
4589{
4590 return intel_cpuc_prepare(cpuc: &per_cpu(cpu_hw_events, cpu), cpu);
4591}
4592
4593static void flip_smm_bit(void *data)
4594{
4595 unsigned long set = *(unsigned long *)data;
4596
4597 if (set > 0) {
4598 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4599 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4600 } else {
4601 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4602 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4603 }
4604}
4605
4606static void intel_pmu_check_num_counters(int *num_counters,
4607 int *num_counters_fixed,
4608 u64 *intel_ctrl, u64 fixed_mask);
4609
4610static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
4611 int num_counters,
4612 int num_counters_fixed,
4613 u64 intel_ctrl);
4614
4615static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
4616
4617static inline bool intel_pmu_broken_perf_cap(void)
4618{
4619 /* The Perf Metric (Bit 15) is always cleared */
4620 if ((boot_cpu_data.x86_model == INTEL_FAM6_METEORLAKE) ||
4621 (boot_cpu_data.x86_model == INTEL_FAM6_METEORLAKE_L))
4622 return true;
4623
4624 return false;
4625}
4626
4627static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
4628{
4629 unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF);
4630 unsigned int eax, ebx, ecx, edx;
4631
4632 if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
4633 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
4634 eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
4635 pmu->num_counters = fls(x: eax);
4636 pmu->num_counters_fixed = fls(x: ebx);
4637 }
4638
4639
4640 if (!intel_pmu_broken_perf_cap()) {
4641 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
4642 rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities);
4643 }
4644}
4645
4646static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
4647{
4648 intel_pmu_check_num_counters(num_counters: &pmu->num_counters, num_counters_fixed: &pmu->num_counters_fixed,
4649 intel_ctrl: &pmu->intel_ctrl, fixed_mask: (1ULL << pmu->num_counters_fixed) - 1);
4650 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
4651 pmu->unconstrained = (struct event_constraint)
4652 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
4653 0, pmu->num_counters, 0, 0);
4654
4655 if (pmu->intel_cap.perf_metrics)
4656 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
4657 else
4658 pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4659
4660 if (pmu->intel_cap.pebs_output_pt_available)
4661 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
4662 else
4663 pmu->pmu.capabilities |= ~PERF_PMU_CAP_AUX_OUTPUT;
4664
4665 intel_pmu_check_event_constraints(event_constraints: pmu->event_constraints,
4666 num_counters: pmu->num_counters,
4667 num_counters_fixed: pmu->num_counters_fixed,
4668 intel_ctrl: pmu->intel_ctrl);
4669
4670 intel_pmu_check_extra_regs(extra_regs: pmu->extra_regs);
4671}
4672
4673static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
4674{
4675 u8 cpu_type = get_this_hybrid_cpu_type();
4676 int i;
4677
4678 /*
4679 * This is running on a CPU model that is known to have hybrid
4680 * configurations. But the CPU told us it is not hybrid, shame
4681 * on it. There should be a fixup function provided for these
4682 * troublesome CPUs (->get_hybrid_cpu_type).
4683 */
4684 if (cpu_type == HYBRID_INTEL_NONE) {
4685 if (x86_pmu.get_hybrid_cpu_type)
4686 cpu_type = x86_pmu.get_hybrid_cpu_type();
4687 else
4688 return NULL;
4689 }
4690
4691 /*
4692 * This essentially just maps between the 'hybrid_cpu_type'
4693 * and 'hybrid_pmu_type' enums:
4694 */
4695 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4696 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
4697
4698 if (cpu_type == HYBRID_INTEL_CORE &&
4699 pmu_type == hybrid_big)
4700 return &x86_pmu.hybrid_pmu[i];
4701 if (cpu_type == HYBRID_INTEL_ATOM &&
4702 pmu_type == hybrid_small)
4703 return &x86_pmu.hybrid_pmu[i];
4704 }
4705
4706 return NULL;
4707}
4708
4709static bool init_hybrid_pmu(int cpu)
4710{
4711 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4712 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
4713
4714 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
4715 cpuc->pmu = NULL;
4716 return false;
4717 }
4718
4719 /* Only check and dump the PMU information for the first CPU */
4720 if (!cpumask_empty(srcp: &pmu->supported_cpus))
4721 goto end;
4722
4723 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
4724 update_pmu_cap(pmu);
4725
4726 intel_pmu_check_hybrid_pmus(pmu);
4727
4728 if (!check_hw_exists(pmu: &pmu->pmu, num_counters: pmu->num_counters, num_counters_fixed: pmu->num_counters_fixed))
4729 return false;
4730
4731 pr_info("%s PMU driver: ", pmu->name);
4732
4733 if (pmu->intel_cap.pebs_output_pt_available)
4734 pr_cont("PEBS-via-PT ");
4735
4736 pr_cont("\n");
4737
4738 x86_pmu_show_pmu_cap(num_counters: pmu->num_counters, num_counters_fixed: pmu->num_counters_fixed,
4739 intel_ctrl: pmu->intel_ctrl);
4740
4741end:
4742 cpumask_set_cpu(cpu, dstp: &pmu->supported_cpus);
4743 cpuc->pmu = &pmu->pmu;
4744
4745 return true;
4746}
4747
4748static void intel_pmu_cpu_starting(int cpu)
4749{
4750 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4751 int core_id = topology_core_id(cpu);
4752 int i;
4753
4754 if (is_hybrid() && !init_hybrid_pmu(cpu))
4755 return;
4756
4757 init_debug_store_on_cpu(cpu);
4758 /*
4759 * Deal with CPUs that don't clear their LBRs on power-up.
4760 */
4761 intel_pmu_lbr_reset();
4762
4763 cpuc->lbr_sel = NULL;
4764
4765 if (x86_pmu.flags & PMU_FL_TFA) {
4766 WARN_ON_ONCE(cpuc->tfa_shadow);
4767 cpuc->tfa_shadow = ~0ULL;
4768 intel_set_tfa(cpuc, on: false);
4769 }
4770
4771 if (x86_pmu.version > 1)
4772 flip_smm_bit(data: &x86_pmu.attr_freeze_on_smi);
4773
4774 /*
4775 * Disable perf metrics if any added CPU doesn't support it.
4776 *
4777 * Turn off the check for a hybrid architecture, because the
4778 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4779 * the architecture features. The perf metrics is a model-specific
4780 * feature for now. The corresponding bit should always be 0 on
4781 * a hybrid platform, e.g., Alder Lake.
4782 */
4783 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4784 union perf_capabilities perf_cap;
4785
4786 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4787 if (!perf_cap.perf_metrics) {
4788 x86_pmu.intel_cap.perf_metrics = 0;
4789 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4790 }
4791 }
4792
4793 if (!cpuc->shared_regs)
4794 return;
4795
4796 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4797 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4798 struct intel_shared_regs *pc;
4799
4800 pc = per_cpu(cpu_hw_events, i).shared_regs;
4801 if (pc && pc->core_id == core_id) {
4802 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4803 cpuc->shared_regs = pc;
4804 break;
4805 }
4806 }
4807 cpuc->shared_regs->core_id = core_id;
4808 cpuc->shared_regs->refcnt++;
4809 }
4810
4811 if (x86_pmu.lbr_sel_map)
4812 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4813
4814 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4815 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4816 struct cpu_hw_events *sibling;
4817 struct intel_excl_cntrs *c;
4818
4819 sibling = &per_cpu(cpu_hw_events, i);
4820 c = sibling->excl_cntrs;
4821 if (c && c->core_id == core_id) {
4822 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4823 cpuc->excl_cntrs = c;
4824 if (!sibling->excl_thread_id)
4825 cpuc->excl_thread_id = 1;
4826 break;
4827 }
4828 }
4829 cpuc->excl_cntrs->core_id = core_id;
4830 cpuc->excl_cntrs->refcnt++;
4831 }
4832}
4833
4834static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4835{
4836 struct intel_excl_cntrs *c;
4837
4838 c = cpuc->excl_cntrs;
4839 if (c) {
4840 if (c->core_id == -1 || --c->refcnt == 0)
4841 kfree(objp: c);
4842 cpuc->excl_cntrs = NULL;
4843 }
4844
4845 kfree(objp: cpuc->constraint_list);
4846 cpuc->constraint_list = NULL;
4847}
4848
4849static void intel_pmu_cpu_dying(int cpu)
4850{
4851 fini_debug_store_on_cpu(cpu);
4852}
4853
4854void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4855{
4856 struct intel_shared_regs *pc;
4857
4858 pc = cpuc->shared_regs;
4859 if (pc) {
4860 if (pc->core_id == -1 || --pc->refcnt == 0)
4861 kfree(objp: pc);
4862 cpuc->shared_regs = NULL;
4863 }
4864
4865 free_excl_cntrs(cpuc);
4866}
4867
4868static void intel_pmu_cpu_dead(int cpu)
4869{
4870 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4871
4872 intel_cpuc_finish(cpuc);
4873
4874 if (is_hybrid() && cpuc->pmu)
4875 cpumask_clear_cpu(cpu, dstp: &hybrid_pmu(pmu: cpuc->pmu)->supported_cpus);
4876}
4877
4878static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
4879 bool sched_in)
4880{
4881 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
4882 intel_pmu_lbr_sched_task(pmu_ctx, sched_in);
4883}
4884
4885static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
4886 struct perf_event_pmu_context *next_epc)
4887{
4888 intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
4889}
4890
4891static int intel_pmu_check_period(struct perf_event *event, u64 value)
4892{
4893 return intel_pmu_has_bts_period(event, period: value) ? -EINVAL : 0;
4894}
4895
4896static void intel_aux_output_init(void)
4897{
4898 /* Refer also intel_pmu_aux_output_match() */
4899 if (x86_pmu.intel_cap.pebs_output_pt_available)
4900 x86_pmu.assign = intel_pmu_assign_event;
4901}
4902
4903static int intel_pmu_aux_output_match(struct perf_event *event)
4904{
4905 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
4906 if (!x86_pmu.intel_cap.pebs_output_pt_available)
4907 return 0;
4908
4909 return is_intel_pt_event(event);
4910}
4911
4912static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
4913{
4914 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
4915
4916 *ret = !cpumask_test_cpu(cpu, cpumask: &hpmu->supported_cpus);
4917}
4918
4919PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4920
4921PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4922
4923PMU_FORMAT_ATTR(frontend, "config1:0-23");
4924
4925PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
4926
4927static struct attribute *intel_arch3_formats_attr[] = {
4928 &format_attr_event.attr,
4929 &format_attr_umask.attr,
4930 &format_attr_edge.attr,
4931 &format_attr_pc.attr,
4932 &format_attr_any.attr,
4933 &format_attr_inv.attr,
4934 &format_attr_cmask.attr,
4935 NULL,
4936};
4937
4938static struct attribute *hsw_format_attr[] = {
4939 &format_attr_in_tx.attr,
4940 &format_attr_in_tx_cp.attr,
4941 &format_attr_offcore_rsp.attr,
4942 &format_attr_ldlat.attr,
4943 NULL
4944};
4945
4946static struct attribute *nhm_format_attr[] = {
4947 &format_attr_offcore_rsp.attr,
4948 &format_attr_ldlat.attr,
4949 NULL
4950};
4951
4952static struct attribute *slm_format_attr[] = {
4953 &format_attr_offcore_rsp.attr,
4954 NULL
4955};
4956
4957static struct attribute *cmt_format_attr[] = {
4958 &format_attr_offcore_rsp.attr,
4959 &format_attr_ldlat.attr,
4960 &format_attr_snoop_rsp.attr,
4961 NULL
4962};
4963
4964static struct attribute *skl_format_attr[] = {
4965 &format_attr_frontend.attr,
4966 NULL,
4967};
4968
4969static __initconst const struct x86_pmu core_pmu = {
4970 .name = "core",
4971 .handle_irq = x86_pmu_handle_irq,
4972 .disable_all = x86_pmu_disable_all,
4973 .enable_all = core_pmu_enable_all,
4974 .enable = core_pmu_enable_event,
4975 .disable = x86_pmu_disable_event,
4976 .hw_config = core_pmu_hw_config,
4977 .schedule_events = x86_schedule_events,
4978 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4979 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4980 .event_map = intel_pmu_event_map,
4981 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4982 .apic = 1,
4983 .large_pebs_flags = LARGE_PEBS_FLAGS,
4984
4985 /*
4986 * Intel PMCs cannot be accessed sanely above 32-bit width,
4987 * so we install an artificial 1<<31 period regardless of
4988 * the generic event period:
4989 */
4990 .max_period = (1ULL<<31) - 1,
4991 .get_event_constraints = intel_get_event_constraints,
4992 .put_event_constraints = intel_put_event_constraints,
4993 .event_constraints = intel_core_event_constraints,
4994 .guest_get_msrs = core_guest_get_msrs,
4995 .format_attrs = intel_arch_formats_attr,
4996 .events_sysfs_show = intel_event_sysfs_show,
4997
4998 /*
4999 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
5000 * together with PMU version 1 and thus be using core_pmu with
5001 * shared_regs. We need following callbacks here to allocate
5002 * it properly.
5003 */
5004 .cpu_prepare = intel_pmu_cpu_prepare,
5005 .cpu_starting = intel_pmu_cpu_starting,
5006 .cpu_dying = intel_pmu_cpu_dying,
5007 .cpu_dead = intel_pmu_cpu_dead,
5008
5009 .check_period = intel_pmu_check_period,
5010
5011 .lbr_reset = intel_pmu_lbr_reset_64,
5012 .lbr_read = intel_pmu_lbr_read_64,
5013 .lbr_save = intel_pmu_lbr_save,
5014 .lbr_restore = intel_pmu_lbr_restore,
5015};
5016
5017static __initconst const struct x86_pmu intel_pmu = {
5018 .name = "Intel",
5019 .handle_irq = intel_pmu_handle_irq,
5020 .disable_all = intel_pmu_disable_all,
5021 .enable_all = intel_pmu_enable_all,
5022 .enable = intel_pmu_enable_event,
5023 .disable = intel_pmu_disable_event,
5024 .add = intel_pmu_add_event,
5025 .del = intel_pmu_del_event,
5026 .read = intel_pmu_read_event,
5027 .set_period = intel_pmu_set_period,
5028 .update = intel_pmu_update,
5029 .hw_config = intel_pmu_hw_config,
5030 .schedule_events = x86_schedule_events,
5031 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5032 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
5033 .event_map = intel_pmu_event_map,
5034 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
5035 .apic = 1,
5036 .large_pebs_flags = LARGE_PEBS_FLAGS,
5037 /*
5038 * Intel PMCs cannot be accessed sanely above 32 bit width,
5039 * so we install an artificial 1<<31 period regardless of
5040 * the generic event period:
5041 */
5042 .max_period = (1ULL << 31) - 1,
5043 .get_event_constraints = intel_get_event_constraints,
5044 .put_event_constraints = intel_put_event_constraints,
5045 .pebs_aliases = intel_pebs_aliases_core2,
5046
5047 .format_attrs = intel_arch3_formats_attr,
5048 .events_sysfs_show = intel_event_sysfs_show,
5049
5050 .cpu_prepare = intel_pmu_cpu_prepare,
5051 .cpu_starting = intel_pmu_cpu_starting,
5052 .cpu_dying = intel_pmu_cpu_dying,
5053 .cpu_dead = intel_pmu_cpu_dead,
5054
5055 .guest_get_msrs = intel_guest_get_msrs,
5056 .sched_task = intel_pmu_sched_task,
5057 .swap_task_ctx = intel_pmu_swap_task_ctx,
5058
5059 .check_period = intel_pmu_check_period,
5060
5061 .aux_output_match = intel_pmu_aux_output_match,
5062
5063 .lbr_reset = intel_pmu_lbr_reset_64,
5064 .lbr_read = intel_pmu_lbr_read_64,
5065 .lbr_save = intel_pmu_lbr_save,
5066 .lbr_restore = intel_pmu_lbr_restore,
5067
5068 /*
5069 * SMM has access to all 4 rings and while traditionally SMM code only
5070 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
5071 *
5072 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
5073 * between SMM or not, this results in what should be pure userspace
5074 * counters including SMM data.
5075 *
5076 * This is a clear privilege issue, therefore globally disable
5077 * counting SMM by default.
5078 */
5079 .attr_freeze_on_smi = 1,
5080};
5081
5082static __init void intel_clovertown_quirk(void)
5083{
5084 /*
5085 * PEBS is unreliable due to:
5086 *
5087 * AJ67 - PEBS may experience CPL leaks
5088 * AJ68 - PEBS PMI may be delayed by one event
5089 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
5090 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
5091 *
5092 * AJ67 could be worked around by restricting the OS/USR flags.
5093 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
5094 *
5095 * AJ106 could possibly be worked around by not allowing LBR
5096 * usage from PEBS, including the fixup.
5097 * AJ68 could possibly be worked around by always programming
5098 * a pebs_event_reset[0] value and coping with the lost events.
5099 *
5100 * But taken together it might just make sense to not enable PEBS on
5101 * these chips.
5102 */
5103 pr_warn("PEBS disabled due to CPU errata\n");
5104 x86_pmu.pebs = 0;
5105 x86_pmu.pebs_constraints = NULL;
5106}
5107
5108static const struct x86_cpu_desc isolation_ucodes[] = {
5109 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
5110 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
5111 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
5112 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
5113 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
5114 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
5115 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
5116 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
5117 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
5118 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
5119 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
5120 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014),
5121 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
5122 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
5123 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000),
5124 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000),
5125 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000),
5126 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 11, 0x00000000),
5127 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
5128 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
5129 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
5130 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
5131 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
5132 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
5133 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
5134 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
5135 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
5136 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
5137 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
5138 {}
5139};
5140
5141static void intel_check_pebs_isolation(void)
5142{
5143 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(table: isolation_ucodes);
5144}
5145
5146static __init void intel_pebs_isolation_quirk(void)
5147{
5148 WARN_ON_ONCE(x86_pmu.check_microcode);
5149 x86_pmu.check_microcode = intel_check_pebs_isolation;
5150 intel_check_pebs_isolation();
5151}
5152
5153static const struct x86_cpu_desc pebs_ucodes[] = {
5154 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
5155 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
5156 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
5157 {}
5158};
5159
5160static bool intel_snb_pebs_broken(void)
5161{
5162 return !x86_cpu_has_min_microcode_rev(table: pebs_ucodes);
5163}
5164
5165static void intel_snb_check_microcode(void)
5166{
5167 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
5168 return;
5169
5170 /*
5171 * Serialized by the microcode lock..
5172 */
5173 if (x86_pmu.pebs_broken) {
5174 pr_info("PEBS enabled due to microcode update\n");
5175 x86_pmu.pebs_broken = 0;
5176 } else {
5177 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
5178 x86_pmu.pebs_broken = 1;
5179 }
5180}
5181
5182static bool is_lbr_from(unsigned long msr)
5183{
5184 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
5185
5186 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
5187}
5188
5189/*
5190 * Under certain circumstances, access certain MSR may cause #GP.
5191 * The function tests if the input MSR can be safely accessed.
5192 */
5193static bool check_msr(unsigned long msr, u64 mask)
5194{
5195 u64 val_old, val_new, val_tmp;
5196
5197 /*
5198 * Disable the check for real HW, so we don't
5199 * mess with potentially enabled registers:
5200 */
5201 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
5202 return true;
5203
5204 /*
5205 * Read the current value, change it and read it back to see if it
5206 * matches, this is needed to detect certain hardware emulators
5207 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
5208 */
5209 if (rdmsrl_safe(msr, p: &val_old))
5210 return false;
5211
5212 /*
5213 * Only change the bits which can be updated by wrmsrl.
5214 */
5215 val_tmp = val_old ^ mask;
5216
5217 if (is_lbr_from(msr))
5218 val_tmp = lbr_from_signext_quirk_wr(val: val_tmp);
5219
5220 if (wrmsrl_safe(msr, val: val_tmp) ||
5221 rdmsrl_safe(msr, p: &val_new))
5222 return false;
5223
5224 /*
5225 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5226 * should equal rdmsrl()'s even with the quirk.
5227 */
5228 if (val_new != val_tmp)
5229 return false;
5230
5231 if (is_lbr_from(msr))
5232 val_old = lbr_from_signext_quirk_wr(val: val_old);
5233
5234 /* Here it's sure that the MSR can be safely accessed.
5235 * Restore the old value and return.
5236 */
5237 wrmsrl(msr, val: val_old);
5238
5239 return true;
5240}
5241
5242static __init void intel_sandybridge_quirk(void)
5243{
5244 x86_pmu.check_microcode = intel_snb_check_microcode;
5245 cpus_read_lock();
5246 intel_snb_check_microcode();
5247 cpus_read_unlock();
5248}
5249
5250static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5251 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5252 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5253 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5254 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5255 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5256 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5257 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5258};
5259
5260static __init void intel_arch_events_quirk(void)
5261{
5262 int bit;
5263
5264 /* disable event that reported as not present by cpuid */
5265 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5266 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5267 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5268 intel_arch_events_map[bit].name);
5269 }
5270}
5271
5272static __init void intel_nehalem_quirk(void)
5273{
5274 union cpuid10_ebx ebx;
5275
5276 ebx.full = x86_pmu.events_maskl;
5277 if (ebx.split.no_branch_misses_retired) {
5278 /*
5279 * Erratum AAJ80 detected, we work it around by using
5280 * the BR_MISP_EXEC.ANY event. This will over-count
5281 * branch-misses, but it's still much better than the
5282 * architectural event which is often completely bogus:
5283 */
5284 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5285 ebx.split.no_branch_misses_retired = 0;
5286 x86_pmu.events_maskl = ebx.full;
5287 pr_info("CPU erratum AAJ80 worked around\n");
5288 }
5289}
5290
5291/*
5292 * enable software workaround for errata:
5293 * SNB: BJ122
5294 * IVB: BV98
5295 * HSW: HSD29
5296 *
5297 * Only needed when HT is enabled. However detecting
5298 * if HT is enabled is difficult (model specific). So instead,
5299 * we enable the workaround in the early boot, and verify if
5300 * it is needed in a later initcall phase once we have valid
5301 * topology information to check if HT is actually enabled
5302 */
5303static __init void intel_ht_bug(void)
5304{
5305 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5306
5307 x86_pmu.start_scheduling = intel_start_scheduling;
5308 x86_pmu.commit_scheduling = intel_commit_scheduling;
5309 x86_pmu.stop_scheduling = intel_stop_scheduling;
5310}
5311
5312EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
5313EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5314
5315/* Haswell special events */
5316EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
5317EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
5318EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
5319EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
5320EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
5321EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
5322EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
5323EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
5324EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
5325EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
5326EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
5327EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
5328
5329static struct attribute *hsw_events_attrs[] = {
5330 EVENT_PTR(td_slots_issued),
5331 EVENT_PTR(td_slots_retired),
5332 EVENT_PTR(td_fetch_bubbles),
5333 EVENT_PTR(td_total_slots),
5334 EVENT_PTR(td_total_slots_scale),
5335 EVENT_PTR(td_recovery_bubbles),
5336 EVENT_PTR(td_recovery_bubbles_scale),
5337 NULL
5338};
5339
5340static struct attribute *hsw_mem_events_attrs[] = {
5341 EVENT_PTR(mem_ld_hsw),
5342 EVENT_PTR(mem_st_hsw),
5343 NULL,
5344};
5345
5346static struct attribute *hsw_tsx_events_attrs[] = {
5347 EVENT_PTR(tx_start),
5348 EVENT_PTR(tx_commit),
5349 EVENT_PTR(tx_abort),
5350 EVENT_PTR(tx_capacity),
5351 EVENT_PTR(tx_conflict),
5352 EVENT_PTR(el_start),
5353 EVENT_PTR(el_commit),
5354 EVENT_PTR(el_abort),
5355 EVENT_PTR(el_capacity),
5356 EVENT_PTR(el_conflict),
5357 EVENT_PTR(cycles_t),
5358 EVENT_PTR(cycles_ct),
5359 NULL
5360};
5361
5362EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
5363EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5364EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
5365EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5366
5367static struct attribute *icl_events_attrs[] = {
5368 EVENT_PTR(mem_ld_hsw),
5369 EVENT_PTR(mem_st_hsw),
5370 NULL,
5371};
5372
5373static struct attribute *icl_td_events_attrs[] = {
5374 EVENT_PTR(slots),
5375 EVENT_PTR(td_retiring),
5376 EVENT_PTR(td_bad_spec),
5377 EVENT_PTR(td_fe_bound),
5378 EVENT_PTR(td_be_bound),
5379 NULL,
5380};
5381
5382static struct attribute *icl_tsx_events_attrs[] = {
5383 EVENT_PTR(tx_start),
5384 EVENT_PTR(tx_abort),
5385 EVENT_PTR(tx_commit),
5386 EVENT_PTR(tx_capacity_read),
5387 EVENT_PTR(tx_capacity_write),
5388 EVENT_PTR(tx_conflict),
5389 EVENT_PTR(el_start),
5390 EVENT_PTR(el_abort),
5391 EVENT_PTR(el_commit),
5392 EVENT_PTR(el_capacity_read),
5393 EVENT_PTR(el_capacity_write),
5394 EVENT_PTR(el_conflict),
5395 EVENT_PTR(cycles_t),
5396 EVENT_PTR(cycles_ct),
5397 NULL,
5398};
5399
5400
5401EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5402EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
5403
5404static struct attribute *glc_events_attrs[] = {
5405 EVENT_PTR(mem_ld_hsw),
5406 EVENT_PTR(mem_st_spr),
5407 EVENT_PTR(mem_ld_aux),
5408 NULL,
5409};
5410
5411static struct attribute *glc_td_events_attrs[] = {
5412 EVENT_PTR(slots),
5413 EVENT_PTR(td_retiring),
5414 EVENT_PTR(td_bad_spec),
5415 EVENT_PTR(td_fe_bound),
5416 EVENT_PTR(td_be_bound),
5417 EVENT_PTR(td_heavy_ops),
5418 EVENT_PTR(td_br_mispredict),
5419 EVENT_PTR(td_fetch_lat),
5420 EVENT_PTR(td_mem_bound),
5421 NULL,
5422};
5423
5424static struct attribute *glc_tsx_events_attrs[] = {
5425 EVENT_PTR(tx_start),
5426 EVENT_PTR(tx_abort),
5427 EVENT_PTR(tx_commit),
5428 EVENT_PTR(tx_capacity_read),
5429 EVENT_PTR(tx_capacity_write),
5430 EVENT_PTR(tx_conflict),
5431 EVENT_PTR(cycles_t),
5432 EVENT_PTR(cycles_ct),
5433 NULL,
5434};
5435
5436static ssize_t freeze_on_smi_show(struct device *cdev,
5437 struct device_attribute *attr,
5438 char *buf)
5439{
5440 return sprintf(buf, fmt: "%lu\n", x86_pmu.attr_freeze_on_smi);
5441}
5442
5443static DEFINE_MUTEX(freeze_on_smi_mutex);
5444
5445static ssize_t freeze_on_smi_store(struct device *cdev,
5446 struct device_attribute *attr,
5447 const char *buf, size_t count)
5448{
5449 unsigned long val;
5450 ssize_t ret;
5451
5452 ret = kstrtoul(s: buf, base: 0, res: &val);
5453 if (ret)
5454 return ret;
5455
5456 if (val > 1)
5457 return -EINVAL;
5458
5459 mutex_lock(&freeze_on_smi_mutex);
5460
5461 if (x86_pmu.attr_freeze_on_smi == val)
5462 goto done;
5463
5464 x86_pmu.attr_freeze_on_smi = val;
5465
5466 cpus_read_lock();
5467 on_each_cpu(func: flip_smm_bit, info: &val, wait: 1);
5468 cpus_read_unlock();
5469done:
5470 mutex_unlock(lock: &freeze_on_smi_mutex);
5471
5472 return count;
5473}
5474
5475static void update_tfa_sched(void *ignored)
5476{
5477 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5478
5479 /*
5480 * check if PMC3 is used
5481 * and if so force schedule out for all event types all contexts
5482 */
5483 if (test_bit(3, cpuc->active_mask))
5484 perf_pmu_resched(pmu: x86_get_pmu(smp_processor_id()));
5485}
5486
5487static ssize_t show_sysctl_tfa(struct device *cdev,
5488 struct device_attribute *attr,
5489 char *buf)
5490{
5491 return snprintf(buf, size: 40, fmt: "%d\n", allow_tsx_force_abort);
5492}
5493
5494static ssize_t set_sysctl_tfa(struct device *cdev,
5495 struct device_attribute *attr,
5496 const char *buf, size_t count)
5497{
5498 bool val;
5499 ssize_t ret;
5500
5501 ret = kstrtobool(s: buf, res: &val);
5502 if (ret)
5503 return ret;
5504
5505 /* no change */
5506 if (val == allow_tsx_force_abort)
5507 return count;
5508
5509 allow_tsx_force_abort = val;
5510
5511 cpus_read_lock();
5512 on_each_cpu(func: update_tfa_sched, NULL, wait: 1);
5513 cpus_read_unlock();
5514
5515 return count;
5516}
5517
5518
5519static DEVICE_ATTR_RW(freeze_on_smi);
5520
5521static ssize_t branches_show(struct device *cdev,
5522 struct device_attribute *attr,
5523 char *buf)
5524{
5525 return snprintf(buf, PAGE_SIZE, fmt: "%d\n", x86_pmu.lbr_nr);
5526}
5527
5528static DEVICE_ATTR_RO(branches);
5529
5530static struct attribute *lbr_attrs[] = {
5531 &dev_attr_branches.attr,
5532 NULL
5533};
5534
5535static char pmu_name_str[30];
5536
5537static ssize_t pmu_name_show(struct device *cdev,
5538 struct device_attribute *attr,
5539 char *buf)
5540{
5541 return snprintf(buf, PAGE_SIZE, fmt: "%s\n", pmu_name_str);
5542}
5543
5544static DEVICE_ATTR_RO(pmu_name);
5545
5546static struct attribute *intel_pmu_caps_attrs[] = {
5547 &dev_attr_pmu_name.attr,
5548 NULL
5549};
5550
5551static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5552 show_sysctl_tfa,
5553 set_sysctl_tfa);
5554
5555static struct attribute *intel_pmu_attrs[] = {
5556 &dev_attr_freeze_on_smi.attr,
5557 &dev_attr_allow_tsx_force_abort.attr,
5558 NULL,
5559};
5560
5561static umode_t
5562tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5563{
5564 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5565}
5566
5567static umode_t
5568pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5569{
5570 return x86_pmu.pebs ? attr->mode : 0;
5571}
5572
5573static umode_t
5574mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5575{
5576 if (attr == &event_attr_mem_ld_aux.attr.attr)
5577 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
5578
5579 return pebs_is_visible(kobj, attr, i);
5580}
5581
5582static umode_t
5583lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5584{
5585 return x86_pmu.lbr_nr ? attr->mode : 0;
5586}
5587
5588static umode_t
5589exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5590{
5591 return x86_pmu.version >= 2 ? attr->mode : 0;
5592}
5593
5594static umode_t
5595default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5596{
5597 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5598 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5599
5600 return attr->mode;
5601}
5602
5603static struct attribute_group group_events_td = {
5604 .name = "events",
5605};
5606
5607static struct attribute_group group_events_mem = {
5608 .name = "events",
5609 .is_visible = mem_is_visible,
5610};
5611
5612static struct attribute_group group_events_tsx = {
5613 .name = "events",
5614 .is_visible = tsx_is_visible,
5615};
5616
5617static struct attribute_group group_caps_gen = {
5618 .name = "caps",
5619 .attrs = intel_pmu_caps_attrs,
5620};
5621
5622static struct attribute_group group_caps_lbr = {
5623 .name = "caps",
5624 .attrs = lbr_attrs,
5625 .is_visible = lbr_is_visible,
5626};
5627
5628static struct attribute_group group_format_extra = {
5629 .name = "format",
5630 .is_visible = exra_is_visible,
5631};
5632
5633static struct attribute_group group_format_extra_skl = {
5634 .name = "format",
5635 .is_visible = exra_is_visible,
5636};
5637
5638static struct attribute_group group_default = {
5639 .attrs = intel_pmu_attrs,
5640 .is_visible = default_is_visible,
5641};
5642
5643static const struct attribute_group *attr_update[] = {
5644 &group_events_td,
5645 &group_events_mem,
5646 &group_events_tsx,
5647 &group_caps_gen,
5648 &group_caps_lbr,
5649 &group_format_extra,
5650 &group_format_extra_skl,
5651 &group_default,
5652 NULL,
5653};
5654
5655EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
5656EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5657EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5658EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5659EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5660EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
5661EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
5662EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
5663EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
5664
5665static struct attribute *adl_hybrid_events_attrs[] = {
5666 EVENT_PTR(slots_adl),
5667 EVENT_PTR(td_retiring_adl),
5668 EVENT_PTR(td_bad_spec_adl),
5669 EVENT_PTR(td_fe_bound_adl),
5670 EVENT_PTR(td_be_bound_adl),
5671 EVENT_PTR(td_heavy_ops_adl),
5672 EVENT_PTR(td_br_mis_adl),
5673 EVENT_PTR(td_fetch_lat_adl),
5674 EVENT_PTR(td_mem_bound_adl),
5675 NULL,
5676};
5677
5678/* Must be in IDX order */
5679EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
5680EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
5681EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
5682
5683static struct attribute *adl_hybrid_mem_attrs[] = {
5684 EVENT_PTR(mem_ld_adl),
5685 EVENT_PTR(mem_st_adl),
5686 EVENT_PTR(mem_ld_aux_adl),
5687 NULL,
5688};
5689
5690static struct attribute *mtl_hybrid_mem_attrs[] = {
5691 EVENT_PTR(mem_ld_adl),
5692 EVENT_PTR(mem_st_adl),
5693 NULL
5694};
5695
5696EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
5697EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
5698EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
5699EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
5700EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
5701EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
5702EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
5703EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
5704
5705static struct attribute *adl_hybrid_tsx_attrs[] = {
5706 EVENT_PTR(tx_start_adl),
5707 EVENT_PTR(tx_abort_adl),
5708 EVENT_PTR(tx_commit_adl),
5709 EVENT_PTR(tx_capacity_read_adl),
5710 EVENT_PTR(tx_capacity_write_adl),
5711 EVENT_PTR(tx_conflict_adl),
5712 EVENT_PTR(cycles_t_adl),
5713 EVENT_PTR(cycles_ct_adl),
5714 NULL,
5715};
5716
5717FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
5718FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
5719FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
5720FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small);
5721FORMAT_ATTR_HYBRID(frontend, hybrid_big);
5722
5723#define ADL_HYBRID_RTM_FORMAT_ATTR \
5724 FORMAT_HYBRID_PTR(in_tx), \
5725 FORMAT_HYBRID_PTR(in_tx_cp)
5726
5727#define ADL_HYBRID_FORMAT_ATTR \
5728 FORMAT_HYBRID_PTR(offcore_rsp), \
5729 FORMAT_HYBRID_PTR(ldlat), \
5730 FORMAT_HYBRID_PTR(frontend)
5731
5732static struct attribute *adl_hybrid_extra_attr_rtm[] = {
5733 ADL_HYBRID_RTM_FORMAT_ATTR,
5734 ADL_HYBRID_FORMAT_ATTR,
5735 NULL
5736};
5737
5738static struct attribute *adl_hybrid_extra_attr[] = {
5739 ADL_HYBRID_FORMAT_ATTR,
5740 NULL
5741};
5742
5743FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small);
5744
5745static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
5746 ADL_HYBRID_RTM_FORMAT_ATTR,
5747 ADL_HYBRID_FORMAT_ATTR,
5748 FORMAT_HYBRID_PTR(snoop_rsp),
5749 NULL
5750};
5751
5752static struct attribute *mtl_hybrid_extra_attr[] = {
5753 ADL_HYBRID_FORMAT_ATTR,
5754 FORMAT_HYBRID_PTR(snoop_rsp),
5755 NULL
5756};
5757
5758static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
5759{
5760 struct device *dev = kobj_to_dev(kobj);
5761 struct x86_hybrid_pmu *pmu =
5762 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5763 struct perf_pmu_events_hybrid_attr *pmu_attr =
5764 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
5765
5766 return pmu->pmu_type & pmu_attr->pmu_type;
5767}
5768
5769static umode_t hybrid_events_is_visible(struct kobject *kobj,
5770 struct attribute *attr, int i)
5771{
5772 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
5773}
5774
5775static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
5776{
5777 int cpu = cpumask_first(srcp: &pmu->supported_cpus);
5778
5779 return (cpu >= nr_cpu_ids) ? -1 : cpu;
5780}
5781
5782static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
5783 struct attribute *attr, int i)
5784{
5785 struct device *dev = kobj_to_dev(kobj);
5786 struct x86_hybrid_pmu *pmu =
5787 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5788 int cpu = hybrid_find_supported_cpu(pmu);
5789
5790 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
5791}
5792
5793static umode_t hybrid_format_is_visible(struct kobject *kobj,
5794 struct attribute *attr, int i)
5795{
5796 struct device *dev = kobj_to_dev(kobj);
5797 struct x86_hybrid_pmu *pmu =
5798 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5799 struct perf_pmu_format_hybrid_attr *pmu_attr =
5800 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
5801 int cpu = hybrid_find_supported_cpu(pmu);
5802
5803 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
5804}
5805
5806static struct attribute_group hybrid_group_events_td = {
5807 .name = "events",
5808 .is_visible = hybrid_events_is_visible,
5809};
5810
5811static struct attribute_group hybrid_group_events_mem = {
5812 .name = "events",
5813 .is_visible = hybrid_events_is_visible,
5814};
5815
5816static struct attribute_group hybrid_group_events_tsx = {
5817 .name = "events",
5818 .is_visible = hybrid_tsx_is_visible,
5819};
5820
5821static struct attribute_group hybrid_group_format_extra = {
5822 .name = "format",
5823 .is_visible = hybrid_format_is_visible,
5824};
5825
5826static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
5827 struct device_attribute *attr,
5828 char *buf)
5829{
5830 struct x86_hybrid_pmu *pmu =
5831 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5832
5833 return cpumap_print_to_pagebuf(list: true, buf, mask: &pmu->supported_cpus);
5834}
5835
5836static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
5837static struct attribute *intel_hybrid_cpus_attrs[] = {
5838 &dev_attr_cpus.attr,
5839 NULL,
5840};
5841
5842static struct attribute_group hybrid_group_cpus = {
5843 .attrs = intel_hybrid_cpus_attrs,
5844};
5845
5846static const struct attribute_group *hybrid_attr_update[] = {
5847 &hybrid_group_events_td,
5848 &hybrid_group_events_mem,
5849 &hybrid_group_events_tsx,
5850 &group_caps_gen,
5851 &group_caps_lbr,
5852 &hybrid_group_format_extra,
5853 &group_default,
5854 &hybrid_group_cpus,
5855 NULL,
5856};
5857
5858static struct attribute *empty_attrs;
5859
5860static void intel_pmu_check_num_counters(int *num_counters,
5861 int *num_counters_fixed,
5862 u64 *intel_ctrl, u64 fixed_mask)
5863{
5864 if (*num_counters > INTEL_PMC_MAX_GENERIC) {
5865 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5866 *num_counters, INTEL_PMC_MAX_GENERIC);
5867 *num_counters = INTEL_PMC_MAX_GENERIC;
5868 }
5869 *intel_ctrl = (1ULL << *num_counters) - 1;
5870
5871 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5872 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5873 *num_counters_fixed, INTEL_PMC_MAX_FIXED);
5874 *num_counters_fixed = INTEL_PMC_MAX_FIXED;
5875 }
5876
5877 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED;
5878}
5879
5880static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5881 int num_counters,
5882 int num_counters_fixed,
5883 u64 intel_ctrl)
5884{
5885 struct event_constraint *c;
5886
5887 if (!event_constraints)
5888 return;
5889
5890 /*
5891 * event on fixed counter2 (REF_CYCLES) only works on this
5892 * counter, so do not extend mask to generic counters
5893 */
5894 for_each_event_constraint(c, event_constraints) {
5895 /*
5896 * Don't extend the topdown slots and metrics
5897 * events to the generic counters.
5898 */
5899 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5900 /*
5901 * Disable topdown slots and metrics events,
5902 * if slots event is not in CPUID.
5903 */
5904 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
5905 c->idxmsk64 = 0;
5906 c->weight = hweight64(c->idxmsk64);
5907 continue;
5908 }
5909
5910 if (c->cmask == FIXED_EVENT_FLAGS) {
5911 /* Disabled fixed counters which are not in CPUID */
5912 c->idxmsk64 &= intel_ctrl;
5913
5914 /*
5915 * Don't extend the pseudo-encoding to the
5916 * generic counters
5917 */
5918 if (!use_fixed_pseudo_encoding(code: c->code))
5919 c->idxmsk64 |= (1ULL << num_counters) - 1;
5920 }
5921 c->idxmsk64 &=
5922 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed));
5923 c->weight = hweight64(c->idxmsk64);
5924 }
5925}
5926
5927static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
5928{
5929 struct extra_reg *er;
5930
5931 /*
5932 * Access extra MSR may cause #GP under certain circumstances.
5933 * E.g. KVM doesn't support offcore event
5934 * Check all extra_regs here.
5935 */
5936 if (!extra_regs)
5937 return;
5938
5939 for (er = extra_regs; er->msr; er++) {
5940 er->extra_msr_access = check_msr(msr: er->msr, mask: 0x11UL);
5941 /* Disable LBR select mapping */
5942 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5943 x86_pmu.lbr_sel_map = NULL;
5944 }
5945}
5946
5947static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
5948 { hybrid_small, "cpu_atom" },
5949 { hybrid_big, "cpu_core" },
5950};
5951
5952static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
5953{
5954 unsigned long pmus_mask = pmus;
5955 struct x86_hybrid_pmu *pmu;
5956 int idx = 0, bit;
5957
5958 x86_pmu.num_hybrid_pmus = hweight_long(w: pmus_mask);
5959 x86_pmu.hybrid_pmu = kcalloc(n: x86_pmu.num_hybrid_pmus,
5960 size: sizeof(struct x86_hybrid_pmu),
5961 GFP_KERNEL);
5962 if (!x86_pmu.hybrid_pmu)
5963 return -ENOMEM;
5964
5965 static_branch_enable(&perf_is_hybrid);
5966 x86_pmu.filter = intel_pmu_filter;
5967
5968 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
5969 pmu = &x86_pmu.hybrid_pmu[idx++];
5970 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
5971 pmu->name = intel_hybrid_pmu_type_map[bit].name;
5972
5973 pmu->num_counters = x86_pmu.num_counters;
5974 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
5975 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
5976 pmu->unconstrained = (struct event_constraint)
5977 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
5978 0, pmu->num_counters, 0, 0);
5979
5980 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
5981 if (pmu->pmu_type & hybrid_small) {
5982 pmu->intel_cap.perf_metrics = 0;
5983 pmu->intel_cap.pebs_output_pt_available = 1;
5984 pmu->mid_ack = true;
5985 } else if (pmu->pmu_type & hybrid_big) {
5986 pmu->intel_cap.perf_metrics = 1;
5987 pmu->intel_cap.pebs_output_pt_available = 0;
5988 pmu->late_ack = true;
5989 }
5990 }
5991
5992 return 0;
5993}
5994
5995static __always_inline void intel_pmu_ref_cycles_ext(void)
5996{
5997 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
5998 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
5999}
6000
6001static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
6002{
6003 x86_pmu.late_ack = true;
6004 x86_pmu.limit_period = glc_limit_period;
6005 x86_pmu.pebs_aliases = NULL;
6006 x86_pmu.pebs_prec_dist = true;
6007 x86_pmu.pebs_block = true;
6008 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6009 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6010 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6011 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6012 x86_pmu.lbr_pt_coexist = true;
6013 x86_pmu.num_topdown_events = 8;
6014 static_call_update(intel_pmu_update_topdown_event,
6015 &icl_update_topdown_event);
6016 static_call_update(intel_pmu_set_topdown_event_period,
6017 &icl_set_topdown_event_period);
6018
6019 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6020 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6021 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
6022 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
6023
6024 intel_pmu_ref_cycles_ext();
6025}
6026
6027static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
6028{
6029 x86_pmu.mid_ack = true;
6030 x86_pmu.limit_period = glc_limit_period;
6031 x86_pmu.pebs_aliases = NULL;
6032 x86_pmu.pebs_prec_dist = true;
6033 x86_pmu.pebs_block = true;
6034 x86_pmu.lbr_pt_coexist = true;
6035 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6036 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6037
6038 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6039 memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6040 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6041 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
6042 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
6043 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
6044
6045 intel_pmu_ref_cycles_ext();
6046}
6047
6048__init int intel_pmu_init(void)
6049{
6050 struct attribute **extra_skl_attr = &empty_attrs;
6051 struct attribute **extra_attr = &empty_attrs;
6052 struct attribute **td_attr = &empty_attrs;
6053 struct attribute **mem_attr = &empty_attrs;
6054 struct attribute **tsx_attr = &empty_attrs;
6055 union cpuid10_edx edx;
6056 union cpuid10_eax eax;
6057 union cpuid10_ebx ebx;
6058 unsigned int fixed_mask;
6059 bool pmem = false;
6060 int version, i;
6061 char *name;
6062 struct x86_hybrid_pmu *pmu;
6063
6064 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
6065 switch (boot_cpu_data.x86) {
6066 case 0x6:
6067 return p6_pmu_init();
6068 case 0xb:
6069 return knc_pmu_init();
6070 case 0xf:
6071 return p4_pmu_init();
6072 }
6073 return -ENODEV;
6074 }
6075
6076 /*
6077 * Check whether the Architectural PerfMon supports
6078 * Branch Misses Retired hw_event or not.
6079 */
6080 cpuid(op: 10, eax: &eax.full, ebx: &ebx.full, ecx: &fixed_mask, edx: &edx.full);
6081 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
6082 return -ENODEV;
6083
6084 version = eax.split.version_id;
6085 if (version < 2)
6086 x86_pmu = core_pmu;
6087 else
6088 x86_pmu = intel_pmu;
6089
6090 x86_pmu.version = version;
6091 x86_pmu.num_counters = eax.split.num_counters;
6092 x86_pmu.cntval_bits = eax.split.bit_width;
6093 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
6094
6095 x86_pmu.events_maskl = ebx.full;
6096 x86_pmu.events_mask_len = eax.split.mask_length;
6097
6098 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
6099 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
6100
6101 /*
6102 * Quirk: v2 perfmon does not report fixed-purpose events, so
6103 * assume at least 3 events, when not running in a hypervisor:
6104 */
6105 if (version > 1 && version < 5) {
6106 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
6107
6108 x86_pmu.num_counters_fixed =
6109 max((int)edx.split.num_counters_fixed, assume);
6110
6111 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
6112 } else if (version >= 5)
6113 x86_pmu.num_counters_fixed = fls(x: fixed_mask);
6114
6115 if (boot_cpu_has(X86_FEATURE_PDCM)) {
6116 u64 capabilities;
6117
6118 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
6119 x86_pmu.intel_cap.capabilities = capabilities;
6120 }
6121
6122 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
6123 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
6124 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
6125 }
6126
6127 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
6128 intel_pmu_arch_lbr_init();
6129
6130 intel_ds_init();
6131
6132 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
6133
6134 if (version >= 5) {
6135 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
6136 if (x86_pmu.intel_cap.anythread_deprecated)
6137 pr_cont(" AnyThread deprecated, ");
6138 }
6139
6140 /*
6141 * Install the hw-cache-events table:
6142 */
6143 switch (boot_cpu_data.x86_model) {
6144 case INTEL_FAM6_CORE_YONAH:
6145 pr_cont("Core events, ");
6146 name = "core";
6147 break;
6148
6149 case INTEL_FAM6_CORE2_MEROM:
6150 x86_add_quirk(intel_clovertown_quirk);
6151 fallthrough;
6152
6153 case INTEL_FAM6_CORE2_MEROM_L:
6154 case INTEL_FAM6_CORE2_PENRYN:
6155 case INTEL_FAM6_CORE2_DUNNINGTON:
6156 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
6157 sizeof(hw_cache_event_ids));
6158
6159 intel_pmu_lbr_init_core();
6160
6161 x86_pmu.event_constraints = intel_core2_event_constraints;
6162 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
6163 pr_cont("Core2 events, ");
6164 name = "core2";
6165 break;
6166
6167 case INTEL_FAM6_NEHALEM:
6168 case INTEL_FAM6_NEHALEM_EP:
6169 case INTEL_FAM6_NEHALEM_EX:
6170 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
6171 sizeof(hw_cache_event_ids));
6172 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6173 sizeof(hw_cache_extra_regs));
6174
6175 intel_pmu_lbr_init_nhm();
6176
6177 x86_pmu.event_constraints = intel_nehalem_event_constraints;
6178 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
6179 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6180 x86_pmu.extra_regs = intel_nehalem_extra_regs;
6181 x86_pmu.limit_period = nhm_limit_period;
6182
6183 mem_attr = nhm_mem_events_attrs;
6184
6185 /* UOPS_ISSUED.STALLED_CYCLES */
6186 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6187 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6188 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6189 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6190 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6191
6192 intel_pmu_pebs_data_source_nhm();
6193 x86_add_quirk(intel_nehalem_quirk);
6194 x86_pmu.pebs_no_tlb = 1;
6195 extra_attr = nhm_format_attr;
6196
6197 pr_cont("Nehalem events, ");
6198 name = "nehalem";
6199 break;
6200
6201 case INTEL_FAM6_ATOM_BONNELL:
6202 case INTEL_FAM6_ATOM_BONNELL_MID:
6203 case INTEL_FAM6_ATOM_SALTWELL:
6204 case INTEL_FAM6_ATOM_SALTWELL_MID:
6205 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
6206 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
6207 sizeof(hw_cache_event_ids));
6208
6209 intel_pmu_lbr_init_atom();
6210
6211 x86_pmu.event_constraints = intel_gen_event_constraints;
6212 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
6213 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
6214 pr_cont("Atom events, ");
6215 name = "bonnell";
6216 break;
6217
6218 case INTEL_FAM6_ATOM_SILVERMONT:
6219 case INTEL_FAM6_ATOM_SILVERMONT_D:
6220 case INTEL_FAM6_ATOM_SILVERMONT_MID:
6221 case INTEL_FAM6_ATOM_AIRMONT:
6222 case INTEL_FAM6_ATOM_AIRMONT_MID:
6223 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
6224 sizeof(hw_cache_event_ids));
6225 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
6226 sizeof(hw_cache_extra_regs));
6227
6228 intel_pmu_lbr_init_slm();
6229
6230 x86_pmu.event_constraints = intel_slm_event_constraints;
6231 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6232 x86_pmu.extra_regs = intel_slm_extra_regs;
6233 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6234 td_attr = slm_events_attrs;
6235 extra_attr = slm_format_attr;
6236 pr_cont("Silvermont events, ");
6237 name = "silvermont";
6238 break;
6239
6240 case INTEL_FAM6_ATOM_GOLDMONT:
6241 case INTEL_FAM6_ATOM_GOLDMONT_D:
6242 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
6243 sizeof(hw_cache_event_ids));
6244 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
6245 sizeof(hw_cache_extra_regs));
6246
6247 intel_pmu_lbr_init_skl();
6248
6249 x86_pmu.event_constraints = intel_slm_event_constraints;
6250 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
6251 x86_pmu.extra_regs = intel_glm_extra_regs;
6252 /*
6253 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6254 * for precise cycles.
6255 * :pp is identical to :ppp
6256 */
6257 x86_pmu.pebs_aliases = NULL;
6258 x86_pmu.pebs_prec_dist = true;
6259 x86_pmu.lbr_pt_coexist = true;
6260 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6261 td_attr = glm_events_attrs;
6262 extra_attr = slm_format_attr;
6263 pr_cont("Goldmont events, ");
6264 name = "goldmont";
6265 break;
6266
6267 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
6268 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6269 sizeof(hw_cache_event_ids));
6270 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
6271 sizeof(hw_cache_extra_regs));
6272
6273 intel_pmu_lbr_init_skl();
6274
6275 x86_pmu.event_constraints = intel_slm_event_constraints;
6276 x86_pmu.extra_regs = intel_glm_extra_regs;
6277 /*
6278 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6279 * for precise cycles.
6280 */
6281 x86_pmu.pebs_aliases = NULL;
6282 x86_pmu.pebs_prec_dist = true;
6283 x86_pmu.lbr_pt_coexist = true;
6284 x86_pmu.pebs_capable = ~0ULL;
6285 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6286 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6287 x86_pmu.get_event_constraints = glp_get_event_constraints;
6288 td_attr = glm_events_attrs;
6289 /* Goldmont Plus has 4-wide pipeline */
6290 event_attr_td_total_slots_scale_glm.event_str = "4";
6291 extra_attr = slm_format_attr;
6292 pr_cont("Goldmont plus events, ");
6293 name = "goldmont_plus";
6294 break;
6295
6296 case INTEL_FAM6_ATOM_TREMONT_D:
6297 case INTEL_FAM6_ATOM_TREMONT:
6298 case INTEL_FAM6_ATOM_TREMONT_L:
6299 x86_pmu.late_ack = true;
6300 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6301 sizeof(hw_cache_event_ids));
6302 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6303 sizeof(hw_cache_extra_regs));
6304 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6305
6306 intel_pmu_lbr_init_skl();
6307
6308 x86_pmu.event_constraints = intel_slm_event_constraints;
6309 x86_pmu.extra_regs = intel_tnt_extra_regs;
6310 /*
6311 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
6312 * for precise cycles.
6313 */
6314 x86_pmu.pebs_aliases = NULL;
6315 x86_pmu.pebs_prec_dist = true;
6316 x86_pmu.lbr_pt_coexist = true;
6317 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6318 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6319 td_attr = tnt_events_attrs;
6320 extra_attr = slm_format_attr;
6321 pr_cont("Tremont events, ");
6322 name = "Tremont";
6323 break;
6324
6325 case INTEL_FAM6_ATOM_GRACEMONT:
6326 intel_pmu_init_grt(NULL);
6327 intel_pmu_pebs_data_source_grt();
6328 x86_pmu.pebs_latency_data = adl_latency_data_small;
6329 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6330 td_attr = tnt_events_attrs;
6331 mem_attr = grt_mem_attrs;
6332 extra_attr = nhm_format_attr;
6333 pr_cont("Gracemont events, ");
6334 name = "gracemont";
6335 break;
6336
6337 case INTEL_FAM6_ATOM_CRESTMONT:
6338 case INTEL_FAM6_ATOM_CRESTMONT_X:
6339 intel_pmu_init_grt(NULL);
6340 x86_pmu.extra_regs = intel_cmt_extra_regs;
6341 intel_pmu_pebs_data_source_cmt();
6342 x86_pmu.pebs_latency_data = mtl_latency_data_small;
6343 x86_pmu.get_event_constraints = cmt_get_event_constraints;
6344 td_attr = cmt_events_attrs;
6345 mem_attr = grt_mem_attrs;
6346 extra_attr = cmt_format_attr;
6347 pr_cont("Crestmont events, ");
6348 name = "crestmont";
6349 break;
6350
6351 case INTEL_FAM6_WESTMERE:
6352 case INTEL_FAM6_WESTMERE_EP:
6353 case INTEL_FAM6_WESTMERE_EX:
6354 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6355 sizeof(hw_cache_event_ids));
6356 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6357 sizeof(hw_cache_extra_regs));
6358
6359 intel_pmu_lbr_init_nhm();
6360
6361 x86_pmu.event_constraints = intel_westmere_event_constraints;
6362 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6363 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6364 x86_pmu.extra_regs = intel_westmere_extra_regs;
6365 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6366
6367 mem_attr = nhm_mem_events_attrs;
6368
6369 /* UOPS_ISSUED.STALLED_CYCLES */
6370 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6371 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6372 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6373 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6374 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6375
6376 intel_pmu_pebs_data_source_nhm();
6377 extra_attr = nhm_format_attr;
6378 pr_cont("Westmere events, ");
6379 name = "westmere";
6380 break;
6381
6382 case INTEL_FAM6_SANDYBRIDGE:
6383 case INTEL_FAM6_SANDYBRIDGE_X:
6384 x86_add_quirk(intel_sandybridge_quirk);
6385 x86_add_quirk(intel_ht_bug);
6386 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6387 sizeof(hw_cache_event_ids));
6388 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6389 sizeof(hw_cache_extra_regs));
6390
6391 intel_pmu_lbr_init_snb();
6392
6393 x86_pmu.event_constraints = intel_snb_event_constraints;
6394 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6395 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6396 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
6397 x86_pmu.extra_regs = intel_snbep_extra_regs;
6398 else
6399 x86_pmu.extra_regs = intel_snb_extra_regs;
6400
6401
6402 /* all extra regs are per-cpu when HT is on */
6403 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6404 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6405
6406 td_attr = snb_events_attrs;
6407 mem_attr = snb_mem_events_attrs;
6408
6409 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6410 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6411 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6412 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6413 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6414 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6415
6416 extra_attr = nhm_format_attr;
6417
6418 pr_cont("SandyBridge events, ");
6419 name = "sandybridge";
6420 break;
6421
6422 case INTEL_FAM6_IVYBRIDGE:
6423 case INTEL_FAM6_IVYBRIDGE_X:
6424 x86_add_quirk(intel_ht_bug);
6425 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6426 sizeof(hw_cache_event_ids));
6427 /* dTLB-load-misses on IVB is different than SNB */
6428 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6429
6430 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6431 sizeof(hw_cache_extra_regs));
6432
6433 intel_pmu_lbr_init_snb();
6434
6435 x86_pmu.event_constraints = intel_ivb_event_constraints;
6436 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6437 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6438 x86_pmu.pebs_prec_dist = true;
6439 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
6440 x86_pmu.extra_regs = intel_snbep_extra_regs;
6441 else
6442 x86_pmu.extra_regs = intel_snb_extra_regs;
6443 /* all extra regs are per-cpu when HT is on */
6444 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6445 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6446
6447 td_attr = snb_events_attrs;
6448 mem_attr = snb_mem_events_attrs;
6449
6450 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6451 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6452 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6453
6454 extra_attr = nhm_format_attr;
6455
6456 pr_cont("IvyBridge events, ");
6457 name = "ivybridge";
6458 break;
6459
6460
6461 case INTEL_FAM6_HASWELL:
6462 case INTEL_FAM6_HASWELL_X:
6463 case INTEL_FAM6_HASWELL_L:
6464 case INTEL_FAM6_HASWELL_G:
6465 x86_add_quirk(intel_ht_bug);
6466 x86_add_quirk(intel_pebs_isolation_quirk);
6467 x86_pmu.late_ack = true;
6468 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6469 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6470
6471 intel_pmu_lbr_init_hsw();
6472
6473 x86_pmu.event_constraints = intel_hsw_event_constraints;
6474 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6475 x86_pmu.extra_regs = intel_snbep_extra_regs;
6476 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6477 x86_pmu.pebs_prec_dist = true;
6478 /* all extra regs are per-cpu when HT is on */
6479 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6480 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6481
6482 x86_pmu.hw_config = hsw_hw_config;
6483 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6484 x86_pmu.lbr_double_abort = true;
6485 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6486 hsw_format_attr : nhm_format_attr;
6487 td_attr = hsw_events_attrs;
6488 mem_attr = hsw_mem_events_attrs;
6489 tsx_attr = hsw_tsx_events_attrs;
6490 pr_cont("Haswell events, ");
6491 name = "haswell";
6492 break;
6493
6494 case INTEL_FAM6_BROADWELL:
6495 case INTEL_FAM6_BROADWELL_D:
6496 case INTEL_FAM6_BROADWELL_G:
6497 case INTEL_FAM6_BROADWELL_X:
6498 x86_add_quirk(intel_pebs_isolation_quirk);
6499 x86_pmu.late_ack = true;
6500 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6501 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6502
6503 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6504 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6505 BDW_L3_MISS|HSW_SNOOP_DRAM;
6506 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6507 HSW_SNOOP_DRAM;
6508 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6509 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6510 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6511 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6512
6513 intel_pmu_lbr_init_hsw();
6514
6515 x86_pmu.event_constraints = intel_bdw_event_constraints;
6516 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
6517 x86_pmu.extra_regs = intel_snbep_extra_regs;
6518 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6519 x86_pmu.pebs_prec_dist = true;
6520 /* all extra regs are per-cpu when HT is on */
6521 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6522 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6523
6524 x86_pmu.hw_config = hsw_hw_config;
6525 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6526 x86_pmu.limit_period = bdw_limit_period;
6527 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6528 hsw_format_attr : nhm_format_attr;
6529 td_attr = hsw_events_attrs;
6530 mem_attr = hsw_mem_events_attrs;
6531 tsx_attr = hsw_tsx_events_attrs;
6532 pr_cont("Broadwell events, ");
6533 name = "broadwell";
6534 break;
6535
6536 case INTEL_FAM6_XEON_PHI_KNL:
6537 case INTEL_FAM6_XEON_PHI_KNM:
6538 memcpy(hw_cache_event_ids,
6539 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6540 memcpy(hw_cache_extra_regs,
6541 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6542 intel_pmu_lbr_init_knl();
6543
6544 x86_pmu.event_constraints = intel_slm_event_constraints;
6545 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6546 x86_pmu.extra_regs = intel_knl_extra_regs;
6547
6548 /* all extra regs are per-cpu when HT is on */
6549 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6550 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6551 extra_attr = slm_format_attr;
6552 pr_cont("Knights Landing/Mill events, ");
6553 name = "knights-landing";
6554 break;
6555
6556 case INTEL_FAM6_SKYLAKE_X:
6557 pmem = true;
6558 fallthrough;
6559 case INTEL_FAM6_SKYLAKE_L:
6560 case INTEL_FAM6_SKYLAKE:
6561 case INTEL_FAM6_KABYLAKE_L:
6562 case INTEL_FAM6_KABYLAKE:
6563 case INTEL_FAM6_COMETLAKE_L:
6564 case INTEL_FAM6_COMETLAKE:
6565 x86_add_quirk(intel_pebs_isolation_quirk);
6566 x86_pmu.late_ack = true;
6567 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6568 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6569 intel_pmu_lbr_init_skl();
6570
6571 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6572 event_attr_td_recovery_bubbles.event_str_noht =
6573 "event=0xd,umask=0x1,cmask=1";
6574 event_attr_td_recovery_bubbles.event_str_ht =
6575 "event=0xd,umask=0x1,cmask=1,any=1";
6576
6577 x86_pmu.event_constraints = intel_skl_event_constraints;
6578 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6579 x86_pmu.extra_regs = intel_skl_extra_regs;
6580 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6581 x86_pmu.pebs_prec_dist = true;
6582 /* all extra regs are per-cpu when HT is on */
6583 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6584 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6585
6586 x86_pmu.hw_config = hsw_hw_config;
6587 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6588 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6589 hsw_format_attr : nhm_format_attr;
6590 extra_skl_attr = skl_format_attr;
6591 td_attr = hsw_events_attrs;
6592 mem_attr = hsw_mem_events_attrs;
6593 tsx_attr = hsw_tsx_events_attrs;
6594 intel_pmu_pebs_data_source_skl(pmem);
6595
6596 /*
6597 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
6598 * TSX force abort hooks are not required on these systems. Only deploy
6599 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
6600 */
6601 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
6602 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
6603 x86_pmu.flags |= PMU_FL_TFA;
6604 x86_pmu.get_event_constraints = tfa_get_event_constraints;
6605 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
6606 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
6607 }
6608
6609 pr_cont("Skylake events, ");
6610 name = "skylake";
6611 break;
6612
6613 case INTEL_FAM6_ICELAKE_X:
6614 case INTEL_FAM6_ICELAKE_D:
6615 x86_pmu.pebs_ept = 1;
6616 pmem = true;
6617 fallthrough;
6618 case INTEL_FAM6_ICELAKE_L:
6619 case INTEL_FAM6_ICELAKE:
6620 case INTEL_FAM6_TIGERLAKE_L:
6621 case INTEL_FAM6_TIGERLAKE:
6622 case INTEL_FAM6_ROCKETLAKE:
6623 x86_pmu.late_ack = true;
6624 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6625 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6626 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6627 intel_pmu_lbr_init_skl();
6628
6629 x86_pmu.event_constraints = intel_icl_event_constraints;
6630 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
6631 x86_pmu.extra_regs = intel_icl_extra_regs;
6632 x86_pmu.pebs_aliases = NULL;
6633 x86_pmu.pebs_prec_dist = true;
6634 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6635 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6636
6637 x86_pmu.hw_config = hsw_hw_config;
6638 x86_pmu.get_event_constraints = icl_get_event_constraints;
6639 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6640 hsw_format_attr : nhm_format_attr;
6641 extra_skl_attr = skl_format_attr;
6642 mem_attr = icl_events_attrs;
6643 td_attr = icl_td_events_attrs;
6644 tsx_attr = icl_tsx_events_attrs;
6645 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6646 x86_pmu.lbr_pt_coexist = true;
6647 intel_pmu_pebs_data_source_skl(pmem);
6648 x86_pmu.num_topdown_events = 4;
6649 static_call_update(intel_pmu_update_topdown_event,
6650 &icl_update_topdown_event);
6651 static_call_update(intel_pmu_set_topdown_event_period,
6652 &icl_set_topdown_event_period);
6653 pr_cont("Icelake events, ");
6654 name = "icelake";
6655 break;
6656
6657 case INTEL_FAM6_SAPPHIRERAPIDS_X:
6658 case INTEL_FAM6_EMERALDRAPIDS_X:
6659 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6660 x86_pmu.extra_regs = intel_glc_extra_regs;
6661 fallthrough;
6662 case INTEL_FAM6_GRANITERAPIDS_X:
6663 case INTEL_FAM6_GRANITERAPIDS_D:
6664 intel_pmu_init_glc(NULL);
6665 if (!x86_pmu.extra_regs)
6666 x86_pmu.extra_regs = intel_rwc_extra_regs;
6667 x86_pmu.pebs_ept = 1;
6668 x86_pmu.hw_config = hsw_hw_config;
6669 x86_pmu.get_event_constraints = glc_get_event_constraints;
6670 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6671 hsw_format_attr : nhm_format_attr;
6672 extra_skl_attr = skl_format_attr;
6673 mem_attr = glc_events_attrs;
6674 td_attr = glc_td_events_attrs;
6675 tsx_attr = glc_tsx_events_attrs;
6676 intel_pmu_pebs_data_source_skl(pmem: true);
6677 pr_cont("Sapphire Rapids events, ");
6678 name = "sapphire_rapids";
6679 break;
6680
6681 case INTEL_FAM6_ALDERLAKE:
6682 case INTEL_FAM6_ALDERLAKE_L:
6683 case INTEL_FAM6_RAPTORLAKE:
6684 case INTEL_FAM6_RAPTORLAKE_P:
6685 case INTEL_FAM6_RAPTORLAKE_S:
6686 /*
6687 * Alder Lake has 2 types of CPU, core and atom.
6688 *
6689 * Initialize the common PerfMon capabilities here.
6690 */
6691 intel_pmu_init_hybrid(pmus: hybrid_big_small);
6692
6693 x86_pmu.pebs_latency_data = adl_latency_data_small;
6694 x86_pmu.get_event_constraints = adl_get_event_constraints;
6695 x86_pmu.hw_config = adl_hw_config;
6696 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
6697
6698 td_attr = adl_hybrid_events_attrs;
6699 mem_attr = adl_hybrid_mem_attrs;
6700 tsx_attr = adl_hybrid_tsx_attrs;
6701 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6702 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
6703
6704 /* Initialize big core specific PerfMon capabilities.*/
6705 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6706 intel_pmu_init_glc(pmu: &pmu->pmu);
6707 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
6708 pmu->num_counters = x86_pmu.num_counters + 2;
6709 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
6710 } else {
6711 pmu->num_counters = x86_pmu.num_counters;
6712 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6713 }
6714
6715 /*
6716 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
6717 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
6718 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
6719 * mistakenly add extra counters for P-cores. Correct the number of
6720 * counters here.
6721 */
6722 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) {
6723 pmu->num_counters = x86_pmu.num_counters;
6724 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6725 }
6726
6727 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
6728 pmu->unconstrained = (struct event_constraint)
6729 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6730 0, pmu->num_counters, 0, 0);
6731 pmu->extra_regs = intel_glc_extra_regs;
6732
6733 /* Initialize Atom core specific PerfMon capabilities.*/
6734 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6735 intel_pmu_init_grt(pmu: &pmu->pmu);
6736
6737 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6738 intel_pmu_pebs_data_source_adl();
6739 pr_cont("Alderlake Hybrid events, ");
6740 name = "alderlake_hybrid";
6741 break;
6742
6743 case INTEL_FAM6_METEORLAKE:
6744 case INTEL_FAM6_METEORLAKE_L:
6745 intel_pmu_init_hybrid(pmus: hybrid_big_small);
6746
6747 x86_pmu.pebs_latency_data = mtl_latency_data_small;
6748 x86_pmu.get_event_constraints = mtl_get_event_constraints;
6749 x86_pmu.hw_config = adl_hw_config;
6750
6751 td_attr = adl_hybrid_events_attrs;
6752 mem_attr = mtl_hybrid_mem_attrs;
6753 tsx_attr = adl_hybrid_tsx_attrs;
6754 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6755 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
6756
6757 /* Initialize big core specific PerfMon capabilities.*/
6758 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6759 intel_pmu_init_glc(pmu: &pmu->pmu);
6760 pmu->extra_regs = intel_rwc_extra_regs;
6761
6762 /* Initialize Atom core specific PerfMon capabilities.*/
6763 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6764 intel_pmu_init_grt(pmu: &pmu->pmu);
6765 pmu->extra_regs = intel_cmt_extra_regs;
6766
6767 intel_pmu_pebs_data_source_mtl();
6768 pr_cont("Meteorlake Hybrid events, ");
6769 name = "meteorlake_hybrid";
6770 break;
6771
6772 default:
6773 switch (x86_pmu.version) {
6774 case 1:
6775 x86_pmu.event_constraints = intel_v1_event_constraints;
6776 pr_cont("generic architected perfmon v1, ");
6777 name = "generic_arch_v1";
6778 break;
6779 case 2:
6780 case 3:
6781 case 4:
6782 /*
6783 * default constraints for v2 and up
6784 */
6785 x86_pmu.event_constraints = intel_gen_event_constraints;
6786 pr_cont("generic architected perfmon, ");
6787 name = "generic_arch_v2+";
6788 break;
6789 default:
6790 /*
6791 * The default constraints for v5 and up can support up to
6792 * 16 fixed counters. For the fixed counters 4 and later,
6793 * the pseudo-encoding is applied.
6794 * The constraints may be cut according to the CPUID enumeration
6795 * by inserting the EVENT_CONSTRAINT_END.
6796 */
6797 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED)
6798 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
6799 intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1;
6800 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
6801 pr_cont("generic architected perfmon, ");
6802 name = "generic_arch_v5+";
6803 break;
6804 }
6805 }
6806
6807 snprintf(buf: pmu_name_str, size: sizeof(pmu_name_str), fmt: "%s", name);
6808
6809 if (!is_hybrid()) {
6810 group_events_td.attrs = td_attr;
6811 group_events_mem.attrs = mem_attr;
6812 group_events_tsx.attrs = tsx_attr;
6813 group_format_extra.attrs = extra_attr;
6814 group_format_extra_skl.attrs = extra_skl_attr;
6815
6816 x86_pmu.attr_update = attr_update;
6817 } else {
6818 hybrid_group_events_td.attrs = td_attr;
6819 hybrid_group_events_mem.attrs = mem_attr;
6820 hybrid_group_events_tsx.attrs = tsx_attr;
6821 hybrid_group_format_extra.attrs = extra_attr;
6822
6823 x86_pmu.attr_update = hybrid_attr_update;
6824 }
6825
6826 intel_pmu_check_num_counters(num_counters: &x86_pmu.num_counters,
6827 num_counters_fixed: &x86_pmu.num_counters_fixed,
6828 intel_ctrl: &x86_pmu.intel_ctrl,
6829 fixed_mask: (u64)fixed_mask);
6830
6831 /* AnyThread may be deprecated on arch perfmon v5 or later */
6832 if (x86_pmu.intel_cap.anythread_deprecated)
6833 x86_pmu.format_attrs = intel_arch_formats_attr;
6834
6835 intel_pmu_check_event_constraints(event_constraints: x86_pmu.event_constraints,
6836 num_counters: x86_pmu.num_counters,
6837 num_counters_fixed: x86_pmu.num_counters_fixed,
6838 intel_ctrl: x86_pmu.intel_ctrl);
6839 /*
6840 * Access LBR MSR may cause #GP under certain circumstances.
6841 * Check all LBR MSR here.
6842 * Disable LBR access if any LBR MSRs can not be accessed.
6843 */
6844 if (x86_pmu.lbr_tos && !check_msr(msr: x86_pmu.lbr_tos, mask: 0x3UL))
6845 x86_pmu.lbr_nr = 0;
6846 for (i = 0; i < x86_pmu.lbr_nr; i++) {
6847 if (!(check_msr(msr: x86_pmu.lbr_from + i, mask: 0xffffUL) &&
6848 check_msr(msr: x86_pmu.lbr_to + i, mask: 0xffffUL)))
6849 x86_pmu.lbr_nr = 0;
6850 }
6851
6852 if (x86_pmu.lbr_nr) {
6853 intel_pmu_lbr_init();
6854
6855 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
6856
6857 /* only support branch_stack snapshot for perfmon >= v2 */
6858 if (x86_pmu.disable_all == intel_pmu_disable_all) {
6859 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
6860 static_call_update(perf_snapshot_branch_stack,
6861 intel_pmu_snapshot_arch_branch_stack);
6862 } else {
6863 static_call_update(perf_snapshot_branch_stack,
6864 intel_pmu_snapshot_branch_stack);
6865 }
6866 }
6867 }
6868
6869 intel_pmu_check_extra_regs(extra_regs: x86_pmu.extra_regs);
6870
6871 /* Support full width counters using alternative MSR range */
6872 if (x86_pmu.intel_cap.full_width_write) {
6873 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
6874 x86_pmu.perfctr = MSR_IA32_PMC0;
6875 pr_cont("full-width counters, ");
6876 }
6877
6878 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
6879 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
6880
6881 if (x86_pmu.intel_cap.pebs_timing_info)
6882 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
6883
6884 intel_aux_output_init();
6885
6886 return 0;
6887}
6888
6889/*
6890 * HT bug: phase 2 init
6891 * Called once we have valid topology information to check
6892 * whether or not HT is enabled
6893 * If HT is off, then we disable the workaround
6894 */
6895static __init int fixup_ht_bug(void)
6896{
6897 int c;
6898 /*
6899 * problem not present on this CPU model, nothing to do
6900 */
6901 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
6902 return 0;
6903
6904 if (topology_max_smt_threads() > 1) {
6905 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
6906 return 0;
6907 }
6908
6909 cpus_read_lock();
6910
6911 hardlockup_detector_perf_stop();
6912
6913 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
6914
6915 x86_pmu.start_scheduling = NULL;
6916 x86_pmu.commit_scheduling = NULL;
6917 x86_pmu.stop_scheduling = NULL;
6918
6919 hardlockup_detector_perf_restart();
6920
6921 for_each_online_cpu(c)
6922 free_excl_cntrs(cpuc: &per_cpu(cpu_hw_events, c));
6923
6924 cpus_read_unlock();
6925 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
6926 return 0;
6927}
6928subsys_initcall(fixup_ht_bug)
6929

source code of linux/arch/x86/events/intel/core.c