1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* nicstar.c
4	*
5	* Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6	*
7	* IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8	* It was taken from the frle-0.22 device driver.
9	* As the file doesn't have a copyright notice, in the file
10	* nicstarmac.copyright I put the copyright notice from the
11	* frle-0.22 device driver.
12	* Some code is based on the nicstar driver by M. Welsh.
13	*
14	* Author: Rui Prior (rprior@inescn.pt)
15	* PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16	*
17	*
18	* (C) INESC 1999
19	*/
20
21	/*
22	* IMPORTANT INFORMATION
23	*
24	* There are currently three types of spinlocks:
25	*
26	* 1 - Per card interrupt spinlock (to protect structures and such)
27	* 2 - Per SCQ scq spinlock
28	* 3 - Per card resource spinlock (to access registers, etc.)
29	*
30	* These must NEVER be grabbed in reverse order.
31	*
32	*/
33
34	/* Header files */
35
36	#include <linux/module.h>
37	#include <linux/kernel.h>
38	#include <linux/skbuff.h>
39	#include <linux/atmdev.h>
40	#include <linux/atm.h>
41	#include <linux/pci.h>
42	#include <linux/dma-mapping.h>
43	#include <linux/types.h>
44	#include <linux/string.h>
45	#include <linux/delay.h>
46	#include <linux/init.h>
47	#include <linux/sched.h>
48	#include <linux/timer.h>
49	#include <linux/interrupt.h>
50	#include <linux/bitops.h>
51	#include <linux/slab.h>
52	#include <linux/idr.h>
53	#include <asm/io.h>
54	#include <linux/uaccess.h>
55	#include <linux/atomic.h>
56	#include <linux/etherdevice.h>
57	#include "nicstar.h"
58	#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59	#include "suni.h"
60	#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61	#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62	#include "idt77105.h"
63	#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65	/* Additional code */
66
67	#include "nicstarmac.c"
68
69	/* Configurable parameters */
70
71	#undef PHY_LOOPBACK
72	#undef TX_DEBUG
73	#undef RX_DEBUG
74	#undef GENERAL_DEBUG
75	#undef EXTRA_DEBUG
76
77	/* Do not touch these */
78
79	#ifdef TX_DEBUG
80	#define TXPRINTK(args...) printk(args)
81	#else
82	#define TXPRINTK(args...)
83	#endif /* TX_DEBUG */
84
85	#ifdef RX_DEBUG
86	#define RXPRINTK(args...) printk(args)
87	#else
88	#define RXPRINTK(args...)
89	#endif /* RX_DEBUG */
90
91	#ifdef GENERAL_DEBUG
92	#define PRINTK(args...) printk(args)
93	#else
94	#define PRINTK(args...) do {} while (0)
95	#endif /* GENERAL_DEBUG */
96
97	#ifdef EXTRA_DEBUG
98	#define XPRINTK(args...) printk(args)
99	#else
100	#define XPRINTK(args...)
101	#endif /* EXTRA_DEBUG */
102
103	/* Macros */
104
105	#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107	#define NS_DELAY mdelay(1)
108
109	#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111	#ifndef ATM_SKB
112	#define ATM_SKB(s) (&(s)->atm)
113	#endif
114
115	#define scq_virt_to_bus(scq, p) \
116	(scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118	/* Function declarations */
119
120	static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121	static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122	int count);
123	static int ns_init_card(int i, struct pci_dev *pcidev);
124	static void ns_init_card_error(ns_dev * card, int error);
125	static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126	static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127	static void push_rxbufs(ns_dev *, struct sk_buff *);
128	static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129	static int ns_open(struct atm_vcc *vcc);
130	static void ns_close(struct atm_vcc *vcc);
131	static void fill_tst(ns_dev * card, int n, vc_map * vc);
132	static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133	static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
134	static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135	struct sk_buff *skb, bool may_sleep);
136	static void process_tsq(ns_dev * card);
137	static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138	static void process_rsq(ns_dev * card);
139	static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140	static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141	static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142	static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143	static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144	static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
145	static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
146	static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
147	#ifdef EXTRA_DEBUG
148	static void which_list(ns_dev * card, struct sk_buff *skb);
149	#endif
150	static void ns_poll(struct timer_list *unused);
151	static void ns_phy_put(struct atm_dev *dev, unsigned char value,
152	unsigned long addr);
153	static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
154
155	/* Global variables */
156
157	static struct ns_dev *cards[NS_MAX_CARDS];
158	static unsigned num_cards;
159	static const struct atmdev_ops atm_ops = {
160	.open = ns_open,
161	.close = ns_close,
162	.ioctl = ns_ioctl,
163	.send = ns_send,
164	.send_bh = ns_send_bh,
165	.phy_put = ns_phy_put,
166	.phy_get = ns_phy_get,
167	.proc_read = ns_proc_read,
168	.owner = THIS_MODULE,
169	};
170
171	static struct timer_list ns_timer;
172	static char *mac[NS_MAX_CARDS];
173	module_param_array(mac, charp, NULL, 0);
174	MODULE_LICENSE("GPL");
175
176	/* Functions */
177
178	static int nicstar_init_one(struct pci_dev *pcidev,
179	const struct pci_device_id *ent)
180	{
181	static int index = -1;
182	unsigned int error;
183
184	index++;
185	cards[index] = NULL;
186
187	error = ns_init_card(i: index, pcidev);
188	if (error) {
189	cards[index--] = NULL; /* don't increment index */
190	goto err_out;
191	}
192
193	return 0;
194	err_out:
195	return -ENODEV;
196	}
197
198	static void nicstar_remove_one(struct pci_dev *pcidev)
199	{
200	int i, j;
201	ns_dev *card = pci_get_drvdata(pdev: pcidev);
202	struct sk_buff *hb;
203	struct sk_buff *iovb;
204	struct sk_buff *lb;
205	struct sk_buff *sb;
206
207	i = card->index;
208
209	if (cards[i] == NULL)
210	return;
211
212	if (card->atmdev->phy && card->atmdev->phy->stop)
213	card->atmdev->phy->stop(card->atmdev);
214
215	/* Stop everything */
216	writel(val: 0x00000000, addr: card->membase + CFG);
217
218	/* De-register device */
219	atm_dev_deregister(dev: card->atmdev);
220
221	/* Disable PCI device */
222	pci_disable_device(dev: pcidev);
223
224	/* Free up resources */
225	j = 0;
226	PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227	while ((hb = skb_dequeue(list: &card->hbpool.queue)) != NULL) {
228	dev_kfree_skb_any(skb: hb);
229	j++;
230	}
231	PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
232	j = 0;
233	PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
234	card->iovpool.count);
235	while ((iovb = skb_dequeue(list: &card->iovpool.queue)) != NULL) {
236	dev_kfree_skb_any(skb: iovb);
237	j++;
238	}
239	PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
240	while ((lb = skb_dequeue(list: &card->lbpool.queue)) != NULL)
241	dev_kfree_skb_any(skb: lb);
242	while ((sb = skb_dequeue(list: &card->sbpool.queue)) != NULL)
243	dev_kfree_skb_any(skb: sb);
244	free_scq(card, scq: card->scq0, NULL);
245	for (j = 0; j < NS_FRSCD_NUM; j++) {
246	if (card->scd2vc[j] != NULL)
247	free_scq(card, scq: card->scd2vc[j]->scq, vcc: card->scd2vc[j]->tx_vcc);
248	}
249	idr_destroy(&card->idr);
250	dma_free_coherent(dev: &card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251	cpu_addr: card->rsq.org, dma_handle: card->rsq.dma);
252	dma_free_coherent(dev: &card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253	cpu_addr: card->tsq.org, dma_handle: card->tsq.dma);
254	free_irq(card->pcidev->irq, card);
255	iounmap(addr: card->membase);
256	kfree(objp: card);
257	}
258
259	static const struct pci_device_id nicstar_pci_tbl[] = {
260	{ PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
261	{0,} /* terminate list */
262	};
263
264	MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
265
266	static struct pci_driver nicstar_driver = {
267	.name = "nicstar",
268	.id_table = nicstar_pci_tbl,
269	.probe = nicstar_init_one,
270	.remove = nicstar_remove_one,
271	};
272
273	static int __init nicstar_init(void)
274	{
275	unsigned error = 0; /* Initialized to remove compile warning */
276
277	XPRINTK("nicstar: nicstar_init() called.\n");
278
279	error = pci_register_driver(&nicstar_driver);
280
281	TXPRINTK("nicstar: TX debug enabled.\n");
282	RXPRINTK("nicstar: RX debug enabled.\n");
283	PRINTK("nicstar: General debug enabled.\n");
284	#ifdef PHY_LOOPBACK
285	printk("nicstar: using PHY loopback.\n");
286	#endif /* PHY_LOOPBACK */
287	XPRINTK("nicstar: nicstar_init() returned.\n");
288
289	if (!error) {
290	timer_setup(&ns_timer, ns_poll, 0);
291	ns_timer.expires = jiffies + NS_POLL_PERIOD;
292	add_timer(timer: &ns_timer);
293	}
294
295	return error;
296	}
297
298	static void __exit nicstar_cleanup(void)
299	{
300	XPRINTK("nicstar: nicstar_cleanup() called.\n");
301
302	del_timer_sync(timer: &ns_timer);
303
304	pci_unregister_driver(dev: &nicstar_driver);
305
306	XPRINTK("nicstar: nicstar_cleanup() returned.\n");
307	}
308
309	static u32 ns_read_sram(ns_dev * card, u32 sram_address)
310	{
311	unsigned long flags;
312	u32 data;
313	sram_address <<= 2;
314	sram_address &= 0x0007FFFC; /* address must be dword aligned */
315	sram_address |= 0x50000000; /* SRAM read command */
316	spin_lock_irqsave(&card->res_lock, flags);
317	while (CMD_BUSY(card)) ;
318	writel(val: sram_address, addr: card->membase + CMD);
319	while (CMD_BUSY(card)) ;
320	data = readl(addr: card->membase + DR0);
321	spin_unlock_irqrestore(lock: &card->res_lock, flags);
322	return data;
323	}
324
325	static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
326	int count)
327	{
328	unsigned long flags;
329	int i, c;
330	count--; /* count range now is 0..3 instead of 1..4 */
331	c = count;
332	c <<= 2; /* to use increments of 4 */
333	spin_lock_irqsave(&card->res_lock, flags);
334	while (CMD_BUSY(card)) ;
335	for (i = 0; i <= c; i += 4)
336	writel(val: *(value++), addr: card->membase + i);
337	/* Note: DR# registers are the first 4 dwords in nicstar's memspace,
338	so card->membase + DR0 == card->membase */
339	sram_address <<= 2;
340	sram_address &= 0x0007FFFC;
341	sram_address |= (0x40000000 | count);
342	writel(val: sram_address, addr: card->membase + CMD);
343	spin_unlock_irqrestore(lock: &card->res_lock, flags);
344	}
345
346	static int ns_init_card(int i, struct pci_dev *pcidev)
347	{
348	int j;
349	struct ns_dev *card = NULL;
350	unsigned char pci_latency;
351	unsigned error;
352	u32 data;
353	u32 u32d[4];
354	u32 ns_cfg_rctsize;
355	int bcount;
356	unsigned long membase;
357
358	error = 0;
359
360	if (pci_enable_device(dev: pcidev)) {
361	printk("nicstar%d: can't enable PCI device\n", i);
362	error = 2;
363	ns_init_card_error(card, error);
364	return error;
365	}
366	if (dma_set_mask_and_coherent(dev: &pcidev->dev, DMA_BIT_MASK(32)) != 0) {
367	printk(KERN_WARNING
368	"nicstar%d: No suitable DMA available.\n", i);
369	error = 2;
370	ns_init_card_error(card, error);
371	return error;
372	}
373
374	card = kmalloc(size: sizeof(*card), GFP_KERNEL);
375	if (!card) {
376	printk
377	("nicstar%d: can't allocate memory for device structure.\n",
378	i);
379	error = 2;
380	ns_init_card_error(card, error);
381	return error;
382	}
383	cards[i] = card;
384	spin_lock_init(&card->int_lock);
385	spin_lock_init(&card->res_lock);
386
387	pci_set_drvdata(pdev: pcidev, data: card);
388
389	card->index = i;
390	card->atmdev = NULL;
391	card->pcidev = pcidev;
392	membase = pci_resource_start(pcidev, 1);
393	card->membase = ioremap(offset: membase, NS_IOREMAP_SIZE);
394	if (!card->membase) {
395	printk("nicstar%d: can't ioremap() membase.\n", i);
396	error = 3;
397	ns_init_card_error(card, error);
398	return error;
399	}
400	PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
401
402	pci_set_master(dev: pcidev);
403
404	if (pci_read_config_byte(dev: pcidev, PCI_LATENCY_TIMER, val: &pci_latency) != 0) {
405	printk("nicstar%d: can't read PCI latency timer.\n", i);
406	error = 6;
407	ns_init_card_error(card, error);
408	return error;
409	}
410	#ifdef NS_PCI_LATENCY
411	if (pci_latency < NS_PCI_LATENCY) {
412	PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
413	NS_PCI_LATENCY);
414	for (j = 1; j < 4; j++) {
415	if (pci_write_config_byte
416	(pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
417	break;
418	}
419	if (j == 4) {
420	printk
421	("nicstar%d: can't set PCI latency timer to %d.\n",
422	i, NS_PCI_LATENCY);
423	error = 7;
424	ns_init_card_error(card, error);
425	return error;
426	}
427	}
428	#endif /* NS_PCI_LATENCY */
429
430	/* Clear timer overflow */
431	data = readl(addr: card->membase + STAT);
432	if (data & NS_STAT_TMROF)
433	writel(NS_STAT_TMROF, addr: card->membase + STAT);
434
435	/* Software reset */
436	writel(NS_CFG_SWRST, addr: card->membase + CFG);
437	NS_DELAY;
438	writel(val: 0x00000000, addr: card->membase + CFG);
439
440	/* PHY reset */
441	writel(val: 0x00000008, addr: card->membase + GP);
442	NS_DELAY;
443	writel(val: 0x00000001, addr: card->membase + GP);
444	NS_DELAY;
445	while (CMD_BUSY(card)) ;
446	writel(NS_CMD_WRITE_UTILITY | 0x00000100, addr: card->membase + CMD); /* Sync UTOPIA with SAR clock */
447	NS_DELAY;
448
449	/* Detect PHY type */
450	while (CMD_BUSY(card)) ;
451	writel(NS_CMD_READ_UTILITY | 0x00000200, addr: card->membase + CMD);
452	while (CMD_BUSY(card)) ;
453	data = readl(addr: card->membase + DR0);
454	switch (data) {
455	case 0x00000009:
456	printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
457	card->max_pcr = ATM_25_PCR;
458	while (CMD_BUSY(card)) ;
459	writel(val: 0x00000008, addr: card->membase + DR0);
460	writel(NS_CMD_WRITE_UTILITY | 0x00000200, addr: card->membase + CMD);
461	/* Clear an eventual pending interrupt */
462	writel(NS_STAT_SFBQF, addr: card->membase + STAT);
463	#ifdef PHY_LOOPBACK
464	while (CMD_BUSY(card)) ;
465	writel(0x00000022, card->membase + DR0);
466	writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
467	#endif /* PHY_LOOPBACK */
468	break;
469	case 0x00000030:
470	case 0x00000031:
471	printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
472	card->max_pcr = ATM_OC3_PCR;
473	#ifdef PHY_LOOPBACK
474	while (CMD_BUSY(card)) ;
475	writel(0x00000002, card->membase + DR0);
476	writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
477	#endif /* PHY_LOOPBACK */
478	break;
479	default:
480	printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
481	error = 8;
482	ns_init_card_error(card, error);
483	return error;
484	}
485	writel(val: 0x00000000, addr: card->membase + GP);
486
487	/* Determine SRAM size */
488	data = 0x76543210;
489	ns_write_sram(card, sram_address: 0x1C003, value: &data, count: 1);
490	data = 0x89ABCDEF;
491	ns_write_sram(card, sram_address: 0x14003, value: &data, count: 1);
492	if (ns_read_sram(card, sram_address: 0x14003) == 0x89ABCDEF &&
493	ns_read_sram(card, sram_address: 0x1C003) == 0x76543210)
494	card->sram_size = 128;
495	else
496	card->sram_size = 32;
497	PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
498
499	card->rct_size = NS_MAX_RCTSIZE;
500
501	#if (NS_MAX_RCTSIZE == 4096)
502	if (card->sram_size == 128)
503	printk
504	("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505	i);
506	#elif (NS_MAX_RCTSIZE == 16384)
507	if (card->sram_size == 32) {
508	printk
509	("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
510	i);
511	card->rct_size = 4096;
512	}
513	#else
514	#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
515	#endif
516
517	card->vpibits = NS_VPIBITS;
518	if (card->rct_size == 4096)
519	card->vcibits = 12 - NS_VPIBITS;
520	else /* card->rct_size == 16384 */
521	card->vcibits = 14 - NS_VPIBITS;
522
523	/* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
524	if (mac[i] == NULL)
525	nicstar_init_eprom(base: card->membase);
526
527	/* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
528	writel(val: 0x00000000, addr: card->membase + VPM);
529
530	card->intcnt = 0;
531	if (request_irq
532	(irq: pcidev->irq, handler: &ns_irq_handler, IRQF_SHARED, name: "nicstar", dev: card) != 0) {
533	pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
534	error = 9;
535	ns_init_card_error(card, error);
536	return error;
537	}
538
539	/* Initialize TSQ */
540	card->tsq.org = dma_alloc_coherent(dev: &card->pcidev->dev,
541	NS_TSQSIZE + NS_TSQ_ALIGNMENT,
542	dma_handle: &card->tsq.dma, GFP_KERNEL);
543	if (card->tsq.org == NULL) {
544	printk("nicstar%d: can't allocate TSQ.\n", i);
545	error = 10;
546	ns_init_card_error(card, error);
547	return error;
548	}
549	card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
550	card->tsq.next = card->tsq.base;
551	card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
552	for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
553	ns_tsi_init(card->tsq.base + j);
554	writel(val: 0x00000000, addr: card->membase + TSQH);
555	writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), addr: card->membase + TSQB);
556	PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
557
558	/* Initialize RSQ */
559	card->rsq.org = dma_alloc_coherent(dev: &card->pcidev->dev,
560	NS_RSQSIZE + NS_RSQ_ALIGNMENT,
561	dma_handle: &card->rsq.dma, GFP_KERNEL);
562	if (card->rsq.org == NULL) {
563	printk("nicstar%d: can't allocate RSQ.\n", i);
564	error = 11;
565	ns_init_card_error(card, error);
566	return error;
567	}
568	card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
569	card->rsq.next = card->rsq.base;
570	card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
571	for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
572	ns_rsqe_init(card->rsq.base + j);
573	writel(val: 0x00000000, addr: card->membase + RSQH);
574	writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), addr: card->membase + RSQB);
575	PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
576
577	/* Initialize SCQ0, the only VBR SCQ used */
578	card->scq1 = NULL;
579	card->scq2 = NULL;
580	card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
581	if (card->scq0 == NULL) {
582	printk("nicstar%d: can't get SCQ0.\n", i);
583	error = 12;
584	ns_init_card_error(card, error);
585	return error;
586	}
587	u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
588	u32d[1] = (u32) 0x00000000;
589	u32d[2] = (u32) 0xffffffff;
590	u32d[3] = (u32) 0x00000000;
591	ns_write_sram(card, NS_VRSCD0, value: u32d, count: 4);
592	ns_write_sram(card, NS_VRSCD1, value: u32d, count: 4); /* These last two won't be used */
593	ns_write_sram(card, NS_VRSCD2, value: u32d, count: 4); /* but are initialized, just in case... */
594	card->scq0->scd = NS_VRSCD0;
595	PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
596
597	/* Initialize TSTs */
598	card->tst_addr = NS_TST0;
599	card->tst_free_entries = NS_TST_NUM_ENTRIES;
600	data = NS_TST_OPCODE_VARIABLE;
601	for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
602	ns_write_sram(card, NS_TST0 + j, value: &data, count: 1);
603	data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
604	ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, value: &data, count: 1);
605	for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
606	ns_write_sram(card, NS_TST1 + j, value: &data, count: 1);
607	data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
608	ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, value: &data, count: 1);
609	for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
610	card->tste2vc[j] = NULL;
611	writel(NS_TST0 << 2, addr: card->membase + TSTB);
612
613	/* Initialize RCT. AAL type is set on opening the VC. */
614	#ifdef RCQ_SUPPORT
615	u32d[0] = NS_RCTE_RAWCELLINTEN;
616	#else
617	u32d[0] = 0x00000000;
618	#endif /* RCQ_SUPPORT */
619	u32d[1] = 0x00000000;
620	u32d[2] = 0x00000000;
621	u32d[3] = 0xFFFFFFFF;
622	for (j = 0; j < card->rct_size; j++)
623	ns_write_sram(card, sram_address: j * 4, value: u32d, count: 4);
624
625	memset(card->vcmap, 0, sizeof(card->vcmap));
626
627	for (j = 0; j < NS_FRSCD_NUM; j++)
628	card->scd2vc[j] = NULL;
629
630	/* Initialize buffer levels */
631	card->sbnr.min = MIN_SB;
632	card->sbnr.init = NUM_SB;
633	card->sbnr.max = MAX_SB;
634	card->lbnr.min = MIN_LB;
635	card->lbnr.init = NUM_LB;
636	card->lbnr.max = MAX_LB;
637	card->iovnr.min = MIN_IOVB;
638	card->iovnr.init = NUM_IOVB;
639	card->iovnr.max = MAX_IOVB;
640	card->hbnr.min = MIN_HB;
641	card->hbnr.init = NUM_HB;
642	card->hbnr.max = MAX_HB;
643
644	card->sm_handle = NULL;
645	card->sm_addr = 0x00000000;
646	card->lg_handle = NULL;
647	card->lg_addr = 0x00000000;
648
649	card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
650
651	idr_init(idr: &card->idr);
652
653	/* Pre-allocate some huge buffers */
654	skb_queue_head_init(list: &card->hbpool.queue);
655	card->hbpool.count = 0;
656	for (j = 0; j < NUM_HB; j++) {
657	struct sk_buff *hb;
658	hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
659	if (hb == NULL) {
660	printk
661	("nicstar%d: can't allocate %dth of %d huge buffers.\n",
662	i, j, NUM_HB);
663	error = 13;
664	ns_init_card_error(card, error);
665	return error;
666	}
667	NS_PRV_BUFTYPE(hb) = BUF_NONE;
668	skb_queue_tail(list: &card->hbpool.queue, newsk: hb);
669	card->hbpool.count++;
670	}
671
672	/* Allocate large buffers */
673	skb_queue_head_init(list: &card->lbpool.queue);
674	card->lbpool.count = 0; /* Not used */
675	for (j = 0; j < NUM_LB; j++) {
676	struct sk_buff *lb;
677	lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
678	if (lb == NULL) {
679	printk
680	("nicstar%d: can't allocate %dth of %d large buffers.\n",
681	i, j, NUM_LB);
682	error = 14;
683	ns_init_card_error(card, error);
684	return error;
685	}
686	NS_PRV_BUFTYPE(lb) = BUF_LG;
687	skb_queue_tail(list: &card->lbpool.queue, newsk: lb);
688	skb_reserve(skb: lb, NS_SMBUFSIZE);
689	push_rxbufs(card, lb);
690	/* Due to the implementation of push_rxbufs() this is 1, not 0 */
691	if (j == 1) {
692	card->rcbuf = lb;
693	card->rawcell = (struct ns_rcqe *) lb->data;
694	card->rawch = NS_PRV_DMA(lb);
695	}
696	}
697	/* Test for strange behaviour which leads to crashes */
698	if ((bcount =
699	ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
700	printk
701	("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
702	i, j, bcount);
703	error = 14;
704	ns_init_card_error(card, error);
705	return error;
706	}
707
708	/* Allocate small buffers */
709	skb_queue_head_init(list: &card->sbpool.queue);
710	card->sbpool.count = 0; /* Not used */
711	for (j = 0; j < NUM_SB; j++) {
712	struct sk_buff *sb;
713	sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
714	if (sb == NULL) {
715	printk
716	("nicstar%d: can't allocate %dth of %d small buffers.\n",
717	i, j, NUM_SB);
718	error = 15;
719	ns_init_card_error(card, error);
720	return error;
721	}
722	NS_PRV_BUFTYPE(sb) = BUF_SM;
723	skb_queue_tail(list: &card->sbpool.queue, newsk: sb);
724	skb_reserve(skb: sb, NS_AAL0_HEADER);
725	push_rxbufs(card, sb);
726	}
727	/* Test for strange behaviour which leads to crashes */
728	if ((bcount =
729	ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
730	printk
731	("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
732	i, j, bcount);
733	error = 15;
734	ns_init_card_error(card, error);
735	return error;
736	}
737
738	/* Allocate iovec buffers */
739	skb_queue_head_init(list: &card->iovpool.queue);
740	card->iovpool.count = 0;
741	for (j = 0; j < NUM_IOVB; j++) {
742	struct sk_buff *iovb;
743	iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
744	if (iovb == NULL) {
745	printk
746	("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
747	i, j, NUM_IOVB);
748	error = 16;
749	ns_init_card_error(card, error);
750	return error;
751	}
752	NS_PRV_BUFTYPE(iovb) = BUF_NONE;
753	skb_queue_tail(list: &card->iovpool.queue, newsk: iovb);
754	card->iovpool.count++;
755	}
756
757	/* Configure NICStAR */
758	if (card->rct_size == 4096)
759	ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
760	else /* (card->rct_size == 16384) */
761	ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
762
763	card->efbie = 1;
764
765	/* Register device */
766	card->atmdev = atm_dev_register(type: "nicstar", parent: &card->pcidev->dev, ops: &atm_ops,
767	number: -1, NULL);
768	if (card->atmdev == NULL) {
769	printk("nicstar%d: can't register device.\n", i);
770	error = 17;
771	ns_init_card_error(card, error);
772	return error;
773	}
774
775	if (mac[i] == NULL || !mac_pton(s: mac[i], mac: card->atmdev->esi)) {
776	nicstar_read_eprom(base: card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777	buffer: card->atmdev->esi, nbytes: 6);
778	if (ether_addr_equal(addr1: card->atmdev->esi, addr2: "\x00\x00\x00\x00\x00\x00")) {
779	nicstar_read_eprom(base: card->membase,
780	NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
781	buffer: card->atmdev->esi, nbytes: 6);
782	}
783	}
784
785	printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
786
787	card->atmdev->dev_data = card;
788	card->atmdev->ci_range.vpi_bits = card->vpibits;
789	card->atmdev->ci_range.vci_bits = card->vcibits;
790	card->atmdev->link_rate = card->max_pcr;
791	card->atmdev->phy = NULL;
792
793	#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
794	if (card->max_pcr == ATM_OC3_PCR)
795	suni_init(dev: card->atmdev);
796	#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
797
798	#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
799	if (card->max_pcr == ATM_25_PCR)
800	idt77105_init(dev: card->atmdev);
801	#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
802
803	if (card->atmdev->phy && card->atmdev->phy->start)
804	card->atmdev->phy->start(card->atmdev);
805
806	writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
807	NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
808	NS_CFG_PHYIE, addr: card->membase + CFG);
809
810	num_cards++;
811
812	return error;
813	}
814
815	static void ns_init_card_error(ns_dev *card, int error)
816	{
817	if (error >= 17) {
818	writel(val: 0x00000000, addr: card->membase + CFG);
819	}
820	if (error >= 16) {
821	struct sk_buff *iovb;
822	while ((iovb = skb_dequeue(list: &card->iovpool.queue)) != NULL)
823	dev_kfree_skb_any(skb: iovb);
824	}
825	if (error >= 15) {
826	struct sk_buff *sb;
827	while ((sb = skb_dequeue(list: &card->sbpool.queue)) != NULL)
828	dev_kfree_skb_any(skb: sb);
829	free_scq(card, scq: card->scq0, NULL);
830	}
831	if (error >= 14) {
832	struct sk_buff *lb;
833	while ((lb = skb_dequeue(list: &card->lbpool.queue)) != NULL)
834	dev_kfree_skb_any(skb: lb);
835	}
836	if (error >= 13) {
837	struct sk_buff *hb;
838	while ((hb = skb_dequeue(list: &card->hbpool.queue)) != NULL)
839	dev_kfree_skb_any(skb: hb);
840	}
841	if (error >= 12) {
842	dma_free_coherent(dev: &card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
843	cpu_addr: card->rsq.org, dma_handle: card->rsq.dma);
844	}
845	if (error >= 11) {
846	dma_free_coherent(dev: &card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
847	cpu_addr: card->tsq.org, dma_handle: card->tsq.dma);
848	}
849	if (error >= 10) {
850	free_irq(card->pcidev->irq, card);
851	}
852	if (error >= 4) {
853	iounmap(addr: card->membase);
854	}
855	if (error >= 3) {
856	pci_disable_device(dev: card->pcidev);
857	kfree(objp: card);
858	}
859	}
860
861	static scq_info *get_scq(ns_dev *card, int size, u32 scd)
862	{
863	scq_info *scq;
864
865	if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
866	return NULL;
867
868	scq = kmalloc(size: sizeof(*scq), GFP_KERNEL);
869	if (!scq)
870	return NULL;
871	scq->org = dma_alloc_coherent(dev: &card->pcidev->dev,
872	size: 2 * size, dma_handle: &scq->dma, GFP_KERNEL);
873	if (!scq->org) {
874	kfree(objp: scq);
875	return NULL;
876	}
877	scq->skb = kcalloc(n: size / NS_SCQE_SIZE, size: sizeof(*scq->skb),
878	GFP_KERNEL);
879	if (!scq->skb) {
880	dma_free_coherent(dev: &card->pcidev->dev,
881	size: 2 * size, cpu_addr: scq->org, dma_handle: scq->dma);
882	kfree(objp: scq);
883	return NULL;
884	}
885	scq->num_entries = size / NS_SCQE_SIZE;
886	scq->base = PTR_ALIGN(scq->org, size);
887	scq->next = scq->base;
888	scq->last = scq->base + (scq->num_entries - 1);
889	scq->tail = scq->last;
890	scq->scd = scd;
891	scq->tbd_count = 0;
892	init_waitqueue_head(&scq->scqfull_waitq);
893	scq->full = 0;
894	spin_lock_init(&scq->lock);
895
896	return scq;
897	}
898
899	/* For variable rate SCQ vcc must be NULL */
900	static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
901	{
902	int i;
903
904	if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
905	for (i = 0; i < scq->num_entries; i++) {
906	if (scq->skb[i] != NULL) {
907	vcc = ATM_SKB(scq->skb[i])->vcc;
908	if (vcc->pop != NULL)
909	vcc->pop(vcc, scq->skb[i]);
910	else
911	dev_kfree_skb_any(skb: scq->skb[i]);
912	}
913	} else { /* vcc must be != NULL */
914
915	if (vcc == NULL) {
916	printk
917	("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
918	for (i = 0; i < scq->num_entries; i++)
919	dev_kfree_skb_any(skb: scq->skb[i]);
920	} else
921	for (i = 0; i < scq->num_entries; i++) {
922	if (scq->skb[i] != NULL) {
923	if (vcc->pop != NULL)
924	vcc->pop(vcc, scq->skb[i]);
925	else
926	dev_kfree_skb_any(skb: scq->skb[i]);
927	}
928	}
929	}
930	kfree(objp: scq->skb);
931	dma_free_coherent(dev: &card->pcidev->dev,
932	size: 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
933	VBR_SCQSIZE : CBR_SCQSIZE),
934	cpu_addr: scq->org, dma_handle: scq->dma);
935	kfree(objp: scq);
936	}
937
938	/* The handles passed must be pointers to the sk_buff containing the small
939	or large buffer(s) cast to u32. */
940	static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
941	{
942	struct sk_buff *handle1, *handle2;
943	int id1, id2;
944	u32 addr1, addr2;
945	u32 stat;
946	unsigned long flags;
947
948	/* *BARF* */
949	handle2 = NULL;
950	addr2 = 0;
951	handle1 = skb;
952	addr1 = dma_map_single(&card->pcidev->dev,
953	skb->data,
954	(NS_PRV_BUFTYPE(skb) == BUF_SM
955	? NS_SMSKBSIZE : NS_LGSKBSIZE),
956	DMA_TO_DEVICE);
957	NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
958
959	#ifdef GENERAL_DEBUG
960	if (!addr1)
961	printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
962	card->index);
963	#endif /* GENERAL_DEBUG */
964
965	stat = readl(addr: card->membase + STAT);
966	card->sbfqc = ns_stat_sfbqc_get(stat);
967	card->lbfqc = ns_stat_lfbqc_get(stat);
968	if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
969	if (!addr2) {
970	if (card->sm_addr) {
971	addr2 = card->sm_addr;
972	handle2 = card->sm_handle;
973	card->sm_addr = 0x00000000;
974	card->sm_handle = NULL;
975	} else { /* (!sm_addr) */
976
977	card->sm_addr = addr1;
978	card->sm_handle = handle1;
979	}
980	}
981	} else { /* buf_type == BUF_LG */
982
983	if (!addr2) {
984	if (card->lg_addr) {
985	addr2 = card->lg_addr;
986	handle2 = card->lg_handle;
987	card->lg_addr = 0x00000000;
988	card->lg_handle = NULL;
989	} else { /* (!lg_addr) */
990
991	card->lg_addr = addr1;
992	card->lg_handle = handle1;
993	}
994	}
995	}
996
997	if (addr2) {
998	if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
999	if (card->sbfqc >= card->sbnr.max) {
1000	skb_unlink(skb: handle1, list: &card->sbpool.queue);
1001	dev_kfree_skb_any(skb: handle1);
1002	skb_unlink(skb: handle2, list: &card->sbpool.queue);
1003	dev_kfree_skb_any(skb: handle2);
1004	return;
1005	} else
1006	card->sbfqc += 2;
1007	} else { /* (buf_type == BUF_LG) */
1008
1009	if (card->lbfqc >= card->lbnr.max) {
1010	skb_unlink(skb: handle1, list: &card->lbpool.queue);
1011	dev_kfree_skb_any(skb: handle1);
1012	skb_unlink(skb: handle2, list: &card->lbpool.queue);
1013	dev_kfree_skb_any(skb: handle2);
1014	return;
1015	} else
1016	card->lbfqc += 2;
1017	}
1018
1019	id1 = idr_alloc(&card->idr, ptr: handle1, start: 0, end: 0, GFP_ATOMIC);
1020	if (id1 < 0)
1021	goto out;
1022
1023	id2 = idr_alloc(&card->idr, ptr: handle2, start: 0, end: 0, GFP_ATOMIC);
1024	if (id2 < 0)
1025	goto out;
1026
1027	spin_lock_irqsave(&card->res_lock, flags);
1028	while (CMD_BUSY(card)) ;
1029	writel(val: addr2, addr: card->membase + DR3);
1030	writel(val: id2, addr: card->membase + DR2);
1031	writel(val: addr1, addr: card->membase + DR1);
1032	writel(val: id1, addr: card->membase + DR0);
1033	writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1034	addr: card->membase + CMD);
1035	spin_unlock_irqrestore(lock: &card->res_lock, flags);
1036
1037	XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1038	card->index,
1039	(NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1040	addr1, addr2);
1041	}
1042
1043	if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1044	card->lbfqc >= card->lbnr.min) {
1045	card->efbie = 1;
1046	writel(val: (readl(addr: card->membase + CFG) | NS_CFG_EFBIE),
1047	addr: card->membase + CFG);
1048	}
1049
1050	out:
1051	return;
1052	}
1053
1054	static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1055	{
1056	u32 stat_r;
1057	ns_dev *card;
1058	struct atm_dev *dev;
1059	unsigned long flags;
1060
1061	card = (ns_dev *) dev_id;
1062	dev = card->atmdev;
1063	card->intcnt++;
1064
1065	PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1066
1067	spin_lock_irqsave(&card->int_lock, flags);
1068
1069	stat_r = readl(addr: card->membase + STAT);
1070
1071	/* Transmit Status Indicator has been written to T. S. Queue */
1072	if (stat_r & NS_STAT_TSIF) {
1073	TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1074	process_tsq(card);
1075	writel(NS_STAT_TSIF, addr: card->membase + STAT);
1076	}
1077
1078	/* Incomplete CS-PDU has been transmitted */
1079	if (stat_r & NS_STAT_TXICP) {
1080	writel(NS_STAT_TXICP, addr: card->membase + STAT);
1081	TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1082	card->index);
1083	}
1084
1085	/* Transmit Status Queue 7/8 full */
1086	if (stat_r & NS_STAT_TSQF) {
1087	writel(NS_STAT_TSQF, addr: card->membase + STAT);
1088	PRINTK("nicstar%d: TSQ full.\n", card->index);
1089	process_tsq(card);
1090	}
1091
1092	/* Timer overflow */
1093	if (stat_r & NS_STAT_TMROF) {
1094	writel(NS_STAT_TMROF, addr: card->membase + STAT);
1095	PRINTK("nicstar%d: Timer overflow.\n", card->index);
1096	}
1097
1098	/* PHY device interrupt signal active */
1099	if (stat_r & NS_STAT_PHYI) {
1100	writel(NS_STAT_PHYI, addr: card->membase + STAT);
1101	PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1102	if (dev->phy && dev->phy->interrupt) {
1103	dev->phy->interrupt(dev);
1104	}
1105	}
1106
1107	/* Small Buffer Queue is full */
1108	if (stat_r & NS_STAT_SFBQF) {
1109	writel(NS_STAT_SFBQF, addr: card->membase + STAT);
1110	printk("nicstar%d: Small free buffer queue is full.\n",
1111	card->index);
1112	}
1113
1114	/* Large Buffer Queue is full */
1115	if (stat_r & NS_STAT_LFBQF) {
1116	writel(NS_STAT_LFBQF, addr: card->membase + STAT);
1117	printk("nicstar%d: Large free buffer queue is full.\n",
1118	card->index);
1119	}
1120
1121	/* Receive Status Queue is full */
1122	if (stat_r & NS_STAT_RSQF) {
1123	writel(NS_STAT_RSQF, addr: card->membase + STAT);
1124	printk("nicstar%d: RSQ full.\n", card->index);
1125	process_rsq(card);
1126	}
1127
1128	/* Complete CS-PDU received */
1129	if (stat_r & NS_STAT_EOPDU) {
1130	RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1131	process_rsq(card);
1132	writel(NS_STAT_EOPDU, addr: card->membase + STAT);
1133	}
1134
1135	/* Raw cell received */
1136	if (stat_r & NS_STAT_RAWCF) {
1137	writel(NS_STAT_RAWCF, addr: card->membase + STAT);
1138	#ifndef RCQ_SUPPORT
1139	printk("nicstar%d: Raw cell received and no support yet...\n",
1140	card->index);
1141	#endif /* RCQ_SUPPORT */
1142	/* NOTE: the following procedure may keep a raw cell pending until the
1143	next interrupt. As this preliminary support is only meant to
1144	avoid buffer leakage, this is not an issue. */
1145	while (readl(addr: card->membase + RAWCT) != card->rawch) {
1146
1147	if (ns_rcqe_islast(card->rawcell)) {
1148	struct sk_buff *oldbuf;
1149
1150	oldbuf = card->rcbuf;
1151	card->rcbuf = idr_find(&card->idr,
1152	ns_rcqe_nextbufhandle(card->rawcell));
1153	card->rawch = NS_PRV_DMA(card->rcbuf);
1154	card->rawcell = (struct ns_rcqe *)
1155	card->rcbuf->data;
1156	recycle_rx_buf(card, skb: oldbuf);
1157	} else {
1158	card->rawch += NS_RCQE_SIZE;
1159	card->rawcell++;
1160	}
1161	}
1162	}
1163
1164	/* Small buffer queue is empty */
1165	if (stat_r & NS_STAT_SFBQE) {
1166	int i;
1167	struct sk_buff *sb;
1168
1169	writel(NS_STAT_SFBQE, addr: card->membase + STAT);
1170	printk("nicstar%d: Small free buffer queue empty.\n",
1171	card->index);
1172	for (i = 0; i < card->sbnr.min; i++) {
1173	sb = dev_alloc_skb(NS_SMSKBSIZE);
1174	if (sb == NULL) {
1175	writel(readl(addr: card->membase + CFG) &
1176	~NS_CFG_EFBIE, addr: card->membase + CFG);
1177	card->efbie = 0;
1178	break;
1179	}
1180	NS_PRV_BUFTYPE(sb) = BUF_SM;
1181	skb_queue_tail(list: &card->sbpool.queue, newsk: sb);
1182	skb_reserve(skb: sb, NS_AAL0_HEADER);
1183	push_rxbufs(card, skb: sb);
1184	}
1185	card->sbfqc = i;
1186	process_rsq(card);
1187	}
1188
1189	/* Large buffer queue empty */
1190	if (stat_r & NS_STAT_LFBQE) {
1191	int i;
1192	struct sk_buff *lb;
1193
1194	writel(NS_STAT_LFBQE, addr: card->membase + STAT);
1195	printk("nicstar%d: Large free buffer queue empty.\n",
1196	card->index);
1197	for (i = 0; i < card->lbnr.min; i++) {
1198	lb = dev_alloc_skb(NS_LGSKBSIZE);
1199	if (lb == NULL) {
1200	writel(readl(addr: card->membase + CFG) &
1201	~NS_CFG_EFBIE, addr: card->membase + CFG);
1202	card->efbie = 0;
1203	break;
1204	}
1205	NS_PRV_BUFTYPE(lb) = BUF_LG;
1206	skb_queue_tail(list: &card->lbpool.queue, newsk: lb);
1207	skb_reserve(skb: lb, NS_SMBUFSIZE);
1208	push_rxbufs(card, skb: lb);
1209	}
1210	card->lbfqc = i;
1211	process_rsq(card);
1212	}
1213
1214	/* Receive Status Queue is 7/8 full */
1215	if (stat_r & NS_STAT_RSQAF) {
1216	writel(NS_STAT_RSQAF, addr: card->membase + STAT);
1217	RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1218	process_rsq(card);
1219	}
1220
1221	spin_unlock_irqrestore(lock: &card->int_lock, flags);
1222	PRINTK("nicstar%d: end of interrupt service\n", card->index);
1223	return IRQ_HANDLED;
1224	}
1225
1226	static int ns_open(struct atm_vcc *vcc)
1227	{
1228	ns_dev *card;
1229	vc_map *vc;
1230	unsigned long tmpl, modl;
1231	int tcr, tcra; /* target cell rate, and absolute value */
1232	int n = 0; /* Number of entries in the TST. Initialized to remove
1233	the compiler warning. */
1234	u32 u32d[4];
1235	int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1236	warning. How I wish compilers were clever enough to
1237	tell which variables can truly be used
1238	uninitialized... */
1239	int inuse; /* tx or rx vc already in use by another vcc */
1240	short vpi = vcc->vpi;
1241	int vci = vcc->vci;
1242
1243	card = (ns_dev *) vcc->dev->dev_data;
1244	PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1245	vci);
1246	if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1247	PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1248	return -EINVAL;
1249	}
1250
1251	vc = &(card->vcmap[vpi << card->vcibits | vci]);
1252	vcc->dev_data = vc;
1253
1254	inuse = 0;
1255	if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1256	inuse = 1;
1257	if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1258	inuse += 2;
1259	if (inuse) {
1260	printk("nicstar%d: %s vci already in use.\n", card->index,
1261	inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1262	return -EINVAL;
1263	}
1264
1265	set_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1266
1267	/* NOTE: You are not allowed to modify an open connection's QOS. To change
1268	that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1269	needed to do that. */
1270	if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1271	scq_info *scq;
1272
1273	set_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1274	if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1275	/* Check requested cell rate and availability of SCD */
1276	if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1277	&& vcc->qos.txtp.min_pcr == 0) {
1278	PRINTK
1279	("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1280	card->index);
1281	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1282	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1283	return -EINVAL;
1284	}
1285
1286	tcr = atm_pcr_goal(tp: &(vcc->qos.txtp));
1287	tcra = tcr >= 0 ? tcr : -tcr;
1288
1289	PRINTK("nicstar%d: target cell rate = %d.\n",
1290	card->index, vcc->qos.txtp.max_pcr);
1291
1292	tmpl =
1293	(unsigned long)tcra *(unsigned long)
1294	NS_TST_NUM_ENTRIES;
1295	modl = tmpl % card->max_pcr;
1296
1297	n = (int)(tmpl / card->max_pcr);
1298	if (tcr > 0) {
1299	if (modl > 0)
1300	n++;
1301	} else if (tcr == 0) {
1302	if ((n =
1303	(card->tst_free_entries -
1304	NS_TST_RESERVED)) <= 0) {
1305	PRINTK
1306	("nicstar%d: no CBR bandwidth free.\n",
1307	card->index);
1308	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1309	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1310	return -EINVAL;
1311	}
1312	}
1313
1314	if (n == 0) {
1315	printk
1316	("nicstar%d: selected bandwidth < granularity.\n",
1317	card->index);
1318	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1319	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1320	return -EINVAL;
1321	}
1322
1323	if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1324	PRINTK
1325	("nicstar%d: not enough free CBR bandwidth.\n",
1326	card->index);
1327	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1328	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1329	return -EINVAL;
1330	} else
1331	card->tst_free_entries -= n;
1332
1333	XPRINTK("nicstar%d: writing %d tst entries.\n",
1334	card->index, n);
1335	for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1336	if (card->scd2vc[frscdi] == NULL) {
1337	card->scd2vc[frscdi] = vc;
1338	break;
1339	}
1340	}
1341	if (frscdi == NS_FRSCD_NUM) {
1342	PRINTK
1343	("nicstar%d: no SCD available for CBR channel.\n",
1344	card->index);
1345	card->tst_free_entries += n;
1346	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1347	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1348	return -EBUSY;
1349	}
1350
1351	vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1352
1353	scq = get_scq(card, CBR_SCQSIZE, scd: vc->cbr_scd);
1354	if (scq == NULL) {
1355	PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1356	card->index);
1357	card->scd2vc[frscdi] = NULL;
1358	card->tst_free_entries += n;
1359	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1360	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1361	return -ENOMEM;
1362	}
1363	vc->scq = scq;
1364	u32d[0] = scq_virt_to_bus(scq, scq->base);
1365	u32d[1] = (u32) 0x00000000;
1366	u32d[2] = (u32) 0xffffffff;
1367	u32d[3] = (u32) 0x00000000;
1368	ns_write_sram(card, sram_address: vc->cbr_scd, value: u32d, count: 4);
1369
1370	fill_tst(card, n, vc);
1371	} else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1372	vc->cbr_scd = 0x00000000;
1373	vc->scq = card->scq0;
1374	}
1375
1376	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1377	vc->tx = 1;
1378	vc->tx_vcc = vcc;
1379	vc->tbd_count = 0;
1380	}
1381	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1382	u32 status;
1383
1384	vc->rx = 1;
1385	vc->rx_vcc = vcc;
1386	vc->rx_iov = NULL;
1387
1388	/* Open the connection in hardware */
1389	if (vcc->qos.aal == ATM_AAL5)
1390	status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1391	else /* vcc->qos.aal == ATM_AAL0 */
1392	status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1393	#ifdef RCQ_SUPPORT
1394	status |= NS_RCTE_RAWCELLINTEN;
1395	#endif /* RCQ_SUPPORT */
1396	ns_write_sram(card,
1397	NS_RCT +
1398	(vpi << card->vcibits | vci) *
1399	NS_RCT_ENTRY_SIZE, value: &status, count: 1);
1400	}
1401
1402	}
1403
1404	set_bit(nr: ATM_VF_READY, addr: &vcc->flags);
1405	return 0;
1406	}
1407
1408	static void ns_close(struct atm_vcc *vcc)
1409	{
1410	vc_map *vc;
1411	ns_dev *card;
1412	u32 data;
1413	int i;
1414
1415	vc = vcc->dev_data;
1416	card = vcc->dev->dev_data;
1417	PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1418	(int)vcc->vpi, vcc->vci);
1419
1420	clear_bit(nr: ATM_VF_READY, addr: &vcc->flags);
1421
1422	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1423	u32 addr;
1424	unsigned long flags;
1425
1426	addr =
1427	NS_RCT +
1428	(vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1429	spin_lock_irqsave(&card->res_lock, flags);
1430	while (CMD_BUSY(card)) ;
1431	writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1432	addr: card->membase + CMD);
1433	spin_unlock_irqrestore(lock: &card->res_lock, flags);
1434
1435	vc->rx = 0;
1436	if (vc->rx_iov != NULL) {
1437	struct sk_buff *iovb;
1438	u32 stat;
1439
1440	stat = readl(addr: card->membase + STAT);
1441	card->sbfqc = ns_stat_sfbqc_get(stat);
1442	card->lbfqc = ns_stat_lfbqc_get(stat);
1443
1444	PRINTK
1445	("nicstar%d: closing a VC with pending rx buffers.\n",
1446	card->index);
1447	iovb = vc->rx_iov;
1448	recycle_iovec_rx_bufs(card, iov: (struct iovec *)iovb->data,
1449	NS_PRV_IOVCNT(iovb));
1450	NS_PRV_IOVCNT(iovb) = 0;
1451	spin_lock_irqsave(&card->int_lock, flags);
1452	recycle_iov_buf(card, iovb);
1453	spin_unlock_irqrestore(lock: &card->int_lock, flags);
1454	vc->rx_iov = NULL;
1455	}
1456	}
1457
1458	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1459	vc->tx = 0;
1460	}
1461
1462	if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1463	unsigned long flags;
1464	ns_scqe *scqep;
1465	scq_info *scq;
1466
1467	scq = vc->scq;
1468
1469	for (;;) {
1470	spin_lock_irqsave(&scq->lock, flags);
1471	scqep = scq->next;
1472	if (scqep == scq->base)
1473	scqep = scq->last;
1474	else
1475	scqep--;
1476	if (scqep == scq->tail) {
1477	spin_unlock_irqrestore(lock: &scq->lock, flags);
1478	break;
1479	}
1480	/* If the last entry is not a TSR, place one in the SCQ in order to
1481	be able to completely drain it and then close. */
1482	if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1483	ns_scqe tsr;
1484	u32 scdi, scqi;
1485	u32 data;
1486	int index;
1487
1488	tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1489	scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1490	scqi = scq->next - scq->base;
1491	tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1492	tsr.word_3 = 0x00000000;
1493	tsr.word_4 = 0x00000000;
1494	*scq->next = tsr;
1495	index = (int)scqi;
1496	scq->skb[index] = NULL;
1497	if (scq->next == scq->last)
1498	scq->next = scq->base;
1499	else
1500	scq->next++;
1501	data = scq_virt_to_bus(scq, scq->next);
1502	ns_write_sram(card, sram_address: scq->scd, value: &data, count: 1);
1503	}
1504	spin_unlock_irqrestore(lock: &scq->lock, flags);
1505	schedule();
1506	}
1507
1508	/* Free all TST entries */
1509	data = NS_TST_OPCODE_VARIABLE;
1510	for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1511	if (card->tste2vc[i] == vc) {
1512	ns_write_sram(card, sram_address: card->tst_addr + i, value: &data,
1513	count: 1);
1514	card->tste2vc[i] = NULL;
1515	card->tst_free_entries++;
1516	}
1517	}
1518
1519	card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1520	free_scq(card, scq: vc->scq, vcc);
1521	}
1522
1523	/* remove all references to vcc before deleting it */
1524	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1525	unsigned long flags;
1526	scq_info *scq = card->scq0;
1527
1528	spin_lock_irqsave(&scq->lock, flags);
1529
1530	for (i = 0; i < scq->num_entries; i++) {
1531	if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1532	ATM_SKB(scq->skb[i])->vcc = NULL;
1533	atm_return(vcc, truesize: scq->skb[i]->truesize);
1534	PRINTK
1535	("nicstar: deleted pending vcc mapping\n");
1536	}
1537	}
1538
1539	spin_unlock_irqrestore(lock: &scq->lock, flags);
1540	}
1541
1542	vcc->dev_data = NULL;
1543	clear_bit(nr: ATM_VF_PARTIAL, addr: &vcc->flags);
1544	clear_bit(nr: ATM_VF_ADDR, addr: &vcc->flags);
1545
1546	#ifdef RX_DEBUG
1547	{
1548	u32 stat, cfg;
1549	stat = readl(card->membase + STAT);
1550	cfg = readl(card->membase + CFG);
1551	printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1552	printk
1553	("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1554	card->tsq.base, card->tsq.next,
1555	card->tsq.last, readl(card->membase + TSQT));
1556	printk
1557	("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1558	card->rsq.base, card->rsq.next,
1559	card->rsq.last, readl(card->membase + RSQT));
1560	printk("Empty free buffer queue interrupt %s \n",
1561	card->efbie ? "enabled" : "disabled");
1562	printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1563	ns_stat_sfbqc_get(stat), card->sbpool.count,
1564	ns_stat_lfbqc_get(stat), card->lbpool.count);
1565	printk("hbpool.count = %d iovpool.count = %d \n",
1566	card->hbpool.count, card->iovpool.count);
1567	}
1568	#endif /* RX_DEBUG */
1569	}
1570
1571	static void fill_tst(ns_dev * card, int n, vc_map * vc)
1572	{
1573	u32 new_tst;
1574	unsigned long cl;
1575	int e, r;
1576	u32 data;
1577
1578	/* It would be very complicated to keep the two TSTs synchronized while
1579	assuring that writes are only made to the inactive TST. So, for now I
1580	will use only one TST. If problems occur, I will change this again */
1581
1582	new_tst = card->tst_addr;
1583
1584	/* Fill procedure */
1585
1586	for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1587	if (card->tste2vc[e] == NULL)
1588	break;
1589	}
1590	if (e == NS_TST_NUM_ENTRIES) {
1591	printk("nicstar%d: No free TST entries found. \n", card->index);
1592	return;
1593	}
1594
1595	r = n;
1596	cl = NS_TST_NUM_ENTRIES;
1597	data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1598
1599	while (r > 0) {
1600	if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1601	card->tste2vc[e] = vc;
1602	ns_write_sram(card, sram_address: new_tst + e, value: &data, count: 1);
1603	cl -= NS_TST_NUM_ENTRIES;
1604	r--;
1605	}
1606
1607	if (++e == NS_TST_NUM_ENTRIES) {
1608	e = 0;
1609	}
1610	cl += n;
1611	}
1612
1613	/* End of fill procedure */
1614
1615	data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1616	ns_write_sram(card, sram_address: new_tst + NS_TST_NUM_ENTRIES, value: &data, count: 1);
1617	ns_write_sram(card, sram_address: card->tst_addr + NS_TST_NUM_ENTRIES, value: &data, count: 1);
1618	card->tst_addr = new_tst;
1619	}
1620
1621	static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
1622	{
1623	ns_dev *card;
1624	vc_map *vc;
1625	scq_info *scq;
1626	unsigned long buflen;
1627	ns_scqe scqe;
1628	u32 flags; /* TBD flags, not CPU flags */
1629
1630	card = vcc->dev->dev_data;
1631	TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1632	if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1633	printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1634	card->index);
1635	atomic_inc(v: &vcc->stats->tx_err);
1636	dev_kfree_skb_any(skb);
1637	return -EINVAL;
1638	}
1639
1640	if (!vc->tx) {
1641	printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1642	card->index);
1643	atomic_inc(v: &vcc->stats->tx_err);
1644	dev_kfree_skb_any(skb);
1645	return -EINVAL;
1646	}
1647
1648	if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1649	printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1650	card->index);
1651	atomic_inc(v: &vcc->stats->tx_err);
1652	dev_kfree_skb_any(skb);
1653	return -EINVAL;
1654	}
1655
1656	if (skb_shinfo(skb)->nr_frags != 0) {
1657	printk("nicstar%d: No scatter-gather yet.\n", card->index);
1658	atomic_inc(v: &vcc->stats->tx_err);
1659	dev_kfree_skb_any(skb);
1660	return -EINVAL;
1661	}
1662
1663	ATM_SKB(skb)->vcc = vcc;
1664
1665	NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1666	skb->len, DMA_TO_DEVICE);
1667
1668	if (vcc->qos.aal == ATM_AAL5) {
1669	buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1670	flags = NS_TBD_AAL5;
1671	scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1672	scqe.word_3 = cpu_to_le32(skb->len);
1673	scqe.word_4 =
1674	ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1675	ATM_SKB(skb)->
1676	atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1677	flags |= NS_TBD_EOPDU;
1678	} else { /* (vcc->qos.aal == ATM_AAL0) */
1679
1680	buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1681	flags = NS_TBD_AAL0;
1682	scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1683	scqe.word_3 = cpu_to_le32(0x00000000);
1684	if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1685	flags |= NS_TBD_EOPDU;
1686	scqe.word_4 =
1687	cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1688	/* Force the VPI/VCI to be the same as in VCC struct */
1689	scqe.word_4 |=
1690	cpu_to_le32((((u32) vcc->
1691	vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1692	vci) <<
1693	NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1694	}
1695
1696	if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1697	scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1698	scq = ((vc_map *) vcc->dev_data)->scq;
1699	} else {
1700	scqe.word_1 =
1701	ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1702	scq = card->scq0;
1703	}
1704
1705	if (push_scqe(card, vc, scq, tbd: &scqe, skb, may_sleep) != 0) {
1706	atomic_inc(v: &vcc->stats->tx_err);
1707	dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1708	DMA_TO_DEVICE);
1709	dev_kfree_skb_any(skb);
1710	return -EIO;
1711	}
1712	atomic_inc(v: &vcc->stats->tx);
1713
1714	return 0;
1715	}
1716
1717	static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1718	{
1719	return _ns_send(vcc, skb, may_sleep: true);
1720	}
1721
1722	static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
1723	{
1724	return _ns_send(vcc, skb, may_sleep: false);
1725	}
1726
1727	static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1728	struct sk_buff *skb, bool may_sleep)
1729	{
1730	unsigned long flags;
1731	ns_scqe tsr;
1732	u32 scdi, scqi;
1733	int scq_is_vbr;
1734	u32 data;
1735	int index;
1736
1737	spin_lock_irqsave(&scq->lock, flags);
1738	while (scq->tail == scq->next) {
1739	if (!may_sleep) {
1740	spin_unlock_irqrestore(lock: &scq->lock, flags);
1741	printk("nicstar%d: Error pushing TBD.\n", card->index);
1742	return 1;
1743	}
1744
1745	scq->full = 1;
1746	wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1747	scq->tail != scq->next,
1748	scq->lock,
1749	SCQFULL_TIMEOUT);
1750
1751	if (scq->full) {
1752	spin_unlock_irqrestore(lock: &scq->lock, flags);
1753	printk("nicstar%d: Timeout pushing TBD.\n",
1754	card->index);
1755	return 1;
1756	}
1757	}
1758	*scq->next = *tbd;
1759	index = (int)(scq->next - scq->base);
1760	scq->skb[index] = skb;
1761	XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1762	card->index, skb, index);
1763	XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1764	card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1765	le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1766	scq->next);
1767	if (scq->next == scq->last)
1768	scq->next = scq->base;
1769	else
1770	scq->next++;
1771
1772	vc->tbd_count++;
1773	if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1774	scq->tbd_count++;
1775	scq_is_vbr = 1;
1776	} else
1777	scq_is_vbr = 0;
1778
1779	if (vc->tbd_count >= MAX_TBD_PER_VC
1780	|| scq->tbd_count >= MAX_TBD_PER_SCQ) {
1781	int has_run = 0;
1782
1783	while (scq->tail == scq->next) {
1784	if (!may_sleep) {
1785	data = scq_virt_to_bus(scq, scq->next);
1786	ns_write_sram(card, sram_address: scq->scd, value: &data, count: 1);
1787	spin_unlock_irqrestore(lock: &scq->lock, flags);
1788	printk("nicstar%d: Error pushing TSR.\n",
1789	card->index);
1790	return 0;
1791	}
1792
1793	scq->full = 1;
1794	if (has_run++)
1795	break;
1796	wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1797	scq->tail != scq->next,
1798	scq->lock,
1799	SCQFULL_TIMEOUT);
1800	}
1801
1802	if (!scq->full) {
1803	tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1804	if (scq_is_vbr)
1805	scdi = NS_TSR_SCDISVBR;
1806	else
1807	scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1808	scqi = scq->next - scq->base;
1809	tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1810	tsr.word_3 = 0x00000000;
1811	tsr.word_4 = 0x00000000;
1812
1813	*scq->next = tsr;
1814	index = (int)scqi;
1815	scq->skb[index] = NULL;
1816	XPRINTK
1817	("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1818	card->index, le32_to_cpu(tsr.word_1),
1819	le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1820	le32_to_cpu(tsr.word_4), scq->next);
1821	if (scq->next == scq->last)
1822	scq->next = scq->base;
1823	else
1824	scq->next++;
1825	vc->tbd_count = 0;
1826	scq->tbd_count = 0;
1827	} else
1828	PRINTK("nicstar%d: Timeout pushing TSR.\n",
1829	card->index);
1830	}
1831	data = scq_virt_to_bus(scq, scq->next);
1832	ns_write_sram(card, sram_address: scq->scd, value: &data, count: 1);
1833
1834	spin_unlock_irqrestore(lock: &scq->lock, flags);
1835
1836	return 0;
1837	}
1838
1839	static void process_tsq(ns_dev * card)
1840	{
1841	u32 scdi;
1842	scq_info *scq;
1843	ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1844	int serviced_entries; /* flag indicating at least on entry was serviced */
1845
1846	serviced_entries = 0;
1847
1848	if (card->tsq.next == card->tsq.last)
1849	one_ahead = card->tsq.base;
1850	else
1851	one_ahead = card->tsq.next + 1;
1852
1853	if (one_ahead == card->tsq.last)
1854	two_ahead = card->tsq.base;
1855	else
1856	two_ahead = one_ahead + 1;
1857
1858	while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1859	!ns_tsi_isempty(two_ahead))
1860	/* At most two empty, as stated in the 77201 errata */
1861	{
1862	serviced_entries = 1;
1863
1864	/* Skip the one or two possible empty entries */
1865	while (ns_tsi_isempty(card->tsq.next)) {
1866	if (card->tsq.next == card->tsq.last)
1867	card->tsq.next = card->tsq.base;
1868	else
1869	card->tsq.next++;
1870	}
1871
1872	if (!ns_tsi_tmrof(card->tsq.next)) {
1873	scdi = ns_tsi_getscdindex(card->tsq.next);
1874	if (scdi == NS_TSI_SCDISVBR)
1875	scq = card->scq0;
1876	else {
1877	if (card->scd2vc[scdi] == NULL) {
1878	printk
1879	("nicstar%d: could not find VC from SCD index.\n",
1880	card->index);
1881	ns_tsi_init(card->tsq.next);
1882	return;
1883	}
1884	scq = card->scd2vc[scdi]->scq;
1885	}
1886	drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1887	scq->full = 0;
1888	wake_up_interruptible(&(scq->scqfull_waitq));
1889	}
1890
1891	ns_tsi_init(card->tsq.next);
1892	previous = card->tsq.next;
1893	if (card->tsq.next == card->tsq.last)
1894	card->tsq.next = card->tsq.base;
1895	else
1896	card->tsq.next++;
1897
1898	if (card->tsq.next == card->tsq.last)
1899	one_ahead = card->tsq.base;
1900	else
1901	one_ahead = card->tsq.next + 1;
1902
1903	if (one_ahead == card->tsq.last)
1904	two_ahead = card->tsq.base;
1905	else
1906	two_ahead = one_ahead + 1;
1907	}
1908
1909	if (serviced_entries)
1910	writel(PTR_DIFF(previous, card->tsq.base),
1911	addr: card->membase + TSQH);
1912	}
1913
1914	static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1915	{
1916	struct atm_vcc *vcc;
1917	struct sk_buff *skb;
1918	int i;
1919	unsigned long flags;
1920
1921	XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1922	card->index, scq, pos);
1923	if (pos >= scq->num_entries) {
1924	printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1925	return;
1926	}
1927
1928	spin_lock_irqsave(&scq->lock, flags);
1929	i = (int)(scq->tail - scq->base);
1930	if (++i == scq->num_entries)
1931	i = 0;
1932	while (i != pos) {
1933	skb = scq->skb[i];
1934	XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1935	card->index, skb, i);
1936	if (skb != NULL) {
1937	dma_unmap_single(&card->pcidev->dev,
1938	NS_PRV_DMA(skb),
1939	skb->len,
1940	DMA_TO_DEVICE);
1941	vcc = ATM_SKB(skb)->vcc;
1942	if (vcc && vcc->pop != NULL) {
1943	vcc->pop(vcc, skb);
1944	} else {
1945	dev_kfree_skb_irq(skb);
1946	}
1947	scq->skb[i] = NULL;
1948	}
1949	if (++i == scq->num_entries)
1950	i = 0;
1951	}
1952	scq->tail = scq->base + pos;
1953	spin_unlock_irqrestore(lock: &scq->lock, flags);
1954	}
1955
1956	static void process_rsq(ns_dev * card)
1957	{
1958	ns_rsqe *previous;
1959
1960	if (!ns_rsqe_valid(card->rsq.next))
1961	return;
1962	do {
1963	dequeue_rx(card, rsqe: card->rsq.next);
1964	ns_rsqe_init(card->rsq.next);
1965	previous = card->rsq.next;
1966	if (card->rsq.next == card->rsq.last)
1967	card->rsq.next = card->rsq.base;
1968	else
1969	card->rsq.next++;
1970	} while (ns_rsqe_valid(card->rsq.next));
1971	writel(PTR_DIFF(previous, card->rsq.base), addr: card->membase + RSQH);
1972	}
1973
1974	static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1975	{
1976	u32 vpi, vci;
1977	vc_map *vc;
1978	struct sk_buff *iovb;
1979	struct iovec *iov;
1980	struct atm_vcc *vcc;
1981	struct sk_buff *skb;
1982	unsigned short aal5_len;
1983	int len;
1984	u32 stat;
1985	u32 id;
1986
1987	stat = readl(addr: card->membase + STAT);
1988	card->sbfqc = ns_stat_sfbqc_get(stat);
1989	card->lbfqc = ns_stat_lfbqc_get(stat);
1990
1991	id = le32_to_cpu(rsqe->buffer_handle);
1992	skb = idr_remove(&card->idr, id);
1993	if (!skb) {
1994	RXPRINTK(KERN_ERR
1995	"nicstar%d: skb not found!\n", card->index);
1996	return;
1997	}
1998	dma_sync_single_for_cpu(dev: &card->pcidev->dev,
1999	NS_PRV_DMA(skb),
2000	size: (NS_PRV_BUFTYPE(skb) == BUF_SM
2001	? NS_SMSKBSIZE : NS_LGSKBSIZE),
2002	dir: DMA_FROM_DEVICE);
2003	dma_unmap_single(&card->pcidev->dev,
2004	NS_PRV_DMA(skb),
2005	(NS_PRV_BUFTYPE(skb) == BUF_SM
2006	? NS_SMSKBSIZE : NS_LGSKBSIZE),
2007	DMA_FROM_DEVICE);
2008	vpi = ns_rsqe_vpi(rsqe);
2009	vci = ns_rsqe_vci(rsqe);
2010	if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2011	printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2012	card->index, vpi, vci);
2013	recycle_rx_buf(card, skb);
2014	return;
2015	}
2016
2017	vc = &(card->vcmap[vpi << card->vcibits | vci]);
2018	if (!vc->rx) {
2019	RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2020	card->index, vpi, vci);
2021	recycle_rx_buf(card, skb);
2022	return;
2023	}
2024
2025	vcc = vc->rx_vcc;
2026
2027	if (vcc->qos.aal == ATM_AAL0) {
2028	struct sk_buff *sb;
2029	unsigned char *cell;
2030	int i;
2031
2032	cell = skb->data;
2033	for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2034	sb = dev_alloc_skb(NS_SMSKBSIZE);
2035	if (!sb) {
2036	printk
2037	("nicstar%d: Can't allocate buffers for aal0.\n",
2038	card->index);
2039	atomic_add(i, v: &vcc->stats->rx_drop);
2040	break;
2041	}
2042	if (!atm_charge(vcc, truesize: sb->truesize)) {
2043	RXPRINTK
2044	("nicstar%d: atm_charge() dropped aal0 packets.\n",
2045	card->index);
2046	atomic_add(i: i - 1, v: &vcc->stats->rx_drop); /* already increased by 1 */
2047	dev_kfree_skb_any(skb: sb);
2048	break;
2049	}
2050	/* Rebuild the header */
2051	*((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2052	(ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2053	if (i == 1 && ns_rsqe_eopdu(rsqe))
2054	*((u32 *) sb->data) |= 0x00000002;
2055	skb_put(skb: sb, NS_AAL0_HEADER);
2056	memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2057	skb_put(skb: sb, ATM_CELL_PAYLOAD);
2058	ATM_SKB(sb)->vcc = vcc;
2059	__net_timestamp(skb: sb);
2060	vcc->push(vcc, sb);
2061	atomic_inc(v: &vcc->stats->rx);
2062	cell += ATM_CELL_PAYLOAD;
2063	}
2064
2065	recycle_rx_buf(card, skb);
2066	return;
2067	}
2068
2069	/* To reach this point, the AAL layer can only be AAL5 */
2070
2071	if ((iovb = vc->rx_iov) == NULL) {
2072	iovb = skb_dequeue(list: &(card->iovpool.queue));
2073	if (iovb == NULL) { /* No buffers in the queue */
2074	iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2075	if (iovb == NULL) {
2076	printk("nicstar%d: Out of iovec buffers.\n",
2077	card->index);
2078	atomic_inc(v: &vcc->stats->rx_drop);
2079	recycle_rx_buf(card, skb);
2080	return;
2081	}
2082	NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2083	} else if (--card->iovpool.count < card->iovnr.min) {
2084	struct sk_buff *new_iovb;
2085	if ((new_iovb =
2086	alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2087	NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2088	skb_queue_tail(list: &card->iovpool.queue, newsk: new_iovb);
2089	card->iovpool.count++;
2090	}
2091	}
2092	vc->rx_iov = iovb;
2093	NS_PRV_IOVCNT(iovb) = 0;
2094	iovb->len = 0;
2095	iovb->data = iovb->head;
2096	skb_reset_tail_pointer(skb: iovb);
2097	/* IMPORTANT: a pointer to the sk_buff containing the small or large
2098	buffer is stored as iovec base, NOT a pointer to the
2099	small or large buffer itself. */
2100	} else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2101	printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2102	atomic_inc(v: &vcc->stats->rx_err);
2103	recycle_iovec_rx_bufs(card, iov: (struct iovec *)iovb->data,
2104	NS_MAX_IOVECS);
2105	NS_PRV_IOVCNT(iovb) = 0;
2106	iovb->len = 0;
2107	iovb->data = iovb->head;
2108	skb_reset_tail_pointer(skb: iovb);
2109	}
2110	iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2111	iov->iov_base = (void *)skb;
2112	iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2113	iovb->len += iov->iov_len;
2114
2115	#ifdef EXTRA_DEBUG
2116	if (NS_PRV_IOVCNT(iovb) == 1) {
2117	if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2118	printk
2119	("nicstar%d: Expected a small buffer, and this is not one.\n",
2120	card->index);
2121	which_list(card, skb);
2122	atomic_inc(&vcc->stats->rx_err);
2123	recycle_rx_buf(card, skb);
2124	vc->rx_iov = NULL;
2125	recycle_iov_buf(card, iovb);
2126	return;
2127	}
2128	} else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2129
2130	if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2131	printk
2132	("nicstar%d: Expected a large buffer, and this is not one.\n",
2133	card->index);
2134	which_list(card, skb);
2135	atomic_inc(&vcc->stats->rx_err);
2136	recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2137	NS_PRV_IOVCNT(iovb));
2138	vc->rx_iov = NULL;
2139	recycle_iov_buf(card, iovb);
2140	return;
2141	}
2142	}
2143	#endif /* EXTRA_DEBUG */
2144
2145	if (ns_rsqe_eopdu(rsqe)) {
2146	/* This works correctly regardless of the endianness of the host */
2147	unsigned char *L1L2 = (unsigned char *)
2148	(skb->data + iov->iov_len - 6);
2149	aal5_len = L1L2[0] << 8 | L1L2[1];
2150	len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2151	if (ns_rsqe_crcerr(rsqe) ||
2152	len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2153	printk("nicstar%d: AAL5 CRC error", card->index);
2154	if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2155	printk(" - PDU size mismatch.\n");
2156	else
2157	printk(".\n");
2158	atomic_inc(v: &vcc->stats->rx_err);
2159	recycle_iovec_rx_bufs(card, iov: (struct iovec *)iovb->data,
2160	NS_PRV_IOVCNT(iovb));
2161	vc->rx_iov = NULL;
2162	recycle_iov_buf(card, iovb);
2163	return;
2164	}
2165
2166	/* By this point we (hopefully) have a complete SDU without errors. */
2167
2168	if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2169	/* skb points to a small buffer */
2170	if (!atm_charge(vcc, truesize: skb->truesize)) {
2171	push_rxbufs(card, skb);
2172	atomic_inc(v: &vcc->stats->rx_drop);
2173	} else {
2174	skb_put(skb, len);
2175	dequeue_sm_buf(card, sb: skb);
2176	ATM_SKB(skb)->vcc = vcc;
2177	__net_timestamp(skb);
2178	vcc->push(vcc, skb);
2179	atomic_inc(v: &vcc->stats->rx);
2180	}
2181	} else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2182	struct sk_buff *sb;
2183
2184	sb = (struct sk_buff *)(iov - 1)->iov_base;
2185	/* skb points to a large buffer */
2186
2187	if (len <= NS_SMBUFSIZE) {
2188	if (!atm_charge(vcc, truesize: sb->truesize)) {
2189	push_rxbufs(card, skb: sb);
2190	atomic_inc(v: &vcc->stats->rx_drop);
2191	} else {
2192	skb_put(skb: sb, len);
2193	dequeue_sm_buf(card, sb);
2194	ATM_SKB(sb)->vcc = vcc;
2195	__net_timestamp(skb: sb);
2196	vcc->push(vcc, sb);
2197	atomic_inc(v: &vcc->stats->rx);
2198	}
2199
2200	push_rxbufs(card, skb);
2201
2202	} else { /* len > NS_SMBUFSIZE, the usual case */
2203
2204	if (!atm_charge(vcc, truesize: skb->truesize)) {
2205	push_rxbufs(card, skb);
2206	atomic_inc(v: &vcc->stats->rx_drop);
2207	} else {
2208	dequeue_lg_buf(card, lb: skb);
2209	skb_push(skb, NS_SMBUFSIZE);
2210	skb_copy_from_linear_data(skb: sb, to: skb->data,
2211	NS_SMBUFSIZE);
2212	skb_put(skb, len: len - NS_SMBUFSIZE);
2213	ATM_SKB(skb)->vcc = vcc;
2214	__net_timestamp(skb);
2215	vcc->push(vcc, skb);
2216	atomic_inc(v: &vcc->stats->rx);
2217	}
2218
2219	push_rxbufs(card, skb: sb);
2220
2221	}
2222
2223	} else { /* Must push a huge buffer */
2224
2225	struct sk_buff *hb, *sb, *lb;
2226	int remaining, tocopy;
2227	int j;
2228
2229	hb = skb_dequeue(list: &(card->hbpool.queue));
2230	if (hb == NULL) { /* No buffers in the queue */
2231
2232	hb = dev_alloc_skb(NS_HBUFSIZE);
2233	if (hb == NULL) {
2234	printk
2235	("nicstar%d: Out of huge buffers.\n",
2236	card->index);
2237	atomic_inc(v: &vcc->stats->rx_drop);
2238	recycle_iovec_rx_bufs(card,
2239	iov: (struct iovec *)
2240	iovb->data,
2241	NS_PRV_IOVCNT(iovb));
2242	vc->rx_iov = NULL;
2243	recycle_iov_buf(card, iovb);
2244	return;
2245	} else if (card->hbpool.count < card->hbnr.min) {
2246	struct sk_buff *new_hb;
2247	if ((new_hb =
2248	dev_alloc_skb(NS_HBUFSIZE)) !=
2249	NULL) {
2250	skb_queue_tail(list: &card->hbpool.
2251	queue, newsk: new_hb);
2252	card->hbpool.count++;
2253	}
2254	}
2255	NS_PRV_BUFTYPE(hb) = BUF_NONE;
2256	} else if (--card->hbpool.count < card->hbnr.min) {
2257	struct sk_buff *new_hb;
2258	if ((new_hb =
2259	dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2260	NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2261	skb_queue_tail(list: &card->hbpool.queue,
2262	newsk: new_hb);
2263	card->hbpool.count++;
2264	}
2265	if (card->hbpool.count < card->hbnr.min) {
2266	if ((new_hb =
2267	dev_alloc_skb(NS_HBUFSIZE)) !=
2268	NULL) {
2269	NS_PRV_BUFTYPE(new_hb) =
2270	BUF_NONE;
2271	skb_queue_tail(list: &card->hbpool.
2272	queue, newsk: new_hb);
2273	card->hbpool.count++;
2274	}
2275	}
2276	}
2277
2278	iov = (struct iovec *)iovb->data;
2279
2280	if (!atm_charge(vcc, truesize: hb->truesize)) {
2281	recycle_iovec_rx_bufs(card, iov,
2282	NS_PRV_IOVCNT(iovb));
2283	if (card->hbpool.count < card->hbnr.max) {
2284	skb_queue_tail(list: &card->hbpool.queue, newsk: hb);
2285	card->hbpool.count++;
2286	} else
2287	dev_kfree_skb_any(skb: hb);
2288	atomic_inc(v: &vcc->stats->rx_drop);
2289	} else {
2290	/* Copy the small buffer to the huge buffer */
2291	sb = (struct sk_buff *)iov->iov_base;
2292	skb_copy_from_linear_data(skb: sb, to: hb->data,
2293	len: iov->iov_len);
2294	skb_put(skb: hb, len: iov->iov_len);
2295	remaining = len - iov->iov_len;
2296	iov++;
2297	/* Free the small buffer */
2298	push_rxbufs(card, skb: sb);
2299
2300	/* Copy all large buffers to the huge buffer and free them */
2301	for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2302	lb = (struct sk_buff *)iov->iov_base;
2303	tocopy =
2304	min_t(int, remaining, iov->iov_len);
2305	skb_copy_from_linear_data(skb: lb,
2306	to: skb_tail_pointer
2307	(skb: hb), len: tocopy);
2308	skb_put(skb: hb, len: tocopy);
2309	iov++;
2310	remaining -= tocopy;
2311	push_rxbufs(card, skb: lb);
2312	}
2313	#ifdef EXTRA_DEBUG
2314	if (remaining != 0 || hb->len != len)
2315	printk
2316	("nicstar%d: Huge buffer len mismatch.\n",
2317	card->index);
2318	#endif /* EXTRA_DEBUG */
2319	ATM_SKB(hb)->vcc = vcc;
2320	__net_timestamp(skb: hb);
2321	vcc->push(vcc, hb);
2322	atomic_inc(v: &vcc->stats->rx);
2323	}
2324	}
2325
2326	vc->rx_iov = NULL;
2327	recycle_iov_buf(card, iovb);
2328	}
2329
2330	}
2331
2332	static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2333	{
2334	if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2335	printk("nicstar%d: What kind of rx buffer is this?\n",
2336	card->index);
2337	dev_kfree_skb_any(skb);
2338	} else
2339	push_rxbufs(card, skb);
2340	}
2341
2342	static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2343	{
2344	while (count-- > 0)
2345	recycle_rx_buf(card, skb: (struct sk_buff *)(iov++)->iov_base);
2346	}
2347
2348	static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2349	{
2350	if (card->iovpool.count < card->iovnr.max) {
2351	skb_queue_tail(list: &card->iovpool.queue, newsk: iovb);
2352	card->iovpool.count++;
2353	} else
2354	dev_kfree_skb_any(skb: iovb);
2355	}
2356
2357	static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2358	{
2359	skb_unlink(skb: sb, list: &card->sbpool.queue);
2360	if (card->sbfqc < card->sbnr.init) {
2361	struct sk_buff *new_sb;
2362	if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2363	NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2364	skb_queue_tail(list: &card->sbpool.queue, newsk: new_sb);
2365	skb_reserve(skb: new_sb, NS_AAL0_HEADER);
2366	push_rxbufs(card, skb: new_sb);
2367	}
2368	}
2369	if (card->sbfqc < card->sbnr.init)
2370	{
2371	struct sk_buff *new_sb;
2372	if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2373	NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2374	skb_queue_tail(list: &card->sbpool.queue, newsk: new_sb);
2375	skb_reserve(skb: new_sb, NS_AAL0_HEADER);
2376	push_rxbufs(card, skb: new_sb);
2377	}
2378	}
2379	}
2380
2381	static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2382	{
2383	skb_unlink(skb: lb, list: &card->lbpool.queue);
2384	if (card->lbfqc < card->lbnr.init) {
2385	struct sk_buff *new_lb;
2386	if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2387	NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2388	skb_queue_tail(list: &card->lbpool.queue, newsk: new_lb);
2389	skb_reserve(skb: new_lb, NS_SMBUFSIZE);
2390	push_rxbufs(card, skb: new_lb);
2391	}
2392	}
2393	if (card->lbfqc < card->lbnr.init)
2394	{
2395	struct sk_buff *new_lb;
2396	if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2397	NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2398	skb_queue_tail(list: &card->lbpool.queue, newsk: new_lb);
2399	skb_reserve(skb: new_lb, NS_SMBUFSIZE);
2400	push_rxbufs(card, skb: new_lb);
2401	}
2402	}
2403	}
2404
2405	static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2406	{
2407	u32 stat;
2408	ns_dev *card;
2409	int left;
2410
2411	left = (int)*pos;
2412	card = (ns_dev *) dev->dev_data;
2413	stat = readl(addr: card->membase + STAT);
2414	if (!left--)
2415	return sprintf(buf: page, fmt: "Pool count min init max \n");
2416	if (!left--)
2417	return sprintf(buf: page, fmt: "Small %5d %5d %5d %5d \n",
2418	ns_stat_sfbqc_get(stat), card->sbnr.min,
2419	card->sbnr.init, card->sbnr.max);
2420	if (!left--)
2421	return sprintf(buf: page, fmt: "Large %5d %5d %5d %5d \n",
2422	ns_stat_lfbqc_get(stat), card->lbnr.min,
2423	card->lbnr.init, card->lbnr.max);
2424	if (!left--)
2425	return sprintf(buf: page, fmt: "Huge %5d %5d %5d %5d \n",
2426	card->hbpool.count, card->hbnr.min,
2427	card->hbnr.init, card->hbnr.max);
2428	if (!left--)
2429	return sprintf(buf: page, fmt: "Iovec %5d %5d %5d %5d \n",
2430	card->iovpool.count, card->iovnr.min,
2431	card->iovnr.init, card->iovnr.max);
2432	if (!left--) {
2433	int retval;
2434	retval =
2435	sprintf(buf: page, fmt: "Interrupt counter: %u \n", card->intcnt);
2436	card->intcnt = 0;
2437	return retval;
2438	}
2439	#if 0
2440	/* Dump 25.6 Mbps PHY registers */
2441	/* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2442	here just in case it's needed for debugging. */
2443	if (card->max_pcr == ATM_25_PCR && !left--) {
2444	u32 phy_regs[4];
2445	u32 i;
2446
2447	for (i = 0; i < 4; i++) {
2448	while (CMD_BUSY(card)) ;
2449	writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2450	card->membase + CMD);
2451	while (CMD_BUSY(card)) ;
2452	phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2453	}
2454
2455	return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2456	phy_regs[0], phy_regs[1], phy_regs[2],
2457	phy_regs[3]);
2458	}
2459	#endif /* 0 - Dump 25.6 Mbps PHY registers */
2460	#if 0
2461	/* Dump TST */
2462	if (left-- < NS_TST_NUM_ENTRIES) {
2463	if (card->tste2vc[left + 1] == NULL)
2464	return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2465	else
2466	return sprintf(page, "%5d - %d %d \n", left + 1,
2467	card->tste2vc[left + 1]->tx_vcc->vpi,
2468	card->tste2vc[left + 1]->tx_vcc->vci);
2469	}
2470	#endif /* 0 */
2471	return 0;
2472	}
2473
2474	static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2475	{
2476	ns_dev *card;
2477	pool_levels pl;
2478	long btype;
2479	unsigned long flags;
2480
2481	card = dev->dev_data;
2482	switch (cmd) {
2483	case NS_GETPSTAT:
2484	if (get_user
2485	(pl.buftype, &((pool_levels __user *) arg)->buftype))
2486	return -EFAULT;
2487	switch (pl.buftype) {
2488	case NS_BUFTYPE_SMALL:
2489	pl.count =
2490	ns_stat_sfbqc_get(readl(card->membase + STAT));
2491	pl.level.min = card->sbnr.min;
2492	pl.level.init = card->sbnr.init;
2493	pl.level.max = card->sbnr.max;
2494	break;
2495
2496	case NS_BUFTYPE_LARGE:
2497	pl.count =
2498	ns_stat_lfbqc_get(readl(card->membase + STAT));
2499	pl.level.min = card->lbnr.min;
2500	pl.level.init = card->lbnr.init;
2501	pl.level.max = card->lbnr.max;
2502	break;
2503
2504	case NS_BUFTYPE_HUGE:
2505	pl.count = card->hbpool.count;
2506	pl.level.min = card->hbnr.min;
2507	pl.level.init = card->hbnr.init;
2508	pl.level.max = card->hbnr.max;
2509	break;
2510
2511	case NS_BUFTYPE_IOVEC:
2512	pl.count = card->iovpool.count;
2513	pl.level.min = card->iovnr.min;
2514	pl.level.init = card->iovnr.init;
2515	pl.level.max = card->iovnr.max;
2516	break;
2517
2518	default:
2519	return -ENOIOCTLCMD;
2520
2521	}
2522	if (!copy_to_user(to: (pool_levels __user *) arg, from: &pl, n: sizeof(pl)))
2523	return (sizeof(pl));
2524	else
2525	return -EFAULT;
2526
2527	case NS_SETBUFLEV:
2528	if (!capable(CAP_NET_ADMIN))
2529	return -EPERM;
2530	if (copy_from_user(to: &pl, from: (pool_levels __user *) arg, n: sizeof(pl)))
2531	return -EFAULT;
2532	if (pl.level.min >= pl.level.init
2533	|| pl.level.init >= pl.level.max)
2534	return -EINVAL;
2535	if (pl.level.min == 0)
2536	return -EINVAL;
2537	switch (pl.buftype) {
2538	case NS_BUFTYPE_SMALL:
2539	if (pl.level.max > TOP_SB)
2540	return -EINVAL;
2541	card->sbnr.min = pl.level.min;
2542	card->sbnr.init = pl.level.init;
2543	card->sbnr.max = pl.level.max;
2544	break;
2545
2546	case NS_BUFTYPE_LARGE:
2547	if (pl.level.max > TOP_LB)
2548	return -EINVAL;
2549	card->lbnr.min = pl.level.min;
2550	card->lbnr.init = pl.level.init;
2551	card->lbnr.max = pl.level.max;
2552	break;
2553
2554	case NS_BUFTYPE_HUGE:
2555	if (pl.level.max > TOP_HB)
2556	return -EINVAL;
2557	card->hbnr.min = pl.level.min;
2558	card->hbnr.init = pl.level.init;
2559	card->hbnr.max = pl.level.max;
2560	break;
2561
2562	case NS_BUFTYPE_IOVEC:
2563	if (pl.level.max > TOP_IOVB)
2564	return -EINVAL;
2565	card->iovnr.min = pl.level.min;
2566	card->iovnr.init = pl.level.init;
2567	card->iovnr.max = pl.level.max;
2568	break;
2569
2570	default:
2571	return -EINVAL;
2572
2573	}
2574	return 0;
2575
2576	case NS_ADJBUFLEV:
2577	if (!capable(CAP_NET_ADMIN))
2578	return -EPERM;
2579	btype = (long)arg; /* a long is the same size as a pointer or bigger */
2580	switch (btype) {
2581	case NS_BUFTYPE_SMALL:
2582	while (card->sbfqc < card->sbnr.init) {
2583	struct sk_buff *sb;
2584
2585	sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2586	if (sb == NULL)
2587	return -ENOMEM;
2588	NS_PRV_BUFTYPE(sb) = BUF_SM;
2589	skb_queue_tail(list: &card->sbpool.queue, newsk: sb);
2590	skb_reserve(skb: sb, NS_AAL0_HEADER);
2591	push_rxbufs(card, skb: sb);
2592	}
2593	break;
2594
2595	case NS_BUFTYPE_LARGE:
2596	while (card->lbfqc < card->lbnr.init) {
2597	struct sk_buff *lb;
2598
2599	lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2600	if (lb == NULL)
2601	return -ENOMEM;
2602	NS_PRV_BUFTYPE(lb) = BUF_LG;
2603	skb_queue_tail(list: &card->lbpool.queue, newsk: lb);
2604	skb_reserve(skb: lb, NS_SMBUFSIZE);
2605	push_rxbufs(card, skb: lb);
2606	}
2607	break;
2608
2609	case NS_BUFTYPE_HUGE:
2610	while (card->hbpool.count > card->hbnr.init) {
2611	struct sk_buff *hb;
2612
2613	spin_lock_irqsave(&card->int_lock, flags);
2614	hb = skb_dequeue(list: &card->hbpool.queue);
2615	card->hbpool.count--;
2616	spin_unlock_irqrestore(lock: &card->int_lock, flags);
2617	if (hb == NULL)
2618	printk
2619	("nicstar%d: huge buffer count inconsistent.\n",
2620	card->index);
2621	else
2622	dev_kfree_skb_any(skb: hb);
2623
2624	}
2625	while (card->hbpool.count < card->hbnr.init) {
2626	struct sk_buff *hb;
2627
2628	hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2629	if (hb == NULL)
2630	return -ENOMEM;
2631	NS_PRV_BUFTYPE(hb) = BUF_NONE;
2632	spin_lock_irqsave(&card->int_lock, flags);
2633	skb_queue_tail(list: &card->hbpool.queue, newsk: hb);
2634	card->hbpool.count++;
2635	spin_unlock_irqrestore(lock: &card->int_lock, flags);
2636	}
2637	break;
2638
2639	case NS_BUFTYPE_IOVEC:
2640	while (card->iovpool.count > card->iovnr.init) {
2641	struct sk_buff *iovb;
2642
2643	spin_lock_irqsave(&card->int_lock, flags);
2644	iovb = skb_dequeue(list: &card->iovpool.queue);
2645	card->iovpool.count--;
2646	spin_unlock_irqrestore(lock: &card->int_lock, flags);
2647	if (iovb == NULL)
2648	printk
2649	("nicstar%d: iovec buffer count inconsistent.\n",
2650	card->index);
2651	else
2652	dev_kfree_skb_any(skb: iovb);
2653
2654	}
2655	while (card->iovpool.count < card->iovnr.init) {
2656	struct sk_buff *iovb;
2657
2658	iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2659	if (iovb == NULL)
2660	return -ENOMEM;
2661	NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2662	spin_lock_irqsave(&card->int_lock, flags);
2663	skb_queue_tail(list: &card->iovpool.queue, newsk: iovb);
2664	card->iovpool.count++;
2665	spin_unlock_irqrestore(lock: &card->int_lock, flags);
2666	}
2667	break;
2668
2669	default:
2670	return -EINVAL;
2671
2672	}
2673	return 0;
2674
2675	default:
2676	if (dev->phy && dev->phy->ioctl) {
2677	return dev->phy->ioctl(dev, cmd, arg);
2678	} else {
2679	printk("nicstar%d: %s == NULL \n", card->index,
2680	dev->phy ? "dev->phy->ioctl" : "dev->phy");
2681	return -ENOIOCTLCMD;
2682	}
2683	}
2684	}
2685
2686	#ifdef EXTRA_DEBUG
2687	static void which_list(ns_dev * card, struct sk_buff *skb)
2688	{
2689	printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2690	}
2691	#endif /* EXTRA_DEBUG */
2692
2693	static void ns_poll(struct timer_list *unused)
2694	{
2695	int i;
2696	ns_dev *card;
2697	unsigned long flags;
2698	u32 stat_r, stat_w;
2699
2700	PRINTK("nicstar: Entering ns_poll().\n");
2701	for (i = 0; i < num_cards; i++) {
2702	card = cards[i];
2703	if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2704	/* Probably it isn't worth spinning */
2705	continue;
2706	}
2707
2708	stat_w = 0;
2709	stat_r = readl(addr: card->membase + STAT);
2710	if (stat_r & NS_STAT_TSIF)
2711	stat_w |= NS_STAT_TSIF;
2712	if (stat_r & NS_STAT_EOPDU)
2713	stat_w |= NS_STAT_EOPDU;
2714
2715	process_tsq(card);
2716	process_rsq(card);
2717
2718	writel(val: stat_w, addr: card->membase + STAT);
2719	spin_unlock_irqrestore(lock: &card->int_lock, flags);
2720	}
2721	mod_timer(timer: &ns_timer, expires: jiffies + NS_POLL_PERIOD);
2722	PRINTK("nicstar: Leaving ns_poll().\n");
2723	}
2724
2725	static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2726	unsigned long addr)
2727	{
2728	ns_dev *card;
2729	unsigned long flags;
2730
2731	card = dev->dev_data;
2732	spin_lock_irqsave(&card->res_lock, flags);
2733	while (CMD_BUSY(card)) ;
2734	writel(val: (u32) value, addr: card->membase + DR0);
2735	writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2736	addr: card->membase + CMD);
2737	spin_unlock_irqrestore(lock: &card->res_lock, flags);
2738	}
2739
2740	static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2741	{
2742	ns_dev *card;
2743	unsigned long flags;
2744	u32 data;
2745
2746	card = dev->dev_data;
2747	spin_lock_irqsave(&card->res_lock, flags);
2748	while (CMD_BUSY(card)) ;
2749	writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2750	addr: card->membase + CMD);
2751	while (CMD_BUSY(card)) ;
2752	data = readl(addr: card->membase + DR0) & 0x000000FF;
2753	spin_unlock_irqrestore(lock: &card->res_lock, flags);
2754	return (unsigned char)data;
2755	}
2756
2757	module_init(nicstar_init);
2758	module_exit(nicstar_cleanup);
2759