1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "amdgpu.h" |
24 | #include "amdgpu_atombios.h" |
25 | #include "nbio_v2_3.h" |
26 | |
27 | #include "nbio/nbio_2_3_default.h" |
28 | #include "nbio/nbio_2_3_offset.h" |
29 | #include "nbio/nbio_2_3_sh_mask.h" |
30 | #include <uapi/linux/kfd_ioctl.h> |
31 | #include <linux/device.h> |
32 | #include <linux/pci.h> |
33 | |
34 | #define smnPCIE_CONFIG_CNTL 0x11180044 |
35 | #define smnCPM_CONTROL 0x11180460 |
36 | #define smnPCIE_CNTL2 0x11180070 |
37 | #define smnPCIE_LC_CNTL 0x11140280 |
38 | #define smnPCIE_LC_CNTL3 0x111402d4 |
39 | #define smnPCIE_LC_CNTL6 0x111402ec |
40 | #define smnPCIE_LC_CNTL7 0x111402f0 |
41 | #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c |
42 | #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 |
43 | #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 |
44 | #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 |
45 | #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c |
46 | |
47 | #define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6 |
48 | #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2 |
49 | #define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7 |
50 | #define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2 |
51 | |
52 | #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8 |
53 | #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 |
54 | |
55 | #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 |
56 | |
57 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */ |
58 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L |
59 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L |
60 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L |
61 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L |
62 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L |
63 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L |
64 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L |
65 | #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L |
66 | |
67 | static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) |
68 | { |
69 | WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, |
70 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); |
71 | WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, |
72 | adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); |
73 | } |
74 | |
75 | static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) |
76 | { |
77 | u32 tmp; |
78 | |
79 | /* |
80 | * guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, |
81 | * therefore we force rev_id to 0 (which is the default value) |
82 | */ |
83 | if (amdgpu_sriov_vf(adev)) { |
84 | return 0; |
85 | } |
86 | |
87 | tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); |
88 | tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; |
89 | tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; |
90 | |
91 | return tmp; |
92 | } |
93 | |
94 | static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) |
95 | { |
96 | if (enable) |
97 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, |
98 | BIF_FB_EN__FB_READ_EN_MASK | |
99 | BIF_FB_EN__FB_WRITE_EN_MASK); |
100 | else |
101 | WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); |
102 | } |
103 | |
104 | static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) |
105 | { |
106 | return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); |
107 | } |
108 | |
109 | static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, |
110 | bool use_doorbell, int doorbell_index, |
111 | int doorbell_size) |
112 | { |
113 | u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : |
114 | instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) : |
115 | instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) : |
116 | SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE); |
117 | |
118 | u32 doorbell_range = RREG32(reg); |
119 | |
120 | if (use_doorbell) { |
121 | doorbell_range = REG_SET_FIELD(doorbell_range, |
122 | BIF_SDMA0_DOORBELL_RANGE, OFFSET, |
123 | doorbell_index); |
124 | doorbell_range = REG_SET_FIELD(doorbell_range, |
125 | BIF_SDMA0_DOORBELL_RANGE, SIZE, |
126 | doorbell_size); |
127 | } else |
128 | doorbell_range = REG_SET_FIELD(doorbell_range, |
129 | BIF_SDMA0_DOORBELL_RANGE, SIZE, |
130 | 0); |
131 | |
132 | WREG32(reg, doorbell_range); |
133 | } |
134 | |
135 | static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, |
136 | int doorbell_index, int instance) |
137 | { |
138 | u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) : |
139 | SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); |
140 | |
141 | u32 doorbell_range = RREG32(reg); |
142 | |
143 | if (use_doorbell) { |
144 | doorbell_range = REG_SET_FIELD(doorbell_range, |
145 | BIF_MMSCH0_DOORBELL_RANGE, OFFSET, |
146 | doorbell_index); |
147 | doorbell_range = REG_SET_FIELD(doorbell_range, |
148 | BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); |
149 | } else |
150 | doorbell_range = REG_SET_FIELD(doorbell_range, |
151 | BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); |
152 | |
153 | WREG32(reg, doorbell_range); |
154 | } |
155 | |
156 | static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, |
157 | bool enable) |
158 | { |
159 | WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, |
160 | enable ? 1 : 0); |
161 | } |
162 | |
163 | static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, |
164 | bool enable) |
165 | { |
166 | u32 tmp = 0; |
167 | |
168 | if (enable) { |
169 | tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, |
170 | DOORBELL_SELFRING_GPA_APER_EN, 1) | |
171 | REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, |
172 | DOORBELL_SELFRING_GPA_APER_MODE, 1) | |
173 | REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, |
174 | DOORBELL_SELFRING_GPA_APER_SIZE, 0); |
175 | |
176 | WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, |
177 | lower_32_bits(adev->doorbell.base)); |
178 | WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, |
179 | upper_32_bits(adev->doorbell.base)); |
180 | } |
181 | |
182 | WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, |
183 | tmp); |
184 | } |
185 | |
186 | |
187 | static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, |
188 | bool use_doorbell, int doorbell_index) |
189 | { |
190 | u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); |
191 | |
192 | if (use_doorbell) { |
193 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
194 | BIF_IH_DOORBELL_RANGE, OFFSET, |
195 | doorbell_index); |
196 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
197 | BIF_IH_DOORBELL_RANGE, SIZE, |
198 | 2); |
199 | } else |
200 | ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, |
201 | BIF_IH_DOORBELL_RANGE, SIZE, |
202 | 0); |
203 | |
204 | WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); |
205 | } |
206 | |
207 | static void nbio_v2_3_ih_control(struct amdgpu_device *adev) |
208 | { |
209 | u32 interrupt_cntl; |
210 | |
211 | /* setup interrupt control */ |
212 | WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); |
213 | |
214 | interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); |
215 | /* |
216 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi |
217 | * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN |
218 | */ |
219 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, |
220 | IH_DUMMY_RD_OVERRIDE, 0); |
221 | |
222 | /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ |
223 | interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, |
224 | IH_REQ_NONSNOOP_EN, 0); |
225 | |
226 | WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); |
227 | } |
228 | |
229 | static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
230 | bool enable) |
231 | { |
232 | uint32_t def, data; |
233 | |
234 | if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) |
235 | return; |
236 | |
237 | def = data = RREG32_PCIE(smnCPM_CONTROL); |
238 | if (enable) { |
239 | data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | |
240 | CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | |
241 | CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | |
242 | CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | |
243 | CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | |
244 | CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); |
245 | } else { |
246 | data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | |
247 | CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | |
248 | CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | |
249 | CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | |
250 | CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | |
251 | CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); |
252 | } |
253 | |
254 | if (def != data) |
255 | WREG32_PCIE(smnCPM_CONTROL, data); |
256 | } |
257 | |
258 | static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
259 | bool enable) |
260 | { |
261 | uint32_t def, data; |
262 | |
263 | if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) |
264 | return; |
265 | |
266 | def = data = RREG32_PCIE(smnPCIE_CNTL2); |
267 | if (enable) { |
268 | data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | |
269 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | |
270 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); |
271 | } else { |
272 | data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | |
273 | PCIE_CNTL2__MST_MEM_LS_EN_MASK | |
274 | PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); |
275 | } |
276 | |
277 | if (def != data) |
278 | WREG32_PCIE(smnPCIE_CNTL2, data); |
279 | } |
280 | |
281 | static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, |
282 | u64 *flags) |
283 | { |
284 | int data; |
285 | |
286 | /* AMD_CG_SUPPORT_BIF_MGCG */ |
287 | data = RREG32_PCIE(smnCPM_CONTROL); |
288 | if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) |
289 | *flags |= AMD_CG_SUPPORT_BIF_MGCG; |
290 | |
291 | /* AMD_CG_SUPPORT_BIF_LS */ |
292 | data = RREG32_PCIE(smnPCIE_CNTL2); |
293 | if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) |
294 | *flags |= AMD_CG_SUPPORT_BIF_LS; |
295 | } |
296 | |
297 | static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) |
298 | { |
299 | return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); |
300 | } |
301 | |
302 | static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) |
303 | { |
304 | return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); |
305 | } |
306 | |
307 | static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) |
308 | { |
309 | return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); |
310 | } |
311 | |
312 | static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) |
313 | { |
314 | return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); |
315 | } |
316 | |
317 | const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { |
318 | .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, |
319 | .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, |
320 | .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, |
321 | .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, |
322 | .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, |
323 | .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, |
324 | .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, |
325 | .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, |
326 | .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, |
327 | .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, |
328 | .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, |
329 | .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, |
330 | }; |
331 | |
332 | static void nbio_v2_3_init_registers(struct amdgpu_device *adev) |
333 | { |
334 | uint32_t def, data; |
335 | |
336 | def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); |
337 | data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); |
338 | data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); |
339 | |
340 | if (def != data) |
341 | WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); |
342 | |
343 | if (amdgpu_sriov_vf(adev)) |
344 | adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, |
345 | mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; |
346 | } |
347 | |
348 | #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1 |
349 | #define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x0000000A // 1=1us, 9=1ms, 10=4ms |
350 | #define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 400ms |
351 | |
352 | static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, |
353 | bool enable) |
354 | { |
355 | uint32_t def, data; |
356 | |
357 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL); |
358 | |
359 | if (enable) { |
360 | /* Disable ASPM L0s/L1 first */ |
361 | data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); |
362 | |
363 | data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; |
364 | |
365 | if (dev_is_removable(dev: &adev->pdev->dev)) |
366 | data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; |
367 | else |
368 | data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; |
369 | |
370 | data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; |
371 | } else { |
372 | /* Disbale ASPM L1 */ |
373 | data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; |
374 | /* Disable ASPM TxL0s */ |
375 | data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; |
376 | /* Disable ACPI L1 */ |
377 | data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; |
378 | } |
379 | |
380 | if (def != data) |
381 | WREG32_PCIE(smnPCIE_LC_CNTL, data); |
382 | } |
383 | |
384 | #ifdef CONFIG_PCIEASPM |
385 | static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) |
386 | { |
387 | uint32_t def, data; |
388 | |
389 | WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); |
390 | |
391 | def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2); |
392 | data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; |
393 | if (def != data) |
394 | WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data); |
395 | |
396 | def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); |
397 | data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; |
398 | if (def != data) |
399 | WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); |
400 | |
401 | def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); |
402 | data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; |
403 | if (def != data) |
404 | WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); |
405 | } |
406 | #endif |
407 | |
408 | static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) |
409 | { |
410 | #ifdef CONFIG_PCIEASPM |
411 | uint32_t def, data; |
412 | |
413 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL); |
414 | data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; |
415 | data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; |
416 | data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; |
417 | if (def != data) |
418 | WREG32_PCIE(smnPCIE_LC_CNTL, data); |
419 | |
420 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); |
421 | data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; |
422 | if (def != data) |
423 | WREG32_PCIE(smnPCIE_LC_CNTL7, data); |
424 | |
425 | def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); |
426 | data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; |
427 | if (def != data) |
428 | WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); |
429 | |
430 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); |
431 | data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; |
432 | if (def != data) |
433 | WREG32_PCIE(smnPCIE_LC_CNTL3, data); |
434 | |
435 | def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); |
436 | data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; |
437 | data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; |
438 | if (def != data) |
439 | WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data); |
440 | |
441 | def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); |
442 | data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; |
443 | if (def != data) |
444 | WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data); |
445 | |
446 | def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); |
447 | data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; |
448 | if (def != data) |
449 | WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); |
450 | |
451 | WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); |
452 | |
453 | def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); |
454 | data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | |
455 | PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; |
456 | data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; |
457 | if (def != data) |
458 | WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); |
459 | |
460 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); |
461 | data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | |
462 | PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; |
463 | if (def != data) |
464 | WREG32_PCIE(smnPCIE_LC_CNTL6, data); |
465 | |
466 | /* Don't bother about LTR if LTR is not enabled |
467 | * in the path */ |
468 | if (adev->pdev->ltr_path) |
469 | nbio_v2_3_program_ltr(adev); |
470 | |
471 | def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); |
472 | data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; |
473 | data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; |
474 | if (def != data) |
475 | WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data); |
476 | |
477 | def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5); |
478 | data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; |
479 | if (def != data) |
480 | WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data); |
481 | |
482 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL); |
483 | data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; |
484 | if (dev_is_removable(dev: &adev->pdev->dev)) |
485 | data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; |
486 | else |
487 | data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; |
488 | data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; |
489 | if (def != data) |
490 | WREG32_PCIE(smnPCIE_LC_CNTL, data); |
491 | |
492 | def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); |
493 | data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; |
494 | if (def != data) |
495 | WREG32_PCIE(smnPCIE_LC_CNTL3, data); |
496 | #endif |
497 | } |
498 | |
499 | static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev) |
500 | { |
501 | uint32_t reg_data = 0; |
502 | uint32_t link_width = 0; |
503 | |
504 | if (!((adev->asic_type >= CHIP_NAVI10) && |
505 | (adev->asic_type <= CHIP_NAVI12))) |
506 | return; |
507 | |
508 | reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); |
509 | link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) |
510 | >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; |
511 | |
512 | /* |
513 | * Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data) |
514 | * if link_width is 0x3 (x4) |
515 | */ |
516 | if (0x3 == link_width) { |
517 | reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6); |
518 | reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK; |
519 | reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT); |
520 | WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data); |
521 | } |
522 | } |
523 | |
524 | static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev) |
525 | { |
526 | uint32_t reg_data = 0; |
527 | |
528 | if (adev->asic_type != CHIP_NAVI10) |
529 | return; |
530 | |
531 | reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); |
532 | reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK; |
533 | WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data); |
534 | } |
535 | |
536 | static void nbio_v2_3_clear_doorbell_interrupt(struct amdgpu_device *adev) |
537 | { |
538 | uint32_t reg, reg_data; |
539 | |
540 | if (amdgpu_ip_version(adev, ip: NBIO_HWIP, inst: 0) != IP_VERSION(3, 3, 0)) |
541 | return; |
542 | |
543 | reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL); |
544 | |
545 | /* Clear Interrupt Status |
546 | */ |
547 | if ((reg & BIF_RB_CNTL__RB_ENABLE_MASK) == 0) { |
548 | reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); |
549 | if (reg & BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK) { |
550 | reg_data = 1 << BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT; |
551 | WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, reg_data); |
552 | } |
553 | } |
554 | } |
555 | |
556 | const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { |
557 | .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, |
558 | .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, |
559 | .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, |
560 | .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, |
561 | .get_rev_id = nbio_v2_3_get_rev_id, |
562 | .mc_access_enable = nbio_v2_3_mc_access_enable, |
563 | .get_memsize = nbio_v2_3_get_memsize, |
564 | .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, |
565 | .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, |
566 | .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, |
567 | .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, |
568 | .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, |
569 | .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, |
570 | .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, |
571 | .get_clockgating_state = nbio_v2_3_get_clockgating_state, |
572 | .ih_control = nbio_v2_3_ih_control, |
573 | .init_registers = nbio_v2_3_init_registers, |
574 | .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, |
575 | .enable_aspm = nbio_v2_3_enable_aspm, |
576 | .program_aspm = nbio_v2_3_program_aspm, |
577 | .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa, |
578 | .apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa, |
579 | .clear_doorbell_interrupt = nbio_v2_3_clear_doorbell_interrupt, |
580 | }; |
581 | |