1 | /* |
2 | * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com> |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include <linux/slab.h> |
27 | |
28 | #include "dce/dce_6_0_d.h" |
29 | #include "dce/dce_6_0_sh_mask.h" |
30 | |
31 | #include "dm_services.h" |
32 | |
33 | #include "link_encoder.h" |
34 | #include "stream_encoder.h" |
35 | |
36 | #include "resource.h" |
37 | #include "include/irq_service_interface.h" |
38 | #include "irq/dce60/irq_service_dce60.h" |
39 | #include "dce110/dce110_timing_generator.h" |
40 | #include "dce110/dce110_resource.h" |
41 | #include "dce60/dce60_timing_generator.h" |
42 | #include "dce/dce_mem_input.h" |
43 | #include "dce/dce_link_encoder.h" |
44 | #include "dce/dce_stream_encoder.h" |
45 | #include "dce/dce_ipp.h" |
46 | #include "dce/dce_transform.h" |
47 | #include "dce/dce_opp.h" |
48 | #include "dce/dce_clock_source.h" |
49 | #include "dce/dce_audio.h" |
50 | #include "dce/dce_hwseq.h" |
51 | #include "dce60/dce60_hw_sequencer.h" |
52 | #include "dce100/dce100_resource.h" |
53 | #include "dce/dce_panel_cntl.h" |
54 | |
55 | #include "reg_helper.h" |
56 | |
57 | #include "dce/dce_dmcu.h" |
58 | #include "dce/dce_aux.h" |
59 | #include "dce/dce_abm.h" |
60 | #include "dce/dce_i2c.h" |
61 | /* TODO remove this include */ |
62 | |
63 | #include "dce60_resource.h" |
64 | |
65 | #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT |
66 | #include "gmc/gmc_6_0_d.h" |
67 | #include "gmc/gmc_6_0_sh_mask.h" |
68 | #endif |
69 | |
70 | #ifndef mmDP_DPHY_INTERNAL_CTRL |
71 | #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE |
72 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE |
73 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE |
74 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE |
75 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE |
76 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE |
77 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE |
78 | #endif |
79 | |
80 | |
81 | #ifndef mmBIOS_SCRATCH_2 |
82 | #define mmBIOS_SCRATCH_2 0x05CB |
83 | #define mmBIOS_SCRATCH_3 0x05CC |
84 | #define mmBIOS_SCRATCH_6 0x05CF |
85 | #endif |
86 | |
87 | #ifndef mmDP_DPHY_FAST_TRAINING |
88 | #define mmDP_DPHY_FAST_TRAINING 0x1CCE |
89 | #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE |
90 | #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE |
91 | #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE |
92 | #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE |
93 | #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE |
94 | #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE |
95 | #endif |
96 | |
97 | |
98 | #ifndef mmHPD_DC_HPD_CONTROL |
99 | #define mmHPD_DC_HPD_CONTROL 0x189A |
100 | #define mmHPD0_DC_HPD_CONTROL 0x189A |
101 | #define mmHPD1_DC_HPD_CONTROL 0x18A2 |
102 | #define mmHPD2_DC_HPD_CONTROL 0x18AA |
103 | #define mmHPD3_DC_HPD_CONTROL 0x18B2 |
104 | #define mmHPD4_DC_HPD_CONTROL 0x18BA |
105 | #define mmHPD5_DC_HPD_CONTROL 0x18C2 |
106 | #endif |
107 | |
108 | #define DCE11_DIG_FE_CNTL 0x4a00 |
109 | #define DCE11_DIG_BE_CNTL 0x4a47 |
110 | #define DCE11_DP_SEC 0x4ac3 |
111 | |
112 | static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = { |
113 | { |
114 | .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), |
115 | .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), |
116 | .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 |
117 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
118 | }, |
119 | { |
120 | .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), |
121 | .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), |
122 | .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 |
123 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
124 | }, |
125 | { |
126 | .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), |
127 | .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), |
128 | .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 |
129 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
130 | }, |
131 | { |
132 | .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), |
133 | .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), |
134 | .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 |
135 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
136 | }, |
137 | { |
138 | .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), |
139 | .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), |
140 | .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 |
141 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
142 | }, |
143 | { |
144 | .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), |
145 | .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), |
146 | .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 |
147 | - mmDPG_PIPE_ARBITRATION_CONTROL3), |
148 | } |
149 | }; |
150 | |
151 | /* set register offset */ |
152 | #define SR(reg_name)\ |
153 | .reg_name = mm ## reg_name |
154 | |
155 | /* set register offset with instance */ |
156 | #define SRI(reg_name, block, id)\ |
157 | .reg_name = mm ## block ## id ## _ ## reg_name |
158 | |
159 | #define ipp_regs(id)\ |
160 | [id] = {\ |
161 | IPP_COMMON_REG_LIST_DCE_BASE(id)\ |
162 | } |
163 | |
164 | static const struct dce_ipp_registers ipp_regs[] = { |
165 | ipp_regs(0), |
166 | ipp_regs(1), |
167 | ipp_regs(2), |
168 | ipp_regs(3), |
169 | ipp_regs(4), |
170 | ipp_regs(5) |
171 | }; |
172 | |
173 | static const struct dce_ipp_shift ipp_shift = { |
174 | IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) |
175 | }; |
176 | |
177 | static const struct dce_ipp_mask ipp_mask = { |
178 | IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) |
179 | }; |
180 | |
181 | #define transform_regs(id)\ |
182 | [id] = {\ |
183 | XFM_COMMON_REG_LIST_DCE60(id)\ |
184 | } |
185 | |
186 | static const struct dce_transform_registers xfm_regs[] = { |
187 | transform_regs(0), |
188 | transform_regs(1), |
189 | transform_regs(2), |
190 | transform_regs(3), |
191 | transform_regs(4), |
192 | transform_regs(5) |
193 | }; |
194 | |
195 | static const struct dce_transform_shift xfm_shift = { |
196 | XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT) |
197 | }; |
198 | |
199 | static const struct dce_transform_mask xfm_mask = { |
200 | XFM_COMMON_MASK_SH_LIST_DCE60(_MASK) |
201 | }; |
202 | |
203 | #define aux_regs(id)\ |
204 | [id] = {\ |
205 | AUX_REG_LIST(id)\ |
206 | } |
207 | |
208 | static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { |
209 | aux_regs(0), |
210 | aux_regs(1), |
211 | aux_regs(2), |
212 | aux_regs(3), |
213 | aux_regs(4), |
214 | aux_regs(5) |
215 | }; |
216 | |
217 | #define hpd_regs(id)\ |
218 | [id] = {\ |
219 | HPD_REG_LIST(id)\ |
220 | } |
221 | |
222 | static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { |
223 | hpd_regs(0), |
224 | hpd_regs(1), |
225 | hpd_regs(2), |
226 | hpd_regs(3), |
227 | hpd_regs(4), |
228 | hpd_regs(5) |
229 | }; |
230 | |
231 | #define link_regs(id)\ |
232 | [id] = {\ |
233 | LE_DCE60_REG_LIST(id)\ |
234 | } |
235 | |
236 | static const struct dce110_link_enc_registers link_enc_regs[] = { |
237 | link_regs(0), |
238 | link_regs(1), |
239 | link_regs(2), |
240 | link_regs(3), |
241 | link_regs(4), |
242 | link_regs(5) |
243 | }; |
244 | |
245 | #define stream_enc_regs(id)\ |
246 | [id] = {\ |
247 | SE_COMMON_REG_LIST_DCE_BASE(id),\ |
248 | .AFMT_CNTL = 0,\ |
249 | } |
250 | |
251 | static const struct dce110_stream_enc_registers stream_enc_regs[] = { |
252 | stream_enc_regs(0), |
253 | stream_enc_regs(1), |
254 | stream_enc_regs(2), |
255 | stream_enc_regs(3), |
256 | stream_enc_regs(4), |
257 | stream_enc_regs(5) |
258 | }; |
259 | |
260 | static const struct dce_stream_encoder_shift se_shift = { |
261 | SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) |
262 | }; |
263 | |
264 | static const struct dce_stream_encoder_mask se_mask = { |
265 | SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) |
266 | }; |
267 | |
268 | static const struct dce_panel_cntl_registers panel_cntl_regs[] = { |
269 | { DCE_PANEL_CNTL_REG_LIST() } |
270 | }; |
271 | |
272 | static const struct dce_panel_cntl_shift panel_cntl_shift = { |
273 | DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) |
274 | }; |
275 | |
276 | static const struct dce_panel_cntl_mask panel_cntl_mask = { |
277 | DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) |
278 | }; |
279 | |
280 | #define opp_regs(id)\ |
281 | [id] = {\ |
282 | OPP_DCE_60_REG_LIST(id),\ |
283 | } |
284 | |
285 | static const struct dce_opp_registers opp_regs[] = { |
286 | opp_regs(0), |
287 | opp_regs(1), |
288 | opp_regs(2), |
289 | opp_regs(3), |
290 | opp_regs(4), |
291 | opp_regs(5) |
292 | }; |
293 | |
294 | static const struct dce_opp_shift opp_shift = { |
295 | OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT) |
296 | }; |
297 | |
298 | static const struct dce_opp_mask opp_mask = { |
299 | OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK) |
300 | }; |
301 | |
302 | static const struct dce110_aux_registers_shift aux_shift = { |
303 | DCE10_AUX_MASK_SH_LIST(__SHIFT) |
304 | }; |
305 | |
306 | static const struct dce110_aux_registers_mask aux_mask = { |
307 | DCE10_AUX_MASK_SH_LIST(_MASK) |
308 | }; |
309 | |
310 | #define aux_engine_regs(id)\ |
311 | [id] = {\ |
312 | AUX_COMMON_REG_LIST(id), \ |
313 | .AUX_RESET_MASK = 0 \ |
314 | } |
315 | |
316 | static const struct dce110_aux_registers aux_engine_regs[] = { |
317 | aux_engine_regs(0), |
318 | aux_engine_regs(1), |
319 | aux_engine_regs(2), |
320 | aux_engine_regs(3), |
321 | aux_engine_regs(4), |
322 | aux_engine_regs(5) |
323 | }; |
324 | |
325 | #define audio_regs(id)\ |
326 | [id] = {\ |
327 | AUD_COMMON_REG_LIST(id)\ |
328 | } |
329 | |
330 | static const struct dce_audio_registers audio_regs[] = { |
331 | audio_regs(0), |
332 | audio_regs(1), |
333 | audio_regs(2), |
334 | audio_regs(3), |
335 | audio_regs(4), |
336 | audio_regs(5), |
337 | }; |
338 | |
339 | static const struct dce_audio_shift audio_shift = { |
340 | AUD_DCE60_MASK_SH_LIST(__SHIFT) |
341 | }; |
342 | |
343 | static const struct dce_audio_mask audio_mask = { |
344 | AUD_DCE60_MASK_SH_LIST(_MASK) |
345 | }; |
346 | |
347 | #define clk_src_regs(id)\ |
348 | [id] = {\ |
349 | CS_COMMON_REG_LIST_DCE_80(id),\ |
350 | } |
351 | |
352 | |
353 | static const struct dce110_clk_src_regs clk_src_regs[] = { |
354 | clk_src_regs(0), |
355 | clk_src_regs(1), |
356 | clk_src_regs(2) |
357 | }; |
358 | |
359 | static const struct dce110_clk_src_shift cs_shift = { |
360 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) |
361 | }; |
362 | |
363 | static const struct dce110_clk_src_mask cs_mask = { |
364 | CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) |
365 | }; |
366 | |
367 | static const struct bios_registers bios_regs = { |
368 | .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, |
369 | .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 |
370 | }; |
371 | |
372 | static const struct resource_caps res_cap = { |
373 | .num_timing_generator = 6, |
374 | .num_audio = 6, |
375 | .num_stream_encoder = 6, |
376 | .num_pll = 2, |
377 | .num_ddc = 6, |
378 | }; |
379 | |
380 | static const struct resource_caps res_cap_61 = { |
381 | .num_timing_generator = 4, |
382 | .num_audio = 6, |
383 | .num_stream_encoder = 6, |
384 | .num_pll = 3, |
385 | .num_ddc = 6, |
386 | }; |
387 | |
388 | static const struct resource_caps res_cap_64 = { |
389 | .num_timing_generator = 2, |
390 | .num_audio = 2, |
391 | .num_stream_encoder = 2, |
392 | .num_pll = 2, |
393 | .num_ddc = 2, |
394 | }; |
395 | |
396 | static const struct dc_plane_cap plane_cap = { |
397 | .type = DC_PLANE_TYPE_DCE_RGB, |
398 | |
399 | .pixel_format_support = { |
400 | .argb8888 = true, |
401 | .nv12 = false, |
402 | .fp16 = false |
403 | }, |
404 | |
405 | .max_upscale_factor = { |
406 | .argb8888 = 16000, |
407 | .nv12 = 1, |
408 | .fp16 = 1 |
409 | }, |
410 | |
411 | .max_downscale_factor = { |
412 | .argb8888 = 250, |
413 | .nv12 = 1, |
414 | .fp16 = 1 |
415 | } |
416 | }; |
417 | |
418 | static const struct dce_dmcu_registers dmcu_regs = { |
419 | DMCU_DCE60_REG_LIST() |
420 | }; |
421 | |
422 | static const struct dce_dmcu_shift dmcu_shift = { |
423 | DMCU_MASK_SH_LIST_DCE60(__SHIFT) |
424 | }; |
425 | |
426 | static const struct dce_dmcu_mask dmcu_mask = { |
427 | DMCU_MASK_SH_LIST_DCE60(_MASK) |
428 | }; |
429 | static const struct dce_abm_registers abm_regs = { |
430 | ABM_DCE110_COMMON_REG_LIST() |
431 | }; |
432 | |
433 | static const struct dce_abm_shift abm_shift = { |
434 | ABM_MASK_SH_LIST_DCE110(__SHIFT) |
435 | }; |
436 | |
437 | static const struct dce_abm_mask abm_mask = { |
438 | ABM_MASK_SH_LIST_DCE110(_MASK) |
439 | }; |
440 | |
441 | #define CTX ctx |
442 | #define REG(reg) mm ## reg |
443 | |
444 | #ifndef mmCC_DC_HDMI_STRAPS |
445 | #define mmCC_DC_HDMI_STRAPS 0x1918 |
446 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 |
447 | #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 |
448 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 |
449 | #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 |
450 | #endif |
451 | |
452 | static int map_transmitter_id_to_phy_instance( |
453 | enum transmitter transmitter) |
454 | { |
455 | switch (transmitter) { |
456 | case TRANSMITTER_UNIPHY_A: |
457 | return 0; |
458 | case TRANSMITTER_UNIPHY_B: |
459 | return 1; |
460 | case TRANSMITTER_UNIPHY_C: |
461 | return 2; |
462 | case TRANSMITTER_UNIPHY_D: |
463 | return 3; |
464 | case TRANSMITTER_UNIPHY_E: |
465 | return 4; |
466 | case TRANSMITTER_UNIPHY_F: |
467 | return 5; |
468 | case TRANSMITTER_UNIPHY_G: |
469 | return 6; |
470 | default: |
471 | ASSERT(0); |
472 | return 0; |
473 | } |
474 | } |
475 | |
476 | static void read_dce_straps( |
477 | struct dc_context *ctx, |
478 | struct resource_straps *straps) |
479 | { |
480 | REG_GET_2(CC_DC_HDMI_STRAPS, |
481 | HDMI_DISABLE, &straps->hdmi_disable, |
482 | AUDIO_STREAM_NUMBER, &straps->audio_stream_number); |
483 | |
484 | REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); |
485 | } |
486 | |
487 | static struct audio *create_audio( |
488 | struct dc_context *ctx, unsigned int inst) |
489 | { |
490 | return dce60_audio_create(ctx, inst, |
491 | reg: &audio_regs[inst], shifts: &audio_shift, masks: &audio_mask); |
492 | } |
493 | |
494 | static struct timing_generator *dce60_timing_generator_create( |
495 | struct dc_context *ctx, |
496 | uint32_t instance, |
497 | const struct dce110_timing_generator_offsets *offsets) |
498 | { |
499 | struct dce110_timing_generator *tg110 = |
500 | kzalloc(size: sizeof(struct dce110_timing_generator), GFP_KERNEL); |
501 | |
502 | if (!tg110) |
503 | return NULL; |
504 | |
505 | dce60_timing_generator_construct(tg: tg110, ctx, instance, offsets); |
506 | return &tg110->base; |
507 | } |
508 | |
509 | static struct output_pixel_processor *dce60_opp_create( |
510 | struct dc_context *ctx, |
511 | uint32_t inst) |
512 | { |
513 | struct dce110_opp *opp = |
514 | kzalloc(size: sizeof(struct dce110_opp), GFP_KERNEL); |
515 | |
516 | if (!opp) |
517 | return NULL; |
518 | |
519 | dce60_opp_construct(opp110: opp, |
520 | ctx, inst, regs: &opp_regs[inst], opp_shift: &opp_shift, opp_mask: &opp_mask); |
521 | return &opp->base; |
522 | } |
523 | |
524 | static struct dce_aux *dce60_aux_engine_create( |
525 | struct dc_context *ctx, |
526 | uint32_t inst) |
527 | { |
528 | struct aux_engine_dce110 *aux_engine = |
529 | kzalloc(size: sizeof(struct aux_engine_dce110), GFP_KERNEL); |
530 | |
531 | if (!aux_engine) |
532 | return NULL; |
533 | |
534 | dce110_aux_engine_construct(aux_engine110: aux_engine, ctx, inst, |
535 | timeout_period: SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, |
536 | regs: &aux_engine_regs[inst], |
537 | mask: &aux_mask, |
538 | shift: &aux_shift, |
539 | is_ext_aux_timeout_configurable: ctx->dc->caps.extended_aux_timeout_support); |
540 | |
541 | return &aux_engine->base; |
542 | } |
543 | #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } |
544 | |
545 | static const struct dce_i2c_registers i2c_hw_regs[] = { |
546 | i2c_inst_regs(1), |
547 | i2c_inst_regs(2), |
548 | i2c_inst_regs(3), |
549 | i2c_inst_regs(4), |
550 | i2c_inst_regs(5), |
551 | i2c_inst_regs(6), |
552 | }; |
553 | |
554 | static const struct dce_i2c_shift i2c_shifts = { |
555 | I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) |
556 | }; |
557 | |
558 | static const struct dce_i2c_mask i2c_masks = { |
559 | I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) |
560 | }; |
561 | |
562 | static struct dce_i2c_hw *dce60_i2c_hw_create( |
563 | struct dc_context *ctx, |
564 | uint32_t inst) |
565 | { |
566 | struct dce_i2c_hw *dce_i2c_hw = |
567 | kzalloc(size: sizeof(struct dce_i2c_hw), GFP_KERNEL); |
568 | |
569 | if (!dce_i2c_hw) |
570 | return NULL; |
571 | |
572 | dce_i2c_hw_construct(dce_i2c_hw, ctx, engine_id: inst, |
573 | regs: &i2c_hw_regs[inst], shifts: &i2c_shifts, masks: &i2c_masks); |
574 | |
575 | return dce_i2c_hw; |
576 | } |
577 | |
578 | static struct dce_i2c_sw *dce60_i2c_sw_create( |
579 | struct dc_context *ctx) |
580 | { |
581 | struct dce_i2c_sw *dce_i2c_sw = |
582 | kzalloc(size: sizeof(struct dce_i2c_sw), GFP_KERNEL); |
583 | |
584 | if (!dce_i2c_sw) |
585 | return NULL; |
586 | |
587 | dce_i2c_sw_construct(dce_i2c_sw, ctx); |
588 | |
589 | return dce_i2c_sw; |
590 | } |
591 | static struct stream_encoder *dce60_stream_encoder_create( |
592 | enum engine_id eng_id, |
593 | struct dc_context *ctx) |
594 | { |
595 | struct dce110_stream_encoder *enc110 = |
596 | kzalloc(size: sizeof(struct dce110_stream_encoder), GFP_KERNEL); |
597 | |
598 | if (!enc110) |
599 | return NULL; |
600 | |
601 | dce110_stream_encoder_construct(enc110, ctx, bp: ctx->dc_bios, eng_id, |
602 | regs: &stream_enc_regs[eng_id], |
603 | se_shift: &se_shift, se_mask: &se_mask); |
604 | return &enc110->base; |
605 | } |
606 | |
607 | #define SRII(reg_name, block, id)\ |
608 | .reg_name[id] = mm ## block ## id ## _ ## reg_name |
609 | |
610 | static const struct dce_hwseq_registers hwseq_reg = { |
611 | HWSEQ_DCE6_REG_LIST() |
612 | }; |
613 | |
614 | static const struct dce_hwseq_shift hwseq_shift = { |
615 | HWSEQ_DCE6_MASK_SH_LIST(__SHIFT) |
616 | }; |
617 | |
618 | static const struct dce_hwseq_mask hwseq_mask = { |
619 | HWSEQ_DCE6_MASK_SH_LIST(_MASK) |
620 | }; |
621 | |
622 | static struct dce_hwseq *dce60_hwseq_create( |
623 | struct dc_context *ctx) |
624 | { |
625 | struct dce_hwseq *hws = kzalloc(size: sizeof(struct dce_hwseq), GFP_KERNEL); |
626 | |
627 | if (hws) { |
628 | hws->ctx = ctx; |
629 | hws->regs = &hwseq_reg; |
630 | hws->shifts = &hwseq_shift; |
631 | hws->masks = &hwseq_mask; |
632 | } |
633 | return hws; |
634 | } |
635 | |
636 | static const struct resource_create_funcs res_create_funcs = { |
637 | .read_dce_straps = read_dce_straps, |
638 | .create_audio = create_audio, |
639 | .create_stream_encoder = dce60_stream_encoder_create, |
640 | .create_hwseq = dce60_hwseq_create, |
641 | }; |
642 | |
643 | #define mi_inst_regs(id) { \ |
644 | MI_DCE6_REG_LIST(id), \ |
645 | .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ |
646 | } |
647 | static const struct dce_mem_input_registers mi_regs[] = { |
648 | mi_inst_regs(0), |
649 | mi_inst_regs(1), |
650 | mi_inst_regs(2), |
651 | mi_inst_regs(3), |
652 | mi_inst_regs(4), |
653 | mi_inst_regs(5), |
654 | }; |
655 | |
656 | static const struct dce_mem_input_shift mi_shifts = { |
657 | MI_DCE6_MASK_SH_LIST(__SHIFT), |
658 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT |
659 | }; |
660 | |
661 | static const struct dce_mem_input_mask mi_masks = { |
662 | MI_DCE6_MASK_SH_LIST(_MASK), |
663 | .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK |
664 | }; |
665 | |
666 | static struct mem_input *dce60_mem_input_create( |
667 | struct dc_context *ctx, |
668 | uint32_t inst) |
669 | { |
670 | struct dce_mem_input *dce_mi = kzalloc(size: sizeof(struct dce_mem_input), |
671 | GFP_KERNEL); |
672 | |
673 | if (!dce_mi) { |
674 | BREAK_TO_DEBUGGER(); |
675 | return NULL; |
676 | } |
677 | |
678 | dce60_mem_input_construct(dce_mi, ctx, inst, regs: &mi_regs[inst], mi_shift: &mi_shifts, mi_mask: &mi_masks); |
679 | dce_mi->wa.single_head_rdreq_dmif_limit = 2; |
680 | return &dce_mi->base; |
681 | } |
682 | |
683 | static void dce60_transform_destroy(struct transform **xfm) |
684 | { |
685 | kfree(TO_DCE_TRANSFORM(*xfm)); |
686 | *xfm = NULL; |
687 | } |
688 | |
689 | static struct transform *dce60_transform_create( |
690 | struct dc_context *ctx, |
691 | uint32_t inst) |
692 | { |
693 | struct dce_transform *transform = |
694 | kzalloc(size: sizeof(struct dce_transform), GFP_KERNEL); |
695 | |
696 | if (!transform) |
697 | return NULL; |
698 | |
699 | dce60_transform_construct(xfm_dce: transform, ctx, inst, |
700 | regs: &xfm_regs[inst], xfm_shift: &xfm_shift, xfm_mask: &xfm_mask); |
701 | transform->prescaler_on = false; |
702 | return &transform->base; |
703 | } |
704 | |
705 | static const struct encoder_feature_support link_enc_feature = { |
706 | .max_hdmi_deep_color = COLOR_DEPTH_121212, |
707 | .max_hdmi_pixel_clock = 297000, |
708 | .flags.bits.IS_HBR2_CAPABLE = true, |
709 | .flags.bits.IS_TPS3_CAPABLE = true |
710 | }; |
711 | |
712 | static struct link_encoder *dce60_link_encoder_create( |
713 | struct dc_context *ctx, |
714 | const struct encoder_init_data *enc_init_data) |
715 | { |
716 | struct dce110_link_encoder *enc110 = |
717 | kzalloc(size: sizeof(struct dce110_link_encoder), GFP_KERNEL); |
718 | int link_regs_id; |
719 | |
720 | if (!enc110) |
721 | return NULL; |
722 | |
723 | link_regs_id = |
724 | map_transmitter_id_to_phy_instance(transmitter: enc_init_data->transmitter); |
725 | |
726 | dce60_link_encoder_construct(enc110, |
727 | init_data: enc_init_data, |
728 | enc_features: &link_enc_feature, |
729 | link_regs: &link_enc_regs[link_regs_id], |
730 | aux_regs: &link_enc_aux_regs[enc_init_data->channel - 1], |
731 | hpd_regs: &link_enc_hpd_regs[enc_init_data->hpd_source]); |
732 | return &enc110->base; |
733 | } |
734 | |
735 | static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data) |
736 | { |
737 | struct dce_panel_cntl *panel_cntl = |
738 | kzalloc(size: sizeof(struct dce_panel_cntl), GFP_KERNEL); |
739 | |
740 | if (!panel_cntl) |
741 | return NULL; |
742 | |
743 | dce_panel_cntl_construct(panel_cntl, |
744 | init_data, |
745 | regs: &panel_cntl_regs[init_data->inst], |
746 | shift: &panel_cntl_shift, |
747 | mask: &panel_cntl_mask); |
748 | |
749 | return &panel_cntl->base; |
750 | } |
751 | |
752 | static struct clock_source *dce60_clock_source_create( |
753 | struct dc_context *ctx, |
754 | struct dc_bios *bios, |
755 | enum clock_source_id id, |
756 | const struct dce110_clk_src_regs *regs, |
757 | bool dp_clk_src) |
758 | { |
759 | struct dce110_clk_src *clk_src = |
760 | kzalloc(size: sizeof(struct dce110_clk_src), GFP_KERNEL); |
761 | |
762 | if (!clk_src) |
763 | return NULL; |
764 | |
765 | if (dce110_clk_src_construct(clk_src, ctx, bios, id, |
766 | regs, cs_shift: &cs_shift, cs_mask: &cs_mask)) { |
767 | clk_src->base.dp_clk_src = dp_clk_src; |
768 | return &clk_src->base; |
769 | } |
770 | |
771 | kfree(objp: clk_src); |
772 | BREAK_TO_DEBUGGER(); |
773 | return NULL; |
774 | } |
775 | |
776 | static void dce60_clock_source_destroy(struct clock_source **clk_src) |
777 | { |
778 | kfree(TO_DCE110_CLK_SRC(*clk_src)); |
779 | *clk_src = NULL; |
780 | } |
781 | |
782 | static struct input_pixel_processor *dce60_ipp_create( |
783 | struct dc_context *ctx, uint32_t inst) |
784 | { |
785 | struct dce_ipp *ipp = kzalloc(size: sizeof(struct dce_ipp), GFP_KERNEL); |
786 | |
787 | if (!ipp) { |
788 | BREAK_TO_DEBUGGER(); |
789 | return NULL; |
790 | } |
791 | |
792 | dce60_ipp_construct(ipp_dce: ipp, ctx, inst, |
793 | regs: &ipp_regs[inst], ipp_shift: &ipp_shift, ipp_mask: &ipp_mask); |
794 | return &ipp->base; |
795 | } |
796 | |
797 | static void dce60_resource_destruct(struct dce110_resource_pool *pool) |
798 | { |
799 | unsigned int i; |
800 | |
801 | for (i = 0; i < pool->base.pipe_count; i++) { |
802 | if (pool->base.opps[i] != NULL) |
803 | dce110_opp_destroy(opp: &pool->base.opps[i]); |
804 | |
805 | if (pool->base.transforms[i] != NULL) |
806 | dce60_transform_destroy(xfm: &pool->base.transforms[i]); |
807 | |
808 | if (pool->base.ipps[i] != NULL) |
809 | dce_ipp_destroy(ipp: &pool->base.ipps[i]); |
810 | |
811 | if (pool->base.mis[i] != NULL) { |
812 | kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); |
813 | pool->base.mis[i] = NULL; |
814 | } |
815 | |
816 | if (pool->base.timing_generators[i] != NULL) { |
817 | kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); |
818 | pool->base.timing_generators[i] = NULL; |
819 | } |
820 | } |
821 | |
822 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
823 | if (pool->base.engines[i] != NULL) |
824 | dce110_engine_destroy(engine: &pool->base.engines[i]); |
825 | if (pool->base.hw_i2cs[i] != NULL) { |
826 | kfree(objp: pool->base.hw_i2cs[i]); |
827 | pool->base.hw_i2cs[i] = NULL; |
828 | } |
829 | if (pool->base.sw_i2cs[i] != NULL) { |
830 | kfree(objp: pool->base.sw_i2cs[i]); |
831 | pool->base.sw_i2cs[i] = NULL; |
832 | } |
833 | } |
834 | |
835 | for (i = 0; i < pool->base.stream_enc_count; i++) { |
836 | if (pool->base.stream_enc[i] != NULL) |
837 | kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); |
838 | } |
839 | |
840 | for (i = 0; i < pool->base.clk_src_count; i++) { |
841 | if (pool->base.clock_sources[i] != NULL) { |
842 | dce60_clock_source_destroy(clk_src: &pool->base.clock_sources[i]); |
843 | } |
844 | } |
845 | |
846 | if (pool->base.abm != NULL) |
847 | dce_abm_destroy(abm: &pool->base.abm); |
848 | |
849 | if (pool->base.dmcu != NULL) |
850 | dce_dmcu_destroy(dmcu: &pool->base.dmcu); |
851 | |
852 | if (pool->base.dp_clock_source != NULL) |
853 | dce60_clock_source_destroy(clk_src: &pool->base.dp_clock_source); |
854 | |
855 | for (i = 0; i < pool->base.audio_count; i++) { |
856 | if (pool->base.audios[i] != NULL) { |
857 | dce_aud_destroy(audio: &pool->base.audios[i]); |
858 | } |
859 | } |
860 | |
861 | if (pool->base.irqs != NULL) { |
862 | dal_irq_service_destroy(irq_service: &pool->base.irqs); |
863 | } |
864 | } |
865 | |
866 | static bool dce60_validate_bandwidth( |
867 | struct dc *dc, |
868 | struct dc_state *context, |
869 | bool fast_validate) |
870 | { |
871 | int i; |
872 | bool at_least_one_pipe = false; |
873 | |
874 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
875 | if (context->res_ctx.pipe_ctx[i].stream) |
876 | at_least_one_pipe = true; |
877 | } |
878 | |
879 | if (at_least_one_pipe) { |
880 | /* TODO implement when needed but for now hardcode max value*/ |
881 | context->bw_ctx.bw.dce.dispclk_khz = 681000; |
882 | context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; |
883 | } else { |
884 | context->bw_ctx.bw.dce.dispclk_khz = 0; |
885 | context->bw_ctx.bw.dce.yclk_khz = 0; |
886 | } |
887 | |
888 | return true; |
889 | } |
890 | |
891 | static bool dce60_validate_surface_sets( |
892 | struct dc_state *context) |
893 | { |
894 | int i; |
895 | |
896 | for (i = 0; i < context->stream_count; i++) { |
897 | if (context->stream_status[i].plane_count == 0) |
898 | continue; |
899 | |
900 | if (context->stream_status[i].plane_count > 1) |
901 | return false; |
902 | |
903 | if (context->stream_status[i].plane_states[0]->format |
904 | >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
905 | return false; |
906 | } |
907 | |
908 | return true; |
909 | } |
910 | |
911 | static enum dc_status dce60_validate_global( |
912 | struct dc *dc, |
913 | struct dc_state *context) |
914 | { |
915 | if (!dce60_validate_surface_sets(context)) |
916 | return DC_FAIL_SURFACE_VALIDATE; |
917 | |
918 | return DC_OK; |
919 | } |
920 | |
921 | static void dce60_destroy_resource_pool(struct resource_pool **pool) |
922 | { |
923 | struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); |
924 | |
925 | dce60_resource_destruct(pool: dce110_pool); |
926 | kfree(objp: dce110_pool); |
927 | *pool = NULL; |
928 | } |
929 | |
930 | static const struct resource_funcs dce60_res_pool_funcs = { |
931 | .destroy = dce60_destroy_resource_pool, |
932 | .link_enc_create = dce60_link_encoder_create, |
933 | .panel_cntl_create = dce60_panel_cntl_create, |
934 | .validate_bandwidth = dce60_validate_bandwidth, |
935 | .validate_plane = dce100_validate_plane, |
936 | .add_stream_to_ctx = dce100_add_stream_to_ctx, |
937 | .validate_global = dce60_validate_global, |
938 | .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link |
939 | }; |
940 | |
941 | static bool dce60_construct( |
942 | uint8_t num_virtual_links, |
943 | struct dc *dc, |
944 | struct dce110_resource_pool *pool) |
945 | { |
946 | unsigned int i; |
947 | struct dc_context *ctx = dc->ctx; |
948 | struct dc_bios *bp; |
949 | |
950 | ctx->dc_bios->regs = &bios_regs; |
951 | |
952 | pool->base.res_cap = &res_cap; |
953 | pool->base.funcs = &dce60_res_pool_funcs; |
954 | |
955 | |
956 | /************************************************* |
957 | * Resource + asic cap harcoding * |
958 | *************************************************/ |
959 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
960 | pool->base.pipe_count = res_cap.num_timing_generator; |
961 | pool->base.timing_generator_count = res_cap.num_timing_generator; |
962 | dc->caps.max_downscale_ratio = 200; |
963 | dc->caps.i2c_speed_in_khz = 40; |
964 | dc->caps.max_cursor_size = 64; |
965 | dc->caps.dual_link_dvi = true; |
966 | dc->caps.extended_aux_timeout_support = false; |
967 | |
968 | /************************************************* |
969 | * Create resources * |
970 | *************************************************/ |
971 | |
972 | bp = ctx->dc_bios; |
973 | |
974 | if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { |
975 | pool->base.dp_clock_source = |
976 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_EXTERNAL, NULL, dp_clk_src: true); |
977 | |
978 | pool->base.clock_sources[0] = |
979 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL0, regs: &clk_src_regs[0], dp_clk_src: false); |
980 | pool->base.clock_sources[1] = |
981 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[1], dp_clk_src: false); |
982 | pool->base.clk_src_count = 2; |
983 | |
984 | } else { |
985 | pool->base.dp_clock_source = |
986 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL0, regs: &clk_src_regs[0], dp_clk_src: true); |
987 | |
988 | pool->base.clock_sources[0] = |
989 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[1], dp_clk_src: false); |
990 | pool->base.clk_src_count = 1; |
991 | } |
992 | |
993 | if (pool->base.dp_clock_source == NULL) { |
994 | dm_error("DC: failed to create dp clock source!\n" ); |
995 | BREAK_TO_DEBUGGER(); |
996 | goto res_create_fail; |
997 | } |
998 | |
999 | for (i = 0; i < pool->base.clk_src_count; i++) { |
1000 | if (pool->base.clock_sources[i] == NULL) { |
1001 | dm_error("DC: failed to create clock sources!\n" ); |
1002 | BREAK_TO_DEBUGGER(); |
1003 | goto res_create_fail; |
1004 | } |
1005 | } |
1006 | |
1007 | pool->base.dmcu = dce_dmcu_create(ctx, |
1008 | regs: &dmcu_regs, |
1009 | dmcu_shift: &dmcu_shift, |
1010 | dmcu_mask: &dmcu_mask); |
1011 | if (pool->base.dmcu == NULL) { |
1012 | dm_error("DC: failed to create dmcu!\n" ); |
1013 | BREAK_TO_DEBUGGER(); |
1014 | goto res_create_fail; |
1015 | } |
1016 | |
1017 | pool->base.abm = dce_abm_create(ctx, |
1018 | regs: &abm_regs, |
1019 | abm_shift: &abm_shift, |
1020 | abm_mask: &abm_mask); |
1021 | if (pool->base.abm == NULL) { |
1022 | dm_error("DC: failed to create abm!\n" ); |
1023 | BREAK_TO_DEBUGGER(); |
1024 | goto res_create_fail; |
1025 | } |
1026 | |
1027 | { |
1028 | struct irq_service_init_data init_data; |
1029 | init_data.ctx = dc->ctx; |
1030 | pool->base.irqs = dal_irq_service_dce60_create(init_data: &init_data); |
1031 | if (!pool->base.irqs) |
1032 | goto res_create_fail; |
1033 | } |
1034 | |
1035 | for (i = 0; i < pool->base.pipe_count; i++) { |
1036 | pool->base.timing_generators[i] = dce60_timing_generator_create( |
1037 | ctx, instance: i, offsets: &dce60_tg_offsets[i]); |
1038 | if (pool->base.timing_generators[i] == NULL) { |
1039 | BREAK_TO_DEBUGGER(); |
1040 | dm_error("DC: failed to create tg!\n" ); |
1041 | goto res_create_fail; |
1042 | } |
1043 | |
1044 | pool->base.mis[i] = dce60_mem_input_create(ctx, inst: i); |
1045 | if (pool->base.mis[i] == NULL) { |
1046 | BREAK_TO_DEBUGGER(); |
1047 | dm_error("DC: failed to create memory input!\n" ); |
1048 | goto res_create_fail; |
1049 | } |
1050 | |
1051 | pool->base.ipps[i] = dce60_ipp_create(ctx, inst: i); |
1052 | if (pool->base.ipps[i] == NULL) { |
1053 | BREAK_TO_DEBUGGER(); |
1054 | dm_error("DC: failed to create input pixel processor!\n" ); |
1055 | goto res_create_fail; |
1056 | } |
1057 | |
1058 | pool->base.transforms[i] = dce60_transform_create(ctx, inst: i); |
1059 | if (pool->base.transforms[i] == NULL) { |
1060 | BREAK_TO_DEBUGGER(); |
1061 | dm_error("DC: failed to create transform!\n" ); |
1062 | goto res_create_fail; |
1063 | } |
1064 | |
1065 | pool->base.opps[i] = dce60_opp_create(ctx, inst: i); |
1066 | if (pool->base.opps[i] == NULL) { |
1067 | BREAK_TO_DEBUGGER(); |
1068 | dm_error("DC: failed to create output pixel processor!\n" ); |
1069 | goto res_create_fail; |
1070 | } |
1071 | } |
1072 | |
1073 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
1074 | pool->base.engines[i] = dce60_aux_engine_create(ctx, inst: i); |
1075 | if (pool->base.engines[i] == NULL) { |
1076 | BREAK_TO_DEBUGGER(); |
1077 | dm_error( |
1078 | "DC:failed to create aux engine!!\n" ); |
1079 | goto res_create_fail; |
1080 | } |
1081 | pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, inst: i); |
1082 | if (pool->base.hw_i2cs[i] == NULL) { |
1083 | BREAK_TO_DEBUGGER(); |
1084 | dm_error( |
1085 | "DC:failed to create i2c engine!!\n" ); |
1086 | goto res_create_fail; |
1087 | } |
1088 | pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); |
1089 | if (pool->base.sw_i2cs[i] == NULL) { |
1090 | BREAK_TO_DEBUGGER(); |
1091 | dm_error( |
1092 | "DC:failed to create sw i2c!!\n" ); |
1093 | goto res_create_fail; |
1094 | } |
1095 | } |
1096 | |
1097 | dc->caps.max_planes = pool->base.pipe_count; |
1098 | |
1099 | for (i = 0; i < dc->caps.max_planes; ++i) |
1100 | dc->caps.planes[i] = plane_cap; |
1101 | |
1102 | dc->caps.disable_dp_clk_share = true; |
1103 | |
1104 | if (!resource_construct(num_virtual_links, dc, pool: &pool->base, |
1105 | create_funcs: &res_create_funcs)) |
1106 | goto res_create_fail; |
1107 | |
1108 | /* Create hardware sequencer */ |
1109 | dce60_hw_sequencer_construct(dc); |
1110 | |
1111 | return true; |
1112 | |
1113 | res_create_fail: |
1114 | dce60_resource_destruct(pool); |
1115 | return false; |
1116 | } |
1117 | |
1118 | struct resource_pool *dce60_create_resource_pool( |
1119 | uint8_t num_virtual_links, |
1120 | struct dc *dc) |
1121 | { |
1122 | struct dce110_resource_pool *pool = |
1123 | kzalloc(size: sizeof(struct dce110_resource_pool), GFP_KERNEL); |
1124 | |
1125 | if (!pool) |
1126 | return NULL; |
1127 | |
1128 | if (dce60_construct(num_virtual_links, dc, pool)) |
1129 | return &pool->base; |
1130 | |
1131 | kfree(objp: pool); |
1132 | BREAK_TO_DEBUGGER(); |
1133 | return NULL; |
1134 | } |
1135 | |
1136 | static bool dce61_construct( |
1137 | uint8_t num_virtual_links, |
1138 | struct dc *dc, |
1139 | struct dce110_resource_pool *pool) |
1140 | { |
1141 | unsigned int i; |
1142 | struct dc_context *ctx = dc->ctx; |
1143 | struct dc_bios *bp; |
1144 | |
1145 | ctx->dc_bios->regs = &bios_regs; |
1146 | |
1147 | pool->base.res_cap = &res_cap_61; |
1148 | pool->base.funcs = &dce60_res_pool_funcs; |
1149 | |
1150 | |
1151 | /************************************************* |
1152 | * Resource + asic cap harcoding * |
1153 | *************************************************/ |
1154 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
1155 | pool->base.pipe_count = res_cap_61.num_timing_generator; |
1156 | pool->base.timing_generator_count = res_cap_61.num_timing_generator; |
1157 | dc->caps.max_downscale_ratio = 200; |
1158 | dc->caps.i2c_speed_in_khz = 40; |
1159 | dc->caps.max_cursor_size = 64; |
1160 | dc->caps.is_apu = true; |
1161 | |
1162 | /************************************************* |
1163 | * Create resources * |
1164 | *************************************************/ |
1165 | |
1166 | bp = ctx->dc_bios; |
1167 | |
1168 | if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { |
1169 | pool->base.dp_clock_source = |
1170 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_EXTERNAL, NULL, dp_clk_src: true); |
1171 | |
1172 | pool->base.clock_sources[0] = |
1173 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL0, regs: &clk_src_regs[0], dp_clk_src: false); |
1174 | pool->base.clock_sources[1] = |
1175 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[1], dp_clk_src: false); |
1176 | pool->base.clock_sources[2] = |
1177 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL2, regs: &clk_src_regs[2], dp_clk_src: false); |
1178 | pool->base.clk_src_count = 3; |
1179 | |
1180 | } else { |
1181 | pool->base.dp_clock_source = |
1182 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL0, regs: &clk_src_regs[0], dp_clk_src: true); |
1183 | |
1184 | pool->base.clock_sources[0] = |
1185 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[1], dp_clk_src: false); |
1186 | pool->base.clock_sources[1] = |
1187 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL2, regs: &clk_src_regs[2], dp_clk_src: false); |
1188 | pool->base.clk_src_count = 2; |
1189 | } |
1190 | |
1191 | if (pool->base.dp_clock_source == NULL) { |
1192 | dm_error("DC: failed to create dp clock source!\n" ); |
1193 | BREAK_TO_DEBUGGER(); |
1194 | goto res_create_fail; |
1195 | } |
1196 | |
1197 | for (i = 0; i < pool->base.clk_src_count; i++) { |
1198 | if (pool->base.clock_sources[i] == NULL) { |
1199 | dm_error("DC: failed to create clock sources!\n" ); |
1200 | BREAK_TO_DEBUGGER(); |
1201 | goto res_create_fail; |
1202 | } |
1203 | } |
1204 | |
1205 | pool->base.dmcu = dce_dmcu_create(ctx, |
1206 | regs: &dmcu_regs, |
1207 | dmcu_shift: &dmcu_shift, |
1208 | dmcu_mask: &dmcu_mask); |
1209 | if (pool->base.dmcu == NULL) { |
1210 | dm_error("DC: failed to create dmcu!\n" ); |
1211 | BREAK_TO_DEBUGGER(); |
1212 | goto res_create_fail; |
1213 | } |
1214 | |
1215 | pool->base.abm = dce_abm_create(ctx, |
1216 | regs: &abm_regs, |
1217 | abm_shift: &abm_shift, |
1218 | abm_mask: &abm_mask); |
1219 | if (pool->base.abm == NULL) { |
1220 | dm_error("DC: failed to create abm!\n" ); |
1221 | BREAK_TO_DEBUGGER(); |
1222 | goto res_create_fail; |
1223 | } |
1224 | |
1225 | { |
1226 | struct irq_service_init_data init_data; |
1227 | init_data.ctx = dc->ctx; |
1228 | pool->base.irqs = dal_irq_service_dce60_create(init_data: &init_data); |
1229 | if (!pool->base.irqs) |
1230 | goto res_create_fail; |
1231 | } |
1232 | |
1233 | for (i = 0; i < pool->base.pipe_count; i++) { |
1234 | pool->base.timing_generators[i] = dce60_timing_generator_create( |
1235 | ctx, instance: i, offsets: &dce60_tg_offsets[i]); |
1236 | if (pool->base.timing_generators[i] == NULL) { |
1237 | BREAK_TO_DEBUGGER(); |
1238 | dm_error("DC: failed to create tg!\n" ); |
1239 | goto res_create_fail; |
1240 | } |
1241 | |
1242 | pool->base.mis[i] = dce60_mem_input_create(ctx, inst: i); |
1243 | if (pool->base.mis[i] == NULL) { |
1244 | BREAK_TO_DEBUGGER(); |
1245 | dm_error("DC: failed to create memory input!\n" ); |
1246 | goto res_create_fail; |
1247 | } |
1248 | |
1249 | pool->base.ipps[i] = dce60_ipp_create(ctx, inst: i); |
1250 | if (pool->base.ipps[i] == NULL) { |
1251 | BREAK_TO_DEBUGGER(); |
1252 | dm_error("DC: failed to create input pixel processor!\n" ); |
1253 | goto res_create_fail; |
1254 | } |
1255 | |
1256 | pool->base.transforms[i] = dce60_transform_create(ctx, inst: i); |
1257 | if (pool->base.transforms[i] == NULL) { |
1258 | BREAK_TO_DEBUGGER(); |
1259 | dm_error("DC: failed to create transform!\n" ); |
1260 | goto res_create_fail; |
1261 | } |
1262 | |
1263 | pool->base.opps[i] = dce60_opp_create(ctx, inst: i); |
1264 | if (pool->base.opps[i] == NULL) { |
1265 | BREAK_TO_DEBUGGER(); |
1266 | dm_error("DC: failed to create output pixel processor!\n" ); |
1267 | goto res_create_fail; |
1268 | } |
1269 | } |
1270 | |
1271 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
1272 | pool->base.engines[i] = dce60_aux_engine_create(ctx, inst: i); |
1273 | if (pool->base.engines[i] == NULL) { |
1274 | BREAK_TO_DEBUGGER(); |
1275 | dm_error( |
1276 | "DC:failed to create aux engine!!\n" ); |
1277 | goto res_create_fail; |
1278 | } |
1279 | pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, inst: i); |
1280 | if (pool->base.hw_i2cs[i] == NULL) { |
1281 | BREAK_TO_DEBUGGER(); |
1282 | dm_error( |
1283 | "DC:failed to create i2c engine!!\n" ); |
1284 | goto res_create_fail; |
1285 | } |
1286 | pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); |
1287 | if (pool->base.sw_i2cs[i] == NULL) { |
1288 | BREAK_TO_DEBUGGER(); |
1289 | dm_error( |
1290 | "DC:failed to create sw i2c!!\n" ); |
1291 | goto res_create_fail; |
1292 | } |
1293 | } |
1294 | |
1295 | dc->caps.max_planes = pool->base.pipe_count; |
1296 | |
1297 | for (i = 0; i < dc->caps.max_planes; ++i) |
1298 | dc->caps.planes[i] = plane_cap; |
1299 | |
1300 | dc->caps.disable_dp_clk_share = true; |
1301 | |
1302 | if (!resource_construct(num_virtual_links, dc, pool: &pool->base, |
1303 | create_funcs: &res_create_funcs)) |
1304 | goto res_create_fail; |
1305 | |
1306 | /* Create hardware sequencer */ |
1307 | dce60_hw_sequencer_construct(dc); |
1308 | |
1309 | return true; |
1310 | |
1311 | res_create_fail: |
1312 | dce60_resource_destruct(pool); |
1313 | return false; |
1314 | } |
1315 | |
1316 | struct resource_pool *dce61_create_resource_pool( |
1317 | uint8_t num_virtual_links, |
1318 | struct dc *dc) |
1319 | { |
1320 | struct dce110_resource_pool *pool = |
1321 | kzalloc(size: sizeof(struct dce110_resource_pool), GFP_KERNEL); |
1322 | |
1323 | if (!pool) |
1324 | return NULL; |
1325 | |
1326 | if (dce61_construct(num_virtual_links, dc, pool)) |
1327 | return &pool->base; |
1328 | |
1329 | kfree(objp: pool); |
1330 | BREAK_TO_DEBUGGER(); |
1331 | return NULL; |
1332 | } |
1333 | |
1334 | static bool dce64_construct( |
1335 | uint8_t num_virtual_links, |
1336 | struct dc *dc, |
1337 | struct dce110_resource_pool *pool) |
1338 | { |
1339 | unsigned int i; |
1340 | struct dc_context *ctx = dc->ctx; |
1341 | struct dc_bios *bp; |
1342 | |
1343 | ctx->dc_bios->regs = &bios_regs; |
1344 | |
1345 | pool->base.res_cap = &res_cap_64; |
1346 | pool->base.funcs = &dce60_res_pool_funcs; |
1347 | |
1348 | |
1349 | /************************************************* |
1350 | * Resource + asic cap harcoding * |
1351 | *************************************************/ |
1352 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
1353 | pool->base.pipe_count = res_cap_64.num_timing_generator; |
1354 | pool->base.timing_generator_count = res_cap_64.num_timing_generator; |
1355 | dc->caps.max_downscale_ratio = 200; |
1356 | dc->caps.i2c_speed_in_khz = 40; |
1357 | dc->caps.max_cursor_size = 64; |
1358 | dc->caps.is_apu = true; |
1359 | |
1360 | /************************************************* |
1361 | * Create resources * |
1362 | *************************************************/ |
1363 | |
1364 | bp = ctx->dc_bios; |
1365 | |
1366 | if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { |
1367 | pool->base.dp_clock_source = |
1368 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_EXTERNAL, NULL, dp_clk_src: true); |
1369 | |
1370 | pool->base.clock_sources[0] = |
1371 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[0], dp_clk_src: false); |
1372 | pool->base.clock_sources[1] = |
1373 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL2, regs: &clk_src_regs[1], dp_clk_src: false); |
1374 | pool->base.clk_src_count = 2; |
1375 | |
1376 | } else { |
1377 | pool->base.dp_clock_source = |
1378 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL1, regs: &clk_src_regs[0], dp_clk_src: true); |
1379 | |
1380 | pool->base.clock_sources[0] = |
1381 | dce60_clock_source_create(ctx, bios: bp, id: CLOCK_SOURCE_ID_PLL2, regs: &clk_src_regs[1], dp_clk_src: false); |
1382 | pool->base.clk_src_count = 1; |
1383 | } |
1384 | |
1385 | if (pool->base.dp_clock_source == NULL) { |
1386 | dm_error("DC: failed to create dp clock source!\n" ); |
1387 | BREAK_TO_DEBUGGER(); |
1388 | goto res_create_fail; |
1389 | } |
1390 | |
1391 | for (i = 0; i < pool->base.clk_src_count; i++) { |
1392 | if (pool->base.clock_sources[i] == NULL) { |
1393 | dm_error("DC: failed to create clock sources!\n" ); |
1394 | BREAK_TO_DEBUGGER(); |
1395 | goto res_create_fail; |
1396 | } |
1397 | } |
1398 | |
1399 | pool->base.dmcu = dce_dmcu_create(ctx, |
1400 | regs: &dmcu_regs, |
1401 | dmcu_shift: &dmcu_shift, |
1402 | dmcu_mask: &dmcu_mask); |
1403 | if (pool->base.dmcu == NULL) { |
1404 | dm_error("DC: failed to create dmcu!\n" ); |
1405 | BREAK_TO_DEBUGGER(); |
1406 | goto res_create_fail; |
1407 | } |
1408 | |
1409 | pool->base.abm = dce_abm_create(ctx, |
1410 | regs: &abm_regs, |
1411 | abm_shift: &abm_shift, |
1412 | abm_mask: &abm_mask); |
1413 | if (pool->base.abm == NULL) { |
1414 | dm_error("DC: failed to create abm!\n" ); |
1415 | BREAK_TO_DEBUGGER(); |
1416 | goto res_create_fail; |
1417 | } |
1418 | |
1419 | { |
1420 | struct irq_service_init_data init_data; |
1421 | init_data.ctx = dc->ctx; |
1422 | pool->base.irqs = dal_irq_service_dce60_create(init_data: &init_data); |
1423 | if (!pool->base.irqs) |
1424 | goto res_create_fail; |
1425 | } |
1426 | |
1427 | for (i = 0; i < pool->base.pipe_count; i++) { |
1428 | pool->base.timing_generators[i] = dce60_timing_generator_create( |
1429 | ctx, instance: i, offsets: &dce60_tg_offsets[i]); |
1430 | if (pool->base.timing_generators[i] == NULL) { |
1431 | BREAK_TO_DEBUGGER(); |
1432 | dm_error("DC: failed to create tg!\n" ); |
1433 | goto res_create_fail; |
1434 | } |
1435 | |
1436 | pool->base.mis[i] = dce60_mem_input_create(ctx, inst: i); |
1437 | if (pool->base.mis[i] == NULL) { |
1438 | BREAK_TO_DEBUGGER(); |
1439 | dm_error("DC: failed to create memory input!\n" ); |
1440 | goto res_create_fail; |
1441 | } |
1442 | |
1443 | pool->base.ipps[i] = dce60_ipp_create(ctx, inst: i); |
1444 | if (pool->base.ipps[i] == NULL) { |
1445 | BREAK_TO_DEBUGGER(); |
1446 | dm_error("DC: failed to create input pixel processor!\n" ); |
1447 | goto res_create_fail; |
1448 | } |
1449 | |
1450 | pool->base.transforms[i] = dce60_transform_create(ctx, inst: i); |
1451 | if (pool->base.transforms[i] == NULL) { |
1452 | BREAK_TO_DEBUGGER(); |
1453 | dm_error("DC: failed to create transform!\n" ); |
1454 | goto res_create_fail; |
1455 | } |
1456 | |
1457 | pool->base.opps[i] = dce60_opp_create(ctx, inst: i); |
1458 | if (pool->base.opps[i] == NULL) { |
1459 | BREAK_TO_DEBUGGER(); |
1460 | dm_error("DC: failed to create output pixel processor!\n" ); |
1461 | goto res_create_fail; |
1462 | } |
1463 | } |
1464 | |
1465 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
1466 | pool->base.engines[i] = dce60_aux_engine_create(ctx, inst: i); |
1467 | if (pool->base.engines[i] == NULL) { |
1468 | BREAK_TO_DEBUGGER(); |
1469 | dm_error( |
1470 | "DC:failed to create aux engine!!\n" ); |
1471 | goto res_create_fail; |
1472 | } |
1473 | pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, inst: i); |
1474 | if (pool->base.hw_i2cs[i] == NULL) { |
1475 | BREAK_TO_DEBUGGER(); |
1476 | dm_error( |
1477 | "DC:failed to create i2c engine!!\n" ); |
1478 | goto res_create_fail; |
1479 | } |
1480 | pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); |
1481 | if (pool->base.sw_i2cs[i] == NULL) { |
1482 | BREAK_TO_DEBUGGER(); |
1483 | dm_error( |
1484 | "DC:failed to create sw i2c!!\n" ); |
1485 | goto res_create_fail; |
1486 | } |
1487 | } |
1488 | |
1489 | dc->caps.max_planes = pool->base.pipe_count; |
1490 | |
1491 | for (i = 0; i < dc->caps.max_planes; ++i) |
1492 | dc->caps.planes[i] = plane_cap; |
1493 | |
1494 | dc->caps.disable_dp_clk_share = true; |
1495 | |
1496 | if (!resource_construct(num_virtual_links, dc, pool: &pool->base, |
1497 | create_funcs: &res_create_funcs)) |
1498 | goto res_create_fail; |
1499 | |
1500 | /* Create hardware sequencer */ |
1501 | dce60_hw_sequencer_construct(dc); |
1502 | |
1503 | return true; |
1504 | |
1505 | res_create_fail: |
1506 | dce60_resource_destruct(pool); |
1507 | return false; |
1508 | } |
1509 | |
1510 | struct resource_pool *dce64_create_resource_pool( |
1511 | uint8_t num_virtual_links, |
1512 | struct dc *dc) |
1513 | { |
1514 | struct dce110_resource_pool *pool = |
1515 | kzalloc(size: sizeof(struct dce110_resource_pool), GFP_KERNEL); |
1516 | |
1517 | if (!pool) |
1518 | return NULL; |
1519 | |
1520 | if (dce64_construct(num_virtual_links, dc, pool)) |
1521 | return &pool->base; |
1522 | |
1523 | kfree(objp: pool); |
1524 | BREAK_TO_DEBUGGER(); |
1525 | return NULL; |
1526 | } |
1527 | |