1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright 2023 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | //#include "dml2_utils.h" |
28 | #include "display_mode_core.h" |
29 | #include "dml_display_rq_dlg_calc.h" |
30 | #include "dml2_internal_types.h" |
31 | #include "dml2_translation_helper.h" |
32 | #include "dml2_utils.h" |
33 | |
34 | void dml2_util_copy_dml_timing(struct dml_timing_cfg_st *dml_timing_array, unsigned int dst_index, unsigned int src_index) |
35 | { |
36 | dml_timing_array->HTotal[dst_index] = dml_timing_array->HTotal[src_index]; |
37 | dml_timing_array->VTotal[dst_index] = dml_timing_array->VTotal[src_index]; |
38 | dml_timing_array->HBlankEnd[dst_index] = dml_timing_array->HBlankEnd[src_index]; |
39 | dml_timing_array->VBlankEnd[dst_index] = dml_timing_array->VBlankEnd[src_index]; |
40 | dml_timing_array->RefreshRate[dst_index] = dml_timing_array->RefreshRate[src_index]; |
41 | dml_timing_array->VFrontPorch[dst_index] = dml_timing_array->VFrontPorch[src_index]; |
42 | dml_timing_array->PixelClock[dst_index] = dml_timing_array->PixelClock[src_index]; |
43 | dml_timing_array->HActive[dst_index] = dml_timing_array->HActive[src_index]; |
44 | dml_timing_array->VActive[dst_index] = dml_timing_array->VActive[src_index]; |
45 | dml_timing_array->Interlace[dst_index] = dml_timing_array->Interlace[src_index]; |
46 | dml_timing_array->DRRDisplay[dst_index] = dml_timing_array->DRRDisplay[src_index]; |
47 | dml_timing_array->VBlankNom[dst_index] = dml_timing_array->VBlankNom[src_index]; |
48 | } |
49 | |
50 | void dml2_util_copy_dml_plane(struct dml_plane_cfg_st *dml_plane_array, unsigned int dst_index, unsigned int src_index) |
51 | { |
52 | dml_plane_array->GPUVMMinPageSizeKBytes[dst_index] = dml_plane_array->GPUVMMinPageSizeKBytes[src_index]; |
53 | dml_plane_array->ForceOneRowForFrame[dst_index] = dml_plane_array->ForceOneRowForFrame[src_index]; |
54 | dml_plane_array->PTEBufferModeOverrideEn[dst_index] = dml_plane_array->PTEBufferModeOverrideEn[src_index]; |
55 | dml_plane_array->PTEBufferMode[dst_index] = dml_plane_array->PTEBufferMode[src_index]; |
56 | dml_plane_array->ViewportWidth[dst_index] = dml_plane_array->ViewportWidth[src_index]; |
57 | dml_plane_array->ViewportHeight[dst_index] = dml_plane_array->ViewportHeight[src_index]; |
58 | dml_plane_array->ViewportWidthChroma[dst_index] = dml_plane_array->ViewportWidthChroma[src_index]; |
59 | dml_plane_array->ViewportHeightChroma[dst_index] = dml_plane_array->ViewportHeightChroma[src_index]; |
60 | dml_plane_array->ViewportXStart[dst_index] = dml_plane_array->ViewportXStart[src_index]; |
61 | dml_plane_array->ViewportXStartC[dst_index] = dml_plane_array->ViewportXStartC[src_index]; |
62 | dml_plane_array->ViewportYStart[dst_index] = dml_plane_array->ViewportYStart[src_index]; |
63 | dml_plane_array->ViewportYStartC[dst_index] = dml_plane_array->ViewportYStartC[src_index]; |
64 | dml_plane_array->ViewportStationary[dst_index] = dml_plane_array->ViewportStationary[src_index]; |
65 | |
66 | dml_plane_array->ScalerEnabled[dst_index] = dml_plane_array->ScalerEnabled[src_index]; |
67 | dml_plane_array->HRatio[dst_index] = dml_plane_array->HRatio[src_index]; |
68 | dml_plane_array->VRatio[dst_index] = dml_plane_array->VRatio[src_index]; |
69 | dml_plane_array->HRatioChroma[dst_index] = dml_plane_array->HRatioChroma[src_index]; |
70 | dml_plane_array->VRatioChroma[dst_index] = dml_plane_array->VRatioChroma[src_index]; |
71 | dml_plane_array->HTaps[dst_index] = dml_plane_array->HTaps[src_index]; |
72 | dml_plane_array->VTaps[dst_index] = dml_plane_array->VTaps[src_index]; |
73 | dml_plane_array->HTapsChroma[dst_index] = dml_plane_array->HTapsChroma[src_index]; |
74 | dml_plane_array->VTapsChroma[dst_index] = dml_plane_array->VTapsChroma[src_index]; |
75 | dml_plane_array->LBBitPerPixel[dst_index] = dml_plane_array->LBBitPerPixel[src_index]; |
76 | |
77 | dml_plane_array->SourceScan[dst_index] = dml_plane_array->SourceScan[src_index]; |
78 | dml_plane_array->ScalerRecoutWidth[dst_index] = dml_plane_array->ScalerRecoutWidth[src_index]; |
79 | |
80 | dml_plane_array->DynamicMetadataEnable[dst_index] = dml_plane_array->DynamicMetadataEnable[src_index]; |
81 | dml_plane_array->DynamicMetadataLinesBeforeActiveRequired[dst_index] = dml_plane_array->DynamicMetadataLinesBeforeActiveRequired[src_index]; |
82 | dml_plane_array->DynamicMetadataTransmittedBytes[dst_index] = dml_plane_array->DynamicMetadataTransmittedBytes[src_index]; |
83 | dml_plane_array->DETSizeOverride[dst_index] = dml_plane_array->DETSizeOverride[src_index]; |
84 | |
85 | dml_plane_array->NumberOfCursors[dst_index] = dml_plane_array->NumberOfCursors[src_index]; |
86 | dml_plane_array->CursorWidth[dst_index] = dml_plane_array->CursorWidth[src_index]; |
87 | dml_plane_array->CursorBPP[dst_index] = dml_plane_array->CursorBPP[src_index]; |
88 | |
89 | dml_plane_array->UseMALLForStaticScreen[dst_index] = dml_plane_array->UseMALLForStaticScreen[src_index]; |
90 | dml_plane_array->UseMALLForPStateChange[dst_index] = dml_plane_array->UseMALLForPStateChange[src_index]; |
91 | |
92 | dml_plane_array->BlendingAndTiming[dst_index] = dml_plane_array->BlendingAndTiming[src_index]; |
93 | } |
94 | |
95 | void dml2_util_copy_dml_surface(struct dml_surface_cfg_st *dml_surface_array, unsigned int dst_index, unsigned int src_index) |
96 | { |
97 | dml_surface_array->SurfaceTiling[dst_index] = dml_surface_array->SurfaceTiling[src_index]; |
98 | dml_surface_array->SourcePixelFormat[dst_index] = dml_surface_array->SourcePixelFormat[src_index]; |
99 | dml_surface_array->PitchY[dst_index] = dml_surface_array->PitchY[src_index]; |
100 | dml_surface_array->SurfaceWidthY[dst_index] = dml_surface_array->SurfaceWidthY[src_index]; |
101 | dml_surface_array->SurfaceHeightY[dst_index] = dml_surface_array->SurfaceHeightY[src_index]; |
102 | dml_surface_array->PitchC[dst_index] = dml_surface_array->PitchC[src_index]; |
103 | dml_surface_array->SurfaceWidthC[dst_index] = dml_surface_array->SurfaceWidthC[src_index]; |
104 | dml_surface_array->SurfaceHeightC[dst_index] = dml_surface_array->SurfaceHeightC[src_index]; |
105 | |
106 | dml_surface_array->DCCEnable[dst_index] = dml_surface_array->DCCEnable[src_index]; |
107 | dml_surface_array->DCCMetaPitchY[dst_index] = dml_surface_array->DCCMetaPitchY[src_index]; |
108 | dml_surface_array->DCCMetaPitchC[dst_index] = dml_surface_array->DCCMetaPitchC[src_index]; |
109 | |
110 | dml_surface_array->DCCRateLuma[dst_index] = dml_surface_array->DCCRateLuma[src_index]; |
111 | dml_surface_array->DCCRateChroma[dst_index] = dml_surface_array->DCCRateChroma[src_index]; |
112 | dml_surface_array->DCCFractionOfZeroSizeRequestsLuma[dst_index] = dml_surface_array->DCCFractionOfZeroSizeRequestsLuma[src_index]; |
113 | dml_surface_array->DCCFractionOfZeroSizeRequestsChroma[dst_index] = dml_surface_array->DCCFractionOfZeroSizeRequestsChroma[src_index]; |
114 | } |
115 | |
116 | void dml2_util_copy_dml_output(struct dml_output_cfg_st *dml_output_array, unsigned int dst_index, unsigned int src_index) |
117 | { |
118 | dml_output_array->DSCInputBitPerComponent[dst_index] = dml_output_array->DSCInputBitPerComponent[src_index]; |
119 | dml_output_array->OutputFormat[dst_index] = dml_output_array->OutputFormat[src_index]; |
120 | dml_output_array->OutputEncoder[dst_index] = dml_output_array->OutputEncoder[src_index]; |
121 | dml_output_array->OutputMultistreamId[dst_index] = dml_output_array->OutputMultistreamId[src_index]; |
122 | dml_output_array->OutputMultistreamEn[dst_index] = dml_output_array->OutputMultistreamEn[src_index]; |
123 | dml_output_array->OutputBpp[dst_index] = dml_output_array->OutputBpp[src_index]; |
124 | dml_output_array->PixelClockBackEnd[dst_index] = dml_output_array->PixelClockBackEnd[src_index]; |
125 | dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index]; |
126 | dml_output_array->OutputLinkDPLanes[dst_index] = dml_output_array->OutputLinkDPLanes[src_index]; |
127 | dml_output_array->OutputLinkDPRate[dst_index] = dml_output_array->OutputLinkDPRate[src_index]; |
128 | dml_output_array->ForcedOutputLinkBPP[dst_index] = dml_output_array->ForcedOutputLinkBPP[src_index]; |
129 | dml_output_array->AudioSampleRate[dst_index] = dml_output_array->AudioSampleRate[src_index]; |
130 | dml_output_array->AudioSampleLayout[dst_index] = dml_output_array->AudioSampleLayout[src_index]; |
131 | } |
132 | |
133 | unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, enum dml_output_encoder_class encoder, bool dsc_enabled) |
134 | { |
135 | switch (encoder) { |
136 | case dml_dp: |
137 | case dml_edp: |
138 | return 2; |
139 | case dml_dp2p0: |
140 | if (dsc_enabled || force_odm_4to1) |
141 | return 4; |
142 | else |
143 | return 2; |
144 | case dml_hdmi: |
145 | return 1; |
146 | case dml_hdmifrl: |
147 | if (force_odm_4to1) |
148 | return 4; |
149 | else |
150 | return 2; |
151 | default: |
152 | return 1; |
153 | } |
154 | } |
155 | |
156 | bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx) |
157 | { |
158 | if (pipe_ctx == NULL || pipe_ctx->stream == NULL) |
159 | return false; |
160 | |
161 | /* If this assert is hit then we have a link encoder dynamic management issue */ |
162 | ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); |
163 | |
164 | /* Count MST hubs once by treating only 1st remote sink in topology as an encoder */ |
165 | if (pipe_ctx->stream->link && pipe_ctx->stream->link->remote_sinks[0]) { |
166 | return (pipe_ctx->stream_res.hpo_dp_stream_enc && |
167 | pipe_ctx->link_res.hpo_dp_link_enc && |
168 | dc_is_dp_signal(signal: pipe_ctx->stream->signal) && |
169 | (pipe_ctx->stream->link->remote_sinks[0]->sink_id == pipe_ctx->stream->sink->sink_id)); |
170 | } |
171 | |
172 | return (pipe_ctx->stream_res.hpo_dp_stream_enc && |
173 | pipe_ctx->link_res.hpo_dp_link_enc && |
174 | dc_is_dp_signal(signal: pipe_ctx->stream->signal)); |
175 | } |
176 | |
177 | bool is_dtbclk_required(const struct dc *dc, struct dc_state *context) |
178 | { |
179 | int i; |
180 | |
181 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
182 | if (!context->res_ctx.pipe_ctx[i].stream) |
183 | continue; |
184 | if (is_dp2p0_output_encoder(pipe_ctx: &context->res_ctx.pipe_ctx[i])) |
185 | return true; |
186 | } |
187 | return false; |
188 | } |
189 | |
190 | void dml2_copy_clocks_to_dc_state(struct dml2_dcn_clocks *out_clks, struct dc_state *context) |
191 | { |
192 | context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; |
193 | context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; |
194 | context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; |
195 | context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; |
196 | context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; |
197 | context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; |
198 | context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; |
199 | context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported; |
200 | } |
201 | |
202 | int dml2_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id) |
203 | { |
204 | int i; |
205 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { |
206 | if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id) |
207 | return i; |
208 | } |
209 | |
210 | return -1; |
211 | } |
212 | |
213 | static int find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) |
214 | { |
215 | int i; |
216 | for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { |
217 | if (ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) |
218 | return i; |
219 | } |
220 | |
221 | return -1; |
222 | } |
223 | |
224 | static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *state, const struct dc_plane_state *plane, |
225 | unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id) |
226 | { |
227 | int i, j; |
228 | bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists; |
229 | |
230 | if (!plane_id) |
231 | return false; |
232 | |
233 | for (i = 0; i < state->stream_count; i++) { |
234 | if (state->streams[i]->stream_id == stream_id) { |
235 | for (j = 0; j < state->stream_status[i].plane_count; j++) { |
236 | if (state->stream_status[i].plane_states[j] == plane && |
237 | (!is_plane_duplicate || (j == plane_index))) { |
238 | *plane_id = (i << 16) | j; |
239 | return true; |
240 | } |
241 | } |
242 | } |
243 | } |
244 | |
245 | return false; |
246 | } |
247 | |
248 | static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, struct display_mode_lib_st *mode_lib, dml_uint_t pipe_idx) |
249 | { |
250 | unsigned int hactive, vactive, hblank_start, vblank_start, hblank_end, vblank_end; |
251 | struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; |
252 | |
253 | hactive = timing->h_addressable + timing->h_border_left + timing->h_border_right; |
254 | vactive = timing->v_addressable + timing->v_border_bottom + timing->v_border_top; |
255 | hblank_start = pipe_ctx->stream->timing.h_total - pipe_ctx->stream->timing.h_front_porch; |
256 | vblank_start = pipe_ctx->stream->timing.v_total - pipe_ctx->stream->timing.v_front_porch; |
257 | |
258 | hblank_end = hblank_start - timing->h_addressable - timing->h_border_left - timing->h_border_right; |
259 | vblank_end = vblank_start - timing->v_addressable - timing->v_border_top - timing->v_border_bottom; |
260 | |
261 | pipe_ctx->pipe_dlg_param.vstartup_start = dml_get_vstartup_calculated(mode_lib, surface_idx: pipe_idx); |
262 | pipe_ctx->pipe_dlg_param.vupdate_offset = dml_get_vupdate_offset(mode_lib, surface_idx: pipe_idx); |
263 | pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, surface_idx: pipe_idx); |
264 | pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, surface_idx: pipe_idx); |
265 | |
266 | pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; |
267 | |
268 | pipe_ctx->pipe_dlg_param.hactive = hactive; |
269 | pipe_ctx->pipe_dlg_param.vactive = vactive; |
270 | pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total; |
271 | pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total; |
272 | pipe_ctx->pipe_dlg_param.hblank_end = hblank_end; |
273 | pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; |
274 | pipe_ctx->pipe_dlg_param.hblank_start = hblank_start; |
275 | pipe_ctx->pipe_dlg_param.vblank_start = vblank_start; |
276 | pipe_ctx->pipe_dlg_param.vfront_porch = pipe_ctx->stream->timing.v_front_porch; |
277 | pipe_ctx->pipe_dlg_param.pixel_rate_mhz = pipe_ctx->stream->timing.pix_clk_100hz / 10000.00; |
278 | pipe_ctx->pipe_dlg_param.refresh_rate = ((timing->pix_clk_100hz * 100) / timing->h_total) / timing->v_total; |
279 | pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max; |
280 | pipe_ctx->pipe_dlg_param.vtotal_min = pipe_ctx->stream->adjust.v_total_min; |
281 | pipe_ctx->pipe_dlg_param.recout_height = pipe_ctx->plane_res.scl_data.recout.height; |
282 | pipe_ctx->pipe_dlg_param.recout_width = pipe_ctx->plane_res.scl_data.recout.width; |
283 | pipe_ctx->pipe_dlg_param.full_recout_height = pipe_ctx->plane_res.scl_data.recout.height; |
284 | pipe_ctx->pipe_dlg_param.full_recout_width = pipe_ctx->plane_res.scl_data.recout.width; |
285 | } |
286 | |
287 | void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt) |
288 | { |
289 | unsigned int dc_pipe_ctx_index, dml_pipe_idx, plane_id; |
290 | enum mall_stream_type pipe_mall_type; |
291 | bool unbounded_req_enabled = false; |
292 | struct dml2_calculate_rq_and_dlg_params_scratch *s = &in_ctx->v20.scratch.calculate_rq_and_dlg_params_scratch; |
293 | |
294 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000; |
295 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; |
296 | |
297 | if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx] == dml_fclock_change_unsupported) |
298 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; |
299 | else |
300 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; |
301 | |
302 | if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) |
303 | context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; |
304 | |
305 | unbounded_req_enabled = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState; |
306 | |
307 | if (unbounded_req_enabled && pipe_cnt > 1) { |
308 | // Unbounded requesting should not ever be used when more than 1 pipe is enabled. |
309 | //ASSERT(false); |
310 | unbounded_req_enabled = false; |
311 | } |
312 | |
313 | context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes; |
314 | |
315 | for (dc_pipe_ctx_index = 0; dc_pipe_ctx_index < pipe_cnt; dc_pipe_ctx_index++) { |
316 | if (!context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream) |
317 | continue; |
318 | /* The DML2 and the DC logic of determining pipe indices are different from each other so |
319 | * there is a need to know which DML pipe index maps to which DC pipe. The code below |
320 | * finds a dml_pipe_index from the plane id if a plane is valid. If a plane is not valid then |
321 | * it finds a dml_pipe_index from the stream id. */ |
322 | if (get_plane_id(dml2: in_ctx, state: context, plane: context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state, |
323 | stream_id: context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id, |
324 | plane_index: in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[context->res_ctx.pipe_ctx[dc_pipe_ctx_index].pipe_idx], plane_id: &plane_id)) { |
325 | dml_pipe_idx = find_dml_pipe_idx_by_plane_id(ctx: in_ctx, plane_id); |
326 | } else { |
327 | dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx: in_ctx, stream_id: context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id); |
328 | } |
329 | |
330 | ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[dml_pipe_idx]); |
331 | ASSERT(in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_pipe_idx] == context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream->stream_id); |
332 | |
333 | /* Use the dml_pipe_index here for the getters to fetch the correct values and dc_pipe_index in the pipe_ctx to populate them |
334 | * at the right locations. |
335 | */ |
336 | populate_pipe_ctx_dlg_params_from_dml(pipe_ctx: &context->res_ctx.pipe_ctx[dc_pipe_ctx_index], mode_lib: &context->bw_ctx.dml2->v20.dml_core_ctx, pipe_idx: dml_pipe_idx); |
337 | |
338 | pipe_mall_type = dc_state_get_pipe_subvp_type(state: context, pipe_ctx: &context->res_ctx.pipe_ctx[dc_pipe_ctx_index]); |
339 | if (pipe_mall_type == SUBVP_PHANTOM) { |
340 | // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests |
341 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = 0; |
342 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = false; |
343 | } else { |
344 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(mode_lib: &context->bw_ctx.dml2->v20.dml_core_ctx, surface_idx: dml_pipe_idx); |
345 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].unbounded_req = unbounded_req_enabled; |
346 | } |
347 | |
348 | context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb; |
349 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(mode_lib: &context->bw_ctx.dml2->v20.dml_core_ctx, surface_idx: dml_pipe_idx) * 1000; |
350 | if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz) |
351 | context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz; |
352 | |
353 | dml_rq_dlg_get_rq_reg(rq_regs: &s->rq_regs, mode_lib: &in_ctx->v20.dml_core_ctx, pipe_idx: dml_pipe_idx); |
354 | dml_rq_dlg_get_dlg_reg(dlg_regs: &s->disp_dlg_regs, ttu_regs: &s->disp_ttu_regs, mode_lib: &in_ctx->v20.dml_core_ctx, pipe_idx: dml_pipe_idx); |
355 | dml2_update_pipe_ctx_dchub_regs(rq_regs: &s->rq_regs, disp_dlg_regs: &s->disp_dlg_regs, disp_ttu_regs: &s->disp_ttu_regs, out: &out_new_hw_state->pipe_ctx[dc_pipe_ctx_index]); |
356 | |
357 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(mode_lib: &context->bw_ctx.dml2->v20.dml_core_ctx, surface_idx: dml_pipe_idx); |
358 | |
359 | /* Reuse MALL Allocation Sizes logic from dcn32_fpu.c */ |
360 | /* Count from active, top pipes per plane only. Only add mall_ss_size_bytes for each unique plane. */ |
361 | if (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].stream && context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state && |
362 | (context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe == NULL || |
363 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_state != context->res_ctx.pipe_ctx[dc_pipe_ctx_index].top_pipe->plane_state) && |
364 | context->res_ctx.pipe_ctx[dc_pipe_ctx_index].prev_odm_pipe == NULL) { |
365 | /* SS: all active surfaces stored in MALL */ |
366 | if (pipe_mall_type != SUBVP_PHANTOM) { |
367 | context->bw_ctx.bw.dcn.mall_ss_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes; |
368 | } else { |
369 | /* SUBVP: phantom surfaces only stored in MALL */ |
370 | context->bw_ctx.bw.dcn.mall_subvp_size_bytes += context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes; |
371 | } |
372 | } |
373 | } |
374 | |
375 | context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; |
376 | context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; |
377 | context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz |
378 | * 1000; |
379 | context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz |
380 | * 1000; |
381 | } |
382 | |
383 | void (struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx) |
384 | { |
385 | watermark->urgent_ns = dml_get_wm_urgent(mode_lib: dml_core_ctx) * 1000; |
386 | watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(mode_lib: dml_core_ctx) * 1000; |
387 | watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(mode_lib: dml_core_ctx) * 1000; |
388 | watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(mode_lib: dml_core_ctx) * 1000; |
389 | watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(mode_lib: dml_core_ctx) * 1000; |
390 | watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(mode_lib: dml_core_ctx) * 1000; |
391 | watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(mode_lib: dml_core_ctx) * 1000; |
392 | watermark->urgent_latency_ns = dml_get_urgent_latency(mode_lib: dml_core_ctx) * 1000; |
393 | watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(mode_lib: dml_core_ctx) * 1000; |
394 | watermark->usr_retraining_ns = dml_get_wm_usr_retraining(mode_lib: dml_core_ctx) * 1000; |
395 | watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(mode_lib: dml_core_ctx) * 1000; |
396 | watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(mode_lib: dml_core_ctx) * 1000; |
397 | } |
398 | |
399 | void dml2_initialize_det_scratch(struct dml2_context *in_ctx) |
400 | { |
401 | int i; |
402 | |
403 | for (i = 0; i < MAX_PLANES; i++) { |
404 | in_ctx->det_helper_scratch.dpps_per_surface[i] = 1; |
405 | } |
406 | } |
407 | |
408 | static unsigned int find_planes_per_stream_and_stream_count(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg, int *num_of_planes_per_stream) |
409 | { |
410 | unsigned int plane_index, stream_index = 0, num_of_streams; |
411 | |
412 | for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) { |
413 | /* Number of planes per stream */ |
414 | num_of_planes_per_stream[stream_index] += 1; |
415 | |
416 | if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1]) |
417 | stream_index++; |
418 | } |
419 | |
420 | num_of_streams = stream_index + 1; |
421 | |
422 | return num_of_streams; |
423 | } |
424 | |
425 | void dml2_apply_det_buffer_allocation_policy(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg) |
426 | { |
427 | unsigned int num_of_streams = 0, plane_index = 0, max_det_size, stream_index = 0; |
428 | int num_of_planes_per_stream[__DML_NUM_PLANES__] = { 0 }; |
429 | |
430 | max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp; |
431 | |
432 | num_of_streams = find_planes_per_stream_and_stream_count(in_ctx, dml_dispcfg, num_of_planes_per_stream); |
433 | |
434 | for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) { |
435 | |
436 | if (in_ctx->config.override_det_buffer_size_kbytes) |
437 | dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count; |
438 | else { |
439 | dml_dispcfg->plane.DETSizeOverride[plane_index] = ((max_det_size / num_of_streams) / num_of_planes_per_stream[stream_index] / in_ctx->det_helper_scratch.dpps_per_surface[plane_index]); |
440 | |
441 | /* If the override size is not divisible by det_segment_size then round off to nearest number divisible by det_segment_size as |
442 | * this is a requirement. |
443 | */ |
444 | if (dml_dispcfg->plane.DETSizeOverride[plane_index] % in_ctx->config.det_segment_size != 0) { |
445 | dml_dispcfg->plane.DETSizeOverride[plane_index] = dml_dispcfg->plane.DETSizeOverride[plane_index] & ~0x3F; |
446 | } |
447 | |
448 | if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_index] != dml_dispcfg->plane.BlendingAndTiming[plane_index + 1]) |
449 | stream_index++; |
450 | } |
451 | } |
452 | } |
453 | |
454 | bool dml2_verify_det_buffer_configuration(struct dml2_context *in_ctx, struct dc_state *display_state, struct dml2_helper_det_policy_scratch *det_scratch) |
455 | { |
456 | unsigned int i = 0, dml_pipe_idx = 0, plane_id = 0; |
457 | unsigned int max_det_size, total_det_allocated = 0; |
458 | bool need_recalculation = false; |
459 | |
460 | max_det_size = in_ctx->config.det_segment_size * in_ctx->config.max_segments_per_hubp; |
461 | |
462 | for (i = 0; i < MAX_PIPES; i++) { |
463 | if (!display_state->res_ctx.pipe_ctx[i].stream) |
464 | continue; |
465 | if (get_plane_id(dml2: in_ctx, state: display_state, plane: display_state->res_ctx.pipe_ctx[i].plane_state, |
466 | stream_id: display_state->res_ctx.pipe_ctx[i].stream->stream_id, |
467 | plane_index: in_ctx->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_index[display_state->res_ctx.pipe_ctx[i].pipe_idx], plane_id: &plane_id)) |
468 | dml_pipe_idx = find_dml_pipe_idx_by_plane_id(ctx: in_ctx, plane_id); |
469 | else |
470 | dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx: in_ctx, stream_id: display_state->res_ctx.pipe_ctx[i].stream->stream_id); |
471 | total_det_allocated += dml_get_det_buffer_size_kbytes(mode_lib: &in_ctx->v20.dml_core_ctx, surface_idx: dml_pipe_idx); |
472 | if (total_det_allocated > max_det_size) { |
473 | need_recalculation = true; |
474 | } |
475 | } |
476 | |
477 | /* Store the DPPPerSurface for correctly determining the number of planes in the next call. */ |
478 | for (i = 0; i < MAX_PLANES; i++) { |
479 | det_scratch->dpps_per_surface[i] = in_ctx->v20.scratch.cur_display_config.hw.DPPPerSurface[i]; |
480 | } |
481 | |
482 | return need_recalculation; |
483 | } |
484 | |
485 | bool dml2_is_stereo_timing(const struct dc_stream_state *stream) |
486 | { |
487 | bool is_stereo = false; |
488 | |
489 | if ((stream->view_format == |
490 | VIEW_3D_FORMAT_SIDE_BY_SIDE || |
491 | stream->view_format == |
492 | VIEW_3D_FORMAT_TOP_AND_BOTTOM) && |
493 | (stream->timing.timing_3d_format == |
494 | TIMING_3D_FORMAT_TOP_AND_BOTTOM || |
495 | stream->timing.timing_3d_format == |
496 | TIMING_3D_FORMAT_SIDE_BY_SIDE)) |
497 | is_stereo = true; |
498 | |
499 | return is_stereo; |
500 | } |
501 | |