1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice (including the next |
13 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: |
25 | * Eric Anholt <eric@anholt.net> |
26 | * Dave Airlie <airlied@linux.ie> |
27 | * Jesse Barnes <jesse.barnes@intel.com> |
28 | */ |
29 | |
30 | #include <acpi/button.h> |
31 | #include <linux/acpi.h> |
32 | #include <linux/dmi.h> |
33 | #include <linux/i2c.h> |
34 | #include <linux/slab.h> |
35 | #include <linux/vga_switcheroo.h> |
36 | |
37 | #include <drm/drm_atomic_helper.h> |
38 | #include <drm/drm_crtc.h> |
39 | #include <drm/drm_edid.h> |
40 | |
41 | #include "i915_drv.h" |
42 | #include "i915_reg.h" |
43 | #include "intel_atomic.h" |
44 | #include "intel_backlight.h" |
45 | #include "intel_connector.h" |
46 | #include "intel_de.h" |
47 | #include "intel_display_types.h" |
48 | #include "intel_dpll.h" |
49 | #include "intel_fdi.h" |
50 | #include "intel_gmbus.h" |
51 | #include "intel_lvds.h" |
52 | #include "intel_lvds_regs.h" |
53 | #include "intel_panel.h" |
54 | #include "intel_pps_regs.h" |
55 | |
56 | /* Private structure for the integrated LVDS support */ |
57 | struct intel_lvds_pps { |
58 | /* 100us units */ |
59 | int t1_t2; |
60 | int t3; |
61 | int t4; |
62 | int t5; |
63 | int tx; |
64 | |
65 | int divider; |
66 | |
67 | int port; |
68 | bool powerdown_on_reset; |
69 | }; |
70 | |
71 | struct intel_lvds_encoder { |
72 | struct intel_encoder base; |
73 | |
74 | bool is_dual_link; |
75 | i915_reg_t reg; |
76 | u32 a3_power; |
77 | |
78 | struct intel_lvds_pps init_pps; |
79 | u32 init_lvds_val; |
80 | |
81 | struct intel_connector *attached_connector; |
82 | }; |
83 | |
84 | static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) |
85 | { |
86 | return container_of(encoder, struct intel_lvds_encoder, base); |
87 | } |
88 | |
89 | bool intel_lvds_port_enabled(struct drm_i915_private *i915, |
90 | i915_reg_t lvds_reg, enum pipe *pipe) |
91 | { |
92 | u32 val; |
93 | |
94 | val = intel_de_read(i915, reg: lvds_reg); |
95 | |
96 | /* asserts want to know the pipe even if the port is disabled */ |
97 | if (HAS_PCH_CPT(i915)) |
98 | *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val); |
99 | else |
100 | *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val); |
101 | |
102 | return val & LVDS_PORT_EN; |
103 | } |
104 | |
105 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
106 | enum pipe *pipe) |
107 | { |
108 | struct drm_i915_private *i915 = to_i915(dev: encoder->base.dev); |
109 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
110 | intel_wakeref_t wakeref; |
111 | bool ret; |
112 | |
113 | wakeref = intel_display_power_get_if_enabled(dev_priv: i915, domain: encoder->power_domain); |
114 | if (!wakeref) |
115 | return false; |
116 | |
117 | ret = intel_lvds_port_enabled(i915, lvds_reg: lvds_encoder->reg, pipe); |
118 | |
119 | intel_display_power_put(dev_priv: i915, domain: encoder->power_domain, wakeref); |
120 | |
121 | return ret; |
122 | } |
123 | |
124 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
125 | struct intel_crtc_state *crtc_state) |
126 | { |
127 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
128 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
129 | u32 tmp, flags = 0; |
130 | |
131 | crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); |
132 | |
133 | tmp = intel_de_read(i915: dev_priv, reg: lvds_encoder->reg); |
134 | if (tmp & LVDS_HSYNC_POLARITY) |
135 | flags |= DRM_MODE_FLAG_NHSYNC; |
136 | else |
137 | flags |= DRM_MODE_FLAG_PHSYNC; |
138 | if (tmp & LVDS_VSYNC_POLARITY) |
139 | flags |= DRM_MODE_FLAG_NVSYNC; |
140 | else |
141 | flags |= DRM_MODE_FLAG_PVSYNC; |
142 | |
143 | crtc_state->hw.adjusted_mode.flags |= flags; |
144 | |
145 | if (DISPLAY_VER(dev_priv) < 5) |
146 | crtc_state->gmch_pfit.lvds_border_bits = |
147 | tmp & LVDS_BORDER_ENABLE; |
148 | |
149 | /* gen2/3 store dither state in pfit control, needs to match */ |
150 | if (DISPLAY_VER(dev_priv) < 4) { |
151 | tmp = intel_de_read(i915: dev_priv, PFIT_CONTROL); |
152 | |
153 | crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; |
154 | } |
155 | |
156 | crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; |
157 | } |
158 | |
159 | static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, |
160 | struct intel_lvds_pps *pps) |
161 | { |
162 | u32 val; |
163 | |
164 | pps->powerdown_on_reset = intel_de_read(i915: dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; |
165 | |
166 | val = intel_de_read(i915: dev_priv, PP_ON_DELAYS(0)); |
167 | pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); |
168 | pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); |
169 | pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); |
170 | |
171 | val = intel_de_read(i915: dev_priv, PP_OFF_DELAYS(0)); |
172 | pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); |
173 | pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); |
174 | |
175 | val = intel_de_read(i915: dev_priv, PP_DIVISOR(0)); |
176 | pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); |
177 | val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); |
178 | /* |
179 | * Remove the BSpec specified +1 (100ms) offset that accounts for a |
180 | * too short power-cycle delay due to the asynchronous programming of |
181 | * the register. |
182 | */ |
183 | if (val) |
184 | val--; |
185 | /* Convert from 100ms to 100us units */ |
186 | pps->t4 = val * 1000; |
187 | |
188 | if (DISPLAY_VER(dev_priv) < 5 && |
189 | pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { |
190 | drm_dbg_kms(&dev_priv->drm, |
191 | "Panel power timings uninitialized, " |
192 | "setting defaults\n" ); |
193 | /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ |
194 | pps->t1_t2 = 40 * 10; |
195 | pps->t5 = 200 * 10; |
196 | /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ |
197 | pps->t3 = 35 * 10; |
198 | pps->tx = 200 * 10; |
199 | } |
200 | |
201 | drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " |
202 | "divider %d port %d powerdown_on_reset %d\n" , |
203 | pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, |
204 | pps->divider, pps->port, pps->powerdown_on_reset); |
205 | } |
206 | |
207 | static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, |
208 | struct intel_lvds_pps *pps) |
209 | { |
210 | u32 val; |
211 | |
212 | val = intel_de_read(i915: dev_priv, PP_CONTROL(0)); |
213 | drm_WARN_ON(&dev_priv->drm, |
214 | (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); |
215 | if (pps->powerdown_on_reset) |
216 | val |= PANEL_POWER_RESET; |
217 | intel_de_write(i915: dev_priv, PP_CONTROL(0), val); |
218 | |
219 | intel_de_write(i915: dev_priv, PP_ON_DELAYS(0), |
220 | REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | |
221 | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | |
222 | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); |
223 | |
224 | intel_de_write(i915: dev_priv, PP_OFF_DELAYS(0), |
225 | REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | |
226 | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); |
227 | |
228 | intel_de_write(i915: dev_priv, PP_DIVISOR(0), |
229 | REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | |
230 | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); |
231 | } |
232 | |
233 | static void intel_pre_enable_lvds(struct intel_atomic_state *state, |
234 | struct intel_encoder *encoder, |
235 | const struct intel_crtc_state *crtc_state, |
236 | const struct drm_connector_state *conn_state) |
237 | { |
238 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
239 | struct drm_i915_private *i915 = to_i915(dev: encoder->base.dev); |
240 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
241 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
242 | enum pipe pipe = crtc->pipe; |
243 | u32 temp; |
244 | |
245 | if (HAS_PCH_SPLIT(i915)) { |
246 | assert_fdi_rx_pll_disabled(i915, pipe); |
247 | assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); |
248 | } else { |
249 | assert_pll_disabled(i915, pipe); |
250 | } |
251 | |
252 | intel_lvds_pps_init_hw(dev_priv: i915, pps: &lvds_encoder->init_pps); |
253 | |
254 | temp = lvds_encoder->init_lvds_val; |
255 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
256 | |
257 | if (HAS_PCH_CPT(i915)) { |
258 | temp &= ~LVDS_PIPE_SEL_MASK_CPT; |
259 | temp |= LVDS_PIPE_SEL_CPT(pipe); |
260 | } else { |
261 | temp &= ~LVDS_PIPE_SEL_MASK; |
262 | temp |= LVDS_PIPE_SEL(pipe); |
263 | } |
264 | |
265 | /* set the corresponsding LVDS_BORDER bit */ |
266 | temp &= ~LVDS_BORDER_ENABLE; |
267 | temp |= crtc_state->gmch_pfit.lvds_border_bits; |
268 | |
269 | /* |
270 | * Set the B0-B3 data pairs corresponding to whether we're going to |
271 | * set the DPLLs for dual-channel mode or not. |
272 | */ |
273 | if (lvds_encoder->is_dual_link) |
274 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
275 | else |
276 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
277 | |
278 | /* |
279 | * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
280 | * appropriately here, but we need to look more thoroughly into how |
281 | * panels behave in the two modes. For now, let's just maintain the |
282 | * value we got from the BIOS. |
283 | */ |
284 | temp &= ~LVDS_A3_POWER_MASK; |
285 | temp |= lvds_encoder->a3_power; |
286 | |
287 | /* |
288 | * Set the dithering flag on LVDS as needed, note that there is no |
289 | * special lvds dither control bit on pch-split platforms, dithering is |
290 | * only controlled through the TRANSCONF reg. |
291 | */ |
292 | if (DISPLAY_VER(i915) == 4) { |
293 | /* |
294 | * Bspec wording suggests that LVDS port dithering only exists |
295 | * for 18bpp panels. |
296 | */ |
297 | if (crtc_state->dither && crtc_state->pipe_bpp == 18) |
298 | temp |= LVDS_ENABLE_DITHER; |
299 | else |
300 | temp &= ~LVDS_ENABLE_DITHER; |
301 | } |
302 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
303 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
304 | temp |= LVDS_HSYNC_POLARITY; |
305 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
306 | temp |= LVDS_VSYNC_POLARITY; |
307 | |
308 | intel_de_write(i915, reg: lvds_encoder->reg, val: temp); |
309 | } |
310 | |
311 | /* |
312 | * Sets the power state for the panel. |
313 | */ |
314 | static void intel_enable_lvds(struct intel_atomic_state *state, |
315 | struct intel_encoder *encoder, |
316 | const struct intel_crtc_state *crtc_state, |
317 | const struct drm_connector_state *conn_state) |
318 | { |
319 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
320 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
321 | |
322 | intel_de_rmw(i915: dev_priv, reg: lvds_encoder->reg, clear: 0, LVDS_PORT_EN); |
323 | |
324 | intel_de_rmw(i915: dev_priv, PP_CONTROL(0), clear: 0, PANEL_POWER_ON); |
325 | intel_de_posting_read(i915: dev_priv, reg: lvds_encoder->reg); |
326 | |
327 | if (intel_de_wait_for_set(i915: dev_priv, PP_STATUS(0), PP_ON, timeout: 5000)) |
328 | drm_err(&dev_priv->drm, |
329 | "timed out waiting for panel to power on\n" ); |
330 | |
331 | intel_backlight_enable(crtc_state, conn_state); |
332 | } |
333 | |
334 | static void intel_disable_lvds(struct intel_atomic_state *state, |
335 | struct intel_encoder *encoder, |
336 | const struct intel_crtc_state *old_crtc_state, |
337 | const struct drm_connector_state *old_conn_state) |
338 | { |
339 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
340 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
341 | |
342 | intel_de_rmw(i915: dev_priv, PP_CONTROL(0), PANEL_POWER_ON, set: 0); |
343 | if (intel_de_wait_for_clear(i915: dev_priv, PP_STATUS(0), PP_ON, timeout: 1000)) |
344 | drm_err(&dev_priv->drm, |
345 | "timed out waiting for panel to power off\n" ); |
346 | |
347 | intel_de_rmw(i915: dev_priv, reg: lvds_encoder->reg, LVDS_PORT_EN, set: 0); |
348 | intel_de_posting_read(i915: dev_priv, reg: lvds_encoder->reg); |
349 | } |
350 | |
351 | static void gmch_disable_lvds(struct intel_atomic_state *state, |
352 | struct intel_encoder *encoder, |
353 | const struct intel_crtc_state *old_crtc_state, |
354 | const struct drm_connector_state *old_conn_state) |
355 | |
356 | { |
357 | intel_backlight_disable(old_conn_state); |
358 | |
359 | intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); |
360 | } |
361 | |
362 | static void pch_disable_lvds(struct intel_atomic_state *state, |
363 | struct intel_encoder *encoder, |
364 | const struct intel_crtc_state *old_crtc_state, |
365 | const struct drm_connector_state *old_conn_state) |
366 | { |
367 | intel_backlight_disable(old_conn_state); |
368 | } |
369 | |
370 | static void pch_post_disable_lvds(struct intel_atomic_state *state, |
371 | struct intel_encoder *encoder, |
372 | const struct intel_crtc_state *old_crtc_state, |
373 | const struct drm_connector_state *old_conn_state) |
374 | { |
375 | intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); |
376 | } |
377 | |
378 | static void intel_lvds_shutdown(struct intel_encoder *encoder) |
379 | { |
380 | struct drm_i915_private *dev_priv = to_i915(dev: encoder->base.dev); |
381 | |
382 | if (intel_de_wait_for_clear(i915: dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, timeout: 5000)) |
383 | drm_err(&dev_priv->drm, |
384 | "timed out waiting for panel power cycle delay\n" ); |
385 | } |
386 | |
387 | static enum drm_mode_status |
388 | intel_lvds_mode_valid(struct drm_connector *_connector, |
389 | struct drm_display_mode *mode) |
390 | { |
391 | struct intel_connector *connector = to_intel_connector(_connector); |
392 | struct drm_i915_private *i915 = to_i915(dev: connector->base.dev); |
393 | const struct drm_display_mode *fixed_mode = |
394 | intel_panel_fixed_mode(connector, mode); |
395 | int max_pixclk = to_i915(dev: connector->base.dev)->max_dotclk_freq; |
396 | enum drm_mode_status status; |
397 | |
398 | status = intel_cpu_transcoder_mode_valid(i915, mode); |
399 | if (status != MODE_OK) |
400 | return status; |
401 | |
402 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
403 | return MODE_NO_DBLESCAN; |
404 | |
405 | status = intel_panel_mode_valid(connector, mode); |
406 | if (status != MODE_OK) |
407 | return status; |
408 | |
409 | if (fixed_mode->clock > max_pixclk) |
410 | return MODE_CLOCK_HIGH; |
411 | |
412 | return MODE_OK; |
413 | } |
414 | |
415 | static int intel_lvds_compute_config(struct intel_encoder *encoder, |
416 | struct intel_crtc_state *crtc_state, |
417 | struct drm_connector_state *conn_state) |
418 | { |
419 | struct drm_i915_private *i915 = to_i915(dev: encoder->base.dev); |
420 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
421 | struct intel_connector *connector = lvds_encoder->attached_connector; |
422 | struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
423 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
424 | unsigned int lvds_bpp; |
425 | int ret; |
426 | |
427 | /* Should never happen!! */ |
428 | if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { |
429 | drm_err(&i915->drm, "Can't support LVDS on pipe A\n" ); |
430 | return -EINVAL; |
431 | } |
432 | |
433 | if (HAS_PCH_SPLIT(i915)) { |
434 | crtc_state->has_pch_encoder = true; |
435 | if (!intel_fdi_compute_pipe_bpp(crtc_state)) |
436 | return -EINVAL; |
437 | } |
438 | |
439 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
440 | lvds_bpp = 8*3; |
441 | else |
442 | lvds_bpp = 6*3; |
443 | |
444 | /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ |
445 | if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { |
446 | drm_dbg_kms(&i915->drm, |
447 | "forcing display bpp (was %d) to LVDS (%d)\n" , |
448 | crtc_state->pipe_bpp, lvds_bpp); |
449 | crtc_state->pipe_bpp = lvds_bpp; |
450 | } |
451 | |
452 | crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; |
453 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; |
454 | |
455 | /* |
456 | * We have timings from the BIOS for the panel, put them in |
457 | * to the adjusted mode. The CRTC will be set up for this mode, |
458 | * with the panel scaling set up to source from the H/VDisplay |
459 | * of the original mode. |
460 | */ |
461 | ret = intel_panel_compute_config(connector, adjusted_mode); |
462 | if (ret) |
463 | return ret; |
464 | |
465 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
466 | return -EINVAL; |
467 | |
468 | ret = intel_panel_fitting(crtc_state, conn_state); |
469 | if (ret) |
470 | return ret; |
471 | |
472 | /* |
473 | * XXX: It would be nice to support lower refresh rates on the |
474 | * panels to reduce power consumption, and perhaps match the |
475 | * user's requested refresh rate. |
476 | */ |
477 | |
478 | return 0; |
479 | } |
480 | |
481 | /* |
482 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. |
483 | */ |
484 | static int intel_lvds_get_modes(struct drm_connector *_connector) |
485 | { |
486 | struct intel_connector *connector = to_intel_connector(_connector); |
487 | const struct drm_edid *fixed_edid = connector->panel.fixed_edid; |
488 | |
489 | /* Use panel fixed edid if we have one */ |
490 | if (!IS_ERR_OR_NULL(ptr: fixed_edid)) { |
491 | drm_edid_connector_update(connector: &connector->base, edid: fixed_edid); |
492 | |
493 | return drm_edid_connector_add_modes(connector: &connector->base); |
494 | } |
495 | |
496 | return intel_panel_get_modes(connector); |
497 | } |
498 | |
499 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
500 | .get_modes = intel_lvds_get_modes, |
501 | .mode_valid = intel_lvds_mode_valid, |
502 | .atomic_check = intel_digital_connector_atomic_check, |
503 | }; |
504 | |
505 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { |
506 | .detect = intel_panel_detect, |
507 | .fill_modes = drm_helper_probe_single_connector_modes, |
508 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
509 | .atomic_set_property = intel_digital_connector_atomic_set_property, |
510 | .late_register = intel_connector_register, |
511 | .early_unregister = intel_connector_unregister, |
512 | .destroy = intel_connector_destroy, |
513 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
514 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
515 | }; |
516 | |
517 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
518 | .destroy = intel_encoder_destroy, |
519 | }; |
520 | |
521 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
522 | { |
523 | DRM_INFO("Skipping LVDS initialization for %s\n" , id->ident); |
524 | return 1; |
525 | } |
526 | |
527 | /* These systems claim to have LVDS, but really don't */ |
528 | static const struct dmi_system_id intel_no_lvds[] = { |
529 | { |
530 | .callback = intel_no_lvds_dmi_callback, |
531 | .ident = "Apple Mac Mini (Core series)" , |
532 | .matches = { |
533 | DMI_MATCH(DMI_SYS_VENDOR, "Apple" ), |
534 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1" ), |
535 | }, |
536 | }, |
537 | { |
538 | .callback = intel_no_lvds_dmi_callback, |
539 | .ident = "Apple Mac Mini (Core 2 series)" , |
540 | .matches = { |
541 | DMI_MATCH(DMI_SYS_VENDOR, "Apple" ), |
542 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1" ), |
543 | }, |
544 | }, |
545 | { |
546 | .callback = intel_no_lvds_dmi_callback, |
547 | .ident = "MSI IM-945GSE-A" , |
548 | .matches = { |
549 | DMI_MATCH(DMI_SYS_VENDOR, "MSI" ), |
550 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS" ), |
551 | }, |
552 | }, |
553 | { |
554 | .callback = intel_no_lvds_dmi_callback, |
555 | .ident = "Dell Studio Hybrid" , |
556 | .matches = { |
557 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc." ), |
558 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g" ), |
559 | }, |
560 | }, |
561 | { |
562 | .callback = intel_no_lvds_dmi_callback, |
563 | .ident = "Dell OptiPlex FX170" , |
564 | .matches = { |
565 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc." ), |
566 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170" ), |
567 | }, |
568 | }, |
569 | { |
570 | .callback = intel_no_lvds_dmi_callback, |
571 | .ident = "AOpen Mini PC" , |
572 | .matches = { |
573 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen" ), |
574 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF" ), |
575 | }, |
576 | }, |
577 | { |
578 | .callback = intel_no_lvds_dmi_callback, |
579 | .ident = "AOpen Mini PC MP915" , |
580 | .matches = { |
581 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen" ), |
582 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F" ), |
583 | }, |
584 | }, |
585 | { |
586 | .callback = intel_no_lvds_dmi_callback, |
587 | .ident = "AOpen i915GMm-HFS" , |
588 | .matches = { |
589 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen" ), |
590 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS" ), |
591 | }, |
592 | }, |
593 | { |
594 | .callback = intel_no_lvds_dmi_callback, |
595 | .ident = "AOpen i45GMx-I" , |
596 | .matches = { |
597 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen" ), |
598 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I" ), |
599 | }, |
600 | }, |
601 | { |
602 | .callback = intel_no_lvds_dmi_callback, |
603 | .ident = "Aopen i945GTt-VFA" , |
604 | .matches = { |
605 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW" ), |
606 | }, |
607 | }, |
608 | { |
609 | .callback = intel_no_lvds_dmi_callback, |
610 | .ident = "Clientron U800" , |
611 | .matches = { |
612 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron" ), |
613 | DMI_MATCH(DMI_PRODUCT_NAME, "U800" ), |
614 | }, |
615 | }, |
616 | { |
617 | .callback = intel_no_lvds_dmi_callback, |
618 | .ident = "Clientron E830" , |
619 | .matches = { |
620 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron" ), |
621 | DMI_MATCH(DMI_PRODUCT_NAME, "E830" ), |
622 | }, |
623 | }, |
624 | { |
625 | .callback = intel_no_lvds_dmi_callback, |
626 | .ident = "Asus EeeBox PC EB1007" , |
627 | .matches = { |
628 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC." ), |
629 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007" ), |
630 | }, |
631 | }, |
632 | { |
633 | .callback = intel_no_lvds_dmi_callback, |
634 | .ident = "Asus AT5NM10T-I" , |
635 | .matches = { |
636 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC." ), |
637 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I" ), |
638 | }, |
639 | }, |
640 | { |
641 | .callback = intel_no_lvds_dmi_callback, |
642 | .ident = "Hewlett-Packard HP t5740" , |
643 | .matches = { |
644 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard" ), |
645 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740" ), |
646 | }, |
647 | }, |
648 | { |
649 | .callback = intel_no_lvds_dmi_callback, |
650 | .ident = "Hewlett-Packard t5745" , |
651 | .matches = { |
652 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard" ), |
653 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745" ), |
654 | }, |
655 | }, |
656 | { |
657 | .callback = intel_no_lvds_dmi_callback, |
658 | .ident = "Hewlett-Packard st5747" , |
659 | .matches = { |
660 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard" ), |
661 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747" ), |
662 | }, |
663 | }, |
664 | { |
665 | .callback = intel_no_lvds_dmi_callback, |
666 | .ident = "MSI Wind Box DC500" , |
667 | .matches = { |
668 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD" ), |
669 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469" ), |
670 | }, |
671 | }, |
672 | { |
673 | .callback = intel_no_lvds_dmi_callback, |
674 | .ident = "Gigabyte GA-D525TUD" , |
675 | .matches = { |
676 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd." ), |
677 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD" ), |
678 | }, |
679 | }, |
680 | { |
681 | .callback = intel_no_lvds_dmi_callback, |
682 | .ident = "Supermicro X7SPA-H" , |
683 | .matches = { |
684 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro" ), |
685 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H" ), |
686 | }, |
687 | }, |
688 | { |
689 | .callback = intel_no_lvds_dmi_callback, |
690 | .ident = "Fujitsu Esprimo Q900" , |
691 | .matches = { |
692 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU" ), |
693 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900" ), |
694 | }, |
695 | }, |
696 | { |
697 | .callback = intel_no_lvds_dmi_callback, |
698 | .ident = "Intel D410PT" , |
699 | .matches = { |
700 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel" ), |
701 | DMI_MATCH(DMI_BOARD_NAME, "D410PT" ), |
702 | }, |
703 | }, |
704 | { |
705 | .callback = intel_no_lvds_dmi_callback, |
706 | .ident = "Intel D425KT" , |
707 | .matches = { |
708 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel" ), |
709 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT" ), |
710 | }, |
711 | }, |
712 | { |
713 | .callback = intel_no_lvds_dmi_callback, |
714 | .ident = "Intel D510MO" , |
715 | .matches = { |
716 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel" ), |
717 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO" ), |
718 | }, |
719 | }, |
720 | { |
721 | .callback = intel_no_lvds_dmi_callback, |
722 | .ident = "Intel D525MW" , |
723 | .matches = { |
724 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel" ), |
725 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW" ), |
726 | }, |
727 | }, |
728 | { |
729 | .callback = intel_no_lvds_dmi_callback, |
730 | .ident = "Radiant P845" , |
731 | .matches = { |
732 | DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc" ), |
733 | DMI_MATCH(DMI_PRODUCT_NAME, "P845" ), |
734 | }, |
735 | }, |
736 | |
737 | { } /* terminating entry */ |
738 | }; |
739 | |
740 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
741 | { |
742 | DRM_INFO("Forcing lvds to dual link mode on %s\n" , id->ident); |
743 | return 1; |
744 | } |
745 | |
746 | static const struct dmi_system_id intel_dual_link_lvds[] = { |
747 | { |
748 | .callback = intel_dual_link_lvds_callback, |
749 | .ident = "Apple MacBook Pro 15\" (2010)" , |
750 | .matches = { |
751 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc." ), |
752 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2" ), |
753 | }, |
754 | }, |
755 | { |
756 | .callback = intel_dual_link_lvds_callback, |
757 | .ident = "Apple MacBook Pro 15\" (2011)" , |
758 | .matches = { |
759 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc." ), |
760 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2" ), |
761 | }, |
762 | }, |
763 | { |
764 | .callback = intel_dual_link_lvds_callback, |
765 | .ident = "Apple MacBook Pro 15\" (2012)" , |
766 | .matches = { |
767 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc." ), |
768 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1" ), |
769 | }, |
770 | }, |
771 | { } /* terminating entry */ |
772 | }; |
773 | |
774 | struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915) |
775 | { |
776 | struct intel_encoder *encoder; |
777 | |
778 | for_each_intel_encoder(&i915->drm, encoder) { |
779 | if (encoder->type == INTEL_OUTPUT_LVDS) |
780 | return encoder; |
781 | } |
782 | |
783 | return NULL; |
784 | } |
785 | |
786 | bool intel_is_dual_link_lvds(struct drm_i915_private *i915) |
787 | { |
788 | struct intel_encoder *encoder = intel_get_lvds_encoder(i915); |
789 | |
790 | return encoder && to_lvds_encoder(encoder)->is_dual_link; |
791 | } |
792 | |
793 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
794 | { |
795 | struct drm_i915_private *i915 = to_i915(dev: lvds_encoder->base.base.dev); |
796 | struct intel_connector *connector = lvds_encoder->attached_connector; |
797 | const struct drm_display_mode *fixed_mode = |
798 | intel_panel_preferred_fixed_mode(connector); |
799 | unsigned int val; |
800 | |
801 | /* use the module option value if specified */ |
802 | if (i915->display.params.lvds_channel_mode > 0) |
803 | return i915->display.params.lvds_channel_mode == 2; |
804 | |
805 | /* single channel LVDS is limited to 112 MHz */ |
806 | if (fixed_mode->clock > 112999) |
807 | return true; |
808 | |
809 | if (dmi_check_system(list: intel_dual_link_lvds)) |
810 | return true; |
811 | |
812 | /* |
813 | * BIOS should set the proper LVDS register value at boot, but |
814 | * in reality, it doesn't set the value when the lid is closed; |
815 | * we need to check "the value to be set" in VBT when LVDS |
816 | * register is uninitialized. |
817 | */ |
818 | val = intel_de_read(i915, reg: lvds_encoder->reg); |
819 | if (HAS_PCH_CPT(i915)) |
820 | val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); |
821 | else |
822 | val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); |
823 | if (val == 0) |
824 | val = connector->panel.vbt.bios_lvds_val; |
825 | |
826 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
827 | } |
828 | |
829 | static void intel_lvds_add_properties(struct drm_connector *connector) |
830 | { |
831 | intel_attach_scaling_mode_property(connector); |
832 | } |
833 | |
834 | /** |
835 | * intel_lvds_init - setup LVDS connectors on this device |
836 | * @i915: i915 device |
837 | * |
838 | * Create the connector, register the LVDS DDC bus, and try to figure out what |
839 | * modes we can display on the LVDS panel (if present). |
840 | */ |
841 | void intel_lvds_init(struct drm_i915_private *i915) |
842 | { |
843 | struct intel_lvds_encoder *lvds_encoder; |
844 | struct intel_connector *connector; |
845 | const struct drm_edid *drm_edid; |
846 | struct intel_encoder *encoder; |
847 | i915_reg_t lvds_reg; |
848 | u32 lvds; |
849 | u8 ddc_pin; |
850 | |
851 | /* Skip init on machines we know falsely report LVDS */ |
852 | if (dmi_check_system(list: intel_no_lvds)) { |
853 | drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, |
854 | "Useless DMI match. Internal LVDS support disabled by VBT\n" ); |
855 | return; |
856 | } |
857 | |
858 | if (!i915->display.vbt.int_lvds_support) { |
859 | drm_dbg_kms(&i915->drm, |
860 | "Internal LVDS support disabled by VBT\n" ); |
861 | return; |
862 | } |
863 | |
864 | if (HAS_PCH_SPLIT(i915)) |
865 | lvds_reg = PCH_LVDS; |
866 | else |
867 | lvds_reg = LVDS; |
868 | |
869 | lvds = intel_de_read(i915, reg: lvds_reg); |
870 | |
871 | if (HAS_PCH_SPLIT(i915)) { |
872 | if ((lvds & LVDS_DETECTED) == 0) |
873 | return; |
874 | } |
875 | |
876 | ddc_pin = GMBUS_PIN_PANEL; |
877 | if (!intel_bios_is_lvds_present(dev_priv: i915, i2c_pin: &ddc_pin)) { |
878 | if ((lvds & LVDS_PORT_EN) == 0) { |
879 | drm_dbg_kms(&i915->drm, |
880 | "LVDS is not present in VBT\n" ); |
881 | return; |
882 | } |
883 | drm_dbg_kms(&i915->drm, |
884 | "LVDS is not present in VBT, but enabled anyway\n" ); |
885 | } |
886 | |
887 | lvds_encoder = kzalloc(size: sizeof(*lvds_encoder), GFP_KERNEL); |
888 | if (!lvds_encoder) |
889 | return; |
890 | |
891 | connector = intel_connector_alloc(); |
892 | if (!connector) { |
893 | kfree(objp: lvds_encoder); |
894 | return; |
895 | } |
896 | |
897 | lvds_encoder->attached_connector = connector; |
898 | encoder = &lvds_encoder->base; |
899 | |
900 | drm_connector_init_with_ddc(dev: &i915->drm, connector: &connector->base, |
901 | funcs: &intel_lvds_connector_funcs, |
902 | DRM_MODE_CONNECTOR_LVDS, |
903 | ddc: intel_gmbus_get_adapter(dev_priv: i915, pin: ddc_pin)); |
904 | |
905 | drm_encoder_init(dev: &i915->drm, encoder: &encoder->base, funcs: &intel_lvds_enc_funcs, |
906 | DRM_MODE_ENCODER_LVDS, name: "LVDS" ); |
907 | |
908 | encoder->enable = intel_enable_lvds; |
909 | encoder->pre_enable = intel_pre_enable_lvds; |
910 | encoder->compute_config = intel_lvds_compute_config; |
911 | if (HAS_PCH_SPLIT(i915)) { |
912 | encoder->disable = pch_disable_lvds; |
913 | encoder->post_disable = pch_post_disable_lvds; |
914 | } else { |
915 | encoder->disable = gmch_disable_lvds; |
916 | } |
917 | encoder->get_hw_state = intel_lvds_get_hw_state; |
918 | encoder->get_config = intel_lvds_get_config; |
919 | encoder->update_pipe = intel_backlight_update; |
920 | encoder->shutdown = intel_lvds_shutdown; |
921 | connector->get_hw_state = intel_connector_get_hw_state; |
922 | |
923 | intel_connector_attach_encoder(connector, encoder); |
924 | |
925 | encoder->type = INTEL_OUTPUT_LVDS; |
926 | encoder->power_domain = POWER_DOMAIN_PORT_OTHER; |
927 | encoder->port = PORT_NONE; |
928 | encoder->cloneable = 0; |
929 | if (DISPLAY_VER(i915) < 4) |
930 | encoder->pipe_mask = BIT(PIPE_B); |
931 | else |
932 | encoder->pipe_mask = ~0; |
933 | |
934 | drm_connector_helper_add(connector: &connector->base, funcs: &intel_lvds_connector_helper_funcs); |
935 | connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; |
936 | |
937 | lvds_encoder->reg = lvds_reg; |
938 | |
939 | intel_lvds_add_properties(connector: &connector->base); |
940 | |
941 | intel_lvds_pps_get_hw_state(dev_priv: i915, pps: &lvds_encoder->init_pps); |
942 | lvds_encoder->init_lvds_val = lvds; |
943 | |
944 | /* |
945 | * LVDS discovery: |
946 | * 1) check for EDID on DDC |
947 | * 2) check for VBT data |
948 | * 3) check to see if LVDS is already on |
949 | * if none of the above, no panel |
950 | */ |
951 | |
952 | /* |
953 | * Attempt to get the fixed panel mode from DDC. Assume that the |
954 | * preferred mode is the right one. |
955 | */ |
956 | mutex_lock(&i915->drm.mode_config.mutex); |
957 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) |
958 | drm_edid = drm_edid_read_switcheroo(connector: &connector->base, adapter: connector->base.ddc); |
959 | else |
960 | drm_edid = drm_edid_read_ddc(connector: &connector->base, adapter: connector->base.ddc); |
961 | if (drm_edid) { |
962 | if (drm_edid_connector_update(connector: &connector->base, edid: drm_edid) || |
963 | !drm_edid_connector_add_modes(connector: &connector->base)) { |
964 | drm_edid_connector_update(connector: &connector->base, NULL); |
965 | drm_edid_free(drm_edid); |
966 | drm_edid = ERR_PTR(error: -EINVAL); |
967 | } |
968 | } else { |
969 | drm_edid = ERR_PTR(error: -ENOENT); |
970 | } |
971 | intel_bios_init_panel_late(dev_priv: i915, panel: &connector->panel, NULL, |
972 | drm_edid: IS_ERR(ptr: drm_edid) ? NULL : drm_edid); |
973 | |
974 | /* Try EDID first */ |
975 | intel_panel_add_edid_fixed_modes(connector, use_alt_fixed_modes: true); |
976 | |
977 | /* Failed to get EDID, what about VBT? */ |
978 | if (!intel_panel_preferred_fixed_mode(connector)) |
979 | intel_panel_add_vbt_lfp_fixed_mode(connector); |
980 | |
981 | /* |
982 | * If we didn't get a fixed mode from EDID or VBT, try checking |
983 | * if the panel is already turned on. If so, assume that |
984 | * whatever is currently programmed is the correct mode. |
985 | */ |
986 | if (!intel_panel_preferred_fixed_mode(connector)) |
987 | intel_panel_add_encoder_fixed_mode(connector, encoder); |
988 | |
989 | mutex_unlock(lock: &i915->drm.mode_config.mutex); |
990 | |
991 | /* If we still don't have a mode after all that, give up. */ |
992 | if (!intel_panel_preferred_fixed_mode(connector)) |
993 | goto failed; |
994 | |
995 | intel_panel_init(connector, fixed_edid: drm_edid); |
996 | |
997 | intel_backlight_setup(connector, pipe: INVALID_PIPE); |
998 | |
999 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
1000 | drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n" , |
1001 | lvds_encoder->is_dual_link ? "dual" : "single" ); |
1002 | |
1003 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
1004 | |
1005 | return; |
1006 | |
1007 | failed: |
1008 | drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n" ); |
1009 | drm_connector_cleanup(connector: &connector->base); |
1010 | drm_encoder_cleanup(encoder: &encoder->base); |
1011 | kfree(objp: lvds_encoder); |
1012 | intel_connector_free(connector); |
1013 | return; |
1014 | } |
1015 | |