1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI ADC MFD driver
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <linux/kernel.h>
9#include <linux/err.h>
10#include <linux/module.h>
11#include <linux/slab.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/iio/iio.h>
16#include <linux/of.h>
17#include <linux/iio/machine.h>
18#include <linux/iio/driver.h>
19#include <linux/iopoll.h>
20
21#include <linux/mfd/ti_am335x_tscadc.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/kfifo_buf.h>
24
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27
28#define DMA_BUFFER_SIZE SZ_2K
29
30struct tiadc_dma {
31 struct dma_slave_config conf;
32 struct dma_chan *chan;
33 dma_addr_t addr;
34 dma_cookie_t cookie;
35 u8 *buf;
36 int current_period;
37 int period_size;
38 u8 fifo_thresh;
39};
40
41struct tiadc_device {
42 struct ti_tscadc_dev *mfd_tscadc;
43 struct tiadc_dma dma;
44 struct mutex fifo1_lock; /* to protect fifo access */
45 int channels;
46 int total_ch_enabled;
47 u8 channel_line[8];
48 u8 channel_step[8];
49 int buffer_en_ch_steps;
50 u16 data[8];
51 u32 open_delay[8], sample_delay[8], step_avg[8];
52};
53
54static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
55{
56 return readl(addr: adc->mfd_tscadc->tscadc_base + reg);
57}
58
59static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
60 unsigned int val)
61{
62 writel(val, addr: adc->mfd_tscadc->tscadc_base + reg);
63}
64
65static u32 get_adc_step_mask(struct tiadc_device *adc_dev)
66{
67 u32 step_en;
68
69 step_en = ((1 << adc_dev->channels) - 1);
70 step_en <<= TOTAL_STEPS - adc_dev->channels + 1;
71 return step_en;
72}
73
74static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev,
75 struct iio_chan_spec const *chan)
76{
77 int i;
78
79 for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) {
80 if (chan->channel == adc_dev->channel_line[i]) {
81 u32 step;
82
83 step = adc_dev->channel_step[i];
84 /* +1 for the charger */
85 return 1 << (step + 1);
86 }
87 }
88 WARN_ON(1);
89 return 0;
90}
91
92static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan)
93{
94 return 1 << adc_dev->channel_step[chan];
95}
96
97static int tiadc_wait_idle(struct tiadc_device *adc_dev)
98{
99 u32 val;
100
101 return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM,
102 val, !(val & SEQ_STATUS), 10,
103 IDLE_TIMEOUT_MS * 1000 * adc_dev->channels);
104}
105
106static void tiadc_step_config(struct iio_dev *indio_dev)
107{
108 struct tiadc_device *adc_dev = iio_priv(indio_dev);
109 unsigned int stepconfig;
110 int i, steps = 0;
111
112 /*
113 * There are 16 configurable steps and 8 analog input
114 * lines available which are shared between Touchscreen and ADC.
115 *
116 * Steps forwards i.e. from 0 towards 16 are used by ADC
117 * depending on number of input lines needed.
118 * Channel would represent which analog input
119 * needs to be given to ADC to digitalize data.
120 */
121 for (i = 0; i < adc_dev->channels; i++) {
122 int chan;
123
124 chan = adc_dev->channel_line[i];
125
126 if (adc_dev->step_avg[i])
127 stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) |
128 STEPCONFIG_FIFO1;
129 else
130 stepconfig = STEPCONFIG_FIFO1;
131
132 if (iio_buffer_enabled(indio_dev))
133 stepconfig |= STEPCONFIG_MODE_SWCNT;
134
135 tiadc_writel(adc: adc_dev, REG_STEPCONFIG(steps),
136 val: stepconfig | STEPCONFIG_INP(chan) |
137 STEPCONFIG_INM_ADCREFM | STEPCONFIG_RFP_VREFP |
138 STEPCONFIG_RFM_VREFN);
139
140 tiadc_writel(adc: adc_dev, REG_STEPDELAY(steps),
141 STEPDELAY_OPEN(adc_dev->open_delay[i]) |
142 STEPDELAY_SAMPLE(adc_dev->sample_delay[i]));
143
144 adc_dev->channel_step[i] = steps;
145 steps++;
146 }
147}
148
149static irqreturn_t tiadc_irq_h(int irq, void *private)
150{
151 struct iio_dev *indio_dev = private;
152 struct tiadc_device *adc_dev = iio_priv(indio_dev);
153 unsigned int status, config, adc_fsm;
154 unsigned short count = 0;
155
156 status = tiadc_readl(adc: adc_dev, REG_IRQSTATUS);
157
158 /*
159 * ADC and touchscreen share the IRQ line.
160 * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only
161 */
162 if (status & IRQENB_FIFO1OVRRUN) {
163 /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */
164 config = tiadc_readl(adc: adc_dev, REG_CTRL);
165 config &= ~(CNTRLREG_SSENB);
166 tiadc_writel(adc: adc_dev, REG_CTRL, val: config);
167 tiadc_writel(adc: adc_dev, REG_IRQSTATUS,
168 IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW |
169 IRQENB_FIFO1THRES);
170
171 /*
172 * Wait for the idle state.
173 * ADC needs to finish the current conversion
174 * before disabling the module
175 */
176 do {
177 adc_fsm = tiadc_readl(adc: adc_dev, REG_ADCFSM);
178 } while (adc_fsm != 0x10 && count++ < 100);
179
180 tiadc_writel(adc: adc_dev, REG_CTRL, val: (config | CNTRLREG_SSENB));
181 return IRQ_HANDLED;
182 } else if (status & IRQENB_FIFO1THRES) {
183 /* Disable irq and wake worker thread */
184 tiadc_writel(adc: adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES);
185 return IRQ_WAKE_THREAD;
186 }
187
188 return IRQ_NONE;
189}
190
191static irqreturn_t tiadc_worker_h(int irq, void *private)
192{
193 struct iio_dev *indio_dev = private;
194 struct tiadc_device *adc_dev = iio_priv(indio_dev);
195 int i, k, fifo1count, read;
196 u16 *data = adc_dev->data;
197
198 fifo1count = tiadc_readl(adc: adc_dev, REG_FIFO1CNT);
199 for (k = 0; k < fifo1count; k = k + i) {
200 for (i = 0; i < indio_dev->scan_bytes / 2; i++) {
201 read = tiadc_readl(adc: adc_dev, REG_FIFO1);
202 data[i] = read & FIFOREAD_DATA_MASK;
203 }
204 iio_push_to_buffers(indio_dev, data: (u8 *)data);
205 }
206
207 tiadc_writel(adc: adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES);
208 tiadc_writel(adc: adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
209
210 return IRQ_HANDLED;
211}
212
213static void tiadc_dma_rx_complete(void *param)
214{
215 struct iio_dev *indio_dev = param;
216 struct tiadc_device *adc_dev = iio_priv(indio_dev);
217 struct tiadc_dma *dma = &adc_dev->dma;
218 u8 *data;
219 int i;
220
221 data = dma->buf + dma->current_period * dma->period_size;
222 dma->current_period = 1 - dma->current_period; /* swap the buffer ID */
223
224 for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) {
225 iio_push_to_buffers(indio_dev, data);
226 data += indio_dev->scan_bytes;
227 }
228}
229
230static int tiadc_start_dma(struct iio_dev *indio_dev)
231{
232 struct tiadc_device *adc_dev = iio_priv(indio_dev);
233 struct tiadc_dma *dma = &adc_dev->dma;
234 struct dma_async_tx_descriptor *desc;
235
236 dma->current_period = 0; /* We start to fill period 0 */
237
238 /*
239 * Make the fifo thresh as the multiple of total number of
240 * channels enabled, so make sure that cyclic DMA period
241 * length is also a multiple of total number of channels
242 * enabled. This ensures that no invalid data is reported
243 * to the stack via iio_push_to_buffers().
244 */
245 dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1,
246 adc_dev->total_ch_enabled) - 1;
247
248 /* Make sure that period length is multiple of fifo thresh level */
249 dma->period_size = rounddown(DMA_BUFFER_SIZE / 2,
250 (dma->fifo_thresh + 1) * sizeof(u16));
251
252 dma->conf.src_maxburst = dma->fifo_thresh + 1;
253 dmaengine_slave_config(chan: dma->chan, config: &dma->conf);
254
255 desc = dmaengine_prep_dma_cyclic(chan: dma->chan, buf_addr: dma->addr,
256 buf_len: dma->period_size * 2,
257 period_len: dma->period_size, dir: DMA_DEV_TO_MEM,
258 flags: DMA_PREP_INTERRUPT);
259 if (!desc)
260 return -EBUSY;
261
262 desc->callback = tiadc_dma_rx_complete;
263 desc->callback_param = indio_dev;
264
265 dma->cookie = dmaengine_submit(desc);
266
267 dma_async_issue_pending(chan: dma->chan);
268
269 tiadc_writel(adc: adc_dev, REG_FIFO1THR, val: dma->fifo_thresh);
270 tiadc_writel(adc: adc_dev, REG_DMA1REQ, val: dma->fifo_thresh);
271 tiadc_writel(adc: adc_dev, REG_DMAENABLE_SET, DMA_FIFO1);
272
273 return 0;
274}
275
276static int tiadc_buffer_preenable(struct iio_dev *indio_dev)
277{
278 struct tiadc_device *adc_dev = iio_priv(indio_dev);
279 int i, fifo1count;
280 int ret;
281
282 ret = tiadc_wait_idle(adc_dev);
283 if (ret)
284 return ret;
285
286 tiadc_writel(adc: adc_dev, REG_IRQCLR,
287 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
288 IRQENB_FIFO1UNDRFLW);
289
290 /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */
291 fifo1count = tiadc_readl(adc: adc_dev, REG_FIFO1CNT);
292 for (i = 0; i < fifo1count; i++)
293 tiadc_readl(adc: adc_dev, REG_FIFO1);
294
295 return 0;
296}
297
298static int tiadc_buffer_postenable(struct iio_dev *indio_dev)
299{
300 struct tiadc_device *adc_dev = iio_priv(indio_dev);
301 struct tiadc_dma *dma = &adc_dev->dma;
302 unsigned int irq_enable;
303 unsigned int enb = 0;
304 u8 bit;
305
306 tiadc_step_config(indio_dev);
307 for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) {
308 enb |= (get_adc_step_bit(adc_dev, chan: bit) << 1);
309 adc_dev->total_ch_enabled++;
310 }
311 adc_dev->buffer_en_ch_steps = enb;
312
313 if (dma->chan)
314 tiadc_start_dma(indio_dev);
315
316 am335x_tsc_se_set_cache(tsadc: adc_dev->mfd_tscadc, val: enb);
317
318 tiadc_writel(adc: adc_dev, REG_IRQSTATUS,
319 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
320 IRQENB_FIFO1UNDRFLW);
321
322 irq_enable = IRQENB_FIFO1OVRRUN;
323 if (!dma->chan)
324 irq_enable |= IRQENB_FIFO1THRES;
325 tiadc_writel(adc: adc_dev, REG_IRQENABLE, val: irq_enable);
326
327 return 0;
328}
329
330static int tiadc_buffer_predisable(struct iio_dev *indio_dev)
331{
332 struct tiadc_device *adc_dev = iio_priv(indio_dev);
333 struct tiadc_dma *dma = &adc_dev->dma;
334 int fifo1count, i;
335
336 tiadc_writel(adc: adc_dev, REG_IRQCLR,
337 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN |
338 IRQENB_FIFO1UNDRFLW);
339 am335x_tsc_se_clr(tsadc: adc_dev->mfd_tscadc, val: adc_dev->buffer_en_ch_steps);
340 adc_dev->buffer_en_ch_steps = 0;
341 adc_dev->total_ch_enabled = 0;
342 if (dma->chan) {
343 tiadc_writel(adc: adc_dev, REG_DMAENABLE_CLEAR, val: 0x2);
344 dmaengine_terminate_async(chan: dma->chan);
345 }
346
347 /* Flush FIFO of leftover data in the time it takes to disable adc */
348 fifo1count = tiadc_readl(adc: adc_dev, REG_FIFO1CNT);
349 for (i = 0; i < fifo1count; i++)
350 tiadc_readl(adc: adc_dev, REG_FIFO1);
351
352 return 0;
353}
354
355static int tiadc_buffer_postdisable(struct iio_dev *indio_dev)
356{
357 tiadc_step_config(indio_dev);
358
359 return 0;
360}
361
362static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = {
363 .preenable = &tiadc_buffer_preenable,
364 .postenable = &tiadc_buffer_postenable,
365 .predisable = &tiadc_buffer_predisable,
366 .postdisable = &tiadc_buffer_postdisable,
367};
368
369static int tiadc_iio_buffered_hardware_setup(struct device *dev,
370 struct iio_dev *indio_dev,
371 irqreturn_t (*pollfunc_bh)(int irq, void *p),
372 irqreturn_t (*pollfunc_th)(int irq, void *p),
373 int irq, unsigned long flags,
374 const struct iio_buffer_setup_ops *setup_ops)
375{
376 int ret;
377
378 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, setup_ops);
379 if (ret)
380 return ret;
381
382 return devm_request_threaded_irq(dev, irq, handler: pollfunc_th, thread_fn: pollfunc_bh,
383 irqflags: flags, devname: indio_dev->name, dev_id: indio_dev);
384}
385
386static const char * const chan_name_ain[] = {
387 "AIN0",
388 "AIN1",
389 "AIN2",
390 "AIN3",
391 "AIN4",
392 "AIN5",
393 "AIN6",
394 "AIN7",
395};
396
397static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev,
398 int channels)
399{
400 struct tiadc_device *adc_dev = iio_priv(indio_dev);
401 struct iio_chan_spec *chan_array;
402 struct iio_chan_spec *chan;
403 int i;
404
405 indio_dev->num_channels = channels;
406 chan_array = devm_kcalloc(dev, n: channels, size: sizeof(*chan_array),
407 GFP_KERNEL);
408 if (!chan_array)
409 return -ENOMEM;
410
411 chan = chan_array;
412 for (i = 0; i < channels; i++, chan++) {
413 chan->type = IIO_VOLTAGE;
414 chan->indexed = 1;
415 chan->channel = adc_dev->channel_line[i];
416 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
417 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
418 chan->datasheet_name = chan_name_ain[chan->channel];
419 chan->scan_index = i;
420 chan->scan_type.sign = 'u';
421 chan->scan_type.realbits = 12;
422 chan->scan_type.storagebits = 16;
423 }
424
425 indio_dev->channels = chan_array;
426
427 return 0;
428}
429
430static int tiadc_read_raw(struct iio_dev *indio_dev,
431 struct iio_chan_spec const *chan, int *val, int *val2,
432 long mask)
433{
434 struct tiadc_device *adc_dev = iio_priv(indio_dev);
435 int i, map_val;
436 unsigned int fifo1count, read, stepid;
437 bool found = false;
438 u32 step_en;
439 unsigned long timeout;
440 int ret;
441
442 switch (mask) {
443 case IIO_CHAN_INFO_RAW:
444 break;
445 case IIO_CHAN_INFO_SCALE:
446 switch (chan->type) {
447 case IIO_VOLTAGE:
448 *val = 1800;
449 *val2 = chan->scan_type.realbits;
450 return IIO_VAL_FRACTIONAL_LOG2;
451 default:
452 return -EINVAL;
453 }
454 break;
455 default:
456 return -EINVAL;
457 }
458
459 if (iio_buffer_enabled(indio_dev))
460 return -EBUSY;
461
462 step_en = get_adc_chan_step_mask(adc_dev, chan);
463 if (!step_en)
464 return -EINVAL;
465
466 mutex_lock(&adc_dev->fifo1_lock);
467
468 ret = tiadc_wait_idle(adc_dev);
469 if (ret)
470 goto err_unlock;
471
472 fifo1count = tiadc_readl(adc: adc_dev, REG_FIFO1CNT);
473 while (fifo1count--)
474 tiadc_readl(adc: adc_dev, REG_FIFO1);
475
476 am335x_tsc_se_set_once(tsadc: adc_dev->mfd_tscadc, val: step_en);
477
478 /* Wait for Fifo threshold interrupt */
479 timeout = jiffies + msecs_to_jiffies(IDLE_TIMEOUT_MS * adc_dev->channels);
480 while (1) {
481 fifo1count = tiadc_readl(adc: adc_dev, REG_FIFO1CNT);
482 if (fifo1count)
483 break;
484
485 if (time_after(jiffies, timeout)) {
486 am335x_tsc_se_adc_done(tsadc: adc_dev->mfd_tscadc);
487 ret = -EAGAIN;
488 goto err_unlock;
489 }
490 }
491
492 map_val = adc_dev->channel_step[chan->scan_index];
493
494 /*
495 * We check the complete FIFO. We programmed just one entry but in case
496 * something went wrong we left empty handed (-EAGAIN previously) and
497 * then the value appeared somehow in the FIFO we would have two entries.
498 * Therefore we read every item and keep only the latest version of the
499 * requested channel.
500 */
501 for (i = 0; i < fifo1count; i++) {
502 read = tiadc_readl(adc: adc_dev, REG_FIFO1);
503 stepid = read & FIFOREAD_CHNLID_MASK;
504 stepid = stepid >> 0x10;
505
506 if (stepid == map_val) {
507 read = read & FIFOREAD_DATA_MASK;
508 found = true;
509 *val = (u16)read;
510 }
511 }
512
513 am335x_tsc_se_adc_done(tsadc: adc_dev->mfd_tscadc);
514
515 if (!found)
516 ret = -EBUSY;
517
518err_unlock:
519 mutex_unlock(lock: &adc_dev->fifo1_lock);
520 return ret ? ret : IIO_VAL_INT;
521}
522
523static const struct iio_info tiadc_info = {
524 .read_raw = &tiadc_read_raw,
525};
526
527static int tiadc_request_dma(struct platform_device *pdev,
528 struct tiadc_device *adc_dev)
529{
530 struct tiadc_dma *dma = &adc_dev->dma;
531 dma_cap_mask_t mask;
532
533 /* Default slave configuration parameters */
534 dma->conf.direction = DMA_DEV_TO_MEM;
535 dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
536 dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1;
537
538 dma_cap_zero(mask);
539 dma_cap_set(DMA_CYCLIC, mask);
540
541 /* Get a channel for RX */
542 dma->chan = dma_request_chan(dev: adc_dev->mfd_tscadc->dev, name: "fifo1");
543 if (IS_ERR(ptr: dma->chan)) {
544 int ret = PTR_ERR(ptr: dma->chan);
545
546 dma->chan = NULL;
547 return ret;
548 }
549
550 /* RX buffer */
551 dma->buf = dma_alloc_coherent(dev: dma->chan->device->dev, DMA_BUFFER_SIZE,
552 dma_handle: &dma->addr, GFP_KERNEL);
553 if (!dma->buf)
554 goto err;
555
556 return 0;
557
558err:
559 dma_release_channel(chan: dma->chan);
560 return -ENOMEM;
561}
562
563static int tiadc_parse_dt(struct platform_device *pdev,
564 struct tiadc_device *adc_dev)
565{
566 struct device_node *node = pdev->dev.of_node;
567 int channels = 0;
568 u32 val;
569 int i;
570
571 of_property_for_each_u32(node, "ti,adc-channels", val) {
572 adc_dev->channel_line[channels] = val;
573
574 /* Set Default values for optional DT parameters */
575 adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY;
576 adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY;
577 adc_dev->step_avg[channels] = 16;
578
579 channels++;
580 }
581
582 adc_dev->channels = channels;
583
584 of_property_read_u32_array(np: node, propname: "ti,chan-step-avg",
585 out_values: adc_dev->step_avg, sz: channels);
586 of_property_read_u32_array(np: node, propname: "ti,chan-step-opendelay",
587 out_values: adc_dev->open_delay, sz: channels);
588 of_property_read_u32_array(np: node, propname: "ti,chan-step-sampledelay",
589 out_values: adc_dev->sample_delay, sz: channels);
590
591 for (i = 0; i < adc_dev->channels; i++) {
592 int chan;
593
594 chan = adc_dev->channel_line[i];
595
596 if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) {
597 dev_warn(&pdev->dev,
598 "chan %d: wrong step avg, truncated to %ld\n",
599 chan, STEPCONFIG_AVG_16);
600 adc_dev->step_avg[i] = STEPCONFIG_AVG_16;
601 }
602
603 if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) {
604 dev_warn(&pdev->dev,
605 "chan %d: wrong open delay, truncated to 0x%lX\n",
606 chan, STEPCONFIG_MAX_OPENDLY);
607 adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY;
608 }
609
610 if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) {
611 dev_warn(&pdev->dev,
612 "chan %d: wrong sample delay, truncated to 0x%lX\n",
613 chan, STEPCONFIG_MAX_SAMPLE);
614 adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE;
615 }
616 }
617
618 return 0;
619}
620
621static int tiadc_probe(struct platform_device *pdev)
622{
623 struct iio_dev *indio_dev;
624 struct tiadc_device *adc_dev;
625 struct device_node *node = pdev->dev.of_node;
626 int err;
627
628 if (!node) {
629 dev_err(&pdev->dev, "Could not find valid DT data.\n");
630 return -EINVAL;
631 }
632
633 indio_dev = devm_iio_device_alloc(parent: &pdev->dev, sizeof_priv: sizeof(*adc_dev));
634 if (!indio_dev) {
635 dev_err(&pdev->dev, "failed to allocate iio device\n");
636 return -ENOMEM;
637 }
638 adc_dev = iio_priv(indio_dev);
639
640 adc_dev->mfd_tscadc = ti_tscadc_dev_get(p: pdev);
641 tiadc_parse_dt(pdev, adc_dev);
642
643 indio_dev->name = dev_name(dev: &pdev->dev);
644 indio_dev->modes = INDIO_DIRECT_MODE;
645 indio_dev->info = &tiadc_info;
646
647 tiadc_step_config(indio_dev);
648 tiadc_writel(adc: adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD);
649 mutex_init(&adc_dev->fifo1_lock);
650
651 err = tiadc_channel_init(dev: &pdev->dev, indio_dev, channels: adc_dev->channels);
652 if (err < 0)
653 return err;
654
655 err = tiadc_iio_buffered_hardware_setup(dev: &pdev->dev, indio_dev,
656 pollfunc_bh: &tiadc_worker_h,
657 pollfunc_th: &tiadc_irq_h,
658 irq: adc_dev->mfd_tscadc->irq,
659 IRQF_SHARED,
660 setup_ops: &tiadc_buffer_setup_ops);
661 if (err)
662 return err;
663
664 err = iio_device_register(indio_dev);
665 if (err)
666 return err;
667
668 platform_set_drvdata(pdev, data: indio_dev);
669
670 err = tiadc_request_dma(pdev, adc_dev);
671 if (err && err != -ENODEV) {
672 dev_err_probe(dev: &pdev->dev, err, fmt: "DMA request failed\n");
673 goto err_dma;
674 }
675
676 return 0;
677
678err_dma:
679 iio_device_unregister(indio_dev);
680
681 return err;
682}
683
684static void tiadc_remove(struct platform_device *pdev)
685{
686 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
687 struct tiadc_device *adc_dev = iio_priv(indio_dev);
688 struct tiadc_dma *dma = &adc_dev->dma;
689 u32 step_en;
690
691 if (dma->chan) {
692 dma_free_coherent(dev: dma->chan->device->dev, DMA_BUFFER_SIZE,
693 cpu_addr: dma->buf, dma_handle: dma->addr);
694 dma_release_channel(chan: dma->chan);
695 }
696 iio_device_unregister(indio_dev);
697
698 step_en = get_adc_step_mask(adc_dev);
699 am335x_tsc_se_clr(tsadc: adc_dev->mfd_tscadc, val: step_en);
700}
701
702static int tiadc_suspend(struct device *dev)
703{
704 struct iio_dev *indio_dev = dev_get_drvdata(dev);
705 struct tiadc_device *adc_dev = iio_priv(indio_dev);
706 unsigned int idle;
707
708 idle = tiadc_readl(adc: adc_dev, REG_CTRL);
709 idle &= ~(CNTRLREG_SSENB);
710 tiadc_writel(adc: adc_dev, REG_CTRL, val: idle | CNTRLREG_POWERDOWN);
711
712 return 0;
713}
714
715static int tiadc_resume(struct device *dev)
716{
717 struct iio_dev *indio_dev = dev_get_drvdata(dev);
718 struct tiadc_device *adc_dev = iio_priv(indio_dev);
719 unsigned int restore;
720
721 /* Make sure ADC is powered up */
722 restore = tiadc_readl(adc: adc_dev, REG_CTRL);
723 restore &= ~CNTRLREG_POWERDOWN;
724 tiadc_writel(adc: adc_dev, REG_CTRL, val: restore);
725
726 tiadc_step_config(indio_dev);
727 am335x_tsc_se_set_cache(tsadc: adc_dev->mfd_tscadc,
728 val: adc_dev->buffer_en_ch_steps);
729 return 0;
730}
731
732static DEFINE_SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume);
733
734static const struct of_device_id ti_adc_dt_ids[] = {
735 { .compatible = "ti,am3359-adc", },
736 { .compatible = "ti,am4372-adc", },
737 { }
738};
739MODULE_DEVICE_TABLE(of, ti_adc_dt_ids);
740
741static struct platform_driver tiadc_driver = {
742 .driver = {
743 .name = "TI-am335x-adc",
744 .pm = pm_sleep_ptr(&tiadc_pm_ops),
745 .of_match_table = ti_adc_dt_ids,
746 },
747 .probe = tiadc_probe,
748 .remove = tiadc_remove,
749};
750module_platform_driver(tiadc_driver);
751
752MODULE_DESCRIPTION("TI ADC controller driver");
753MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
754MODULE_LICENSE("GPL");
755

source code of linux/drivers/iio/adc/ti_am335x_adc.c