1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8#include <linux/delay.h>
9#include <linux/dsa/ksz_common.h>
10#include <linux/export.h>
11#include <linux/gpio/consumer.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <linux/if_vlan.h>
19#include <linux/if_hsr.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_mdio.h>
24#include <linux/of_net.h>
25#include <linux/micrel_phy.h>
26#include <net/dsa.h>
27#include <net/pkt_cls.h>
28#include <net/switchdev.h>
29
30#include "ksz_common.h"
31#include "ksz_ptp.h"
32#include "ksz8.h"
33#include "ksz9477.h"
34#include "lan937x.h"
35
36#define MIB_COUNTER_NUM 0x20
37
38struct ksz_stats_raw {
39 u64 rx_hi;
40 u64 rx_undersize;
41 u64 rx_fragments;
42 u64 rx_oversize;
43 u64 rx_jabbers;
44 u64 rx_symbol_err;
45 u64 rx_crc_err;
46 u64 rx_align_err;
47 u64 rx_mac_ctrl;
48 u64 rx_pause;
49 u64 rx_bcast;
50 u64 rx_mcast;
51 u64 rx_ucast;
52 u64 rx_64_or_less;
53 u64 rx_65_127;
54 u64 rx_128_255;
55 u64 rx_256_511;
56 u64 rx_512_1023;
57 u64 rx_1024_1522;
58 u64 rx_1523_2000;
59 u64 rx_2001;
60 u64 tx_hi;
61 u64 tx_late_col;
62 u64 tx_pause;
63 u64 tx_bcast;
64 u64 tx_mcast;
65 u64 tx_ucast;
66 u64 tx_deferred;
67 u64 tx_total_col;
68 u64 tx_exc_col;
69 u64 tx_single_col;
70 u64 tx_mult_col;
71 u64 rx_total;
72 u64 tx_total;
73 u64 rx_discards;
74 u64 tx_discards;
75};
76
77struct ksz88xx_stats_raw {
78 u64 rx;
79 u64 rx_hi;
80 u64 rx_undersize;
81 u64 rx_fragments;
82 u64 rx_oversize;
83 u64 rx_jabbers;
84 u64 rx_symbol_err;
85 u64 rx_crc_err;
86 u64 rx_align_err;
87 u64 rx_mac_ctrl;
88 u64 rx_pause;
89 u64 rx_bcast;
90 u64 rx_mcast;
91 u64 rx_ucast;
92 u64 rx_64_or_less;
93 u64 rx_65_127;
94 u64 rx_128_255;
95 u64 rx_256_511;
96 u64 rx_512_1023;
97 u64 rx_1024_1522;
98 u64 tx;
99 u64 tx_hi;
100 u64 tx_late_col;
101 u64 tx_pause;
102 u64 tx_bcast;
103 u64 tx_mcast;
104 u64 tx_ucast;
105 u64 tx_deferred;
106 u64 tx_total_col;
107 u64 tx_exc_col;
108 u64 tx_single_col;
109 u64 tx_mult_col;
110 u64 rx_discards;
111 u64 tx_discards;
112};
113
114static const struct ksz_mib_names ksz88xx_mib_names[] = {
115 { 0x00, "rx" },
116 { 0x01, "rx_hi" },
117 { 0x02, "rx_undersize" },
118 { 0x03, "rx_fragments" },
119 { 0x04, "rx_oversize" },
120 { 0x05, "rx_jabbers" },
121 { 0x06, "rx_symbol_err" },
122 { 0x07, "rx_crc_err" },
123 { 0x08, "rx_align_err" },
124 { 0x09, "rx_mac_ctrl" },
125 { 0x0a, "rx_pause" },
126 { 0x0b, "rx_bcast" },
127 { 0x0c, "rx_mcast" },
128 { 0x0d, "rx_ucast" },
129 { 0x0e, "rx_64_or_less" },
130 { 0x0f, "rx_65_127" },
131 { 0x10, "rx_128_255" },
132 { 0x11, "rx_256_511" },
133 { 0x12, "rx_512_1023" },
134 { 0x13, "rx_1024_1522" },
135 { 0x14, "tx" },
136 { 0x15, "tx_hi" },
137 { 0x16, "tx_late_col" },
138 { 0x17, "tx_pause" },
139 { 0x18, "tx_bcast" },
140 { 0x19, "tx_mcast" },
141 { 0x1a, "tx_ucast" },
142 { 0x1b, "tx_deferred" },
143 { 0x1c, "tx_total_col" },
144 { 0x1d, "tx_exc_col" },
145 { 0x1e, "tx_single_col" },
146 { 0x1f, "tx_mult_col" },
147 { 0x100, "rx_discards" },
148 { 0x101, "tx_discards" },
149};
150
151static const struct ksz_mib_names ksz9477_mib_names[] = {
152 { 0x00, "rx_hi" },
153 { 0x01, "rx_undersize" },
154 { 0x02, "rx_fragments" },
155 { 0x03, "rx_oversize" },
156 { 0x04, "rx_jabbers" },
157 { 0x05, "rx_symbol_err" },
158 { 0x06, "rx_crc_err" },
159 { 0x07, "rx_align_err" },
160 { 0x08, "rx_mac_ctrl" },
161 { 0x09, "rx_pause" },
162 { 0x0A, "rx_bcast" },
163 { 0x0B, "rx_mcast" },
164 { 0x0C, "rx_ucast" },
165 { 0x0D, "rx_64_or_less" },
166 { 0x0E, "rx_65_127" },
167 { 0x0F, "rx_128_255" },
168 { 0x10, "rx_256_511" },
169 { 0x11, "rx_512_1023" },
170 { 0x12, "rx_1024_1522" },
171 { 0x13, "rx_1523_2000" },
172 { 0x14, "rx_2001" },
173 { 0x15, "tx_hi" },
174 { 0x16, "tx_late_col" },
175 { 0x17, "tx_pause" },
176 { 0x18, "tx_bcast" },
177 { 0x19, "tx_mcast" },
178 { 0x1A, "tx_ucast" },
179 { 0x1B, "tx_deferred" },
180 { 0x1C, "tx_total_col" },
181 { 0x1D, "tx_exc_col" },
182 { 0x1E, "tx_single_col" },
183 { 0x1F, "tx_mult_col" },
184 { 0x80, "rx_total" },
185 { 0x81, "tx_total" },
186 { 0x82, "rx_discards" },
187 { 0x83, "tx_discards" },
188};
189
190struct ksz_driver_strength_prop {
191 const char *name;
192 int offset;
193 int value;
194};
195
196enum ksz_driver_strength_type {
197 KSZ_DRIVER_STRENGTH_HI,
198 KSZ_DRIVER_STRENGTH_LO,
199 KSZ_DRIVER_STRENGTH_IO,
200};
201
202/**
203 * struct ksz_drive_strength - drive strength mapping
204 * @reg_val: register value
205 * @microamp: microamp value
206 */
207struct ksz_drive_strength {
208 u32 reg_val;
209 u32 microamp;
210};
211
212/* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
213 *
214 * This values are not documented in KSZ9477 variants but confirmed by
215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
217 *
218 * Documentation in KSZ8795CLX provides more information with some
219 * recommendations:
220 * - for high speed signals
221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
222 * 2.5V or 3.3V VDDIO.
223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
224 * using 1.8V VDDIO.
225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
226 * or 3.3V VDDIO.
227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
228 * 5. In same interface, the heavy loading should use higher one of the
229 * drive current strength.
230 * - for low speed signals
231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
234 * 4. If it is heavy loading, can use higher drive current strength.
235 */
236static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
237 { SW_DRIVE_STRENGTH_2MA, 2000 },
238 { SW_DRIVE_STRENGTH_4MA, 4000 },
239 { SW_DRIVE_STRENGTH_8MA, 8000 },
240 { SW_DRIVE_STRENGTH_12MA, 12000 },
241 { SW_DRIVE_STRENGTH_16MA, 16000 },
242 { SW_DRIVE_STRENGTH_20MA, 20000 },
243 { SW_DRIVE_STRENGTH_24MA, 24000 },
244 { SW_DRIVE_STRENGTH_28MA, 28000 },
245};
246
247/* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, ..
248 * variants.
249 * This values are documented in KSZ8873 and KSZ8863 datasheets.
250 */
251static const struct ksz_drive_strength ksz8830_drive_strengths[] = {
252 { 0, 8000 },
253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
254};
255
256static const struct ksz_dev_ops ksz8_dev_ops = {
257 .setup = ksz8_setup,
258 .get_port_addr = ksz8_get_port_addr,
259 .cfg_port_member = ksz8_cfg_port_member,
260 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
261 .port_setup = ksz8_port_setup,
262 .r_phy = ksz8_r_phy,
263 .w_phy = ksz8_w_phy,
264 .r_mib_cnt = ksz8_r_mib_cnt,
265 .r_mib_pkt = ksz8_r_mib_pkt,
266 .r_mib_stat64 = ksz88xx_r_mib_stats64,
267 .freeze_mib = ksz8_freeze_mib,
268 .port_init_cnt = ksz8_port_init_cnt,
269 .fdb_dump = ksz8_fdb_dump,
270 .fdb_add = ksz8_fdb_add,
271 .fdb_del = ksz8_fdb_del,
272 .mdb_add = ksz8_mdb_add,
273 .mdb_del = ksz8_mdb_del,
274 .vlan_filtering = ksz8_port_vlan_filtering,
275 .vlan_add = ksz8_port_vlan_add,
276 .vlan_del = ksz8_port_vlan_del,
277 .mirror_add = ksz8_port_mirror_add,
278 .mirror_del = ksz8_port_mirror_del,
279 .get_caps = ksz8_get_caps,
280 .config_cpu_port = ksz8_config_cpu_port,
281 .enable_stp_addr = ksz8_enable_stp_addr,
282 .reset = ksz8_reset_switch,
283 .init = ksz8_switch_init,
284 .exit = ksz8_switch_exit,
285 .change_mtu = ksz8_change_mtu,
286};
287
288static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
289 unsigned int mode,
290 phy_interface_t interface,
291 struct phy_device *phydev, int speed,
292 int duplex, bool tx_pause,
293 bool rx_pause);
294
295static const struct ksz_dev_ops ksz9477_dev_ops = {
296 .setup = ksz9477_setup,
297 .get_port_addr = ksz9477_get_port_addr,
298 .cfg_port_member = ksz9477_cfg_port_member,
299 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
300 .port_setup = ksz9477_port_setup,
301 .set_ageing_time = ksz9477_set_ageing_time,
302 .r_phy = ksz9477_r_phy,
303 .w_phy = ksz9477_w_phy,
304 .r_mib_cnt = ksz9477_r_mib_cnt,
305 .r_mib_pkt = ksz9477_r_mib_pkt,
306 .r_mib_stat64 = ksz_r_mib_stats64,
307 .freeze_mib = ksz9477_freeze_mib,
308 .port_init_cnt = ksz9477_port_init_cnt,
309 .vlan_filtering = ksz9477_port_vlan_filtering,
310 .vlan_add = ksz9477_port_vlan_add,
311 .vlan_del = ksz9477_port_vlan_del,
312 .mirror_add = ksz9477_port_mirror_add,
313 .mirror_del = ksz9477_port_mirror_del,
314 .get_caps = ksz9477_get_caps,
315 .fdb_dump = ksz9477_fdb_dump,
316 .fdb_add = ksz9477_fdb_add,
317 .fdb_del = ksz9477_fdb_del,
318 .mdb_add = ksz9477_mdb_add,
319 .mdb_del = ksz9477_mdb_del,
320 .change_mtu = ksz9477_change_mtu,
321 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
322 .get_wol = ksz9477_get_wol,
323 .set_wol = ksz9477_set_wol,
324 .wol_pre_shutdown = ksz9477_wol_pre_shutdown,
325 .config_cpu_port = ksz9477_config_cpu_port,
326 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
327 .enable_stp_addr = ksz9477_enable_stp_addr,
328 .reset = ksz9477_reset_switch,
329 .init = ksz9477_switch_init,
330 .exit = ksz9477_switch_exit,
331};
332
333static const struct ksz_dev_ops lan937x_dev_ops = {
334 .setup = lan937x_setup,
335 .teardown = lan937x_teardown,
336 .get_port_addr = ksz9477_get_port_addr,
337 .cfg_port_member = ksz9477_cfg_port_member,
338 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
339 .port_setup = lan937x_port_setup,
340 .set_ageing_time = lan937x_set_ageing_time,
341 .r_phy = lan937x_r_phy,
342 .w_phy = lan937x_w_phy,
343 .r_mib_cnt = ksz9477_r_mib_cnt,
344 .r_mib_pkt = ksz9477_r_mib_pkt,
345 .r_mib_stat64 = ksz_r_mib_stats64,
346 .freeze_mib = ksz9477_freeze_mib,
347 .port_init_cnt = ksz9477_port_init_cnt,
348 .vlan_filtering = ksz9477_port_vlan_filtering,
349 .vlan_add = ksz9477_port_vlan_add,
350 .vlan_del = ksz9477_port_vlan_del,
351 .mirror_add = ksz9477_port_mirror_add,
352 .mirror_del = ksz9477_port_mirror_del,
353 .get_caps = lan937x_phylink_get_caps,
354 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
355 .fdb_dump = ksz9477_fdb_dump,
356 .fdb_add = ksz9477_fdb_add,
357 .fdb_del = ksz9477_fdb_del,
358 .mdb_add = ksz9477_mdb_add,
359 .mdb_del = ksz9477_mdb_del,
360 .change_mtu = lan937x_change_mtu,
361 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
362 .config_cpu_port = lan937x_config_cpu_port,
363 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
364 .enable_stp_addr = ksz9477_enable_stp_addr,
365 .reset = lan937x_reset_switch,
366 .init = lan937x_switch_init,
367 .exit = lan937x_switch_exit,
368};
369
370static const u16 ksz8795_regs[] = {
371 [REG_SW_MAC_ADDR] = 0x68,
372 [REG_IND_CTRL_0] = 0x6E,
373 [REG_IND_DATA_8] = 0x70,
374 [REG_IND_DATA_CHECK] = 0x72,
375 [REG_IND_DATA_HI] = 0x71,
376 [REG_IND_DATA_LO] = 0x75,
377 [REG_IND_MIB_CHECK] = 0x74,
378 [REG_IND_BYTE] = 0xA0,
379 [P_FORCE_CTRL] = 0x0C,
380 [P_LINK_STATUS] = 0x0E,
381 [P_LOCAL_CTRL] = 0x07,
382 [P_NEG_RESTART_CTRL] = 0x0D,
383 [P_REMOTE_STATUS] = 0x08,
384 [P_SPEED_STATUS] = 0x09,
385 [S_TAIL_TAG_CTRL] = 0x0C,
386 [P_STP_CTRL] = 0x02,
387 [S_START_CTRL] = 0x01,
388 [S_BROADCAST_CTRL] = 0x06,
389 [S_MULTICAST_CTRL] = 0x04,
390 [P_XMII_CTRL_0] = 0x06,
391 [P_XMII_CTRL_1] = 0x06,
392};
393
394static const u32 ksz8795_masks[] = {
395 [PORT_802_1P_REMAPPING] = BIT(7),
396 [SW_TAIL_TAG_ENABLE] = BIT(1),
397 [MIB_COUNTER_OVERFLOW] = BIT(6),
398 [MIB_COUNTER_VALID] = BIT(5),
399 [VLAN_TABLE_FID] = GENMASK(6, 0),
400 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
401 [VLAN_TABLE_VALID] = BIT(12),
402 [STATIC_MAC_TABLE_VALID] = BIT(21),
403 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
404 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
405 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
406 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
407 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
408 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
409 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
410 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
411 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
412 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
413 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
414 [P_MII_TX_FLOW_CTRL] = BIT(5),
415 [P_MII_RX_FLOW_CTRL] = BIT(5),
416};
417
418static const u8 ksz8795_xmii_ctrl0[] = {
419 [P_MII_100MBIT] = 0,
420 [P_MII_10MBIT] = 1,
421 [P_MII_FULL_DUPLEX] = 0,
422 [P_MII_HALF_DUPLEX] = 1,
423};
424
425static const u8 ksz8795_xmii_ctrl1[] = {
426 [P_RGMII_SEL] = 3,
427 [P_GMII_SEL] = 2,
428 [P_RMII_SEL] = 1,
429 [P_MII_SEL] = 0,
430 [P_GMII_1GBIT] = 1,
431 [P_GMII_NOT_1GBIT] = 0,
432};
433
434static const u8 ksz8795_shifts[] = {
435 [VLAN_TABLE_MEMBERSHIP_S] = 7,
436 [VLAN_TABLE] = 16,
437 [STATIC_MAC_FWD_PORTS] = 16,
438 [STATIC_MAC_FID] = 24,
439 [DYNAMIC_MAC_ENTRIES_H] = 3,
440 [DYNAMIC_MAC_ENTRIES] = 29,
441 [DYNAMIC_MAC_FID] = 16,
442 [DYNAMIC_MAC_TIMESTAMP] = 27,
443 [DYNAMIC_MAC_SRC_PORT] = 24,
444};
445
446static const u16 ksz8863_regs[] = {
447 [REG_SW_MAC_ADDR] = 0x70,
448 [REG_IND_CTRL_0] = 0x79,
449 [REG_IND_DATA_8] = 0x7B,
450 [REG_IND_DATA_CHECK] = 0x7B,
451 [REG_IND_DATA_HI] = 0x7C,
452 [REG_IND_DATA_LO] = 0x80,
453 [REG_IND_MIB_CHECK] = 0x80,
454 [P_FORCE_CTRL] = 0x0C,
455 [P_LINK_STATUS] = 0x0E,
456 [P_LOCAL_CTRL] = 0x0C,
457 [P_NEG_RESTART_CTRL] = 0x0D,
458 [P_REMOTE_STATUS] = 0x0E,
459 [P_SPEED_STATUS] = 0x0F,
460 [S_TAIL_TAG_CTRL] = 0x03,
461 [P_STP_CTRL] = 0x02,
462 [S_START_CTRL] = 0x01,
463 [S_BROADCAST_CTRL] = 0x06,
464 [S_MULTICAST_CTRL] = 0x04,
465};
466
467static const u32 ksz8863_masks[] = {
468 [PORT_802_1P_REMAPPING] = BIT(3),
469 [SW_TAIL_TAG_ENABLE] = BIT(6),
470 [MIB_COUNTER_OVERFLOW] = BIT(7),
471 [MIB_COUNTER_VALID] = BIT(6),
472 [VLAN_TABLE_FID] = GENMASK(15, 12),
473 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
474 [VLAN_TABLE_VALID] = BIT(19),
475 [STATIC_MAC_TABLE_VALID] = BIT(19),
476 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
477 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
478 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
479 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
480 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
481 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
482 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
483 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
484 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
485 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
486 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
487};
488
489static u8 ksz8863_shifts[] = {
490 [VLAN_TABLE_MEMBERSHIP_S] = 16,
491 [STATIC_MAC_FWD_PORTS] = 16,
492 [STATIC_MAC_FID] = 22,
493 [DYNAMIC_MAC_ENTRIES_H] = 8,
494 [DYNAMIC_MAC_ENTRIES] = 24,
495 [DYNAMIC_MAC_FID] = 16,
496 [DYNAMIC_MAC_TIMESTAMP] = 22,
497 [DYNAMIC_MAC_SRC_PORT] = 20,
498};
499
500static const u16 ksz9477_regs[] = {
501 [REG_SW_MAC_ADDR] = 0x0302,
502 [P_STP_CTRL] = 0x0B04,
503 [S_START_CTRL] = 0x0300,
504 [S_BROADCAST_CTRL] = 0x0332,
505 [S_MULTICAST_CTRL] = 0x0331,
506 [P_XMII_CTRL_0] = 0x0300,
507 [P_XMII_CTRL_1] = 0x0301,
508};
509
510static const u32 ksz9477_masks[] = {
511 [ALU_STAT_WRITE] = 0,
512 [ALU_STAT_READ] = 1,
513 [P_MII_TX_FLOW_CTRL] = BIT(5),
514 [P_MII_RX_FLOW_CTRL] = BIT(3),
515};
516
517static const u8 ksz9477_shifts[] = {
518 [ALU_STAT_INDEX] = 16,
519};
520
521static const u8 ksz9477_xmii_ctrl0[] = {
522 [P_MII_100MBIT] = 1,
523 [P_MII_10MBIT] = 0,
524 [P_MII_FULL_DUPLEX] = 1,
525 [P_MII_HALF_DUPLEX] = 0,
526};
527
528static const u8 ksz9477_xmii_ctrl1[] = {
529 [P_RGMII_SEL] = 0,
530 [P_RMII_SEL] = 1,
531 [P_GMII_SEL] = 2,
532 [P_MII_SEL] = 3,
533 [P_GMII_1GBIT] = 0,
534 [P_GMII_NOT_1GBIT] = 1,
535};
536
537static const u32 lan937x_masks[] = {
538 [ALU_STAT_WRITE] = 1,
539 [ALU_STAT_READ] = 2,
540 [P_MII_TX_FLOW_CTRL] = BIT(5),
541 [P_MII_RX_FLOW_CTRL] = BIT(3),
542};
543
544static const u8 lan937x_shifts[] = {
545 [ALU_STAT_INDEX] = 8,
546};
547
548static const struct regmap_range ksz8563_valid_regs[] = {
549 regmap_reg_range(0x0000, 0x0003),
550 regmap_reg_range(0x0006, 0x0006),
551 regmap_reg_range(0x000f, 0x001f),
552 regmap_reg_range(0x0100, 0x0100),
553 regmap_reg_range(0x0104, 0x0107),
554 regmap_reg_range(0x010d, 0x010d),
555 regmap_reg_range(0x0110, 0x0113),
556 regmap_reg_range(0x0120, 0x012b),
557 regmap_reg_range(0x0201, 0x0201),
558 regmap_reg_range(0x0210, 0x0213),
559 regmap_reg_range(0x0300, 0x0300),
560 regmap_reg_range(0x0302, 0x031b),
561 regmap_reg_range(0x0320, 0x032b),
562 regmap_reg_range(0x0330, 0x0336),
563 regmap_reg_range(0x0338, 0x033e),
564 regmap_reg_range(0x0340, 0x035f),
565 regmap_reg_range(0x0370, 0x0370),
566 regmap_reg_range(0x0378, 0x0378),
567 regmap_reg_range(0x037c, 0x037d),
568 regmap_reg_range(0x0390, 0x0393),
569 regmap_reg_range(0x0400, 0x040e),
570 regmap_reg_range(0x0410, 0x042f),
571 regmap_reg_range(0x0500, 0x0519),
572 regmap_reg_range(0x0520, 0x054b),
573 regmap_reg_range(0x0550, 0x05b3),
574
575 /* port 1 */
576 regmap_reg_range(0x1000, 0x1001),
577 regmap_reg_range(0x1004, 0x100b),
578 regmap_reg_range(0x1013, 0x1013),
579 regmap_reg_range(0x1017, 0x1017),
580 regmap_reg_range(0x101b, 0x101b),
581 regmap_reg_range(0x101f, 0x1021),
582 regmap_reg_range(0x1030, 0x1030),
583 regmap_reg_range(0x1100, 0x1111),
584 regmap_reg_range(0x111a, 0x111d),
585 regmap_reg_range(0x1122, 0x1127),
586 regmap_reg_range(0x112a, 0x112b),
587 regmap_reg_range(0x1136, 0x1139),
588 regmap_reg_range(0x113e, 0x113f),
589 regmap_reg_range(0x1400, 0x1401),
590 regmap_reg_range(0x1403, 0x1403),
591 regmap_reg_range(0x1410, 0x1417),
592 regmap_reg_range(0x1420, 0x1423),
593 regmap_reg_range(0x1500, 0x1507),
594 regmap_reg_range(0x1600, 0x1612),
595 regmap_reg_range(0x1800, 0x180f),
596 regmap_reg_range(0x1900, 0x1907),
597 regmap_reg_range(0x1914, 0x191b),
598 regmap_reg_range(0x1a00, 0x1a03),
599 regmap_reg_range(0x1a04, 0x1a08),
600 regmap_reg_range(0x1b00, 0x1b01),
601 regmap_reg_range(0x1b04, 0x1b04),
602 regmap_reg_range(0x1c00, 0x1c05),
603 regmap_reg_range(0x1c08, 0x1c1b),
604
605 /* port 2 */
606 regmap_reg_range(0x2000, 0x2001),
607 regmap_reg_range(0x2004, 0x200b),
608 regmap_reg_range(0x2013, 0x2013),
609 regmap_reg_range(0x2017, 0x2017),
610 regmap_reg_range(0x201b, 0x201b),
611 regmap_reg_range(0x201f, 0x2021),
612 regmap_reg_range(0x2030, 0x2030),
613 regmap_reg_range(0x2100, 0x2111),
614 regmap_reg_range(0x211a, 0x211d),
615 regmap_reg_range(0x2122, 0x2127),
616 regmap_reg_range(0x212a, 0x212b),
617 regmap_reg_range(0x2136, 0x2139),
618 regmap_reg_range(0x213e, 0x213f),
619 regmap_reg_range(0x2400, 0x2401),
620 regmap_reg_range(0x2403, 0x2403),
621 regmap_reg_range(0x2410, 0x2417),
622 regmap_reg_range(0x2420, 0x2423),
623 regmap_reg_range(0x2500, 0x2507),
624 regmap_reg_range(0x2600, 0x2612),
625 regmap_reg_range(0x2800, 0x280f),
626 regmap_reg_range(0x2900, 0x2907),
627 regmap_reg_range(0x2914, 0x291b),
628 regmap_reg_range(0x2a00, 0x2a03),
629 regmap_reg_range(0x2a04, 0x2a08),
630 regmap_reg_range(0x2b00, 0x2b01),
631 regmap_reg_range(0x2b04, 0x2b04),
632 regmap_reg_range(0x2c00, 0x2c05),
633 regmap_reg_range(0x2c08, 0x2c1b),
634
635 /* port 3 */
636 regmap_reg_range(0x3000, 0x3001),
637 regmap_reg_range(0x3004, 0x300b),
638 regmap_reg_range(0x3013, 0x3013),
639 regmap_reg_range(0x3017, 0x3017),
640 regmap_reg_range(0x301b, 0x301b),
641 regmap_reg_range(0x301f, 0x3021),
642 regmap_reg_range(0x3030, 0x3030),
643 regmap_reg_range(0x3300, 0x3301),
644 regmap_reg_range(0x3303, 0x3303),
645 regmap_reg_range(0x3400, 0x3401),
646 regmap_reg_range(0x3403, 0x3403),
647 regmap_reg_range(0x3410, 0x3417),
648 regmap_reg_range(0x3420, 0x3423),
649 regmap_reg_range(0x3500, 0x3507),
650 regmap_reg_range(0x3600, 0x3612),
651 regmap_reg_range(0x3800, 0x380f),
652 regmap_reg_range(0x3900, 0x3907),
653 regmap_reg_range(0x3914, 0x391b),
654 regmap_reg_range(0x3a00, 0x3a03),
655 regmap_reg_range(0x3a04, 0x3a08),
656 regmap_reg_range(0x3b00, 0x3b01),
657 regmap_reg_range(0x3b04, 0x3b04),
658 regmap_reg_range(0x3c00, 0x3c05),
659 regmap_reg_range(0x3c08, 0x3c1b),
660};
661
662static const struct regmap_access_table ksz8563_register_set = {
663 .yes_ranges = ksz8563_valid_regs,
664 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
665};
666
667static const struct regmap_range ksz9477_valid_regs[] = {
668 regmap_reg_range(0x0000, 0x0003),
669 regmap_reg_range(0x0006, 0x0006),
670 regmap_reg_range(0x0010, 0x001f),
671 regmap_reg_range(0x0100, 0x0100),
672 regmap_reg_range(0x0103, 0x0107),
673 regmap_reg_range(0x010d, 0x010d),
674 regmap_reg_range(0x0110, 0x0113),
675 regmap_reg_range(0x0120, 0x012b),
676 regmap_reg_range(0x0201, 0x0201),
677 regmap_reg_range(0x0210, 0x0213),
678 regmap_reg_range(0x0300, 0x0300),
679 regmap_reg_range(0x0302, 0x031b),
680 regmap_reg_range(0x0320, 0x032b),
681 regmap_reg_range(0x0330, 0x0336),
682 regmap_reg_range(0x0338, 0x033b),
683 regmap_reg_range(0x033e, 0x033e),
684 regmap_reg_range(0x0340, 0x035f),
685 regmap_reg_range(0x0370, 0x0370),
686 regmap_reg_range(0x0378, 0x0378),
687 regmap_reg_range(0x037c, 0x037d),
688 regmap_reg_range(0x0390, 0x0393),
689 regmap_reg_range(0x0400, 0x040e),
690 regmap_reg_range(0x0410, 0x042f),
691 regmap_reg_range(0x0444, 0x044b),
692 regmap_reg_range(0x0450, 0x046f),
693 regmap_reg_range(0x0500, 0x0519),
694 regmap_reg_range(0x0520, 0x054b),
695 regmap_reg_range(0x0550, 0x05b3),
696 regmap_reg_range(0x0604, 0x060b),
697 regmap_reg_range(0x0610, 0x0612),
698 regmap_reg_range(0x0614, 0x062c),
699 regmap_reg_range(0x0640, 0x0645),
700 regmap_reg_range(0x0648, 0x064d),
701
702 /* port 1 */
703 regmap_reg_range(0x1000, 0x1001),
704 regmap_reg_range(0x1013, 0x1013),
705 regmap_reg_range(0x1017, 0x1017),
706 regmap_reg_range(0x101b, 0x101b),
707 regmap_reg_range(0x101f, 0x1020),
708 regmap_reg_range(0x1030, 0x1030),
709 regmap_reg_range(0x1100, 0x1115),
710 regmap_reg_range(0x111a, 0x111f),
711 regmap_reg_range(0x1120, 0x112b),
712 regmap_reg_range(0x1134, 0x113b),
713 regmap_reg_range(0x113c, 0x113f),
714 regmap_reg_range(0x1400, 0x1401),
715 regmap_reg_range(0x1403, 0x1403),
716 regmap_reg_range(0x1410, 0x1417),
717 regmap_reg_range(0x1420, 0x1423),
718 regmap_reg_range(0x1500, 0x1507),
719 regmap_reg_range(0x1600, 0x1613),
720 regmap_reg_range(0x1800, 0x180f),
721 regmap_reg_range(0x1820, 0x1827),
722 regmap_reg_range(0x1830, 0x1837),
723 regmap_reg_range(0x1840, 0x184b),
724 regmap_reg_range(0x1900, 0x1907),
725 regmap_reg_range(0x1914, 0x191b),
726 regmap_reg_range(0x1920, 0x1920),
727 regmap_reg_range(0x1923, 0x1927),
728 regmap_reg_range(0x1a00, 0x1a03),
729 regmap_reg_range(0x1a04, 0x1a07),
730 regmap_reg_range(0x1b00, 0x1b01),
731 regmap_reg_range(0x1b04, 0x1b04),
732 regmap_reg_range(0x1c00, 0x1c05),
733 regmap_reg_range(0x1c08, 0x1c1b),
734
735 /* port 2 */
736 regmap_reg_range(0x2000, 0x2001),
737 regmap_reg_range(0x2013, 0x2013),
738 regmap_reg_range(0x2017, 0x2017),
739 regmap_reg_range(0x201b, 0x201b),
740 regmap_reg_range(0x201f, 0x2020),
741 regmap_reg_range(0x2030, 0x2030),
742 regmap_reg_range(0x2100, 0x2115),
743 regmap_reg_range(0x211a, 0x211f),
744 regmap_reg_range(0x2120, 0x212b),
745 regmap_reg_range(0x2134, 0x213b),
746 regmap_reg_range(0x213c, 0x213f),
747 regmap_reg_range(0x2400, 0x2401),
748 regmap_reg_range(0x2403, 0x2403),
749 regmap_reg_range(0x2410, 0x2417),
750 regmap_reg_range(0x2420, 0x2423),
751 regmap_reg_range(0x2500, 0x2507),
752 regmap_reg_range(0x2600, 0x2613),
753 regmap_reg_range(0x2800, 0x280f),
754 regmap_reg_range(0x2820, 0x2827),
755 regmap_reg_range(0x2830, 0x2837),
756 regmap_reg_range(0x2840, 0x284b),
757 regmap_reg_range(0x2900, 0x2907),
758 regmap_reg_range(0x2914, 0x291b),
759 regmap_reg_range(0x2920, 0x2920),
760 regmap_reg_range(0x2923, 0x2927),
761 regmap_reg_range(0x2a00, 0x2a03),
762 regmap_reg_range(0x2a04, 0x2a07),
763 regmap_reg_range(0x2b00, 0x2b01),
764 regmap_reg_range(0x2b04, 0x2b04),
765 regmap_reg_range(0x2c00, 0x2c05),
766 regmap_reg_range(0x2c08, 0x2c1b),
767
768 /* port 3 */
769 regmap_reg_range(0x3000, 0x3001),
770 regmap_reg_range(0x3013, 0x3013),
771 regmap_reg_range(0x3017, 0x3017),
772 regmap_reg_range(0x301b, 0x301b),
773 regmap_reg_range(0x301f, 0x3020),
774 regmap_reg_range(0x3030, 0x3030),
775 regmap_reg_range(0x3100, 0x3115),
776 regmap_reg_range(0x311a, 0x311f),
777 regmap_reg_range(0x3120, 0x312b),
778 regmap_reg_range(0x3134, 0x313b),
779 regmap_reg_range(0x313c, 0x313f),
780 regmap_reg_range(0x3400, 0x3401),
781 regmap_reg_range(0x3403, 0x3403),
782 regmap_reg_range(0x3410, 0x3417),
783 regmap_reg_range(0x3420, 0x3423),
784 regmap_reg_range(0x3500, 0x3507),
785 regmap_reg_range(0x3600, 0x3613),
786 regmap_reg_range(0x3800, 0x380f),
787 regmap_reg_range(0x3820, 0x3827),
788 regmap_reg_range(0x3830, 0x3837),
789 regmap_reg_range(0x3840, 0x384b),
790 regmap_reg_range(0x3900, 0x3907),
791 regmap_reg_range(0x3914, 0x391b),
792 regmap_reg_range(0x3920, 0x3920),
793 regmap_reg_range(0x3923, 0x3927),
794 regmap_reg_range(0x3a00, 0x3a03),
795 regmap_reg_range(0x3a04, 0x3a07),
796 regmap_reg_range(0x3b00, 0x3b01),
797 regmap_reg_range(0x3b04, 0x3b04),
798 regmap_reg_range(0x3c00, 0x3c05),
799 regmap_reg_range(0x3c08, 0x3c1b),
800
801 /* port 4 */
802 regmap_reg_range(0x4000, 0x4001),
803 regmap_reg_range(0x4013, 0x4013),
804 regmap_reg_range(0x4017, 0x4017),
805 regmap_reg_range(0x401b, 0x401b),
806 regmap_reg_range(0x401f, 0x4020),
807 regmap_reg_range(0x4030, 0x4030),
808 regmap_reg_range(0x4100, 0x4115),
809 regmap_reg_range(0x411a, 0x411f),
810 regmap_reg_range(0x4120, 0x412b),
811 regmap_reg_range(0x4134, 0x413b),
812 regmap_reg_range(0x413c, 0x413f),
813 regmap_reg_range(0x4400, 0x4401),
814 regmap_reg_range(0x4403, 0x4403),
815 regmap_reg_range(0x4410, 0x4417),
816 regmap_reg_range(0x4420, 0x4423),
817 regmap_reg_range(0x4500, 0x4507),
818 regmap_reg_range(0x4600, 0x4613),
819 regmap_reg_range(0x4800, 0x480f),
820 regmap_reg_range(0x4820, 0x4827),
821 regmap_reg_range(0x4830, 0x4837),
822 regmap_reg_range(0x4840, 0x484b),
823 regmap_reg_range(0x4900, 0x4907),
824 regmap_reg_range(0x4914, 0x491b),
825 regmap_reg_range(0x4920, 0x4920),
826 regmap_reg_range(0x4923, 0x4927),
827 regmap_reg_range(0x4a00, 0x4a03),
828 regmap_reg_range(0x4a04, 0x4a07),
829 regmap_reg_range(0x4b00, 0x4b01),
830 regmap_reg_range(0x4b04, 0x4b04),
831 regmap_reg_range(0x4c00, 0x4c05),
832 regmap_reg_range(0x4c08, 0x4c1b),
833
834 /* port 5 */
835 regmap_reg_range(0x5000, 0x5001),
836 regmap_reg_range(0x5013, 0x5013),
837 regmap_reg_range(0x5017, 0x5017),
838 regmap_reg_range(0x501b, 0x501b),
839 regmap_reg_range(0x501f, 0x5020),
840 regmap_reg_range(0x5030, 0x5030),
841 regmap_reg_range(0x5100, 0x5115),
842 regmap_reg_range(0x511a, 0x511f),
843 regmap_reg_range(0x5120, 0x512b),
844 regmap_reg_range(0x5134, 0x513b),
845 regmap_reg_range(0x513c, 0x513f),
846 regmap_reg_range(0x5400, 0x5401),
847 regmap_reg_range(0x5403, 0x5403),
848 regmap_reg_range(0x5410, 0x5417),
849 regmap_reg_range(0x5420, 0x5423),
850 regmap_reg_range(0x5500, 0x5507),
851 regmap_reg_range(0x5600, 0x5613),
852 regmap_reg_range(0x5800, 0x580f),
853 regmap_reg_range(0x5820, 0x5827),
854 regmap_reg_range(0x5830, 0x5837),
855 regmap_reg_range(0x5840, 0x584b),
856 regmap_reg_range(0x5900, 0x5907),
857 regmap_reg_range(0x5914, 0x591b),
858 regmap_reg_range(0x5920, 0x5920),
859 regmap_reg_range(0x5923, 0x5927),
860 regmap_reg_range(0x5a00, 0x5a03),
861 regmap_reg_range(0x5a04, 0x5a07),
862 regmap_reg_range(0x5b00, 0x5b01),
863 regmap_reg_range(0x5b04, 0x5b04),
864 regmap_reg_range(0x5c00, 0x5c05),
865 regmap_reg_range(0x5c08, 0x5c1b),
866
867 /* port 6 */
868 regmap_reg_range(0x6000, 0x6001),
869 regmap_reg_range(0x6013, 0x6013),
870 regmap_reg_range(0x6017, 0x6017),
871 regmap_reg_range(0x601b, 0x601b),
872 regmap_reg_range(0x601f, 0x6020),
873 regmap_reg_range(0x6030, 0x6030),
874 regmap_reg_range(0x6300, 0x6301),
875 regmap_reg_range(0x6400, 0x6401),
876 regmap_reg_range(0x6403, 0x6403),
877 regmap_reg_range(0x6410, 0x6417),
878 regmap_reg_range(0x6420, 0x6423),
879 regmap_reg_range(0x6500, 0x6507),
880 regmap_reg_range(0x6600, 0x6613),
881 regmap_reg_range(0x6800, 0x680f),
882 regmap_reg_range(0x6820, 0x6827),
883 regmap_reg_range(0x6830, 0x6837),
884 regmap_reg_range(0x6840, 0x684b),
885 regmap_reg_range(0x6900, 0x6907),
886 regmap_reg_range(0x6914, 0x691b),
887 regmap_reg_range(0x6920, 0x6920),
888 regmap_reg_range(0x6923, 0x6927),
889 regmap_reg_range(0x6a00, 0x6a03),
890 regmap_reg_range(0x6a04, 0x6a07),
891 regmap_reg_range(0x6b00, 0x6b01),
892 regmap_reg_range(0x6b04, 0x6b04),
893 regmap_reg_range(0x6c00, 0x6c05),
894 regmap_reg_range(0x6c08, 0x6c1b),
895
896 /* port 7 */
897 regmap_reg_range(0x7000, 0x7001),
898 regmap_reg_range(0x7013, 0x7013),
899 regmap_reg_range(0x7017, 0x7017),
900 regmap_reg_range(0x701b, 0x701b),
901 regmap_reg_range(0x701f, 0x7020),
902 regmap_reg_range(0x7030, 0x7030),
903 regmap_reg_range(0x7200, 0x7203),
904 regmap_reg_range(0x7206, 0x7207),
905 regmap_reg_range(0x7300, 0x7301),
906 regmap_reg_range(0x7400, 0x7401),
907 regmap_reg_range(0x7403, 0x7403),
908 regmap_reg_range(0x7410, 0x7417),
909 regmap_reg_range(0x7420, 0x7423),
910 regmap_reg_range(0x7500, 0x7507),
911 regmap_reg_range(0x7600, 0x7613),
912 regmap_reg_range(0x7800, 0x780f),
913 regmap_reg_range(0x7820, 0x7827),
914 regmap_reg_range(0x7830, 0x7837),
915 regmap_reg_range(0x7840, 0x784b),
916 regmap_reg_range(0x7900, 0x7907),
917 regmap_reg_range(0x7914, 0x791b),
918 regmap_reg_range(0x7920, 0x7920),
919 regmap_reg_range(0x7923, 0x7927),
920 regmap_reg_range(0x7a00, 0x7a03),
921 regmap_reg_range(0x7a04, 0x7a07),
922 regmap_reg_range(0x7b00, 0x7b01),
923 regmap_reg_range(0x7b04, 0x7b04),
924 regmap_reg_range(0x7c00, 0x7c05),
925 regmap_reg_range(0x7c08, 0x7c1b),
926};
927
928static const struct regmap_access_table ksz9477_register_set = {
929 .yes_ranges = ksz9477_valid_regs,
930 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
931};
932
933static const struct regmap_range ksz9896_valid_regs[] = {
934 regmap_reg_range(0x0000, 0x0003),
935 regmap_reg_range(0x0006, 0x0006),
936 regmap_reg_range(0x0010, 0x001f),
937 regmap_reg_range(0x0100, 0x0100),
938 regmap_reg_range(0x0103, 0x0107),
939 regmap_reg_range(0x010d, 0x010d),
940 regmap_reg_range(0x0110, 0x0113),
941 regmap_reg_range(0x0120, 0x0127),
942 regmap_reg_range(0x0201, 0x0201),
943 regmap_reg_range(0x0210, 0x0213),
944 regmap_reg_range(0x0300, 0x0300),
945 regmap_reg_range(0x0302, 0x030b),
946 regmap_reg_range(0x0310, 0x031b),
947 regmap_reg_range(0x0320, 0x032b),
948 regmap_reg_range(0x0330, 0x0336),
949 regmap_reg_range(0x0338, 0x033b),
950 regmap_reg_range(0x033e, 0x033e),
951 regmap_reg_range(0x0340, 0x035f),
952 regmap_reg_range(0x0370, 0x0370),
953 regmap_reg_range(0x0378, 0x0378),
954 regmap_reg_range(0x037c, 0x037d),
955 regmap_reg_range(0x0390, 0x0393),
956 regmap_reg_range(0x0400, 0x040e),
957 regmap_reg_range(0x0410, 0x042f),
958
959 /* port 1 */
960 regmap_reg_range(0x1000, 0x1001),
961 regmap_reg_range(0x1013, 0x1013),
962 regmap_reg_range(0x1017, 0x1017),
963 regmap_reg_range(0x101b, 0x101b),
964 regmap_reg_range(0x101f, 0x1020),
965 regmap_reg_range(0x1030, 0x1030),
966 regmap_reg_range(0x1100, 0x1115),
967 regmap_reg_range(0x111a, 0x111f),
968 regmap_reg_range(0x1122, 0x1127),
969 regmap_reg_range(0x112a, 0x112b),
970 regmap_reg_range(0x1136, 0x1139),
971 regmap_reg_range(0x113e, 0x113f),
972 regmap_reg_range(0x1400, 0x1401),
973 regmap_reg_range(0x1403, 0x1403),
974 regmap_reg_range(0x1410, 0x1417),
975 regmap_reg_range(0x1420, 0x1423),
976 regmap_reg_range(0x1500, 0x1507),
977 regmap_reg_range(0x1600, 0x1612),
978 regmap_reg_range(0x1800, 0x180f),
979 regmap_reg_range(0x1820, 0x1827),
980 regmap_reg_range(0x1830, 0x1837),
981 regmap_reg_range(0x1840, 0x184b),
982 regmap_reg_range(0x1900, 0x1907),
983 regmap_reg_range(0x1914, 0x1915),
984 regmap_reg_range(0x1a00, 0x1a03),
985 regmap_reg_range(0x1a04, 0x1a07),
986 regmap_reg_range(0x1b00, 0x1b01),
987 regmap_reg_range(0x1b04, 0x1b04),
988
989 /* port 2 */
990 regmap_reg_range(0x2000, 0x2001),
991 regmap_reg_range(0x2013, 0x2013),
992 regmap_reg_range(0x2017, 0x2017),
993 regmap_reg_range(0x201b, 0x201b),
994 regmap_reg_range(0x201f, 0x2020),
995 regmap_reg_range(0x2030, 0x2030),
996 regmap_reg_range(0x2100, 0x2115),
997 regmap_reg_range(0x211a, 0x211f),
998 regmap_reg_range(0x2122, 0x2127),
999 regmap_reg_range(0x212a, 0x212b),
1000 regmap_reg_range(0x2136, 0x2139),
1001 regmap_reg_range(0x213e, 0x213f),
1002 regmap_reg_range(0x2400, 0x2401),
1003 regmap_reg_range(0x2403, 0x2403),
1004 regmap_reg_range(0x2410, 0x2417),
1005 regmap_reg_range(0x2420, 0x2423),
1006 regmap_reg_range(0x2500, 0x2507),
1007 regmap_reg_range(0x2600, 0x2612),
1008 regmap_reg_range(0x2800, 0x280f),
1009 regmap_reg_range(0x2820, 0x2827),
1010 regmap_reg_range(0x2830, 0x2837),
1011 regmap_reg_range(0x2840, 0x284b),
1012 regmap_reg_range(0x2900, 0x2907),
1013 regmap_reg_range(0x2914, 0x2915),
1014 regmap_reg_range(0x2a00, 0x2a03),
1015 regmap_reg_range(0x2a04, 0x2a07),
1016 regmap_reg_range(0x2b00, 0x2b01),
1017 regmap_reg_range(0x2b04, 0x2b04),
1018
1019 /* port 3 */
1020 regmap_reg_range(0x3000, 0x3001),
1021 regmap_reg_range(0x3013, 0x3013),
1022 regmap_reg_range(0x3017, 0x3017),
1023 regmap_reg_range(0x301b, 0x301b),
1024 regmap_reg_range(0x301f, 0x3020),
1025 regmap_reg_range(0x3030, 0x3030),
1026 regmap_reg_range(0x3100, 0x3115),
1027 regmap_reg_range(0x311a, 0x311f),
1028 regmap_reg_range(0x3122, 0x3127),
1029 regmap_reg_range(0x312a, 0x312b),
1030 regmap_reg_range(0x3136, 0x3139),
1031 regmap_reg_range(0x313e, 0x313f),
1032 regmap_reg_range(0x3400, 0x3401),
1033 regmap_reg_range(0x3403, 0x3403),
1034 regmap_reg_range(0x3410, 0x3417),
1035 regmap_reg_range(0x3420, 0x3423),
1036 regmap_reg_range(0x3500, 0x3507),
1037 regmap_reg_range(0x3600, 0x3612),
1038 regmap_reg_range(0x3800, 0x380f),
1039 regmap_reg_range(0x3820, 0x3827),
1040 regmap_reg_range(0x3830, 0x3837),
1041 regmap_reg_range(0x3840, 0x384b),
1042 regmap_reg_range(0x3900, 0x3907),
1043 regmap_reg_range(0x3914, 0x3915),
1044 regmap_reg_range(0x3a00, 0x3a03),
1045 regmap_reg_range(0x3a04, 0x3a07),
1046 regmap_reg_range(0x3b00, 0x3b01),
1047 regmap_reg_range(0x3b04, 0x3b04),
1048
1049 /* port 4 */
1050 regmap_reg_range(0x4000, 0x4001),
1051 regmap_reg_range(0x4013, 0x4013),
1052 regmap_reg_range(0x4017, 0x4017),
1053 regmap_reg_range(0x401b, 0x401b),
1054 regmap_reg_range(0x401f, 0x4020),
1055 regmap_reg_range(0x4030, 0x4030),
1056 regmap_reg_range(0x4100, 0x4115),
1057 regmap_reg_range(0x411a, 0x411f),
1058 regmap_reg_range(0x4122, 0x4127),
1059 regmap_reg_range(0x412a, 0x412b),
1060 regmap_reg_range(0x4136, 0x4139),
1061 regmap_reg_range(0x413e, 0x413f),
1062 regmap_reg_range(0x4400, 0x4401),
1063 regmap_reg_range(0x4403, 0x4403),
1064 regmap_reg_range(0x4410, 0x4417),
1065 regmap_reg_range(0x4420, 0x4423),
1066 regmap_reg_range(0x4500, 0x4507),
1067 regmap_reg_range(0x4600, 0x4612),
1068 regmap_reg_range(0x4800, 0x480f),
1069 regmap_reg_range(0x4820, 0x4827),
1070 regmap_reg_range(0x4830, 0x4837),
1071 regmap_reg_range(0x4840, 0x484b),
1072 regmap_reg_range(0x4900, 0x4907),
1073 regmap_reg_range(0x4914, 0x4915),
1074 regmap_reg_range(0x4a00, 0x4a03),
1075 regmap_reg_range(0x4a04, 0x4a07),
1076 regmap_reg_range(0x4b00, 0x4b01),
1077 regmap_reg_range(0x4b04, 0x4b04),
1078
1079 /* port 5 */
1080 regmap_reg_range(0x5000, 0x5001),
1081 regmap_reg_range(0x5013, 0x5013),
1082 regmap_reg_range(0x5017, 0x5017),
1083 regmap_reg_range(0x501b, 0x501b),
1084 regmap_reg_range(0x501f, 0x5020),
1085 regmap_reg_range(0x5030, 0x5030),
1086 regmap_reg_range(0x5100, 0x5115),
1087 regmap_reg_range(0x511a, 0x511f),
1088 regmap_reg_range(0x5122, 0x5127),
1089 regmap_reg_range(0x512a, 0x512b),
1090 regmap_reg_range(0x5136, 0x5139),
1091 regmap_reg_range(0x513e, 0x513f),
1092 regmap_reg_range(0x5400, 0x5401),
1093 regmap_reg_range(0x5403, 0x5403),
1094 regmap_reg_range(0x5410, 0x5417),
1095 regmap_reg_range(0x5420, 0x5423),
1096 regmap_reg_range(0x5500, 0x5507),
1097 regmap_reg_range(0x5600, 0x5612),
1098 regmap_reg_range(0x5800, 0x580f),
1099 regmap_reg_range(0x5820, 0x5827),
1100 regmap_reg_range(0x5830, 0x5837),
1101 regmap_reg_range(0x5840, 0x584b),
1102 regmap_reg_range(0x5900, 0x5907),
1103 regmap_reg_range(0x5914, 0x5915),
1104 regmap_reg_range(0x5a00, 0x5a03),
1105 regmap_reg_range(0x5a04, 0x5a07),
1106 regmap_reg_range(0x5b00, 0x5b01),
1107 regmap_reg_range(0x5b04, 0x5b04),
1108
1109 /* port 6 */
1110 regmap_reg_range(0x6000, 0x6001),
1111 regmap_reg_range(0x6013, 0x6013),
1112 regmap_reg_range(0x6017, 0x6017),
1113 regmap_reg_range(0x601b, 0x601b),
1114 regmap_reg_range(0x601f, 0x6020),
1115 regmap_reg_range(0x6030, 0x6030),
1116 regmap_reg_range(0x6100, 0x6115),
1117 regmap_reg_range(0x611a, 0x611f),
1118 regmap_reg_range(0x6122, 0x6127),
1119 regmap_reg_range(0x612a, 0x612b),
1120 regmap_reg_range(0x6136, 0x6139),
1121 regmap_reg_range(0x613e, 0x613f),
1122 regmap_reg_range(0x6300, 0x6301),
1123 regmap_reg_range(0x6400, 0x6401),
1124 regmap_reg_range(0x6403, 0x6403),
1125 regmap_reg_range(0x6410, 0x6417),
1126 regmap_reg_range(0x6420, 0x6423),
1127 regmap_reg_range(0x6500, 0x6507),
1128 regmap_reg_range(0x6600, 0x6612),
1129 regmap_reg_range(0x6800, 0x680f),
1130 regmap_reg_range(0x6820, 0x6827),
1131 regmap_reg_range(0x6830, 0x6837),
1132 regmap_reg_range(0x6840, 0x684b),
1133 regmap_reg_range(0x6900, 0x6907),
1134 regmap_reg_range(0x6914, 0x6915),
1135 regmap_reg_range(0x6a00, 0x6a03),
1136 regmap_reg_range(0x6a04, 0x6a07),
1137 regmap_reg_range(0x6b00, 0x6b01),
1138 regmap_reg_range(0x6b04, 0x6b04),
1139};
1140
1141static const struct regmap_access_table ksz9896_register_set = {
1142 .yes_ranges = ksz9896_valid_regs,
1143 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1144};
1145
1146static const struct regmap_range ksz8873_valid_regs[] = {
1147 regmap_reg_range(0x00, 0x01),
1148 /* global control register */
1149 regmap_reg_range(0x02, 0x0f),
1150
1151 /* port registers */
1152 regmap_reg_range(0x10, 0x1d),
1153 regmap_reg_range(0x1e, 0x1f),
1154 regmap_reg_range(0x20, 0x2d),
1155 regmap_reg_range(0x2e, 0x2f),
1156 regmap_reg_range(0x30, 0x39),
1157 regmap_reg_range(0x3f, 0x3f),
1158
1159 /* advanced control registers */
1160 regmap_reg_range(0x60, 0x6f),
1161 regmap_reg_range(0x70, 0x75),
1162 regmap_reg_range(0x76, 0x78),
1163 regmap_reg_range(0x79, 0x7a),
1164 regmap_reg_range(0x7b, 0x83),
1165 regmap_reg_range(0x8e, 0x99),
1166 regmap_reg_range(0x9a, 0xa5),
1167 regmap_reg_range(0xa6, 0xa6),
1168 regmap_reg_range(0xa7, 0xaa),
1169 regmap_reg_range(0xab, 0xae),
1170 regmap_reg_range(0xaf, 0xba),
1171 regmap_reg_range(0xbb, 0xbc),
1172 regmap_reg_range(0xbd, 0xbd),
1173 regmap_reg_range(0xc0, 0xc0),
1174 regmap_reg_range(0xc2, 0xc2),
1175 regmap_reg_range(0xc3, 0xc3),
1176 regmap_reg_range(0xc4, 0xc4),
1177 regmap_reg_range(0xc6, 0xc6),
1178};
1179
1180static const struct regmap_access_table ksz8873_register_set = {
1181 .yes_ranges = ksz8873_valid_regs,
1182 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1183};
1184
1185const struct ksz_chip_data ksz_switch_chips[] = {
1186 [KSZ8563] = {
1187 .chip_id = KSZ8563_CHIP_ID,
1188 .dev_name = "KSZ8563",
1189 .num_vlans = 4096,
1190 .num_alus = 4096,
1191 .num_statics = 16,
1192 .cpu_ports = 0x07, /* can be configured as cpu port */
1193 .port_cnt = 3, /* total port count */
1194 .port_nirqs = 3,
1195 .num_tx_queues = 4,
1196 .tc_cbs_supported = true,
1197 .tc_ets_supported = true,
1198 .ops = &ksz9477_dev_ops,
1199 .mib_names = ksz9477_mib_names,
1200 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1201 .reg_mib_cnt = MIB_COUNTER_NUM,
1202 .regs = ksz9477_regs,
1203 .masks = ksz9477_masks,
1204 .shifts = ksz9477_shifts,
1205 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1206 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1207 .supports_mii = {false, false, true},
1208 .supports_rmii = {false, false, true},
1209 .supports_rgmii = {false, false, true},
1210 .internal_phy = {true, true, false},
1211 .gbit_capable = {false, false, true},
1212 .wr_table = &ksz8563_register_set,
1213 .rd_table = &ksz8563_register_set,
1214 },
1215
1216 [KSZ8795] = {
1217 .chip_id = KSZ8795_CHIP_ID,
1218 .dev_name = "KSZ8795",
1219 .num_vlans = 4096,
1220 .num_alus = 0,
1221 .num_statics = 8,
1222 .cpu_ports = 0x10, /* can be configured as cpu port */
1223 .port_cnt = 5, /* total cpu and user ports */
1224 .num_tx_queues = 4,
1225 .ops = &ksz8_dev_ops,
1226 .ksz87xx_eee_link_erratum = true,
1227 .mib_names = ksz9477_mib_names,
1228 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1229 .reg_mib_cnt = MIB_COUNTER_NUM,
1230 .regs = ksz8795_regs,
1231 .masks = ksz8795_masks,
1232 .shifts = ksz8795_shifts,
1233 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1234 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1235 .supports_mii = {false, false, false, false, true},
1236 .supports_rmii = {false, false, false, false, true},
1237 .supports_rgmii = {false, false, false, false, true},
1238 .internal_phy = {true, true, true, true, false},
1239 },
1240
1241 [KSZ8794] = {
1242 /* WARNING
1243 * =======
1244 * KSZ8794 is similar to KSZ8795, except the port map
1245 * contains a gap between external and CPU ports, the
1246 * port map is NOT continuous. The per-port register
1247 * map is shifted accordingly too, i.e. registers at
1248 * offset 0x40 are NOT used on KSZ8794 and they ARE
1249 * used on KSZ8795 for external port 3.
1250 * external cpu
1251 * KSZ8794 0,1,2 4
1252 * KSZ8795 0,1,2,3 4
1253 * KSZ8765 0,1,2,3 4
1254 * port_cnt is configured as 5, even though it is 4
1255 */
1256 .chip_id = KSZ8794_CHIP_ID,
1257 .dev_name = "KSZ8794",
1258 .num_vlans = 4096,
1259 .num_alus = 0,
1260 .num_statics = 8,
1261 .cpu_ports = 0x10, /* can be configured as cpu port */
1262 .port_cnt = 5, /* total cpu and user ports */
1263 .num_tx_queues = 4,
1264 .ops = &ksz8_dev_ops,
1265 .ksz87xx_eee_link_erratum = true,
1266 .mib_names = ksz9477_mib_names,
1267 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1268 .reg_mib_cnt = MIB_COUNTER_NUM,
1269 .regs = ksz8795_regs,
1270 .masks = ksz8795_masks,
1271 .shifts = ksz8795_shifts,
1272 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1273 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1274 .supports_mii = {false, false, false, false, true},
1275 .supports_rmii = {false, false, false, false, true},
1276 .supports_rgmii = {false, false, false, false, true},
1277 .internal_phy = {true, true, true, false, false},
1278 },
1279
1280 [KSZ8765] = {
1281 .chip_id = KSZ8765_CHIP_ID,
1282 .dev_name = "KSZ8765",
1283 .num_vlans = 4096,
1284 .num_alus = 0,
1285 .num_statics = 8,
1286 .cpu_ports = 0x10, /* can be configured as cpu port */
1287 .port_cnt = 5, /* total cpu and user ports */
1288 .num_tx_queues = 4,
1289 .ops = &ksz8_dev_ops,
1290 .ksz87xx_eee_link_erratum = true,
1291 .mib_names = ksz9477_mib_names,
1292 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1293 .reg_mib_cnt = MIB_COUNTER_NUM,
1294 .regs = ksz8795_regs,
1295 .masks = ksz8795_masks,
1296 .shifts = ksz8795_shifts,
1297 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1298 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1299 .supports_mii = {false, false, false, false, true},
1300 .supports_rmii = {false, false, false, false, true},
1301 .supports_rgmii = {false, false, false, false, true},
1302 .internal_phy = {true, true, true, true, false},
1303 },
1304
1305 [KSZ8830] = {
1306 .chip_id = KSZ8830_CHIP_ID,
1307 .dev_name = "KSZ8863/KSZ8873",
1308 .num_vlans = 16,
1309 .num_alus = 0,
1310 .num_statics = 8,
1311 .cpu_ports = 0x4, /* can be configured as cpu port */
1312 .port_cnt = 3,
1313 .num_tx_queues = 4,
1314 .ops = &ksz8_dev_ops,
1315 .mib_names = ksz88xx_mib_names,
1316 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1317 .reg_mib_cnt = MIB_COUNTER_NUM,
1318 .regs = ksz8863_regs,
1319 .masks = ksz8863_masks,
1320 .shifts = ksz8863_shifts,
1321 .supports_mii = {false, false, true},
1322 .supports_rmii = {false, false, true},
1323 .internal_phy = {true, true, false},
1324 .wr_table = &ksz8873_register_set,
1325 .rd_table = &ksz8873_register_set,
1326 },
1327
1328 [KSZ9477] = {
1329 .chip_id = KSZ9477_CHIP_ID,
1330 .dev_name = "KSZ9477",
1331 .num_vlans = 4096,
1332 .num_alus = 4096,
1333 .num_statics = 16,
1334 .cpu_ports = 0x7F, /* can be configured as cpu port */
1335 .port_cnt = 7, /* total physical port count */
1336 .port_nirqs = 4,
1337 .num_tx_queues = 4,
1338 .tc_cbs_supported = true,
1339 .tc_ets_supported = true,
1340 .ops = &ksz9477_dev_ops,
1341 .mib_names = ksz9477_mib_names,
1342 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1343 .reg_mib_cnt = MIB_COUNTER_NUM,
1344 .regs = ksz9477_regs,
1345 .masks = ksz9477_masks,
1346 .shifts = ksz9477_shifts,
1347 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1348 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1349 .supports_mii = {false, false, false, false,
1350 false, true, false},
1351 .supports_rmii = {false, false, false, false,
1352 false, true, false},
1353 .supports_rgmii = {false, false, false, false,
1354 false, true, false},
1355 .internal_phy = {true, true, true, true,
1356 true, false, false},
1357 .gbit_capable = {true, true, true, true, true, true, true},
1358 .wr_table = &ksz9477_register_set,
1359 .rd_table = &ksz9477_register_set,
1360 },
1361
1362 [KSZ9896] = {
1363 .chip_id = KSZ9896_CHIP_ID,
1364 .dev_name = "KSZ9896",
1365 .num_vlans = 4096,
1366 .num_alus = 4096,
1367 .num_statics = 16,
1368 .cpu_ports = 0x3F, /* can be configured as cpu port */
1369 .port_cnt = 6, /* total physical port count */
1370 .port_nirqs = 2,
1371 .num_tx_queues = 4,
1372 .ops = &ksz9477_dev_ops,
1373 .mib_names = ksz9477_mib_names,
1374 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1375 .reg_mib_cnt = MIB_COUNTER_NUM,
1376 .regs = ksz9477_regs,
1377 .masks = ksz9477_masks,
1378 .shifts = ksz9477_shifts,
1379 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1380 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1381 .supports_mii = {false, false, false, false,
1382 false, true},
1383 .supports_rmii = {false, false, false, false,
1384 false, true},
1385 .supports_rgmii = {false, false, false, false,
1386 false, true},
1387 .internal_phy = {true, true, true, true,
1388 true, false},
1389 .gbit_capable = {true, true, true, true, true, true},
1390 .wr_table = &ksz9896_register_set,
1391 .rd_table = &ksz9896_register_set,
1392 },
1393
1394 [KSZ9897] = {
1395 .chip_id = KSZ9897_CHIP_ID,
1396 .dev_name = "KSZ9897",
1397 .num_vlans = 4096,
1398 .num_alus = 4096,
1399 .num_statics = 16,
1400 .cpu_ports = 0x7F, /* can be configured as cpu port */
1401 .port_cnt = 7, /* total physical port count */
1402 .port_nirqs = 2,
1403 .num_tx_queues = 4,
1404 .ops = &ksz9477_dev_ops,
1405 .mib_names = ksz9477_mib_names,
1406 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1407 .reg_mib_cnt = MIB_COUNTER_NUM,
1408 .regs = ksz9477_regs,
1409 .masks = ksz9477_masks,
1410 .shifts = ksz9477_shifts,
1411 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1412 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1413 .supports_mii = {false, false, false, false,
1414 false, true, true},
1415 .supports_rmii = {false, false, false, false,
1416 false, true, true},
1417 .supports_rgmii = {false, false, false, false,
1418 false, true, true},
1419 .internal_phy = {true, true, true, true,
1420 true, false, false},
1421 .gbit_capable = {true, true, true, true, true, true, true},
1422 },
1423
1424 [KSZ9893] = {
1425 .chip_id = KSZ9893_CHIP_ID,
1426 .dev_name = "KSZ9893",
1427 .num_vlans = 4096,
1428 .num_alus = 4096,
1429 .num_statics = 16,
1430 .cpu_ports = 0x07, /* can be configured as cpu port */
1431 .port_cnt = 3, /* total port count */
1432 .port_nirqs = 2,
1433 .num_tx_queues = 4,
1434 .ops = &ksz9477_dev_ops,
1435 .mib_names = ksz9477_mib_names,
1436 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1437 .reg_mib_cnt = MIB_COUNTER_NUM,
1438 .regs = ksz9477_regs,
1439 .masks = ksz9477_masks,
1440 .shifts = ksz9477_shifts,
1441 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1442 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1443 .supports_mii = {false, false, true},
1444 .supports_rmii = {false, false, true},
1445 .supports_rgmii = {false, false, true},
1446 .internal_phy = {true, true, false},
1447 .gbit_capable = {true, true, true},
1448 },
1449
1450 [KSZ9563] = {
1451 .chip_id = KSZ9563_CHIP_ID,
1452 .dev_name = "KSZ9563",
1453 .num_vlans = 4096,
1454 .num_alus = 4096,
1455 .num_statics = 16,
1456 .cpu_ports = 0x07, /* can be configured as cpu port */
1457 .port_cnt = 3, /* total port count */
1458 .port_nirqs = 3,
1459 .num_tx_queues = 4,
1460 .tc_cbs_supported = true,
1461 .tc_ets_supported = true,
1462 .ops = &ksz9477_dev_ops,
1463 .mib_names = ksz9477_mib_names,
1464 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1465 .reg_mib_cnt = MIB_COUNTER_NUM,
1466 .regs = ksz9477_regs,
1467 .masks = ksz9477_masks,
1468 .shifts = ksz9477_shifts,
1469 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1470 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1471 .supports_mii = {false, false, true},
1472 .supports_rmii = {false, false, true},
1473 .supports_rgmii = {false, false, true},
1474 .internal_phy = {true, true, false},
1475 .gbit_capable = {true, true, true},
1476 },
1477
1478 [KSZ9567] = {
1479 .chip_id = KSZ9567_CHIP_ID,
1480 .dev_name = "KSZ9567",
1481 .num_vlans = 4096,
1482 .num_alus = 4096,
1483 .num_statics = 16,
1484 .cpu_ports = 0x7F, /* can be configured as cpu port */
1485 .port_cnt = 7, /* total physical port count */
1486 .port_nirqs = 3,
1487 .num_tx_queues = 4,
1488 .tc_cbs_supported = true,
1489 .tc_ets_supported = true,
1490 .ops = &ksz9477_dev_ops,
1491 .mib_names = ksz9477_mib_names,
1492 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1493 .reg_mib_cnt = MIB_COUNTER_NUM,
1494 .regs = ksz9477_regs,
1495 .masks = ksz9477_masks,
1496 .shifts = ksz9477_shifts,
1497 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1498 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1499 .supports_mii = {false, false, false, false,
1500 false, true, true},
1501 .supports_rmii = {false, false, false, false,
1502 false, true, true},
1503 .supports_rgmii = {false, false, false, false,
1504 false, true, true},
1505 .internal_phy = {true, true, true, true,
1506 true, false, false},
1507 .gbit_capable = {true, true, true, true, true, true, true},
1508 },
1509
1510 [LAN9370] = {
1511 .chip_id = LAN9370_CHIP_ID,
1512 .dev_name = "LAN9370",
1513 .num_vlans = 4096,
1514 .num_alus = 1024,
1515 .num_statics = 256,
1516 .cpu_ports = 0x10, /* can be configured as cpu port */
1517 .port_cnt = 5, /* total physical port count */
1518 .port_nirqs = 6,
1519 .num_tx_queues = 8,
1520 .tc_cbs_supported = true,
1521 .tc_ets_supported = true,
1522 .ops = &lan937x_dev_ops,
1523 .mib_names = ksz9477_mib_names,
1524 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1525 .reg_mib_cnt = MIB_COUNTER_NUM,
1526 .regs = ksz9477_regs,
1527 .masks = lan937x_masks,
1528 .shifts = lan937x_shifts,
1529 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1530 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1531 .supports_mii = {false, false, false, false, true},
1532 .supports_rmii = {false, false, false, false, true},
1533 .supports_rgmii = {false, false, false, false, true},
1534 .internal_phy = {true, true, true, true, false},
1535 },
1536
1537 [LAN9371] = {
1538 .chip_id = LAN9371_CHIP_ID,
1539 .dev_name = "LAN9371",
1540 .num_vlans = 4096,
1541 .num_alus = 1024,
1542 .num_statics = 256,
1543 .cpu_ports = 0x30, /* can be configured as cpu port */
1544 .port_cnt = 6, /* total physical port count */
1545 .port_nirqs = 6,
1546 .num_tx_queues = 8,
1547 .tc_cbs_supported = true,
1548 .tc_ets_supported = true,
1549 .ops = &lan937x_dev_ops,
1550 .mib_names = ksz9477_mib_names,
1551 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1552 .reg_mib_cnt = MIB_COUNTER_NUM,
1553 .regs = ksz9477_regs,
1554 .masks = lan937x_masks,
1555 .shifts = lan937x_shifts,
1556 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1557 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1558 .supports_mii = {false, false, false, false, true, true},
1559 .supports_rmii = {false, false, false, false, true, true},
1560 .supports_rgmii = {false, false, false, false, true, true},
1561 .internal_phy = {true, true, true, true, false, false},
1562 },
1563
1564 [LAN9372] = {
1565 .chip_id = LAN9372_CHIP_ID,
1566 .dev_name = "LAN9372",
1567 .num_vlans = 4096,
1568 .num_alus = 1024,
1569 .num_statics = 256,
1570 .cpu_ports = 0x30, /* can be configured as cpu port */
1571 .port_cnt = 8, /* total physical port count */
1572 .port_nirqs = 6,
1573 .num_tx_queues = 8,
1574 .tc_cbs_supported = true,
1575 .tc_ets_supported = true,
1576 .ops = &lan937x_dev_ops,
1577 .mib_names = ksz9477_mib_names,
1578 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1579 .reg_mib_cnt = MIB_COUNTER_NUM,
1580 .regs = ksz9477_regs,
1581 .masks = lan937x_masks,
1582 .shifts = lan937x_shifts,
1583 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1584 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1585 .supports_mii = {false, false, false, false,
1586 true, true, false, false},
1587 .supports_rmii = {false, false, false, false,
1588 true, true, false, false},
1589 .supports_rgmii = {false, false, false, false,
1590 true, true, false, false},
1591 .internal_phy = {true, true, true, true,
1592 false, false, true, true},
1593 },
1594
1595 [LAN9373] = {
1596 .chip_id = LAN9373_CHIP_ID,
1597 .dev_name = "LAN9373",
1598 .num_vlans = 4096,
1599 .num_alus = 1024,
1600 .num_statics = 256,
1601 .cpu_ports = 0x38, /* can be configured as cpu port */
1602 .port_cnt = 5, /* total physical port count */
1603 .port_nirqs = 6,
1604 .num_tx_queues = 8,
1605 .tc_cbs_supported = true,
1606 .tc_ets_supported = true,
1607 .ops = &lan937x_dev_ops,
1608 .mib_names = ksz9477_mib_names,
1609 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1610 .reg_mib_cnt = MIB_COUNTER_NUM,
1611 .regs = ksz9477_regs,
1612 .masks = lan937x_masks,
1613 .shifts = lan937x_shifts,
1614 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1615 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1616 .supports_mii = {false, false, false, false,
1617 true, true, false, false},
1618 .supports_rmii = {false, false, false, false,
1619 true, true, false, false},
1620 .supports_rgmii = {false, false, false, false,
1621 true, true, false, false},
1622 .internal_phy = {true, true, true, false,
1623 false, false, true, true},
1624 },
1625
1626 [LAN9374] = {
1627 .chip_id = LAN9374_CHIP_ID,
1628 .dev_name = "LAN9374",
1629 .num_vlans = 4096,
1630 .num_alus = 1024,
1631 .num_statics = 256,
1632 .cpu_ports = 0x30, /* can be configured as cpu port */
1633 .port_cnt = 8, /* total physical port count */
1634 .port_nirqs = 6,
1635 .num_tx_queues = 8,
1636 .tc_cbs_supported = true,
1637 .tc_ets_supported = true,
1638 .ops = &lan937x_dev_ops,
1639 .mib_names = ksz9477_mib_names,
1640 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1641 .reg_mib_cnt = MIB_COUNTER_NUM,
1642 .regs = ksz9477_regs,
1643 .masks = lan937x_masks,
1644 .shifts = lan937x_shifts,
1645 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1646 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1647 .supports_mii = {false, false, false, false,
1648 true, true, false, false},
1649 .supports_rmii = {false, false, false, false,
1650 true, true, false, false},
1651 .supports_rgmii = {false, false, false, false,
1652 true, true, false, false},
1653 .internal_phy = {true, true, true, true,
1654 false, false, true, true},
1655 },
1656};
1657EXPORT_SYMBOL_GPL(ksz_switch_chips);
1658
1659static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1660{
1661 int i;
1662
1663 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1664 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1665
1666 if (chip->chip_id == prod_num)
1667 return chip;
1668 }
1669
1670 return NULL;
1671}
1672
1673static int ksz_check_device_id(struct ksz_device *dev)
1674{
1675 const struct ksz_chip_data *dt_chip_data;
1676
1677 dt_chip_data = of_device_get_match_data(dev: dev->dev);
1678
1679 /* Check for Device Tree and Chip ID */
1680 if (dt_chip_data->chip_id != dev->chip_id) {
1681 dev_err(dev->dev,
1682 "Device tree specifies chip %s but found %s, please fix it!\n",
1683 dt_chip_data->dev_name, dev->info->dev_name);
1684 return -ENODEV;
1685 }
1686
1687 return 0;
1688}
1689
1690static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1691 struct phylink_config *config)
1692{
1693 struct ksz_device *dev = ds->priv;
1694
1695 if (dev->info->supports_mii[port])
1696 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1697
1698 if (dev->info->supports_rmii[port])
1699 __set_bit(PHY_INTERFACE_MODE_RMII,
1700 config->supported_interfaces);
1701
1702 if (dev->info->supports_rgmii[port])
1703 phy_interface_set_rgmii(intf: config->supported_interfaces);
1704
1705 if (dev->info->internal_phy[port]) {
1706 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1707 config->supported_interfaces);
1708 /* Compatibility for phylib's default interface type when the
1709 * phy-mode property is absent
1710 */
1711 __set_bit(PHY_INTERFACE_MODE_GMII,
1712 config->supported_interfaces);
1713 }
1714
1715 if (dev->dev_ops->get_caps)
1716 dev->dev_ops->get_caps(dev, port, config);
1717}
1718
1719void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1720{
1721 struct ethtool_pause_stats *pstats;
1722 struct rtnl_link_stats64 *stats;
1723 struct ksz_stats_raw *raw;
1724 struct ksz_port_mib *mib;
1725
1726 mib = &dev->ports[port].mib;
1727 stats = &mib->stats64;
1728 pstats = &mib->pause_stats;
1729 raw = (struct ksz_stats_raw *)mib->counters;
1730
1731 spin_lock(lock: &mib->stats64_lock);
1732
1733 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1734 raw->rx_pause;
1735 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1736 raw->tx_pause;
1737
1738 /* HW counters are counting bytes + FCS which is not acceptable
1739 * for rtnl_link_stats64 interface
1740 */
1741 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1742 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1743
1744 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1745 raw->rx_oversize;
1746
1747 stats->rx_crc_errors = raw->rx_crc_err;
1748 stats->rx_frame_errors = raw->rx_align_err;
1749 stats->rx_dropped = raw->rx_discards;
1750 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1751 stats->rx_frame_errors + stats->rx_dropped;
1752
1753 stats->tx_window_errors = raw->tx_late_col;
1754 stats->tx_fifo_errors = raw->tx_discards;
1755 stats->tx_aborted_errors = raw->tx_exc_col;
1756 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1757 stats->tx_aborted_errors;
1758
1759 stats->multicast = raw->rx_mcast;
1760 stats->collisions = raw->tx_total_col;
1761
1762 pstats->tx_pause_frames = raw->tx_pause;
1763 pstats->rx_pause_frames = raw->rx_pause;
1764
1765 spin_unlock(lock: &mib->stats64_lock);
1766}
1767
1768void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1769{
1770 struct ethtool_pause_stats *pstats;
1771 struct rtnl_link_stats64 *stats;
1772 struct ksz88xx_stats_raw *raw;
1773 struct ksz_port_mib *mib;
1774
1775 mib = &dev->ports[port].mib;
1776 stats = &mib->stats64;
1777 pstats = &mib->pause_stats;
1778 raw = (struct ksz88xx_stats_raw *)mib->counters;
1779
1780 spin_lock(lock: &mib->stats64_lock);
1781
1782 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1783 raw->rx_pause;
1784 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1785 raw->tx_pause;
1786
1787 /* HW counters are counting bytes + FCS which is not acceptable
1788 * for rtnl_link_stats64 interface
1789 */
1790 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1791 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1792
1793 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1794 raw->rx_oversize;
1795
1796 stats->rx_crc_errors = raw->rx_crc_err;
1797 stats->rx_frame_errors = raw->rx_align_err;
1798 stats->rx_dropped = raw->rx_discards;
1799 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1800 stats->rx_frame_errors + stats->rx_dropped;
1801
1802 stats->tx_window_errors = raw->tx_late_col;
1803 stats->tx_fifo_errors = raw->tx_discards;
1804 stats->tx_aborted_errors = raw->tx_exc_col;
1805 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1806 stats->tx_aborted_errors;
1807
1808 stats->multicast = raw->rx_mcast;
1809 stats->collisions = raw->tx_total_col;
1810
1811 pstats->tx_pause_frames = raw->tx_pause;
1812 pstats->rx_pause_frames = raw->rx_pause;
1813
1814 spin_unlock(lock: &mib->stats64_lock);
1815}
1816
1817static void ksz_get_stats64(struct dsa_switch *ds, int port,
1818 struct rtnl_link_stats64 *s)
1819{
1820 struct ksz_device *dev = ds->priv;
1821 struct ksz_port_mib *mib;
1822
1823 mib = &dev->ports[port].mib;
1824
1825 spin_lock(lock: &mib->stats64_lock);
1826 memcpy(s, &mib->stats64, sizeof(*s));
1827 spin_unlock(lock: &mib->stats64_lock);
1828}
1829
1830static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1831 struct ethtool_pause_stats *pause_stats)
1832{
1833 struct ksz_device *dev = ds->priv;
1834 struct ksz_port_mib *mib;
1835
1836 mib = &dev->ports[port].mib;
1837
1838 spin_lock(lock: &mib->stats64_lock);
1839 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1840 spin_unlock(lock: &mib->stats64_lock);
1841}
1842
1843static void ksz_get_strings(struct dsa_switch *ds, int port,
1844 u32 stringset, uint8_t *buf)
1845{
1846 struct ksz_device *dev = ds->priv;
1847 int i;
1848
1849 if (stringset != ETH_SS_STATS)
1850 return;
1851
1852 for (i = 0; i < dev->info->mib_cnt; i++) {
1853 memcpy(buf + i * ETH_GSTRING_LEN,
1854 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1855 }
1856}
1857
1858static void ksz_update_port_member(struct ksz_device *dev, int port)
1859{
1860 struct ksz_port *p = &dev->ports[port];
1861 struct dsa_switch *ds = dev->ds;
1862 u8 port_member = 0, cpu_port;
1863 const struct dsa_port *dp;
1864 int i, j;
1865
1866 if (!dsa_is_user_port(ds, p: port))
1867 return;
1868
1869 dp = dsa_to_port(ds, p: port);
1870 cpu_port = BIT(dsa_upstream_port(ds, port));
1871
1872 for (i = 0; i < ds->num_ports; i++) {
1873 const struct dsa_port *other_dp = dsa_to_port(ds, p: i);
1874 struct ksz_port *other_p = &dev->ports[i];
1875 u8 val = 0;
1876
1877 if (!dsa_is_user_port(ds, p: i))
1878 continue;
1879 if (port == i)
1880 continue;
1881 if (!dsa_port_bridge_same(a: dp, b: other_dp))
1882 continue;
1883 if (other_p->stp_state != BR_STATE_FORWARDING)
1884 continue;
1885
1886 if (p->stp_state == BR_STATE_FORWARDING) {
1887 val |= BIT(port);
1888 port_member |= BIT(i);
1889 }
1890
1891 /* Retain port [i]'s relationship to other ports than [port] */
1892 for (j = 0; j < ds->num_ports; j++) {
1893 const struct dsa_port *third_dp;
1894 struct ksz_port *third_p;
1895
1896 if (j == i)
1897 continue;
1898 if (j == port)
1899 continue;
1900 if (!dsa_is_user_port(ds, p: j))
1901 continue;
1902 third_p = &dev->ports[j];
1903 if (third_p->stp_state != BR_STATE_FORWARDING)
1904 continue;
1905 third_dp = dsa_to_port(ds, p: j);
1906 if (dsa_port_bridge_same(a: other_dp, b: third_dp))
1907 val |= BIT(j);
1908 }
1909
1910 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1911 }
1912
1913 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1914}
1915
1916static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1917{
1918 struct ksz_device *dev = bus->priv;
1919 u16 val;
1920 int ret;
1921
1922 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1923 if (ret < 0)
1924 return ret;
1925
1926 return val;
1927}
1928
1929static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1930 u16 val)
1931{
1932 struct ksz_device *dev = bus->priv;
1933
1934 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1935}
1936
1937static int ksz_irq_phy_setup(struct ksz_device *dev)
1938{
1939 struct dsa_switch *ds = dev->ds;
1940 int phy;
1941 int irq;
1942 int ret;
1943
1944 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1945 if (BIT(phy) & ds->phys_mii_mask) {
1946 irq = irq_find_mapping(domain: dev->ports[phy].pirq.domain,
1947 PORT_SRC_PHY_INT);
1948 if (irq < 0) {
1949 ret = irq;
1950 goto out;
1951 }
1952 ds->user_mii_bus->irq[phy] = irq;
1953 }
1954 }
1955 return 0;
1956out:
1957 while (phy--)
1958 if (BIT(phy) & ds->phys_mii_mask)
1959 irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
1960
1961 return ret;
1962}
1963
1964static void ksz_irq_phy_free(struct ksz_device *dev)
1965{
1966 struct dsa_switch *ds = dev->ds;
1967 int phy;
1968
1969 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1970 if (BIT(phy) & ds->phys_mii_mask)
1971 irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
1972}
1973
1974static int ksz_mdio_register(struct ksz_device *dev)
1975{
1976 struct dsa_switch *ds = dev->ds;
1977 struct device_node *mdio_np;
1978 struct mii_bus *bus;
1979 int ret;
1980
1981 mdio_np = of_get_child_by_name(node: dev->dev->of_node, name: "mdio");
1982 if (!mdio_np)
1983 return 0;
1984
1985 bus = devm_mdiobus_alloc(dev: ds->dev);
1986 if (!bus) {
1987 of_node_put(node: mdio_np);
1988 return -ENOMEM;
1989 }
1990
1991 bus->priv = dev;
1992 bus->read = ksz_sw_mdio_read;
1993 bus->write = ksz_sw_mdio_write;
1994 bus->name = "ksz user smi";
1995 snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d", ds->index);
1996 bus->parent = ds->dev;
1997 bus->phy_mask = ~ds->phys_mii_mask;
1998
1999 ds->user_mii_bus = bus;
2000
2001 if (dev->irq > 0) {
2002 ret = ksz_irq_phy_setup(dev);
2003 if (ret) {
2004 of_node_put(node: mdio_np);
2005 return ret;
2006 }
2007 }
2008
2009 ret = devm_of_mdiobus_register(dev: ds->dev, mdio: bus, np: mdio_np);
2010 if (ret) {
2011 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2012 bus->id);
2013 if (dev->irq > 0)
2014 ksz_irq_phy_free(dev);
2015 }
2016
2017 of_node_put(node: mdio_np);
2018
2019 return ret;
2020}
2021
2022static void ksz_irq_mask(struct irq_data *d)
2023{
2024 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2025
2026 kirq->masked |= BIT(d->hwirq);
2027}
2028
2029static void ksz_irq_unmask(struct irq_data *d)
2030{
2031 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2032
2033 kirq->masked &= ~BIT(d->hwirq);
2034}
2035
2036static void ksz_irq_bus_lock(struct irq_data *d)
2037{
2038 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2039
2040 mutex_lock(&kirq->dev->lock_irq);
2041}
2042
2043static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2044{
2045 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2046 struct ksz_device *dev = kirq->dev;
2047 int ret;
2048
2049 ret = ksz_write32(dev, reg: kirq->reg_mask, value: kirq->masked);
2050 if (ret)
2051 dev_err(dev->dev, "failed to change IRQ mask\n");
2052
2053 mutex_unlock(lock: &dev->lock_irq);
2054}
2055
2056static const struct irq_chip ksz_irq_chip = {
2057 .name = "ksz-irq",
2058 .irq_mask = ksz_irq_mask,
2059 .irq_unmask = ksz_irq_unmask,
2060 .irq_bus_lock = ksz_irq_bus_lock,
2061 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2062};
2063
2064static int ksz_irq_domain_map(struct irq_domain *d,
2065 unsigned int irq, irq_hw_number_t hwirq)
2066{
2067 irq_set_chip_data(irq, data: d->host_data);
2068 irq_set_chip_and_handler(irq, chip: &ksz_irq_chip, handle: handle_level_irq);
2069 irq_set_noprobe(irq);
2070
2071 return 0;
2072}
2073
2074static const struct irq_domain_ops ksz_irq_domain_ops = {
2075 .map = ksz_irq_domain_map,
2076 .xlate = irq_domain_xlate_twocell,
2077};
2078
2079static void ksz_irq_free(struct ksz_irq *kirq)
2080{
2081 int irq, virq;
2082
2083 free_irq(kirq->irq_num, kirq);
2084
2085 for (irq = 0; irq < kirq->nirqs; irq++) {
2086 virq = irq_find_mapping(domain: kirq->domain, hwirq: irq);
2087 irq_dispose_mapping(virq);
2088 }
2089
2090 irq_domain_remove(host: kirq->domain);
2091}
2092
2093static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2094{
2095 struct ksz_irq *kirq = dev_id;
2096 unsigned int nhandled = 0;
2097 struct ksz_device *dev;
2098 unsigned int sub_irq;
2099 u8 data;
2100 int ret;
2101 u8 n;
2102
2103 dev = kirq->dev;
2104
2105 /* Read interrupt status register */
2106 ret = ksz_read8(dev, reg: kirq->reg_status, val: &data);
2107 if (ret)
2108 goto out;
2109
2110 for (n = 0; n < kirq->nirqs; ++n) {
2111 if (data & BIT(n)) {
2112 sub_irq = irq_find_mapping(domain: kirq->domain, hwirq: n);
2113 handle_nested_irq(irq: sub_irq);
2114 ++nhandled;
2115 }
2116 }
2117out:
2118 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2119}
2120
2121static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2122{
2123 int ret, n;
2124
2125 kirq->dev = dev;
2126 kirq->masked = ~0;
2127
2128 kirq->domain = irq_domain_add_simple(of_node: dev->dev->of_node, size: kirq->nirqs, first_irq: 0,
2129 ops: &ksz_irq_domain_ops, host_data: kirq);
2130 if (!kirq->domain)
2131 return -ENOMEM;
2132
2133 for (n = 0; n < kirq->nirqs; n++)
2134 irq_create_mapping(host: kirq->domain, hwirq: n);
2135
2136 ret = request_threaded_irq(irq: kirq->irq_num, NULL, thread_fn: ksz_irq_thread_fn,
2137 IRQF_ONESHOT, name: kirq->name, dev: kirq);
2138 if (ret)
2139 goto out;
2140
2141 return 0;
2142
2143out:
2144 ksz_irq_free(kirq);
2145
2146 return ret;
2147}
2148
2149static int ksz_girq_setup(struct ksz_device *dev)
2150{
2151 struct ksz_irq *girq = &dev->girq;
2152
2153 girq->nirqs = dev->info->port_cnt;
2154 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2155 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2156 snprintf(buf: girq->name, size: sizeof(girq->name), fmt: "global_port_irq");
2157
2158 girq->irq_num = dev->irq;
2159
2160 return ksz_irq_common_setup(dev, kirq: girq);
2161}
2162
2163static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2164{
2165 struct ksz_irq *pirq = &dev->ports[p].pirq;
2166
2167 pirq->nirqs = dev->info->port_nirqs;
2168 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2169 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2170 snprintf(buf: pirq->name, size: sizeof(pirq->name), fmt: "port_irq-%d", p);
2171
2172 pirq->irq_num = irq_find_mapping(domain: dev->girq.domain, hwirq: p);
2173 if (pirq->irq_num < 0)
2174 return pirq->irq_num;
2175
2176 return ksz_irq_common_setup(dev, kirq: pirq);
2177}
2178
2179static int ksz_setup(struct dsa_switch *ds)
2180{
2181 struct ksz_device *dev = ds->priv;
2182 struct dsa_port *dp;
2183 struct ksz_port *p;
2184 const u16 *regs;
2185 int ret;
2186
2187 regs = dev->info->regs;
2188
2189 dev->vlan_cache = devm_kcalloc(dev: dev->dev, n: sizeof(struct vlan_table),
2190 size: dev->info->num_vlans, GFP_KERNEL);
2191 if (!dev->vlan_cache)
2192 return -ENOMEM;
2193
2194 ret = dev->dev_ops->reset(dev);
2195 if (ret) {
2196 dev_err(ds->dev, "failed to reset switch\n");
2197 return ret;
2198 }
2199
2200 /* set broadcast storm protection 10% rate */
2201 regmap_update_bits(map: ksz_regmap_16(dev), reg: regs[S_BROADCAST_CTRL],
2202 BROADCAST_STORM_RATE,
2203 val: (BROADCAST_STORM_VALUE *
2204 BROADCAST_STORM_PROT_RATE) / 100);
2205
2206 dev->dev_ops->config_cpu_port(ds);
2207
2208 dev->dev_ops->enable_stp_addr(dev);
2209
2210 ds->num_tx_queues = dev->info->num_tx_queues;
2211
2212 regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_MULTICAST_CTRL],
2213 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2214
2215 ksz_init_mib_timer(dev);
2216
2217 ds->configure_vlan_while_not_filtering = false;
2218
2219 if (dev->dev_ops->setup) {
2220 ret = dev->dev_ops->setup(ds);
2221 if (ret)
2222 return ret;
2223 }
2224
2225 /* Start with learning disabled on standalone user ports, and enabled
2226 * on the CPU port. In lack of other finer mechanisms, learning on the
2227 * CPU port will avoid flooding bridge local addresses on the network
2228 * in some cases.
2229 */
2230 p = &dev->ports[dev->cpu_port];
2231 p->learning = true;
2232
2233 if (dev->irq > 0) {
2234 ret = ksz_girq_setup(dev);
2235 if (ret)
2236 return ret;
2237
2238 dsa_switch_for_each_user_port(dp, dev->ds) {
2239 ret = ksz_pirq_setup(dev, p: dp->index);
2240 if (ret)
2241 goto out_girq;
2242
2243 ret = ksz_ptp_irq_setup(ds, p: dp->index);
2244 if (ret)
2245 goto out_pirq;
2246 }
2247 }
2248
2249 ret = ksz_ptp_clock_register(ds);
2250 if (ret) {
2251 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
2252 goto out_ptpirq;
2253 }
2254
2255 ret = ksz_mdio_register(dev);
2256 if (ret < 0) {
2257 dev_err(dev->dev, "failed to register the mdio");
2258 goto out_ptp_clock_unregister;
2259 }
2260
2261 /* start switch */
2262 regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_START_CTRL],
2263 SW_START, SW_START);
2264
2265 return 0;
2266
2267out_ptp_clock_unregister:
2268 ksz_ptp_clock_unregister(ds);
2269out_ptpirq:
2270 if (dev->irq > 0)
2271 dsa_switch_for_each_user_port(dp, dev->ds)
2272 ksz_ptp_irq_free(ds, p: dp->index);
2273out_pirq:
2274 if (dev->irq > 0)
2275 dsa_switch_for_each_user_port(dp, dev->ds)
2276 ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
2277out_girq:
2278 if (dev->irq > 0)
2279 ksz_irq_free(kirq: &dev->girq);
2280
2281 return ret;
2282}
2283
2284static void ksz_teardown(struct dsa_switch *ds)
2285{
2286 struct ksz_device *dev = ds->priv;
2287 struct dsa_port *dp;
2288
2289 ksz_ptp_clock_unregister(ds);
2290
2291 if (dev->irq > 0) {
2292 dsa_switch_for_each_user_port(dp, dev->ds) {
2293 ksz_ptp_irq_free(ds, p: dp->index);
2294
2295 ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
2296 }
2297
2298 ksz_irq_free(kirq: &dev->girq);
2299 }
2300
2301 if (dev->dev_ops->teardown)
2302 dev->dev_ops->teardown(ds);
2303}
2304
2305static void port_r_cnt(struct ksz_device *dev, int port)
2306{
2307 struct ksz_port_mib *mib = &dev->ports[port].mib;
2308 u64 *dropped;
2309
2310 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2311 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2312 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2313 &mib->counters[mib->cnt_ptr]);
2314 ++mib->cnt_ptr;
2315 }
2316
2317 /* last one in storage */
2318 dropped = &mib->counters[dev->info->mib_cnt];
2319
2320 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2321 while (mib->cnt_ptr < dev->info->mib_cnt) {
2322 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2323 dropped, &mib->counters[mib->cnt_ptr]);
2324 ++mib->cnt_ptr;
2325 }
2326 mib->cnt_ptr = 0;
2327}
2328
2329static void ksz_mib_read_work(struct work_struct *work)
2330{
2331 struct ksz_device *dev = container_of(work, struct ksz_device,
2332 mib_read.work);
2333 struct ksz_port_mib *mib;
2334 struct ksz_port *p;
2335 int i;
2336
2337 for (i = 0; i < dev->info->port_cnt; i++) {
2338 if (dsa_is_unused_port(ds: dev->ds, p: i))
2339 continue;
2340
2341 p = &dev->ports[i];
2342 mib = &p->mib;
2343 mutex_lock(&mib->cnt_mutex);
2344
2345 /* Only read MIB counters when the port is told to do.
2346 * If not, read only dropped counters when link is not up.
2347 */
2348 if (!p->read) {
2349 const struct dsa_port *dp = dsa_to_port(ds: dev->ds, p: i);
2350
2351 if (!netif_carrier_ok(dev: dp->user))
2352 mib->cnt_ptr = dev->info->reg_mib_cnt;
2353 }
2354 port_r_cnt(dev, port: i);
2355 p->read = false;
2356
2357 if (dev->dev_ops->r_mib_stat64)
2358 dev->dev_ops->r_mib_stat64(dev, i);
2359
2360 mutex_unlock(lock: &mib->cnt_mutex);
2361 }
2362
2363 schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval);
2364}
2365
2366void ksz_init_mib_timer(struct ksz_device *dev)
2367{
2368 int i;
2369
2370 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2371
2372 for (i = 0; i < dev->info->port_cnt; i++) {
2373 struct ksz_port_mib *mib = &dev->ports[i].mib;
2374
2375 dev->dev_ops->port_init_cnt(dev, i);
2376
2377 mib->cnt_ptr = 0;
2378 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2379 }
2380}
2381
2382static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2383{
2384 struct ksz_device *dev = ds->priv;
2385 u16 val = 0xffff;
2386 int ret;
2387
2388 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2389 if (ret)
2390 return ret;
2391
2392 return val;
2393}
2394
2395static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2396{
2397 struct ksz_device *dev = ds->priv;
2398 int ret;
2399
2400 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2401 if (ret)
2402 return ret;
2403
2404 return 0;
2405}
2406
2407static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2408{
2409 struct ksz_device *dev = ds->priv;
2410
2411 switch (dev->chip_id) {
2412 case KSZ8830_CHIP_ID:
2413 /* Silicon Errata Sheet (DS80000830A):
2414 * Port 1 does not work with LinkMD Cable-Testing.
2415 * Port 1 does not respond to received PAUSE control frames.
2416 */
2417 if (!port)
2418 return MICREL_KSZ8_P1_ERRATA;
2419 break;
2420 case KSZ9477_CHIP_ID:
2421 /* KSZ9477 Errata DS80000754C
2422 *
2423 * Module 4: Energy Efficient Ethernet (EEE) feature select must
2424 * be manually disabled
2425 * The EEE feature is enabled by default, but it is not fully
2426 * operational. It must be manually disabled through register
2427 * controls. If not disabled, the PHY ports can auto-negotiate
2428 * to enable EEE, and this feature can cause link drops when
2429 * linked to another device supporting EEE.
2430 */
2431 return MICREL_NO_EEE;
2432 }
2433
2434 return 0;
2435}
2436
2437static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2438 unsigned int mode, phy_interface_t interface)
2439{
2440 struct ksz_device *dev = ds->priv;
2441 struct ksz_port *p = &dev->ports[port];
2442
2443 /* Read all MIB counters when the link is going down. */
2444 p->read = true;
2445 /* timer started */
2446 if (dev->mib_read_interval)
2447 schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
2448}
2449
2450static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2451{
2452 struct ksz_device *dev = ds->priv;
2453
2454 if (sset != ETH_SS_STATS)
2455 return 0;
2456
2457 return dev->info->mib_cnt;
2458}
2459
2460static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2461 uint64_t *buf)
2462{
2463 const struct dsa_port *dp = dsa_to_port(ds, p: port);
2464 struct ksz_device *dev = ds->priv;
2465 struct ksz_port_mib *mib;
2466
2467 mib = &dev->ports[port].mib;
2468 mutex_lock(&mib->cnt_mutex);
2469
2470 /* Only read dropped counters if no link. */
2471 if (!netif_carrier_ok(dev: dp->user))
2472 mib->cnt_ptr = dev->info->reg_mib_cnt;
2473 port_r_cnt(dev, port);
2474 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2475 mutex_unlock(lock: &mib->cnt_mutex);
2476}
2477
2478static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2479 struct dsa_bridge bridge,
2480 bool *tx_fwd_offload,
2481 struct netlink_ext_ack *extack)
2482{
2483 /* port_stp_state_set() will be called after to put the port in
2484 * appropriate state so there is no need to do anything.
2485 */
2486
2487 return 0;
2488}
2489
2490static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2491 struct dsa_bridge bridge)
2492{
2493 /* port_stp_state_set() will be called after to put the port in
2494 * forwarding state so there is no need to do anything.
2495 */
2496}
2497
2498static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2499{
2500 struct ksz_device *dev = ds->priv;
2501
2502 dev->dev_ops->flush_dyn_mac_table(dev, port);
2503}
2504
2505static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2506{
2507 struct ksz_device *dev = ds->priv;
2508
2509 if (!dev->dev_ops->set_ageing_time)
2510 return -EOPNOTSUPP;
2511
2512 return dev->dev_ops->set_ageing_time(dev, msecs);
2513}
2514
2515static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2516 const unsigned char *addr, u16 vid,
2517 struct dsa_db db)
2518{
2519 struct ksz_device *dev = ds->priv;
2520
2521 if (!dev->dev_ops->fdb_add)
2522 return -EOPNOTSUPP;
2523
2524 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2525}
2526
2527static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2528 const unsigned char *addr,
2529 u16 vid, struct dsa_db db)
2530{
2531 struct ksz_device *dev = ds->priv;
2532
2533 if (!dev->dev_ops->fdb_del)
2534 return -EOPNOTSUPP;
2535
2536 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2537}
2538
2539static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2540 dsa_fdb_dump_cb_t *cb, void *data)
2541{
2542 struct ksz_device *dev = ds->priv;
2543
2544 if (!dev->dev_ops->fdb_dump)
2545 return -EOPNOTSUPP;
2546
2547 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2548}
2549
2550static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2551 const struct switchdev_obj_port_mdb *mdb,
2552 struct dsa_db db)
2553{
2554 struct ksz_device *dev = ds->priv;
2555
2556 if (!dev->dev_ops->mdb_add)
2557 return -EOPNOTSUPP;
2558
2559 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2560}
2561
2562static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2563 const struct switchdev_obj_port_mdb *mdb,
2564 struct dsa_db db)
2565{
2566 struct ksz_device *dev = ds->priv;
2567
2568 if (!dev->dev_ops->mdb_del)
2569 return -EOPNOTSUPP;
2570
2571 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2572}
2573
2574static int ksz_port_setup(struct dsa_switch *ds, int port)
2575{
2576 struct ksz_device *dev = ds->priv;
2577
2578 if (!dsa_is_user_port(ds, p: port))
2579 return 0;
2580
2581 /* setup user port */
2582 dev->dev_ops->port_setup(dev, port, false);
2583
2584 /* port_stp_state_set() will be called after to enable the port so
2585 * there is no need to do anything.
2586 */
2587
2588 return 0;
2589}
2590
2591void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2592{
2593 struct ksz_device *dev = ds->priv;
2594 struct ksz_port *p;
2595 const u16 *regs;
2596 u8 data;
2597
2598 regs = dev->info->regs;
2599
2600 ksz_pread8(dev, port, offset: regs[P_STP_CTRL], data: &data);
2601 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2602
2603 p = &dev->ports[port];
2604
2605 switch (state) {
2606 case BR_STATE_DISABLED:
2607 data |= PORT_LEARN_DISABLE;
2608 break;
2609 case BR_STATE_LISTENING:
2610 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2611 break;
2612 case BR_STATE_LEARNING:
2613 data |= PORT_RX_ENABLE;
2614 if (!p->learning)
2615 data |= PORT_LEARN_DISABLE;
2616 break;
2617 case BR_STATE_FORWARDING:
2618 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2619 if (!p->learning)
2620 data |= PORT_LEARN_DISABLE;
2621 break;
2622 case BR_STATE_BLOCKING:
2623 data |= PORT_LEARN_DISABLE;
2624 break;
2625 default:
2626 dev_err(ds->dev, "invalid STP state: %d\n", state);
2627 return;
2628 }
2629
2630 ksz_pwrite8(dev, port, offset: regs[P_STP_CTRL], data);
2631
2632 p->stp_state = state;
2633
2634 ksz_update_port_member(dev, port);
2635}
2636
2637static void ksz_port_teardown(struct dsa_switch *ds, int port)
2638{
2639 struct ksz_device *dev = ds->priv;
2640
2641 switch (dev->chip_id) {
2642 case KSZ8563_CHIP_ID:
2643 case KSZ9477_CHIP_ID:
2644 case KSZ9563_CHIP_ID:
2645 case KSZ9567_CHIP_ID:
2646 case KSZ9893_CHIP_ID:
2647 case KSZ9896_CHIP_ID:
2648 case KSZ9897_CHIP_ID:
2649 if (dsa_is_user_port(ds, p: port))
2650 ksz9477_port_acl_free(dev, port);
2651 }
2652}
2653
2654static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2655 struct switchdev_brport_flags flags,
2656 struct netlink_ext_ack *extack)
2657{
2658 if (flags.mask & ~BR_LEARNING)
2659 return -EINVAL;
2660
2661 return 0;
2662}
2663
2664static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2665 struct switchdev_brport_flags flags,
2666 struct netlink_ext_ack *extack)
2667{
2668 struct ksz_device *dev = ds->priv;
2669 struct ksz_port *p = &dev->ports[port];
2670
2671 if (flags.mask & BR_LEARNING) {
2672 p->learning = !!(flags.val & BR_LEARNING);
2673
2674 /* Make the change take effect immediately */
2675 ksz_port_stp_state_set(ds, port, state: p->stp_state);
2676 }
2677
2678 return 0;
2679}
2680
2681static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2682 int port,
2683 enum dsa_tag_protocol mp)
2684{
2685 struct ksz_device *dev = ds->priv;
2686 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2687
2688 if (dev->chip_id == KSZ8795_CHIP_ID ||
2689 dev->chip_id == KSZ8794_CHIP_ID ||
2690 dev->chip_id == KSZ8765_CHIP_ID)
2691 proto = DSA_TAG_PROTO_KSZ8795;
2692
2693 if (dev->chip_id == KSZ8830_CHIP_ID ||
2694 dev->chip_id == KSZ8563_CHIP_ID ||
2695 dev->chip_id == KSZ9893_CHIP_ID ||
2696 dev->chip_id == KSZ9563_CHIP_ID)
2697 proto = DSA_TAG_PROTO_KSZ9893;
2698
2699 if (dev->chip_id == KSZ9477_CHIP_ID ||
2700 dev->chip_id == KSZ9896_CHIP_ID ||
2701 dev->chip_id == KSZ9897_CHIP_ID ||
2702 dev->chip_id == KSZ9567_CHIP_ID)
2703 proto = DSA_TAG_PROTO_KSZ9477;
2704
2705 if (is_lan937x(dev))
2706 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2707
2708 return proto;
2709}
2710
2711static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2712 enum dsa_tag_protocol proto)
2713{
2714 struct ksz_tagger_data *tagger_data;
2715
2716 tagger_data = ksz_tagger_data(ds);
2717 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2718
2719 return 0;
2720}
2721
2722static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2723 bool flag, struct netlink_ext_ack *extack)
2724{
2725 struct ksz_device *dev = ds->priv;
2726
2727 if (!dev->dev_ops->vlan_filtering)
2728 return -EOPNOTSUPP;
2729
2730 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2731}
2732
2733static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2734 const struct switchdev_obj_port_vlan *vlan,
2735 struct netlink_ext_ack *extack)
2736{
2737 struct ksz_device *dev = ds->priv;
2738
2739 if (!dev->dev_ops->vlan_add)
2740 return -EOPNOTSUPP;
2741
2742 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2743}
2744
2745static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2746 const struct switchdev_obj_port_vlan *vlan)
2747{
2748 struct ksz_device *dev = ds->priv;
2749
2750 if (!dev->dev_ops->vlan_del)
2751 return -EOPNOTSUPP;
2752
2753 return dev->dev_ops->vlan_del(dev, port, vlan);
2754}
2755
2756static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2757 struct dsa_mall_mirror_tc_entry *mirror,
2758 bool ingress, struct netlink_ext_ack *extack)
2759{
2760 struct ksz_device *dev = ds->priv;
2761
2762 if (!dev->dev_ops->mirror_add)
2763 return -EOPNOTSUPP;
2764
2765 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2766}
2767
2768static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2769 struct dsa_mall_mirror_tc_entry *mirror)
2770{
2771 struct ksz_device *dev = ds->priv;
2772
2773 if (dev->dev_ops->mirror_del)
2774 dev->dev_ops->mirror_del(dev, port, mirror);
2775}
2776
2777static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2778{
2779 struct ksz_device *dev = ds->priv;
2780
2781 if (!dev->dev_ops->change_mtu)
2782 return -EOPNOTSUPP;
2783
2784 return dev->dev_ops->change_mtu(dev, port, mtu);
2785}
2786
2787static int ksz_max_mtu(struct dsa_switch *ds, int port)
2788{
2789 struct ksz_device *dev = ds->priv;
2790
2791 switch (dev->chip_id) {
2792 case KSZ8795_CHIP_ID:
2793 case KSZ8794_CHIP_ID:
2794 case KSZ8765_CHIP_ID:
2795 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2796 case KSZ8830_CHIP_ID:
2797 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2798 case KSZ8563_CHIP_ID:
2799 case KSZ9477_CHIP_ID:
2800 case KSZ9563_CHIP_ID:
2801 case KSZ9567_CHIP_ID:
2802 case KSZ9893_CHIP_ID:
2803 case KSZ9896_CHIP_ID:
2804 case KSZ9897_CHIP_ID:
2805 case LAN9370_CHIP_ID:
2806 case LAN9371_CHIP_ID:
2807 case LAN9372_CHIP_ID:
2808 case LAN9373_CHIP_ID:
2809 case LAN9374_CHIP_ID:
2810 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2811 }
2812
2813 return -EOPNOTSUPP;
2814}
2815
2816static int ksz_validate_eee(struct dsa_switch *ds, int port)
2817{
2818 struct ksz_device *dev = ds->priv;
2819
2820 if (!dev->info->internal_phy[port])
2821 return -EOPNOTSUPP;
2822
2823 switch (dev->chip_id) {
2824 case KSZ8563_CHIP_ID:
2825 case KSZ9477_CHIP_ID:
2826 case KSZ9563_CHIP_ID:
2827 case KSZ9567_CHIP_ID:
2828 case KSZ9893_CHIP_ID:
2829 case KSZ9896_CHIP_ID:
2830 case KSZ9897_CHIP_ID:
2831 return 0;
2832 }
2833
2834 return -EOPNOTSUPP;
2835}
2836
2837static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2838 struct ethtool_eee *e)
2839{
2840 int ret;
2841
2842 ret = ksz_validate_eee(ds, port);
2843 if (ret)
2844 return ret;
2845
2846 /* There is no documented control of Tx LPI configuration. */
2847 e->tx_lpi_enabled = true;
2848
2849 /* There is no documented control of Tx LPI timer. According to tests
2850 * Tx LPI timer seems to be set by default to minimal value.
2851 */
2852 e->tx_lpi_timer = 0;
2853
2854 return 0;
2855}
2856
2857static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2858 struct ethtool_eee *e)
2859{
2860 struct ksz_device *dev = ds->priv;
2861 int ret;
2862
2863 ret = ksz_validate_eee(ds, port);
2864 if (ret)
2865 return ret;
2866
2867 if (!e->tx_lpi_enabled) {
2868 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2869 return -EINVAL;
2870 }
2871
2872 if (e->tx_lpi_timer) {
2873 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2874 return -EINVAL;
2875 }
2876
2877 return 0;
2878}
2879
2880static void ksz_set_xmii(struct ksz_device *dev, int port,
2881 phy_interface_t interface)
2882{
2883 const u8 *bitval = dev->info->xmii_ctrl1;
2884 struct ksz_port *p = &dev->ports[port];
2885 const u16 *regs = dev->info->regs;
2886 u8 data8;
2887
2888 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
2889
2890 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2891 P_RGMII_ID_EG_ENABLE);
2892
2893 switch (interface) {
2894 case PHY_INTERFACE_MODE_MII:
2895 data8 |= bitval[P_MII_SEL];
2896 break;
2897 case PHY_INTERFACE_MODE_RMII:
2898 data8 |= bitval[P_RMII_SEL];
2899 break;
2900 case PHY_INTERFACE_MODE_GMII:
2901 data8 |= bitval[P_GMII_SEL];
2902 break;
2903 case PHY_INTERFACE_MODE_RGMII:
2904 case PHY_INTERFACE_MODE_RGMII_ID:
2905 case PHY_INTERFACE_MODE_RGMII_TXID:
2906 case PHY_INTERFACE_MODE_RGMII_RXID:
2907 data8 |= bitval[P_RGMII_SEL];
2908 /* On KSZ9893, disable RGMII in-band status support */
2909 if (dev->chip_id == KSZ9893_CHIP_ID ||
2910 dev->chip_id == KSZ8563_CHIP_ID ||
2911 dev->chip_id == KSZ9563_CHIP_ID)
2912 data8 &= ~P_MII_MAC_MODE;
2913 break;
2914 default:
2915 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2916 phy_modes(interface), port);
2917 return;
2918 }
2919
2920 if (p->rgmii_tx_val)
2921 data8 |= P_RGMII_ID_EG_ENABLE;
2922
2923 if (p->rgmii_rx_val)
2924 data8 |= P_RGMII_ID_IG_ENABLE;
2925
2926 /* Write the updated value */
2927 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
2928}
2929
2930phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2931{
2932 const u8 *bitval = dev->info->xmii_ctrl1;
2933 const u16 *regs = dev->info->regs;
2934 phy_interface_t interface;
2935 u8 data8;
2936 u8 val;
2937
2938 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
2939
2940 val = FIELD_GET(P_MII_SEL_M, data8);
2941
2942 if (val == bitval[P_MII_SEL]) {
2943 if (gbit)
2944 interface = PHY_INTERFACE_MODE_GMII;
2945 else
2946 interface = PHY_INTERFACE_MODE_MII;
2947 } else if (val == bitval[P_RMII_SEL]) {
2948 interface = PHY_INTERFACE_MODE_RGMII;
2949 } else {
2950 interface = PHY_INTERFACE_MODE_RGMII;
2951 if (data8 & P_RGMII_ID_EG_ENABLE)
2952 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2953 if (data8 & P_RGMII_ID_IG_ENABLE) {
2954 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2955 if (data8 & P_RGMII_ID_EG_ENABLE)
2956 interface = PHY_INTERFACE_MODE_RGMII_ID;
2957 }
2958 }
2959
2960 return interface;
2961}
2962
2963static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2964 unsigned int mode,
2965 const struct phylink_link_state *state)
2966{
2967 struct ksz_device *dev = ds->priv;
2968
2969 if (ksz_is_ksz88x3(dev))
2970 return;
2971
2972 /* Internal PHYs */
2973 if (dev->info->internal_phy[port])
2974 return;
2975
2976 if (phylink_autoneg_inband(mode)) {
2977 dev_err(dev->dev, "In-band AN not supported!\n");
2978 return;
2979 }
2980
2981 ksz_set_xmii(dev, port, interface: state->interface);
2982
2983 if (dev->dev_ops->phylink_mac_config)
2984 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2985
2986 if (dev->dev_ops->setup_rgmii_delay)
2987 dev->dev_ops->setup_rgmii_delay(dev, port);
2988}
2989
2990bool ksz_get_gbit(struct ksz_device *dev, int port)
2991{
2992 const u8 *bitval = dev->info->xmii_ctrl1;
2993 const u16 *regs = dev->info->regs;
2994 bool gbit = false;
2995 u8 data8;
2996 bool val;
2997
2998 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
2999
3000 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3001
3002 if (val == bitval[P_GMII_1GBIT])
3003 gbit = true;
3004
3005 return gbit;
3006}
3007
3008static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3009{
3010 const u8 *bitval = dev->info->xmii_ctrl1;
3011 const u16 *regs = dev->info->regs;
3012 u8 data8;
3013
3014 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3015
3016 data8 &= ~P_GMII_1GBIT_M;
3017
3018 if (gbit)
3019 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3020 else
3021 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3022
3023 /* Write the updated value */
3024 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
3025}
3026
3027static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3028{
3029 const u8 *bitval = dev->info->xmii_ctrl0;
3030 const u16 *regs = dev->info->regs;
3031 u8 data8;
3032
3033 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_0], data: &data8);
3034
3035 data8 &= ~P_MII_100MBIT_M;
3036
3037 if (speed == SPEED_100)
3038 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3039 else
3040 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3041
3042 /* Write the updated value */
3043 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_0], data: data8);
3044}
3045
3046static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3047{
3048 if (speed == SPEED_1000)
3049 ksz_set_gbit(dev, port, gbit: true);
3050 else
3051 ksz_set_gbit(dev, port, gbit: false);
3052
3053 if (speed == SPEED_100 || speed == SPEED_10)
3054 ksz_set_100_10mbit(dev, port, speed);
3055}
3056
3057static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3058 bool tx_pause, bool rx_pause)
3059{
3060 const u8 *bitval = dev->info->xmii_ctrl0;
3061 const u32 *masks = dev->info->masks;
3062 const u16 *regs = dev->info->regs;
3063 u8 mask;
3064 u8 val;
3065
3066 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3067 masks[P_MII_RX_FLOW_CTRL];
3068
3069 if (duplex == DUPLEX_FULL)
3070 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3071 else
3072 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3073
3074 if (tx_pause)
3075 val |= masks[P_MII_TX_FLOW_CTRL];
3076
3077 if (rx_pause)
3078 val |= masks[P_MII_RX_FLOW_CTRL];
3079
3080 ksz_prmw8(dev, port, offset: regs[P_XMII_CTRL_0], mask, val);
3081}
3082
3083static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
3084 unsigned int mode,
3085 phy_interface_t interface,
3086 struct phy_device *phydev, int speed,
3087 int duplex, bool tx_pause,
3088 bool rx_pause)
3089{
3090 struct ksz_port *p;
3091
3092 p = &dev->ports[port];
3093
3094 /* Internal PHYs */
3095 if (dev->info->internal_phy[port])
3096 return;
3097
3098 p->phydev.speed = speed;
3099
3100 ksz_port_set_xmii_speed(dev, port, speed);
3101
3102 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3103}
3104
3105static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
3106 unsigned int mode,
3107 phy_interface_t interface,
3108 struct phy_device *phydev, int speed,
3109 int duplex, bool tx_pause, bool rx_pause)
3110{
3111 struct ksz_device *dev = ds->priv;
3112
3113 if (dev->dev_ops->phylink_mac_link_up)
3114 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
3115 phydev, speed, duplex,
3116 tx_pause, rx_pause);
3117}
3118
3119static int ksz_switch_detect(struct ksz_device *dev)
3120{
3121 u8 id1, id2, id4;
3122 u16 id16;
3123 u32 id32;
3124 int ret;
3125
3126 /* read chip id */
3127 ret = ksz_read16(dev, REG_CHIP_ID0, val: &id16);
3128 if (ret)
3129 return ret;
3130
3131 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3132 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3133
3134 switch (id1) {
3135 case KSZ87_FAMILY_ID:
3136 if (id2 == KSZ87_CHIP_ID_95) {
3137 u8 val;
3138
3139 dev->chip_id = KSZ8795_CHIP_ID;
3140
3141 ksz_read8(dev, KSZ8_PORT_STATUS_0, val: &val);
3142 if (val & KSZ8_PORT_FIBER_MODE)
3143 dev->chip_id = KSZ8765_CHIP_ID;
3144 } else if (id2 == KSZ87_CHIP_ID_94) {
3145 dev->chip_id = KSZ8794_CHIP_ID;
3146 } else {
3147 return -ENODEV;
3148 }
3149 break;
3150 case KSZ88_FAMILY_ID:
3151 if (id2 == KSZ88_CHIP_ID_63)
3152 dev->chip_id = KSZ8830_CHIP_ID;
3153 else
3154 return -ENODEV;
3155 break;
3156 default:
3157 ret = ksz_read32(dev, REG_CHIP_ID0, val: &id32);
3158 if (ret)
3159 return ret;
3160
3161 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3162 id32 &= ~0xFF;
3163
3164 switch (id32) {
3165 case KSZ9477_CHIP_ID:
3166 case KSZ9896_CHIP_ID:
3167 case KSZ9897_CHIP_ID:
3168 case KSZ9567_CHIP_ID:
3169 case LAN9370_CHIP_ID:
3170 case LAN9371_CHIP_ID:
3171 case LAN9372_CHIP_ID:
3172 case LAN9373_CHIP_ID:
3173 case LAN9374_CHIP_ID:
3174 dev->chip_id = id32;
3175 break;
3176 case KSZ9893_CHIP_ID:
3177 ret = ksz_read8(dev, REG_CHIP_ID4,
3178 val: &id4);
3179 if (ret)
3180 return ret;
3181
3182 if (id4 == SKU_ID_KSZ8563)
3183 dev->chip_id = KSZ8563_CHIP_ID;
3184 else if (id4 == SKU_ID_KSZ9563)
3185 dev->chip_id = KSZ9563_CHIP_ID;
3186 else
3187 dev->chip_id = KSZ9893_CHIP_ID;
3188
3189 break;
3190 default:
3191 dev_err(dev->dev,
3192 "unsupported switch detected %x)\n", id32);
3193 return -ENODEV;
3194 }
3195 }
3196 return 0;
3197}
3198
3199static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3200 struct flow_cls_offload *cls, bool ingress)
3201{
3202 struct ksz_device *dev = ds->priv;
3203
3204 switch (dev->chip_id) {
3205 case KSZ8563_CHIP_ID:
3206 case KSZ9477_CHIP_ID:
3207 case KSZ9563_CHIP_ID:
3208 case KSZ9567_CHIP_ID:
3209 case KSZ9893_CHIP_ID:
3210 case KSZ9896_CHIP_ID:
3211 case KSZ9897_CHIP_ID:
3212 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3213 }
3214
3215 return -EOPNOTSUPP;
3216}
3217
3218static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3219 struct flow_cls_offload *cls, bool ingress)
3220{
3221 struct ksz_device *dev = ds->priv;
3222
3223 switch (dev->chip_id) {
3224 case KSZ8563_CHIP_ID:
3225 case KSZ9477_CHIP_ID:
3226 case KSZ9563_CHIP_ID:
3227 case KSZ9567_CHIP_ID:
3228 case KSZ9893_CHIP_ID:
3229 case KSZ9896_CHIP_ID:
3230 case KSZ9897_CHIP_ID:
3231 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3232 }
3233
3234 return -EOPNOTSUPP;
3235}
3236
3237/* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3238 * is converted to Hex-decimal using the successive multiplication method. On
3239 * every step, integer part is taken and decimal part is carry forwarded.
3240 */
3241static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3242{
3243 u32 cinc = 0;
3244 u32 txrate;
3245 u32 rate;
3246 u8 temp;
3247 u8 i;
3248
3249 txrate = idle_slope - send_slope;
3250
3251 if (!txrate)
3252 return -EINVAL;
3253
3254 rate = idle_slope;
3255
3256 /* 24 bit register */
3257 for (i = 0; i < 6; i++) {
3258 rate = rate * 16;
3259
3260 temp = rate / txrate;
3261
3262 rate %= txrate;
3263
3264 cinc = ((cinc << 4) | temp);
3265 }
3266
3267 *bw = cinc;
3268
3269 return 0;
3270}
3271
3272static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3273 u8 shaper)
3274{
3275 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3276 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3277 FIELD_PREP(MTI_SHAPING_M, shaper));
3278}
3279
3280static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3281 struct tc_cbs_qopt_offload *qopt)
3282{
3283 struct ksz_device *dev = ds->priv;
3284 int ret;
3285 u32 bw;
3286
3287 if (!dev->info->tc_cbs_supported)
3288 return -EOPNOTSUPP;
3289
3290 if (qopt->queue > dev->info->num_tx_queues)
3291 return -EINVAL;
3292
3293 /* Queue Selection */
3294 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: qopt->queue);
3295 if (ret)
3296 return ret;
3297
3298 if (!qopt->enable)
3299 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3300 MTI_SHAPING_OFF);
3301
3302 /* High Credit */
3303 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3304 data: qopt->hicredit);
3305 if (ret)
3306 return ret;
3307
3308 /* Low Credit */
3309 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3310 data: qopt->locredit);
3311 if (ret)
3312 return ret;
3313
3314 /* Credit Increment Register */
3315 ret = cinc_cal(idle_slope: qopt->idleslope, send_slope: qopt->sendslope, bw: &bw);
3316 if (ret)
3317 return ret;
3318
3319 if (dev->dev_ops->tc_cbs_set_cinc) {
3320 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3321 if (ret)
3322 return ret;
3323 }
3324
3325 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3326 MTI_SHAPING_SRP);
3327}
3328
3329static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3330{
3331 int queue, ret;
3332
3333 /* Configuration will not take effect until the last Port Queue X
3334 * Egress Limit Control Register is written.
3335 */
3336 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3337 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3338 KSZ9477_OUT_RATE_NO_LIMIT);
3339 if (ret)
3340 return ret;
3341 }
3342
3343 return 0;
3344}
3345
3346static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3347 int band)
3348{
3349 /* Compared to queues, bands prioritize packets differently. In strict
3350 * priority mode, the lowest priority is assigned to Queue 0 while the
3351 * highest priority is given to Band 0.
3352 */
3353 return p->bands - 1 - band;
3354}
3355
3356static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3357{
3358 int ret;
3359
3360 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
3361 if (ret)
3362 return ret;
3363
3364 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3365 MTI_SHAPING_OFF);
3366}
3367
3368static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3369 int weight)
3370{
3371 int ret;
3372
3373 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
3374 if (ret)
3375 return ret;
3376
3377 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3378 MTI_SHAPING_OFF);
3379 if (ret)
3380 return ret;
3381
3382 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, data: weight);
3383}
3384
3385static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3386 struct tc_ets_qopt_offload_replace_params *p)
3387{
3388 int ret, band, tc_prio;
3389 u32 queue_map = 0;
3390
3391 /* In order to ensure proper prioritization, it is necessary to set the
3392 * rate limit for the related queue to zero. Otherwise strict priority
3393 * or WRR mode will not work. This is a hardware limitation.
3394 */
3395 ret = ksz_disable_egress_rate_limit(dev, port);
3396 if (ret)
3397 return ret;
3398
3399 /* Configure queue scheduling mode for all bands. Currently only strict
3400 * prio mode is supported.
3401 */
3402 for (band = 0; band < p->bands; band++) {
3403 int queue = ksz_ets_band_to_queue(p, band);
3404
3405 ret = ksz_queue_set_strict(dev, port, queue);
3406 if (ret)
3407 return ret;
3408 }
3409
3410 /* Configure the mapping between traffic classes and queues. Note:
3411 * priomap variable support 16 traffic classes, but the chip can handle
3412 * only 8 classes.
3413 */
3414 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3415 int queue;
3416
3417 if (tc_prio > KSZ9477_MAX_TC_PRIO)
3418 break;
3419
3420 queue = ksz_ets_band_to_queue(p, band: p->priomap[tc_prio]);
3421 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3422 }
3423
3424 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
3425}
3426
3427static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3428{
3429 int ret, queue, tc_prio, s;
3430 u32 queue_map = 0;
3431
3432 /* To restore the default chip configuration, set all queues to use the
3433 * WRR scheduler with a weight of 1.
3434 */
3435 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3436 ret = ksz_queue_set_wrr(dev, port, queue,
3437 KSZ9477_DEFAULT_WRR_WEIGHT);
3438 if (ret)
3439 return ret;
3440 }
3441
3442 switch (dev->info->num_tx_queues) {
3443 case 2:
3444 s = 2;
3445 break;
3446 case 4:
3447 s = 1;
3448 break;
3449 case 8:
3450 s = 0;
3451 break;
3452 default:
3453 return -EINVAL;
3454 }
3455
3456 /* Revert the queue mapping for TC-priority to its default setting on
3457 * the chip.
3458 */
3459 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3460 int queue;
3461
3462 queue = tc_prio >> s;
3463 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3464 }
3465
3466 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
3467}
3468
3469static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3470 struct tc_ets_qopt_offload_replace_params *p)
3471{
3472 int band;
3473
3474 /* Since it is not feasible to share one port among multiple qdisc,
3475 * the user must configure all available queues appropriately.
3476 */
3477 if (p->bands != dev->info->num_tx_queues) {
3478 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3479 dev->info->num_tx_queues);
3480 return -EOPNOTSUPP;
3481 }
3482
3483 for (band = 0; band < p->bands; ++band) {
3484 /* The KSZ switches utilize a weighted round robin configuration
3485 * where a certain number of packets can be transmitted from a
3486 * queue before the next queue is serviced. For more information
3487 * on this, refer to section 5.2.8.4 of the KSZ8565R
3488 * documentation on the Port Transmit Queue Control 1 Register.
3489 * However, the current ETS Qdisc implementation (as of February
3490 * 2023) assigns a weight to each queue based on the number of
3491 * bytes or extrapolated bandwidth in percentages. Since this
3492 * differs from the KSZ switches' method and we don't want to
3493 * fake support by converting bytes to packets, it is better to
3494 * return an error instead.
3495 */
3496 if (p->quanta[band]) {
3497 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3498 return -EOPNOTSUPP;
3499 }
3500 }
3501
3502 return 0;
3503}
3504
3505static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3506 struct tc_ets_qopt_offload *qopt)
3507{
3508 struct ksz_device *dev = ds->priv;
3509 int ret;
3510
3511 if (!dev->info->tc_ets_supported)
3512 return -EOPNOTSUPP;
3513
3514 if (qopt->parent != TC_H_ROOT) {
3515 dev_err(dev->dev, "Parent should be \"root\"\n");
3516 return -EOPNOTSUPP;
3517 }
3518
3519 switch (qopt->command) {
3520 case TC_ETS_REPLACE:
3521 ret = ksz_tc_ets_validate(dev, port, p: &qopt->replace_params);
3522 if (ret)
3523 return ret;
3524
3525 return ksz_tc_ets_add(dev, port, p: &qopt->replace_params);
3526 case TC_ETS_DESTROY:
3527 return ksz_tc_ets_del(dev, port);
3528 case TC_ETS_STATS:
3529 case TC_ETS_GRAFT:
3530 return -EOPNOTSUPP;
3531 }
3532
3533 return -EOPNOTSUPP;
3534}
3535
3536static int ksz_setup_tc(struct dsa_switch *ds, int port,
3537 enum tc_setup_type type, void *type_data)
3538{
3539 switch (type) {
3540 case TC_SETUP_QDISC_CBS:
3541 return ksz_setup_tc_cbs(ds, port, qopt: type_data);
3542 case TC_SETUP_QDISC_ETS:
3543 return ksz_tc_setup_qdisc_ets(ds, port, qopt: type_data);
3544 default:
3545 return -EOPNOTSUPP;
3546 }
3547}
3548
3549static void ksz_get_wol(struct dsa_switch *ds, int port,
3550 struct ethtool_wolinfo *wol)
3551{
3552 struct ksz_device *dev = ds->priv;
3553
3554 if (dev->dev_ops->get_wol)
3555 dev->dev_ops->get_wol(dev, port, wol);
3556}
3557
3558static int ksz_set_wol(struct dsa_switch *ds, int port,
3559 struct ethtool_wolinfo *wol)
3560{
3561 struct ksz_device *dev = ds->priv;
3562
3563 if (dev->dev_ops->set_wol)
3564 return dev->dev_ops->set_wol(dev, port, wol);
3565
3566 return -EOPNOTSUPP;
3567}
3568
3569static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
3570 const unsigned char *addr)
3571{
3572 struct dsa_port *dp = dsa_to_port(ds, p: port);
3573 struct ethtool_wolinfo wol;
3574
3575 if (dp->hsr_dev) {
3576 dev_err(ds->dev,
3577 "Cannot change MAC address on port %d with active HSR offload\n",
3578 port);
3579 return -EBUSY;
3580 }
3581
3582 ksz_get_wol(ds, port: dp->index, wol: &wol);
3583 if (wol.wolopts & WAKE_MAGIC) {
3584 dev_err(ds->dev,
3585 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
3586 port);
3587 return -EBUSY;
3588 }
3589
3590 return 0;
3591}
3592
3593/**
3594 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
3595 * can be used as a global address.
3596 * @ds: Pointer to the DSA switch structure.
3597 * @port: The port number on which the MAC address is to be checked.
3598 *
3599 * This function examines the MAC address set on the specified port and
3600 * determines if it can be used as a global address for the switch.
3601 *
3602 * Return: true if the port's MAC address can be used as a global address, false
3603 * otherwise.
3604 */
3605bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
3606{
3607 struct net_device *user = dsa_to_port(ds, p: port)->user;
3608 const unsigned char *addr = user->dev_addr;
3609 struct ksz_switch_macaddr *switch_macaddr;
3610 struct ksz_device *dev = ds->priv;
3611
3612 ASSERT_RTNL();
3613
3614 switch_macaddr = dev->switch_macaddr;
3615 if (switch_macaddr && !ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr))
3616 return false;
3617
3618 return true;
3619}
3620
3621/**
3622 * ksz_switch_macaddr_get - Program the switch's MAC address register.
3623 * @ds: DSA switch instance.
3624 * @port: Port number.
3625 * @extack: Netlink extended acknowledgment.
3626 *
3627 * This function programs the switch's MAC address register with the MAC address
3628 * of the requesting user port. This single address is used by the switch for
3629 * multiple features like HSR self-address filtering and WoL. Other user ports
3630 * can share ownership of this address as long as their MAC address is the same.
3631 * The MAC addresses of user ports must not change while they have ownership of
3632 * the switch MAC address.
3633 *
3634 * Return: 0 on success, or other error codes on failure.
3635 */
3636int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
3637 struct netlink_ext_ack *extack)
3638{
3639 struct net_device *user = dsa_to_port(ds, p: port)->user;
3640 const unsigned char *addr = user->dev_addr;
3641 struct ksz_switch_macaddr *switch_macaddr;
3642 struct ksz_device *dev = ds->priv;
3643 const u16 *regs = dev->info->regs;
3644 int i, ret;
3645
3646 /* Make sure concurrent MAC address changes are blocked */
3647 ASSERT_RTNL();
3648
3649 switch_macaddr = dev->switch_macaddr;
3650 if (switch_macaddr) {
3651 if (!ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr)) {
3652 NL_SET_ERR_MSG_FMT_MOD(extack,
3653 "Switch already configured for MAC address %pM",
3654 switch_macaddr->addr);
3655 return -EBUSY;
3656 }
3657
3658 refcount_inc(r: &switch_macaddr->refcount);
3659 return 0;
3660 }
3661
3662 switch_macaddr = kzalloc(size: sizeof(*switch_macaddr), GFP_KERNEL);
3663 if (!switch_macaddr)
3664 return -ENOMEM;
3665
3666 ether_addr_copy(dst: switch_macaddr->addr, src: addr);
3667 refcount_set(r: &switch_macaddr->refcount, n: 1);
3668 dev->switch_macaddr = switch_macaddr;
3669
3670 /* Program the switch MAC address to hardware */
3671 for (i = 0; i < ETH_ALEN; i++) {
3672 ret = ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: addr[i]);
3673 if (ret)
3674 goto macaddr_drop;
3675 }
3676
3677 return 0;
3678
3679macaddr_drop:
3680 dev->switch_macaddr = NULL;
3681 refcount_set(r: &switch_macaddr->refcount, n: 0);
3682 kfree(objp: switch_macaddr);
3683
3684 return ret;
3685}
3686
3687void ksz_switch_macaddr_put(struct dsa_switch *ds)
3688{
3689 struct ksz_switch_macaddr *switch_macaddr;
3690 struct ksz_device *dev = ds->priv;
3691 const u16 *regs = dev->info->regs;
3692 int i;
3693
3694 /* Make sure concurrent MAC address changes are blocked */
3695 ASSERT_RTNL();
3696
3697 switch_macaddr = dev->switch_macaddr;
3698 if (!refcount_dec_and_test(r: &switch_macaddr->refcount))
3699 return;
3700
3701 for (i = 0; i < ETH_ALEN; i++)
3702 ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: 0);
3703
3704 dev->switch_macaddr = NULL;
3705 kfree(objp: switch_macaddr);
3706}
3707
3708static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
3709 struct netlink_ext_ack *extack)
3710{
3711 struct ksz_device *dev = ds->priv;
3712 enum hsr_version ver;
3713 int ret;
3714
3715 ret = hsr_get_version(dev: hsr, ver: &ver);
3716 if (ret)
3717 return ret;
3718
3719 if (dev->chip_id != KSZ9477_CHIP_ID) {
3720 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
3721 return -EOPNOTSUPP;
3722 }
3723
3724 /* KSZ9477 can support HW offloading of only 1 HSR device */
3725 if (dev->hsr_dev && hsr != dev->hsr_dev) {
3726 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
3727 return -EOPNOTSUPP;
3728 }
3729
3730 /* KSZ9477 only supports HSR v0 and v1 */
3731 if (!(ver == HSR_V0 || ver == HSR_V1)) {
3732 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
3733 return -EOPNOTSUPP;
3734 }
3735
3736 /* Self MAC address filtering, to avoid frames traversing
3737 * the HSR ring more than once.
3738 */
3739 ret = ksz_switch_macaddr_get(ds, port, extack);
3740 if (ret)
3741 return ret;
3742
3743 ksz9477_hsr_join(ds, port, hsr);
3744 dev->hsr_dev = hsr;
3745 dev->hsr_ports |= BIT(port);
3746
3747 return 0;
3748}
3749
3750static int ksz_hsr_leave(struct dsa_switch *ds, int port,
3751 struct net_device *hsr)
3752{
3753 struct ksz_device *dev = ds->priv;
3754
3755 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
3756
3757 ksz9477_hsr_leave(ds, port, hsr);
3758 dev->hsr_ports &= ~BIT(port);
3759 if (!dev->hsr_ports)
3760 dev->hsr_dev = NULL;
3761
3762 ksz_switch_macaddr_put(ds);
3763
3764 return 0;
3765}
3766
3767static const struct dsa_switch_ops ksz_switch_ops = {
3768 .get_tag_protocol = ksz_get_tag_protocol,
3769 .connect_tag_protocol = ksz_connect_tag_protocol,
3770 .get_phy_flags = ksz_get_phy_flags,
3771 .setup = ksz_setup,
3772 .teardown = ksz_teardown,
3773 .phy_read = ksz_phy_read16,
3774 .phy_write = ksz_phy_write16,
3775 .phylink_get_caps = ksz_phylink_get_caps,
3776 .phylink_mac_config = ksz_phylink_mac_config,
3777 .phylink_mac_link_up = ksz_phylink_mac_link_up,
3778 .phylink_mac_link_down = ksz_mac_link_down,
3779 .port_setup = ksz_port_setup,
3780 .set_ageing_time = ksz_set_ageing_time,
3781 .get_strings = ksz_get_strings,
3782 .get_ethtool_stats = ksz_get_ethtool_stats,
3783 .get_sset_count = ksz_sset_count,
3784 .port_bridge_join = ksz_port_bridge_join,
3785 .port_bridge_leave = ksz_port_bridge_leave,
3786 .port_hsr_join = ksz_hsr_join,
3787 .port_hsr_leave = ksz_hsr_leave,
3788 .port_set_mac_address = ksz_port_set_mac_address,
3789 .port_stp_state_set = ksz_port_stp_state_set,
3790 .port_teardown = ksz_port_teardown,
3791 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3792 .port_bridge_flags = ksz_port_bridge_flags,
3793 .port_fast_age = ksz_port_fast_age,
3794 .port_vlan_filtering = ksz_port_vlan_filtering,
3795 .port_vlan_add = ksz_port_vlan_add,
3796 .port_vlan_del = ksz_port_vlan_del,
3797 .port_fdb_dump = ksz_port_fdb_dump,
3798 .port_fdb_add = ksz_port_fdb_add,
3799 .port_fdb_del = ksz_port_fdb_del,
3800 .port_mdb_add = ksz_port_mdb_add,
3801 .port_mdb_del = ksz_port_mdb_del,
3802 .port_mirror_add = ksz_port_mirror_add,
3803 .port_mirror_del = ksz_port_mirror_del,
3804 .get_stats64 = ksz_get_stats64,
3805 .get_pause_stats = ksz_get_pause_stats,
3806 .port_change_mtu = ksz_change_mtu,
3807 .port_max_mtu = ksz_max_mtu,
3808 .get_wol = ksz_get_wol,
3809 .set_wol = ksz_set_wol,
3810 .get_ts_info = ksz_get_ts_info,
3811 .port_hwtstamp_get = ksz_hwtstamp_get,
3812 .port_hwtstamp_set = ksz_hwtstamp_set,
3813 .port_txtstamp = ksz_port_txtstamp,
3814 .port_rxtstamp = ksz_port_rxtstamp,
3815 .cls_flower_add = ksz_cls_flower_add,
3816 .cls_flower_del = ksz_cls_flower_del,
3817 .port_setup_tc = ksz_setup_tc,
3818 .get_mac_eee = ksz_get_mac_eee,
3819 .set_mac_eee = ksz_set_mac_eee,
3820};
3821
3822struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
3823{
3824 struct dsa_switch *ds;
3825 struct ksz_device *swdev;
3826
3827 ds = devm_kzalloc(dev: base, size: sizeof(*ds), GFP_KERNEL);
3828 if (!ds)
3829 return NULL;
3830
3831 ds->dev = base;
3832 ds->num_ports = DSA_MAX_PORTS;
3833 ds->ops = &ksz_switch_ops;
3834
3835 swdev = devm_kzalloc(dev: base, size: sizeof(*swdev), GFP_KERNEL);
3836 if (!swdev)
3837 return NULL;
3838
3839 ds->priv = swdev;
3840 swdev->dev = base;
3841
3842 swdev->ds = ds;
3843 swdev->priv = priv;
3844
3845 return swdev;
3846}
3847EXPORT_SYMBOL(ksz_switch_alloc);
3848
3849/**
3850 * ksz_switch_shutdown - Shutdown routine for the switch device.
3851 * @dev: The switch device structure.
3852 *
3853 * This function is responsible for initiating a shutdown sequence for the
3854 * switch device. It invokes the reset operation defined in the device
3855 * operations, if available, to reset the switch. Subsequently, it calls the
3856 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
3857 * switch.
3858 */
3859void ksz_switch_shutdown(struct ksz_device *dev)
3860{
3861 bool wol_enabled = false;
3862
3863 if (dev->dev_ops->wol_pre_shutdown)
3864 dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled);
3865
3866 if (dev->dev_ops->reset && !wol_enabled)
3867 dev->dev_ops->reset(dev);
3868
3869 dsa_switch_shutdown(ds: dev->ds);
3870}
3871EXPORT_SYMBOL(ksz_switch_shutdown);
3872
3873static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3874 struct device_node *port_dn)
3875{
3876 phy_interface_t phy_mode = dev->ports[port_num].interface;
3877 int rx_delay = -1, tx_delay = -1;
3878
3879 if (!phy_interface_mode_is_rgmii(mode: phy_mode))
3880 return;
3881
3882 of_property_read_u32(np: port_dn, propname: "rx-internal-delay-ps", out_value: &rx_delay);
3883 of_property_read_u32(np: port_dn, propname: "tx-internal-delay-ps", out_value: &tx_delay);
3884
3885 if (rx_delay == -1 && tx_delay == -1) {
3886 dev_warn(dev->dev,
3887 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3888 "please update device tree to specify \"rx-internal-delay-ps\" and "
3889 "\"tx-internal-delay-ps\"",
3890 port_num);
3891
3892 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3893 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3894 rx_delay = 2000;
3895
3896 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3897 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3898 tx_delay = 2000;
3899 }
3900
3901 if (rx_delay < 0)
3902 rx_delay = 0;
3903 if (tx_delay < 0)
3904 tx_delay = 0;
3905
3906 dev->ports[port_num].rgmii_rx_val = rx_delay;
3907 dev->ports[port_num].rgmii_tx_val = tx_delay;
3908}
3909
3910/**
3911 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
3912 * register value.
3913 * @array: The array of drive strength values to search.
3914 * @array_size: The size of the array.
3915 * @microamp: The drive strength value in microamp to be converted.
3916 *
3917 * This function searches the array of drive strength values for the given
3918 * microamp value and returns the corresponding register value for that drive.
3919 *
3920 * Returns: If found, the corresponding register value for that drive strength
3921 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
3922 */
3923static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
3924 size_t array_size, int microamp)
3925{
3926 int i;
3927
3928 for (i = 0; i < array_size; i++) {
3929 if (array[i].microamp == microamp)
3930 return array[i].reg_val;
3931 }
3932
3933 return -EINVAL;
3934}
3935
3936/**
3937 * ksz_drive_strength_error() - Report invalid drive strength value
3938 * @dev: ksz device
3939 * @array: The array of drive strength values to search.
3940 * @array_size: The size of the array.
3941 * @microamp: Invalid drive strength value in microamp
3942 *
3943 * This function logs an error message when an unsupported drive strength value
3944 * is detected. It lists out all the supported drive strength values for
3945 * reference in the error message.
3946 */
3947static void ksz_drive_strength_error(struct ksz_device *dev,
3948 const struct ksz_drive_strength *array,
3949 size_t array_size, int microamp)
3950{
3951 char supported_values[100];
3952 size_t remaining_size;
3953 int added_len;
3954 char *ptr;
3955 int i;
3956
3957 remaining_size = sizeof(supported_values);
3958 ptr = supported_values;
3959
3960 for (i = 0; i < array_size; i++) {
3961 added_len = snprintf(buf: ptr, size: remaining_size,
3962 fmt: i == 0 ? "%d" : ", %d", array[i].microamp);
3963
3964 if (added_len >= remaining_size)
3965 break;
3966
3967 ptr += added_len;
3968 remaining_size -= added_len;
3969 }
3970
3971 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
3972 microamp, supported_values);
3973}
3974
3975/**
3976 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
3977 * chip variants.
3978 * @dev: ksz device
3979 * @props: Array of drive strength properties to be applied
3980 * @num_props: Number of properties in the array
3981 *
3982 * This function configures the drive strength for various KSZ9477 chip variants
3983 * based on the provided properties. It handles chip-specific nuances and
3984 * ensures only valid drive strengths are written to the respective chip.
3985 *
3986 * Return: 0 on successful configuration, a negative error code on failure.
3987 */
3988static int ksz9477_drive_strength_write(struct ksz_device *dev,
3989 struct ksz_driver_strength_prop *props,
3990 int num_props)
3991{
3992 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
3993 int i, ret, reg;
3994 u8 mask = 0;
3995 u8 val = 0;
3996
3997 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
3998 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
3999 props[KSZ_DRIVER_STRENGTH_IO].name);
4000
4001 if (dev->chip_id == KSZ8795_CHIP_ID ||
4002 dev->chip_id == KSZ8794_CHIP_ID ||
4003 dev->chip_id == KSZ8765_CHIP_ID)
4004 reg = KSZ8795_REG_SW_CTRL_20;
4005 else
4006 reg = KSZ9477_REG_SW_IO_STRENGTH;
4007
4008 for (i = 0; i < num_props; i++) {
4009 if (props[i].value == -1)
4010 continue;
4011
4012 ret = ksz_drive_strength_to_reg(array: ksz9477_drive_strengths,
4013 array_size, microamp: props[i].value);
4014 if (ret < 0) {
4015 ksz_drive_strength_error(dev, array: ksz9477_drive_strengths,
4016 array_size, microamp: props[i].value);
4017 return ret;
4018 }
4019
4020 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
4021 val |= ret << props[i].offset;
4022 }
4023
4024 return ksz_rmw8(dev, offset: reg, mask, val);
4025}
4026
4027/**
4028 * ksz8830_drive_strength_write() - Set the drive strength configuration for
4029 * KSZ8830 compatible chip variants.
4030 * @dev: ksz device
4031 * @props: Array of drive strength properties to be set
4032 * @num_props: Number of properties in the array
4033 *
4034 * This function applies the specified drive strength settings to KSZ8830 chip
4035 * variants (KSZ8873, KSZ8863).
4036 * It ensures the configurations align with what the chip variant supports and
4037 * warns or errors out on unsupported settings.
4038 *
4039 * Return: 0 on success, error code otherwise
4040 */
4041static int ksz8830_drive_strength_write(struct ksz_device *dev,
4042 struct ksz_driver_strength_prop *props,
4043 int num_props)
4044{
4045 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths);
4046 int microamp;
4047 int i, ret;
4048
4049 for (i = 0; i < num_props; i++) {
4050 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4051 continue;
4052
4053 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4054 props[i].name);
4055 }
4056
4057 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4058 ret = ksz_drive_strength_to_reg(array: ksz8830_drive_strengths, array_size,
4059 microamp);
4060 if (ret < 0) {
4061 ksz_drive_strength_error(dev, array: ksz8830_drive_strengths,
4062 array_size, microamp);
4063 return ret;
4064 }
4065
4066 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4067 KSZ8873_DRIVE_STRENGTH_16MA, val: ret);
4068}
4069
4070/**
4071 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4072 * from device tree properties.
4073 * @dev: ksz device
4074 *
4075 * This function reads the specified drive strength properties from the
4076 * device tree, validates against the supported chip variants, and sets
4077 * them accordingly. An error should be critical here, as the drive strength
4078 * settings are crucial for EMI compliance.
4079 *
4080 * Return: 0 on success, error code otherwise
4081 */
4082static int ksz_parse_drive_strength(struct ksz_device *dev)
4083{
4084 struct ksz_driver_strength_prop of_props[] = {
4085 [KSZ_DRIVER_STRENGTH_HI] = {
4086 .name = "microchip,hi-drive-strength-microamp",
4087 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4088 .value = -1,
4089 },
4090 [KSZ_DRIVER_STRENGTH_LO] = {
4091 .name = "microchip,lo-drive-strength-microamp",
4092 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4093 .value = -1,
4094 },
4095 [KSZ_DRIVER_STRENGTH_IO] = {
4096 .name = "microchip,io-drive-strength-microamp",
4097 .offset = 0, /* don't care */
4098 .value = -1,
4099 },
4100 };
4101 struct device_node *np = dev->dev->of_node;
4102 bool have_any_prop = false;
4103 int i, ret;
4104
4105 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4106 ret = of_property_read_u32(np, propname: of_props[i].name,
4107 out_value: &of_props[i].value);
4108 if (ret && ret != -EINVAL)
4109 dev_warn(dev->dev, "Failed to read %s\n",
4110 of_props[i].name);
4111 if (ret)
4112 continue;
4113
4114 have_any_prop = true;
4115 }
4116
4117 if (!have_any_prop)
4118 return 0;
4119
4120 switch (dev->chip_id) {
4121 case KSZ8830_CHIP_ID:
4122 return ksz8830_drive_strength_write(dev, props: of_props,
4123 ARRAY_SIZE(of_props));
4124 case KSZ8795_CHIP_ID:
4125 case KSZ8794_CHIP_ID:
4126 case KSZ8765_CHIP_ID:
4127 case KSZ8563_CHIP_ID:
4128 case KSZ9477_CHIP_ID:
4129 case KSZ9563_CHIP_ID:
4130 case KSZ9567_CHIP_ID:
4131 case KSZ9893_CHIP_ID:
4132 case KSZ9896_CHIP_ID:
4133 case KSZ9897_CHIP_ID:
4134 return ksz9477_drive_strength_write(dev, props: of_props,
4135 ARRAY_SIZE(of_props));
4136 default:
4137 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4138 if (of_props[i].value == -1)
4139 continue;
4140
4141 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4142 of_props[i].name);
4143 }
4144 }
4145
4146 return 0;
4147}
4148
4149int ksz_switch_register(struct ksz_device *dev)
4150{
4151 const struct ksz_chip_data *info;
4152 struct device_node *port, *ports;
4153 phy_interface_t interface;
4154 unsigned int port_num;
4155 int ret;
4156 int i;
4157
4158 if (dev->pdata)
4159 dev->chip_id = dev->pdata->chip_id;
4160
4161 dev->reset_gpio = devm_gpiod_get_optional(dev: dev->dev, con_id: "reset",
4162 flags: GPIOD_OUT_LOW);
4163 if (IS_ERR(ptr: dev->reset_gpio))
4164 return PTR_ERR(ptr: dev->reset_gpio);
4165
4166 if (dev->reset_gpio) {
4167 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
4168 usleep_range(min: 10000, max: 12000);
4169 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 0);
4170 msleep(msecs: 100);
4171 }
4172
4173 mutex_init(&dev->dev_mutex);
4174 mutex_init(&dev->regmap_mutex);
4175 mutex_init(&dev->alu_mutex);
4176 mutex_init(&dev->vlan_mutex);
4177
4178 ret = ksz_switch_detect(dev);
4179 if (ret)
4180 return ret;
4181
4182 info = ksz_lookup_info(prod_num: dev->chip_id);
4183 if (!info)
4184 return -ENODEV;
4185
4186 /* Update the compatible info with the probed one */
4187 dev->info = info;
4188
4189 dev_info(dev->dev, "found switch: %s, rev %i\n",
4190 dev->info->dev_name, dev->chip_rev);
4191
4192 ret = ksz_check_device_id(dev);
4193 if (ret)
4194 return ret;
4195
4196 dev->dev_ops = dev->info->ops;
4197
4198 ret = dev->dev_ops->init(dev);
4199 if (ret)
4200 return ret;
4201
4202 dev->ports = devm_kzalloc(dev: dev->dev,
4203 size: dev->info->port_cnt * sizeof(struct ksz_port),
4204 GFP_KERNEL);
4205 if (!dev->ports)
4206 return -ENOMEM;
4207
4208 for (i = 0; i < dev->info->port_cnt; i++) {
4209 spin_lock_init(&dev->ports[i].mib.stats64_lock);
4210 mutex_init(&dev->ports[i].mib.cnt_mutex);
4211 dev->ports[i].mib.counters =
4212 devm_kzalloc(dev: dev->dev,
4213 size: sizeof(u64) * (dev->info->mib_cnt + 1),
4214 GFP_KERNEL);
4215 if (!dev->ports[i].mib.counters)
4216 return -ENOMEM;
4217
4218 dev->ports[i].ksz_dev = dev;
4219 dev->ports[i].num = i;
4220 }
4221
4222 /* set the real number of ports */
4223 dev->ds->num_ports = dev->info->port_cnt;
4224
4225 /* Host port interface will be self detected, or specifically set in
4226 * device tree.
4227 */
4228 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
4229 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
4230 if (dev->dev->of_node) {
4231 ret = ksz_parse_drive_strength(dev);
4232 if (ret)
4233 return ret;
4234
4235 ret = of_get_phy_mode(np: dev->dev->of_node, interface: &interface);
4236 if (ret == 0)
4237 dev->compat_interface = interface;
4238 ports = of_get_child_by_name(node: dev->dev->of_node, name: "ethernet-ports");
4239 if (!ports)
4240 ports = of_get_child_by_name(node: dev->dev->of_node, name: "ports");
4241 if (ports) {
4242 for_each_available_child_of_node(ports, port) {
4243 if (of_property_read_u32(np: port, propname: "reg",
4244 out_value: &port_num))
4245 continue;
4246 if (!(dev->port_mask & BIT(port_num))) {
4247 of_node_put(node: port);
4248 of_node_put(node: ports);
4249 return -EINVAL;
4250 }
4251 of_get_phy_mode(np: port,
4252 interface: &dev->ports[port_num].interface);
4253
4254 ksz_parse_rgmii_delay(dev, port_num, port_dn: port);
4255 }
4256 of_node_put(node: ports);
4257 }
4258 dev->synclko_125 = of_property_read_bool(np: dev->dev->of_node,
4259 propname: "microchip,synclko-125");
4260 dev->synclko_disable = of_property_read_bool(np: dev->dev->of_node,
4261 propname: "microchip,synclko-disable");
4262 if (dev->synclko_125 && dev->synclko_disable) {
4263 dev_err(dev->dev, "inconsistent synclko settings\n");
4264 return -EINVAL;
4265 }
4266
4267 dev->wakeup_source = of_property_read_bool(np: dev->dev->of_node,
4268 propname: "wakeup-source");
4269 }
4270
4271 ret = dsa_register_switch(ds: dev->ds);
4272 if (ret) {
4273 dev->dev_ops->exit(dev);
4274 return ret;
4275 }
4276
4277 /* Read MIB counters every 30 seconds to avoid overflow. */
4278 dev->mib_read_interval = msecs_to_jiffies(m: 5000);
4279
4280 /* Start the MIB timer. */
4281 schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
4282
4283 return ret;
4284}
4285EXPORT_SYMBOL(ksz_switch_register);
4286
4287void ksz_switch_remove(struct ksz_device *dev)
4288{
4289 /* timer started */
4290 if (dev->mib_read_interval) {
4291 dev->mib_read_interval = 0;
4292 cancel_delayed_work_sync(dwork: &dev->mib_read);
4293 }
4294
4295 dev->dev_ops->exit(dev);
4296 dsa_unregister_switch(ds: dev->ds);
4297
4298 if (dev->reset_gpio)
4299 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
4300
4301}
4302EXPORT_SYMBOL(ksz_switch_remove);
4303
4304MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
4305MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
4306MODULE_LICENSE("GPL");
4307

source code of linux/drivers/net/dsa/microchip/ksz_common.c