1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2025 Microchip Technology Inc.
6 */
7
8#include <linux/delay.h>
9#include <linux/dsa/ksz_common.h>
10#include <linux/export.h>
11#include <linux/gpio/consumer.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <linux/if_vlan.h>
19#include <linux/if_hsr.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_mdio.h>
24#include <linux/of_net.h>
25#include <linux/micrel_phy.h>
26#include <net/dsa.h>
27#include <net/ieee8021q.h>
28#include <net/pkt_cls.h>
29#include <net/switchdev.h>
30
31#include "ksz_common.h"
32#include "ksz_dcb.h"
33#include "ksz_ptp.h"
34#include "ksz8.h"
35#include "ksz9477.h"
36#include "lan937x.h"
37
38#define MIB_COUNTER_NUM 0x20
39
40struct ksz_stats_raw {
41 u64 rx_hi;
42 u64 rx_undersize;
43 u64 rx_fragments;
44 u64 rx_oversize;
45 u64 rx_jabbers;
46 u64 rx_symbol_err;
47 u64 rx_crc_err;
48 u64 rx_align_err;
49 u64 rx_mac_ctrl;
50 u64 rx_pause;
51 u64 rx_bcast;
52 u64 rx_mcast;
53 u64 rx_ucast;
54 u64 rx_64_or_less;
55 u64 rx_65_127;
56 u64 rx_128_255;
57 u64 rx_256_511;
58 u64 rx_512_1023;
59 u64 rx_1024_1522;
60 u64 rx_1523_2000;
61 u64 rx_2001;
62 u64 tx_hi;
63 u64 tx_late_col;
64 u64 tx_pause;
65 u64 tx_bcast;
66 u64 tx_mcast;
67 u64 tx_ucast;
68 u64 tx_deferred;
69 u64 tx_total_col;
70 u64 tx_exc_col;
71 u64 tx_single_col;
72 u64 tx_mult_col;
73 u64 rx_total;
74 u64 tx_total;
75 u64 rx_discards;
76 u64 tx_discards;
77};
78
79struct ksz88xx_stats_raw {
80 u64 rx;
81 u64 rx_hi;
82 u64 rx_undersize;
83 u64 rx_fragments;
84 u64 rx_oversize;
85 u64 rx_jabbers;
86 u64 rx_symbol_err;
87 u64 rx_crc_err;
88 u64 rx_align_err;
89 u64 rx_mac_ctrl;
90 u64 rx_pause;
91 u64 rx_bcast;
92 u64 rx_mcast;
93 u64 rx_ucast;
94 u64 rx_64_or_less;
95 u64 rx_65_127;
96 u64 rx_128_255;
97 u64 rx_256_511;
98 u64 rx_512_1023;
99 u64 rx_1024_1522;
100 u64 tx;
101 u64 tx_hi;
102 u64 tx_late_col;
103 u64 tx_pause;
104 u64 tx_bcast;
105 u64 tx_mcast;
106 u64 tx_ucast;
107 u64 tx_deferred;
108 u64 tx_total_col;
109 u64 tx_exc_col;
110 u64 tx_single_col;
111 u64 tx_mult_col;
112 u64 rx_discards;
113 u64 tx_discards;
114};
115
116static const struct ksz_mib_names ksz88xx_mib_names[] = {
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
126 { 0x09, "rx_mac_ctrl" },
127 { 0x0a, "rx_pause" },
128 { 0x0b, "rx_bcast" },
129 { 0x0c, "rx_mcast" },
130 { 0x0d, "rx_ucast" },
131 { 0x0e, "rx_64_or_less" },
132 { 0x0f, "rx_65_127" },
133 { 0x10, "rx_128_255" },
134 { 0x11, "rx_256_511" },
135 { 0x12, "rx_512_1023" },
136 { 0x13, "rx_1024_1522" },
137 { 0x14, "tx" },
138 { 0x15, "tx_hi" },
139 { 0x16, "tx_late_col" },
140 { 0x17, "tx_pause" },
141 { 0x18, "tx_bcast" },
142 { 0x19, "tx_mcast" },
143 { 0x1a, "tx_ucast" },
144 { 0x1b, "tx_deferred" },
145 { 0x1c, "tx_total_col" },
146 { 0x1d, "tx_exc_col" },
147 { 0x1e, "tx_single_col" },
148 { 0x1f, "tx_mult_col" },
149 { 0x100, "rx_discards" },
150 { 0x101, "tx_discards" },
151};
152
153static const struct ksz_mib_names ksz9477_mib_names[] = {
154 { 0x00, "rx_hi" },
155 { 0x01, "rx_undersize" },
156 { 0x02, "rx_fragments" },
157 { 0x03, "rx_oversize" },
158 { 0x04, "rx_jabbers" },
159 { 0x05, "rx_symbol_err" },
160 { 0x06, "rx_crc_err" },
161 { 0x07, "rx_align_err" },
162 { 0x08, "rx_mac_ctrl" },
163 { 0x09, "rx_pause" },
164 { 0x0A, "rx_bcast" },
165 { 0x0B, "rx_mcast" },
166 { 0x0C, "rx_ucast" },
167 { 0x0D, "rx_64_or_less" },
168 { 0x0E, "rx_65_127" },
169 { 0x0F, "rx_128_255" },
170 { 0x10, "rx_256_511" },
171 { 0x11, "rx_512_1023" },
172 { 0x12, "rx_1024_1522" },
173 { 0x13, "rx_1523_2000" },
174 { 0x14, "rx_2001" },
175 { 0x15, "tx_hi" },
176 { 0x16, "tx_late_col" },
177 { 0x17, "tx_pause" },
178 { 0x18, "tx_bcast" },
179 { 0x19, "tx_mcast" },
180 { 0x1A, "tx_ucast" },
181 { 0x1B, "tx_deferred" },
182 { 0x1C, "tx_total_col" },
183 { 0x1D, "tx_exc_col" },
184 { 0x1E, "tx_single_col" },
185 { 0x1F, "tx_mult_col" },
186 { 0x80, "rx_total" },
187 { 0x81, "tx_total" },
188 { 0x82, "rx_discards" },
189 { 0x83, "tx_discards" },
190};
191
192struct ksz_driver_strength_prop {
193 const char *name;
194 int offset;
195 int value;
196};
197
198enum ksz_driver_strength_type {
199 KSZ_DRIVER_STRENGTH_HI,
200 KSZ_DRIVER_STRENGTH_LO,
201 KSZ_DRIVER_STRENGTH_IO,
202};
203
204/**
205 * struct ksz_drive_strength - drive strength mapping
206 * @reg_val: register value
207 * @microamp: microamp value
208 */
209struct ksz_drive_strength {
210 u32 reg_val;
211 u32 microamp;
212};
213
214/* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
215 *
216 * This values are not documented in KSZ9477 variants but confirmed by
217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
219 *
220 * Documentation in KSZ8795CLX provides more information with some
221 * recommendations:
222 * - for high speed signals
223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
224 * 2.5V or 3.3V VDDIO.
225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
226 * using 1.8V VDDIO.
227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
228 * or 3.3V VDDIO.
229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
230 * 5. In same interface, the heavy loading should use higher one of the
231 * drive current strength.
232 * - for low speed signals
233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
236 * 4. If it is heavy loading, can use higher drive current strength.
237 */
238static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
239 { SW_DRIVE_STRENGTH_2MA, 2000 },
240 { SW_DRIVE_STRENGTH_4MA, 4000 },
241 { SW_DRIVE_STRENGTH_8MA, 8000 },
242 { SW_DRIVE_STRENGTH_12MA, 12000 },
243 { SW_DRIVE_STRENGTH_16MA, 16000 },
244 { SW_DRIVE_STRENGTH_20MA, 20000 },
245 { SW_DRIVE_STRENGTH_24MA, 24000 },
246 { SW_DRIVE_STRENGTH_28MA, 28000 },
247};
248
249/* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
250 * variants.
251 * This values are documented in KSZ8873 and KSZ8863 datasheets.
252 */
253static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
254 { 0, 8000 },
255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
256};
257
258static void ksz88x3_phylink_mac_config(struct phylink_config *config,
259 unsigned int mode,
260 const struct phylink_link_state *state);
261static void ksz_phylink_mac_config(struct phylink_config *config,
262 unsigned int mode,
263 const struct phylink_link_state *state);
264static void ksz_phylink_mac_link_down(struct phylink_config *config,
265 unsigned int mode,
266 phy_interface_t interface);
267
268/**
269 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
270 * @config: phylink config structure
271 *
272 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for
273 * a detailed explanation of EEE/LPI handling in KSZ switches.
274 */
275static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config)
276{
277}
278
279/**
280 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
281 * @config: phylink config structure
282 * @timer: timer value before entering LPI (unused)
283 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused)
284 *
285 * This function signals to phylink that the driver architecture supports
286 * LPI management, enabling phylink to control EEE advertisement during
287 * negotiation according to IEEE Std 802.3 (Clause 78).
288 *
289 * Hardware Management of EEE/LPI State:
290 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2),
291 * observation and testing suggest that the actual EEE / Low Power Idle (LPI)
292 * state transitions are managed autonomously by the hardware based on
293 * the auto-negotiation results. (Note: While the datasheet describes EEE
294 * operation based on negotiation, it doesn't explicitly detail the internal
295 * MAC/PHY interaction, so autonomous hardware management of the MAC state
296 * for LPI is inferred from observed behavior).
297 * This hardware control, consistent with the switch's ability to operate
298 * autonomously via strapping, means MAC-level software intervention is not
299 * required or exposed for managing the LPI state once EEE is negotiated.
300 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining
301 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration
302 * Straps).
303 *
304 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3)
305 * lack documented MAC-level LPI control.
306 *
307 * Therefore, this callback performs no action and serves primarily to inform
308 * phylink of LPI awareness and to document the inferred hardware behavior.
309 *
310 * Returns: 0 (Always success)
311 */
312static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
313 u32 timer, bool tx_clock_stop)
314{
315 return 0;
316}
317
318static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
319 .mac_config = ksz88x3_phylink_mac_config,
320 .mac_link_down = ksz_phylink_mac_link_down,
321 .mac_link_up = ksz8_phylink_mac_link_up,
322 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
323 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
324};
325
326static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
327 .mac_config = ksz_phylink_mac_config,
328 .mac_link_down = ksz_phylink_mac_link_down,
329 .mac_link_up = ksz8_phylink_mac_link_up,
330 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
331 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
332};
333
334static const struct ksz_dev_ops ksz88xx_dev_ops = {
335 .setup = ksz8_setup,
336 .get_port_addr = ksz8_get_port_addr,
337 .cfg_port_member = ksz8_cfg_port_member,
338 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
339 .port_setup = ksz8_port_setup,
340 .r_phy = ksz8_r_phy,
341 .w_phy = ksz8_w_phy,
342 .r_mib_cnt = ksz8_r_mib_cnt,
343 .r_mib_pkt = ksz8_r_mib_pkt,
344 .r_mib_stat64 = ksz88xx_r_mib_stats64,
345 .freeze_mib = ksz8_freeze_mib,
346 .port_init_cnt = ksz8_port_init_cnt,
347 .fdb_dump = ksz8_fdb_dump,
348 .fdb_add = ksz8_fdb_add,
349 .fdb_del = ksz8_fdb_del,
350 .mdb_add = ksz8_mdb_add,
351 .mdb_del = ksz8_mdb_del,
352 .vlan_filtering = ksz8_port_vlan_filtering,
353 .vlan_add = ksz8_port_vlan_add,
354 .vlan_del = ksz8_port_vlan_del,
355 .mirror_add = ksz8_port_mirror_add,
356 .mirror_del = ksz8_port_mirror_del,
357 .get_caps = ksz8_get_caps,
358 .config_cpu_port = ksz8_config_cpu_port,
359 .enable_stp_addr = ksz8_enable_stp_addr,
360 .reset = ksz8_reset_switch,
361 .init = ksz8_switch_init,
362 .exit = ksz8_switch_exit,
363 .change_mtu = ksz8_change_mtu,
364 .pme_write8 = ksz8_pme_write8,
365 .pme_pread8 = ksz8_pme_pread8,
366 .pme_pwrite8 = ksz8_pme_pwrite8,
367};
368
369static const struct ksz_dev_ops ksz87xx_dev_ops = {
370 .setup = ksz8_setup,
371 .get_port_addr = ksz8_get_port_addr,
372 .cfg_port_member = ksz8_cfg_port_member,
373 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
374 .port_setup = ksz8_port_setup,
375 .r_phy = ksz8_r_phy,
376 .w_phy = ksz8_w_phy,
377 .r_mib_cnt = ksz8_r_mib_cnt,
378 .r_mib_pkt = ksz8_r_mib_pkt,
379 .r_mib_stat64 = ksz_r_mib_stats64,
380 .freeze_mib = ksz8_freeze_mib,
381 .port_init_cnt = ksz8_port_init_cnt,
382 .fdb_dump = ksz8_fdb_dump,
383 .fdb_add = ksz8_fdb_add,
384 .fdb_del = ksz8_fdb_del,
385 .mdb_add = ksz8_mdb_add,
386 .mdb_del = ksz8_mdb_del,
387 .vlan_filtering = ksz8_port_vlan_filtering,
388 .vlan_add = ksz8_port_vlan_add,
389 .vlan_del = ksz8_port_vlan_del,
390 .mirror_add = ksz8_port_mirror_add,
391 .mirror_del = ksz8_port_mirror_del,
392 .get_caps = ksz8_get_caps,
393 .config_cpu_port = ksz8_config_cpu_port,
394 .enable_stp_addr = ksz8_enable_stp_addr,
395 .reset = ksz8_reset_switch,
396 .init = ksz8_switch_init,
397 .exit = ksz8_switch_exit,
398 .change_mtu = ksz8_change_mtu,
399 .pme_write8 = ksz8_pme_write8,
400 .pme_pread8 = ksz8_pme_pread8,
401 .pme_pwrite8 = ksz8_pme_pwrite8,
402};
403
404static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
405 struct phy_device *phydev,
406 unsigned int mode,
407 phy_interface_t interface,
408 int speed, int duplex, bool tx_pause,
409 bool rx_pause);
410
411static struct phylink_pcs *
412ksz_phylink_mac_select_pcs(struct phylink_config *config,
413 phy_interface_t interface)
414{
415 struct dsa_port *dp = dsa_phylink_to_port(config);
416 struct ksz_device *dev = dp->ds->priv;
417 struct ksz_port *p = &dev->ports[dp->index];
418
419 if (ksz_is_sgmii_port(dev, port: dp->index) &&
420 (interface == PHY_INTERFACE_MODE_SGMII ||
421 interface == PHY_INTERFACE_MODE_1000BASEX))
422 return p->pcs;
423
424 return NULL;
425}
426
427static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
428 .mac_config = ksz_phylink_mac_config,
429 .mac_link_down = ksz_phylink_mac_link_down,
430 .mac_link_up = ksz9477_phylink_mac_link_up,
431 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
432 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
433 .mac_select_pcs = ksz_phylink_mac_select_pcs,
434};
435
436static const struct ksz_dev_ops ksz9477_dev_ops = {
437 .setup = ksz9477_setup,
438 .get_port_addr = ksz9477_get_port_addr,
439 .cfg_port_member = ksz9477_cfg_port_member,
440 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
441 .port_setup = ksz9477_port_setup,
442 .set_ageing_time = ksz9477_set_ageing_time,
443 .r_phy = ksz9477_r_phy,
444 .w_phy = ksz9477_w_phy,
445 .r_mib_cnt = ksz9477_r_mib_cnt,
446 .r_mib_pkt = ksz9477_r_mib_pkt,
447 .r_mib_stat64 = ksz_r_mib_stats64,
448 .freeze_mib = ksz9477_freeze_mib,
449 .port_init_cnt = ksz9477_port_init_cnt,
450 .vlan_filtering = ksz9477_port_vlan_filtering,
451 .vlan_add = ksz9477_port_vlan_add,
452 .vlan_del = ksz9477_port_vlan_del,
453 .mirror_add = ksz9477_port_mirror_add,
454 .mirror_del = ksz9477_port_mirror_del,
455 .get_caps = ksz9477_get_caps,
456 .fdb_dump = ksz9477_fdb_dump,
457 .fdb_add = ksz9477_fdb_add,
458 .fdb_del = ksz9477_fdb_del,
459 .mdb_add = ksz9477_mdb_add,
460 .mdb_del = ksz9477_mdb_del,
461 .change_mtu = ksz9477_change_mtu,
462 .pme_write8 = ksz_write8,
463 .pme_pread8 = ksz_pread8,
464 .pme_pwrite8 = ksz_pwrite8,
465 .config_cpu_port = ksz9477_config_cpu_port,
466 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
467 .enable_stp_addr = ksz9477_enable_stp_addr,
468 .reset = ksz9477_reset_switch,
469 .init = ksz9477_switch_init,
470 .exit = ksz9477_switch_exit,
471 .pcs_create = ksz9477_pcs_create,
472};
473
474static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
475 .mac_config = ksz_phylink_mac_config,
476 .mac_link_down = ksz_phylink_mac_link_down,
477 .mac_link_up = ksz9477_phylink_mac_link_up,
478 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
479 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
480};
481
482static const struct ksz_dev_ops lan937x_dev_ops = {
483 .setup = lan937x_setup,
484 .teardown = lan937x_teardown,
485 .get_port_addr = ksz9477_get_port_addr,
486 .cfg_port_member = ksz9477_cfg_port_member,
487 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
488 .port_setup = lan937x_port_setup,
489 .set_ageing_time = lan937x_set_ageing_time,
490 .mdio_bus_preinit = lan937x_mdio_bus_preinit,
491 .create_phy_addr_map = lan937x_create_phy_addr_map,
492 .r_phy = lan937x_r_phy,
493 .w_phy = lan937x_w_phy,
494 .r_mib_cnt = ksz9477_r_mib_cnt,
495 .r_mib_pkt = ksz9477_r_mib_pkt,
496 .r_mib_stat64 = ksz_r_mib_stats64,
497 .freeze_mib = ksz9477_freeze_mib,
498 .port_init_cnt = ksz9477_port_init_cnt,
499 .vlan_filtering = ksz9477_port_vlan_filtering,
500 .vlan_add = ksz9477_port_vlan_add,
501 .vlan_del = ksz9477_port_vlan_del,
502 .mirror_add = ksz9477_port_mirror_add,
503 .mirror_del = ksz9477_port_mirror_del,
504 .get_caps = lan937x_phylink_get_caps,
505 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
506 .fdb_dump = ksz9477_fdb_dump,
507 .fdb_add = ksz9477_fdb_add,
508 .fdb_del = ksz9477_fdb_del,
509 .mdb_add = ksz9477_mdb_add,
510 .mdb_del = ksz9477_mdb_del,
511 .change_mtu = lan937x_change_mtu,
512 .config_cpu_port = lan937x_config_cpu_port,
513 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
514 .enable_stp_addr = ksz9477_enable_stp_addr,
515 .reset = lan937x_reset_switch,
516 .init = lan937x_switch_init,
517 .exit = lan937x_switch_exit,
518};
519
520static const u16 ksz8795_regs[] = {
521 [REG_SW_MAC_ADDR] = 0x68,
522 [REG_IND_CTRL_0] = 0x6E,
523 [REG_IND_DATA_8] = 0x70,
524 [REG_IND_DATA_CHECK] = 0x72,
525 [REG_IND_DATA_HI] = 0x71,
526 [REG_IND_DATA_LO] = 0x75,
527 [REG_IND_MIB_CHECK] = 0x74,
528 [REG_IND_BYTE] = 0xA0,
529 [P_FORCE_CTRL] = 0x0C,
530 [P_LINK_STATUS] = 0x0E,
531 [P_LOCAL_CTRL] = 0x07,
532 [P_NEG_RESTART_CTRL] = 0x0D,
533 [P_REMOTE_STATUS] = 0x08,
534 [P_SPEED_STATUS] = 0x09,
535 [S_TAIL_TAG_CTRL] = 0x0C,
536 [P_STP_CTRL] = 0x02,
537 [S_START_CTRL] = 0x01,
538 [S_BROADCAST_CTRL] = 0x06,
539 [S_MULTICAST_CTRL] = 0x04,
540 [P_XMII_CTRL_0] = 0x06,
541 [P_XMII_CTRL_1] = 0x06,
542 [REG_SW_PME_CTRL] = 0x8003,
543 [REG_PORT_PME_STATUS] = 0x8003,
544 [REG_PORT_PME_CTRL] = 0x8007,
545};
546
547static const u32 ksz8795_masks[] = {
548 [PORT_802_1P_REMAPPING] = BIT(7),
549 [SW_TAIL_TAG_ENABLE] = BIT(1),
550 [MIB_COUNTER_OVERFLOW] = BIT(6),
551 [MIB_COUNTER_VALID] = BIT(5),
552 [VLAN_TABLE_FID] = GENMASK(6, 0),
553 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
554 [VLAN_TABLE_VALID] = BIT(12),
555 [STATIC_MAC_TABLE_VALID] = BIT(21),
556 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
557 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
558 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
559 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
560 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
561 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
562 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
563 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
564 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
565 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
566 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
567 [P_MII_TX_FLOW_CTRL] = BIT(5),
568 [P_MII_RX_FLOW_CTRL] = BIT(5),
569};
570
571static const u8 ksz8795_xmii_ctrl0[] = {
572 [P_MII_100MBIT] = 0,
573 [P_MII_10MBIT] = 1,
574 [P_MII_FULL_DUPLEX] = 0,
575 [P_MII_HALF_DUPLEX] = 1,
576};
577
578static const u8 ksz8795_xmii_ctrl1[] = {
579 [P_RGMII_SEL] = 3,
580 [P_GMII_SEL] = 2,
581 [P_RMII_SEL] = 1,
582 [P_MII_SEL] = 0,
583 [P_GMII_1GBIT] = 1,
584 [P_GMII_NOT_1GBIT] = 0,
585};
586
587static const u8 ksz8795_shifts[] = {
588 [VLAN_TABLE_MEMBERSHIP_S] = 7,
589 [VLAN_TABLE] = 16,
590 [STATIC_MAC_FWD_PORTS] = 16,
591 [STATIC_MAC_FID] = 24,
592 [DYNAMIC_MAC_ENTRIES_H] = 3,
593 [DYNAMIC_MAC_ENTRIES] = 29,
594 [DYNAMIC_MAC_FID] = 16,
595 [DYNAMIC_MAC_TIMESTAMP] = 27,
596 [DYNAMIC_MAC_SRC_PORT] = 24,
597};
598
599static const u16 ksz8863_regs[] = {
600 [REG_SW_MAC_ADDR] = 0x70,
601 [REG_IND_CTRL_0] = 0x79,
602 [REG_IND_DATA_8] = 0x7B,
603 [REG_IND_DATA_CHECK] = 0x7B,
604 [REG_IND_DATA_HI] = 0x7C,
605 [REG_IND_DATA_LO] = 0x80,
606 [REG_IND_MIB_CHECK] = 0x80,
607 [P_FORCE_CTRL] = 0x0C,
608 [P_LINK_STATUS] = 0x0E,
609 [P_LOCAL_CTRL] = 0x0C,
610 [P_NEG_RESTART_CTRL] = 0x0D,
611 [P_REMOTE_STATUS] = 0x0E,
612 [P_SPEED_STATUS] = 0x0F,
613 [S_TAIL_TAG_CTRL] = 0x03,
614 [P_STP_CTRL] = 0x02,
615 [S_START_CTRL] = 0x01,
616 [S_BROADCAST_CTRL] = 0x06,
617 [S_MULTICAST_CTRL] = 0x04,
618};
619
620static const u32 ksz8863_masks[] = {
621 [PORT_802_1P_REMAPPING] = BIT(3),
622 [SW_TAIL_TAG_ENABLE] = BIT(6),
623 [MIB_COUNTER_OVERFLOW] = BIT(7),
624 [MIB_COUNTER_VALID] = BIT(6),
625 [VLAN_TABLE_FID] = GENMASK(15, 12),
626 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
627 [VLAN_TABLE_VALID] = BIT(19),
628 [STATIC_MAC_TABLE_VALID] = BIT(19),
629 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
630 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
631 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
632 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
633 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
634 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
635 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
636 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
637 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
638 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
639 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
640};
641
642static u8 ksz8863_shifts[] = {
643 [VLAN_TABLE_MEMBERSHIP_S] = 16,
644 [STATIC_MAC_FWD_PORTS] = 16,
645 [STATIC_MAC_FID] = 22,
646 [DYNAMIC_MAC_ENTRIES_H] = 8,
647 [DYNAMIC_MAC_ENTRIES] = 24,
648 [DYNAMIC_MAC_FID] = 16,
649 [DYNAMIC_MAC_TIMESTAMP] = 22,
650 [DYNAMIC_MAC_SRC_PORT] = 20,
651};
652
653static const u16 ksz8895_regs[] = {
654 [REG_SW_MAC_ADDR] = 0x68,
655 [REG_IND_CTRL_0] = 0x6E,
656 [REG_IND_DATA_8] = 0x70,
657 [REG_IND_DATA_CHECK] = 0x72,
658 [REG_IND_DATA_HI] = 0x71,
659 [REG_IND_DATA_LO] = 0x75,
660 [REG_IND_MIB_CHECK] = 0x75,
661 [P_FORCE_CTRL] = 0x0C,
662 [P_LINK_STATUS] = 0x0E,
663 [P_LOCAL_CTRL] = 0x0C,
664 [P_NEG_RESTART_CTRL] = 0x0D,
665 [P_REMOTE_STATUS] = 0x0E,
666 [P_SPEED_STATUS] = 0x09,
667 [S_TAIL_TAG_CTRL] = 0x0C,
668 [P_STP_CTRL] = 0x02,
669 [S_START_CTRL] = 0x01,
670 [S_BROADCAST_CTRL] = 0x06,
671 [S_MULTICAST_CTRL] = 0x04,
672};
673
674static const u32 ksz8895_masks[] = {
675 [PORT_802_1P_REMAPPING] = BIT(7),
676 [SW_TAIL_TAG_ENABLE] = BIT(1),
677 [MIB_COUNTER_OVERFLOW] = BIT(7),
678 [MIB_COUNTER_VALID] = BIT(6),
679 [VLAN_TABLE_FID] = GENMASK(6, 0),
680 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
681 [VLAN_TABLE_VALID] = BIT(12),
682 [STATIC_MAC_TABLE_VALID] = BIT(21),
683 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
684 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
685 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
686 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
687 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
688 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
689 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
690 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
691 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
692 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
693 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
694};
695
696static const u8 ksz8895_shifts[] = {
697 [VLAN_TABLE_MEMBERSHIP_S] = 7,
698 [VLAN_TABLE] = 13,
699 [STATIC_MAC_FWD_PORTS] = 16,
700 [STATIC_MAC_FID] = 24,
701 [DYNAMIC_MAC_ENTRIES_H] = 3,
702 [DYNAMIC_MAC_ENTRIES] = 29,
703 [DYNAMIC_MAC_FID] = 16,
704 [DYNAMIC_MAC_TIMESTAMP] = 27,
705 [DYNAMIC_MAC_SRC_PORT] = 24,
706};
707
708static const u16 ksz9477_regs[] = {
709 [REG_SW_MAC_ADDR] = 0x0302,
710 [P_STP_CTRL] = 0x0B04,
711 [S_START_CTRL] = 0x0300,
712 [S_BROADCAST_CTRL] = 0x0332,
713 [S_MULTICAST_CTRL] = 0x0331,
714 [P_XMII_CTRL_0] = 0x0300,
715 [P_XMII_CTRL_1] = 0x0301,
716 [REG_SW_PME_CTRL] = 0x0006,
717 [REG_PORT_PME_STATUS] = 0x0013,
718 [REG_PORT_PME_CTRL] = 0x0017,
719};
720
721static const u32 ksz9477_masks[] = {
722 [ALU_STAT_WRITE] = 0,
723 [ALU_STAT_READ] = 1,
724 [P_MII_TX_FLOW_CTRL] = BIT(5),
725 [P_MII_RX_FLOW_CTRL] = BIT(3),
726};
727
728static const u8 ksz9477_shifts[] = {
729 [ALU_STAT_INDEX] = 16,
730};
731
732static const u8 ksz9477_xmii_ctrl0[] = {
733 [P_MII_100MBIT] = 1,
734 [P_MII_10MBIT] = 0,
735 [P_MII_FULL_DUPLEX] = 1,
736 [P_MII_HALF_DUPLEX] = 0,
737};
738
739static const u8 ksz9477_xmii_ctrl1[] = {
740 [P_RGMII_SEL] = 0,
741 [P_RMII_SEL] = 1,
742 [P_GMII_SEL] = 2,
743 [P_MII_SEL] = 3,
744 [P_GMII_1GBIT] = 0,
745 [P_GMII_NOT_1GBIT] = 1,
746};
747
748static const u32 lan937x_masks[] = {
749 [ALU_STAT_WRITE] = 1,
750 [ALU_STAT_READ] = 2,
751 [P_MII_TX_FLOW_CTRL] = BIT(5),
752 [P_MII_RX_FLOW_CTRL] = BIT(3),
753};
754
755static const u8 lan937x_shifts[] = {
756 [ALU_STAT_INDEX] = 8,
757};
758
759static const struct regmap_range ksz8563_valid_regs[] = {
760 regmap_reg_range(0x0000, 0x0003),
761 regmap_reg_range(0x0006, 0x0006),
762 regmap_reg_range(0x000f, 0x001f),
763 regmap_reg_range(0x0100, 0x0100),
764 regmap_reg_range(0x0104, 0x0107),
765 regmap_reg_range(0x010d, 0x010d),
766 regmap_reg_range(0x0110, 0x0113),
767 regmap_reg_range(0x0120, 0x012b),
768 regmap_reg_range(0x0201, 0x0201),
769 regmap_reg_range(0x0210, 0x0213),
770 regmap_reg_range(0x0300, 0x0300),
771 regmap_reg_range(0x0302, 0x031b),
772 regmap_reg_range(0x0320, 0x032b),
773 regmap_reg_range(0x0330, 0x0336),
774 regmap_reg_range(0x0338, 0x033e),
775 regmap_reg_range(0x0340, 0x035f),
776 regmap_reg_range(0x0370, 0x0370),
777 regmap_reg_range(0x0378, 0x0378),
778 regmap_reg_range(0x037c, 0x037d),
779 regmap_reg_range(0x0390, 0x0393),
780 regmap_reg_range(0x0400, 0x040e),
781 regmap_reg_range(0x0410, 0x042f),
782 regmap_reg_range(0x0500, 0x0519),
783 regmap_reg_range(0x0520, 0x054b),
784 regmap_reg_range(0x0550, 0x05b3),
785
786 /* port 1 */
787 regmap_reg_range(0x1000, 0x1001),
788 regmap_reg_range(0x1004, 0x100b),
789 regmap_reg_range(0x1013, 0x1013),
790 regmap_reg_range(0x1017, 0x1017),
791 regmap_reg_range(0x101b, 0x101b),
792 regmap_reg_range(0x101f, 0x1021),
793 regmap_reg_range(0x1030, 0x1030),
794 regmap_reg_range(0x1100, 0x1111),
795 regmap_reg_range(0x111a, 0x111d),
796 regmap_reg_range(0x1122, 0x1127),
797 regmap_reg_range(0x112a, 0x112b),
798 regmap_reg_range(0x1136, 0x1139),
799 regmap_reg_range(0x113e, 0x113f),
800 regmap_reg_range(0x1400, 0x1401),
801 regmap_reg_range(0x1403, 0x1403),
802 regmap_reg_range(0x1410, 0x1417),
803 regmap_reg_range(0x1420, 0x1423),
804 regmap_reg_range(0x1500, 0x1507),
805 regmap_reg_range(0x1600, 0x1612),
806 regmap_reg_range(0x1800, 0x180f),
807 regmap_reg_range(0x1900, 0x1907),
808 regmap_reg_range(0x1914, 0x191b),
809 regmap_reg_range(0x1a00, 0x1a03),
810 regmap_reg_range(0x1a04, 0x1a08),
811 regmap_reg_range(0x1b00, 0x1b01),
812 regmap_reg_range(0x1b04, 0x1b04),
813 regmap_reg_range(0x1c00, 0x1c05),
814 regmap_reg_range(0x1c08, 0x1c1b),
815
816 /* port 2 */
817 regmap_reg_range(0x2000, 0x2001),
818 regmap_reg_range(0x2004, 0x200b),
819 regmap_reg_range(0x2013, 0x2013),
820 regmap_reg_range(0x2017, 0x2017),
821 regmap_reg_range(0x201b, 0x201b),
822 regmap_reg_range(0x201f, 0x2021),
823 regmap_reg_range(0x2030, 0x2030),
824 regmap_reg_range(0x2100, 0x2111),
825 regmap_reg_range(0x211a, 0x211d),
826 regmap_reg_range(0x2122, 0x2127),
827 regmap_reg_range(0x212a, 0x212b),
828 regmap_reg_range(0x2136, 0x2139),
829 regmap_reg_range(0x213e, 0x213f),
830 regmap_reg_range(0x2400, 0x2401),
831 regmap_reg_range(0x2403, 0x2403),
832 regmap_reg_range(0x2410, 0x2417),
833 regmap_reg_range(0x2420, 0x2423),
834 regmap_reg_range(0x2500, 0x2507),
835 regmap_reg_range(0x2600, 0x2612),
836 regmap_reg_range(0x2800, 0x280f),
837 regmap_reg_range(0x2900, 0x2907),
838 regmap_reg_range(0x2914, 0x291b),
839 regmap_reg_range(0x2a00, 0x2a03),
840 regmap_reg_range(0x2a04, 0x2a08),
841 regmap_reg_range(0x2b00, 0x2b01),
842 regmap_reg_range(0x2b04, 0x2b04),
843 regmap_reg_range(0x2c00, 0x2c05),
844 regmap_reg_range(0x2c08, 0x2c1b),
845
846 /* port 3 */
847 regmap_reg_range(0x3000, 0x3001),
848 regmap_reg_range(0x3004, 0x300b),
849 regmap_reg_range(0x3013, 0x3013),
850 regmap_reg_range(0x3017, 0x3017),
851 regmap_reg_range(0x301b, 0x301b),
852 regmap_reg_range(0x301f, 0x3021),
853 regmap_reg_range(0x3030, 0x3030),
854 regmap_reg_range(0x3300, 0x3301),
855 regmap_reg_range(0x3303, 0x3303),
856 regmap_reg_range(0x3400, 0x3401),
857 regmap_reg_range(0x3403, 0x3403),
858 regmap_reg_range(0x3410, 0x3417),
859 regmap_reg_range(0x3420, 0x3423),
860 regmap_reg_range(0x3500, 0x3507),
861 regmap_reg_range(0x3600, 0x3612),
862 regmap_reg_range(0x3800, 0x380f),
863 regmap_reg_range(0x3900, 0x3907),
864 regmap_reg_range(0x3914, 0x391b),
865 regmap_reg_range(0x3a00, 0x3a03),
866 regmap_reg_range(0x3a04, 0x3a08),
867 regmap_reg_range(0x3b00, 0x3b01),
868 regmap_reg_range(0x3b04, 0x3b04),
869 regmap_reg_range(0x3c00, 0x3c05),
870 regmap_reg_range(0x3c08, 0x3c1b),
871};
872
873static const struct regmap_access_table ksz8563_register_set = {
874 .yes_ranges = ksz8563_valid_regs,
875 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
876};
877
878static const struct regmap_range ksz9477_valid_regs[] = {
879 regmap_reg_range(0x0000, 0x0003),
880 regmap_reg_range(0x0006, 0x0006),
881 regmap_reg_range(0x0010, 0x001f),
882 regmap_reg_range(0x0100, 0x0100),
883 regmap_reg_range(0x0103, 0x0107),
884 regmap_reg_range(0x010d, 0x010d),
885 regmap_reg_range(0x0110, 0x0113),
886 regmap_reg_range(0x0120, 0x012b),
887 regmap_reg_range(0x0201, 0x0201),
888 regmap_reg_range(0x0210, 0x0213),
889 regmap_reg_range(0x0300, 0x0300),
890 regmap_reg_range(0x0302, 0x031b),
891 regmap_reg_range(0x0320, 0x032b),
892 regmap_reg_range(0x0330, 0x0336),
893 regmap_reg_range(0x0338, 0x033b),
894 regmap_reg_range(0x033e, 0x033e),
895 regmap_reg_range(0x0340, 0x035f),
896 regmap_reg_range(0x0370, 0x0370),
897 regmap_reg_range(0x0378, 0x0378),
898 regmap_reg_range(0x037c, 0x037d),
899 regmap_reg_range(0x0390, 0x0393),
900 regmap_reg_range(0x0400, 0x040e),
901 regmap_reg_range(0x0410, 0x042f),
902 regmap_reg_range(0x0444, 0x044b),
903 regmap_reg_range(0x0450, 0x046f),
904 regmap_reg_range(0x0500, 0x0519),
905 regmap_reg_range(0x0520, 0x054b),
906 regmap_reg_range(0x0550, 0x05b3),
907 regmap_reg_range(0x0604, 0x060b),
908 regmap_reg_range(0x0610, 0x0612),
909 regmap_reg_range(0x0614, 0x062c),
910 regmap_reg_range(0x0640, 0x0645),
911 regmap_reg_range(0x0648, 0x064d),
912
913 /* port 1 */
914 regmap_reg_range(0x1000, 0x1001),
915 regmap_reg_range(0x1013, 0x1013),
916 regmap_reg_range(0x1017, 0x1017),
917 regmap_reg_range(0x101b, 0x101b),
918 regmap_reg_range(0x101f, 0x1020),
919 regmap_reg_range(0x1030, 0x1030),
920 regmap_reg_range(0x1100, 0x1115),
921 regmap_reg_range(0x111a, 0x111f),
922 regmap_reg_range(0x1120, 0x112b),
923 regmap_reg_range(0x1134, 0x113b),
924 regmap_reg_range(0x113c, 0x113f),
925 regmap_reg_range(0x1400, 0x1401),
926 regmap_reg_range(0x1403, 0x1403),
927 regmap_reg_range(0x1410, 0x1417),
928 regmap_reg_range(0x1420, 0x1423),
929 regmap_reg_range(0x1500, 0x1507),
930 regmap_reg_range(0x1600, 0x1613),
931 regmap_reg_range(0x1800, 0x180f),
932 regmap_reg_range(0x1820, 0x1827),
933 regmap_reg_range(0x1830, 0x1837),
934 regmap_reg_range(0x1840, 0x184b),
935 regmap_reg_range(0x1900, 0x1907),
936 regmap_reg_range(0x1914, 0x191b),
937 regmap_reg_range(0x1920, 0x1920),
938 regmap_reg_range(0x1923, 0x1927),
939 regmap_reg_range(0x1a00, 0x1a03),
940 regmap_reg_range(0x1a04, 0x1a07),
941 regmap_reg_range(0x1b00, 0x1b01),
942 regmap_reg_range(0x1b04, 0x1b04),
943 regmap_reg_range(0x1c00, 0x1c05),
944 regmap_reg_range(0x1c08, 0x1c1b),
945
946 /* port 2 */
947 regmap_reg_range(0x2000, 0x2001),
948 regmap_reg_range(0x2013, 0x2013),
949 regmap_reg_range(0x2017, 0x2017),
950 regmap_reg_range(0x201b, 0x201b),
951 regmap_reg_range(0x201f, 0x2020),
952 regmap_reg_range(0x2030, 0x2030),
953 regmap_reg_range(0x2100, 0x2115),
954 regmap_reg_range(0x211a, 0x211f),
955 regmap_reg_range(0x2120, 0x212b),
956 regmap_reg_range(0x2134, 0x213b),
957 regmap_reg_range(0x213c, 0x213f),
958 regmap_reg_range(0x2400, 0x2401),
959 regmap_reg_range(0x2403, 0x2403),
960 regmap_reg_range(0x2410, 0x2417),
961 regmap_reg_range(0x2420, 0x2423),
962 regmap_reg_range(0x2500, 0x2507),
963 regmap_reg_range(0x2600, 0x2613),
964 regmap_reg_range(0x2800, 0x280f),
965 regmap_reg_range(0x2820, 0x2827),
966 regmap_reg_range(0x2830, 0x2837),
967 regmap_reg_range(0x2840, 0x284b),
968 regmap_reg_range(0x2900, 0x2907),
969 regmap_reg_range(0x2914, 0x291b),
970 regmap_reg_range(0x2920, 0x2920),
971 regmap_reg_range(0x2923, 0x2927),
972 regmap_reg_range(0x2a00, 0x2a03),
973 regmap_reg_range(0x2a04, 0x2a07),
974 regmap_reg_range(0x2b00, 0x2b01),
975 regmap_reg_range(0x2b04, 0x2b04),
976 regmap_reg_range(0x2c00, 0x2c05),
977 regmap_reg_range(0x2c08, 0x2c1b),
978
979 /* port 3 */
980 regmap_reg_range(0x3000, 0x3001),
981 regmap_reg_range(0x3013, 0x3013),
982 regmap_reg_range(0x3017, 0x3017),
983 regmap_reg_range(0x301b, 0x301b),
984 regmap_reg_range(0x301f, 0x3020),
985 regmap_reg_range(0x3030, 0x3030),
986 regmap_reg_range(0x3100, 0x3115),
987 regmap_reg_range(0x311a, 0x311f),
988 regmap_reg_range(0x3120, 0x312b),
989 regmap_reg_range(0x3134, 0x313b),
990 regmap_reg_range(0x313c, 0x313f),
991 regmap_reg_range(0x3400, 0x3401),
992 regmap_reg_range(0x3403, 0x3403),
993 regmap_reg_range(0x3410, 0x3417),
994 regmap_reg_range(0x3420, 0x3423),
995 regmap_reg_range(0x3500, 0x3507),
996 regmap_reg_range(0x3600, 0x3613),
997 regmap_reg_range(0x3800, 0x380f),
998 regmap_reg_range(0x3820, 0x3827),
999 regmap_reg_range(0x3830, 0x3837),
1000 regmap_reg_range(0x3840, 0x384b),
1001 regmap_reg_range(0x3900, 0x3907),
1002 regmap_reg_range(0x3914, 0x391b),
1003 regmap_reg_range(0x3920, 0x3920),
1004 regmap_reg_range(0x3923, 0x3927),
1005 regmap_reg_range(0x3a00, 0x3a03),
1006 regmap_reg_range(0x3a04, 0x3a07),
1007 regmap_reg_range(0x3b00, 0x3b01),
1008 regmap_reg_range(0x3b04, 0x3b04),
1009 regmap_reg_range(0x3c00, 0x3c05),
1010 regmap_reg_range(0x3c08, 0x3c1b),
1011
1012 /* port 4 */
1013 regmap_reg_range(0x4000, 0x4001),
1014 regmap_reg_range(0x4013, 0x4013),
1015 regmap_reg_range(0x4017, 0x4017),
1016 regmap_reg_range(0x401b, 0x401b),
1017 regmap_reg_range(0x401f, 0x4020),
1018 regmap_reg_range(0x4030, 0x4030),
1019 regmap_reg_range(0x4100, 0x4115),
1020 regmap_reg_range(0x411a, 0x411f),
1021 regmap_reg_range(0x4120, 0x412b),
1022 regmap_reg_range(0x4134, 0x413b),
1023 regmap_reg_range(0x413c, 0x413f),
1024 regmap_reg_range(0x4400, 0x4401),
1025 regmap_reg_range(0x4403, 0x4403),
1026 regmap_reg_range(0x4410, 0x4417),
1027 regmap_reg_range(0x4420, 0x4423),
1028 regmap_reg_range(0x4500, 0x4507),
1029 regmap_reg_range(0x4600, 0x4613),
1030 regmap_reg_range(0x4800, 0x480f),
1031 regmap_reg_range(0x4820, 0x4827),
1032 regmap_reg_range(0x4830, 0x4837),
1033 regmap_reg_range(0x4840, 0x484b),
1034 regmap_reg_range(0x4900, 0x4907),
1035 regmap_reg_range(0x4914, 0x491b),
1036 regmap_reg_range(0x4920, 0x4920),
1037 regmap_reg_range(0x4923, 0x4927),
1038 regmap_reg_range(0x4a00, 0x4a03),
1039 regmap_reg_range(0x4a04, 0x4a07),
1040 regmap_reg_range(0x4b00, 0x4b01),
1041 regmap_reg_range(0x4b04, 0x4b04),
1042 regmap_reg_range(0x4c00, 0x4c05),
1043 regmap_reg_range(0x4c08, 0x4c1b),
1044
1045 /* port 5 */
1046 regmap_reg_range(0x5000, 0x5001),
1047 regmap_reg_range(0x5013, 0x5013),
1048 regmap_reg_range(0x5017, 0x5017),
1049 regmap_reg_range(0x501b, 0x501b),
1050 regmap_reg_range(0x501f, 0x5020),
1051 regmap_reg_range(0x5030, 0x5030),
1052 regmap_reg_range(0x5100, 0x5115),
1053 regmap_reg_range(0x511a, 0x511f),
1054 regmap_reg_range(0x5120, 0x512b),
1055 regmap_reg_range(0x5134, 0x513b),
1056 regmap_reg_range(0x513c, 0x513f),
1057 regmap_reg_range(0x5400, 0x5401),
1058 regmap_reg_range(0x5403, 0x5403),
1059 regmap_reg_range(0x5410, 0x5417),
1060 regmap_reg_range(0x5420, 0x5423),
1061 regmap_reg_range(0x5500, 0x5507),
1062 regmap_reg_range(0x5600, 0x5613),
1063 regmap_reg_range(0x5800, 0x580f),
1064 regmap_reg_range(0x5820, 0x5827),
1065 regmap_reg_range(0x5830, 0x5837),
1066 regmap_reg_range(0x5840, 0x584b),
1067 regmap_reg_range(0x5900, 0x5907),
1068 regmap_reg_range(0x5914, 0x591b),
1069 regmap_reg_range(0x5920, 0x5920),
1070 regmap_reg_range(0x5923, 0x5927),
1071 regmap_reg_range(0x5a00, 0x5a03),
1072 regmap_reg_range(0x5a04, 0x5a07),
1073 regmap_reg_range(0x5b00, 0x5b01),
1074 regmap_reg_range(0x5b04, 0x5b04),
1075 regmap_reg_range(0x5c00, 0x5c05),
1076 regmap_reg_range(0x5c08, 0x5c1b),
1077
1078 /* port 6 */
1079 regmap_reg_range(0x6000, 0x6001),
1080 regmap_reg_range(0x6013, 0x6013),
1081 regmap_reg_range(0x6017, 0x6017),
1082 regmap_reg_range(0x601b, 0x601b),
1083 regmap_reg_range(0x601f, 0x6020),
1084 regmap_reg_range(0x6030, 0x6030),
1085 regmap_reg_range(0x6300, 0x6301),
1086 regmap_reg_range(0x6400, 0x6401),
1087 regmap_reg_range(0x6403, 0x6403),
1088 regmap_reg_range(0x6410, 0x6417),
1089 regmap_reg_range(0x6420, 0x6423),
1090 regmap_reg_range(0x6500, 0x6507),
1091 regmap_reg_range(0x6600, 0x6613),
1092 regmap_reg_range(0x6800, 0x680f),
1093 regmap_reg_range(0x6820, 0x6827),
1094 regmap_reg_range(0x6830, 0x6837),
1095 regmap_reg_range(0x6840, 0x684b),
1096 regmap_reg_range(0x6900, 0x6907),
1097 regmap_reg_range(0x6914, 0x691b),
1098 regmap_reg_range(0x6920, 0x6920),
1099 regmap_reg_range(0x6923, 0x6927),
1100 regmap_reg_range(0x6a00, 0x6a03),
1101 regmap_reg_range(0x6a04, 0x6a07),
1102 regmap_reg_range(0x6b00, 0x6b01),
1103 regmap_reg_range(0x6b04, 0x6b04),
1104 regmap_reg_range(0x6c00, 0x6c05),
1105 regmap_reg_range(0x6c08, 0x6c1b),
1106
1107 /* port 7 */
1108 regmap_reg_range(0x7000, 0x7001),
1109 regmap_reg_range(0x7013, 0x7013),
1110 regmap_reg_range(0x7017, 0x7017),
1111 regmap_reg_range(0x701b, 0x701b),
1112 regmap_reg_range(0x701f, 0x7020),
1113 regmap_reg_range(0x7030, 0x7030),
1114 regmap_reg_range(0x7200, 0x7207),
1115 regmap_reg_range(0x7300, 0x7301),
1116 regmap_reg_range(0x7400, 0x7401),
1117 regmap_reg_range(0x7403, 0x7403),
1118 regmap_reg_range(0x7410, 0x7417),
1119 regmap_reg_range(0x7420, 0x7423),
1120 regmap_reg_range(0x7500, 0x7507),
1121 regmap_reg_range(0x7600, 0x7613),
1122 regmap_reg_range(0x7800, 0x780f),
1123 regmap_reg_range(0x7820, 0x7827),
1124 regmap_reg_range(0x7830, 0x7837),
1125 regmap_reg_range(0x7840, 0x784b),
1126 regmap_reg_range(0x7900, 0x7907),
1127 regmap_reg_range(0x7914, 0x791b),
1128 regmap_reg_range(0x7920, 0x7920),
1129 regmap_reg_range(0x7923, 0x7927),
1130 regmap_reg_range(0x7a00, 0x7a03),
1131 regmap_reg_range(0x7a04, 0x7a07),
1132 regmap_reg_range(0x7b00, 0x7b01),
1133 regmap_reg_range(0x7b04, 0x7b04),
1134 regmap_reg_range(0x7c00, 0x7c05),
1135 regmap_reg_range(0x7c08, 0x7c1b),
1136};
1137
1138static const struct regmap_access_table ksz9477_register_set = {
1139 .yes_ranges = ksz9477_valid_regs,
1140 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1141};
1142
1143static const struct regmap_range ksz9896_valid_regs[] = {
1144 regmap_reg_range(0x0000, 0x0003),
1145 regmap_reg_range(0x0006, 0x0006),
1146 regmap_reg_range(0x0010, 0x001f),
1147 regmap_reg_range(0x0100, 0x0100),
1148 regmap_reg_range(0x0103, 0x0107),
1149 regmap_reg_range(0x010d, 0x010d),
1150 regmap_reg_range(0x0110, 0x0113),
1151 regmap_reg_range(0x0120, 0x0127),
1152 regmap_reg_range(0x0201, 0x0201),
1153 regmap_reg_range(0x0210, 0x0213),
1154 regmap_reg_range(0x0300, 0x0300),
1155 regmap_reg_range(0x0302, 0x030b),
1156 regmap_reg_range(0x0310, 0x031b),
1157 regmap_reg_range(0x0320, 0x032b),
1158 regmap_reg_range(0x0330, 0x0336),
1159 regmap_reg_range(0x0338, 0x033b),
1160 regmap_reg_range(0x033e, 0x033e),
1161 regmap_reg_range(0x0340, 0x035f),
1162 regmap_reg_range(0x0370, 0x0370),
1163 regmap_reg_range(0x0378, 0x0378),
1164 regmap_reg_range(0x037c, 0x037d),
1165 regmap_reg_range(0x0390, 0x0393),
1166 regmap_reg_range(0x0400, 0x040e),
1167 regmap_reg_range(0x0410, 0x042f),
1168
1169 /* port 1 */
1170 regmap_reg_range(0x1000, 0x1001),
1171 regmap_reg_range(0x1013, 0x1013),
1172 regmap_reg_range(0x1017, 0x1017),
1173 regmap_reg_range(0x101b, 0x101b),
1174 regmap_reg_range(0x101f, 0x1020),
1175 regmap_reg_range(0x1030, 0x1030),
1176 regmap_reg_range(0x1100, 0x1115),
1177 regmap_reg_range(0x111a, 0x111f),
1178 regmap_reg_range(0x1120, 0x112b),
1179 regmap_reg_range(0x1134, 0x113b),
1180 regmap_reg_range(0x113c, 0x113f),
1181 regmap_reg_range(0x1400, 0x1401),
1182 regmap_reg_range(0x1403, 0x1403),
1183 regmap_reg_range(0x1410, 0x1417),
1184 regmap_reg_range(0x1420, 0x1423),
1185 regmap_reg_range(0x1500, 0x1507),
1186 regmap_reg_range(0x1600, 0x1612),
1187 regmap_reg_range(0x1800, 0x180f),
1188 regmap_reg_range(0x1820, 0x1827),
1189 regmap_reg_range(0x1830, 0x1837),
1190 regmap_reg_range(0x1840, 0x184b),
1191 regmap_reg_range(0x1900, 0x1907),
1192 regmap_reg_range(0x1914, 0x1915),
1193 regmap_reg_range(0x1a00, 0x1a03),
1194 regmap_reg_range(0x1a04, 0x1a07),
1195 regmap_reg_range(0x1b00, 0x1b01),
1196 regmap_reg_range(0x1b04, 0x1b04),
1197
1198 /* port 2 */
1199 regmap_reg_range(0x2000, 0x2001),
1200 regmap_reg_range(0x2013, 0x2013),
1201 regmap_reg_range(0x2017, 0x2017),
1202 regmap_reg_range(0x201b, 0x201b),
1203 regmap_reg_range(0x201f, 0x2020),
1204 regmap_reg_range(0x2030, 0x2030),
1205 regmap_reg_range(0x2100, 0x2115),
1206 regmap_reg_range(0x211a, 0x211f),
1207 regmap_reg_range(0x2120, 0x212b),
1208 regmap_reg_range(0x2134, 0x213b),
1209 regmap_reg_range(0x213c, 0x213f),
1210 regmap_reg_range(0x2400, 0x2401),
1211 regmap_reg_range(0x2403, 0x2403),
1212 regmap_reg_range(0x2410, 0x2417),
1213 regmap_reg_range(0x2420, 0x2423),
1214 regmap_reg_range(0x2500, 0x2507),
1215 regmap_reg_range(0x2600, 0x2612),
1216 regmap_reg_range(0x2800, 0x280f),
1217 regmap_reg_range(0x2820, 0x2827),
1218 regmap_reg_range(0x2830, 0x2837),
1219 regmap_reg_range(0x2840, 0x284b),
1220 regmap_reg_range(0x2900, 0x2907),
1221 regmap_reg_range(0x2914, 0x2915),
1222 regmap_reg_range(0x2a00, 0x2a03),
1223 regmap_reg_range(0x2a04, 0x2a07),
1224 regmap_reg_range(0x2b00, 0x2b01),
1225 regmap_reg_range(0x2b04, 0x2b04),
1226
1227 /* port 3 */
1228 regmap_reg_range(0x3000, 0x3001),
1229 regmap_reg_range(0x3013, 0x3013),
1230 regmap_reg_range(0x3017, 0x3017),
1231 regmap_reg_range(0x301b, 0x301b),
1232 regmap_reg_range(0x301f, 0x3020),
1233 regmap_reg_range(0x3030, 0x3030),
1234 regmap_reg_range(0x3100, 0x3115),
1235 regmap_reg_range(0x311a, 0x311f),
1236 regmap_reg_range(0x3120, 0x312b),
1237 regmap_reg_range(0x3134, 0x313b),
1238 regmap_reg_range(0x313c, 0x313f),
1239 regmap_reg_range(0x3400, 0x3401),
1240 regmap_reg_range(0x3403, 0x3403),
1241 regmap_reg_range(0x3410, 0x3417),
1242 regmap_reg_range(0x3420, 0x3423),
1243 regmap_reg_range(0x3500, 0x3507),
1244 regmap_reg_range(0x3600, 0x3612),
1245 regmap_reg_range(0x3800, 0x380f),
1246 regmap_reg_range(0x3820, 0x3827),
1247 regmap_reg_range(0x3830, 0x3837),
1248 regmap_reg_range(0x3840, 0x384b),
1249 regmap_reg_range(0x3900, 0x3907),
1250 regmap_reg_range(0x3914, 0x3915),
1251 regmap_reg_range(0x3a00, 0x3a03),
1252 regmap_reg_range(0x3a04, 0x3a07),
1253 regmap_reg_range(0x3b00, 0x3b01),
1254 regmap_reg_range(0x3b04, 0x3b04),
1255
1256 /* port 4 */
1257 regmap_reg_range(0x4000, 0x4001),
1258 regmap_reg_range(0x4013, 0x4013),
1259 regmap_reg_range(0x4017, 0x4017),
1260 regmap_reg_range(0x401b, 0x401b),
1261 regmap_reg_range(0x401f, 0x4020),
1262 regmap_reg_range(0x4030, 0x4030),
1263 regmap_reg_range(0x4100, 0x4115),
1264 regmap_reg_range(0x411a, 0x411f),
1265 regmap_reg_range(0x4120, 0x412b),
1266 regmap_reg_range(0x4134, 0x413b),
1267 regmap_reg_range(0x413c, 0x413f),
1268 regmap_reg_range(0x4400, 0x4401),
1269 regmap_reg_range(0x4403, 0x4403),
1270 regmap_reg_range(0x4410, 0x4417),
1271 regmap_reg_range(0x4420, 0x4423),
1272 regmap_reg_range(0x4500, 0x4507),
1273 regmap_reg_range(0x4600, 0x4612),
1274 regmap_reg_range(0x4800, 0x480f),
1275 regmap_reg_range(0x4820, 0x4827),
1276 regmap_reg_range(0x4830, 0x4837),
1277 regmap_reg_range(0x4840, 0x484b),
1278 regmap_reg_range(0x4900, 0x4907),
1279 regmap_reg_range(0x4914, 0x4915),
1280 regmap_reg_range(0x4a00, 0x4a03),
1281 regmap_reg_range(0x4a04, 0x4a07),
1282 regmap_reg_range(0x4b00, 0x4b01),
1283 regmap_reg_range(0x4b04, 0x4b04),
1284
1285 /* port 5 */
1286 regmap_reg_range(0x5000, 0x5001),
1287 regmap_reg_range(0x5013, 0x5013),
1288 regmap_reg_range(0x5017, 0x5017),
1289 regmap_reg_range(0x501b, 0x501b),
1290 regmap_reg_range(0x501f, 0x5020),
1291 regmap_reg_range(0x5030, 0x5030),
1292 regmap_reg_range(0x5100, 0x5115),
1293 regmap_reg_range(0x511a, 0x511f),
1294 regmap_reg_range(0x5120, 0x512b),
1295 regmap_reg_range(0x5134, 0x513b),
1296 regmap_reg_range(0x513c, 0x513f),
1297 regmap_reg_range(0x5400, 0x5401),
1298 regmap_reg_range(0x5403, 0x5403),
1299 regmap_reg_range(0x5410, 0x5417),
1300 regmap_reg_range(0x5420, 0x5423),
1301 regmap_reg_range(0x5500, 0x5507),
1302 regmap_reg_range(0x5600, 0x5612),
1303 regmap_reg_range(0x5800, 0x580f),
1304 regmap_reg_range(0x5820, 0x5827),
1305 regmap_reg_range(0x5830, 0x5837),
1306 regmap_reg_range(0x5840, 0x584b),
1307 regmap_reg_range(0x5900, 0x5907),
1308 regmap_reg_range(0x5914, 0x5915),
1309 regmap_reg_range(0x5a00, 0x5a03),
1310 regmap_reg_range(0x5a04, 0x5a07),
1311 regmap_reg_range(0x5b00, 0x5b01),
1312 regmap_reg_range(0x5b04, 0x5b04),
1313
1314 /* port 6 */
1315 regmap_reg_range(0x6000, 0x6001),
1316 regmap_reg_range(0x6013, 0x6013),
1317 regmap_reg_range(0x6017, 0x6017),
1318 regmap_reg_range(0x601b, 0x601b),
1319 regmap_reg_range(0x601f, 0x6020),
1320 regmap_reg_range(0x6030, 0x6030),
1321 regmap_reg_range(0x6100, 0x6115),
1322 regmap_reg_range(0x611a, 0x611f),
1323 regmap_reg_range(0x6120, 0x612b),
1324 regmap_reg_range(0x6134, 0x613b),
1325 regmap_reg_range(0x613c, 0x613f),
1326 regmap_reg_range(0x6300, 0x6301),
1327 regmap_reg_range(0x6400, 0x6401),
1328 regmap_reg_range(0x6403, 0x6403),
1329 regmap_reg_range(0x6410, 0x6417),
1330 regmap_reg_range(0x6420, 0x6423),
1331 regmap_reg_range(0x6500, 0x6507),
1332 regmap_reg_range(0x6600, 0x6612),
1333 regmap_reg_range(0x6800, 0x680f),
1334 regmap_reg_range(0x6820, 0x6827),
1335 regmap_reg_range(0x6830, 0x6837),
1336 regmap_reg_range(0x6840, 0x684b),
1337 regmap_reg_range(0x6900, 0x6907),
1338 regmap_reg_range(0x6914, 0x6915),
1339 regmap_reg_range(0x6a00, 0x6a03),
1340 regmap_reg_range(0x6a04, 0x6a07),
1341 regmap_reg_range(0x6b00, 0x6b01),
1342 regmap_reg_range(0x6b04, 0x6b04),
1343};
1344
1345static const struct regmap_access_table ksz9896_register_set = {
1346 .yes_ranges = ksz9896_valid_regs,
1347 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1348};
1349
1350static const struct regmap_range ksz8873_valid_regs[] = {
1351 regmap_reg_range(0x00, 0x01),
1352 /* global control register */
1353 regmap_reg_range(0x02, 0x0f),
1354
1355 /* port registers */
1356 regmap_reg_range(0x10, 0x1d),
1357 regmap_reg_range(0x1e, 0x1f),
1358 regmap_reg_range(0x20, 0x2d),
1359 regmap_reg_range(0x2e, 0x2f),
1360 regmap_reg_range(0x30, 0x39),
1361 regmap_reg_range(0x3f, 0x3f),
1362
1363 /* advanced control registers */
1364 regmap_reg_range(0x60, 0x6f),
1365 regmap_reg_range(0x70, 0x75),
1366 regmap_reg_range(0x76, 0x78),
1367 regmap_reg_range(0x79, 0x7a),
1368 regmap_reg_range(0x7b, 0x83),
1369 regmap_reg_range(0x8e, 0x99),
1370 regmap_reg_range(0x9a, 0xa5),
1371 regmap_reg_range(0xa6, 0xa6),
1372 regmap_reg_range(0xa7, 0xaa),
1373 regmap_reg_range(0xab, 0xae),
1374 regmap_reg_range(0xaf, 0xba),
1375 regmap_reg_range(0xbb, 0xbc),
1376 regmap_reg_range(0xbd, 0xbd),
1377 regmap_reg_range(0xc0, 0xc0),
1378 regmap_reg_range(0xc2, 0xc2),
1379 regmap_reg_range(0xc3, 0xc3),
1380 regmap_reg_range(0xc4, 0xc4),
1381 regmap_reg_range(0xc6, 0xc6),
1382};
1383
1384static const struct regmap_access_table ksz8873_register_set = {
1385 .yes_ranges = ksz8873_valid_regs,
1386 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1387};
1388
1389const struct ksz_chip_data ksz_switch_chips[] = {
1390 [KSZ8563] = {
1391 .chip_id = KSZ8563_CHIP_ID,
1392 .dev_name = "KSZ8563",
1393 .num_vlans = 4096,
1394 .num_alus = 4096,
1395 .num_statics = 16,
1396 .cpu_ports = 0x07, /* can be configured as cpu port */
1397 .port_cnt = 3, /* total port count */
1398 .port_nirqs = 3,
1399 .num_tx_queues = 4,
1400 .num_ipms = 8,
1401 .tc_cbs_supported = true,
1402 .ops = &ksz9477_dev_ops,
1403 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1404 .mib_names = ksz9477_mib_names,
1405 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1406 .reg_mib_cnt = MIB_COUNTER_NUM,
1407 .regs = ksz9477_regs,
1408 .masks = ksz9477_masks,
1409 .shifts = ksz9477_shifts,
1410 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1411 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1412 .supports_mii = {false, false, true},
1413 .supports_rmii = {false, false, true},
1414 .supports_rgmii = {false, false, true},
1415 .internal_phy = {true, true, false},
1416 .gbit_capable = {false, false, true},
1417 .ptp_capable = true,
1418 .wr_table = &ksz8563_register_set,
1419 .rd_table = &ksz8563_register_set,
1420 },
1421
1422 [KSZ8795] = {
1423 .chip_id = KSZ8795_CHIP_ID,
1424 .dev_name = "KSZ8795",
1425 .num_vlans = 4096,
1426 .num_alus = 0,
1427 .num_statics = 32,
1428 .cpu_ports = 0x10, /* can be configured as cpu port */
1429 .port_cnt = 5, /* total cpu and user ports */
1430 .num_tx_queues = 4,
1431 .num_ipms = 4,
1432 .ops = &ksz87xx_dev_ops,
1433 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1434 .ksz87xx_eee_link_erratum = true,
1435 .mib_names = ksz9477_mib_names,
1436 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1437 .reg_mib_cnt = MIB_COUNTER_NUM,
1438 .regs = ksz8795_regs,
1439 .masks = ksz8795_masks,
1440 .shifts = ksz8795_shifts,
1441 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1442 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1443 .supports_mii = {false, false, false, false, true},
1444 .supports_rmii = {false, false, false, false, true},
1445 .supports_rgmii = {false, false, false, false, true},
1446 .internal_phy = {true, true, true, true, false},
1447 },
1448
1449 [KSZ8794] = {
1450 /* WARNING
1451 * =======
1452 * KSZ8794 is similar to KSZ8795, except the port map
1453 * contains a gap between external and CPU ports, the
1454 * port map is NOT continuous. The per-port register
1455 * map is shifted accordingly too, i.e. registers at
1456 * offset 0x40 are NOT used on KSZ8794 and they ARE
1457 * used on KSZ8795 for external port 3.
1458 * external cpu
1459 * KSZ8794 0,1,2 4
1460 * KSZ8795 0,1,2,3 4
1461 * KSZ8765 0,1,2,3 4
1462 * port_cnt is configured as 5, even though it is 4
1463 */
1464 .chip_id = KSZ8794_CHIP_ID,
1465 .dev_name = "KSZ8794",
1466 .num_vlans = 4096,
1467 .num_alus = 0,
1468 .num_statics = 32,
1469 .cpu_ports = 0x10, /* can be configured as cpu port */
1470 .port_cnt = 5, /* total cpu and user ports */
1471 .num_tx_queues = 4,
1472 .num_ipms = 4,
1473 .ops = &ksz87xx_dev_ops,
1474 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1475 .ksz87xx_eee_link_erratum = true,
1476 .mib_names = ksz9477_mib_names,
1477 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1478 .reg_mib_cnt = MIB_COUNTER_NUM,
1479 .regs = ksz8795_regs,
1480 .masks = ksz8795_masks,
1481 .shifts = ksz8795_shifts,
1482 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1483 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1484 .supports_mii = {false, false, false, false, true},
1485 .supports_rmii = {false, false, false, false, true},
1486 .supports_rgmii = {false, false, false, false, true},
1487 .internal_phy = {true, true, true, false, false},
1488 },
1489
1490 [KSZ8765] = {
1491 .chip_id = KSZ8765_CHIP_ID,
1492 .dev_name = "KSZ8765",
1493 .num_vlans = 4096,
1494 .num_alus = 0,
1495 .num_statics = 32,
1496 .cpu_ports = 0x10, /* can be configured as cpu port */
1497 .port_cnt = 5, /* total cpu and user ports */
1498 .num_tx_queues = 4,
1499 .num_ipms = 4,
1500 .ops = &ksz87xx_dev_ops,
1501 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1502 .ksz87xx_eee_link_erratum = true,
1503 .mib_names = ksz9477_mib_names,
1504 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1505 .reg_mib_cnt = MIB_COUNTER_NUM,
1506 .regs = ksz8795_regs,
1507 .masks = ksz8795_masks,
1508 .shifts = ksz8795_shifts,
1509 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1510 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1511 .supports_mii = {false, false, false, false, true},
1512 .supports_rmii = {false, false, false, false, true},
1513 .supports_rgmii = {false, false, false, false, true},
1514 .internal_phy = {true, true, true, true, false},
1515 },
1516
1517 [KSZ88X3] = {
1518 .chip_id = KSZ88X3_CHIP_ID,
1519 .dev_name = "KSZ8863/KSZ8873",
1520 .num_vlans = 16,
1521 .num_alus = 0,
1522 .num_statics = 8,
1523 .cpu_ports = 0x4, /* can be configured as cpu port */
1524 .port_cnt = 3,
1525 .num_tx_queues = 4,
1526 .num_ipms = 4,
1527 .ops = &ksz88xx_dev_ops,
1528 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1529 .mib_names = ksz88xx_mib_names,
1530 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1531 .reg_mib_cnt = MIB_COUNTER_NUM,
1532 .regs = ksz8863_regs,
1533 .masks = ksz8863_masks,
1534 .shifts = ksz8863_shifts,
1535 .supports_mii = {false, false, true},
1536 .supports_rmii = {false, false, true},
1537 .internal_phy = {true, true, false},
1538 .wr_table = &ksz8873_register_set,
1539 .rd_table = &ksz8873_register_set,
1540 },
1541
1542 [KSZ8864] = {
1543 /* WARNING
1544 * =======
1545 * KSZ8864 is similar to KSZ8895, except the first port
1546 * does not exist.
1547 * external cpu
1548 * KSZ8864 1,2,3 4
1549 * KSZ8895 0,1,2,3 4
1550 * port_cnt is configured as 5, even though it is 4
1551 */
1552 .chip_id = KSZ8864_CHIP_ID,
1553 .dev_name = "KSZ8864",
1554 .num_vlans = 4096,
1555 .num_alus = 0,
1556 .num_statics = 32,
1557 .cpu_ports = 0x10, /* can be configured as cpu port */
1558 .port_cnt = 5, /* total cpu and user ports */
1559 .num_tx_queues = 4,
1560 .num_ipms = 4,
1561 .ops = &ksz88xx_dev_ops,
1562 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1563 .mib_names = ksz88xx_mib_names,
1564 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1565 .reg_mib_cnt = MIB_COUNTER_NUM,
1566 .regs = ksz8895_regs,
1567 .masks = ksz8895_masks,
1568 .shifts = ksz8895_shifts,
1569 .supports_mii = {false, false, false, false, true},
1570 .supports_rmii = {false, false, false, false, true},
1571 .internal_phy = {false, true, true, true, false},
1572 },
1573
1574 [KSZ8895] = {
1575 .chip_id = KSZ8895_CHIP_ID,
1576 .dev_name = "KSZ8895",
1577 .num_vlans = 4096,
1578 .num_alus = 0,
1579 .num_statics = 32,
1580 .cpu_ports = 0x10, /* can be configured as cpu port */
1581 .port_cnt = 5, /* total cpu and user ports */
1582 .num_tx_queues = 4,
1583 .num_ipms = 4,
1584 .ops = &ksz88xx_dev_ops,
1585 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1586 .mib_names = ksz88xx_mib_names,
1587 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1588 .reg_mib_cnt = MIB_COUNTER_NUM,
1589 .regs = ksz8895_regs,
1590 .masks = ksz8895_masks,
1591 .shifts = ksz8895_shifts,
1592 .supports_mii = {false, false, false, false, true},
1593 .supports_rmii = {false, false, false, false, true},
1594 .internal_phy = {true, true, true, true, false},
1595 },
1596
1597 [KSZ9477] = {
1598 .chip_id = KSZ9477_CHIP_ID,
1599 .dev_name = "KSZ9477",
1600 .num_vlans = 4096,
1601 .num_alus = 4096,
1602 .num_statics = 16,
1603 .cpu_ports = 0x7F, /* can be configured as cpu port */
1604 .port_cnt = 7, /* total physical port count */
1605 .port_nirqs = 4,
1606 .num_tx_queues = 4,
1607 .num_ipms = 8,
1608 .tc_cbs_supported = true,
1609 .ops = &ksz9477_dev_ops,
1610 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1611 .phy_errata_9477 = true,
1612 .mib_names = ksz9477_mib_names,
1613 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1614 .reg_mib_cnt = MIB_COUNTER_NUM,
1615 .regs = ksz9477_regs,
1616 .masks = ksz9477_masks,
1617 .shifts = ksz9477_shifts,
1618 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1619 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1620 .supports_mii = {false, false, false, false,
1621 false, true, false},
1622 .supports_rmii = {false, false, false, false,
1623 false, true, false},
1624 .supports_rgmii = {false, false, false, false,
1625 false, true, false},
1626 .internal_phy = {true, true, true, true,
1627 true, false, false},
1628 .gbit_capable = {true, true, true, true, true, true, true},
1629 .ptp_capable = true,
1630 .sgmii_port = 7,
1631 .wr_table = &ksz9477_register_set,
1632 .rd_table = &ksz9477_register_set,
1633 },
1634
1635 [KSZ9896] = {
1636 .chip_id = KSZ9896_CHIP_ID,
1637 .dev_name = "KSZ9896",
1638 .num_vlans = 4096,
1639 .num_alus = 4096,
1640 .num_statics = 16,
1641 .cpu_ports = 0x3F, /* can be configured as cpu port */
1642 .port_cnt = 6, /* total physical port count */
1643 .port_nirqs = 2,
1644 .num_tx_queues = 4,
1645 .num_ipms = 8,
1646 .ops = &ksz9477_dev_ops,
1647 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1648 .phy_errata_9477 = true,
1649 .mib_names = ksz9477_mib_names,
1650 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1651 .reg_mib_cnt = MIB_COUNTER_NUM,
1652 .regs = ksz9477_regs,
1653 .masks = ksz9477_masks,
1654 .shifts = ksz9477_shifts,
1655 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1656 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1657 .supports_mii = {false, false, false, false,
1658 false, true},
1659 .supports_rmii = {false, false, false, false,
1660 false, true},
1661 .supports_rgmii = {false, false, false, false,
1662 false, true},
1663 .internal_phy = {true, true, true, true,
1664 true, false},
1665 .gbit_capable = {true, true, true, true, true, true},
1666 .wr_table = &ksz9896_register_set,
1667 .rd_table = &ksz9896_register_set,
1668 },
1669
1670 [KSZ9897] = {
1671 .chip_id = KSZ9897_CHIP_ID,
1672 .dev_name = "KSZ9897",
1673 .num_vlans = 4096,
1674 .num_alus = 4096,
1675 .num_statics = 16,
1676 .cpu_ports = 0x7F, /* can be configured as cpu port */
1677 .port_cnt = 7, /* total physical port count */
1678 .port_nirqs = 2,
1679 .num_tx_queues = 4,
1680 .num_ipms = 8,
1681 .ops = &ksz9477_dev_ops,
1682 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1683 .phy_errata_9477 = true,
1684 .mib_names = ksz9477_mib_names,
1685 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1686 .reg_mib_cnt = MIB_COUNTER_NUM,
1687 .regs = ksz9477_regs,
1688 .masks = ksz9477_masks,
1689 .shifts = ksz9477_shifts,
1690 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1691 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1692 .supports_mii = {false, false, false, false,
1693 false, true, true},
1694 .supports_rmii = {false, false, false, false,
1695 false, true, true},
1696 .supports_rgmii = {false, false, false, false,
1697 false, true, true},
1698 .internal_phy = {true, true, true, true,
1699 true, false, false},
1700 .gbit_capable = {true, true, true, true, true, true, true},
1701 },
1702
1703 [KSZ9893] = {
1704 .chip_id = KSZ9893_CHIP_ID,
1705 .dev_name = "KSZ9893",
1706 .num_vlans = 4096,
1707 .num_alus = 4096,
1708 .num_statics = 16,
1709 .cpu_ports = 0x07, /* can be configured as cpu port */
1710 .port_cnt = 3, /* total port count */
1711 .port_nirqs = 2,
1712 .num_tx_queues = 4,
1713 .num_ipms = 8,
1714 .ops = &ksz9477_dev_ops,
1715 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1716 .mib_names = ksz9477_mib_names,
1717 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1718 .reg_mib_cnt = MIB_COUNTER_NUM,
1719 .regs = ksz9477_regs,
1720 .masks = ksz9477_masks,
1721 .shifts = ksz9477_shifts,
1722 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1723 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1724 .supports_mii = {false, false, true},
1725 .supports_rmii = {false, false, true},
1726 .supports_rgmii = {false, false, true},
1727 .internal_phy = {true, true, false},
1728 .gbit_capable = {true, true, true},
1729 },
1730
1731 [KSZ9563] = {
1732 .chip_id = KSZ9563_CHIP_ID,
1733 .dev_name = "KSZ9563",
1734 .num_vlans = 4096,
1735 .num_alus = 4096,
1736 .num_statics = 16,
1737 .cpu_ports = 0x07, /* can be configured as cpu port */
1738 .port_cnt = 3, /* total port count */
1739 .port_nirqs = 3,
1740 .num_tx_queues = 4,
1741 .num_ipms = 8,
1742 .tc_cbs_supported = true,
1743 .ops = &ksz9477_dev_ops,
1744 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1745 .mib_names = ksz9477_mib_names,
1746 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1747 .reg_mib_cnt = MIB_COUNTER_NUM,
1748 .regs = ksz9477_regs,
1749 .masks = ksz9477_masks,
1750 .shifts = ksz9477_shifts,
1751 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1752 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1753 .supports_mii = {false, false, true},
1754 .supports_rmii = {false, false, true},
1755 .supports_rgmii = {false, false, true},
1756 .internal_phy = {true, true, false},
1757 .gbit_capable = {true, true, true},
1758 .ptp_capable = true,
1759 },
1760
1761 [KSZ8567] = {
1762 .chip_id = KSZ8567_CHIP_ID,
1763 .dev_name = "KSZ8567",
1764 .num_vlans = 4096,
1765 .num_alus = 4096,
1766 .num_statics = 16,
1767 .cpu_ports = 0x7F, /* can be configured as cpu port */
1768 .port_cnt = 7, /* total port count */
1769 .port_nirqs = 3,
1770 .num_tx_queues = 4,
1771 .num_ipms = 8,
1772 .tc_cbs_supported = true,
1773 .ops = &ksz9477_dev_ops,
1774 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1775 .phy_errata_9477 = true,
1776 .mib_names = ksz9477_mib_names,
1777 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1778 .reg_mib_cnt = MIB_COUNTER_NUM,
1779 .regs = ksz9477_regs,
1780 .masks = ksz9477_masks,
1781 .shifts = ksz9477_shifts,
1782 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1783 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1784 .supports_mii = {false, false, false, false,
1785 false, true, true},
1786 .supports_rmii = {false, false, false, false,
1787 false, true, true},
1788 .supports_rgmii = {false, false, false, false,
1789 false, true, true},
1790 .internal_phy = {true, true, true, true,
1791 true, false, false},
1792 .gbit_capable = {false, false, false, false, false,
1793 true, true},
1794 .ptp_capable = true,
1795 },
1796
1797 [KSZ9567] = {
1798 .chip_id = KSZ9567_CHIP_ID,
1799 .dev_name = "KSZ9567",
1800 .num_vlans = 4096,
1801 .num_alus = 4096,
1802 .num_statics = 16,
1803 .cpu_ports = 0x7F, /* can be configured as cpu port */
1804 .port_cnt = 7, /* total physical port count */
1805 .port_nirqs = 3,
1806 .num_tx_queues = 4,
1807 .num_ipms = 8,
1808 .tc_cbs_supported = true,
1809 .ops = &ksz9477_dev_ops,
1810 .mib_names = ksz9477_mib_names,
1811 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1812 .reg_mib_cnt = MIB_COUNTER_NUM,
1813 .regs = ksz9477_regs,
1814 .masks = ksz9477_masks,
1815 .shifts = ksz9477_shifts,
1816 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1817 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1818 .supports_mii = {false, false, false, false,
1819 false, true, true},
1820 .supports_rmii = {false, false, false, false,
1821 false, true, true},
1822 .supports_rgmii = {false, false, false, false,
1823 false, true, true},
1824 .internal_phy = {true, true, true, true,
1825 true, false, false},
1826 .gbit_capable = {true, true, true, true, true, true, true},
1827 .ptp_capable = true,
1828 },
1829
1830 [LAN9370] = {
1831 .chip_id = LAN9370_CHIP_ID,
1832 .dev_name = "LAN9370",
1833 .num_vlans = 4096,
1834 .num_alus = 1024,
1835 .num_statics = 256,
1836 .cpu_ports = 0x10, /* can be configured as cpu port */
1837 .port_cnt = 5, /* total physical port count */
1838 .port_nirqs = 6,
1839 .num_tx_queues = 8,
1840 .num_ipms = 8,
1841 .tc_cbs_supported = true,
1842 .phy_side_mdio_supported = true,
1843 .ops = &lan937x_dev_ops,
1844 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1845 .mib_names = ksz9477_mib_names,
1846 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1847 .reg_mib_cnt = MIB_COUNTER_NUM,
1848 .regs = ksz9477_regs,
1849 .masks = lan937x_masks,
1850 .shifts = lan937x_shifts,
1851 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1852 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1853 .supports_mii = {false, false, false, false, true},
1854 .supports_rmii = {false, false, false, false, true},
1855 .supports_rgmii = {false, false, false, false, true},
1856 .internal_phy = {true, true, true, true, false},
1857 .ptp_capable = true,
1858 },
1859
1860 [LAN9371] = {
1861 .chip_id = LAN9371_CHIP_ID,
1862 .dev_name = "LAN9371",
1863 .num_vlans = 4096,
1864 .num_alus = 1024,
1865 .num_statics = 256,
1866 .cpu_ports = 0x30, /* can be configured as cpu port */
1867 .port_cnt = 6, /* total physical port count */
1868 .port_nirqs = 6,
1869 .num_tx_queues = 8,
1870 .num_ipms = 8,
1871 .tc_cbs_supported = true,
1872 .phy_side_mdio_supported = true,
1873 .ops = &lan937x_dev_ops,
1874 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1875 .mib_names = ksz9477_mib_names,
1876 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1877 .reg_mib_cnt = MIB_COUNTER_NUM,
1878 .regs = ksz9477_regs,
1879 .masks = lan937x_masks,
1880 .shifts = lan937x_shifts,
1881 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1882 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1883 .supports_mii = {false, false, false, false, true, true},
1884 .supports_rmii = {false, false, false, false, true, true},
1885 .supports_rgmii = {false, false, false, false, true, true},
1886 .internal_phy = {true, true, true, true, false, false},
1887 .ptp_capable = true,
1888 },
1889
1890 [LAN9372] = {
1891 .chip_id = LAN9372_CHIP_ID,
1892 .dev_name = "LAN9372",
1893 .num_vlans = 4096,
1894 .num_alus = 1024,
1895 .num_statics = 256,
1896 .cpu_ports = 0x30, /* can be configured as cpu port */
1897 .port_cnt = 8, /* total physical port count */
1898 .port_nirqs = 6,
1899 .num_tx_queues = 8,
1900 .num_ipms = 8,
1901 .tc_cbs_supported = true,
1902 .phy_side_mdio_supported = true,
1903 .ops = &lan937x_dev_ops,
1904 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1905 .mib_names = ksz9477_mib_names,
1906 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1907 .reg_mib_cnt = MIB_COUNTER_NUM,
1908 .regs = ksz9477_regs,
1909 .masks = lan937x_masks,
1910 .shifts = lan937x_shifts,
1911 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1912 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1913 .supports_mii = {false, false, false, false,
1914 true, true, false, false},
1915 .supports_rmii = {false, false, false, false,
1916 true, true, false, false},
1917 .supports_rgmii = {false, false, false, false,
1918 true, true, false, false},
1919 .internal_phy = {true, true, true, true,
1920 false, false, true, true},
1921 .ptp_capable = true,
1922 },
1923
1924 [LAN9373] = {
1925 .chip_id = LAN9373_CHIP_ID,
1926 .dev_name = "LAN9373",
1927 .num_vlans = 4096,
1928 .num_alus = 1024,
1929 .num_statics = 256,
1930 .cpu_ports = 0x38, /* can be configured as cpu port */
1931 .port_cnt = 5, /* total physical port count */
1932 .port_nirqs = 6,
1933 .num_tx_queues = 8,
1934 .num_ipms = 8,
1935 .tc_cbs_supported = true,
1936 .phy_side_mdio_supported = true,
1937 .ops = &lan937x_dev_ops,
1938 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1939 .mib_names = ksz9477_mib_names,
1940 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1941 .reg_mib_cnt = MIB_COUNTER_NUM,
1942 .regs = ksz9477_regs,
1943 .masks = lan937x_masks,
1944 .shifts = lan937x_shifts,
1945 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1946 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1947 .supports_mii = {false, false, false, false,
1948 true, true, false, false},
1949 .supports_rmii = {false, false, false, false,
1950 true, true, false, false},
1951 .supports_rgmii = {false, false, false, false,
1952 true, true, false, false},
1953 .internal_phy = {true, true, true, false,
1954 false, false, true, true},
1955 .ptp_capable = true,
1956 },
1957
1958 [LAN9374] = {
1959 .chip_id = LAN9374_CHIP_ID,
1960 .dev_name = "LAN9374",
1961 .num_vlans = 4096,
1962 .num_alus = 1024,
1963 .num_statics = 256,
1964 .cpu_ports = 0x30, /* can be configured as cpu port */
1965 .port_cnt = 8, /* total physical port count */
1966 .port_nirqs = 6,
1967 .num_tx_queues = 8,
1968 .num_ipms = 8,
1969 .tc_cbs_supported = true,
1970 .phy_side_mdio_supported = true,
1971 .ops = &lan937x_dev_ops,
1972 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1973 .mib_names = ksz9477_mib_names,
1974 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1975 .reg_mib_cnt = MIB_COUNTER_NUM,
1976 .regs = ksz9477_regs,
1977 .masks = lan937x_masks,
1978 .shifts = lan937x_shifts,
1979 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1980 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1981 .supports_mii = {false, false, false, false,
1982 true, true, false, false},
1983 .supports_rmii = {false, false, false, false,
1984 true, true, false, false},
1985 .supports_rgmii = {false, false, false, false,
1986 true, true, false, false},
1987 .internal_phy = {true, true, true, true,
1988 false, false, true, true},
1989 .ptp_capable = true,
1990 },
1991
1992 [LAN9646] = {
1993 .chip_id = LAN9646_CHIP_ID,
1994 .dev_name = "LAN9646",
1995 .num_vlans = 4096,
1996 .num_alus = 4096,
1997 .num_statics = 16,
1998 .cpu_ports = 0x7F, /* can be configured as cpu port */
1999 .port_cnt = 7, /* total physical port count */
2000 .port_nirqs = 4,
2001 .num_tx_queues = 4,
2002 .num_ipms = 8,
2003 .ops = &ksz9477_dev_ops,
2004 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
2005 .phy_errata_9477 = true,
2006 .mib_names = ksz9477_mib_names,
2007 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2008 .reg_mib_cnt = MIB_COUNTER_NUM,
2009 .regs = ksz9477_regs,
2010 .masks = ksz9477_masks,
2011 .shifts = ksz9477_shifts,
2012 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2013 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2014 .supports_mii = {false, false, false, false,
2015 false, true, true},
2016 .supports_rmii = {false, false, false, false,
2017 false, true, true},
2018 .supports_rgmii = {false, false, false, false,
2019 false, true, true},
2020 .internal_phy = {true, true, true, true,
2021 true, false, false},
2022 .gbit_capable = {true, true, true, true, true, true, true},
2023 .sgmii_port = 7,
2024 .wr_table = &ksz9477_register_set,
2025 .rd_table = &ksz9477_register_set,
2026 },
2027};
2028EXPORT_SYMBOL_GPL(ksz_switch_chips);
2029
2030static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
2031{
2032 int i;
2033
2034 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
2035 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
2036
2037 if (chip->chip_id == prod_num)
2038 return chip;
2039 }
2040
2041 return NULL;
2042}
2043
2044static int ksz_check_device_id(struct ksz_device *dev)
2045{
2046 const struct ksz_chip_data *expected_chip_data;
2047 u32 expected_chip_id;
2048
2049 if (dev->pdata) {
2050 expected_chip_id = dev->pdata->chip_id;
2051 expected_chip_data = ksz_lookup_info(prod_num: expected_chip_id);
2052 if (WARN_ON(!expected_chip_data))
2053 return -ENODEV;
2054 } else {
2055 expected_chip_data = of_device_get_match_data(dev: dev->dev);
2056 expected_chip_id = expected_chip_data->chip_id;
2057 }
2058
2059 if (expected_chip_id != dev->chip_id) {
2060 dev_err(dev->dev,
2061 "Device tree specifies chip %s but found %s, please fix it!\n",
2062 expected_chip_data->dev_name, dev->info->dev_name);
2063 return -ENODEV;
2064 }
2065
2066 return 0;
2067}
2068
2069static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
2070 struct phylink_config *config)
2071{
2072 struct ksz_device *dev = ds->priv;
2073
2074 if (dev->info->supports_mii[port])
2075 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
2076
2077 if (dev->info->supports_rmii[port])
2078 __set_bit(PHY_INTERFACE_MODE_RMII,
2079 config->supported_interfaces);
2080
2081 if (dev->info->supports_rgmii[port])
2082 phy_interface_set_rgmii(intf: config->supported_interfaces);
2083
2084 if (dev->info->internal_phy[port]) {
2085 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2086 config->supported_interfaces);
2087 /* Compatibility for phylib's default interface type when the
2088 * phy-mode property is absent
2089 */
2090 __set_bit(PHY_INTERFACE_MODE_GMII,
2091 config->supported_interfaces);
2092 }
2093
2094 if (dev->dev_ops->get_caps)
2095 dev->dev_ops->get_caps(dev, port, config);
2096
2097 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) {
2098 memcpy(config->lpi_interfaces, config->supported_interfaces,
2099 sizeof(config->lpi_interfaces));
2100
2101 config->lpi_capabilities = MAC_100FD;
2102 if (dev->info->gbit_capable[port])
2103 config->lpi_capabilities |= MAC_1000FD;
2104
2105 /* EEE is fully operational */
2106 config->eee_enabled_default = true;
2107 }
2108}
2109
2110void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2111{
2112 struct ethtool_pause_stats *pstats;
2113 struct rtnl_link_stats64 *stats;
2114 struct ksz_stats_raw *raw;
2115 struct ksz_port_mib *mib;
2116 int ret;
2117
2118 mib = &dev->ports[port].mib;
2119 stats = &mib->stats64;
2120 pstats = &mib->pause_stats;
2121 raw = (struct ksz_stats_raw *)mib->counters;
2122
2123 spin_lock(lock: &mib->stats64_lock);
2124
2125 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2126 raw->rx_pause;
2127 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2128 raw->tx_pause;
2129
2130 /* HW counters are counting bytes + FCS which is not acceptable
2131 * for rtnl_link_stats64 interface
2132 */
2133 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2134 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2135
2136 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2137 raw->rx_oversize;
2138
2139 stats->rx_crc_errors = raw->rx_crc_err;
2140 stats->rx_frame_errors = raw->rx_align_err;
2141 stats->rx_dropped = raw->rx_discards;
2142 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2143 stats->rx_frame_errors + stats->rx_dropped;
2144
2145 stats->tx_window_errors = raw->tx_late_col;
2146 stats->tx_fifo_errors = raw->tx_discards;
2147 stats->tx_aborted_errors = raw->tx_exc_col;
2148 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2149 stats->tx_aborted_errors;
2150
2151 stats->multicast = raw->rx_mcast;
2152 stats->collisions = raw->tx_total_col;
2153
2154 pstats->tx_pause_frames = raw->tx_pause;
2155 pstats->rx_pause_frames = raw->rx_pause;
2156
2157 spin_unlock(lock: &mib->stats64_lock);
2158
2159 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) {
2160 ret = ksz9477_errata_monitor(dev, port, tx_late_col: raw->tx_late_col);
2161 if (ret)
2162 dev_err(dev->dev, "Failed to monitor transmission halt\n");
2163 }
2164}
2165
2166void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2167{
2168 struct ethtool_pause_stats *pstats;
2169 struct rtnl_link_stats64 *stats;
2170 struct ksz88xx_stats_raw *raw;
2171 struct ksz_port_mib *mib;
2172
2173 mib = &dev->ports[port].mib;
2174 stats = &mib->stats64;
2175 pstats = &mib->pause_stats;
2176 raw = (struct ksz88xx_stats_raw *)mib->counters;
2177
2178 spin_lock(lock: &mib->stats64_lock);
2179
2180 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2181 raw->rx_pause;
2182 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2183 raw->tx_pause;
2184
2185 /* HW counters are counting bytes + FCS which is not acceptable
2186 * for rtnl_link_stats64 interface
2187 */
2188 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2189 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2190
2191 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2192 raw->rx_oversize;
2193
2194 stats->rx_crc_errors = raw->rx_crc_err;
2195 stats->rx_frame_errors = raw->rx_align_err;
2196 stats->rx_dropped = raw->rx_discards;
2197 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2198 stats->rx_frame_errors + stats->rx_dropped;
2199
2200 stats->tx_window_errors = raw->tx_late_col;
2201 stats->tx_fifo_errors = raw->tx_discards;
2202 stats->tx_aborted_errors = raw->tx_exc_col;
2203 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2204 stats->tx_aborted_errors;
2205
2206 stats->multicast = raw->rx_mcast;
2207 stats->collisions = raw->tx_total_col;
2208
2209 pstats->tx_pause_frames = raw->tx_pause;
2210 pstats->rx_pause_frames = raw->rx_pause;
2211
2212 spin_unlock(lock: &mib->stats64_lock);
2213}
2214
2215static void ksz_get_stats64(struct dsa_switch *ds, int port,
2216 struct rtnl_link_stats64 *s)
2217{
2218 struct ksz_device *dev = ds->priv;
2219 struct ksz_port_mib *mib;
2220
2221 mib = &dev->ports[port].mib;
2222
2223 spin_lock(lock: &mib->stats64_lock);
2224 memcpy(s, &mib->stats64, sizeof(*s));
2225 spin_unlock(lock: &mib->stats64_lock);
2226}
2227
2228static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2229 struct ethtool_pause_stats *pause_stats)
2230{
2231 struct ksz_device *dev = ds->priv;
2232 struct ksz_port_mib *mib;
2233
2234 mib = &dev->ports[port].mib;
2235
2236 spin_lock(lock: &mib->stats64_lock);
2237 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2238 spin_unlock(lock: &mib->stats64_lock);
2239}
2240
2241static void ksz_get_strings(struct dsa_switch *ds, int port,
2242 u32 stringset, uint8_t *buf)
2243{
2244 struct ksz_device *dev = ds->priv;
2245 int i;
2246
2247 if (stringset != ETH_SS_STATS)
2248 return;
2249
2250 for (i = 0; i < dev->info->mib_cnt; i++)
2251 ethtool_puts(data: &buf, str: dev->info->mib_names[i].string);
2252}
2253
2254/**
2255 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
2256 * isolation settings.
2257 * @dev: A pointer to the struct ksz_device representing the device.
2258 * @port: The port number to adjust.
2259 *
2260 * This function dynamically adjusts the port membership configuration for a
2261 * specified port and other device ports, based on Spanning Tree Protocol (STP)
2262 * states and port isolation settings. Each port, including the CPU port, has a
2263 * membership register, represented as a bitfield, where each bit corresponds
2264 * to a port number. A set bit indicates permission to forward frames to that
2265 * port. This function iterates over all ports, updating the membership register
2266 * to reflect current forwarding permissions:
2267 *
2268 * 1. Forwards frames only to ports that are part of the same bridge group and
2269 * in the BR_STATE_FORWARDING state.
2270 * 2. Takes into account the isolation status of ports; ports in the
2271 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2272 * frames to each other, even if they are in the same bridge group.
2273 * 3. Ensures that the CPU port is included in the membership based on its
2274 * upstream port configuration, allowing for management and control traffic
2275 * to flow as required.
2276 */
2277static void ksz_update_port_member(struct ksz_device *dev, int port)
2278{
2279 struct ksz_port *p = &dev->ports[port];
2280 struct dsa_switch *ds = dev->ds;
2281 u8 port_member = 0, cpu_port;
2282 const struct dsa_port *dp;
2283 int i, j;
2284
2285 if (!dsa_is_user_port(ds, p: port))
2286 return;
2287
2288 dp = dsa_to_port(ds, p: port);
2289 cpu_port = BIT(dsa_upstream_port(ds, port));
2290
2291 for (i = 0; i < ds->num_ports; i++) {
2292 const struct dsa_port *other_dp = dsa_to_port(ds, p: i);
2293 struct ksz_port *other_p = &dev->ports[i];
2294 u8 val = 0;
2295
2296 if (!dsa_is_user_port(ds, p: i))
2297 continue;
2298 if (port == i)
2299 continue;
2300 if (!dsa_port_bridge_same(a: dp, b: other_dp))
2301 continue;
2302 if (other_p->stp_state != BR_STATE_FORWARDING)
2303 continue;
2304
2305 /* At this point we know that "port" and "other" port [i] are in
2306 * the same bridge group and that "other" port [i] is in
2307 * forwarding stp state. If "port" is also in forwarding stp
2308 * state, we can allow forwarding from port [port] to port [i].
2309 * Except if both ports are isolated.
2310 */
2311 if (p->stp_state == BR_STATE_FORWARDING &&
2312 !(p->isolated && other_p->isolated)) {
2313 val |= BIT(port);
2314 port_member |= BIT(i);
2315 }
2316
2317 /* Retain port [i]'s relationship to other ports than [port] */
2318 for (j = 0; j < ds->num_ports; j++) {
2319 const struct dsa_port *third_dp;
2320 struct ksz_port *third_p;
2321
2322 if (j == i)
2323 continue;
2324 if (j == port)
2325 continue;
2326 if (!dsa_is_user_port(ds, p: j))
2327 continue;
2328 third_p = &dev->ports[j];
2329 if (third_p->stp_state != BR_STATE_FORWARDING)
2330 continue;
2331
2332 third_dp = dsa_to_port(ds, p: j);
2333
2334 /* Now we updating relation of the "other" port [i] to
2335 * the "third" port [j]. We already know that "other"
2336 * port [i] is in forwarding stp state and that "third"
2337 * port [j] is in forwarding stp state too.
2338 * We need to check if "other" port [i] and "third" port
2339 * [j] are in the same bridge group and not isolated
2340 * before allowing forwarding from port [i] to port [j].
2341 */
2342 if (dsa_port_bridge_same(a: other_dp, b: third_dp) &&
2343 !(other_p->isolated && third_p->isolated))
2344 val |= BIT(j);
2345 }
2346
2347 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2348 }
2349
2350 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2351}
2352
2353static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2354{
2355 struct ksz_device *dev = bus->priv;
2356 u16 val;
2357 int ret;
2358
2359 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2360 if (ret < 0)
2361 return ret;
2362
2363 return val;
2364}
2365
2366static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2367 u16 val)
2368{
2369 struct ksz_device *dev = bus->priv;
2370
2371 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2372}
2373
2374/**
2375 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2376 * @bus: MDIO bus structure.
2377 * @addr: PHY address on the parent MDIO bus.
2378 * @regnum: Register number to read.
2379 *
2380 * This function provides a direct read operation on the parent MDIO bus for
2381 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2382 * to retrieve data from the PHY registers at the specified address and register
2383 * number.
2384 *
2385 * Return: Value of the PHY register, or a negative error code on failure.
2386 */
2387static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2388{
2389 struct ksz_device *dev = bus->priv;
2390
2391 return mdiobus_read_nested(bus: dev->parent_mdio_bus, addr, regnum);
2392}
2393
2394/**
2395 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2396 * @bus: MDIO bus structure.
2397 * @addr: PHY address on the parent MDIO bus.
2398 * @regnum: Register number to write to.
2399 * @val: Value to write to the PHY register.
2400 *
2401 * This function provides a direct write operation on the parent MDIO bus for
2402 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2403 * to modify the PHY register values at the specified address.
2404 *
2405 * Return: 0 on success, or a negative error code on failure.
2406 */
2407static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2408 u16 val)
2409{
2410 struct ksz_device *dev = bus->priv;
2411
2412 return mdiobus_write_nested(bus: dev->parent_mdio_bus, addr, regnum, val);
2413}
2414
2415/**
2416 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2417 * @dev: Pointer to device structure.
2418 * @addr: PHY address to map to a port.
2419 *
2420 * This function finds the corresponding switch port for a given PHY address by
2421 * iterating over all user ports on the device. It checks if a port's PHY
2422 * address in `phy_addr_map` matches the specified address and if the port
2423 * contains an internal PHY. If a match is found, the index of the port is
2424 * returned.
2425 *
2426 * Return: Port index on success, or -EINVAL if no matching port is found.
2427 */
2428static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2429{
2430 struct dsa_switch *ds = dev->ds;
2431 struct dsa_port *dp;
2432
2433 dsa_switch_for_each_user_port(dp, ds) {
2434 if (dev->info->internal_phy[dp->index] &&
2435 dev->phy_addr_map[dp->index] == addr)
2436 return dp->index;
2437 }
2438
2439 return -EINVAL;
2440}
2441
2442/**
2443 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2444 * @dev: Pointer to the KSZ device structure.
2445 *
2446 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2447 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2448 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2449 *
2450 * Return: 0 on success, or a negative error code on failure.
2451 */
2452static int ksz_irq_phy_setup(struct ksz_device *dev)
2453{
2454 struct dsa_switch *ds = dev->ds;
2455 int phy, port;
2456 int irq;
2457 int ret;
2458
2459 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2460 if (BIT(phy) & ds->phys_mii_mask) {
2461 port = ksz_phy_addr_to_port(dev, addr: phy);
2462 if (port < 0) {
2463 ret = port;
2464 goto out;
2465 }
2466
2467 irq = irq_find_mapping(domain: dev->ports[port].pirq.domain,
2468 PORT_SRC_PHY_INT);
2469 if (irq < 0) {
2470 ret = irq;
2471 goto out;
2472 }
2473 ds->user_mii_bus->irq[phy] = irq;
2474 }
2475 }
2476 return 0;
2477out:
2478 while (phy--)
2479 if (BIT(phy) & ds->phys_mii_mask)
2480 irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
2481
2482 return ret;
2483}
2484
2485/**
2486 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2487 * @dev: Pointer to the KSZ device structure.
2488 *
2489 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2490 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2491 */
2492static void ksz_irq_phy_free(struct ksz_device *dev)
2493{
2494 struct dsa_switch *ds = dev->ds;
2495 int phy;
2496
2497 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2498 if (BIT(phy) & ds->phys_mii_mask)
2499 irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
2500}
2501
2502/**
2503 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2504 * @dev: pointer to the KSZ device structure
2505 * @bus: pointer to the MII bus structure
2506 * @mdio_np: pointer to the MDIO node in the device tree
2507 *
2508 * This function parses and validates PHY configurations for each user port
2509 * defined in the device tree for a KSZ switch device. It verifies that the
2510 * `phy-handle` properties are correctly set and that the internal PHYs match
2511 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2512 * all validations pass. Logs error messages for any mismatches or missing data.
2513 *
2514 * Return: 0 on success, or a negative error code on failure.
2515 */
2516static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2517 struct device_node *mdio_np)
2518{
2519 struct device_node *phy_node, *phy_parent_node;
2520 bool phys_are_valid = true;
2521 struct dsa_port *dp;
2522 u32 phy_addr;
2523 int ret;
2524
2525 dsa_switch_for_each_user_port(dp, dev->ds) {
2526 if (!dev->info->internal_phy[dp->index])
2527 continue;
2528
2529 phy_node = of_parse_phandle(np: dp->dn, phandle_name: "phy-handle", index: 0);
2530 if (!phy_node) {
2531 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2532 dp->index);
2533 phys_are_valid = false;
2534 continue;
2535 }
2536
2537 phy_parent_node = of_get_parent(node: phy_node);
2538 if (!phy_parent_node) {
2539 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2540 dp->index);
2541 phys_are_valid = false;
2542 } else if (phy_parent_node != mdio_np) {
2543 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2544 dp->index, mdio_np, phy_parent_node);
2545 phys_are_valid = false;
2546 } else {
2547 ret = of_property_read_u32(np: phy_node, propname: "reg", out_value: &phy_addr);
2548 if (ret < 0) {
2549 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2550 dp->index, ret);
2551 phys_are_valid = false;
2552 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2553 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2554 dp->index, dev->phy_addr_map[dp->index],
2555 phy_addr);
2556 phys_are_valid = false;
2557 } else {
2558 bus->phy_mask |= BIT(phy_addr);
2559 }
2560 }
2561
2562 of_node_put(node: phy_node);
2563 of_node_put(node: phy_parent_node);
2564 }
2565
2566 if (!phys_are_valid)
2567 return -EINVAL;
2568
2569 return 0;
2570}
2571
2572/**
2573 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2574 * @dev: Pointer to the KSZ device structure.
2575 *
2576 * This function sets up and registers an MDIO bus for the KSZ switch device,
2577 * allowing access to its internal PHYs. If the device supports side MDIO,
2578 * the function will configure the external MDIO controller specified by the
2579 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2580 * Otherwise, SPI or I2C access is set up for PHY access.
2581 *
2582 * Return: 0 on success, or a negative error code on failure.
2583 */
2584static int ksz_mdio_register(struct ksz_device *dev)
2585{
2586 struct device_node *parent_bus_node;
2587 struct mii_bus *parent_bus = NULL;
2588 struct dsa_switch *ds = dev->ds;
2589 struct device_node *mdio_np;
2590 struct mii_bus *bus;
2591 int ret, i;
2592
2593 mdio_np = of_get_child_by_name(node: dev->dev->of_node, name: "mdio");
2594 if (!mdio_np)
2595 return 0;
2596
2597 parent_bus_node = of_parse_phandle(np: mdio_np, phandle_name: "mdio-parent-bus", index: 0);
2598 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2599 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2600 ret = -EINVAL;
2601
2602 goto put_mdio_node;
2603 } else if (parent_bus_node) {
2604 parent_bus = of_mdio_find_bus(mdio_np: parent_bus_node);
2605 if (!parent_bus) {
2606 ret = -EPROBE_DEFER;
2607
2608 goto put_mdio_node;
2609 }
2610
2611 dev->parent_mdio_bus = parent_bus;
2612 }
2613
2614 bus = devm_mdiobus_alloc(dev: ds->dev);
2615 if (!bus) {
2616 ret = -ENOMEM;
2617 goto put_mdio_node;
2618 }
2619
2620 if (dev->dev_ops->mdio_bus_preinit) {
2621 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2622 if (ret)
2623 goto put_mdio_node;
2624 }
2625
2626 if (dev->dev_ops->create_phy_addr_map) {
2627 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2628 if (ret)
2629 goto put_mdio_node;
2630 } else {
2631 for (i = 0; i < dev->info->port_cnt; i++)
2632 dev->phy_addr_map[i] = i;
2633 }
2634
2635 bus->priv = dev;
2636 if (parent_bus) {
2637 bus->read = ksz_parent_mdio_read;
2638 bus->write = ksz_parent_mdio_write;
2639 bus->name = "KSZ side MDIO";
2640 snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "ksz-side-mdio-%d",
2641 ds->index);
2642 } else {
2643 bus->read = ksz_sw_mdio_read;
2644 bus->write = ksz_sw_mdio_write;
2645 bus->name = "ksz user smi";
2646 if (ds->dst->index != 0) {
2647 snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d-%d", ds->dst->index, ds->index);
2648 } else {
2649 snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d", ds->index);
2650 }
2651 }
2652
2653 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2654 if (ret)
2655 goto put_mdio_node;
2656
2657 ds->phys_mii_mask = bus->phy_mask;
2658 bus->parent = ds->dev;
2659
2660 ds->user_mii_bus = bus;
2661
2662 if (dev->irq > 0) {
2663 ret = ksz_irq_phy_setup(dev);
2664 if (ret)
2665 goto put_mdio_node;
2666 }
2667
2668 ret = devm_of_mdiobus_register(dev: ds->dev, mdio: bus, np: mdio_np);
2669 if (ret) {
2670 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2671 bus->id);
2672 if (dev->irq > 0)
2673 ksz_irq_phy_free(dev);
2674 }
2675
2676put_mdio_node:
2677 of_node_put(node: mdio_np);
2678 of_node_put(node: parent_bus_node);
2679
2680 return ret;
2681}
2682
2683static void ksz_irq_mask(struct irq_data *d)
2684{
2685 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2686
2687 kirq->masked |= BIT(d->hwirq);
2688}
2689
2690static void ksz_irq_unmask(struct irq_data *d)
2691{
2692 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2693
2694 kirq->masked &= ~BIT(d->hwirq);
2695}
2696
2697static void ksz_irq_bus_lock(struct irq_data *d)
2698{
2699 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2700
2701 mutex_lock(&kirq->dev->lock_irq);
2702}
2703
2704static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2705{
2706 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2707 struct ksz_device *dev = kirq->dev;
2708 int ret;
2709
2710 ret = ksz_write8(dev, reg: kirq->reg_mask, value: kirq->masked);
2711 if (ret)
2712 dev_err(dev->dev, "failed to change IRQ mask\n");
2713
2714 mutex_unlock(lock: &dev->lock_irq);
2715}
2716
2717static const struct irq_chip ksz_irq_chip = {
2718 .name = "ksz-irq",
2719 .irq_mask = ksz_irq_mask,
2720 .irq_unmask = ksz_irq_unmask,
2721 .irq_bus_lock = ksz_irq_bus_lock,
2722 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2723};
2724
2725static int ksz_irq_domain_map(struct irq_domain *d,
2726 unsigned int irq, irq_hw_number_t hwirq)
2727{
2728 irq_set_chip_data(irq, data: d->host_data);
2729 irq_set_chip_and_handler(irq, chip: &ksz_irq_chip, handle: handle_level_irq);
2730 irq_set_noprobe(irq);
2731
2732 return 0;
2733}
2734
2735static const struct irq_domain_ops ksz_irq_domain_ops = {
2736 .map = ksz_irq_domain_map,
2737 .xlate = irq_domain_xlate_twocell,
2738};
2739
2740static void ksz_irq_free(struct ksz_irq *kirq)
2741{
2742 int irq, virq;
2743
2744 free_irq(kirq->irq_num, kirq);
2745
2746 for (irq = 0; irq < kirq->nirqs; irq++) {
2747 virq = irq_find_mapping(domain: kirq->domain, hwirq: irq);
2748 irq_dispose_mapping(virq);
2749 }
2750
2751 irq_domain_remove(domain: kirq->domain);
2752}
2753
2754static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2755{
2756 struct ksz_irq *kirq = dev_id;
2757 unsigned int nhandled = 0;
2758 struct ksz_device *dev;
2759 unsigned int sub_irq;
2760 u8 data;
2761 int ret;
2762 u8 n;
2763
2764 dev = kirq->dev;
2765
2766 /* Read interrupt status register */
2767 ret = ksz_read8(dev, reg: kirq->reg_status, val: &data);
2768 if (ret)
2769 goto out;
2770
2771 for (n = 0; n < kirq->nirqs; ++n) {
2772 if (data & BIT(n)) {
2773 sub_irq = irq_find_mapping(domain: kirq->domain, hwirq: n);
2774 handle_nested_irq(irq: sub_irq);
2775 ++nhandled;
2776 }
2777 }
2778out:
2779 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2780}
2781
2782static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2783{
2784 int ret, n;
2785
2786 kirq->dev = dev;
2787 kirq->masked = ~0;
2788
2789 kirq->domain = irq_domain_create_simple(of_fwnode_handle(dev->dev->of_node),
2790 size: kirq->nirqs, first_irq: 0,
2791 ops: &ksz_irq_domain_ops, host_data: kirq);
2792 if (!kirq->domain)
2793 return -ENOMEM;
2794
2795 for (n = 0; n < kirq->nirqs; n++)
2796 irq_create_mapping(domain: kirq->domain, hwirq: n);
2797
2798 ret = request_threaded_irq(irq: kirq->irq_num, NULL, thread_fn: ksz_irq_thread_fn,
2799 IRQF_ONESHOT, name: kirq->name, dev: kirq);
2800 if (ret)
2801 goto out;
2802
2803 return 0;
2804
2805out:
2806 ksz_irq_free(kirq);
2807
2808 return ret;
2809}
2810
2811static int ksz_girq_setup(struct ksz_device *dev)
2812{
2813 struct ksz_irq *girq = &dev->girq;
2814
2815 girq->nirqs = dev->info->port_cnt;
2816 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2817 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2818 snprintf(buf: girq->name, size: sizeof(girq->name), fmt: "global_port_irq");
2819
2820 girq->irq_num = dev->irq;
2821
2822 return ksz_irq_common_setup(dev, kirq: girq);
2823}
2824
2825static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2826{
2827 struct ksz_irq *pirq = &dev->ports[p].pirq;
2828
2829 pirq->nirqs = dev->info->port_nirqs;
2830 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2831 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2832 snprintf(buf: pirq->name, size: sizeof(pirq->name), fmt: "port_irq-%d", p);
2833
2834 pirq->irq_num = irq_find_mapping(domain: dev->girq.domain, hwirq: p);
2835 if (pirq->irq_num < 0)
2836 return pirq->irq_num;
2837
2838 return ksz_irq_common_setup(dev, kirq: pirq);
2839}
2840
2841static int ksz_parse_drive_strength(struct ksz_device *dev);
2842
2843static int ksz_setup(struct dsa_switch *ds)
2844{
2845 struct ksz_device *dev = ds->priv;
2846 struct dsa_port *dp;
2847 struct ksz_port *p;
2848 const u16 *regs;
2849 int ret;
2850
2851 regs = dev->info->regs;
2852
2853 dev->vlan_cache = devm_kcalloc(dev: dev->dev, n: sizeof(struct vlan_table),
2854 size: dev->info->num_vlans, GFP_KERNEL);
2855 if (!dev->vlan_cache)
2856 return -ENOMEM;
2857
2858 ret = dev->dev_ops->reset(dev);
2859 if (ret) {
2860 dev_err(ds->dev, "failed to reset switch\n");
2861 return ret;
2862 }
2863
2864 ret = ksz_parse_drive_strength(dev);
2865 if (ret)
2866 return ret;
2867
2868 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) {
2869 ret = dev->dev_ops->pcs_create(dev);
2870 if (ret)
2871 return ret;
2872 }
2873
2874 /* set broadcast storm protection 10% rate */
2875 regmap_update_bits(map: ksz_regmap_16(dev), reg: regs[S_BROADCAST_CTRL],
2876 BROADCAST_STORM_RATE,
2877 val: (BROADCAST_STORM_VALUE *
2878 BROADCAST_STORM_PROT_RATE) / 100);
2879
2880 dev->dev_ops->config_cpu_port(ds);
2881
2882 dev->dev_ops->enable_stp_addr(dev);
2883
2884 ds->num_tx_queues = dev->info->num_tx_queues;
2885
2886 regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_MULTICAST_CTRL],
2887 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2888
2889 ksz_init_mib_timer(dev);
2890
2891 ds->configure_vlan_while_not_filtering = false;
2892 ds->dscp_prio_mapping_is_global = true;
2893
2894 if (dev->dev_ops->setup) {
2895 ret = dev->dev_ops->setup(ds);
2896 if (ret)
2897 return ret;
2898 }
2899
2900 /* Start with learning disabled on standalone user ports, and enabled
2901 * on the CPU port. In lack of other finer mechanisms, learning on the
2902 * CPU port will avoid flooding bridge local addresses on the network
2903 * in some cases.
2904 */
2905 p = &dev->ports[dev->cpu_port];
2906 p->learning = true;
2907
2908 if (dev->irq > 0) {
2909 ret = ksz_girq_setup(dev);
2910 if (ret)
2911 return ret;
2912
2913 dsa_switch_for_each_user_port(dp, dev->ds) {
2914 ret = ksz_pirq_setup(dev, p: dp->index);
2915 if (ret)
2916 goto out_girq;
2917
2918 if (dev->info->ptp_capable) {
2919 ret = ksz_ptp_irq_setup(ds, p: dp->index);
2920 if (ret)
2921 goto out_pirq;
2922 }
2923 }
2924 }
2925
2926 if (dev->info->ptp_capable) {
2927 ret = ksz_ptp_clock_register(ds);
2928 if (ret) {
2929 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
2930 ret);
2931 goto out_ptpirq;
2932 }
2933 }
2934
2935 ret = ksz_mdio_register(dev);
2936 if (ret < 0) {
2937 dev_err(dev->dev, "failed to register the mdio");
2938 goto out_ptp_clock_unregister;
2939 }
2940
2941 ret = ksz_dcb_init(dev);
2942 if (ret)
2943 goto out_ptp_clock_unregister;
2944
2945 /* start switch */
2946 regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_START_CTRL],
2947 SW_START, SW_START);
2948
2949 return 0;
2950
2951out_ptp_clock_unregister:
2952 if (dev->info->ptp_capable)
2953 ksz_ptp_clock_unregister(ds);
2954out_ptpirq:
2955 if (dev->irq > 0 && dev->info->ptp_capable)
2956 dsa_switch_for_each_user_port(dp, dev->ds)
2957 ksz_ptp_irq_free(ds, p: dp->index);
2958out_pirq:
2959 if (dev->irq > 0)
2960 dsa_switch_for_each_user_port(dp, dev->ds)
2961 ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
2962out_girq:
2963 if (dev->irq > 0)
2964 ksz_irq_free(kirq: &dev->girq);
2965
2966 return ret;
2967}
2968
2969static void ksz_teardown(struct dsa_switch *ds)
2970{
2971 struct ksz_device *dev = ds->priv;
2972 struct dsa_port *dp;
2973
2974 if (dev->info->ptp_capable)
2975 ksz_ptp_clock_unregister(ds);
2976
2977 if (dev->irq > 0) {
2978 dsa_switch_for_each_user_port(dp, dev->ds) {
2979 if (dev->info->ptp_capable)
2980 ksz_ptp_irq_free(ds, p: dp->index);
2981
2982 ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
2983 }
2984
2985 ksz_irq_free(kirq: &dev->girq);
2986 }
2987
2988 if (dev->dev_ops->teardown)
2989 dev->dev_ops->teardown(ds);
2990}
2991
2992static void port_r_cnt(struct ksz_device *dev, int port)
2993{
2994 struct ksz_port_mib *mib = &dev->ports[port].mib;
2995 u64 *dropped;
2996
2997 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2998 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2999 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
3000 &mib->counters[mib->cnt_ptr]);
3001 ++mib->cnt_ptr;
3002 }
3003
3004 /* last one in storage */
3005 dropped = &mib->counters[dev->info->mib_cnt];
3006
3007 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
3008 while (mib->cnt_ptr < dev->info->mib_cnt) {
3009 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
3010 dropped, &mib->counters[mib->cnt_ptr]);
3011 ++mib->cnt_ptr;
3012 }
3013 mib->cnt_ptr = 0;
3014}
3015
3016static void ksz_mib_read_work(struct work_struct *work)
3017{
3018 struct ksz_device *dev = container_of(work, struct ksz_device,
3019 mib_read.work);
3020 struct ksz_port_mib *mib;
3021 struct ksz_port *p;
3022 int i;
3023
3024 for (i = 0; i < dev->info->port_cnt; i++) {
3025 if (dsa_is_unused_port(ds: dev->ds, p: i))
3026 continue;
3027
3028 p = &dev->ports[i];
3029 mib = &p->mib;
3030 mutex_lock(&mib->cnt_mutex);
3031
3032 /* Only read MIB counters when the port is told to do.
3033 * If not, read only dropped counters when link is not up.
3034 */
3035 if (!p->read) {
3036 const struct dsa_port *dp = dsa_to_port(ds: dev->ds, p: i);
3037
3038 if (!netif_carrier_ok(dev: dp->user))
3039 mib->cnt_ptr = dev->info->reg_mib_cnt;
3040 }
3041 port_r_cnt(dev, port: i);
3042 p->read = false;
3043
3044 if (dev->dev_ops->r_mib_stat64)
3045 dev->dev_ops->r_mib_stat64(dev, i);
3046
3047 mutex_unlock(lock: &mib->cnt_mutex);
3048 }
3049
3050 schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval);
3051}
3052
3053void ksz_init_mib_timer(struct ksz_device *dev)
3054{
3055 int i;
3056
3057 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
3058
3059 for (i = 0; i < dev->info->port_cnt; i++) {
3060 struct ksz_port_mib *mib = &dev->ports[i].mib;
3061
3062 dev->dev_ops->port_init_cnt(dev, i);
3063
3064 mib->cnt_ptr = 0;
3065 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
3066 }
3067}
3068
3069static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
3070{
3071 struct ksz_device *dev = ds->priv;
3072 u16 val = 0xffff;
3073 int ret;
3074
3075 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
3076 if (ret)
3077 return ret;
3078
3079 return val;
3080}
3081
3082static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
3083{
3084 struct ksz_device *dev = ds->priv;
3085 int ret;
3086
3087 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
3088 if (ret)
3089 return ret;
3090
3091 return 0;
3092}
3093
3094static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
3095{
3096 struct ksz_device *dev = ds->priv;
3097
3098 switch (dev->chip_id) {
3099 case KSZ88X3_CHIP_ID:
3100 /* Silicon Errata Sheet (DS80000830A):
3101 * Port 1 does not work with LinkMD Cable-Testing.
3102 * Port 1 does not respond to received PAUSE control frames.
3103 */
3104 if (!port)
3105 return MICREL_KSZ8_P1_ERRATA;
3106 break;
3107 }
3108
3109 return 0;
3110}
3111
3112static void ksz_phylink_mac_link_down(struct phylink_config *config,
3113 unsigned int mode,
3114 phy_interface_t interface)
3115{
3116 struct dsa_port *dp = dsa_phylink_to_port(config);
3117 struct ksz_device *dev = dp->ds->priv;
3118
3119 /* Read all MIB counters when the link is going down. */
3120 dev->ports[dp->index].read = true;
3121 /* timer started */
3122 if (dev->mib_read_interval)
3123 schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
3124}
3125
3126static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3127{
3128 struct ksz_device *dev = ds->priv;
3129
3130 if (sset != ETH_SS_STATS)
3131 return 0;
3132
3133 return dev->info->mib_cnt;
3134}
3135
3136static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3137 uint64_t *buf)
3138{
3139 const struct dsa_port *dp = dsa_to_port(ds, p: port);
3140 struct ksz_device *dev = ds->priv;
3141 struct ksz_port_mib *mib;
3142
3143 mib = &dev->ports[port].mib;
3144 mutex_lock(&mib->cnt_mutex);
3145
3146 /* Only read dropped counters if no link. */
3147 if (!netif_carrier_ok(dev: dp->user))
3148 mib->cnt_ptr = dev->info->reg_mib_cnt;
3149 port_r_cnt(dev, port);
3150 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3151 mutex_unlock(lock: &mib->cnt_mutex);
3152}
3153
3154static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3155 struct dsa_bridge bridge,
3156 bool *tx_fwd_offload,
3157 struct netlink_ext_ack *extack)
3158{
3159 /* port_stp_state_set() will be called after to put the port in
3160 * appropriate state so there is no need to do anything.
3161 */
3162
3163 return 0;
3164}
3165
3166static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3167 struct dsa_bridge bridge)
3168{
3169 /* port_stp_state_set() will be called after to put the port in
3170 * forwarding state so there is no need to do anything.
3171 */
3172}
3173
3174static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3175{
3176 struct ksz_device *dev = ds->priv;
3177
3178 dev->dev_ops->flush_dyn_mac_table(dev, port);
3179}
3180
3181static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3182{
3183 struct ksz_device *dev = ds->priv;
3184
3185 if (!dev->dev_ops->set_ageing_time)
3186 return -EOPNOTSUPP;
3187
3188 return dev->dev_ops->set_ageing_time(dev, msecs);
3189}
3190
3191static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3192 const unsigned char *addr, u16 vid,
3193 struct dsa_db db)
3194{
3195 struct ksz_device *dev = ds->priv;
3196
3197 if (!dev->dev_ops->fdb_add)
3198 return -EOPNOTSUPP;
3199
3200 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3201}
3202
3203static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3204 const unsigned char *addr,
3205 u16 vid, struct dsa_db db)
3206{
3207 struct ksz_device *dev = ds->priv;
3208
3209 if (!dev->dev_ops->fdb_del)
3210 return -EOPNOTSUPP;
3211
3212 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3213}
3214
3215static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3216 dsa_fdb_dump_cb_t *cb, void *data)
3217{
3218 struct ksz_device *dev = ds->priv;
3219
3220 if (!dev->dev_ops->fdb_dump)
3221 return -EOPNOTSUPP;
3222
3223 return dev->dev_ops->fdb_dump(dev, port, cb, data);
3224}
3225
3226static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3227 const struct switchdev_obj_port_mdb *mdb,
3228 struct dsa_db db)
3229{
3230 struct ksz_device *dev = ds->priv;
3231
3232 if (!dev->dev_ops->mdb_add)
3233 return -EOPNOTSUPP;
3234
3235 return dev->dev_ops->mdb_add(dev, port, mdb, db);
3236}
3237
3238static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3239 const struct switchdev_obj_port_mdb *mdb,
3240 struct dsa_db db)
3241{
3242 struct ksz_device *dev = ds->priv;
3243
3244 if (!dev->dev_ops->mdb_del)
3245 return -EOPNOTSUPP;
3246
3247 return dev->dev_ops->mdb_del(dev, port, mdb, db);
3248}
3249
3250static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3251 int port)
3252{
3253 u32 queue_map = 0;
3254 int ipm;
3255
3256 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3257 int queue;
3258
3259 /* Traffic Type (TT) is corresponding to the Internal Priority
3260 * Map (IPM) in the switch. Traffic Class (TC) is
3261 * corresponding to the queue in the switch.
3262 */
3263 queue = ieee8021q_tt_to_tc(tt: ipm, num_queues: dev->info->num_tx_queues);
3264 if (queue < 0)
3265 return queue;
3266
3267 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3268 }
3269
3270 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
3271}
3272
3273static int ksz_port_setup(struct dsa_switch *ds, int port)
3274{
3275 struct ksz_device *dev = ds->priv;
3276 int ret;
3277
3278 if (!dsa_is_user_port(ds, p: port))
3279 return 0;
3280
3281 /* setup user port */
3282 dev->dev_ops->port_setup(dev, port, false);
3283
3284 if (!is_ksz8(dev)) {
3285 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3286 if (ret)
3287 return ret;
3288 }
3289
3290 /* port_stp_state_set() will be called after to enable the port so
3291 * there is no need to do anything.
3292 */
3293
3294 return ksz_dcb_init_port(dev, port);
3295}
3296
3297void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3298{
3299 struct ksz_device *dev = ds->priv;
3300 struct ksz_port *p;
3301 const u16 *regs;
3302 u8 data;
3303
3304 regs = dev->info->regs;
3305
3306 ksz_pread8(dev, port, offset: regs[P_STP_CTRL], data: &data);
3307 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3308
3309 p = &dev->ports[port];
3310
3311 switch (state) {
3312 case BR_STATE_DISABLED:
3313 data |= PORT_LEARN_DISABLE;
3314 break;
3315 case BR_STATE_LISTENING:
3316 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3317 break;
3318 case BR_STATE_LEARNING:
3319 data |= PORT_RX_ENABLE;
3320 if (!p->learning)
3321 data |= PORT_LEARN_DISABLE;
3322 break;
3323 case BR_STATE_FORWARDING:
3324 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3325 if (!p->learning)
3326 data |= PORT_LEARN_DISABLE;
3327 break;
3328 case BR_STATE_BLOCKING:
3329 data |= PORT_LEARN_DISABLE;
3330 break;
3331 default:
3332 dev_err(ds->dev, "invalid STP state: %d\n", state);
3333 return;
3334 }
3335
3336 ksz_pwrite8(dev, port, offset: regs[P_STP_CTRL], data);
3337
3338 p->stp_state = state;
3339
3340 ksz_update_port_member(dev, port);
3341}
3342
3343static void ksz_port_teardown(struct dsa_switch *ds, int port)
3344{
3345 struct ksz_device *dev = ds->priv;
3346
3347 switch (dev->chip_id) {
3348 case KSZ8563_CHIP_ID:
3349 case KSZ8567_CHIP_ID:
3350 case KSZ9477_CHIP_ID:
3351 case KSZ9563_CHIP_ID:
3352 case KSZ9567_CHIP_ID:
3353 case KSZ9893_CHIP_ID:
3354 case KSZ9896_CHIP_ID:
3355 case KSZ9897_CHIP_ID:
3356 case LAN9646_CHIP_ID:
3357 if (dsa_is_user_port(ds, p: port))
3358 ksz9477_port_acl_free(dev, port);
3359 }
3360}
3361
3362static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3363 struct switchdev_brport_flags flags,
3364 struct netlink_ext_ack *extack)
3365{
3366 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3367 return -EINVAL;
3368
3369 return 0;
3370}
3371
3372static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3373 struct switchdev_brport_flags flags,
3374 struct netlink_ext_ack *extack)
3375{
3376 struct ksz_device *dev = ds->priv;
3377 struct ksz_port *p = &dev->ports[port];
3378
3379 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3380 if (flags.mask & BR_LEARNING)
3381 p->learning = !!(flags.val & BR_LEARNING);
3382
3383 if (flags.mask & BR_ISOLATED)
3384 p->isolated = !!(flags.val & BR_ISOLATED);
3385
3386 /* Make the change take effect immediately */
3387 ksz_port_stp_state_set(ds, port, state: p->stp_state);
3388 }
3389
3390 return 0;
3391}
3392
3393static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3394 int port,
3395 enum dsa_tag_protocol mp)
3396{
3397 struct ksz_device *dev = ds->priv;
3398 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3399
3400 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3401 proto = DSA_TAG_PROTO_KSZ8795;
3402
3403 if (dev->chip_id == KSZ88X3_CHIP_ID ||
3404 dev->chip_id == KSZ8563_CHIP_ID ||
3405 dev->chip_id == KSZ9893_CHIP_ID ||
3406 dev->chip_id == KSZ9563_CHIP_ID)
3407 proto = DSA_TAG_PROTO_KSZ9893;
3408
3409 if (dev->chip_id == KSZ8567_CHIP_ID ||
3410 dev->chip_id == KSZ9477_CHIP_ID ||
3411 dev->chip_id == KSZ9896_CHIP_ID ||
3412 dev->chip_id == KSZ9897_CHIP_ID ||
3413 dev->chip_id == KSZ9567_CHIP_ID ||
3414 dev->chip_id == LAN9646_CHIP_ID)
3415 proto = DSA_TAG_PROTO_KSZ9477;
3416
3417 if (is_lan937x(dev))
3418 proto = DSA_TAG_PROTO_LAN937X;
3419
3420 return proto;
3421}
3422
3423static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3424 enum dsa_tag_protocol proto)
3425{
3426 struct ksz_tagger_data *tagger_data;
3427
3428 switch (proto) {
3429 case DSA_TAG_PROTO_KSZ8795:
3430 return 0;
3431 case DSA_TAG_PROTO_KSZ9893:
3432 case DSA_TAG_PROTO_KSZ9477:
3433 case DSA_TAG_PROTO_LAN937X:
3434 tagger_data = ksz_tagger_data(ds);
3435 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3436 return 0;
3437 default:
3438 return -EPROTONOSUPPORT;
3439 }
3440}
3441
3442static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3443 bool flag, struct netlink_ext_ack *extack)
3444{
3445 struct ksz_device *dev = ds->priv;
3446
3447 if (!dev->dev_ops->vlan_filtering)
3448 return -EOPNOTSUPP;
3449
3450 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3451}
3452
3453static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3454 const struct switchdev_obj_port_vlan *vlan,
3455 struct netlink_ext_ack *extack)
3456{
3457 struct ksz_device *dev = ds->priv;
3458
3459 if (!dev->dev_ops->vlan_add)
3460 return -EOPNOTSUPP;
3461
3462 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3463}
3464
3465static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3466 const struct switchdev_obj_port_vlan *vlan)
3467{
3468 struct ksz_device *dev = ds->priv;
3469
3470 if (!dev->dev_ops->vlan_del)
3471 return -EOPNOTSUPP;
3472
3473 return dev->dev_ops->vlan_del(dev, port, vlan);
3474}
3475
3476static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3477 struct dsa_mall_mirror_tc_entry *mirror,
3478 bool ingress, struct netlink_ext_ack *extack)
3479{
3480 struct ksz_device *dev = ds->priv;
3481
3482 if (!dev->dev_ops->mirror_add)
3483 return -EOPNOTSUPP;
3484
3485 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3486}
3487
3488static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3489 struct dsa_mall_mirror_tc_entry *mirror)
3490{
3491 struct ksz_device *dev = ds->priv;
3492
3493 if (dev->dev_ops->mirror_del)
3494 dev->dev_ops->mirror_del(dev, port, mirror);
3495}
3496
3497static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3498{
3499 struct ksz_device *dev = ds->priv;
3500
3501 if (!dev->dev_ops->change_mtu)
3502 return -EOPNOTSUPP;
3503
3504 return dev->dev_ops->change_mtu(dev, port, mtu);
3505}
3506
3507static int ksz_max_mtu(struct dsa_switch *ds, int port)
3508{
3509 struct ksz_device *dev = ds->priv;
3510
3511 switch (dev->chip_id) {
3512 case KSZ8795_CHIP_ID:
3513 case KSZ8794_CHIP_ID:
3514 case KSZ8765_CHIP_ID:
3515 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3516 case KSZ88X3_CHIP_ID:
3517 case KSZ8864_CHIP_ID:
3518 case KSZ8895_CHIP_ID:
3519 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3520 case KSZ8563_CHIP_ID:
3521 case KSZ8567_CHIP_ID:
3522 case KSZ9477_CHIP_ID:
3523 case KSZ9563_CHIP_ID:
3524 case KSZ9567_CHIP_ID:
3525 case KSZ9893_CHIP_ID:
3526 case KSZ9896_CHIP_ID:
3527 case KSZ9897_CHIP_ID:
3528 case LAN9370_CHIP_ID:
3529 case LAN9371_CHIP_ID:
3530 case LAN9372_CHIP_ID:
3531 case LAN9373_CHIP_ID:
3532 case LAN9374_CHIP_ID:
3533 case LAN9646_CHIP_ID:
3534 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3535 }
3536
3537 return -EOPNOTSUPP;
3538}
3539
3540/**
3541 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a
3542 * port
3543 * @ds: Pointer to the DSA switch structure
3544 * @port: Port number to check
3545 *
3546 * This function also documents devices where EEE was initially advertised but
3547 * later withdrawn due to reliability issues, as described in official errata
3548 * documents. These devices are explicitly listed to record known limitations,
3549 * even if there is no technical necessity for runtime checks.
3550 *
3551 * Returns: true if the internal PHY on the given port supports fully
3552 * operational EEE, false otherwise.
3553 */
3554static bool ksz_support_eee(struct dsa_switch *ds, int port)
3555{
3556 struct ksz_device *dev = ds->priv;
3557
3558 if (!dev->info->internal_phy[port])
3559 return false;
3560
3561 switch (dev->chip_id) {
3562 case KSZ8563_CHIP_ID:
3563 case KSZ9563_CHIP_ID:
3564 case KSZ9893_CHIP_ID:
3565 return true;
3566 case KSZ8567_CHIP_ID:
3567 /* KSZ8567R Errata DS80000752C Module 4 */
3568 case KSZ8765_CHIP_ID:
3569 case KSZ8794_CHIP_ID:
3570 case KSZ8795_CHIP_ID:
3571 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
3572 case KSZ9477_CHIP_ID:
3573 /* KSZ9477S Errata DS80000754A Module 4 */
3574 case KSZ9567_CHIP_ID:
3575 /* KSZ9567S Errata DS80000756A Module 4 */
3576 case KSZ9896_CHIP_ID:
3577 /* KSZ9896C Errata DS80000757A Module 3 */
3578 case KSZ9897_CHIP_ID:
3579 case LAN9646_CHIP_ID:
3580 /* KSZ9897R Errata DS80000758C Module 4 */
3581 /* Energy Efficient Ethernet (EEE) feature select must be
3582 * manually disabled
3583 * The EEE feature is enabled by default, but it is not fully
3584 * operational. It must be manually disabled through register
3585 * controls. If not disabled, the PHY ports can auto-negotiate
3586 * to enable EEE, and this feature can cause link drops when
3587 * linked to another device supporting EEE.
3588 *
3589 * The same item appears in the errata for all switches above.
3590 */
3591 break;
3592 }
3593
3594 return false;
3595}
3596
3597static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3598 struct ethtool_keee *e)
3599{
3600 struct ksz_device *dev = ds->priv;
3601
3602 if (!e->tx_lpi_enabled) {
3603 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3604 return -EINVAL;
3605 }
3606
3607 if (e->tx_lpi_timer) {
3608 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3609 return -EINVAL;
3610 }
3611
3612 return 0;
3613}
3614
3615static void ksz_set_xmii(struct ksz_device *dev, int port,
3616 phy_interface_t interface)
3617{
3618 const u8 *bitval = dev->info->xmii_ctrl1;
3619 struct ksz_port *p = &dev->ports[port];
3620 const u16 *regs = dev->info->regs;
3621 u8 data8;
3622
3623 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3624
3625 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3626 P_RGMII_ID_EG_ENABLE);
3627
3628 switch (interface) {
3629 case PHY_INTERFACE_MODE_MII:
3630 data8 |= bitval[P_MII_SEL];
3631 break;
3632 case PHY_INTERFACE_MODE_RMII:
3633 data8 |= bitval[P_RMII_SEL];
3634 break;
3635 case PHY_INTERFACE_MODE_GMII:
3636 data8 |= bitval[P_GMII_SEL];
3637 break;
3638 case PHY_INTERFACE_MODE_RGMII:
3639 case PHY_INTERFACE_MODE_RGMII_ID:
3640 case PHY_INTERFACE_MODE_RGMII_TXID:
3641 case PHY_INTERFACE_MODE_RGMII_RXID:
3642 data8 |= bitval[P_RGMII_SEL];
3643 /* On KSZ9893, disable RGMII in-band status support */
3644 if (dev->chip_id == KSZ9893_CHIP_ID ||
3645 dev->chip_id == KSZ8563_CHIP_ID ||
3646 dev->chip_id == KSZ9563_CHIP_ID ||
3647 is_lan937x(dev))
3648 data8 &= ~P_MII_MAC_MODE;
3649 break;
3650 default:
3651 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3652 phy_modes(interface), port);
3653 return;
3654 }
3655
3656 if (p->rgmii_tx_val)
3657 data8 |= P_RGMII_ID_EG_ENABLE;
3658
3659 if (p->rgmii_rx_val)
3660 data8 |= P_RGMII_ID_IG_ENABLE;
3661
3662 /* Write the updated value */
3663 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
3664}
3665
3666phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3667{
3668 const u8 *bitval = dev->info->xmii_ctrl1;
3669 const u16 *regs = dev->info->regs;
3670 phy_interface_t interface;
3671 u8 data8;
3672 u8 val;
3673
3674 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3675
3676 val = FIELD_GET(P_MII_SEL_M, data8);
3677
3678 if (val == bitval[P_MII_SEL]) {
3679 if (gbit)
3680 interface = PHY_INTERFACE_MODE_GMII;
3681 else
3682 interface = PHY_INTERFACE_MODE_MII;
3683 } else if (val == bitval[P_RMII_SEL]) {
3684 interface = PHY_INTERFACE_MODE_RMII;
3685 } else {
3686 interface = PHY_INTERFACE_MODE_RGMII;
3687 if (data8 & P_RGMII_ID_EG_ENABLE)
3688 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3689 if (data8 & P_RGMII_ID_IG_ENABLE) {
3690 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3691 if (data8 & P_RGMII_ID_EG_ENABLE)
3692 interface = PHY_INTERFACE_MODE_RGMII_ID;
3693 }
3694 }
3695
3696 return interface;
3697}
3698
3699static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3700 unsigned int mode,
3701 const struct phylink_link_state *state)
3702{
3703 struct dsa_port *dp = dsa_phylink_to_port(config);
3704 struct ksz_device *dev = dp->ds->priv;
3705
3706 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3707}
3708
3709static void ksz_phylink_mac_config(struct phylink_config *config,
3710 unsigned int mode,
3711 const struct phylink_link_state *state)
3712{
3713 struct dsa_port *dp = dsa_phylink_to_port(config);
3714 struct ksz_device *dev = dp->ds->priv;
3715 int port = dp->index;
3716
3717 /* Internal PHYs */
3718 if (dev->info->internal_phy[port])
3719 return;
3720
3721 /* No need to configure XMII control register when using SGMII. */
3722 if (ksz_is_sgmii_port(dev, port))
3723 return;
3724
3725 if (phylink_autoneg_inband(mode)) {
3726 dev_err(dev->dev, "In-band AN not supported!\n");
3727 return;
3728 }
3729
3730 ksz_set_xmii(dev, port, interface: state->interface);
3731
3732 if (dev->dev_ops->setup_rgmii_delay)
3733 dev->dev_ops->setup_rgmii_delay(dev, port);
3734}
3735
3736bool ksz_get_gbit(struct ksz_device *dev, int port)
3737{
3738 const u8 *bitval = dev->info->xmii_ctrl1;
3739 const u16 *regs = dev->info->regs;
3740 bool gbit = false;
3741 u8 data8;
3742 bool val;
3743
3744 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3745
3746 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3747
3748 if (val == bitval[P_GMII_1GBIT])
3749 gbit = true;
3750
3751 return gbit;
3752}
3753
3754static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3755{
3756 const u8 *bitval = dev->info->xmii_ctrl1;
3757 const u16 *regs = dev->info->regs;
3758 u8 data8;
3759
3760 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3761
3762 data8 &= ~P_GMII_1GBIT_M;
3763
3764 if (gbit)
3765 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3766 else
3767 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3768
3769 /* Write the updated value */
3770 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
3771}
3772
3773static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3774{
3775 const u8 *bitval = dev->info->xmii_ctrl0;
3776 const u16 *regs = dev->info->regs;
3777 u8 data8;
3778
3779 ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_0], data: &data8);
3780
3781 data8 &= ~P_MII_100MBIT_M;
3782
3783 if (speed == SPEED_100)
3784 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3785 else
3786 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3787
3788 /* Write the updated value */
3789 ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_0], data: data8);
3790}
3791
3792static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3793{
3794 if (speed == SPEED_1000)
3795 ksz_set_gbit(dev, port, gbit: true);
3796 else
3797 ksz_set_gbit(dev, port, gbit: false);
3798
3799 if (speed == SPEED_100 || speed == SPEED_10)
3800 ksz_set_100_10mbit(dev, port, speed);
3801}
3802
3803static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3804 bool tx_pause, bool rx_pause)
3805{
3806 const u8 *bitval = dev->info->xmii_ctrl0;
3807 const u32 *masks = dev->info->masks;
3808 const u16 *regs = dev->info->regs;
3809 u8 mask;
3810 u8 val;
3811
3812 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3813 masks[P_MII_RX_FLOW_CTRL];
3814
3815 if (duplex == DUPLEX_FULL)
3816 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3817 else
3818 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3819
3820 if (tx_pause)
3821 val |= masks[P_MII_TX_FLOW_CTRL];
3822
3823 if (rx_pause)
3824 val |= masks[P_MII_RX_FLOW_CTRL];
3825
3826 ksz_prmw8(dev, port, offset: regs[P_XMII_CTRL_0], mask, val);
3827}
3828
3829static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3830 struct phy_device *phydev,
3831 unsigned int mode,
3832 phy_interface_t interface,
3833 int speed, int duplex, bool tx_pause,
3834 bool rx_pause)
3835{
3836 struct dsa_port *dp = dsa_phylink_to_port(config);
3837 struct ksz_device *dev = dp->ds->priv;
3838 int port = dp->index;
3839 struct ksz_port *p;
3840
3841 p = &dev->ports[port];
3842
3843 /* Internal PHYs */
3844 if (dev->info->internal_phy[port])
3845 return;
3846
3847 p->phydev.speed = speed;
3848
3849 ksz_port_set_xmii_speed(dev, port, speed);
3850
3851 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3852}
3853
3854static int ksz_switch_detect(struct ksz_device *dev)
3855{
3856 u8 id1, id2, id4;
3857 u16 id16;
3858 u32 id32;
3859 int ret;
3860
3861 /* read chip id */
3862 ret = ksz_read16(dev, REG_CHIP_ID0, val: &id16);
3863 if (ret)
3864 return ret;
3865
3866 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3867 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3868
3869 switch (id1) {
3870 case KSZ87_FAMILY_ID:
3871 if (id2 == KSZ87_CHIP_ID_95) {
3872 u8 val;
3873
3874 dev->chip_id = KSZ8795_CHIP_ID;
3875
3876 ksz_read8(dev, KSZ8_PORT_STATUS_0, val: &val);
3877 if (val & KSZ8_PORT_FIBER_MODE)
3878 dev->chip_id = KSZ8765_CHIP_ID;
3879 } else if (id2 == KSZ87_CHIP_ID_94) {
3880 dev->chip_id = KSZ8794_CHIP_ID;
3881 } else {
3882 return -ENODEV;
3883 }
3884 break;
3885 case KSZ88_FAMILY_ID:
3886 if (id2 == KSZ88_CHIP_ID_63)
3887 dev->chip_id = KSZ88X3_CHIP_ID;
3888 else
3889 return -ENODEV;
3890 break;
3891 case KSZ8895_FAMILY_ID:
3892 if (id2 == KSZ8895_CHIP_ID_95 ||
3893 id2 == KSZ8895_CHIP_ID_95R)
3894 dev->chip_id = KSZ8895_CHIP_ID;
3895 else
3896 return -ENODEV;
3897 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, val: &id4);
3898 if (ret)
3899 return ret;
3900 if (id4 & SW_KSZ8864)
3901 dev->chip_id = KSZ8864_CHIP_ID;
3902 break;
3903 default:
3904 ret = ksz_read32(dev, REG_CHIP_ID0, val: &id32);
3905 if (ret)
3906 return ret;
3907
3908 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3909 id32 &= ~0xFF;
3910
3911 switch (id32) {
3912 case KSZ9477_CHIP_ID:
3913 case KSZ9896_CHIP_ID:
3914 case KSZ9897_CHIP_ID:
3915 case KSZ9567_CHIP_ID:
3916 case KSZ8567_CHIP_ID:
3917 case LAN9370_CHIP_ID:
3918 case LAN9371_CHIP_ID:
3919 case LAN9372_CHIP_ID:
3920 case LAN9373_CHIP_ID:
3921 case LAN9374_CHIP_ID:
3922
3923 /* LAN9646 does not have its own chip id. */
3924 if (dev->chip_id != LAN9646_CHIP_ID)
3925 dev->chip_id = id32;
3926 break;
3927 case KSZ9893_CHIP_ID:
3928 ret = ksz_read8(dev, REG_CHIP_ID4,
3929 val: &id4);
3930 if (ret)
3931 return ret;
3932
3933 if (id4 == SKU_ID_KSZ8563)
3934 dev->chip_id = KSZ8563_CHIP_ID;
3935 else if (id4 == SKU_ID_KSZ9563)
3936 dev->chip_id = KSZ9563_CHIP_ID;
3937 else
3938 dev->chip_id = KSZ9893_CHIP_ID;
3939
3940 break;
3941 default:
3942 dev_err(dev->dev,
3943 "unsupported switch detected %x)\n", id32);
3944 return -ENODEV;
3945 }
3946 }
3947 return 0;
3948}
3949
3950static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3951 struct flow_cls_offload *cls, bool ingress)
3952{
3953 struct ksz_device *dev = ds->priv;
3954
3955 switch (dev->chip_id) {
3956 case KSZ8563_CHIP_ID:
3957 case KSZ8567_CHIP_ID:
3958 case KSZ9477_CHIP_ID:
3959 case KSZ9563_CHIP_ID:
3960 case KSZ9567_CHIP_ID:
3961 case KSZ9893_CHIP_ID:
3962 case KSZ9896_CHIP_ID:
3963 case KSZ9897_CHIP_ID:
3964 case LAN9646_CHIP_ID:
3965 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3966 }
3967
3968 return -EOPNOTSUPP;
3969}
3970
3971static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3972 struct flow_cls_offload *cls, bool ingress)
3973{
3974 struct ksz_device *dev = ds->priv;
3975
3976 switch (dev->chip_id) {
3977 case KSZ8563_CHIP_ID:
3978 case KSZ8567_CHIP_ID:
3979 case KSZ9477_CHIP_ID:
3980 case KSZ9563_CHIP_ID:
3981 case KSZ9567_CHIP_ID:
3982 case KSZ9893_CHIP_ID:
3983 case KSZ9896_CHIP_ID:
3984 case KSZ9897_CHIP_ID:
3985 case LAN9646_CHIP_ID:
3986 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3987 }
3988
3989 return -EOPNOTSUPP;
3990}
3991
3992/* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3993 * is converted to Hex-decimal using the successive multiplication method. On
3994 * every step, integer part is taken and decimal part is carry forwarded.
3995 */
3996static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3997{
3998 u32 cinc = 0;
3999 u32 txrate;
4000 u32 rate;
4001 u8 temp;
4002 u8 i;
4003
4004 txrate = idle_slope - send_slope;
4005
4006 if (!txrate)
4007 return -EINVAL;
4008
4009 rate = idle_slope;
4010
4011 /* 24 bit register */
4012 for (i = 0; i < 6; i++) {
4013 rate = rate * 16;
4014
4015 temp = rate / txrate;
4016
4017 rate %= txrate;
4018
4019 cinc = ((cinc << 4) | temp);
4020 }
4021
4022 *bw = cinc;
4023
4024 return 0;
4025}
4026
4027static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
4028 u8 shaper)
4029{
4030 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
4031 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
4032 FIELD_PREP(MTI_SHAPING_M, shaper));
4033}
4034
4035static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
4036 struct tc_cbs_qopt_offload *qopt)
4037{
4038 struct ksz_device *dev = ds->priv;
4039 int ret;
4040 u32 bw;
4041
4042 if (!dev->info->tc_cbs_supported)
4043 return -EOPNOTSUPP;
4044
4045 if (qopt->queue > dev->info->num_tx_queues)
4046 return -EINVAL;
4047
4048 /* Queue Selection */
4049 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: qopt->queue);
4050 if (ret)
4051 return ret;
4052
4053 if (!qopt->enable)
4054 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4055 MTI_SHAPING_OFF);
4056
4057 /* High Credit */
4058 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
4059 data: qopt->hicredit);
4060 if (ret)
4061 return ret;
4062
4063 /* Low Credit */
4064 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
4065 data: qopt->locredit);
4066 if (ret)
4067 return ret;
4068
4069 /* Credit Increment Register */
4070 ret = cinc_cal(idle_slope: qopt->idleslope, send_slope: qopt->sendslope, bw: &bw);
4071 if (ret)
4072 return ret;
4073
4074 if (dev->dev_ops->tc_cbs_set_cinc) {
4075 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
4076 if (ret)
4077 return ret;
4078 }
4079
4080 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4081 MTI_SHAPING_SRP);
4082}
4083
4084static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
4085{
4086 int queue, ret;
4087
4088 /* Configuration will not take effect until the last Port Queue X
4089 * Egress Limit Control Register is written.
4090 */
4091 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4092 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
4093 KSZ9477_OUT_RATE_NO_LIMIT);
4094 if (ret)
4095 return ret;
4096 }
4097
4098 return 0;
4099}
4100
4101static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
4102 int band)
4103{
4104 /* Compared to queues, bands prioritize packets differently. In strict
4105 * priority mode, the lowest priority is assigned to Queue 0 while the
4106 * highest priority is given to Band 0.
4107 */
4108 return p->bands - 1 - band;
4109}
4110
4111/**
4112 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection)
4113 * for a port on KSZ88x3 switch
4114 * @dev: Pointer to the KSZ switch device structure
4115 * @port: Port number to configure
4116 * @p: Pointer to offload replace parameters describing ETS bands and mapping
4117 *
4118 * The KSZ88x3 supports two scheduling modes: Strict Priority and
4119 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior:
4120 * - No configurable queue-to-priority mapping
4121 * - No weight adjustment in WFQ mode
4122 *
4123 * This function configures the switch to use strict priority mode by
4124 * clearing the WFQ enable bit for all queues associated with ETS bands.
4125 * If strict priority is not explicitly requested, the switch will default
4126 * to WFQ mode.
4127 *
4128 * Return: 0 on success, or a negative error code on failure
4129 */
4130static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port,
4131 struct tc_ets_qopt_offload_replace_params *p)
4132{
4133 int ret, band;
4134
4135 /* Only strict priority mode is supported for now.
4136 * WFQ is implicitly enabled when strict mode is disabled.
4137 */
4138 for (band = 0; band < p->bands; band++) {
4139 int queue = ksz_ets_band_to_queue(p, band);
4140 u8 reg;
4141
4142 /* Calculate TXQ Split Control register address for this
4143 * port/queue
4144 */
4145 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4146
4147 /* Clear WFQ enable bit to select strict priority scheduling */
4148 ret = ksz_rmw8(dev, offset: reg, KSZ8873_TXQ_WFQ_ENABLE, val: 0);
4149 if (ret)
4150 return ret;
4151 }
4152
4153 return 0;
4154}
4155
4156/**
4157 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config
4158 * for a port on KSZ88x3 switch
4159 * @dev: Pointer to the KSZ switch device structure
4160 * @port: Port number to reset
4161 *
4162 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or
4163 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or
4164 * queue mapping. This function resets the port’s scheduling mode to
4165 * the default, which is WFQ, by enabling the WFQ bit for all queues.
4166 *
4167 * Return: 0 on success, or a negative error code on failure
4168 */
4169static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port)
4170{
4171 int ret, queue;
4172
4173 /* Iterate over all transmit queues for this port */
4174 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4175 u8 reg;
4176
4177 /* Calculate TXQ Split Control register address for this
4178 * port/queue
4179 */
4180 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4181
4182 /* Set WFQ enable bit to revert back to default scheduling
4183 * mode
4184 */
4185 ret = ksz_rmw8(dev, offset: reg, KSZ8873_TXQ_WFQ_ENABLE,
4186 KSZ8873_TXQ_WFQ_ENABLE);
4187 if (ret)
4188 return ret;
4189 }
4190
4191 return 0;
4192}
4193
4194static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4195{
4196 int ret;
4197
4198 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
4199 if (ret)
4200 return ret;
4201
4202 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4203 MTI_SHAPING_OFF);
4204}
4205
4206static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4207 int weight)
4208{
4209 int ret;
4210
4211 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
4212 if (ret)
4213 return ret;
4214
4215 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4216 MTI_SHAPING_OFF);
4217 if (ret)
4218 return ret;
4219
4220 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, data: weight);
4221}
4222
4223static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4224 struct tc_ets_qopt_offload_replace_params *p)
4225{
4226 int ret, band, tc_prio;
4227 u32 queue_map = 0;
4228
4229 /* In order to ensure proper prioritization, it is necessary to set the
4230 * rate limit for the related queue to zero. Otherwise strict priority
4231 * or WRR mode will not work. This is a hardware limitation.
4232 */
4233 ret = ksz_disable_egress_rate_limit(dev, port);
4234 if (ret)
4235 return ret;
4236
4237 /* Configure queue scheduling mode for all bands. Currently only strict
4238 * prio mode is supported.
4239 */
4240 for (band = 0; band < p->bands; band++) {
4241 int queue = ksz_ets_band_to_queue(p, band);
4242
4243 ret = ksz_queue_set_strict(dev, port, queue);
4244 if (ret)
4245 return ret;
4246 }
4247
4248 /* Configure the mapping between traffic classes and queues. Note:
4249 * priomap variable support 16 traffic classes, but the chip can handle
4250 * only 8 classes.
4251 */
4252 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4253 int queue;
4254
4255 if (tc_prio >= dev->info->num_ipms)
4256 break;
4257
4258 queue = ksz_ets_band_to_queue(p, band: p->priomap[tc_prio]);
4259 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4260 }
4261
4262 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
4263}
4264
4265static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4266{
4267 int ret, queue;
4268
4269 /* To restore the default chip configuration, set all queues to use the
4270 * WRR scheduler with a weight of 1.
4271 */
4272 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4273 ret = ksz_queue_set_wrr(dev, port, queue,
4274 KSZ9477_DEFAULT_WRR_WEIGHT);
4275
4276 if (ret)
4277 return ret;
4278 }
4279
4280 /* Revert the queue mapping for TC-priority to its default setting on
4281 * the chip.
4282 */
4283 return ksz9477_set_default_prio_queue_mapping(dev, port);
4284}
4285
4286static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4287 struct tc_ets_qopt_offload_replace_params *p)
4288{
4289 int band;
4290
4291 /* Since it is not feasible to share one port among multiple qdisc,
4292 * the user must configure all available queues appropriately.
4293 */
4294 if (p->bands != dev->info->num_tx_queues) {
4295 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4296 dev->info->num_tx_queues);
4297 return -EOPNOTSUPP;
4298 }
4299
4300 for (band = 0; band < p->bands; ++band) {
4301 /* The KSZ switches utilize a weighted round robin configuration
4302 * where a certain number of packets can be transmitted from a
4303 * queue before the next queue is serviced. For more information
4304 * on this, refer to section 5.2.8.4 of the KSZ8565R
4305 * documentation on the Port Transmit Queue Control 1 Register.
4306 * However, the current ETS Qdisc implementation (as of February
4307 * 2023) assigns a weight to each queue based on the number of
4308 * bytes or extrapolated bandwidth in percentages. Since this
4309 * differs from the KSZ switches' method and we don't want to
4310 * fake support by converting bytes to packets, it is better to
4311 * return an error instead.
4312 */
4313 if (p->quanta[band]) {
4314 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4315 return -EOPNOTSUPP;
4316 }
4317 }
4318
4319 return 0;
4320}
4321
4322static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4323 struct tc_ets_qopt_offload *qopt)
4324{
4325 struct ksz_device *dev = ds->priv;
4326 int ret;
4327
4328 if (is_ksz8(dev) && !ksz_is_ksz88x3(dev))
4329 return -EOPNOTSUPP;
4330
4331 if (qopt->parent != TC_H_ROOT) {
4332 dev_err(dev->dev, "Parent should be \"root\"\n");
4333 return -EOPNOTSUPP;
4334 }
4335
4336 switch (qopt->command) {
4337 case TC_ETS_REPLACE:
4338 ret = ksz_tc_ets_validate(dev, port, p: &qopt->replace_params);
4339 if (ret)
4340 return ret;
4341
4342 if (ksz_is_ksz88x3(dev))
4343 return ksz88x3_tc_ets_add(dev, port,
4344 p: &qopt->replace_params);
4345 else
4346 return ksz_tc_ets_add(dev, port, p: &qopt->replace_params);
4347 case TC_ETS_DESTROY:
4348 if (ksz_is_ksz88x3(dev))
4349 return ksz88x3_tc_ets_del(dev, port);
4350 else
4351 return ksz_tc_ets_del(dev, port);
4352 case TC_ETS_STATS:
4353 case TC_ETS_GRAFT:
4354 return -EOPNOTSUPP;
4355 }
4356
4357 return -EOPNOTSUPP;
4358}
4359
4360static int ksz_setup_tc(struct dsa_switch *ds, int port,
4361 enum tc_setup_type type, void *type_data)
4362{
4363 switch (type) {
4364 case TC_SETUP_QDISC_CBS:
4365 return ksz_setup_tc_cbs(ds, port, qopt: type_data);
4366 case TC_SETUP_QDISC_ETS:
4367 return ksz_tc_setup_qdisc_ets(ds, port, qopt: type_data);
4368 default:
4369 return -EOPNOTSUPP;
4370 }
4371}
4372
4373/**
4374 * ksz_handle_wake_reason - Handle wake reason on a specified port.
4375 * @dev: The device structure.
4376 * @port: The port number.
4377 *
4378 * This function reads the PME (Power Management Event) status register of a
4379 * specified port to determine the wake reason. If there is no wake event, it
4380 * returns early. Otherwise, it logs the wake reason which could be due to a
4381 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4382 * is then cleared to acknowledge the handling of the wake event.
4383 *
4384 * Return: 0 on success, or an error code on failure.
4385 */
4386int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4387{
4388 const struct ksz_dev_ops *ops = dev->dev_ops;
4389 const u16 *regs = dev->info->regs;
4390 u8 pme_status;
4391 int ret;
4392
4393 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4394 &pme_status);
4395 if (ret)
4396 return ret;
4397
4398 if (!pme_status)
4399 return 0;
4400
4401 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4402 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4403 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4404 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4405
4406 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4407 pme_status);
4408}
4409
4410/**
4411 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4412 * @ds: The dsa_switch structure.
4413 * @port: The port number.
4414 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4415 *
4416 * This function checks the device PME wakeup_source flag and chip_id.
4417 * If enabled and supported, it sets the supported and active WoL
4418 * flags.
4419 */
4420static void ksz_get_wol(struct dsa_switch *ds, int port,
4421 struct ethtool_wolinfo *wol)
4422{
4423 struct ksz_device *dev = ds->priv;
4424 const u16 *regs = dev->info->regs;
4425 u8 pme_ctrl;
4426 int ret;
4427
4428 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4429 return;
4430
4431 if (!dev->wakeup_source)
4432 return;
4433
4434 wol->supported = WAKE_PHY;
4435
4436 /* Check if the current MAC address on this port can be set
4437 * as global for WAKE_MAGIC support. The result may vary
4438 * dynamically based on other ports configurations.
4439 */
4440 if (ksz_is_port_mac_global_usable(ds: dev->ds, port))
4441 wol->supported |= WAKE_MAGIC;
4442
4443 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4444 &pme_ctrl);
4445 if (ret)
4446 return;
4447
4448 if (pme_ctrl & PME_WOL_MAGICPKT)
4449 wol->wolopts |= WAKE_MAGIC;
4450 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4451 wol->wolopts |= WAKE_PHY;
4452}
4453
4454/**
4455 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4456 * @ds: The dsa_switch structure.
4457 * @port: The port number.
4458 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4459 *
4460 * This function configures Wake-on-LAN (WoL) settings for a specified
4461 * port. It validates the provided WoL options, checks if PME is
4462 * enabled and supported, clears any previous wake reasons, and sets
4463 * the Magic Packet flag in the port's PME control register if
4464 * specified.
4465 *
4466 * Return: 0 on success, or other error codes on failure.
4467 */
4468static int ksz_set_wol(struct dsa_switch *ds, int port,
4469 struct ethtool_wolinfo *wol)
4470{
4471 u8 pme_ctrl = 0, pme_ctrl_old = 0;
4472 struct ksz_device *dev = ds->priv;
4473 const u16 *regs = dev->info->regs;
4474 bool magic_switched_off;
4475 bool magic_switched_on;
4476 int ret;
4477
4478 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4479 return -EINVAL;
4480
4481 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4482 return -EOPNOTSUPP;
4483
4484 if (!dev->wakeup_source)
4485 return -EOPNOTSUPP;
4486
4487 ret = ksz_handle_wake_reason(dev, port);
4488 if (ret)
4489 return ret;
4490
4491 if (wol->wolopts & WAKE_MAGIC)
4492 pme_ctrl |= PME_WOL_MAGICPKT;
4493 if (wol->wolopts & WAKE_PHY)
4494 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4495
4496 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4497 &pme_ctrl_old);
4498 if (ret)
4499 return ret;
4500
4501 if (pme_ctrl_old == pme_ctrl)
4502 return 0;
4503
4504 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4505 !(pme_ctrl & PME_WOL_MAGICPKT);
4506 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4507 (pme_ctrl & PME_WOL_MAGICPKT);
4508
4509 /* To keep reference count of MAC address, we should do this
4510 * operation only on change of WOL settings.
4511 */
4512 if (magic_switched_on) {
4513 ret = ksz_switch_macaddr_get(ds: dev->ds, port, NULL);
4514 if (ret)
4515 return ret;
4516 } else if (magic_switched_off) {
4517 ksz_switch_macaddr_put(ds: dev->ds);
4518 }
4519
4520 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4521 pme_ctrl);
4522 if (ret) {
4523 if (magic_switched_on)
4524 ksz_switch_macaddr_put(ds: dev->ds);
4525 return ret;
4526 }
4527
4528 return 0;
4529}
4530
4531/**
4532 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4533 * considering Wake-on-LAN (WoL) settings.
4534 * @dev: The switch device structure.
4535 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4536 * enabled on any port.
4537 *
4538 * This function prepares the switch device for a safe shutdown while taking
4539 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4540 * the wol_enabled flag accordingly to reflect whether WoL is active on any
4541 * port.
4542 */
4543static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4544{
4545 const struct ksz_dev_ops *ops = dev->dev_ops;
4546 const u16 *regs = dev->info->regs;
4547 u8 pme_pin_en = PME_ENABLE;
4548 struct dsa_port *dp;
4549 int ret;
4550
4551 *wol_enabled = false;
4552
4553 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4554 return;
4555
4556 if (!dev->wakeup_source)
4557 return;
4558
4559 dsa_switch_for_each_user_port(dp, dev->ds) {
4560 u8 pme_ctrl = 0;
4561
4562 ret = ops->pme_pread8(dev, dp->index,
4563 regs[REG_PORT_PME_CTRL], &pme_ctrl);
4564 if (!ret && pme_ctrl)
4565 *wol_enabled = true;
4566
4567 /* make sure there are no pending wake events which would
4568 * prevent the device from going to sleep/shutdown.
4569 */
4570 ksz_handle_wake_reason(dev, port: dp->index);
4571 }
4572
4573 /* Now we are save to enable PME pin. */
4574 if (*wol_enabled) {
4575 if (dev->pme_active_high)
4576 pme_pin_en |= PME_POLARITY;
4577 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4578 if (ksz_is_ksz87xx(dev))
4579 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4580 }
4581}
4582
4583static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4584 const unsigned char *addr)
4585{
4586 struct dsa_port *dp = dsa_to_port(ds, p: port);
4587 struct ethtool_wolinfo wol;
4588
4589 if (dp->hsr_dev) {
4590 dev_err(ds->dev,
4591 "Cannot change MAC address on port %d with active HSR offload\n",
4592 port);
4593 return -EBUSY;
4594 }
4595
4596 /* Need to initialize variable as the code to fill in settings may
4597 * not be executed.
4598 */
4599 wol.wolopts = 0;
4600
4601 ksz_get_wol(ds, port: dp->index, wol: &wol);
4602 if (wol.wolopts & WAKE_MAGIC) {
4603 dev_err(ds->dev,
4604 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4605 port);
4606 return -EBUSY;
4607 }
4608
4609 return 0;
4610}
4611
4612/**
4613 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4614 * can be used as a global address.
4615 * @ds: Pointer to the DSA switch structure.
4616 * @port: The port number on which the MAC address is to be checked.
4617 *
4618 * This function examines the MAC address set on the specified port and
4619 * determines if it can be used as a global address for the switch.
4620 *
4621 * Return: true if the port's MAC address can be used as a global address, false
4622 * otherwise.
4623 */
4624bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4625{
4626 struct net_device *user = dsa_to_port(ds, p: port)->user;
4627 const unsigned char *addr = user->dev_addr;
4628 struct ksz_switch_macaddr *switch_macaddr;
4629 struct ksz_device *dev = ds->priv;
4630
4631 ASSERT_RTNL();
4632
4633 switch_macaddr = dev->switch_macaddr;
4634 if (switch_macaddr && !ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr))
4635 return false;
4636
4637 return true;
4638}
4639
4640/**
4641 * ksz_switch_macaddr_get - Program the switch's MAC address register.
4642 * @ds: DSA switch instance.
4643 * @port: Port number.
4644 * @extack: Netlink extended acknowledgment.
4645 *
4646 * This function programs the switch's MAC address register with the MAC address
4647 * of the requesting user port. This single address is used by the switch for
4648 * multiple features like HSR self-address filtering and WoL. Other user ports
4649 * can share ownership of this address as long as their MAC address is the same.
4650 * The MAC addresses of user ports must not change while they have ownership of
4651 * the switch MAC address.
4652 *
4653 * Return: 0 on success, or other error codes on failure.
4654 */
4655int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4656 struct netlink_ext_ack *extack)
4657{
4658 struct net_device *user = dsa_to_port(ds, p: port)->user;
4659 const unsigned char *addr = user->dev_addr;
4660 struct ksz_switch_macaddr *switch_macaddr;
4661 struct ksz_device *dev = ds->priv;
4662 const u16 *regs = dev->info->regs;
4663 int i, ret;
4664
4665 /* Make sure concurrent MAC address changes are blocked */
4666 ASSERT_RTNL();
4667
4668 switch_macaddr = dev->switch_macaddr;
4669 if (switch_macaddr) {
4670 if (!ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr)) {
4671 NL_SET_ERR_MSG_FMT_MOD(extack,
4672 "Switch already configured for MAC address %pM",
4673 switch_macaddr->addr);
4674 return -EBUSY;
4675 }
4676
4677 refcount_inc(r: &switch_macaddr->refcount);
4678 return 0;
4679 }
4680
4681 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4682 if (!switch_macaddr)
4683 return -ENOMEM;
4684
4685 ether_addr_copy(dst: switch_macaddr->addr, src: addr);
4686 refcount_set(r: &switch_macaddr->refcount, n: 1);
4687 dev->switch_macaddr = switch_macaddr;
4688
4689 /* Program the switch MAC address to hardware */
4690 for (i = 0; i < ETH_ALEN; i++) {
4691 ret = ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: addr[i]);
4692 if (ret)
4693 goto macaddr_drop;
4694 }
4695
4696 return 0;
4697
4698macaddr_drop:
4699 dev->switch_macaddr = NULL;
4700 refcount_set(r: &switch_macaddr->refcount, n: 0);
4701 kfree(objp: switch_macaddr);
4702
4703 return ret;
4704}
4705
4706void ksz_switch_macaddr_put(struct dsa_switch *ds)
4707{
4708 struct ksz_switch_macaddr *switch_macaddr;
4709 struct ksz_device *dev = ds->priv;
4710 const u16 *regs = dev->info->regs;
4711 int i;
4712
4713 /* Make sure concurrent MAC address changes are blocked */
4714 ASSERT_RTNL();
4715
4716 switch_macaddr = dev->switch_macaddr;
4717 if (!refcount_dec_and_test(r: &switch_macaddr->refcount))
4718 return;
4719
4720 for (i = 0; i < ETH_ALEN; i++)
4721 ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: 0);
4722
4723 dev->switch_macaddr = NULL;
4724 kfree(objp: switch_macaddr);
4725}
4726
4727static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4728 struct netlink_ext_ack *extack)
4729{
4730 struct ksz_device *dev = ds->priv;
4731 enum hsr_version ver;
4732 int ret;
4733
4734 ret = hsr_get_version(dev: hsr, ver: &ver);
4735 if (ret)
4736 return ret;
4737
4738 if (dev->chip_id != KSZ9477_CHIP_ID) {
4739 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4740 return -EOPNOTSUPP;
4741 }
4742
4743 /* KSZ9477 can support HW offloading of only 1 HSR device */
4744 if (dev->hsr_dev && hsr != dev->hsr_dev) {
4745 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4746 return -EOPNOTSUPP;
4747 }
4748
4749 /* KSZ9477 only supports HSR v0 and v1 */
4750 if (!(ver == HSR_V0 || ver == HSR_V1)) {
4751 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4752 return -EOPNOTSUPP;
4753 }
4754
4755 /* KSZ9477 can only perform HSR offloading for up to two ports */
4756 if (hweight8(dev->hsr_ports) >= 2) {
4757 NL_SET_ERR_MSG_MOD(extack,
4758 "Cannot offload more than two ports - using software HSR");
4759 return -EOPNOTSUPP;
4760 }
4761
4762 /* Self MAC address filtering, to avoid frames traversing
4763 * the HSR ring more than once.
4764 */
4765 ret = ksz_switch_macaddr_get(ds, port, extack);
4766 if (ret)
4767 return ret;
4768
4769 ksz9477_hsr_join(ds, port, hsr);
4770 dev->hsr_dev = hsr;
4771 dev->hsr_ports |= BIT(port);
4772
4773 return 0;
4774}
4775
4776static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4777 struct net_device *hsr)
4778{
4779 struct ksz_device *dev = ds->priv;
4780
4781 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4782
4783 ksz9477_hsr_leave(ds, port, hsr);
4784 dev->hsr_ports &= ~BIT(port);
4785 if (!dev->hsr_ports)
4786 dev->hsr_dev = NULL;
4787
4788 ksz_switch_macaddr_put(ds);
4789
4790 return 0;
4791}
4792
4793static int ksz_suspend(struct dsa_switch *ds)
4794{
4795 struct ksz_device *dev = ds->priv;
4796
4797 cancel_delayed_work_sync(dwork: &dev->mib_read);
4798 return 0;
4799}
4800
4801static int ksz_resume(struct dsa_switch *ds)
4802{
4803 struct ksz_device *dev = ds->priv;
4804
4805 if (dev->mib_read_interval)
4806 schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval);
4807 return 0;
4808}
4809
4810static const struct dsa_switch_ops ksz_switch_ops = {
4811 .get_tag_protocol = ksz_get_tag_protocol,
4812 .connect_tag_protocol = ksz_connect_tag_protocol,
4813 .get_phy_flags = ksz_get_phy_flags,
4814 .setup = ksz_setup,
4815 .teardown = ksz_teardown,
4816 .phy_read = ksz_phy_read16,
4817 .phy_write = ksz_phy_write16,
4818 .phylink_get_caps = ksz_phylink_get_caps,
4819 .port_setup = ksz_port_setup,
4820 .set_ageing_time = ksz_set_ageing_time,
4821 .get_strings = ksz_get_strings,
4822 .get_ethtool_stats = ksz_get_ethtool_stats,
4823 .get_sset_count = ksz_sset_count,
4824 .port_bridge_join = ksz_port_bridge_join,
4825 .port_bridge_leave = ksz_port_bridge_leave,
4826 .port_hsr_join = ksz_hsr_join,
4827 .port_hsr_leave = ksz_hsr_leave,
4828 .port_set_mac_address = ksz_port_set_mac_address,
4829 .port_stp_state_set = ksz_port_stp_state_set,
4830 .port_teardown = ksz_port_teardown,
4831 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4832 .port_bridge_flags = ksz_port_bridge_flags,
4833 .port_fast_age = ksz_port_fast_age,
4834 .port_vlan_filtering = ksz_port_vlan_filtering,
4835 .port_vlan_add = ksz_port_vlan_add,
4836 .port_vlan_del = ksz_port_vlan_del,
4837 .port_fdb_dump = ksz_port_fdb_dump,
4838 .port_fdb_add = ksz_port_fdb_add,
4839 .port_fdb_del = ksz_port_fdb_del,
4840 .port_mdb_add = ksz_port_mdb_add,
4841 .port_mdb_del = ksz_port_mdb_del,
4842 .port_mirror_add = ksz_port_mirror_add,
4843 .port_mirror_del = ksz_port_mirror_del,
4844 .get_stats64 = ksz_get_stats64,
4845 .get_pause_stats = ksz_get_pause_stats,
4846 .port_change_mtu = ksz_change_mtu,
4847 .port_max_mtu = ksz_max_mtu,
4848 .get_wol = ksz_get_wol,
4849 .set_wol = ksz_set_wol,
4850 .suspend = ksz_suspend,
4851 .resume = ksz_resume,
4852 .get_ts_info = ksz_get_ts_info,
4853 .port_hwtstamp_get = ksz_hwtstamp_get,
4854 .port_hwtstamp_set = ksz_hwtstamp_set,
4855 .port_txtstamp = ksz_port_txtstamp,
4856 .port_rxtstamp = ksz_port_rxtstamp,
4857 .cls_flower_add = ksz_cls_flower_add,
4858 .cls_flower_del = ksz_cls_flower_del,
4859 .port_setup_tc = ksz_setup_tc,
4860 .support_eee = ksz_support_eee,
4861 .set_mac_eee = ksz_set_mac_eee,
4862 .port_get_default_prio = ksz_port_get_default_prio,
4863 .port_set_default_prio = ksz_port_set_default_prio,
4864 .port_get_dscp_prio = ksz_port_get_dscp_prio,
4865 .port_add_dscp_prio = ksz_port_add_dscp_prio,
4866 .port_del_dscp_prio = ksz_port_del_dscp_prio,
4867 .port_get_apptrust = ksz_port_get_apptrust,
4868 .port_set_apptrust = ksz_port_set_apptrust,
4869};
4870
4871struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
4872{
4873 struct dsa_switch *ds;
4874 struct ksz_device *swdev;
4875
4876 ds = devm_kzalloc(dev: base, size: sizeof(*ds), GFP_KERNEL);
4877 if (!ds)
4878 return NULL;
4879
4880 ds->dev = base;
4881 ds->num_ports = DSA_MAX_PORTS;
4882 ds->ops = &ksz_switch_ops;
4883
4884 swdev = devm_kzalloc(dev: base, size: sizeof(*swdev), GFP_KERNEL);
4885 if (!swdev)
4886 return NULL;
4887
4888 ds->priv = swdev;
4889 swdev->dev = base;
4890
4891 swdev->ds = ds;
4892 swdev->priv = priv;
4893
4894 return swdev;
4895}
4896EXPORT_SYMBOL(ksz_switch_alloc);
4897
4898/**
4899 * ksz_switch_shutdown - Shutdown routine for the switch device.
4900 * @dev: The switch device structure.
4901 *
4902 * This function is responsible for initiating a shutdown sequence for the
4903 * switch device. It invokes the reset operation defined in the device
4904 * operations, if available, to reset the switch. Subsequently, it calls the
4905 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
4906 * switch.
4907 */
4908void ksz_switch_shutdown(struct ksz_device *dev)
4909{
4910 bool wol_enabled = false;
4911
4912 ksz_wol_pre_shutdown(dev, wol_enabled: &wol_enabled);
4913
4914 if (dev->dev_ops->reset && !wol_enabled)
4915 dev->dev_ops->reset(dev);
4916
4917 dsa_switch_shutdown(ds: dev->ds);
4918}
4919EXPORT_SYMBOL(ksz_switch_shutdown);
4920
4921static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
4922 struct device_node *port_dn)
4923{
4924 phy_interface_t phy_mode = dev->ports[port_num].interface;
4925 int rx_delay = -1, tx_delay = -1;
4926
4927 if (!phy_interface_mode_is_rgmii(mode: phy_mode))
4928 return;
4929
4930 of_property_read_u32(np: port_dn, propname: "rx-internal-delay-ps", out_value: &rx_delay);
4931 of_property_read_u32(np: port_dn, propname: "tx-internal-delay-ps", out_value: &tx_delay);
4932
4933 if (rx_delay == -1 && tx_delay == -1) {
4934 dev_warn(dev->dev,
4935 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
4936 "please update device tree to specify \"rx-internal-delay-ps\" and "
4937 "\"tx-internal-delay-ps\"",
4938 port_num);
4939
4940 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
4941 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4942 rx_delay = 2000;
4943
4944 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
4945 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4946 tx_delay = 2000;
4947 }
4948
4949 if (rx_delay < 0)
4950 rx_delay = 0;
4951 if (tx_delay < 0)
4952 tx_delay = 0;
4953
4954 dev->ports[port_num].rgmii_rx_val = rx_delay;
4955 dev->ports[port_num].rgmii_tx_val = tx_delay;
4956}
4957
4958/**
4959 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
4960 * register value.
4961 * @array: The array of drive strength values to search.
4962 * @array_size: The size of the array.
4963 * @microamp: The drive strength value in microamp to be converted.
4964 *
4965 * This function searches the array of drive strength values for the given
4966 * microamp value and returns the corresponding register value for that drive.
4967 *
4968 * Returns: If found, the corresponding register value for that drive strength
4969 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
4970 */
4971static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
4972 size_t array_size, int microamp)
4973{
4974 int i;
4975
4976 for (i = 0; i < array_size; i++) {
4977 if (array[i].microamp == microamp)
4978 return array[i].reg_val;
4979 }
4980
4981 return -EINVAL;
4982}
4983
4984/**
4985 * ksz_drive_strength_error() - Report invalid drive strength value
4986 * @dev: ksz device
4987 * @array: The array of drive strength values to search.
4988 * @array_size: The size of the array.
4989 * @microamp: Invalid drive strength value in microamp
4990 *
4991 * This function logs an error message when an unsupported drive strength value
4992 * is detected. It lists out all the supported drive strength values for
4993 * reference in the error message.
4994 */
4995static void ksz_drive_strength_error(struct ksz_device *dev,
4996 const struct ksz_drive_strength *array,
4997 size_t array_size, int microamp)
4998{
4999 char supported_values[100];
5000 size_t remaining_size;
5001 int added_len;
5002 char *ptr;
5003 int i;
5004
5005 remaining_size = sizeof(supported_values);
5006 ptr = supported_values;
5007
5008 for (i = 0; i < array_size; i++) {
5009 added_len = snprintf(buf: ptr, size: remaining_size,
5010 fmt: i == 0 ? "%d" : ", %d", array[i].microamp);
5011
5012 if (added_len >= remaining_size)
5013 break;
5014
5015 ptr += added_len;
5016 remaining_size -= added_len;
5017 }
5018
5019 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
5020 microamp, supported_values);
5021}
5022
5023/**
5024 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
5025 * chip variants.
5026 * @dev: ksz device
5027 * @props: Array of drive strength properties to be applied
5028 * @num_props: Number of properties in the array
5029 *
5030 * This function configures the drive strength for various KSZ9477 chip variants
5031 * based on the provided properties. It handles chip-specific nuances and
5032 * ensures only valid drive strengths are written to the respective chip.
5033 *
5034 * Return: 0 on successful configuration, a negative error code on failure.
5035 */
5036static int ksz9477_drive_strength_write(struct ksz_device *dev,
5037 struct ksz_driver_strength_prop *props,
5038 int num_props)
5039{
5040 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
5041 int i, ret, reg;
5042 u8 mask = 0;
5043 u8 val = 0;
5044
5045 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
5046 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5047 props[KSZ_DRIVER_STRENGTH_IO].name);
5048
5049 if (dev->chip_id == KSZ8795_CHIP_ID ||
5050 dev->chip_id == KSZ8794_CHIP_ID ||
5051 dev->chip_id == KSZ8765_CHIP_ID)
5052 reg = KSZ8795_REG_SW_CTRL_20;
5053 else
5054 reg = KSZ9477_REG_SW_IO_STRENGTH;
5055
5056 for (i = 0; i < num_props; i++) {
5057 if (props[i].value == -1)
5058 continue;
5059
5060 ret = ksz_drive_strength_to_reg(array: ksz9477_drive_strengths,
5061 array_size, microamp: props[i].value);
5062 if (ret < 0) {
5063 ksz_drive_strength_error(dev, array: ksz9477_drive_strengths,
5064 array_size, microamp: props[i].value);
5065 return ret;
5066 }
5067
5068 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
5069 val |= ret << props[i].offset;
5070 }
5071
5072 return ksz_rmw8(dev, offset: reg, mask, val);
5073}
5074
5075/**
5076 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
5077 * KSZ8863 compatible chip variants.
5078 * @dev: ksz device
5079 * @props: Array of drive strength properties to be set
5080 * @num_props: Number of properties in the array
5081 *
5082 * This function applies the specified drive strength settings to KSZ88X3 chip
5083 * variants (KSZ8873, KSZ8863).
5084 * It ensures the configurations align with what the chip variant supports and
5085 * warns or errors out on unsupported settings.
5086 *
5087 * Return: 0 on success, error code otherwise
5088 */
5089static int ksz88x3_drive_strength_write(struct ksz_device *dev,
5090 struct ksz_driver_strength_prop *props,
5091 int num_props)
5092{
5093 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
5094 int microamp;
5095 int i, ret;
5096
5097 for (i = 0; i < num_props; i++) {
5098 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
5099 continue;
5100
5101 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5102 props[i].name);
5103 }
5104
5105 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
5106 ret = ksz_drive_strength_to_reg(array: ksz88x3_drive_strengths, array_size,
5107 microamp);
5108 if (ret < 0) {
5109 ksz_drive_strength_error(dev, array: ksz88x3_drive_strengths,
5110 array_size, microamp);
5111 return ret;
5112 }
5113
5114 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
5115 KSZ8873_DRIVE_STRENGTH_16MA, val: ret);
5116}
5117
5118/**
5119 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
5120 * from device tree properties.
5121 * @dev: ksz device
5122 *
5123 * This function reads the specified drive strength properties from the
5124 * device tree, validates against the supported chip variants, and sets
5125 * them accordingly. An error should be critical here, as the drive strength
5126 * settings are crucial for EMI compliance.
5127 *
5128 * Return: 0 on success, error code otherwise
5129 */
5130static int ksz_parse_drive_strength(struct ksz_device *dev)
5131{
5132 struct ksz_driver_strength_prop of_props[] = {
5133 [KSZ_DRIVER_STRENGTH_HI] = {
5134 .name = "microchip,hi-drive-strength-microamp",
5135 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
5136 .value = -1,
5137 },
5138 [KSZ_DRIVER_STRENGTH_LO] = {
5139 .name = "microchip,lo-drive-strength-microamp",
5140 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
5141 .value = -1,
5142 },
5143 [KSZ_DRIVER_STRENGTH_IO] = {
5144 .name = "microchip,io-drive-strength-microamp",
5145 .offset = 0, /* don't care */
5146 .value = -1,
5147 },
5148 };
5149 struct device_node *np = dev->dev->of_node;
5150 bool have_any_prop = false;
5151 int i, ret;
5152
5153 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5154 ret = of_property_read_u32(np, propname: of_props[i].name,
5155 out_value: &of_props[i].value);
5156 if (ret && ret != -EINVAL)
5157 dev_warn(dev->dev, "Failed to read %s\n",
5158 of_props[i].name);
5159 if (ret)
5160 continue;
5161
5162 have_any_prop = true;
5163 }
5164
5165 if (!have_any_prop)
5166 return 0;
5167
5168 switch (dev->chip_id) {
5169 case KSZ88X3_CHIP_ID:
5170 return ksz88x3_drive_strength_write(dev, props: of_props,
5171 ARRAY_SIZE(of_props));
5172 case KSZ8795_CHIP_ID:
5173 case KSZ8794_CHIP_ID:
5174 case KSZ8765_CHIP_ID:
5175 case KSZ8563_CHIP_ID:
5176 case KSZ8567_CHIP_ID:
5177 case KSZ9477_CHIP_ID:
5178 case KSZ9563_CHIP_ID:
5179 case KSZ9567_CHIP_ID:
5180 case KSZ9893_CHIP_ID:
5181 case KSZ9896_CHIP_ID:
5182 case KSZ9897_CHIP_ID:
5183 case LAN9646_CHIP_ID:
5184 return ksz9477_drive_strength_write(dev, props: of_props,
5185 ARRAY_SIZE(of_props));
5186 default:
5187 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5188 if (of_props[i].value == -1)
5189 continue;
5190
5191 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5192 of_props[i].name);
5193 }
5194 }
5195
5196 return 0;
5197}
5198
5199int ksz_switch_register(struct ksz_device *dev)
5200{
5201 const struct ksz_chip_data *info;
5202 struct device_node *ports;
5203 phy_interface_t interface;
5204 unsigned int port_num;
5205 int ret;
5206 int i;
5207
5208 dev->reset_gpio = devm_gpiod_get_optional(dev: dev->dev, con_id: "reset",
5209 flags: GPIOD_OUT_LOW);
5210 if (IS_ERR(ptr: dev->reset_gpio))
5211 return PTR_ERR(ptr: dev->reset_gpio);
5212
5213 if (dev->reset_gpio) {
5214 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
5215 usleep_range(min: 10000, max: 12000);
5216 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 0);
5217 msleep(msecs: 100);
5218 }
5219
5220 mutex_init(&dev->dev_mutex);
5221 mutex_init(&dev->regmap_mutex);
5222 mutex_init(&dev->alu_mutex);
5223 mutex_init(&dev->vlan_mutex);
5224
5225 ret = ksz_switch_detect(dev);
5226 if (ret)
5227 return ret;
5228
5229 info = ksz_lookup_info(prod_num: dev->chip_id);
5230 if (!info)
5231 return -ENODEV;
5232
5233 /* Update the compatible info with the probed one */
5234 dev->info = info;
5235
5236 dev_info(dev->dev, "found switch: %s, rev %i\n",
5237 dev->info->dev_name, dev->chip_rev);
5238
5239 ret = ksz_check_device_id(dev);
5240 if (ret)
5241 return ret;
5242
5243 dev->dev_ops = dev->info->ops;
5244
5245 ret = dev->dev_ops->init(dev);
5246 if (ret)
5247 return ret;
5248
5249 dev->ports = devm_kzalloc(dev: dev->dev,
5250 size: dev->info->port_cnt * sizeof(struct ksz_port),
5251 GFP_KERNEL);
5252 if (!dev->ports)
5253 return -ENOMEM;
5254
5255 for (i = 0; i < dev->info->port_cnt; i++) {
5256 spin_lock_init(&dev->ports[i].mib.stats64_lock);
5257 mutex_init(&dev->ports[i].mib.cnt_mutex);
5258 dev->ports[i].mib.counters =
5259 devm_kzalloc(dev: dev->dev,
5260 size: sizeof(u64) * (dev->info->mib_cnt + 1),
5261 GFP_KERNEL);
5262 if (!dev->ports[i].mib.counters)
5263 return -ENOMEM;
5264
5265 dev->ports[i].ksz_dev = dev;
5266 dev->ports[i].num = i;
5267 }
5268
5269 /* set the real number of ports */
5270 dev->ds->num_ports = dev->info->port_cnt;
5271
5272 /* set the phylink ops */
5273 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5274
5275 /* Host port interface will be self detected, or specifically set in
5276 * device tree.
5277 */
5278 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5279 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5280 if (dev->dev->of_node) {
5281 ret = of_get_phy_mode(np: dev->dev->of_node, interface: &interface);
5282 if (ret == 0)
5283 dev->compat_interface = interface;
5284 ports = of_get_child_by_name(node: dev->dev->of_node, name: "ethernet-ports");
5285 if (!ports)
5286 ports = of_get_child_by_name(node: dev->dev->of_node, name: "ports");
5287 if (ports) {
5288 for_each_available_child_of_node_scoped(ports, port) {
5289 if (of_property_read_u32(np: port, propname: "reg",
5290 out_value: &port_num))
5291 continue;
5292 if (!(dev->port_mask & BIT(port_num))) {
5293 of_node_put(node: ports);
5294 return -EINVAL;
5295 }
5296 of_get_phy_mode(np: port,
5297 interface: &dev->ports[port_num].interface);
5298
5299 ksz_parse_rgmii_delay(dev, port_num, port_dn: port);
5300 }
5301 of_node_put(node: ports);
5302 }
5303 dev->synclko_125 = of_property_read_bool(np: dev->dev->of_node,
5304 propname: "microchip,synclko-125");
5305 dev->synclko_disable = of_property_read_bool(np: dev->dev->of_node,
5306 propname: "microchip,synclko-disable");
5307 if (dev->synclko_125 && dev->synclko_disable) {
5308 dev_err(dev->dev, "inconsistent synclko settings\n");
5309 return -EINVAL;
5310 }
5311
5312 dev->wakeup_source = of_property_read_bool(np: dev->dev->of_node,
5313 propname: "wakeup-source");
5314 dev->pme_active_high = of_property_read_bool(np: dev->dev->of_node,
5315 propname: "microchip,pme-active-high");
5316 }
5317
5318 ret = dsa_register_switch(ds: dev->ds);
5319 if (ret) {
5320 dev->dev_ops->exit(dev);
5321 return ret;
5322 }
5323
5324 /* Read MIB counters every 30 seconds to avoid overflow. */
5325 dev->mib_read_interval = msecs_to_jiffies(m: 5000);
5326
5327 /* Start the MIB timer. */
5328 schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
5329
5330 return ret;
5331}
5332EXPORT_SYMBOL(ksz_switch_register);
5333
5334void ksz_switch_remove(struct ksz_device *dev)
5335{
5336 /* timer started */
5337 if (dev->mib_read_interval) {
5338 dev->mib_read_interval = 0;
5339 cancel_delayed_work_sync(dwork: &dev->mib_read);
5340 }
5341
5342 dev->dev_ops->exit(dev);
5343 dsa_unregister_switch(ds: dev->ds);
5344
5345 if (dev->reset_gpio)
5346 gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
5347
5348}
5349EXPORT_SYMBOL(ksz_switch_remove);
5350
5351#ifdef CONFIG_PM_SLEEP
5352int ksz_switch_suspend(struct device *dev)
5353{
5354 struct ksz_device *priv = dev_get_drvdata(dev);
5355
5356 return dsa_switch_suspend(ds: priv->ds);
5357}
5358EXPORT_SYMBOL(ksz_switch_suspend);
5359
5360int ksz_switch_resume(struct device *dev)
5361{
5362 struct ksz_device *priv = dev_get_drvdata(dev);
5363
5364 return dsa_switch_resume(ds: priv->ds);
5365}
5366EXPORT_SYMBOL(ksz_switch_resume);
5367#endif
5368
5369MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5370MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5371MODULE_LICENSE("GPL");
5372

source code of linux/drivers/net/dsa/microchip/ksz_common.c