1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Microchip switch driver main logic
4	*
5	* Copyright (C) 2017-2025 Microchip Technology Inc.
6	*/
7
8	#include <linux/delay.h>
9	#include <linux/dsa/ksz_common.h>
10	#include <linux/export.h>
11	#include <linux/gpio/consumer.h>
12	#include <linux/kernel.h>
13	#include <linux/module.h>
14	#include <linux/platform_data/microchip-ksz.h>
15	#include <linux/phy.h>
16	#include <linux/etherdevice.h>
17	#include <linux/if_bridge.h>
18	#include <linux/if_vlan.h>
19	#include <linux/if_hsr.h>
20	#include <linux/irq.h>
21	#include <linux/irqdomain.h>
22	#include <linux/of.h>
23	#include <linux/of_mdio.h>
24	#include <linux/of_net.h>
25	#include <linux/micrel_phy.h>
26	#include <linux/pinctrl/consumer.h>
27	#include <net/dsa.h>
28	#include <net/ieee8021q.h>
29	#include <net/pkt_cls.h>
30	#include <net/switchdev.h>
31
32	#include "ksz_common.h"
33	#include "ksz_dcb.h"
34	#include "ksz_ptp.h"
35	#include "ksz8.h"
36	#include "ksz9477.h"
37	#include "lan937x.h"
38
39	#define MIB_COUNTER_NUM 0x20
40
41	struct ksz_stats_raw {
42	u64 rx_hi;
43	u64 rx_undersize;
44	u64 rx_fragments;
45	u64 rx_oversize;
46	u64 rx_jabbers;
47	u64 rx_symbol_err;
48	u64 rx_crc_err;
49	u64 rx_align_err;
50	u64 rx_mac_ctrl;
51	u64 rx_pause;
52	u64 rx_bcast;
53	u64 rx_mcast;
54	u64 rx_ucast;
55	u64 rx_64_or_less;
56	u64 rx_65_127;
57	u64 rx_128_255;
58	u64 rx_256_511;
59	u64 rx_512_1023;
60	u64 rx_1024_1522;
61	u64 rx_1523_2000;
62	u64 rx_2001;
63	u64 tx_hi;
64	u64 tx_late_col;
65	u64 tx_pause;
66	u64 tx_bcast;
67	u64 tx_mcast;
68	u64 tx_ucast;
69	u64 tx_deferred;
70	u64 tx_total_col;
71	u64 tx_exc_col;
72	u64 tx_single_col;
73	u64 tx_mult_col;
74	u64 rx_total;
75	u64 tx_total;
76	u64 rx_discards;
77	u64 tx_discards;
78	};
79
80	struct ksz88xx_stats_raw {
81	u64 rx;
82	u64 rx_hi;
83	u64 rx_undersize;
84	u64 rx_fragments;
85	u64 rx_oversize;
86	u64 rx_jabbers;
87	u64 rx_symbol_err;
88	u64 rx_crc_err;
89	u64 rx_align_err;
90	u64 rx_mac_ctrl;
91	u64 rx_pause;
92	u64 rx_bcast;
93	u64 rx_mcast;
94	u64 rx_ucast;
95	u64 rx_64_or_less;
96	u64 rx_65_127;
97	u64 rx_128_255;
98	u64 rx_256_511;
99	u64 rx_512_1023;
100	u64 rx_1024_1522;
101	u64 tx;
102	u64 tx_hi;
103	u64 tx_late_col;
104	u64 tx_pause;
105	u64 tx_bcast;
106	u64 tx_mcast;
107	u64 tx_ucast;
108	u64 tx_deferred;
109	u64 tx_total_col;
110	u64 tx_exc_col;
111	u64 tx_single_col;
112	u64 tx_mult_col;
113	u64 rx_discards;
114	u64 tx_discards;
115	};
116
117	static const struct ksz_mib_names ksz88xx_mib_names[] = {
118	{ 0x00, "rx" },
119	{ 0x01, "rx_hi" },
120	{ 0x02, "rx_undersize" },
121	{ 0x03, "rx_fragments" },
122	{ 0x04, "rx_oversize" },
123	{ 0x05, "rx_jabbers" },
124	{ 0x06, "rx_symbol_err" },
125	{ 0x07, "rx_crc_err" },
126	{ 0x08, "rx_align_err" },
127	{ 0x09, "rx_mac_ctrl" },
128	{ 0x0a, "rx_pause" },
129	{ 0x0b, "rx_bcast" },
130	{ 0x0c, "rx_mcast" },
131	{ 0x0d, "rx_ucast" },
132	{ 0x0e, "rx_64_or_less" },
133	{ 0x0f, "rx_65_127" },
134	{ 0x10, "rx_128_255" },
135	{ 0x11, "rx_256_511" },
136	{ 0x12, "rx_512_1023" },
137	{ 0x13, "rx_1024_1522" },
138	{ 0x14, "tx" },
139	{ 0x15, "tx_hi" },
140	{ 0x16, "tx_late_col" },
141	{ 0x17, "tx_pause" },
142	{ 0x18, "tx_bcast" },
143	{ 0x19, "tx_mcast" },
144	{ 0x1a, "tx_ucast" },
145	{ 0x1b, "tx_deferred" },
146	{ 0x1c, "tx_total_col" },
147	{ 0x1d, "tx_exc_col" },
148	{ 0x1e, "tx_single_col" },
149	{ 0x1f, "tx_mult_col" },
150	{ 0x100, "rx_discards" },
151	{ 0x101, "tx_discards" },
152	};
153
154	static const struct ksz_mib_names ksz9477_mib_names[] = {
155	{ 0x00, "rx_hi" },
156	{ 0x01, "rx_undersize" },
157	{ 0x02, "rx_fragments" },
158	{ 0x03, "rx_oversize" },
159	{ 0x04, "rx_jabbers" },
160	{ 0x05, "rx_symbol_err" },
161	{ 0x06, "rx_crc_err" },
162	{ 0x07, "rx_align_err" },
163	{ 0x08, "rx_mac_ctrl" },
164	{ 0x09, "rx_pause" },
165	{ 0x0A, "rx_bcast" },
166	{ 0x0B, "rx_mcast" },
167	{ 0x0C, "rx_ucast" },
168	{ 0x0D, "rx_64_or_less" },
169	{ 0x0E, "rx_65_127" },
170	{ 0x0F, "rx_128_255" },
171	{ 0x10, "rx_256_511" },
172	{ 0x11, "rx_512_1023" },
173	{ 0x12, "rx_1024_1522" },
174	{ 0x13, "rx_1523_2000" },
175	{ 0x14, "rx_2001" },
176	{ 0x15, "tx_hi" },
177	{ 0x16, "tx_late_col" },
178	{ 0x17, "tx_pause" },
179	{ 0x18, "tx_bcast" },
180	{ 0x19, "tx_mcast" },
181	{ 0x1A, "tx_ucast" },
182	{ 0x1B, "tx_deferred" },
183	{ 0x1C, "tx_total_col" },
184	{ 0x1D, "tx_exc_col" },
185	{ 0x1E, "tx_single_col" },
186	{ 0x1F, "tx_mult_col" },
187	{ 0x80, "rx_total" },
188	{ 0x81, "tx_total" },
189	{ 0x82, "rx_discards" },
190	{ 0x83, "tx_discards" },
191	};
192
193	struct ksz_driver_strength_prop {
194	const char *name;
195	int offset;
196	int value;
197	};
198
199	enum ksz_driver_strength_type {
200	KSZ_DRIVER_STRENGTH_HI,
201	KSZ_DRIVER_STRENGTH_LO,
202	KSZ_DRIVER_STRENGTH_IO,
203	};
204
205	/**
206	* struct ksz_drive_strength - drive strength mapping
207	* @reg_val: register value
208	* @microamp: microamp value
209	*/
210	struct ksz_drive_strength {
211	u32 reg_val;
212	u32 microamp;
213	};
214
215	/* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
216	*
217	* This values are not documented in KSZ9477 variants but confirmed by
218	* Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
219	* and KSZ8563 are using same register (drive strength) settings like KSZ8795.
220	*
221	* Documentation in KSZ8795CLX provides more information with some
222	* recommendations:
223	* - for high speed signals
224	* 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
225	* 2.5V or 3.3V VDDIO.
226	* 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
227	* using 1.8V VDDIO.
228	* 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
229	* or 3.3V VDDIO.
230	* 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
231	* 5. In same interface, the heavy loading should use higher one of the
232	* drive current strength.
233	* - for low speed signals
234	* 1. 3.3V VDDIO, use either 4 mA or 8 mA.
235	* 2. 2.5V VDDIO, use either 8 mA or 12 mA.
236	* 3. 1.8V VDDIO, use either 12 mA or 16 mA.
237	* 4. If it is heavy loading, can use higher drive current strength.
238	*/
239	static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
240	{ SW_DRIVE_STRENGTH_2MA, 2000 },
241	{ SW_DRIVE_STRENGTH_4MA, 4000 },
242	{ SW_DRIVE_STRENGTH_8MA, 8000 },
243	{ SW_DRIVE_STRENGTH_12MA, 12000 },
244	{ SW_DRIVE_STRENGTH_16MA, 16000 },
245	{ SW_DRIVE_STRENGTH_20MA, 20000 },
246	{ SW_DRIVE_STRENGTH_24MA, 24000 },
247	{ SW_DRIVE_STRENGTH_28MA, 28000 },
248	};
249
250	/* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
251	* variants.
252	* This values are documented in KSZ8873 and KSZ8863 datasheets.
253	*/
254	static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
255	{ 0, 8000 },
256	{ KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
257	};
258
259	static void ksz88x3_phylink_mac_config(struct phylink_config *config,
260	unsigned int mode,
261	const struct phylink_link_state *state);
262	static void ksz_phylink_mac_config(struct phylink_config *config,
263	unsigned int mode,
264	const struct phylink_link_state *state);
265	static void ksz_phylink_mac_link_down(struct phylink_config *config,
266	unsigned int mode,
267	phy_interface_t interface);
268
269	/**
270	* ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
271	* @config: phylink config structure
272	*
273	* This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for
274	* a detailed explanation of EEE/LPI handling in KSZ switches.
275	*/
276	static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config)
277	{
278	}
279
280	/**
281	* ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
282	* @config: phylink config structure
283	* @timer: timer value before entering LPI (unused)
284	* @tx_clock_stop: whether to stop the TX clock in LPI mode (unused)
285	*
286	* This function signals to phylink that the driver architecture supports
287	* LPI management, enabling phylink to control EEE advertisement during
288	* negotiation according to IEEE Std 802.3 (Clause 78).
289	*
290	* Hardware Management of EEE/LPI State:
291	* For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2),
292	* observation and testing suggest that the actual EEE / Low Power Idle (LPI)
293	* state transitions are managed autonomously by the hardware based on
294	* the auto-negotiation results. (Note: While the datasheet describes EEE
295	* operation based on negotiation, it doesn't explicitly detail the internal
296	* MAC/PHY interaction, so autonomous hardware management of the MAC state
297	* for LPI is inferred from observed behavior).
298	* This hardware control, consistent with the switch's ability to operate
299	* autonomously via strapping, means MAC-level software intervention is not
300	* required or exposed for managing the LPI state once EEE is negotiated.
301	* (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining
302	* EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration
303	* Straps).
304	*
305	* Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3)
306	* lack documented MAC-level LPI control.
307	*
308	* Therefore, this callback performs no action and serves primarily to inform
309	* phylink of LPI awareness and to document the inferred hardware behavior.
310	*
311	* Returns: 0 (Always success)
312	*/
313	static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
314	u32 timer, bool tx_clock_stop)
315	{
316	return 0;
317	}
318
319	static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
320	.mac_config = ksz88x3_phylink_mac_config,
321	.mac_link_down = ksz_phylink_mac_link_down,
322	.mac_link_up = ksz8_phylink_mac_link_up,
323	.mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
324	.mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
325	};
326
327	static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
328	.mac_config = ksz_phylink_mac_config,
329	.mac_link_down = ksz_phylink_mac_link_down,
330	.mac_link_up = ksz8_phylink_mac_link_up,
331	.mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
332	.mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
333	};
334
335	static const struct ksz_dev_ops ksz8463_dev_ops = {
336	.setup = ksz8_setup,
337	.get_port_addr = ksz8463_get_port_addr,
338	.cfg_port_member = ksz8_cfg_port_member,
339	.flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
340	.port_setup = ksz8_port_setup,
341	.r_phy = ksz8463_r_phy,
342	.w_phy = ksz8463_w_phy,
343	.r_mib_cnt = ksz8_r_mib_cnt,
344	.r_mib_pkt = ksz8_r_mib_pkt,
345	.r_mib_stat64 = ksz88xx_r_mib_stats64,
346	.freeze_mib = ksz8_freeze_mib,
347	.port_init_cnt = ksz8_port_init_cnt,
348	.fdb_dump = ksz8_fdb_dump,
349	.fdb_add = ksz8_fdb_add,
350	.fdb_del = ksz8_fdb_del,
351	.mdb_add = ksz8_mdb_add,
352	.mdb_del = ksz8_mdb_del,
353	.vlan_filtering = ksz8_port_vlan_filtering,
354	.vlan_add = ksz8_port_vlan_add,
355	.vlan_del = ksz8_port_vlan_del,
356	.mirror_add = ksz8_port_mirror_add,
357	.mirror_del = ksz8_port_mirror_del,
358	.get_caps = ksz8_get_caps,
359	.config_cpu_port = ksz8_config_cpu_port,
360	.enable_stp_addr = ksz8_enable_stp_addr,
361	.reset = ksz8_reset_switch,
362	.init = ksz8_switch_init,
363	.exit = ksz8_switch_exit,
364	.change_mtu = ksz8_change_mtu,
365	};
366
367	static const struct ksz_dev_ops ksz88xx_dev_ops = {
368	.setup = ksz8_setup,
369	.get_port_addr = ksz8_get_port_addr,
370	.cfg_port_member = ksz8_cfg_port_member,
371	.flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
372	.port_setup = ksz8_port_setup,
373	.r_phy = ksz8_r_phy,
374	.w_phy = ksz8_w_phy,
375	.r_mib_cnt = ksz8_r_mib_cnt,
376	.r_mib_pkt = ksz8_r_mib_pkt,
377	.r_mib_stat64 = ksz88xx_r_mib_stats64,
378	.freeze_mib = ksz8_freeze_mib,
379	.port_init_cnt = ksz8_port_init_cnt,
380	.fdb_dump = ksz8_fdb_dump,
381	.fdb_add = ksz8_fdb_add,
382	.fdb_del = ksz8_fdb_del,
383	.mdb_add = ksz8_mdb_add,
384	.mdb_del = ksz8_mdb_del,
385	.vlan_filtering = ksz8_port_vlan_filtering,
386	.vlan_add = ksz8_port_vlan_add,
387	.vlan_del = ksz8_port_vlan_del,
388	.mirror_add = ksz8_port_mirror_add,
389	.mirror_del = ksz8_port_mirror_del,
390	.get_caps = ksz8_get_caps,
391	.config_cpu_port = ksz8_config_cpu_port,
392	.enable_stp_addr = ksz8_enable_stp_addr,
393	.reset = ksz8_reset_switch,
394	.init = ksz8_switch_init,
395	.exit = ksz8_switch_exit,
396	.change_mtu = ksz8_change_mtu,
397	.pme_write8 = ksz8_pme_write8,
398	.pme_pread8 = ksz8_pme_pread8,
399	.pme_pwrite8 = ksz8_pme_pwrite8,
400	};
401
402	static const struct ksz_dev_ops ksz87xx_dev_ops = {
403	.setup = ksz8_setup,
404	.get_port_addr = ksz8_get_port_addr,
405	.cfg_port_member = ksz8_cfg_port_member,
406	.flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
407	.port_setup = ksz8_port_setup,
408	.r_phy = ksz8_r_phy,
409	.w_phy = ksz8_w_phy,
410	.r_mib_cnt = ksz8_r_mib_cnt,
411	.r_mib_pkt = ksz8_r_mib_pkt,
412	.r_mib_stat64 = ksz_r_mib_stats64,
413	.freeze_mib = ksz8_freeze_mib,
414	.port_init_cnt = ksz8_port_init_cnt,
415	.fdb_dump = ksz8_fdb_dump,
416	.fdb_add = ksz8_fdb_add,
417	.fdb_del = ksz8_fdb_del,
418	.mdb_add = ksz8_mdb_add,
419	.mdb_del = ksz8_mdb_del,
420	.vlan_filtering = ksz8_port_vlan_filtering,
421	.vlan_add = ksz8_port_vlan_add,
422	.vlan_del = ksz8_port_vlan_del,
423	.mirror_add = ksz8_port_mirror_add,
424	.mirror_del = ksz8_port_mirror_del,
425	.get_caps = ksz8_get_caps,
426	.config_cpu_port = ksz8_config_cpu_port,
427	.enable_stp_addr = ksz8_enable_stp_addr,
428	.reset = ksz8_reset_switch,
429	.init = ksz8_switch_init,
430	.exit = ksz8_switch_exit,
431	.change_mtu = ksz8_change_mtu,
432	.pme_write8 = ksz8_pme_write8,
433	.pme_pread8 = ksz8_pme_pread8,
434	.pme_pwrite8 = ksz8_pme_pwrite8,
435	};
436
437	static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
438	struct phy_device *phydev,
439	unsigned int mode,
440	phy_interface_t interface,
441	int speed, int duplex, bool tx_pause,
442	bool rx_pause);
443
444	static struct phylink_pcs *
445	ksz_phylink_mac_select_pcs(struct phylink_config *config,
446	phy_interface_t interface)
447	{
448	struct dsa_port *dp = dsa_phylink_to_port(config);
449	struct ksz_device *dev = dp->ds->priv;
450	struct ksz_port *p = &dev->ports[dp->index];
451
452	if (ksz_is_sgmii_port(dev, port: dp->index) &&
453	(interface == PHY_INTERFACE_MODE_SGMII ||
454	interface == PHY_INTERFACE_MODE_1000BASEX))
455	return p->pcs;
456
457	return NULL;
458	}
459
460	static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
461	.mac_config = ksz_phylink_mac_config,
462	.mac_link_down = ksz_phylink_mac_link_down,
463	.mac_link_up = ksz9477_phylink_mac_link_up,
464	.mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
465	.mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
466	.mac_select_pcs = ksz_phylink_mac_select_pcs,
467	};
468
469	static const struct ksz_dev_ops ksz9477_dev_ops = {
470	.setup = ksz9477_setup,
471	.get_port_addr = ksz9477_get_port_addr,
472	.cfg_port_member = ksz9477_cfg_port_member,
473	.flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
474	.port_setup = ksz9477_port_setup,
475	.set_ageing_time = ksz9477_set_ageing_time,
476	.r_phy = ksz9477_r_phy,
477	.w_phy = ksz9477_w_phy,
478	.r_mib_cnt = ksz9477_r_mib_cnt,
479	.r_mib_pkt = ksz9477_r_mib_pkt,
480	.r_mib_stat64 = ksz_r_mib_stats64,
481	.freeze_mib = ksz9477_freeze_mib,
482	.port_init_cnt = ksz9477_port_init_cnt,
483	.vlan_filtering = ksz9477_port_vlan_filtering,
484	.vlan_add = ksz9477_port_vlan_add,
485	.vlan_del = ksz9477_port_vlan_del,
486	.mirror_add = ksz9477_port_mirror_add,
487	.mirror_del = ksz9477_port_mirror_del,
488	.get_caps = ksz9477_get_caps,
489	.fdb_dump = ksz9477_fdb_dump,
490	.fdb_add = ksz9477_fdb_add,
491	.fdb_del = ksz9477_fdb_del,
492	.mdb_add = ksz9477_mdb_add,
493	.mdb_del = ksz9477_mdb_del,
494	.change_mtu = ksz9477_change_mtu,
495	.pme_write8 = ksz_write8,
496	.pme_pread8 = ksz_pread8,
497	.pme_pwrite8 = ksz_pwrite8,
498	.config_cpu_port = ksz9477_config_cpu_port,
499	.tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
500	.enable_stp_addr = ksz9477_enable_stp_addr,
501	.reset = ksz9477_reset_switch,
502	.init = ksz9477_switch_init,
503	.exit = ksz9477_switch_exit,
504	.pcs_create = ksz9477_pcs_create,
505	};
506
507	static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
508	.mac_config = ksz_phylink_mac_config,
509	.mac_link_down = ksz_phylink_mac_link_down,
510	.mac_link_up = ksz9477_phylink_mac_link_up,
511	.mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
512	.mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
513	};
514
515	static const struct ksz_dev_ops lan937x_dev_ops = {
516	.setup = lan937x_setup,
517	.teardown = lan937x_teardown,
518	.get_port_addr = ksz9477_get_port_addr,
519	.cfg_port_member = ksz9477_cfg_port_member,
520	.flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
521	.port_setup = lan937x_port_setup,
522	.set_ageing_time = lan937x_set_ageing_time,
523	.mdio_bus_preinit = lan937x_mdio_bus_preinit,
524	.create_phy_addr_map = lan937x_create_phy_addr_map,
525	.r_phy = lan937x_r_phy,
526	.w_phy = lan937x_w_phy,
527	.r_mib_cnt = ksz9477_r_mib_cnt,
528	.r_mib_pkt = ksz9477_r_mib_pkt,
529	.r_mib_stat64 = ksz_r_mib_stats64,
530	.freeze_mib = ksz9477_freeze_mib,
531	.port_init_cnt = ksz9477_port_init_cnt,
532	.vlan_filtering = ksz9477_port_vlan_filtering,
533	.vlan_add = ksz9477_port_vlan_add,
534	.vlan_del = ksz9477_port_vlan_del,
535	.mirror_add = ksz9477_port_mirror_add,
536	.mirror_del = ksz9477_port_mirror_del,
537	.get_caps = lan937x_phylink_get_caps,
538	.setup_rgmii_delay = lan937x_setup_rgmii_delay,
539	.fdb_dump = ksz9477_fdb_dump,
540	.fdb_add = ksz9477_fdb_add,
541	.fdb_del = ksz9477_fdb_del,
542	.mdb_add = ksz9477_mdb_add,
543	.mdb_del = ksz9477_mdb_del,
544	.change_mtu = lan937x_change_mtu,
545	.config_cpu_port = lan937x_config_cpu_port,
546	.tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
547	.enable_stp_addr = ksz9477_enable_stp_addr,
548	.reset = lan937x_reset_switch,
549	.init = lan937x_switch_init,
550	.exit = lan937x_switch_exit,
551	};
552
553	static const u16 ksz8463_regs[] = {
554	[REG_SW_MAC_ADDR] = 0x10,
555	[REG_IND_CTRL_0] = 0x30,
556	[REG_IND_DATA_8] = 0x26,
557	[REG_IND_DATA_CHECK] = 0x26,
558	[REG_IND_DATA_HI] = 0x28,
559	[REG_IND_DATA_LO] = 0x2C,
560	[REG_IND_MIB_CHECK] = 0x2F,
561	[P_FORCE_CTRL] = 0x0C,
562	[P_LINK_STATUS] = 0x0E,
563	[P_LOCAL_CTRL] = 0x0C,
564	[P_NEG_RESTART_CTRL] = 0x0D,
565	[P_REMOTE_STATUS] = 0x0E,
566	[P_SPEED_STATUS] = 0x0F,
567	[S_TAIL_TAG_CTRL] = 0xAD,
568	[P_STP_CTRL] = 0x6F,
569	[S_START_CTRL] = 0x01,
570	[S_BROADCAST_CTRL] = 0x06,
571	[S_MULTICAST_CTRL] = 0x04,
572	};
573
574	static const u32 ksz8463_masks[] = {
575	[PORT_802_1P_REMAPPING] = BIT(3),
576	[SW_TAIL_TAG_ENABLE] = BIT(0),
577	[MIB_COUNTER_OVERFLOW] = BIT(7),
578	[MIB_COUNTER_VALID] = BIT(6),
579	[VLAN_TABLE_FID] = GENMASK(15, 12),
580	[VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
581	[VLAN_TABLE_VALID] = BIT(19),
582	[STATIC_MAC_TABLE_VALID] = BIT(19),
583	[STATIC_MAC_TABLE_USE_FID] = BIT(21),
584	[STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
585	[STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
586	[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
587	[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
588	[DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
589	[DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
590	[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
591	[DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
592	[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
593	[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
594	};
595
596	static u8 ksz8463_shifts[] = {
597	[VLAN_TABLE_MEMBERSHIP_S] = 16,
598	[STATIC_MAC_FWD_PORTS] = 16,
599	[STATIC_MAC_FID] = 22,
600	[DYNAMIC_MAC_ENTRIES_H] = 8,
601	[DYNAMIC_MAC_ENTRIES] = 24,
602	[DYNAMIC_MAC_FID] = 16,
603	[DYNAMIC_MAC_TIMESTAMP] = 22,
604	[DYNAMIC_MAC_SRC_PORT] = 20,
605	};
606
607	static const u16 ksz8795_regs[] = {
608	[REG_SW_MAC_ADDR] = 0x68,
609	[REG_IND_CTRL_0] = 0x6E,
610	[REG_IND_DATA_8] = 0x70,
611	[REG_IND_DATA_CHECK] = 0x72,
612	[REG_IND_DATA_HI] = 0x71,
613	[REG_IND_DATA_LO] = 0x75,
614	[REG_IND_MIB_CHECK] = 0x74,
615	[REG_IND_BYTE] = 0xA0,
616	[P_FORCE_CTRL] = 0x0C,
617	[P_LINK_STATUS] = 0x0E,
618	[P_LOCAL_CTRL] = 0x07,
619	[P_NEG_RESTART_CTRL] = 0x0D,
620	[P_REMOTE_STATUS] = 0x08,
621	[P_SPEED_STATUS] = 0x09,
622	[S_TAIL_TAG_CTRL] = 0x0C,
623	[P_STP_CTRL] = 0x02,
624	[S_START_CTRL] = 0x01,
625	[S_BROADCAST_CTRL] = 0x06,
626	[S_MULTICAST_CTRL] = 0x04,
627	[P_XMII_CTRL_0] = 0x06,
628	[P_XMII_CTRL_1] = 0x06,
629	[REG_SW_PME_CTRL] = 0x8003,
630	[REG_PORT_PME_STATUS] = 0x8003,
631	[REG_PORT_PME_CTRL] = 0x8007,
632	};
633
634	static const u32 ksz8795_masks[] = {
635	[PORT_802_1P_REMAPPING] = BIT(7),
636	[SW_TAIL_TAG_ENABLE] = BIT(1),
637	[MIB_COUNTER_OVERFLOW] = BIT(6),
638	[MIB_COUNTER_VALID] = BIT(5),
639	[VLAN_TABLE_FID] = GENMASK(6, 0),
640	[VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
641	[VLAN_TABLE_VALID] = BIT(12),
642	[STATIC_MAC_TABLE_VALID] = BIT(21),
643	[STATIC_MAC_TABLE_USE_FID] = BIT(23),
644	[STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
645	[STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
646	[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
647	[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
648	[DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
649	[DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
650	[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
651	[DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
652	[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
653	[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
654	[P_MII_TX_FLOW_CTRL] = BIT(5),
655	[P_MII_RX_FLOW_CTRL] = BIT(5),
656	};
657
658	static const u8 ksz8795_xmii_ctrl0[] = {
659	[P_MII_100MBIT] = 0,
660	[P_MII_10MBIT] = 1,
661	[P_MII_FULL_DUPLEX] = 0,
662	[P_MII_HALF_DUPLEX] = 1,
663	};
664
665	static const u8 ksz8795_xmii_ctrl1[] = {
666	[P_RGMII_SEL] = 3,
667	[P_GMII_SEL] = 2,
668	[P_RMII_SEL] = 1,
669	[P_MII_SEL] = 0,
670	[P_GMII_1GBIT] = 1,
671	[P_GMII_NOT_1GBIT] = 0,
672	};
673
674	static const u8 ksz8795_shifts[] = {
675	[VLAN_TABLE_MEMBERSHIP_S] = 7,
676	[VLAN_TABLE] = 16,
677	[STATIC_MAC_FWD_PORTS] = 16,
678	[STATIC_MAC_FID] = 24,
679	[DYNAMIC_MAC_ENTRIES_H] = 3,
680	[DYNAMIC_MAC_ENTRIES] = 29,
681	[DYNAMIC_MAC_FID] = 16,
682	[DYNAMIC_MAC_TIMESTAMP] = 27,
683	[DYNAMIC_MAC_SRC_PORT] = 24,
684	};
685
686	static const u16 ksz8863_regs[] = {
687	[REG_SW_MAC_ADDR] = 0x70,
688	[REG_IND_CTRL_0] = 0x79,
689	[REG_IND_DATA_8] = 0x7B,
690	[REG_IND_DATA_CHECK] = 0x7B,
691	[REG_IND_DATA_HI] = 0x7C,
692	[REG_IND_DATA_LO] = 0x80,
693	[REG_IND_MIB_CHECK] = 0x80,
694	[P_FORCE_CTRL] = 0x0C,
695	[P_LINK_STATUS] = 0x0E,
696	[P_LOCAL_CTRL] = 0x0C,
697	[P_NEG_RESTART_CTRL] = 0x0D,
698	[P_REMOTE_STATUS] = 0x0E,
699	[P_SPEED_STATUS] = 0x0F,
700	[S_TAIL_TAG_CTRL] = 0x03,
701	[P_STP_CTRL] = 0x02,
702	[S_START_CTRL] = 0x01,
703	[S_BROADCAST_CTRL] = 0x06,
704	[S_MULTICAST_CTRL] = 0x04,
705	};
706
707	static const u32 ksz8863_masks[] = {
708	[PORT_802_1P_REMAPPING] = BIT(3),
709	[SW_TAIL_TAG_ENABLE] = BIT(6),
710	[MIB_COUNTER_OVERFLOW] = BIT(7),
711	[MIB_COUNTER_VALID] = BIT(6),
712	[VLAN_TABLE_FID] = GENMASK(15, 12),
713	[VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
714	[VLAN_TABLE_VALID] = BIT(19),
715	[STATIC_MAC_TABLE_VALID] = BIT(19),
716	[STATIC_MAC_TABLE_USE_FID] = BIT(21),
717	[STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
718	[STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
719	[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
720	[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
721	[DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
722	[DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
723	[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
724	[DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
725	[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
726	[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
727	};
728
729	static u8 ksz8863_shifts[] = {
730	[VLAN_TABLE_MEMBERSHIP_S] = 16,
731	[STATIC_MAC_FWD_PORTS] = 16,
732	[STATIC_MAC_FID] = 22,
733	[DYNAMIC_MAC_ENTRIES_H] = 8,
734	[DYNAMIC_MAC_ENTRIES] = 24,
735	[DYNAMIC_MAC_FID] = 16,
736	[DYNAMIC_MAC_TIMESTAMP] = 22,
737	[DYNAMIC_MAC_SRC_PORT] = 20,
738	};
739
740	static const u16 ksz8895_regs[] = {
741	[REG_SW_MAC_ADDR] = 0x68,
742	[REG_IND_CTRL_0] = 0x6E,
743	[REG_IND_DATA_8] = 0x70,
744	[REG_IND_DATA_CHECK] = 0x72,
745	[REG_IND_DATA_HI] = 0x71,
746	[REG_IND_DATA_LO] = 0x75,
747	[REG_IND_MIB_CHECK] = 0x75,
748	[P_FORCE_CTRL] = 0x0C,
749	[P_LINK_STATUS] = 0x0E,
750	[P_LOCAL_CTRL] = 0x0C,
751	[P_NEG_RESTART_CTRL] = 0x0D,
752	[P_REMOTE_STATUS] = 0x0E,
753	[P_SPEED_STATUS] = 0x09,
754	[S_TAIL_TAG_CTRL] = 0x0C,
755	[P_STP_CTRL] = 0x02,
756	[S_START_CTRL] = 0x01,
757	[S_BROADCAST_CTRL] = 0x06,
758	[S_MULTICAST_CTRL] = 0x04,
759	};
760
761	static const u32 ksz8895_masks[] = {
762	[PORT_802_1P_REMAPPING] = BIT(7),
763	[SW_TAIL_TAG_ENABLE] = BIT(1),
764	[MIB_COUNTER_OVERFLOW] = BIT(7),
765	[MIB_COUNTER_VALID] = BIT(6),
766	[VLAN_TABLE_FID] = GENMASK(6, 0),
767	[VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
768	[VLAN_TABLE_VALID] = BIT(12),
769	[STATIC_MAC_TABLE_VALID] = BIT(21),
770	[STATIC_MAC_TABLE_USE_FID] = BIT(23),
771	[STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
772	[STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
773	[STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
774	[DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
775	[DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
776	[DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
777	[DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
778	[DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
779	[DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
780	[DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
781	};
782
783	static const u8 ksz8895_shifts[] = {
784	[VLAN_TABLE_MEMBERSHIP_S] = 7,
785	[VLAN_TABLE] = 13,
786	[STATIC_MAC_FWD_PORTS] = 16,
787	[STATIC_MAC_FID] = 24,
788	[DYNAMIC_MAC_ENTRIES_H] = 3,
789	[DYNAMIC_MAC_ENTRIES] = 29,
790	[DYNAMIC_MAC_FID] = 16,
791	[DYNAMIC_MAC_TIMESTAMP] = 27,
792	[DYNAMIC_MAC_SRC_PORT] = 24,
793	};
794
795	static const u16 ksz9477_regs[] = {
796	[REG_SW_MAC_ADDR] = 0x0302,
797	[P_STP_CTRL] = 0x0B04,
798	[S_START_CTRL] = 0x0300,
799	[S_BROADCAST_CTRL] = 0x0332,
800	[S_MULTICAST_CTRL] = 0x0331,
801	[P_XMII_CTRL_0] = 0x0300,
802	[P_XMII_CTRL_1] = 0x0301,
803	[REG_SW_PME_CTRL] = 0x0006,
804	[REG_PORT_PME_STATUS] = 0x0013,
805	[REG_PORT_PME_CTRL] = 0x0017,
806	};
807
808	static const u32 ksz9477_masks[] = {
809	[ALU_STAT_WRITE] = 0,
810	[ALU_STAT_READ] = 1,
811	[ALU_STAT_DIRECT] = 0,
812	[ALU_RESV_MCAST_ADDR] = BIT(1),
813	[P_MII_TX_FLOW_CTRL] = BIT(5),
814	[P_MII_RX_FLOW_CTRL] = BIT(3),
815	};
816
817	static const u8 ksz9477_shifts[] = {
818	[ALU_STAT_INDEX] = 16,
819	};
820
821	static const u8 ksz9477_xmii_ctrl0[] = {
822	[P_MII_100MBIT] = 1,
823	[P_MII_10MBIT] = 0,
824	[P_MII_FULL_DUPLEX] = 1,
825	[P_MII_HALF_DUPLEX] = 0,
826	};
827
828	static const u8 ksz9477_xmii_ctrl1[] = {
829	[P_RGMII_SEL] = 0,
830	[P_RMII_SEL] = 1,
831	[P_GMII_SEL] = 2,
832	[P_MII_SEL] = 3,
833	[P_GMII_1GBIT] = 0,
834	[P_GMII_NOT_1GBIT] = 1,
835	};
836
837	static const u32 lan937x_masks[] = {
838	[ALU_STAT_WRITE] = 1,
839	[ALU_STAT_READ] = 2,
840	[ALU_STAT_DIRECT] = BIT(3),
841	[ALU_RESV_MCAST_ADDR] = BIT(2),
842	[P_MII_TX_FLOW_CTRL] = BIT(5),
843	[P_MII_RX_FLOW_CTRL] = BIT(3),
844	};
845
846	static const u8 lan937x_shifts[] = {
847	[ALU_STAT_INDEX] = 8,
848	};
849
850	static const struct regmap_range ksz8563_valid_regs[] = {
851	regmap_reg_range(0x0000, 0x0003),
852	regmap_reg_range(0x0006, 0x0006),
853	regmap_reg_range(0x000f, 0x001f),
854	regmap_reg_range(0x0100, 0x0100),
855	regmap_reg_range(0x0104, 0x0107),
856	regmap_reg_range(0x010d, 0x010d),
857	regmap_reg_range(0x0110, 0x0113),
858	regmap_reg_range(0x0120, 0x012b),
859	regmap_reg_range(0x0201, 0x0201),
860	regmap_reg_range(0x0210, 0x0213),
861	regmap_reg_range(0x0300, 0x0300),
862	regmap_reg_range(0x0302, 0x031b),
863	regmap_reg_range(0x0320, 0x032b),
864	regmap_reg_range(0x0330, 0x0336),
865	regmap_reg_range(0x0338, 0x033e),
866	regmap_reg_range(0x0340, 0x035f),
867	regmap_reg_range(0x0370, 0x0370),
868	regmap_reg_range(0x0378, 0x0378),
869	regmap_reg_range(0x037c, 0x037d),
870	regmap_reg_range(0x0390, 0x0393),
871	regmap_reg_range(0x0400, 0x040e),
872	regmap_reg_range(0x0410, 0x042f),
873	regmap_reg_range(0x0500, 0x0519),
874	regmap_reg_range(0x0520, 0x054b),
875	regmap_reg_range(0x0550, 0x05b3),
876
877	/* port 1 */
878	regmap_reg_range(0x1000, 0x1001),
879	regmap_reg_range(0x1004, 0x100b),
880	regmap_reg_range(0x1013, 0x1013),
881	regmap_reg_range(0x1017, 0x1017),
882	regmap_reg_range(0x101b, 0x101b),
883	regmap_reg_range(0x101f, 0x1021),
884	regmap_reg_range(0x1030, 0x1030),
885	regmap_reg_range(0x1100, 0x1111),
886	regmap_reg_range(0x111a, 0x111d),
887	regmap_reg_range(0x1122, 0x1127),
888	regmap_reg_range(0x112a, 0x112b),
889	regmap_reg_range(0x1136, 0x1139),
890	regmap_reg_range(0x113e, 0x113f),
891	regmap_reg_range(0x1400, 0x1401),
892	regmap_reg_range(0x1403, 0x1403),
893	regmap_reg_range(0x1410, 0x1417),
894	regmap_reg_range(0x1420, 0x1423),
895	regmap_reg_range(0x1500, 0x1507),
896	regmap_reg_range(0x1600, 0x1612),
897	regmap_reg_range(0x1800, 0x180f),
898	regmap_reg_range(0x1900, 0x1907),
899	regmap_reg_range(0x1914, 0x191b),
900	regmap_reg_range(0x1a00, 0x1a03),
901	regmap_reg_range(0x1a04, 0x1a08),
902	regmap_reg_range(0x1b00, 0x1b01),
903	regmap_reg_range(0x1b04, 0x1b04),
904	regmap_reg_range(0x1c00, 0x1c05),
905	regmap_reg_range(0x1c08, 0x1c1b),
906
907	/* port 2 */
908	regmap_reg_range(0x2000, 0x2001),
909	regmap_reg_range(0x2004, 0x200b),
910	regmap_reg_range(0x2013, 0x2013),
911	regmap_reg_range(0x2017, 0x2017),
912	regmap_reg_range(0x201b, 0x201b),
913	regmap_reg_range(0x201f, 0x2021),
914	regmap_reg_range(0x2030, 0x2030),
915	regmap_reg_range(0x2100, 0x2111),
916	regmap_reg_range(0x211a, 0x211d),
917	regmap_reg_range(0x2122, 0x2127),
918	regmap_reg_range(0x212a, 0x212b),
919	regmap_reg_range(0x2136, 0x2139),
920	regmap_reg_range(0x213e, 0x213f),
921	regmap_reg_range(0x2400, 0x2401),
922	regmap_reg_range(0x2403, 0x2403),
923	regmap_reg_range(0x2410, 0x2417),
924	regmap_reg_range(0x2420, 0x2423),
925	regmap_reg_range(0x2500, 0x2507),
926	regmap_reg_range(0x2600, 0x2612),
927	regmap_reg_range(0x2800, 0x280f),
928	regmap_reg_range(0x2900, 0x2907),
929	regmap_reg_range(0x2914, 0x291b),
930	regmap_reg_range(0x2a00, 0x2a03),
931	regmap_reg_range(0x2a04, 0x2a08),
932	regmap_reg_range(0x2b00, 0x2b01),
933	regmap_reg_range(0x2b04, 0x2b04),
934	regmap_reg_range(0x2c00, 0x2c05),
935	regmap_reg_range(0x2c08, 0x2c1b),
936
937	/* port 3 */
938	regmap_reg_range(0x3000, 0x3001),
939	regmap_reg_range(0x3004, 0x300b),
940	regmap_reg_range(0x3013, 0x3013),
941	regmap_reg_range(0x3017, 0x3017),
942	regmap_reg_range(0x301b, 0x301b),
943	regmap_reg_range(0x301f, 0x3021),
944	regmap_reg_range(0x3030, 0x3030),
945	regmap_reg_range(0x3300, 0x3301),
946	regmap_reg_range(0x3303, 0x3303),
947	regmap_reg_range(0x3400, 0x3401),
948	regmap_reg_range(0x3403, 0x3403),
949	regmap_reg_range(0x3410, 0x3417),
950	regmap_reg_range(0x3420, 0x3423),
951	regmap_reg_range(0x3500, 0x3507),
952	regmap_reg_range(0x3600, 0x3612),
953	regmap_reg_range(0x3800, 0x380f),
954	regmap_reg_range(0x3900, 0x3907),
955	regmap_reg_range(0x3914, 0x391b),
956	regmap_reg_range(0x3a00, 0x3a03),
957	regmap_reg_range(0x3a04, 0x3a08),
958	regmap_reg_range(0x3b00, 0x3b01),
959	regmap_reg_range(0x3b04, 0x3b04),
960	regmap_reg_range(0x3c00, 0x3c05),
961	regmap_reg_range(0x3c08, 0x3c1b),
962	};
963
964	static const struct regmap_access_table ksz8563_register_set = {
965	.yes_ranges = ksz8563_valid_regs,
966	.n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
967	};
968
969	static const struct regmap_range ksz9477_valid_regs[] = {
970	regmap_reg_range(0x0000, 0x0003),
971	regmap_reg_range(0x0006, 0x0006),
972	regmap_reg_range(0x0010, 0x001f),
973	regmap_reg_range(0x0100, 0x0100),
974	regmap_reg_range(0x0103, 0x0107),
975	regmap_reg_range(0x010d, 0x010d),
976	regmap_reg_range(0x0110, 0x0113),
977	regmap_reg_range(0x0120, 0x012b),
978	regmap_reg_range(0x0201, 0x0201),
979	regmap_reg_range(0x0210, 0x0213),
980	regmap_reg_range(0x0300, 0x0300),
981	regmap_reg_range(0x0302, 0x031b),
982	regmap_reg_range(0x0320, 0x032b),
983	regmap_reg_range(0x0330, 0x0336),
984	regmap_reg_range(0x0338, 0x033b),
985	regmap_reg_range(0x033e, 0x033e),
986	regmap_reg_range(0x0340, 0x035f),
987	regmap_reg_range(0x0370, 0x0370),
988	regmap_reg_range(0x0378, 0x0378),
989	regmap_reg_range(0x037c, 0x037d),
990	regmap_reg_range(0x0390, 0x0393),
991	regmap_reg_range(0x0400, 0x040e),
992	regmap_reg_range(0x0410, 0x042f),
993	regmap_reg_range(0x0444, 0x044b),
994	regmap_reg_range(0x0450, 0x046f),
995	regmap_reg_range(0x0500, 0x0519),
996	regmap_reg_range(0x0520, 0x054b),
997	regmap_reg_range(0x0550, 0x05b3),
998	regmap_reg_range(0x0604, 0x060b),
999	regmap_reg_range(0x0610, 0x0612),
1000	regmap_reg_range(0x0614, 0x062c),
1001	regmap_reg_range(0x0640, 0x0645),
1002	regmap_reg_range(0x0648, 0x064d),
1003
1004	/* port 1 */
1005	regmap_reg_range(0x1000, 0x1001),
1006	regmap_reg_range(0x1013, 0x1013),
1007	regmap_reg_range(0x1017, 0x1017),
1008	regmap_reg_range(0x101b, 0x101b),
1009	regmap_reg_range(0x101f, 0x1020),
1010	regmap_reg_range(0x1030, 0x1030),
1011	regmap_reg_range(0x1100, 0x1115),
1012	regmap_reg_range(0x111a, 0x111f),
1013	regmap_reg_range(0x1120, 0x112b),
1014	regmap_reg_range(0x1134, 0x113b),
1015	regmap_reg_range(0x113c, 0x113f),
1016	regmap_reg_range(0x1400, 0x1401),
1017	regmap_reg_range(0x1403, 0x1403),
1018	regmap_reg_range(0x1410, 0x1417),
1019	regmap_reg_range(0x1420, 0x1423),
1020	regmap_reg_range(0x1500, 0x1507),
1021	regmap_reg_range(0x1600, 0x1613),
1022	regmap_reg_range(0x1800, 0x180f),
1023	regmap_reg_range(0x1820, 0x1827),
1024	regmap_reg_range(0x1830, 0x1837),
1025	regmap_reg_range(0x1840, 0x184b),
1026	regmap_reg_range(0x1900, 0x1907),
1027	regmap_reg_range(0x1914, 0x191b),
1028	regmap_reg_range(0x1920, 0x1920),
1029	regmap_reg_range(0x1923, 0x1927),
1030	regmap_reg_range(0x1a00, 0x1a03),
1031	regmap_reg_range(0x1a04, 0x1a07),
1032	regmap_reg_range(0x1b00, 0x1b01),
1033	regmap_reg_range(0x1b04, 0x1b04),
1034	regmap_reg_range(0x1c00, 0x1c05),
1035	regmap_reg_range(0x1c08, 0x1c1b),
1036
1037	/* port 2 */
1038	regmap_reg_range(0x2000, 0x2001),
1039	regmap_reg_range(0x2013, 0x2013),
1040	regmap_reg_range(0x2017, 0x2017),
1041	regmap_reg_range(0x201b, 0x201b),
1042	regmap_reg_range(0x201f, 0x2020),
1043	regmap_reg_range(0x2030, 0x2030),
1044	regmap_reg_range(0x2100, 0x2115),
1045	regmap_reg_range(0x211a, 0x211f),
1046	regmap_reg_range(0x2120, 0x212b),
1047	regmap_reg_range(0x2134, 0x213b),
1048	regmap_reg_range(0x213c, 0x213f),
1049	regmap_reg_range(0x2400, 0x2401),
1050	regmap_reg_range(0x2403, 0x2403),
1051	regmap_reg_range(0x2410, 0x2417),
1052	regmap_reg_range(0x2420, 0x2423),
1053	regmap_reg_range(0x2500, 0x2507),
1054	regmap_reg_range(0x2600, 0x2613),
1055	regmap_reg_range(0x2800, 0x280f),
1056	regmap_reg_range(0x2820, 0x2827),
1057	regmap_reg_range(0x2830, 0x2837),
1058	regmap_reg_range(0x2840, 0x284b),
1059	regmap_reg_range(0x2900, 0x2907),
1060	regmap_reg_range(0x2914, 0x291b),
1061	regmap_reg_range(0x2920, 0x2920),
1062	regmap_reg_range(0x2923, 0x2927),
1063	regmap_reg_range(0x2a00, 0x2a03),
1064	regmap_reg_range(0x2a04, 0x2a07),
1065	regmap_reg_range(0x2b00, 0x2b01),
1066	regmap_reg_range(0x2b04, 0x2b04),
1067	regmap_reg_range(0x2c00, 0x2c05),
1068	regmap_reg_range(0x2c08, 0x2c1b),
1069
1070	/* port 3 */
1071	regmap_reg_range(0x3000, 0x3001),
1072	regmap_reg_range(0x3013, 0x3013),
1073	regmap_reg_range(0x3017, 0x3017),
1074	regmap_reg_range(0x301b, 0x301b),
1075	regmap_reg_range(0x301f, 0x3020),
1076	regmap_reg_range(0x3030, 0x3030),
1077	regmap_reg_range(0x3100, 0x3115),
1078	regmap_reg_range(0x311a, 0x311f),
1079	regmap_reg_range(0x3120, 0x312b),
1080	regmap_reg_range(0x3134, 0x313b),
1081	regmap_reg_range(0x313c, 0x313f),
1082	regmap_reg_range(0x3400, 0x3401),
1083	regmap_reg_range(0x3403, 0x3403),
1084	regmap_reg_range(0x3410, 0x3417),
1085	regmap_reg_range(0x3420, 0x3423),
1086	regmap_reg_range(0x3500, 0x3507),
1087	regmap_reg_range(0x3600, 0x3613),
1088	regmap_reg_range(0x3800, 0x380f),
1089	regmap_reg_range(0x3820, 0x3827),
1090	regmap_reg_range(0x3830, 0x3837),
1091	regmap_reg_range(0x3840, 0x384b),
1092	regmap_reg_range(0x3900, 0x3907),
1093	regmap_reg_range(0x3914, 0x391b),
1094	regmap_reg_range(0x3920, 0x3920),
1095	regmap_reg_range(0x3923, 0x3927),
1096	regmap_reg_range(0x3a00, 0x3a03),
1097	regmap_reg_range(0x3a04, 0x3a07),
1098	regmap_reg_range(0x3b00, 0x3b01),
1099	regmap_reg_range(0x3b04, 0x3b04),
1100	regmap_reg_range(0x3c00, 0x3c05),
1101	regmap_reg_range(0x3c08, 0x3c1b),
1102
1103	/* port 4 */
1104	regmap_reg_range(0x4000, 0x4001),
1105	regmap_reg_range(0x4013, 0x4013),
1106	regmap_reg_range(0x4017, 0x4017),
1107	regmap_reg_range(0x401b, 0x401b),
1108	regmap_reg_range(0x401f, 0x4020),
1109	regmap_reg_range(0x4030, 0x4030),
1110	regmap_reg_range(0x4100, 0x4115),
1111	regmap_reg_range(0x411a, 0x411f),
1112	regmap_reg_range(0x4120, 0x412b),
1113	regmap_reg_range(0x4134, 0x413b),
1114	regmap_reg_range(0x413c, 0x413f),
1115	regmap_reg_range(0x4400, 0x4401),
1116	regmap_reg_range(0x4403, 0x4403),
1117	regmap_reg_range(0x4410, 0x4417),
1118	regmap_reg_range(0x4420, 0x4423),
1119	regmap_reg_range(0x4500, 0x4507),
1120	regmap_reg_range(0x4600, 0x4613),
1121	regmap_reg_range(0x4800, 0x480f),
1122	regmap_reg_range(0x4820, 0x4827),
1123	regmap_reg_range(0x4830, 0x4837),
1124	regmap_reg_range(0x4840, 0x484b),
1125	regmap_reg_range(0x4900, 0x4907),
1126	regmap_reg_range(0x4914, 0x491b),
1127	regmap_reg_range(0x4920, 0x4920),
1128	regmap_reg_range(0x4923, 0x4927),
1129	regmap_reg_range(0x4a00, 0x4a03),
1130	regmap_reg_range(0x4a04, 0x4a07),
1131	regmap_reg_range(0x4b00, 0x4b01),
1132	regmap_reg_range(0x4b04, 0x4b04),
1133	regmap_reg_range(0x4c00, 0x4c05),
1134	regmap_reg_range(0x4c08, 0x4c1b),
1135
1136	/* port 5 */
1137	regmap_reg_range(0x5000, 0x5001),
1138	regmap_reg_range(0x5013, 0x5013),
1139	regmap_reg_range(0x5017, 0x5017),
1140	regmap_reg_range(0x501b, 0x501b),
1141	regmap_reg_range(0x501f, 0x5020),
1142	regmap_reg_range(0x5030, 0x5030),
1143	regmap_reg_range(0x5100, 0x5115),
1144	regmap_reg_range(0x511a, 0x511f),
1145	regmap_reg_range(0x5120, 0x512b),
1146	regmap_reg_range(0x5134, 0x513b),
1147	regmap_reg_range(0x513c, 0x513f),
1148	regmap_reg_range(0x5400, 0x5401),
1149	regmap_reg_range(0x5403, 0x5403),
1150	regmap_reg_range(0x5410, 0x5417),
1151	regmap_reg_range(0x5420, 0x5423),
1152	regmap_reg_range(0x5500, 0x5507),
1153	regmap_reg_range(0x5600, 0x5613),
1154	regmap_reg_range(0x5800, 0x580f),
1155	regmap_reg_range(0x5820, 0x5827),
1156	regmap_reg_range(0x5830, 0x5837),
1157	regmap_reg_range(0x5840, 0x584b),
1158	regmap_reg_range(0x5900, 0x5907),
1159	regmap_reg_range(0x5914, 0x591b),
1160	regmap_reg_range(0x5920, 0x5920),
1161	regmap_reg_range(0x5923, 0x5927),
1162	regmap_reg_range(0x5a00, 0x5a03),
1163	regmap_reg_range(0x5a04, 0x5a07),
1164	regmap_reg_range(0x5b00, 0x5b01),
1165	regmap_reg_range(0x5b04, 0x5b04),
1166	regmap_reg_range(0x5c00, 0x5c05),
1167	regmap_reg_range(0x5c08, 0x5c1b),
1168
1169	/* port 6 */
1170	regmap_reg_range(0x6000, 0x6001),
1171	regmap_reg_range(0x6013, 0x6013),
1172	regmap_reg_range(0x6017, 0x6017),
1173	regmap_reg_range(0x601b, 0x601b),
1174	regmap_reg_range(0x601f, 0x6020),
1175	regmap_reg_range(0x6030, 0x6030),
1176	regmap_reg_range(0x6300, 0x6301),
1177	regmap_reg_range(0x6400, 0x6401),
1178	regmap_reg_range(0x6403, 0x6403),
1179	regmap_reg_range(0x6410, 0x6417),
1180	regmap_reg_range(0x6420, 0x6423),
1181	regmap_reg_range(0x6500, 0x6507),
1182	regmap_reg_range(0x6600, 0x6613),
1183	regmap_reg_range(0x6800, 0x680f),
1184	regmap_reg_range(0x6820, 0x6827),
1185	regmap_reg_range(0x6830, 0x6837),
1186	regmap_reg_range(0x6840, 0x684b),
1187	regmap_reg_range(0x6900, 0x6907),
1188	regmap_reg_range(0x6914, 0x691b),
1189	regmap_reg_range(0x6920, 0x6920),
1190	regmap_reg_range(0x6923, 0x6927),
1191	regmap_reg_range(0x6a00, 0x6a03),
1192	regmap_reg_range(0x6a04, 0x6a07),
1193	regmap_reg_range(0x6b00, 0x6b01),
1194	regmap_reg_range(0x6b04, 0x6b04),
1195	regmap_reg_range(0x6c00, 0x6c05),
1196	regmap_reg_range(0x6c08, 0x6c1b),
1197
1198	/* port 7 */
1199	regmap_reg_range(0x7000, 0x7001),
1200	regmap_reg_range(0x7013, 0x7013),
1201	regmap_reg_range(0x7017, 0x7017),
1202	regmap_reg_range(0x701b, 0x701b),
1203	regmap_reg_range(0x701f, 0x7020),
1204	regmap_reg_range(0x7030, 0x7030),
1205	regmap_reg_range(0x7200, 0x7207),
1206	regmap_reg_range(0x7300, 0x7301),
1207	regmap_reg_range(0x7400, 0x7401),
1208	regmap_reg_range(0x7403, 0x7403),
1209	regmap_reg_range(0x7410, 0x7417),
1210	regmap_reg_range(0x7420, 0x7423),
1211	regmap_reg_range(0x7500, 0x7507),
1212	regmap_reg_range(0x7600, 0x7613),
1213	regmap_reg_range(0x7800, 0x780f),
1214	regmap_reg_range(0x7820, 0x7827),
1215	regmap_reg_range(0x7830, 0x7837),
1216	regmap_reg_range(0x7840, 0x784b),
1217	regmap_reg_range(0x7900, 0x7907),
1218	regmap_reg_range(0x7914, 0x791b),
1219	regmap_reg_range(0x7920, 0x7920),
1220	regmap_reg_range(0x7923, 0x7927),
1221	regmap_reg_range(0x7a00, 0x7a03),
1222	regmap_reg_range(0x7a04, 0x7a07),
1223	regmap_reg_range(0x7b00, 0x7b01),
1224	regmap_reg_range(0x7b04, 0x7b04),
1225	regmap_reg_range(0x7c00, 0x7c05),
1226	regmap_reg_range(0x7c08, 0x7c1b),
1227	};
1228
1229	static const struct regmap_access_table ksz9477_register_set = {
1230	.yes_ranges = ksz9477_valid_regs,
1231	.n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1232	};
1233
1234	static const struct regmap_range ksz9896_valid_regs[] = {
1235	regmap_reg_range(0x0000, 0x0003),
1236	regmap_reg_range(0x0006, 0x0006),
1237	regmap_reg_range(0x0010, 0x001f),
1238	regmap_reg_range(0x0100, 0x0100),
1239	regmap_reg_range(0x0103, 0x0107),
1240	regmap_reg_range(0x010d, 0x010d),
1241	regmap_reg_range(0x0110, 0x0113),
1242	regmap_reg_range(0x0120, 0x0127),
1243	regmap_reg_range(0x0201, 0x0201),
1244	regmap_reg_range(0x0210, 0x0213),
1245	regmap_reg_range(0x0300, 0x0300),
1246	regmap_reg_range(0x0302, 0x030b),
1247	regmap_reg_range(0x0310, 0x031b),
1248	regmap_reg_range(0x0320, 0x032b),
1249	regmap_reg_range(0x0330, 0x0336),
1250	regmap_reg_range(0x0338, 0x033b),
1251	regmap_reg_range(0x033e, 0x033e),
1252	regmap_reg_range(0x0340, 0x035f),
1253	regmap_reg_range(0x0370, 0x0370),
1254	regmap_reg_range(0x0378, 0x0378),
1255	regmap_reg_range(0x037c, 0x037d),
1256	regmap_reg_range(0x0390, 0x0393),
1257	regmap_reg_range(0x0400, 0x040e),
1258	regmap_reg_range(0x0410, 0x042f),
1259
1260	/* port 1 */
1261	regmap_reg_range(0x1000, 0x1001),
1262	regmap_reg_range(0x1013, 0x1013),
1263	regmap_reg_range(0x1017, 0x1017),
1264	regmap_reg_range(0x101b, 0x101b),
1265	regmap_reg_range(0x101f, 0x1020),
1266	regmap_reg_range(0x1030, 0x1030),
1267	regmap_reg_range(0x1100, 0x1115),
1268	regmap_reg_range(0x111a, 0x111f),
1269	regmap_reg_range(0x1120, 0x112b),
1270	regmap_reg_range(0x1134, 0x113b),
1271	regmap_reg_range(0x113c, 0x113f),
1272	regmap_reg_range(0x1400, 0x1401),
1273	regmap_reg_range(0x1403, 0x1403),
1274	regmap_reg_range(0x1410, 0x1417),
1275	regmap_reg_range(0x1420, 0x1423),
1276	regmap_reg_range(0x1500, 0x1507),
1277	regmap_reg_range(0x1600, 0x1612),
1278	regmap_reg_range(0x1800, 0x180f),
1279	regmap_reg_range(0x1820, 0x1827),
1280	regmap_reg_range(0x1830, 0x1837),
1281	regmap_reg_range(0x1840, 0x184b),
1282	regmap_reg_range(0x1900, 0x1907),
1283	regmap_reg_range(0x1914, 0x1915),
1284	regmap_reg_range(0x1a00, 0x1a03),
1285	regmap_reg_range(0x1a04, 0x1a07),
1286	regmap_reg_range(0x1b00, 0x1b01),
1287	regmap_reg_range(0x1b04, 0x1b04),
1288
1289	/* port 2 */
1290	regmap_reg_range(0x2000, 0x2001),
1291	regmap_reg_range(0x2013, 0x2013),
1292	regmap_reg_range(0x2017, 0x2017),
1293	regmap_reg_range(0x201b, 0x201b),
1294	regmap_reg_range(0x201f, 0x2020),
1295	regmap_reg_range(0x2030, 0x2030),
1296	regmap_reg_range(0x2100, 0x2115),
1297	regmap_reg_range(0x211a, 0x211f),
1298	regmap_reg_range(0x2120, 0x212b),
1299	regmap_reg_range(0x2134, 0x213b),
1300	regmap_reg_range(0x213c, 0x213f),
1301	regmap_reg_range(0x2400, 0x2401),
1302	regmap_reg_range(0x2403, 0x2403),
1303	regmap_reg_range(0x2410, 0x2417),
1304	regmap_reg_range(0x2420, 0x2423),
1305	regmap_reg_range(0x2500, 0x2507),
1306	regmap_reg_range(0x2600, 0x2612),
1307	regmap_reg_range(0x2800, 0x280f),
1308	regmap_reg_range(0x2820, 0x2827),
1309	regmap_reg_range(0x2830, 0x2837),
1310	regmap_reg_range(0x2840, 0x284b),
1311	regmap_reg_range(0x2900, 0x2907),
1312	regmap_reg_range(0x2914, 0x2915),
1313	regmap_reg_range(0x2a00, 0x2a03),
1314	regmap_reg_range(0x2a04, 0x2a07),
1315	regmap_reg_range(0x2b00, 0x2b01),
1316	regmap_reg_range(0x2b04, 0x2b04),
1317
1318	/* port 3 */
1319	regmap_reg_range(0x3000, 0x3001),
1320	regmap_reg_range(0x3013, 0x3013),
1321	regmap_reg_range(0x3017, 0x3017),
1322	regmap_reg_range(0x301b, 0x301b),
1323	regmap_reg_range(0x301f, 0x3020),
1324	regmap_reg_range(0x3030, 0x3030),
1325	regmap_reg_range(0x3100, 0x3115),
1326	regmap_reg_range(0x311a, 0x311f),
1327	regmap_reg_range(0x3120, 0x312b),
1328	regmap_reg_range(0x3134, 0x313b),
1329	regmap_reg_range(0x313c, 0x313f),
1330	regmap_reg_range(0x3400, 0x3401),
1331	regmap_reg_range(0x3403, 0x3403),
1332	regmap_reg_range(0x3410, 0x3417),
1333	regmap_reg_range(0x3420, 0x3423),
1334	regmap_reg_range(0x3500, 0x3507),
1335	regmap_reg_range(0x3600, 0x3612),
1336	regmap_reg_range(0x3800, 0x380f),
1337	regmap_reg_range(0x3820, 0x3827),
1338	regmap_reg_range(0x3830, 0x3837),
1339	regmap_reg_range(0x3840, 0x384b),
1340	regmap_reg_range(0x3900, 0x3907),
1341	regmap_reg_range(0x3914, 0x3915),
1342	regmap_reg_range(0x3a00, 0x3a03),
1343	regmap_reg_range(0x3a04, 0x3a07),
1344	regmap_reg_range(0x3b00, 0x3b01),
1345	regmap_reg_range(0x3b04, 0x3b04),
1346
1347	/* port 4 */
1348	regmap_reg_range(0x4000, 0x4001),
1349	regmap_reg_range(0x4013, 0x4013),
1350	regmap_reg_range(0x4017, 0x4017),
1351	regmap_reg_range(0x401b, 0x401b),
1352	regmap_reg_range(0x401f, 0x4020),
1353	regmap_reg_range(0x4030, 0x4030),
1354	regmap_reg_range(0x4100, 0x4115),
1355	regmap_reg_range(0x411a, 0x411f),
1356	regmap_reg_range(0x4120, 0x412b),
1357	regmap_reg_range(0x4134, 0x413b),
1358	regmap_reg_range(0x413c, 0x413f),
1359	regmap_reg_range(0x4400, 0x4401),
1360	regmap_reg_range(0x4403, 0x4403),
1361	regmap_reg_range(0x4410, 0x4417),
1362	regmap_reg_range(0x4420, 0x4423),
1363	regmap_reg_range(0x4500, 0x4507),
1364	regmap_reg_range(0x4600, 0x4612),
1365	regmap_reg_range(0x4800, 0x480f),
1366	regmap_reg_range(0x4820, 0x4827),
1367	regmap_reg_range(0x4830, 0x4837),
1368	regmap_reg_range(0x4840, 0x484b),
1369	regmap_reg_range(0x4900, 0x4907),
1370	regmap_reg_range(0x4914, 0x4915),
1371	regmap_reg_range(0x4a00, 0x4a03),
1372	regmap_reg_range(0x4a04, 0x4a07),
1373	regmap_reg_range(0x4b00, 0x4b01),
1374	regmap_reg_range(0x4b04, 0x4b04),
1375
1376	/* port 5 */
1377	regmap_reg_range(0x5000, 0x5001),
1378	regmap_reg_range(0x5013, 0x5013),
1379	regmap_reg_range(0x5017, 0x5017),
1380	regmap_reg_range(0x501b, 0x501b),
1381	regmap_reg_range(0x501f, 0x5020),
1382	regmap_reg_range(0x5030, 0x5030),
1383	regmap_reg_range(0x5100, 0x5115),
1384	regmap_reg_range(0x511a, 0x511f),
1385	regmap_reg_range(0x5120, 0x512b),
1386	regmap_reg_range(0x5134, 0x513b),
1387	regmap_reg_range(0x513c, 0x513f),
1388	regmap_reg_range(0x5400, 0x5401),
1389	regmap_reg_range(0x5403, 0x5403),
1390	regmap_reg_range(0x5410, 0x5417),
1391	regmap_reg_range(0x5420, 0x5423),
1392	regmap_reg_range(0x5500, 0x5507),
1393	regmap_reg_range(0x5600, 0x5612),
1394	regmap_reg_range(0x5800, 0x580f),
1395	regmap_reg_range(0x5820, 0x5827),
1396	regmap_reg_range(0x5830, 0x5837),
1397	regmap_reg_range(0x5840, 0x584b),
1398	regmap_reg_range(0x5900, 0x5907),
1399	regmap_reg_range(0x5914, 0x5915),
1400	regmap_reg_range(0x5a00, 0x5a03),
1401	regmap_reg_range(0x5a04, 0x5a07),
1402	regmap_reg_range(0x5b00, 0x5b01),
1403	regmap_reg_range(0x5b04, 0x5b04),
1404
1405	/* port 6 */
1406	regmap_reg_range(0x6000, 0x6001),
1407	regmap_reg_range(0x6013, 0x6013),
1408	regmap_reg_range(0x6017, 0x6017),
1409	regmap_reg_range(0x601b, 0x601b),
1410	regmap_reg_range(0x601f, 0x6020),
1411	regmap_reg_range(0x6030, 0x6030),
1412	regmap_reg_range(0x6100, 0x6115),
1413	regmap_reg_range(0x611a, 0x611f),
1414	regmap_reg_range(0x6120, 0x612b),
1415	regmap_reg_range(0x6134, 0x613b),
1416	regmap_reg_range(0x613c, 0x613f),
1417	regmap_reg_range(0x6300, 0x6301),
1418	regmap_reg_range(0x6400, 0x6401),
1419	regmap_reg_range(0x6403, 0x6403),
1420	regmap_reg_range(0x6410, 0x6417),
1421	regmap_reg_range(0x6420, 0x6423),
1422	regmap_reg_range(0x6500, 0x6507),
1423	regmap_reg_range(0x6600, 0x6612),
1424	regmap_reg_range(0x6800, 0x680f),
1425	regmap_reg_range(0x6820, 0x6827),
1426	regmap_reg_range(0x6830, 0x6837),
1427	regmap_reg_range(0x6840, 0x684b),
1428	regmap_reg_range(0x6900, 0x6907),
1429	regmap_reg_range(0x6914, 0x6915),
1430	regmap_reg_range(0x6a00, 0x6a03),
1431	regmap_reg_range(0x6a04, 0x6a07),
1432	regmap_reg_range(0x6b00, 0x6b01),
1433	regmap_reg_range(0x6b04, 0x6b04),
1434	};
1435
1436	static const struct regmap_access_table ksz9896_register_set = {
1437	.yes_ranges = ksz9896_valid_regs,
1438	.n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1439	};
1440
1441	static const struct regmap_range ksz8873_valid_regs[] = {
1442	regmap_reg_range(0x00, 0x01),
1443	/* global control register */
1444	regmap_reg_range(0x02, 0x0f),
1445
1446	/* port registers */
1447	regmap_reg_range(0x10, 0x1d),
1448	regmap_reg_range(0x1e, 0x1f),
1449	regmap_reg_range(0x20, 0x2d),
1450	regmap_reg_range(0x2e, 0x2f),
1451	regmap_reg_range(0x30, 0x39),
1452	regmap_reg_range(0x3f, 0x3f),
1453
1454	/* advanced control registers */
1455	regmap_reg_range(0x43, 0x43),
1456	regmap_reg_range(0x60, 0x6f),
1457	regmap_reg_range(0x70, 0x75),
1458	regmap_reg_range(0x76, 0x78),
1459	regmap_reg_range(0x79, 0x7a),
1460	regmap_reg_range(0x7b, 0x83),
1461	regmap_reg_range(0x8e, 0x99),
1462	regmap_reg_range(0x9a, 0xa5),
1463	regmap_reg_range(0xa6, 0xa6),
1464	regmap_reg_range(0xa7, 0xaa),
1465	regmap_reg_range(0xab, 0xae),
1466	regmap_reg_range(0xaf, 0xba),
1467	regmap_reg_range(0xbb, 0xbc),
1468	regmap_reg_range(0xbd, 0xbd),
1469	regmap_reg_range(0xc0, 0xc0),
1470	regmap_reg_range(0xc2, 0xc2),
1471	regmap_reg_range(0xc3, 0xc3),
1472	regmap_reg_range(0xc4, 0xc4),
1473	regmap_reg_range(0xc6, 0xc6),
1474	};
1475
1476	static const struct regmap_access_table ksz8873_register_set = {
1477	.yes_ranges = ksz8873_valid_regs,
1478	.n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1479	};
1480
1481	const struct ksz_chip_data ksz_switch_chips[] = {
1482	[KSZ8463] = {
1483	.chip_id = KSZ8463_CHIP_ID,
1484	.dev_name = "KSZ8463",
1485	.num_vlans = 16,
1486	.num_alus = 0,
1487	.num_statics = 8,
1488	.cpu_ports = 0x4, /* can be configured as cpu port */
1489	.port_cnt = 3,
1490	.num_tx_queues = 4,
1491	.num_ipms = 4,
1492	.ops = &ksz8463_dev_ops,
1493	.phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1494	.mib_names = ksz88xx_mib_names,
1495	.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1496	.reg_mib_cnt = MIB_COUNTER_NUM,
1497	.regs = ksz8463_regs,
1498	.masks = ksz8463_masks,
1499	.shifts = ksz8463_shifts,
1500	.supports_mii = {false, false, true},
1501	.supports_rmii = {false, false, true},
1502	.internal_phy = {true, true, false},
1503	},
1504
1505	[KSZ8563] = {
1506	.chip_id = KSZ8563_CHIP_ID,
1507	.dev_name = "KSZ8563",
1508	.num_vlans = 4096,
1509	.num_alus = 4096,
1510	.num_statics = 16,
1511	.cpu_ports = 0x07, /* can be configured as cpu port */
1512	.port_cnt = 3, /* total port count */
1513	.port_nirqs = 3,
1514	.num_tx_queues = 4,
1515	.num_ipms = 8,
1516	.tc_cbs_supported = true,
1517	.ops = &ksz9477_dev_ops,
1518	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1519	.mib_names = ksz9477_mib_names,
1520	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1521	.reg_mib_cnt = MIB_COUNTER_NUM,
1522	.regs = ksz9477_regs,
1523	.masks = ksz9477_masks,
1524	.shifts = ksz9477_shifts,
1525	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1526	.xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1527	.supports_mii = {false, false, true},
1528	.supports_rmii = {false, false, true},
1529	.supports_rgmii = {false, false, true},
1530	.internal_phy = {true, true, false},
1531	.gbit_capable = {false, false, true},
1532	.ptp_capable = true,
1533	.wr_table = &ksz8563_register_set,
1534	.rd_table = &ksz8563_register_set,
1535	},
1536
1537	[KSZ8795] = {
1538	.chip_id = KSZ8795_CHIP_ID,
1539	.dev_name = "KSZ8795",
1540	.num_vlans = 4096,
1541	.num_alus = 0,
1542	.num_statics = 32,
1543	.cpu_ports = 0x10, /* can be configured as cpu port */
1544	.port_cnt = 5, /* total cpu and user ports */
1545	.num_tx_queues = 4,
1546	.num_ipms = 4,
1547	.ops = &ksz87xx_dev_ops,
1548	.phylink_mac_ops = &ksz8_phylink_mac_ops,
1549	.ksz87xx_eee_link_erratum = true,
1550	.mib_names = ksz9477_mib_names,
1551	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1552	.reg_mib_cnt = MIB_COUNTER_NUM,
1553	.regs = ksz8795_regs,
1554	.masks = ksz8795_masks,
1555	.shifts = ksz8795_shifts,
1556	.xmii_ctrl0 = ksz8795_xmii_ctrl0,
1557	.xmii_ctrl1 = ksz8795_xmii_ctrl1,
1558	.supports_mii = {false, false, false, false, true},
1559	.supports_rmii = {false, false, false, false, true},
1560	.supports_rgmii = {false, false, false, false, true},
1561	.internal_phy = {true, true, true, true, false},
1562	},
1563
1564	[KSZ8794] = {
1565	/* WARNING
1566	* =======
1567	* KSZ8794 is similar to KSZ8795, except the port map
1568	* contains a gap between external and CPU ports, the
1569	* port map is NOT continuous. The per-port register
1570	* map is shifted accordingly too, i.e. registers at
1571	* offset 0x40 are NOT used on KSZ8794 and they ARE
1572	* used on KSZ8795 for external port 3.
1573	* external cpu
1574	* KSZ8794 0,1,2 4
1575	* KSZ8795 0,1,2,3 4
1576	* KSZ8765 0,1,2,3 4
1577	* port_cnt is configured as 5, even though it is 4
1578	*/
1579	.chip_id = KSZ8794_CHIP_ID,
1580	.dev_name = "KSZ8794",
1581	.num_vlans = 4096,
1582	.num_alus = 0,
1583	.num_statics = 32,
1584	.cpu_ports = 0x10, /* can be configured as cpu port */
1585	.port_cnt = 5, /* total cpu and user ports */
1586	.num_tx_queues = 4,
1587	.num_ipms = 4,
1588	.ops = &ksz87xx_dev_ops,
1589	.phylink_mac_ops = &ksz8_phylink_mac_ops,
1590	.ksz87xx_eee_link_erratum = true,
1591	.mib_names = ksz9477_mib_names,
1592	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1593	.reg_mib_cnt = MIB_COUNTER_NUM,
1594	.regs = ksz8795_regs,
1595	.masks = ksz8795_masks,
1596	.shifts = ksz8795_shifts,
1597	.xmii_ctrl0 = ksz8795_xmii_ctrl0,
1598	.xmii_ctrl1 = ksz8795_xmii_ctrl1,
1599	.supports_mii = {false, false, false, false, true},
1600	.supports_rmii = {false, false, false, false, true},
1601	.supports_rgmii = {false, false, false, false, true},
1602	.internal_phy = {true, true, true, false, false},
1603	},
1604
1605	[KSZ8765] = {
1606	.chip_id = KSZ8765_CHIP_ID,
1607	.dev_name = "KSZ8765",
1608	.num_vlans = 4096,
1609	.num_alus = 0,
1610	.num_statics = 32,
1611	.cpu_ports = 0x10, /* can be configured as cpu port */
1612	.port_cnt = 5, /* total cpu and user ports */
1613	.num_tx_queues = 4,
1614	.num_ipms = 4,
1615	.ops = &ksz87xx_dev_ops,
1616	.phylink_mac_ops = &ksz8_phylink_mac_ops,
1617	.ksz87xx_eee_link_erratum = true,
1618	.mib_names = ksz9477_mib_names,
1619	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1620	.reg_mib_cnt = MIB_COUNTER_NUM,
1621	.regs = ksz8795_regs,
1622	.masks = ksz8795_masks,
1623	.shifts = ksz8795_shifts,
1624	.xmii_ctrl0 = ksz8795_xmii_ctrl0,
1625	.xmii_ctrl1 = ksz8795_xmii_ctrl1,
1626	.supports_mii = {false, false, false, false, true},
1627	.supports_rmii = {false, false, false, false, true},
1628	.supports_rgmii = {false, false, false, false, true},
1629	.internal_phy = {true, true, true, true, false},
1630	},
1631
1632	[KSZ88X3] = {
1633	.chip_id = KSZ88X3_CHIP_ID,
1634	.dev_name = "KSZ8863/KSZ8873",
1635	.num_vlans = 16,
1636	.num_alus = 0,
1637	.num_statics = 8,
1638	.cpu_ports = 0x4, /* can be configured as cpu port */
1639	.port_cnt = 3,
1640	.num_tx_queues = 4,
1641	.num_ipms = 4,
1642	.ops = &ksz88xx_dev_ops,
1643	.phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1644	.mib_names = ksz88xx_mib_names,
1645	.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1646	.reg_mib_cnt = MIB_COUNTER_NUM,
1647	.regs = ksz8863_regs,
1648	.masks = ksz8863_masks,
1649	.shifts = ksz8863_shifts,
1650	.supports_mii = {false, false, true},
1651	.supports_rmii = {false, false, true},
1652	.internal_phy = {true, true, false},
1653	.wr_table = &ksz8873_register_set,
1654	.rd_table = &ksz8873_register_set,
1655	},
1656
1657	[KSZ8864] = {
1658	/* WARNING
1659	* =======
1660	* KSZ8864 is similar to KSZ8895, except the first port
1661	* does not exist.
1662	* external cpu
1663	* KSZ8864 1,2,3 4
1664	* KSZ8895 0,1,2,3 4
1665	* port_cnt is configured as 5, even though it is 4
1666	*/
1667	.chip_id = KSZ8864_CHIP_ID,
1668	.dev_name = "KSZ8864",
1669	.num_vlans = 4096,
1670	.num_alus = 0,
1671	.num_statics = 32,
1672	.cpu_ports = 0x10, /* can be configured as cpu port */
1673	.port_cnt = 5, /* total cpu and user ports */
1674	.num_tx_queues = 4,
1675	.num_ipms = 4,
1676	.ops = &ksz88xx_dev_ops,
1677	.phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1678	.mib_names = ksz88xx_mib_names,
1679	.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1680	.reg_mib_cnt = MIB_COUNTER_NUM,
1681	.regs = ksz8895_regs,
1682	.masks = ksz8895_masks,
1683	.shifts = ksz8895_shifts,
1684	.supports_mii = {false, false, false, false, true},
1685	.supports_rmii = {false, false, false, false, true},
1686	.internal_phy = {false, true, true, true, false},
1687	},
1688
1689	[KSZ8895] = {
1690	.chip_id = KSZ8895_CHIP_ID,
1691	.dev_name = "KSZ8895",
1692	.num_vlans = 4096,
1693	.num_alus = 0,
1694	.num_statics = 32,
1695	.cpu_ports = 0x10, /* can be configured as cpu port */
1696	.port_cnt = 5, /* total cpu and user ports */
1697	.num_tx_queues = 4,
1698	.num_ipms = 4,
1699	.ops = &ksz88xx_dev_ops,
1700	.phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1701	.mib_names = ksz88xx_mib_names,
1702	.mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1703	.reg_mib_cnt = MIB_COUNTER_NUM,
1704	.regs = ksz8895_regs,
1705	.masks = ksz8895_masks,
1706	.shifts = ksz8895_shifts,
1707	.supports_mii = {false, false, false, false, true},
1708	.supports_rmii = {false, false, false, false, true},
1709	.internal_phy = {true, true, true, true, false},
1710	},
1711
1712	[KSZ9477] = {
1713	.chip_id = KSZ9477_CHIP_ID,
1714	.dev_name = "KSZ9477",
1715	.num_vlans = 4096,
1716	.num_alus = 4096,
1717	.num_statics = 16,
1718	.cpu_ports = 0x7F, /* can be configured as cpu port */
1719	.port_cnt = 7, /* total physical port count */
1720	.port_nirqs = 4,
1721	.num_tx_queues = 4,
1722	.num_ipms = 8,
1723	.tc_cbs_supported = true,
1724	.ops = &ksz9477_dev_ops,
1725	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1726	.phy_errata_9477 = true,
1727	.mib_names = ksz9477_mib_names,
1728	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1729	.reg_mib_cnt = MIB_COUNTER_NUM,
1730	.regs = ksz9477_regs,
1731	.masks = ksz9477_masks,
1732	.shifts = ksz9477_shifts,
1733	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1734	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1735	.supports_mii = {false, false, false, false,
1736	false, true, false},
1737	.supports_rmii = {false, false, false, false,
1738	false, true, false},
1739	.supports_rgmii = {false, false, false, false,
1740	false, true, false},
1741	.internal_phy = {true, true, true, true,
1742	true, false, false},
1743	.gbit_capable = {true, true, true, true, true, true, true},
1744	.ptp_capable = true,
1745	.sgmii_port = 7,
1746	.wr_table = &ksz9477_register_set,
1747	.rd_table = &ksz9477_register_set,
1748	},
1749
1750	[KSZ9896] = {
1751	.chip_id = KSZ9896_CHIP_ID,
1752	.dev_name = "KSZ9896",
1753	.num_vlans = 4096,
1754	.num_alus = 4096,
1755	.num_statics = 16,
1756	.cpu_ports = 0x3F, /* can be configured as cpu port */
1757	.port_cnt = 6, /* total physical port count */
1758	.port_nirqs = 2,
1759	.num_tx_queues = 4,
1760	.num_ipms = 8,
1761	.ops = &ksz9477_dev_ops,
1762	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1763	.phy_errata_9477 = true,
1764	.mib_names = ksz9477_mib_names,
1765	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1766	.reg_mib_cnt = MIB_COUNTER_NUM,
1767	.regs = ksz9477_regs,
1768	.masks = ksz9477_masks,
1769	.shifts = ksz9477_shifts,
1770	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1771	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1772	.supports_mii = {false, false, false, false,
1773	false, true},
1774	.supports_rmii = {false, false, false, false,
1775	false, true},
1776	.supports_rgmii = {false, false, false, false,
1777	false, true},
1778	.internal_phy = {true, true, true, true,
1779	true, false},
1780	.gbit_capable = {true, true, true, true, true, true},
1781	.wr_table = &ksz9896_register_set,
1782	.rd_table = &ksz9896_register_set,
1783	},
1784
1785	[KSZ9897] = {
1786	.chip_id = KSZ9897_CHIP_ID,
1787	.dev_name = "KSZ9897",
1788	.num_vlans = 4096,
1789	.num_alus = 4096,
1790	.num_statics = 16,
1791	.cpu_ports = 0x7F, /* can be configured as cpu port */
1792	.port_cnt = 7, /* total physical port count */
1793	.port_nirqs = 2,
1794	.num_tx_queues = 4,
1795	.num_ipms = 8,
1796	.ops = &ksz9477_dev_ops,
1797	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1798	.phy_errata_9477 = true,
1799	.mib_names = ksz9477_mib_names,
1800	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1801	.reg_mib_cnt = MIB_COUNTER_NUM,
1802	.regs = ksz9477_regs,
1803	.masks = ksz9477_masks,
1804	.shifts = ksz9477_shifts,
1805	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1806	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1807	.supports_mii = {false, false, false, false,
1808	false, true, true},
1809	.supports_rmii = {false, false, false, false,
1810	false, true, true},
1811	.supports_rgmii = {false, false, false, false,
1812	false, true, true},
1813	.internal_phy = {true, true, true, true,
1814	true, false, false},
1815	.gbit_capable = {true, true, true, true, true, true, true},
1816	},
1817
1818	[KSZ9893] = {
1819	.chip_id = KSZ9893_CHIP_ID,
1820	.dev_name = "KSZ9893",
1821	.num_vlans = 4096,
1822	.num_alus = 4096,
1823	.num_statics = 16,
1824	.cpu_ports = 0x07, /* can be configured as cpu port */
1825	.port_cnt = 3, /* total port count */
1826	.port_nirqs = 2,
1827	.num_tx_queues = 4,
1828	.num_ipms = 8,
1829	.ops = &ksz9477_dev_ops,
1830	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1831	.mib_names = ksz9477_mib_names,
1832	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1833	.reg_mib_cnt = MIB_COUNTER_NUM,
1834	.regs = ksz9477_regs,
1835	.masks = ksz9477_masks,
1836	.shifts = ksz9477_shifts,
1837	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1838	.xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1839	.supports_mii = {false, false, true},
1840	.supports_rmii = {false, false, true},
1841	.supports_rgmii = {false, false, true},
1842	.internal_phy = {true, true, false},
1843	.gbit_capable = {true, true, true},
1844	},
1845
1846	[KSZ9563] = {
1847	.chip_id = KSZ9563_CHIP_ID,
1848	.dev_name = "KSZ9563",
1849	.num_vlans = 4096,
1850	.num_alus = 4096,
1851	.num_statics = 16,
1852	.cpu_ports = 0x07, /* can be configured as cpu port */
1853	.port_cnt = 3, /* total port count */
1854	.port_nirqs = 3,
1855	.num_tx_queues = 4,
1856	.num_ipms = 8,
1857	.tc_cbs_supported = true,
1858	.ops = &ksz9477_dev_ops,
1859	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1860	.mib_names = ksz9477_mib_names,
1861	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1862	.reg_mib_cnt = MIB_COUNTER_NUM,
1863	.regs = ksz9477_regs,
1864	.masks = ksz9477_masks,
1865	.shifts = ksz9477_shifts,
1866	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1867	.xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1868	.supports_mii = {false, false, true},
1869	.supports_rmii = {false, false, true},
1870	.supports_rgmii = {false, false, true},
1871	.internal_phy = {true, true, false},
1872	.gbit_capable = {true, true, true},
1873	.ptp_capable = true,
1874	},
1875
1876	[KSZ8567] = {
1877	.chip_id = KSZ8567_CHIP_ID,
1878	.dev_name = "KSZ8567",
1879	.num_vlans = 4096,
1880	.num_alus = 4096,
1881	.num_statics = 16,
1882	.cpu_ports = 0x7F, /* can be configured as cpu port */
1883	.port_cnt = 7, /* total port count */
1884	.port_nirqs = 3,
1885	.num_tx_queues = 4,
1886	.num_ipms = 8,
1887	.tc_cbs_supported = true,
1888	.ops = &ksz9477_dev_ops,
1889	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
1890	.phy_errata_9477 = true,
1891	.mib_names = ksz9477_mib_names,
1892	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1893	.reg_mib_cnt = MIB_COUNTER_NUM,
1894	.regs = ksz9477_regs,
1895	.masks = ksz9477_masks,
1896	.shifts = ksz9477_shifts,
1897	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1898	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1899	.supports_mii = {false, false, false, false,
1900	false, true, true},
1901	.supports_rmii = {false, false, false, false,
1902	false, true, true},
1903	.supports_rgmii = {false, false, false, false,
1904	false, true, true},
1905	.internal_phy = {true, true, true, true,
1906	true, false, false},
1907	.gbit_capable = {false, false, false, false, false,
1908	true, true},
1909	.ptp_capable = true,
1910	},
1911
1912	[KSZ9567] = {
1913	.chip_id = KSZ9567_CHIP_ID,
1914	.dev_name = "KSZ9567",
1915	.num_vlans = 4096,
1916	.num_alus = 4096,
1917	.num_statics = 16,
1918	.cpu_ports = 0x7F, /* can be configured as cpu port */
1919	.port_cnt = 7, /* total physical port count */
1920	.port_nirqs = 3,
1921	.num_tx_queues = 4,
1922	.num_ipms = 8,
1923	.tc_cbs_supported = true,
1924	.ops = &ksz9477_dev_ops,
1925	.mib_names = ksz9477_mib_names,
1926	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1927	.reg_mib_cnt = MIB_COUNTER_NUM,
1928	.regs = ksz9477_regs,
1929	.masks = ksz9477_masks,
1930	.shifts = ksz9477_shifts,
1931	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1932	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1933	.supports_mii = {false, false, false, false,
1934	false, true, true},
1935	.supports_rmii = {false, false, false, false,
1936	false, true, true},
1937	.supports_rgmii = {false, false, false, false,
1938	false, true, true},
1939	.internal_phy = {true, true, true, true,
1940	true, false, false},
1941	.gbit_capable = {true, true, true, true, true, true, true},
1942	.ptp_capable = true,
1943	},
1944
1945	[LAN9370] = {
1946	.chip_id = LAN9370_CHIP_ID,
1947	.dev_name = "LAN9370",
1948	.num_vlans = 4096,
1949	.num_alus = 1024,
1950	.num_statics = 256,
1951	.cpu_ports = 0x10, /* can be configured as cpu port */
1952	.port_cnt = 5, /* total physical port count */
1953	.port_nirqs = 6,
1954	.num_tx_queues = 8,
1955	.num_ipms = 8,
1956	.tc_cbs_supported = true,
1957	.phy_side_mdio_supported = true,
1958	.ops = &lan937x_dev_ops,
1959	.phylink_mac_ops = &lan937x_phylink_mac_ops,
1960	.mib_names = ksz9477_mib_names,
1961	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1962	.reg_mib_cnt = MIB_COUNTER_NUM,
1963	.regs = ksz9477_regs,
1964	.masks = lan937x_masks,
1965	.shifts = lan937x_shifts,
1966	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1967	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1968	.supports_mii = {false, false, false, false, true},
1969	.supports_rmii = {false, false, false, false, true},
1970	.supports_rgmii = {false, false, false, false, true},
1971	.internal_phy = {true, true, true, true, false},
1972	.ptp_capable = true,
1973	},
1974
1975	[LAN9371] = {
1976	.chip_id = LAN9371_CHIP_ID,
1977	.dev_name = "LAN9371",
1978	.num_vlans = 4096,
1979	.num_alus = 1024,
1980	.num_statics = 256,
1981	.cpu_ports = 0x30, /* can be configured as cpu port */
1982	.port_cnt = 6, /* total physical port count */
1983	.port_nirqs = 6,
1984	.num_tx_queues = 8,
1985	.num_ipms = 8,
1986	.tc_cbs_supported = true,
1987	.phy_side_mdio_supported = true,
1988	.ops = &lan937x_dev_ops,
1989	.phylink_mac_ops = &lan937x_phylink_mac_ops,
1990	.mib_names = ksz9477_mib_names,
1991	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1992	.reg_mib_cnt = MIB_COUNTER_NUM,
1993	.regs = ksz9477_regs,
1994	.masks = lan937x_masks,
1995	.shifts = lan937x_shifts,
1996	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
1997	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
1998	.supports_mii = {false, false, false, false, true, true},
1999	.supports_rmii = {false, false, false, false, true, true},
2000	.supports_rgmii = {false, false, false, false, true, true},
2001	.internal_phy = {true, true, true, true, false, false},
2002	.ptp_capable = true,
2003	},
2004
2005	[LAN9372] = {
2006	.chip_id = LAN9372_CHIP_ID,
2007	.dev_name = "LAN9372",
2008	.num_vlans = 4096,
2009	.num_alus = 1024,
2010	.num_statics = 256,
2011	.cpu_ports = 0x30, /* can be configured as cpu port */
2012	.port_cnt = 8, /* total physical port count */
2013	.port_nirqs = 6,
2014	.num_tx_queues = 8,
2015	.num_ipms = 8,
2016	.tc_cbs_supported = true,
2017	.phy_side_mdio_supported = true,
2018	.ops = &lan937x_dev_ops,
2019	.phylink_mac_ops = &lan937x_phylink_mac_ops,
2020	.mib_names = ksz9477_mib_names,
2021	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2022	.reg_mib_cnt = MIB_COUNTER_NUM,
2023	.regs = ksz9477_regs,
2024	.masks = lan937x_masks,
2025	.shifts = lan937x_shifts,
2026	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
2027	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
2028	.supports_mii = {false, false, false, false,
2029	true, true, false, false},
2030	.supports_rmii = {false, false, false, false,
2031	true, true, false, false},
2032	.supports_rgmii = {false, false, false, false,
2033	true, true, false, false},
2034	.internal_phy = {true, true, true, true,
2035	false, false, true, true},
2036	.ptp_capable = true,
2037	},
2038
2039	[LAN9373] = {
2040	.chip_id = LAN9373_CHIP_ID,
2041	.dev_name = "LAN9373",
2042	.num_vlans = 4096,
2043	.num_alus = 1024,
2044	.num_statics = 256,
2045	.cpu_ports = 0x38, /* can be configured as cpu port */
2046	.port_cnt = 5, /* total physical port count */
2047	.port_nirqs = 6,
2048	.num_tx_queues = 8,
2049	.num_ipms = 8,
2050	.tc_cbs_supported = true,
2051	.phy_side_mdio_supported = true,
2052	.ops = &lan937x_dev_ops,
2053	.phylink_mac_ops = &lan937x_phylink_mac_ops,
2054	.mib_names = ksz9477_mib_names,
2055	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2056	.reg_mib_cnt = MIB_COUNTER_NUM,
2057	.regs = ksz9477_regs,
2058	.masks = lan937x_masks,
2059	.shifts = lan937x_shifts,
2060	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
2061	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
2062	.supports_mii = {false, false, false, false,
2063	true, true, false, false},
2064	.supports_rmii = {false, false, false, false,
2065	true, true, false, false},
2066	.supports_rgmii = {false, false, false, false,
2067	true, true, false, false},
2068	.internal_phy = {true, true, true, false,
2069	false, false, true, true},
2070	.ptp_capable = true,
2071	},
2072
2073	[LAN9374] = {
2074	.chip_id = LAN9374_CHIP_ID,
2075	.dev_name = "LAN9374",
2076	.num_vlans = 4096,
2077	.num_alus = 1024,
2078	.num_statics = 256,
2079	.cpu_ports = 0x30, /* can be configured as cpu port */
2080	.port_cnt = 8, /* total physical port count */
2081	.port_nirqs = 6,
2082	.num_tx_queues = 8,
2083	.num_ipms = 8,
2084	.tc_cbs_supported = true,
2085	.phy_side_mdio_supported = true,
2086	.ops = &lan937x_dev_ops,
2087	.phylink_mac_ops = &lan937x_phylink_mac_ops,
2088	.mib_names = ksz9477_mib_names,
2089	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2090	.reg_mib_cnt = MIB_COUNTER_NUM,
2091	.regs = ksz9477_regs,
2092	.masks = lan937x_masks,
2093	.shifts = lan937x_shifts,
2094	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
2095	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
2096	.supports_mii = {false, false, false, false,
2097	true, true, false, false},
2098	.supports_rmii = {false, false, false, false,
2099	true, true, false, false},
2100	.supports_rgmii = {false, false, false, false,
2101	true, true, false, false},
2102	.internal_phy = {true, true, true, true,
2103	false, false, true, true},
2104	.ptp_capable = true,
2105	},
2106
2107	[LAN9646] = {
2108	.chip_id = LAN9646_CHIP_ID,
2109	.dev_name = "LAN9646",
2110	.num_vlans = 4096,
2111	.num_alus = 4096,
2112	.num_statics = 16,
2113	.cpu_ports = 0x7F, /* can be configured as cpu port */
2114	.port_cnt = 7, /* total physical port count */
2115	.port_nirqs = 4,
2116	.num_tx_queues = 4,
2117	.num_ipms = 8,
2118	.ops = &ksz9477_dev_ops,
2119	.phylink_mac_ops = &ksz9477_phylink_mac_ops,
2120	.phy_errata_9477 = true,
2121	.mib_names = ksz9477_mib_names,
2122	.mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2123	.reg_mib_cnt = MIB_COUNTER_NUM,
2124	.regs = ksz9477_regs,
2125	.masks = ksz9477_masks,
2126	.shifts = ksz9477_shifts,
2127	.xmii_ctrl0 = ksz9477_xmii_ctrl0,
2128	.xmii_ctrl1 = ksz9477_xmii_ctrl1,
2129	.supports_mii = {false, false, false, false,
2130	false, true, true},
2131	.supports_rmii = {false, false, false, false,
2132	false, true, true},
2133	.supports_rgmii = {false, false, false, false,
2134	false, true, true},
2135	.internal_phy = {true, true, true, true,
2136	true, false, false},
2137	.gbit_capable = {true, true, true, true, true, true, true},
2138	.sgmii_port = 7,
2139	.wr_table = &ksz9477_register_set,
2140	.rd_table = &ksz9477_register_set,
2141	},
2142	};
2143	EXPORT_SYMBOL_GPL(ksz_switch_chips);
2144
2145	static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
2146	{
2147	int i;
2148
2149	for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
2150	const struct ksz_chip_data *chip = &ksz_switch_chips[i];
2151
2152	if (chip->chip_id == prod_num)
2153	return chip;
2154	}
2155
2156	return NULL;
2157	}
2158
2159	static int ksz_check_device_id(struct ksz_device *dev)
2160	{
2161	const struct ksz_chip_data *expected_chip_data;
2162	u32 expected_chip_id;
2163
2164	if (dev->pdata) {
2165	expected_chip_id = dev->pdata->chip_id;
2166	expected_chip_data = ksz_lookup_info(prod_num: expected_chip_id);
2167	if (WARN_ON(!expected_chip_data))
2168	return -ENODEV;
2169	} else {
2170	expected_chip_data = of_device_get_match_data(dev: dev->dev);
2171	expected_chip_id = expected_chip_data->chip_id;
2172	}
2173
2174	if (expected_chip_id != dev->chip_id) {
2175	dev_err(dev->dev,
2176	"Device tree specifies chip %s but found %s, please fix it!\n",
2177	expected_chip_data->dev_name, dev->info->dev_name);
2178	return -ENODEV;
2179	}
2180
2181	return 0;
2182	}
2183
2184	static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
2185	struct phylink_config *config)
2186	{
2187	struct ksz_device *dev = ds->priv;
2188
2189	if (dev->info->supports_mii[port])
2190	__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
2191
2192	if (dev->info->supports_rmii[port])
2193	__set_bit(PHY_INTERFACE_MODE_RMII,
2194	config->supported_interfaces);
2195
2196	if (dev->info->supports_rgmii[port])
2197	phy_interface_set_rgmii(intf: config->supported_interfaces);
2198
2199	if (dev->info->internal_phy[port]) {
2200	__set_bit(PHY_INTERFACE_MODE_INTERNAL,
2201	config->supported_interfaces);
2202	/* Compatibility for phylib's default interface type when the
2203	* phy-mode property is absent
2204	*/
2205	__set_bit(PHY_INTERFACE_MODE_GMII,
2206	config->supported_interfaces);
2207	}
2208
2209	if (dev->dev_ops->get_caps)
2210	dev->dev_ops->get_caps(dev, port, config);
2211
2212	if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) {
2213	memcpy(config->lpi_interfaces, config->supported_interfaces,
2214	sizeof(config->lpi_interfaces));
2215
2216	config->lpi_capabilities = MAC_100FD;
2217	if (dev->info->gbit_capable[port])
2218	config->lpi_capabilities |= MAC_1000FD;
2219
2220	/* EEE is fully operational */
2221	config->eee_enabled_default = true;
2222	}
2223	}
2224
2225	void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2226	{
2227	struct ethtool_pause_stats *pstats;
2228	struct rtnl_link_stats64 *stats;
2229	struct ksz_stats_raw *raw;
2230	struct ksz_port_mib *mib;
2231	int ret;
2232
2233	mib = &dev->ports[port].mib;
2234	stats = &mib->stats64;
2235	pstats = &mib->pause_stats;
2236	raw = (struct ksz_stats_raw *)mib->counters;
2237
2238	spin_lock(lock: &mib->stats64_lock);
2239
2240	stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2241	raw->rx_pause;
2242	stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2243	raw->tx_pause;
2244
2245	/* HW counters are counting bytes + FCS which is not acceptable
2246	* for rtnl_link_stats64 interface
2247	*/
2248	stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2249	stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2250
2251	stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2252	raw->rx_oversize;
2253
2254	stats->rx_crc_errors = raw->rx_crc_err;
2255	stats->rx_frame_errors = raw->rx_align_err;
2256	stats->rx_dropped = raw->rx_discards;
2257	stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2258	stats->rx_frame_errors + stats->rx_dropped;
2259
2260	stats->tx_window_errors = raw->tx_late_col;
2261	stats->tx_fifo_errors = raw->tx_discards;
2262	stats->tx_aborted_errors = raw->tx_exc_col;
2263	stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2264	stats->tx_aborted_errors;
2265
2266	stats->multicast = raw->rx_mcast;
2267	stats->collisions = raw->tx_total_col;
2268
2269	pstats->tx_pause_frames = raw->tx_pause;
2270	pstats->rx_pause_frames = raw->rx_pause;
2271
2272	spin_unlock(lock: &mib->stats64_lock);
2273
2274	if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) {
2275	ret = ksz9477_errata_monitor(dev, port, tx_late_col: raw->tx_late_col);
2276	if (ret)
2277	dev_err(dev->dev, "Failed to monitor transmission halt\n");
2278	}
2279	}
2280
2281	void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2282	{
2283	struct ethtool_pause_stats *pstats;
2284	struct rtnl_link_stats64 *stats;
2285	struct ksz88xx_stats_raw *raw;
2286	struct ksz_port_mib *mib;
2287
2288	mib = &dev->ports[port].mib;
2289	stats = &mib->stats64;
2290	pstats = &mib->pause_stats;
2291	raw = (struct ksz88xx_stats_raw *)mib->counters;
2292
2293	spin_lock(lock: &mib->stats64_lock);
2294
2295	stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2296	raw->rx_pause;
2297	stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2298	raw->tx_pause;
2299
2300	/* HW counters are counting bytes + FCS which is not acceptable
2301	* for rtnl_link_stats64 interface
2302	*/
2303	stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2304	stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2305
2306	stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2307	raw->rx_oversize;
2308
2309	stats->rx_crc_errors = raw->rx_crc_err;
2310	stats->rx_frame_errors = raw->rx_align_err;
2311	stats->rx_dropped = raw->rx_discards;
2312	stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2313	stats->rx_frame_errors + stats->rx_dropped;
2314
2315	stats->tx_window_errors = raw->tx_late_col;
2316	stats->tx_fifo_errors = raw->tx_discards;
2317	stats->tx_aborted_errors = raw->tx_exc_col;
2318	stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2319	stats->tx_aborted_errors;
2320
2321	stats->multicast = raw->rx_mcast;
2322	stats->collisions = raw->tx_total_col;
2323
2324	pstats->tx_pause_frames = raw->tx_pause;
2325	pstats->rx_pause_frames = raw->rx_pause;
2326
2327	spin_unlock(lock: &mib->stats64_lock);
2328	}
2329
2330	static void ksz_get_stats64(struct dsa_switch *ds, int port,
2331	struct rtnl_link_stats64 *s)
2332	{
2333	struct ksz_device *dev = ds->priv;
2334	struct ksz_port_mib *mib;
2335
2336	mib = &dev->ports[port].mib;
2337
2338	spin_lock(lock: &mib->stats64_lock);
2339	memcpy(s, &mib->stats64, sizeof(*s));
2340	spin_unlock(lock: &mib->stats64_lock);
2341	}
2342
2343	static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2344	struct ethtool_pause_stats *pause_stats)
2345	{
2346	struct ksz_device *dev = ds->priv;
2347	struct ksz_port_mib *mib;
2348
2349	mib = &dev->ports[port].mib;
2350
2351	spin_lock(lock: &mib->stats64_lock);
2352	memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2353	spin_unlock(lock: &mib->stats64_lock);
2354	}
2355
2356	static void ksz_get_strings(struct dsa_switch *ds, int port,
2357	u32 stringset, uint8_t *buf)
2358	{
2359	struct ksz_device *dev = ds->priv;
2360	int i;
2361
2362	if (stringset != ETH_SS_STATS)
2363	return;
2364
2365	for (i = 0; i < dev->info->mib_cnt; i++)
2366	ethtool_puts(data: &buf, str: dev->info->mib_names[i].string);
2367	}
2368
2369	/**
2370	* ksz_update_port_member - Adjust port forwarding rules based on STP state and
2371	* isolation settings.
2372	* @dev: A pointer to the struct ksz_device representing the device.
2373	* @port: The port number to adjust.
2374	*
2375	* This function dynamically adjusts the port membership configuration for a
2376	* specified port and other device ports, based on Spanning Tree Protocol (STP)
2377	* states and port isolation settings. Each port, including the CPU port, has a
2378	* membership register, represented as a bitfield, where each bit corresponds
2379	* to a port number. A set bit indicates permission to forward frames to that
2380	* port. This function iterates over all ports, updating the membership register
2381	* to reflect current forwarding permissions:
2382	*
2383	* 1. Forwards frames only to ports that are part of the same bridge group and
2384	* in the BR_STATE_FORWARDING state.
2385	* 2. Takes into account the isolation status of ports; ports in the
2386	* BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2387	* frames to each other, even if they are in the same bridge group.
2388	* 3. Ensures that the CPU port is included in the membership based on its
2389	* upstream port configuration, allowing for management and control traffic
2390	* to flow as required.
2391	*/
2392	static void ksz_update_port_member(struct ksz_device *dev, int port)
2393	{
2394	struct ksz_port *p = &dev->ports[port];
2395	struct dsa_switch *ds = dev->ds;
2396	u8 port_member = 0, cpu_port;
2397	const struct dsa_port *dp;
2398	int i, j;
2399
2400	if (!dsa_is_user_port(ds, p: port))
2401	return;
2402
2403	dp = dsa_to_port(ds, p: port);
2404	cpu_port = BIT(dsa_upstream_port(ds, port));
2405
2406	for (i = 0; i < ds->num_ports; i++) {
2407	const struct dsa_port *other_dp = dsa_to_port(ds, p: i);
2408	struct ksz_port *other_p = &dev->ports[i];
2409	u8 val = 0;
2410
2411	if (!dsa_is_user_port(ds, p: i))
2412	continue;
2413	if (port == i)
2414	continue;
2415	if (!dsa_port_bridge_same(a: dp, b: other_dp))
2416	continue;
2417	if (other_p->stp_state != BR_STATE_FORWARDING)
2418	continue;
2419
2420	/* At this point we know that "port" and "other" port [i] are in
2421	* the same bridge group and that "other" port [i] is in
2422	* forwarding stp state. If "port" is also in forwarding stp
2423	* state, we can allow forwarding from port [port] to port [i].
2424	* Except if both ports are isolated.
2425	*/
2426	if (p->stp_state == BR_STATE_FORWARDING &&
2427	!(p->isolated && other_p->isolated)) {
2428	val |= BIT(port);
2429	port_member |= BIT(i);
2430	}
2431
2432	/* Retain port [i]'s relationship to other ports than [port] */
2433	for (j = 0; j < ds->num_ports; j++) {
2434	const struct dsa_port *third_dp;
2435	struct ksz_port *third_p;
2436
2437	if (j == i)
2438	continue;
2439	if (j == port)
2440	continue;
2441	if (!dsa_is_user_port(ds, p: j))
2442	continue;
2443	third_p = &dev->ports[j];
2444	if (third_p->stp_state != BR_STATE_FORWARDING)
2445	continue;
2446
2447	third_dp = dsa_to_port(ds, p: j);
2448
2449	/* Now we updating relation of the "other" port [i] to
2450	* the "third" port [j]. We already know that "other"
2451	* port [i] is in forwarding stp state and that "third"
2452	* port [j] is in forwarding stp state too.
2453	* We need to check if "other" port [i] and "third" port
2454	* [j] are in the same bridge group and not isolated
2455	* before allowing forwarding from port [i] to port [j].
2456	*/
2457	if (dsa_port_bridge_same(a: other_dp, b: third_dp) &&
2458	!(other_p->isolated && third_p->isolated))
2459	val |= BIT(j);
2460	}
2461
2462	dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2463	}
2464
2465	/* HSR ports are setup once so need to use the assigned membership
2466	* when the port is enabled.
2467	*/
2468	if (!port_member && p->stp_state == BR_STATE_FORWARDING &&
2469	(dev->hsr_ports & BIT(port)))
2470	port_member = dev->hsr_ports;
2471	dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2472	}
2473
2474	static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2475	{
2476	struct ksz_device *dev = bus->priv;
2477	u16 val;
2478	int ret;
2479
2480	ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2481	if (ret < 0)
2482	return ret;
2483
2484	return val;
2485	}
2486
2487	static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2488	u16 val)
2489	{
2490	struct ksz_device *dev = bus->priv;
2491
2492	return dev->dev_ops->w_phy(dev, addr, regnum, val);
2493	}
2494
2495	/**
2496	* ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2497	* @bus: MDIO bus structure.
2498	* @addr: PHY address on the parent MDIO bus.
2499	* @regnum: Register number to read.
2500	*
2501	* This function provides a direct read operation on the parent MDIO bus for
2502	* accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2503	* to retrieve data from the PHY registers at the specified address and register
2504	* number.
2505	*
2506	* Return: Value of the PHY register, or a negative error code on failure.
2507	*/
2508	static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2509	{
2510	struct ksz_device *dev = bus->priv;
2511
2512	return mdiobus_read_nested(bus: dev->parent_mdio_bus, addr, regnum);
2513	}
2514
2515	/**
2516	* ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2517	* @bus: MDIO bus structure.
2518	* @addr: PHY address on the parent MDIO bus.
2519	* @regnum: Register number to write to.
2520	* @val: Value to write to the PHY register.
2521	*
2522	* This function provides a direct write operation on the parent MDIO bus for
2523	* accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2524	* to modify the PHY register values at the specified address.
2525	*
2526	* Return: 0 on success, or a negative error code on failure.
2527	*/
2528	static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2529	u16 val)
2530	{
2531	struct ksz_device *dev = bus->priv;
2532
2533	return mdiobus_write_nested(bus: dev->parent_mdio_bus, addr, regnum, val);
2534	}
2535
2536	/**
2537	* ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2538	* @dev: Pointer to device structure.
2539	* @addr: PHY address to map to a port.
2540	*
2541	* This function finds the corresponding switch port for a given PHY address by
2542	* iterating over all user ports on the device. It checks if a port's PHY
2543	* address in `phy_addr_map` matches the specified address and if the port
2544	* contains an internal PHY. If a match is found, the index of the port is
2545	* returned.
2546	*
2547	* Return: Port index on success, or -EINVAL if no matching port is found.
2548	*/
2549	static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2550	{
2551	struct dsa_switch *ds = dev->ds;
2552	struct dsa_port *dp;
2553
2554	dsa_switch_for_each_user_port(dp, ds) {
2555	if (dev->info->internal_phy[dp->index] &&
2556	dev->phy_addr_map[dp->index] == addr)
2557	return dp->index;
2558	}
2559
2560	return -EINVAL;
2561	}
2562
2563	/**
2564	* ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2565	* @dev: Pointer to the KSZ device structure.
2566	*
2567	* Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2568	* appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2569	* the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2570	*
2571	* Return: 0 on success, or a negative error code on failure.
2572	*/
2573	static int ksz_irq_phy_setup(struct ksz_device *dev)
2574	{
2575	struct dsa_switch *ds = dev->ds;
2576	int phy, port;
2577	int irq;
2578	int ret;
2579
2580	for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2581	if (BIT(phy) & ds->phys_mii_mask) {
2582	port = ksz_phy_addr_to_port(dev, addr: phy);
2583	if (port < 0) {
2584	ret = port;
2585	goto out;
2586	}
2587
2588	irq = irq_find_mapping(domain: dev->ports[port].pirq.domain,
2589	PORT_SRC_PHY_INT);
2590	if (!irq) {
2591	ret = -EINVAL;
2592	goto out;
2593	}
2594	ds->user_mii_bus->irq[phy] = irq;
2595	}
2596	}
2597	return 0;
2598	out:
2599	while (phy--)
2600	if (BIT(phy) & ds->phys_mii_mask)
2601	irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
2602
2603	return ret;
2604	}
2605
2606	/**
2607	* ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2608	* @dev: Pointer to the KSZ device structure.
2609	*
2610	* Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2611	* switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2612	*/
2613	static void ksz_irq_phy_free(struct ksz_device *dev)
2614	{
2615	struct dsa_switch *ds = dev->ds;
2616	int phy;
2617
2618	for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2619	if (BIT(phy) & ds->phys_mii_mask)
2620	irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]);
2621	}
2622
2623	/**
2624	* ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2625	* @dev: pointer to the KSZ device structure
2626	* @bus: pointer to the MII bus structure
2627	* @mdio_np: pointer to the MDIO node in the device tree
2628	*
2629	* This function parses and validates PHY configurations for each user port
2630	* defined in the device tree for a KSZ switch device. It verifies that the
2631	* `phy-handle` properties are correctly set and that the internal PHYs match
2632	* expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2633	* all validations pass. Logs error messages for any mismatches or missing data.
2634	*
2635	* Return: 0 on success, or a negative error code on failure.
2636	*/
2637	static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2638	struct device_node *mdio_np)
2639	{
2640	struct device_node *phy_node, *phy_parent_node;
2641	bool phys_are_valid = true;
2642	struct dsa_port *dp;
2643	u32 phy_addr;
2644	int ret;
2645
2646	dsa_switch_for_each_user_port(dp, dev->ds) {
2647	if (!dev->info->internal_phy[dp->index])
2648	continue;
2649
2650	phy_node = of_parse_phandle(np: dp->dn, phandle_name: "phy-handle", index: 0);
2651	if (!phy_node) {
2652	dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2653	dp->index);
2654	phys_are_valid = false;
2655	continue;
2656	}
2657
2658	phy_parent_node = of_get_parent(node: phy_node);
2659	if (!phy_parent_node) {
2660	dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2661	dp->index);
2662	phys_are_valid = false;
2663	} else if (phy_parent_node != mdio_np) {
2664	dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2665	dp->index, mdio_np, phy_parent_node);
2666	phys_are_valid = false;
2667	} else {
2668	ret = of_property_read_u32(np: phy_node, propname: "reg", out_value: &phy_addr);
2669	if (ret < 0) {
2670	dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2671	dp->index, ret);
2672	phys_are_valid = false;
2673	} else if (phy_addr != dev->phy_addr_map[dp->index]) {
2674	dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2675	dp->index, dev->phy_addr_map[dp->index],
2676	phy_addr);
2677	phys_are_valid = false;
2678	} else {
2679	bus->phy_mask |= BIT(phy_addr);
2680	}
2681	}
2682
2683	of_node_put(node: phy_node);
2684	of_node_put(node: phy_parent_node);
2685	}
2686
2687	if (!phys_are_valid)
2688	return -EINVAL;
2689
2690	return 0;
2691	}
2692
2693	/**
2694	* ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2695	* @dev: Pointer to the KSZ device structure.
2696	*
2697	* This function sets up and registers an MDIO bus for the KSZ switch device,
2698	* allowing access to its internal PHYs. If the device supports side MDIO,
2699	* the function will configure the external MDIO controller specified by the
2700	* "mdio-parent-bus" device tree property to directly manage internal PHYs.
2701	* Otherwise, SPI or I2C access is set up for PHY access.
2702	*
2703	* Return: 0 on success, or a negative error code on failure.
2704	*/
2705	static int ksz_mdio_register(struct ksz_device *dev)
2706	{
2707	struct device_node *parent_bus_node;
2708	struct mii_bus *parent_bus = NULL;
2709	struct dsa_switch *ds = dev->ds;
2710	struct device_node *mdio_np;
2711	struct mii_bus *bus;
2712	int ret, i;
2713
2714	mdio_np = of_get_child_by_name(node: dev->dev->of_node, name: "mdio");
2715	if (!mdio_np)
2716	return 0;
2717
2718	parent_bus_node = of_parse_phandle(np: mdio_np, phandle_name: "mdio-parent-bus", index: 0);
2719	if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2720	dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2721	ret = -EINVAL;
2722
2723	goto put_mdio_node;
2724	} else if (parent_bus_node) {
2725	parent_bus = of_mdio_find_bus(mdio_np: parent_bus_node);
2726	if (!parent_bus) {
2727	ret = -EPROBE_DEFER;
2728
2729	goto put_mdio_node;
2730	}
2731
2732	dev->parent_mdio_bus = parent_bus;
2733	}
2734
2735	bus = devm_mdiobus_alloc(dev: ds->dev);
2736	if (!bus) {
2737	ret = -ENOMEM;
2738	goto put_mdio_node;
2739	}
2740
2741	if (dev->dev_ops->mdio_bus_preinit) {
2742	ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2743	if (ret)
2744	goto put_mdio_node;
2745	}
2746
2747	if (dev->dev_ops->create_phy_addr_map) {
2748	ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2749	if (ret)
2750	goto put_mdio_node;
2751	} else {
2752	for (i = 0; i < dev->info->port_cnt; i++)
2753	dev->phy_addr_map[i] = i;
2754	}
2755
2756	bus->priv = dev;
2757	if (parent_bus) {
2758	bus->read = ksz_parent_mdio_read;
2759	bus->write = ksz_parent_mdio_write;
2760	bus->name = "KSZ side MDIO";
2761	snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "ksz-side-mdio-%d",
2762	ds->index);
2763	} else {
2764	bus->read = ksz_sw_mdio_read;
2765	bus->write = ksz_sw_mdio_write;
2766	bus->name = "ksz user smi";
2767	if (ds->dst->index != 0) {
2768	snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d-%d", ds->dst->index, ds->index);
2769	} else {
2770	snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d", ds->index);
2771	}
2772	}
2773
2774	ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2775	if (ret)
2776	goto put_mdio_node;
2777
2778	ds->phys_mii_mask = bus->phy_mask;
2779	bus->parent = ds->dev;
2780
2781	ds->user_mii_bus = bus;
2782
2783	if (dev->irq > 0) {
2784	ret = ksz_irq_phy_setup(dev);
2785	if (ret)
2786	goto put_mdio_node;
2787	}
2788
2789	ret = devm_of_mdiobus_register(dev: ds->dev, mdio: bus, np: mdio_np);
2790	if (ret) {
2791	dev_err(ds->dev, "unable to register MDIO bus %s\n",
2792	bus->id);
2793	if (dev->irq > 0)
2794	ksz_irq_phy_free(dev);
2795	}
2796
2797	put_mdio_node:
2798	of_node_put(node: mdio_np);
2799	of_node_put(node: parent_bus_node);
2800
2801	return ret;
2802	}
2803
2804	static void ksz_irq_mask(struct irq_data *d)
2805	{
2806	struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2807
2808	kirq->masked |= BIT(d->hwirq);
2809	}
2810
2811	static void ksz_irq_unmask(struct irq_data *d)
2812	{
2813	struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2814
2815	kirq->masked &= ~BIT(d->hwirq);
2816	}
2817
2818	static void ksz_irq_bus_lock(struct irq_data *d)
2819	{
2820	struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2821
2822	mutex_lock(&kirq->dev->lock_irq);
2823	}
2824
2825	static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2826	{
2827	struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2828	struct ksz_device *dev = kirq->dev;
2829	int ret;
2830
2831	ret = ksz_write8(dev, reg: kirq->reg_mask, value: kirq->masked);
2832	if (ret)
2833	dev_err(dev->dev, "failed to change IRQ mask\n");
2834
2835	mutex_unlock(lock: &dev->lock_irq);
2836	}
2837
2838	static const struct irq_chip ksz_irq_chip = {
2839	.name = "ksz-irq",
2840	.irq_mask = ksz_irq_mask,
2841	.irq_unmask = ksz_irq_unmask,
2842	.irq_bus_lock = ksz_irq_bus_lock,
2843	.irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2844	};
2845
2846	static int ksz_irq_domain_map(struct irq_domain *d,
2847	unsigned int irq, irq_hw_number_t hwirq)
2848	{
2849	irq_set_chip_data(irq, data: d->host_data);
2850	irq_set_chip_and_handler(irq, chip: &ksz_irq_chip, handle: handle_level_irq);
2851	irq_set_noprobe(irq);
2852
2853	return 0;
2854	}
2855
2856	static const struct irq_domain_ops ksz_irq_domain_ops = {
2857	.map = ksz_irq_domain_map,
2858	.xlate = irq_domain_xlate_twocell,
2859	};
2860
2861	static void ksz_irq_free(struct ksz_irq *kirq)
2862	{
2863	int irq, virq;
2864
2865	free_irq(kirq->irq_num, kirq);
2866
2867	for (irq = 0; irq < kirq->nirqs; irq++) {
2868	virq = irq_find_mapping(domain: kirq->domain, hwirq: irq);
2869	irq_dispose_mapping(virq);
2870	}
2871
2872	irq_domain_remove(domain: kirq->domain);
2873	}
2874
2875	static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2876	{
2877	struct ksz_irq *kirq = dev_id;
2878	unsigned int nhandled = 0;
2879	struct ksz_device *dev;
2880	unsigned int sub_irq;
2881	u8 data;
2882	int ret;
2883	u8 n;
2884
2885	dev = kirq->dev;
2886
2887	/* Read interrupt status register */
2888	ret = ksz_read8(dev, reg: kirq->reg_status, val: &data);
2889	if (ret)
2890	goto out;
2891
2892	for (n = 0; n < kirq->nirqs; ++n) {
2893	if (data & BIT(n)) {
2894	sub_irq = irq_find_mapping(domain: kirq->domain, hwirq: n);
2895	handle_nested_irq(irq: sub_irq);
2896	++nhandled;
2897	}
2898	}
2899	out:
2900	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2901	}
2902
2903	static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2904	{
2905	int ret, n;
2906
2907	kirq->dev = dev;
2908	kirq->masked = ~0;
2909
2910	kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), size: kirq->nirqs, first_irq: 0,
2911	ops: &ksz_irq_domain_ops, host_data: kirq);
2912	if (!kirq->domain)
2913	return -ENOMEM;
2914
2915	for (n = 0; n < kirq->nirqs; n++)
2916	irq_create_mapping(domain: kirq->domain, hwirq: n);
2917
2918	ret = request_threaded_irq(irq: kirq->irq_num, NULL, thread_fn: ksz_irq_thread_fn,
2919	IRQF_ONESHOT, name: kirq->name, dev: kirq);
2920	if (ret)
2921	goto out;
2922
2923	return 0;
2924
2925	out:
2926	ksz_irq_free(kirq);
2927
2928	return ret;
2929	}
2930
2931	static int ksz_girq_setup(struct ksz_device *dev)
2932	{
2933	struct ksz_irq *girq = &dev->girq;
2934
2935	girq->nirqs = dev->info->port_cnt;
2936	girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2937	girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2938	snprintf(buf: girq->name, size: sizeof(girq->name), fmt: "global_port_irq");
2939
2940	girq->irq_num = dev->irq;
2941
2942	return ksz_irq_common_setup(dev, kirq: girq);
2943	}
2944
2945	static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2946	{
2947	struct ksz_irq *pirq = &dev->ports[p].pirq;
2948
2949	pirq->nirqs = dev->info->port_nirqs;
2950	pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2951	pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2952	snprintf(buf: pirq->name, size: sizeof(pirq->name), fmt: "port_irq-%d", p);
2953
2954	pirq->irq_num = irq_find_mapping(domain: dev->girq.domain, hwirq: p);
2955	if (!pirq->irq_num)
2956	return -EINVAL;
2957
2958	return ksz_irq_common_setup(dev, kirq: pirq);
2959	}
2960
2961	static int ksz_parse_drive_strength(struct ksz_device *dev);
2962
2963	static int ksz_setup(struct dsa_switch *ds)
2964	{
2965	struct ksz_device *dev = ds->priv;
2966	u16 storm_mask, storm_rate;
2967	struct dsa_port *dp;
2968	struct ksz_port *p;
2969	const u16 *regs;
2970	int ret;
2971
2972	regs = dev->info->regs;
2973
2974	dev->vlan_cache = devm_kcalloc(dev: dev->dev, n: sizeof(struct vlan_table),
2975	size: dev->info->num_vlans, GFP_KERNEL);
2976	if (!dev->vlan_cache)
2977	return -ENOMEM;
2978
2979	ret = dev->dev_ops->reset(dev);
2980	if (ret) {
2981	dev_err(ds->dev, "failed to reset switch\n");
2982	return ret;
2983	}
2984
2985	ret = ksz_parse_drive_strength(dev);
2986	if (ret)
2987	return ret;
2988
2989	if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) {
2990	ret = dev->dev_ops->pcs_create(dev);
2991	if (ret)
2992	return ret;
2993	}
2994
2995	/* set broadcast storm protection 10% rate */
2996	storm_mask = BROADCAST_STORM_RATE;
2997	storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
2998	if (ksz_is_ksz8463(dev)) {
2999	storm_mask = swab16(storm_mask);
3000	storm_rate = swab16(storm_rate);
3001	}
3002	regmap_update_bits(map: ksz_regmap_16(dev), reg: regs[S_BROADCAST_CTRL],
3003	mask: storm_mask, val: storm_rate);
3004
3005	dev->dev_ops->config_cpu_port(ds);
3006
3007	dev->dev_ops->enable_stp_addr(dev);
3008
3009	ds->num_tx_queues = dev->info->num_tx_queues;
3010
3011	regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_MULTICAST_CTRL],
3012	MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
3013
3014	ksz_init_mib_timer(dev);
3015
3016	ds->configure_vlan_while_not_filtering = false;
3017	ds->dscp_prio_mapping_is_global = true;
3018
3019	if (dev->dev_ops->setup) {
3020	ret = dev->dev_ops->setup(ds);
3021	if (ret)
3022	return ret;
3023	}
3024
3025	/* Start with learning disabled on standalone user ports, and enabled
3026	* on the CPU port. In lack of other finer mechanisms, learning on the
3027	* CPU port will avoid flooding bridge local addresses on the network
3028	* in some cases.
3029	*/
3030	p = &dev->ports[dev->cpu_port];
3031	p->learning = true;
3032
3033	if (dev->irq > 0) {
3034	ret = ksz_girq_setup(dev);
3035	if (ret)
3036	return ret;
3037
3038	dsa_switch_for_each_user_port(dp, dev->ds) {
3039	ret = ksz_pirq_setup(dev, p: dp->index);
3040	if (ret)
3041	goto port_release;
3042
3043	if (dev->info->ptp_capable) {
3044	ret = ksz_ptp_irq_setup(ds, p: dp->index);
3045	if (ret)
3046	goto pirq_release;
3047	}
3048	}
3049	}
3050
3051	if (dev->info->ptp_capable) {
3052	ret = ksz_ptp_clock_register(ds);
3053	if (ret) {
3054	dev_err(dev->dev, "Failed to register PTP clock: %d\n",
3055	ret);
3056	goto port_release;
3057	}
3058	}
3059
3060	ret = ksz_mdio_register(dev);
3061	if (ret < 0) {
3062	dev_err(dev->dev, "failed to register the mdio");
3063	goto out_ptp_clock_unregister;
3064	}
3065
3066	ret = ksz_dcb_init(dev);
3067	if (ret)
3068	goto out_ptp_clock_unregister;
3069
3070	/* start switch */
3071	regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_START_CTRL],
3072	SW_START, SW_START);
3073
3074	return 0;
3075
3076	out_ptp_clock_unregister:
3077	if (dev->info->ptp_capable)
3078	ksz_ptp_clock_unregister(ds);
3079	port_release:
3080	if (dev->irq > 0) {
3081	dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) {
3082	if (dev->info->ptp_capable)
3083	ksz_ptp_irq_free(ds, p: dp->index);
3084	pirq_release:
3085	ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
3086	}
3087	ksz_irq_free(kirq: &dev->girq);
3088	}
3089
3090	return ret;
3091	}
3092
3093	static void ksz_teardown(struct dsa_switch *ds)
3094	{
3095	struct ksz_device *dev = ds->priv;
3096	struct dsa_port *dp;
3097
3098	if (dev->info->ptp_capable)
3099	ksz_ptp_clock_unregister(ds);
3100
3101	if (dev->irq > 0) {
3102	dsa_switch_for_each_user_port(dp, dev->ds) {
3103	if (dev->info->ptp_capable)
3104	ksz_ptp_irq_free(ds, p: dp->index);
3105
3106	ksz_irq_free(kirq: &dev->ports[dp->index].pirq);
3107	}
3108
3109	ksz_irq_free(kirq: &dev->girq);
3110	}
3111
3112	if (dev->dev_ops->teardown)
3113	dev->dev_ops->teardown(ds);
3114	}
3115
3116	static void port_r_cnt(struct ksz_device *dev, int port)
3117	{
3118	struct ksz_port_mib *mib = &dev->ports[port].mib;
3119	u64 *dropped;
3120
3121	/* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
3122	while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
3123	dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
3124	&mib->counters[mib->cnt_ptr]);
3125	++mib->cnt_ptr;
3126	}
3127
3128	/* last one in storage */
3129	dropped = &mib->counters[dev->info->mib_cnt];
3130
3131	/* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
3132	while (mib->cnt_ptr < dev->info->mib_cnt) {
3133	dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
3134	dropped, &mib->counters[mib->cnt_ptr]);
3135	++mib->cnt_ptr;
3136	}
3137	mib->cnt_ptr = 0;
3138	}
3139
3140	static void ksz_mib_read_work(struct work_struct *work)
3141	{
3142	struct ksz_device *dev = container_of(work, struct ksz_device,
3143	mib_read.work);
3144	struct ksz_port_mib *mib;
3145	struct ksz_port *p;
3146	int i;
3147
3148	for (i = 0; i < dev->info->port_cnt; i++) {
3149	if (dsa_is_unused_port(ds: dev->ds, p: i))
3150	continue;
3151
3152	p = &dev->ports[i];
3153	mib = &p->mib;
3154	mutex_lock(&mib->cnt_mutex);
3155
3156	/* Only read MIB counters when the port is told to do.
3157	* If not, read only dropped counters when link is not up.
3158	*/
3159	if (!p->read) {
3160	const struct dsa_port *dp = dsa_to_port(ds: dev->ds, p: i);
3161
3162	if (!netif_carrier_ok(dev: dp->user))
3163	mib->cnt_ptr = dev->info->reg_mib_cnt;
3164	}
3165	port_r_cnt(dev, port: i);
3166	p->read = false;
3167
3168	if (dev->dev_ops->r_mib_stat64)
3169	dev->dev_ops->r_mib_stat64(dev, i);
3170
3171	mutex_unlock(lock: &mib->cnt_mutex);
3172	}
3173
3174	schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval);
3175	}
3176
3177	void ksz_init_mib_timer(struct ksz_device *dev)
3178	{
3179	int i;
3180
3181	INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
3182
3183	for (i = 0; i < dev->info->port_cnt; i++) {
3184	struct ksz_port_mib *mib = &dev->ports[i].mib;
3185
3186	dev->dev_ops->port_init_cnt(dev, i);
3187
3188	mib->cnt_ptr = 0;
3189	memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
3190	}
3191	}
3192
3193	static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
3194	{
3195	struct ksz_device *dev = ds->priv;
3196	u16 val = 0xffff;
3197	int ret;
3198
3199	ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
3200	if (ret)
3201	return ret;
3202
3203	return val;
3204	}
3205
3206	static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
3207	{
3208	struct ksz_device *dev = ds->priv;
3209	int ret;
3210
3211	ret = dev->dev_ops->w_phy(dev, addr, reg, val);
3212	if (ret)
3213	return ret;
3214
3215	return 0;
3216	}
3217
3218	static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
3219	{
3220	struct ksz_device *dev = ds->priv;
3221
3222	switch (dev->chip_id) {
3223	case KSZ88X3_CHIP_ID:
3224	/* Silicon Errata Sheet (DS80000830A):
3225	* Port 1 does not work with LinkMD Cable-Testing.
3226	* Port 1 does not respond to received PAUSE control frames.
3227	*/
3228	if (!port)
3229	return MICREL_KSZ8_P1_ERRATA;
3230	break;
3231	}
3232
3233	return 0;
3234	}
3235
3236	static void ksz_phylink_mac_link_down(struct phylink_config *config,
3237	unsigned int mode,
3238	phy_interface_t interface)
3239	{
3240	struct dsa_port *dp = dsa_phylink_to_port(config);
3241	struct ksz_device *dev = dp->ds->priv;
3242
3243	/* Read all MIB counters when the link is going down. */
3244	dev->ports[dp->index].read = true;
3245	/* timer started */
3246	if (dev->mib_read_interval)
3247	schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
3248	}
3249
3250	static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3251	{
3252	struct ksz_device *dev = ds->priv;
3253
3254	if (sset != ETH_SS_STATS)
3255	return 0;
3256
3257	return dev->info->mib_cnt;
3258	}
3259
3260	static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3261	uint64_t *buf)
3262	{
3263	const struct dsa_port *dp = dsa_to_port(ds, p: port);
3264	struct ksz_device *dev = ds->priv;
3265	struct ksz_port_mib *mib;
3266
3267	mib = &dev->ports[port].mib;
3268	mutex_lock(&mib->cnt_mutex);
3269
3270	/* Only read dropped counters if no link. */
3271	if (!netif_carrier_ok(dev: dp->user))
3272	mib->cnt_ptr = dev->info->reg_mib_cnt;
3273	port_r_cnt(dev, port);
3274	memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3275	mutex_unlock(lock: &mib->cnt_mutex);
3276	}
3277
3278	static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3279	struct dsa_bridge bridge,
3280	bool *tx_fwd_offload,
3281	struct netlink_ext_ack *extack)
3282	{
3283	/* port_stp_state_set() will be called after to put the port in
3284	* appropriate state so there is no need to do anything.
3285	*/
3286
3287	return 0;
3288	}
3289
3290	static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3291	struct dsa_bridge bridge)
3292	{
3293	/* port_stp_state_set() will be called after to put the port in
3294	* forwarding state so there is no need to do anything.
3295	*/
3296	}
3297
3298	static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3299	{
3300	struct ksz_device *dev = ds->priv;
3301
3302	dev->dev_ops->flush_dyn_mac_table(dev, port);
3303	}
3304
3305	static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3306	{
3307	struct ksz_device *dev = ds->priv;
3308
3309	if (!dev->dev_ops->set_ageing_time)
3310	return -EOPNOTSUPP;
3311
3312	return dev->dev_ops->set_ageing_time(dev, msecs);
3313	}
3314
3315	static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3316	const unsigned char *addr, u16 vid,
3317	struct dsa_db db)
3318	{
3319	struct ksz_device *dev = ds->priv;
3320
3321	if (!dev->dev_ops->fdb_add)
3322	return -EOPNOTSUPP;
3323
3324	return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3325	}
3326
3327	static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3328	const unsigned char *addr,
3329	u16 vid, struct dsa_db db)
3330	{
3331	struct ksz_device *dev = ds->priv;
3332
3333	if (!dev->dev_ops->fdb_del)
3334	return -EOPNOTSUPP;
3335
3336	return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3337	}
3338
3339	static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3340	dsa_fdb_dump_cb_t *cb, void *data)
3341	{
3342	struct ksz_device *dev = ds->priv;
3343
3344	if (!dev->dev_ops->fdb_dump)
3345	return -EOPNOTSUPP;
3346
3347	return dev->dev_ops->fdb_dump(dev, port, cb, data);
3348	}
3349
3350	static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3351	const struct switchdev_obj_port_mdb *mdb,
3352	struct dsa_db db)
3353	{
3354	struct ksz_device *dev = ds->priv;
3355
3356	if (!dev->dev_ops->mdb_add)
3357	return -EOPNOTSUPP;
3358
3359	return dev->dev_ops->mdb_add(dev, port, mdb, db);
3360	}
3361
3362	static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3363	const struct switchdev_obj_port_mdb *mdb,
3364	struct dsa_db db)
3365	{
3366	struct ksz_device *dev = ds->priv;
3367
3368	if (!dev->dev_ops->mdb_del)
3369	return -EOPNOTSUPP;
3370
3371	return dev->dev_ops->mdb_del(dev, port, mdb, db);
3372	}
3373
3374	static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3375	int port)
3376	{
3377	u32 queue_map = 0;
3378	int ipm;
3379
3380	for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3381	int queue;
3382
3383	/* Traffic Type (TT) is corresponding to the Internal Priority
3384	* Map (IPM) in the switch. Traffic Class (TC) is
3385	* corresponding to the queue in the switch.
3386	*/
3387	queue = ieee8021q_tt_to_tc(tt: ipm, num_queues: dev->info->num_tx_queues);
3388	if (queue < 0)
3389	return queue;
3390
3391	queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3392	}
3393
3394	return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
3395	}
3396
3397	static int ksz_port_setup(struct dsa_switch *ds, int port)
3398	{
3399	struct ksz_device *dev = ds->priv;
3400	int ret;
3401
3402	if (!dsa_is_user_port(ds, p: port))
3403	return 0;
3404
3405	/* setup user port */
3406	dev->dev_ops->port_setup(dev, port, false);
3407
3408	if (!is_ksz8(dev)) {
3409	ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3410	if (ret)
3411	return ret;
3412	}
3413
3414	/* port_stp_state_set() will be called after to enable the port so
3415	* there is no need to do anything.
3416	*/
3417
3418	return ksz_dcb_init_port(dev, port);
3419	}
3420
3421	void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3422	{
3423	struct ksz_device *dev = ds->priv;
3424	struct ksz_port *p;
3425	const u16 *regs;
3426	u8 data;
3427
3428	regs = dev->info->regs;
3429
3430	ksz_pread8(dev, port, offset: regs[P_STP_CTRL], data: &data);
3431	data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3432
3433	p = &dev->ports[port];
3434
3435	switch (state) {
3436	case BR_STATE_DISABLED:
3437	data |= PORT_LEARN_DISABLE;
3438	break;
3439	case BR_STATE_LISTENING:
3440	data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3441	break;
3442	case BR_STATE_LEARNING:
3443	data |= PORT_RX_ENABLE;
3444	if (!p->learning)
3445	data |= PORT_LEARN_DISABLE;
3446	break;
3447	case BR_STATE_FORWARDING:
3448	data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3449	if (!p->learning)
3450	data |= PORT_LEARN_DISABLE;
3451	break;
3452	case BR_STATE_BLOCKING:
3453	data |= PORT_LEARN_DISABLE;
3454	break;
3455	default:
3456	dev_err(ds->dev, "invalid STP state: %d\n", state);
3457	return;
3458	}
3459
3460	ksz_pwrite8(dev, port, offset: regs[P_STP_CTRL], data);
3461
3462	p->stp_state = state;
3463
3464	ksz_update_port_member(dev, port);
3465	}
3466
3467	static void ksz_port_teardown(struct dsa_switch *ds, int port)
3468	{
3469	struct ksz_device *dev = ds->priv;
3470
3471	switch (dev->chip_id) {
3472	case KSZ8563_CHIP_ID:
3473	case KSZ8567_CHIP_ID:
3474	case KSZ9477_CHIP_ID:
3475	case KSZ9563_CHIP_ID:
3476	case KSZ9567_CHIP_ID:
3477	case KSZ9893_CHIP_ID:
3478	case KSZ9896_CHIP_ID:
3479	case KSZ9897_CHIP_ID:
3480	case LAN9646_CHIP_ID:
3481	if (dsa_is_user_port(ds, p: port))
3482	ksz9477_port_acl_free(dev, port);
3483	}
3484	}
3485
3486	static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3487	struct switchdev_brport_flags flags,
3488	struct netlink_ext_ack *extack)
3489	{
3490	if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3491	return -EINVAL;
3492
3493	return 0;
3494	}
3495
3496	static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3497	struct switchdev_brport_flags flags,
3498	struct netlink_ext_ack *extack)
3499	{
3500	struct ksz_device *dev = ds->priv;
3501	struct ksz_port *p = &dev->ports[port];
3502
3503	if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3504	if (flags.mask & BR_LEARNING)
3505	p->learning = !!(flags.val & BR_LEARNING);
3506
3507	if (flags.mask & BR_ISOLATED)
3508	p->isolated = !!(flags.val & BR_ISOLATED);
3509
3510	/* Make the change take effect immediately */
3511	ksz_port_stp_state_set(ds, port, state: p->stp_state);
3512	}
3513
3514	return 0;
3515	}
3516
3517	static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3518	int port,
3519	enum dsa_tag_protocol mp)
3520	{
3521	struct ksz_device *dev = ds->priv;
3522	enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3523
3524	if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3525	proto = DSA_TAG_PROTO_KSZ8795;
3526
3527	if (dev->chip_id == KSZ88X3_CHIP_ID ||
3528	dev->chip_id == KSZ8463_CHIP_ID ||
3529	dev->chip_id == KSZ8563_CHIP_ID ||
3530	dev->chip_id == KSZ9893_CHIP_ID ||
3531	dev->chip_id == KSZ9563_CHIP_ID)
3532	proto = DSA_TAG_PROTO_KSZ9893;
3533
3534	if (dev->chip_id == KSZ8567_CHIP_ID ||
3535	dev->chip_id == KSZ9477_CHIP_ID ||
3536	dev->chip_id == KSZ9896_CHIP_ID ||
3537	dev->chip_id == KSZ9897_CHIP_ID ||
3538	dev->chip_id == KSZ9567_CHIP_ID ||
3539	dev->chip_id == LAN9646_CHIP_ID)
3540	proto = DSA_TAG_PROTO_KSZ9477;
3541
3542	if (is_lan937x(dev))
3543	proto = DSA_TAG_PROTO_LAN937X;
3544
3545	return proto;
3546	}
3547
3548	static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3549	enum dsa_tag_protocol proto)
3550	{
3551	struct ksz_tagger_data *tagger_data;
3552
3553	switch (proto) {
3554	case DSA_TAG_PROTO_KSZ8795:
3555	return 0;
3556	case DSA_TAG_PROTO_KSZ9893:
3557	case DSA_TAG_PROTO_KSZ9477:
3558	case DSA_TAG_PROTO_LAN937X:
3559	tagger_data = ksz_tagger_data(ds);
3560	tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3561	return 0;
3562	default:
3563	return -EPROTONOSUPPORT;
3564	}
3565	}
3566
3567	static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3568	bool flag, struct netlink_ext_ack *extack)
3569	{
3570	struct ksz_device *dev = ds->priv;
3571
3572	if (!dev->dev_ops->vlan_filtering)
3573	return -EOPNOTSUPP;
3574
3575	return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3576	}
3577
3578	static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3579	const struct switchdev_obj_port_vlan *vlan,
3580	struct netlink_ext_ack *extack)
3581	{
3582	struct ksz_device *dev = ds->priv;
3583
3584	if (!dev->dev_ops->vlan_add)
3585	return -EOPNOTSUPP;
3586
3587	return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3588	}
3589
3590	static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3591	const struct switchdev_obj_port_vlan *vlan)
3592	{
3593	struct ksz_device *dev = ds->priv;
3594
3595	if (!dev->dev_ops->vlan_del)
3596	return -EOPNOTSUPP;
3597
3598	return dev->dev_ops->vlan_del(dev, port, vlan);
3599	}
3600
3601	static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3602	struct dsa_mall_mirror_tc_entry *mirror,
3603	bool ingress, struct netlink_ext_ack *extack)
3604	{
3605	struct ksz_device *dev = ds->priv;
3606
3607	if (!dev->dev_ops->mirror_add)
3608	return -EOPNOTSUPP;
3609
3610	return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3611	}
3612
3613	static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3614	struct dsa_mall_mirror_tc_entry *mirror)
3615	{
3616	struct ksz_device *dev = ds->priv;
3617
3618	if (dev->dev_ops->mirror_del)
3619	dev->dev_ops->mirror_del(dev, port, mirror);
3620	}
3621
3622	static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3623	{
3624	struct ksz_device *dev = ds->priv;
3625
3626	if (!dev->dev_ops->change_mtu)
3627	return -EOPNOTSUPP;
3628
3629	return dev->dev_ops->change_mtu(dev, port, mtu);
3630	}
3631
3632	static int ksz_max_mtu(struct dsa_switch *ds, int port)
3633	{
3634	struct ksz_device *dev = ds->priv;
3635
3636	switch (dev->chip_id) {
3637	case KSZ8795_CHIP_ID:
3638	case KSZ8794_CHIP_ID:
3639	case KSZ8765_CHIP_ID:
3640	return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3641	case KSZ8463_CHIP_ID:
3642	case KSZ88X3_CHIP_ID:
3643	case KSZ8864_CHIP_ID:
3644	case KSZ8895_CHIP_ID:
3645	return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3646	case KSZ8563_CHIP_ID:
3647	case KSZ8567_CHIP_ID:
3648	case KSZ9477_CHIP_ID:
3649	case KSZ9563_CHIP_ID:
3650	case KSZ9567_CHIP_ID:
3651	case KSZ9893_CHIP_ID:
3652	case KSZ9896_CHIP_ID:
3653	case KSZ9897_CHIP_ID:
3654	case LAN9370_CHIP_ID:
3655	case LAN9371_CHIP_ID:
3656	case LAN9372_CHIP_ID:
3657	case LAN9373_CHIP_ID:
3658	case LAN9374_CHIP_ID:
3659	case LAN9646_CHIP_ID:
3660	return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3661	}
3662
3663	return -EOPNOTSUPP;
3664	}
3665
3666	/**
3667	* ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a
3668	* port
3669	* @ds: Pointer to the DSA switch structure
3670	* @port: Port number to check
3671	*
3672	* This function also documents devices where EEE was initially advertised but
3673	* later withdrawn due to reliability issues, as described in official errata
3674	* documents. These devices are explicitly listed to record known limitations,
3675	* even if there is no technical necessity for runtime checks.
3676	*
3677	* Returns: true if the internal PHY on the given port supports fully
3678	* operational EEE, false otherwise.
3679	*/
3680	static bool ksz_support_eee(struct dsa_switch *ds, int port)
3681	{
3682	struct ksz_device *dev = ds->priv;
3683
3684	if (!dev->info->internal_phy[port])
3685	return false;
3686
3687	switch (dev->chip_id) {
3688	case KSZ8563_CHIP_ID:
3689	case KSZ9563_CHIP_ID:
3690	case KSZ9893_CHIP_ID:
3691	return true;
3692	case KSZ8567_CHIP_ID:
3693	/* KSZ8567R Errata DS80000752C Module 4 */
3694	case KSZ8765_CHIP_ID:
3695	case KSZ8794_CHIP_ID:
3696	case KSZ8795_CHIP_ID:
3697	/* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
3698	case KSZ9477_CHIP_ID:
3699	/* KSZ9477S Errata DS80000754A Module 4 */
3700	case KSZ9567_CHIP_ID:
3701	/* KSZ9567S Errata DS80000756A Module 4 */
3702	case KSZ9896_CHIP_ID:
3703	/* KSZ9896C Errata DS80000757A Module 3 */
3704	case KSZ9897_CHIP_ID:
3705	case LAN9646_CHIP_ID:
3706	/* KSZ9897R Errata DS80000758C Module 4 */
3707	/* Energy Efficient Ethernet (EEE) feature select must be
3708	* manually disabled
3709	* The EEE feature is enabled by default, but it is not fully
3710	* operational. It must be manually disabled through register
3711	* controls. If not disabled, the PHY ports can auto-negotiate
3712	* to enable EEE, and this feature can cause link drops when
3713	* linked to another device supporting EEE.
3714	*
3715	* The same item appears in the errata for all switches above.
3716	*/
3717	break;
3718	}
3719
3720	return false;
3721	}
3722
3723	static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3724	struct ethtool_keee *e)
3725	{
3726	struct ksz_device *dev = ds->priv;
3727
3728	if (!e->tx_lpi_enabled) {
3729	dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3730	return -EINVAL;
3731	}
3732
3733	if (e->tx_lpi_timer) {
3734	dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3735	return -EINVAL;
3736	}
3737
3738	return 0;
3739	}
3740
3741	static void ksz_set_xmii(struct ksz_device *dev, int port,
3742	phy_interface_t interface)
3743	{
3744	const u8 *bitval = dev->info->xmii_ctrl1;
3745	struct ksz_port *p = &dev->ports[port];
3746	const u16 *regs = dev->info->regs;
3747	u8 data8;
3748
3749	ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3750
3751	data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3752	P_RGMII_ID_EG_ENABLE);
3753
3754	switch (interface) {
3755	case PHY_INTERFACE_MODE_MII:
3756	data8 |= bitval[P_MII_SEL];
3757	break;
3758	case PHY_INTERFACE_MODE_RMII:
3759	data8 |= bitval[P_RMII_SEL];
3760	break;
3761	case PHY_INTERFACE_MODE_GMII:
3762	data8 |= bitval[P_GMII_SEL];
3763	break;
3764	case PHY_INTERFACE_MODE_RGMII:
3765	case PHY_INTERFACE_MODE_RGMII_ID:
3766	case PHY_INTERFACE_MODE_RGMII_TXID:
3767	case PHY_INTERFACE_MODE_RGMII_RXID:
3768	data8 |= bitval[P_RGMII_SEL];
3769	/* On KSZ9893, disable RGMII in-band status support */
3770	if (dev->chip_id == KSZ9893_CHIP_ID ||
3771	dev->chip_id == KSZ8563_CHIP_ID ||
3772	dev->chip_id == KSZ9563_CHIP_ID ||
3773	is_lan937x(dev))
3774	data8 &= ~P_MII_MAC_MODE;
3775	break;
3776	default:
3777	dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3778	phy_modes(interface), port);
3779	return;
3780	}
3781
3782	if (p->rgmii_tx_val)
3783	data8 |= P_RGMII_ID_EG_ENABLE;
3784
3785	if (p->rgmii_rx_val)
3786	data8 |= P_RGMII_ID_IG_ENABLE;
3787
3788	/* Write the updated value */
3789	ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
3790	}
3791
3792	phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3793	{
3794	const u8 *bitval = dev->info->xmii_ctrl1;
3795	const u16 *regs = dev->info->regs;
3796	phy_interface_t interface;
3797	u8 data8;
3798	u8 val;
3799
3800	ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3801
3802	val = FIELD_GET(P_MII_SEL_M, data8);
3803
3804	if (val == bitval[P_MII_SEL]) {
3805	if (gbit)
3806	interface = PHY_INTERFACE_MODE_GMII;
3807	else
3808	interface = PHY_INTERFACE_MODE_MII;
3809	} else if (val == bitval[P_RMII_SEL]) {
3810	interface = PHY_INTERFACE_MODE_RMII;
3811	} else {
3812	interface = PHY_INTERFACE_MODE_RGMII;
3813	if (data8 & P_RGMII_ID_EG_ENABLE)
3814	interface = PHY_INTERFACE_MODE_RGMII_TXID;
3815	if (data8 & P_RGMII_ID_IG_ENABLE) {
3816	interface = PHY_INTERFACE_MODE_RGMII_RXID;
3817	if (data8 & P_RGMII_ID_EG_ENABLE)
3818	interface = PHY_INTERFACE_MODE_RGMII_ID;
3819	}
3820	}
3821
3822	return interface;
3823	}
3824
3825	static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3826	unsigned int mode,
3827	const struct phylink_link_state *state)
3828	{
3829	struct dsa_port *dp = dsa_phylink_to_port(config);
3830	struct ksz_device *dev = dp->ds->priv;
3831
3832	dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3833	}
3834
3835	static void ksz_phylink_mac_config(struct phylink_config *config,
3836	unsigned int mode,
3837	const struct phylink_link_state *state)
3838	{
3839	struct dsa_port *dp = dsa_phylink_to_port(config);
3840	struct ksz_device *dev = dp->ds->priv;
3841	int port = dp->index;
3842
3843	/* Internal PHYs */
3844	if (dev->info->internal_phy[port])
3845	return;
3846
3847	/* No need to configure XMII control register when using SGMII. */
3848	if (ksz_is_sgmii_port(dev, port))
3849	return;
3850
3851	if (phylink_autoneg_inband(mode)) {
3852	dev_err(dev->dev, "In-band AN not supported!\n");
3853	return;
3854	}
3855
3856	ksz_set_xmii(dev, port, interface: state->interface);
3857
3858	if (dev->dev_ops->setup_rgmii_delay)
3859	dev->dev_ops->setup_rgmii_delay(dev, port);
3860	}
3861
3862	bool ksz_get_gbit(struct ksz_device *dev, int port)
3863	{
3864	const u8 *bitval = dev->info->xmii_ctrl1;
3865	const u16 *regs = dev->info->regs;
3866	bool gbit = false;
3867	u8 data8;
3868	bool val;
3869
3870	ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3871
3872	val = FIELD_GET(P_GMII_1GBIT_M, data8);
3873
3874	if (val == bitval[P_GMII_1GBIT])
3875	gbit = true;
3876
3877	return gbit;
3878	}
3879
3880	static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3881	{
3882	const u8 *bitval = dev->info->xmii_ctrl1;
3883	const u16 *regs = dev->info->regs;
3884	u8 data8;
3885
3886	ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8);
3887
3888	data8 &= ~P_GMII_1GBIT_M;
3889
3890	if (gbit)
3891	data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3892	else
3893	data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3894
3895	/* Write the updated value */
3896	ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8);
3897	}
3898
3899	static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3900	{
3901	const u8 *bitval = dev->info->xmii_ctrl0;
3902	const u16 *regs = dev->info->regs;
3903	u8 data8;
3904
3905	ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_0], data: &data8);
3906
3907	data8 &= ~P_MII_100MBIT_M;
3908
3909	if (speed == SPEED_100)
3910	data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3911	else
3912	data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3913
3914	/* Write the updated value */
3915	ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_0], data: data8);
3916	}
3917
3918	static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3919	{
3920	if (speed == SPEED_1000)
3921	ksz_set_gbit(dev, port, gbit: true);
3922	else
3923	ksz_set_gbit(dev, port, gbit: false);
3924
3925	if (speed == SPEED_100 || speed == SPEED_10)
3926	ksz_set_100_10mbit(dev, port, speed);
3927	}
3928
3929	static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3930	bool tx_pause, bool rx_pause)
3931	{
3932	const u8 *bitval = dev->info->xmii_ctrl0;
3933	const u32 *masks = dev->info->masks;
3934	const u16 *regs = dev->info->regs;
3935	u8 mask;
3936	u8 val;
3937
3938	mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3939	masks[P_MII_RX_FLOW_CTRL];
3940
3941	if (duplex == DUPLEX_FULL)
3942	val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3943	else
3944	val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3945
3946	if (tx_pause)
3947	val |= masks[P_MII_TX_FLOW_CTRL];
3948
3949	if (rx_pause)
3950	val |= masks[P_MII_RX_FLOW_CTRL];
3951
3952	ksz_prmw8(dev, port, offset: regs[P_XMII_CTRL_0], mask, val);
3953	}
3954
3955	static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3956	struct phy_device *phydev,
3957	unsigned int mode,
3958	phy_interface_t interface,
3959	int speed, int duplex, bool tx_pause,
3960	bool rx_pause)
3961	{
3962	struct dsa_port *dp = dsa_phylink_to_port(config);
3963	struct ksz_device *dev = dp->ds->priv;
3964	int port = dp->index;
3965	struct ksz_port *p;
3966
3967	p = &dev->ports[port];
3968
3969	/* Internal PHYs */
3970	if (dev->info->internal_phy[port])
3971	return;
3972
3973	p->phydev.speed = speed;
3974
3975	ksz_port_set_xmii_speed(dev, port, speed);
3976
3977	ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3978	}
3979
3980	static int ksz_switch_detect(struct ksz_device *dev)
3981	{
3982	u8 id1, id2, id4;
3983	u16 id16;
3984	u32 id32;
3985	int ret;
3986
3987	/* read chip id */
3988	ret = ksz_read16(dev, REG_CHIP_ID0, val: &id16);
3989	if (ret)
3990	return ret;
3991
3992	id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3993	id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3994
3995	switch (id1) {
3996	case KSZ84_FAMILY_ID:
3997	dev->chip_id = KSZ8463_CHIP_ID;
3998	break;
3999	case KSZ87_FAMILY_ID:
4000	if (id2 == KSZ87_CHIP_ID_95) {
4001	u8 val;
4002
4003	dev->chip_id = KSZ8795_CHIP_ID;
4004
4005	ksz_read8(dev, KSZ8_PORT_STATUS_0, val: &val);
4006	if (val & KSZ8_PORT_FIBER_MODE)
4007	dev->chip_id = KSZ8765_CHIP_ID;
4008	} else if (id2 == KSZ87_CHIP_ID_94) {
4009	dev->chip_id = KSZ8794_CHIP_ID;
4010	} else {
4011	return -ENODEV;
4012	}
4013	break;
4014	case KSZ88_FAMILY_ID:
4015	if (id2 == KSZ88_CHIP_ID_63)
4016	dev->chip_id = KSZ88X3_CHIP_ID;
4017	else
4018	return -ENODEV;
4019	break;
4020	case KSZ8895_FAMILY_ID:
4021	if (id2 == KSZ8895_CHIP_ID_95 ||
4022	id2 == KSZ8895_CHIP_ID_95R)
4023	dev->chip_id = KSZ8895_CHIP_ID;
4024	else
4025	return -ENODEV;
4026	ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, val: &id4);
4027	if (ret)
4028	return ret;
4029	if (id4 & SW_KSZ8864)
4030	dev->chip_id = KSZ8864_CHIP_ID;
4031	break;
4032	default:
4033	ret = ksz_read32(dev, REG_CHIP_ID0, val: &id32);
4034	if (ret)
4035	return ret;
4036
4037	dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
4038	id32 &= ~0xFF;
4039
4040	switch (id32) {
4041	case KSZ9477_CHIP_ID:
4042	case KSZ9896_CHIP_ID:
4043	case KSZ9897_CHIP_ID:
4044	case KSZ9567_CHIP_ID:
4045	case KSZ8567_CHIP_ID:
4046	case LAN9370_CHIP_ID:
4047	case LAN9371_CHIP_ID:
4048	case LAN9372_CHIP_ID:
4049	case LAN9373_CHIP_ID:
4050	case LAN9374_CHIP_ID:
4051
4052	/* LAN9646 does not have its own chip id. */
4053	if (dev->chip_id != LAN9646_CHIP_ID)
4054	dev->chip_id = id32;
4055	break;
4056	case KSZ9893_CHIP_ID:
4057	ret = ksz_read8(dev, REG_CHIP_ID4,
4058	val: &id4);
4059	if (ret)
4060	return ret;
4061
4062	if (id4 == SKU_ID_KSZ8563)
4063	dev->chip_id = KSZ8563_CHIP_ID;
4064	else if (id4 == SKU_ID_KSZ9563)
4065	dev->chip_id = KSZ9563_CHIP_ID;
4066	else
4067	dev->chip_id = KSZ9893_CHIP_ID;
4068
4069	break;
4070	default:
4071	dev_err(dev->dev,
4072	"unsupported switch detected %x)\n", id32);
4073	return -ENODEV;
4074	}
4075	}
4076	return 0;
4077	}
4078
4079	static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
4080	struct flow_cls_offload *cls, bool ingress)
4081	{
4082	struct ksz_device *dev = ds->priv;
4083
4084	switch (dev->chip_id) {
4085	case KSZ8563_CHIP_ID:
4086	case KSZ8567_CHIP_ID:
4087	case KSZ9477_CHIP_ID:
4088	case KSZ9563_CHIP_ID:
4089	case KSZ9567_CHIP_ID:
4090	case KSZ9893_CHIP_ID:
4091	case KSZ9896_CHIP_ID:
4092	case KSZ9897_CHIP_ID:
4093	case LAN9646_CHIP_ID:
4094	return ksz9477_cls_flower_add(ds, port, cls, ingress);
4095	}
4096
4097	return -EOPNOTSUPP;
4098	}
4099
4100	static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
4101	struct flow_cls_offload *cls, bool ingress)
4102	{
4103	struct ksz_device *dev = ds->priv;
4104
4105	switch (dev->chip_id) {
4106	case KSZ8563_CHIP_ID:
4107	case KSZ8567_CHIP_ID:
4108	case KSZ9477_CHIP_ID:
4109	case KSZ9563_CHIP_ID:
4110	case KSZ9567_CHIP_ID:
4111	case KSZ9893_CHIP_ID:
4112	case KSZ9896_CHIP_ID:
4113	case KSZ9897_CHIP_ID:
4114	case LAN9646_CHIP_ID:
4115	return ksz9477_cls_flower_del(ds, port, cls, ingress);
4116	}
4117
4118	return -EOPNOTSUPP;
4119	}
4120
4121	/* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
4122	* is converted to Hex-decimal using the successive multiplication method. On
4123	* every step, integer part is taken and decimal part is carry forwarded.
4124	*/
4125	static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
4126	{
4127	u32 cinc = 0;
4128	u32 txrate;
4129	u32 rate;
4130	u8 temp;
4131	u8 i;
4132
4133	txrate = idle_slope - send_slope;
4134
4135	if (!txrate)
4136	return -EINVAL;
4137
4138	rate = idle_slope;
4139
4140	/* 24 bit register */
4141	for (i = 0; i < 6; i++) {
4142	rate = rate * 16;
4143
4144	temp = rate / txrate;
4145
4146	rate %= txrate;
4147
4148	cinc = ((cinc << 4) | temp);
4149	}
4150
4151	*bw = cinc;
4152
4153	return 0;
4154	}
4155
4156	static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
4157	u8 shaper)
4158	{
4159	return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
4160	FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
4161	FIELD_PREP(MTI_SHAPING_M, shaper));
4162	}
4163
4164	static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
4165	struct tc_cbs_qopt_offload *qopt)
4166	{
4167	struct ksz_device *dev = ds->priv;
4168	int ret;
4169	u32 bw;
4170
4171	if (!dev->info->tc_cbs_supported)
4172	return -EOPNOTSUPP;
4173
4174	if (qopt->queue > dev->info->num_tx_queues)
4175	return -EINVAL;
4176
4177	/* Queue Selection */
4178	ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: qopt->queue);
4179	if (ret)
4180	return ret;
4181
4182	if (!qopt->enable)
4183	return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4184	MTI_SHAPING_OFF);
4185
4186	/* High Credit */
4187	ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
4188	data: qopt->hicredit);
4189	if (ret)
4190	return ret;
4191
4192	/* Low Credit */
4193	ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
4194	data: qopt->locredit);
4195	if (ret)
4196	return ret;
4197
4198	/* Credit Increment Register */
4199	ret = cinc_cal(idle_slope: qopt->idleslope, send_slope: qopt->sendslope, bw: &bw);
4200	if (ret)
4201	return ret;
4202
4203	if (dev->dev_ops->tc_cbs_set_cinc) {
4204	ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
4205	if (ret)
4206	return ret;
4207	}
4208
4209	return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4210	MTI_SHAPING_SRP);
4211	}
4212
4213	static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
4214	{
4215	int queue, ret;
4216
4217	/* Configuration will not take effect until the last Port Queue X
4218	* Egress Limit Control Register is written.
4219	*/
4220	for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4221	ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
4222	KSZ9477_OUT_RATE_NO_LIMIT);
4223	if (ret)
4224	return ret;
4225	}
4226
4227	return 0;
4228	}
4229
4230	static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
4231	int band)
4232	{
4233	/* Compared to queues, bands prioritize packets differently. In strict
4234	* priority mode, the lowest priority is assigned to Queue 0 while the
4235	* highest priority is given to Band 0.
4236	*/
4237	return p->bands - 1 - band;
4238	}
4239
4240	static u8 ksz8463_tc_ctrl(int port, int queue)
4241	{
4242	u8 reg;
4243
4244	reg = 0xC8 + port * 4;
4245	reg += ((3 - queue) / 2) * 2;
4246	reg++;
4247	reg -= (queue & 1);
4248	return reg;
4249	}
4250
4251	/**
4252	* ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection)
4253	* for a port on KSZ88x3 switch
4254	* @dev: Pointer to the KSZ switch device structure
4255	* @port: Port number to configure
4256	* @p: Pointer to offload replace parameters describing ETS bands and mapping
4257	*
4258	* The KSZ88x3 supports two scheduling modes: Strict Priority and
4259	* Weighted Fair Queuing (WFQ). Both modes have fixed behavior:
4260	* - No configurable queue-to-priority mapping
4261	* - No weight adjustment in WFQ mode
4262	*
4263	* This function configures the switch to use strict priority mode by
4264	* clearing the WFQ enable bit for all queues associated with ETS bands.
4265	* If strict priority is not explicitly requested, the switch will default
4266	* to WFQ mode.
4267	*
4268	* Return: 0 on success, or a negative error code on failure
4269	*/
4270	static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port,
4271	struct tc_ets_qopt_offload_replace_params *p)
4272	{
4273	int ret, band;
4274
4275	/* Only strict priority mode is supported for now.
4276	* WFQ is implicitly enabled when strict mode is disabled.
4277	*/
4278	for (band = 0; band < p->bands; band++) {
4279	int queue = ksz_ets_band_to_queue(p, band);
4280	u8 reg;
4281
4282	/* Calculate TXQ Split Control register address for this
4283	* port/queue
4284	*/
4285	reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4286	if (ksz_is_ksz8463(dev))
4287	reg = ksz8463_tc_ctrl(port, queue);
4288
4289	/* Clear WFQ enable bit to select strict priority scheduling */
4290	ret = ksz_rmw8(dev, offset: reg, KSZ8873_TXQ_WFQ_ENABLE, val: 0);
4291	if (ret)
4292	return ret;
4293	}
4294
4295	return 0;
4296	}
4297
4298	/**
4299	* ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config
4300	* for a port on KSZ88x3 switch
4301	* @dev: Pointer to the KSZ switch device structure
4302	* @port: Port number to reset
4303	*
4304	* The KSZ88x3 supports only fixed scheduling modes: Strict Priority or
4305	* Weighted Fair Queuing (WFQ), with no reconfiguration of weights or
4306	* queue mapping. This function resets the port’s scheduling mode to
4307	* the default, which is WFQ, by enabling the WFQ bit for all queues.
4308	*
4309	* Return: 0 on success, or a negative error code on failure
4310	*/
4311	static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port)
4312	{
4313	int ret, queue;
4314
4315	/* Iterate over all transmit queues for this port */
4316	for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4317	u8 reg;
4318
4319	/* Calculate TXQ Split Control register address for this
4320	* port/queue
4321	*/
4322	reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4323	if (ksz_is_ksz8463(dev))
4324	reg = ksz8463_tc_ctrl(port, queue);
4325
4326	/* Set WFQ enable bit to revert back to default scheduling
4327	* mode
4328	*/
4329	ret = ksz_rmw8(dev, offset: reg, KSZ8873_TXQ_WFQ_ENABLE,
4330	KSZ8873_TXQ_WFQ_ENABLE);
4331	if (ret)
4332	return ret;
4333	}
4334
4335	return 0;
4336	}
4337
4338	static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4339	{
4340	int ret;
4341
4342	ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
4343	if (ret)
4344	return ret;
4345
4346	return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4347	MTI_SHAPING_OFF);
4348	}
4349
4350	static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4351	int weight)
4352	{
4353	int ret;
4354
4355	ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue);
4356	if (ret)
4357	return ret;
4358
4359	ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4360	MTI_SHAPING_OFF);
4361	if (ret)
4362	return ret;
4363
4364	return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, data: weight);
4365	}
4366
4367	static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4368	struct tc_ets_qopt_offload_replace_params *p)
4369	{
4370	int ret, band, tc_prio;
4371	u32 queue_map = 0;
4372
4373	/* In order to ensure proper prioritization, it is necessary to set the
4374	* rate limit for the related queue to zero. Otherwise strict priority
4375	* or WRR mode will not work. This is a hardware limitation.
4376	*/
4377	ret = ksz_disable_egress_rate_limit(dev, port);
4378	if (ret)
4379	return ret;
4380
4381	/* Configure queue scheduling mode for all bands. Currently only strict
4382	* prio mode is supported.
4383	*/
4384	for (band = 0; band < p->bands; band++) {
4385	int queue = ksz_ets_band_to_queue(p, band);
4386
4387	ret = ksz_queue_set_strict(dev, port, queue);
4388	if (ret)
4389	return ret;
4390	}
4391
4392	/* Configure the mapping between traffic classes and queues. Note:
4393	* priomap variable support 16 traffic classes, but the chip can handle
4394	* only 8 classes.
4395	*/
4396	for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4397	int queue;
4398
4399	if (tc_prio >= dev->info->num_ipms)
4400	break;
4401
4402	queue = ksz_ets_band_to_queue(p, band: p->priomap[tc_prio]);
4403	queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4404	}
4405
4406	return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map);
4407	}
4408
4409	static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4410	{
4411	int ret, queue;
4412
4413	/* To restore the default chip configuration, set all queues to use the
4414	* WRR scheduler with a weight of 1.
4415	*/
4416	for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4417	ret = ksz_queue_set_wrr(dev, port, queue,
4418	KSZ9477_DEFAULT_WRR_WEIGHT);
4419
4420	if (ret)
4421	return ret;
4422	}
4423
4424	/* Revert the queue mapping for TC-priority to its default setting on
4425	* the chip.
4426	*/
4427	return ksz9477_set_default_prio_queue_mapping(dev, port);
4428	}
4429
4430	static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4431	struct tc_ets_qopt_offload_replace_params *p)
4432	{
4433	int band;
4434
4435	/* Since it is not feasible to share one port among multiple qdisc,
4436	* the user must configure all available queues appropriately.
4437	*/
4438	if (p->bands != dev->info->num_tx_queues) {
4439	dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4440	dev->info->num_tx_queues);
4441	return -EOPNOTSUPP;
4442	}
4443
4444	for (band = 0; band < p->bands; ++band) {
4445	/* The KSZ switches utilize a weighted round robin configuration
4446	* where a certain number of packets can be transmitted from a
4447	* queue before the next queue is serviced. For more information
4448	* on this, refer to section 5.2.8.4 of the KSZ8565R
4449	* documentation on the Port Transmit Queue Control 1 Register.
4450	* However, the current ETS Qdisc implementation (as of February
4451	* 2023) assigns a weight to each queue based on the number of
4452	* bytes or extrapolated bandwidth in percentages. Since this
4453	* differs from the KSZ switches' method and we don't want to
4454	* fake support by converting bytes to packets, it is better to
4455	* return an error instead.
4456	*/
4457	if (p->quanta[band]) {
4458	dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4459	return -EOPNOTSUPP;
4460	}
4461	}
4462
4463	return 0;
4464	}
4465
4466	static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4467	struct tc_ets_qopt_offload *qopt)
4468	{
4469	struct ksz_device *dev = ds->priv;
4470	int ret;
4471
4472	if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)))
4473	return -EOPNOTSUPP;
4474
4475	if (qopt->parent != TC_H_ROOT) {
4476	dev_err(dev->dev, "Parent should be \"root\"\n");
4477	return -EOPNOTSUPP;
4478	}
4479
4480	switch (qopt->command) {
4481	case TC_ETS_REPLACE:
4482	ret = ksz_tc_ets_validate(dev, port, p: &qopt->replace_params);
4483	if (ret)
4484	return ret;
4485
4486	if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4487	return ksz88x3_tc_ets_add(dev, port,
4488	p: &qopt->replace_params);
4489	else
4490	return ksz_tc_ets_add(dev, port, p: &qopt->replace_params);
4491	case TC_ETS_DESTROY:
4492	if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4493	return ksz88x3_tc_ets_del(dev, port);
4494	else
4495	return ksz_tc_ets_del(dev, port);
4496	case TC_ETS_STATS:
4497	case TC_ETS_GRAFT:
4498	return -EOPNOTSUPP;
4499	}
4500
4501	return -EOPNOTSUPP;
4502	}
4503
4504	static int ksz_setup_tc(struct dsa_switch *ds, int port,
4505	enum tc_setup_type type, void *type_data)
4506	{
4507	switch (type) {
4508	case TC_SETUP_QDISC_CBS:
4509	return ksz_setup_tc_cbs(ds, port, qopt: type_data);
4510	case TC_SETUP_QDISC_ETS:
4511	return ksz_tc_setup_qdisc_ets(ds, port, qopt: type_data);
4512	default:
4513	return -EOPNOTSUPP;
4514	}
4515	}
4516
4517	/**
4518	* ksz_handle_wake_reason - Handle wake reason on a specified port.
4519	* @dev: The device structure.
4520	* @port: The port number.
4521	*
4522	* This function reads the PME (Power Management Event) status register of a
4523	* specified port to determine the wake reason. If there is no wake event, it
4524	* returns early. Otherwise, it logs the wake reason which could be due to a
4525	* "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4526	* is then cleared to acknowledge the handling of the wake event.
4527	*
4528	* Return: 0 on success, or an error code on failure.
4529	*/
4530	int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4531	{
4532	const struct ksz_dev_ops *ops = dev->dev_ops;
4533	const u16 *regs = dev->info->regs;
4534	u8 pme_status;
4535	int ret;
4536
4537	ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4538	&pme_status);
4539	if (ret)
4540	return ret;
4541
4542	if (!pme_status)
4543	return 0;
4544
4545	dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4546	pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4547	pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4548	pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4549
4550	return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4551	pme_status);
4552	}
4553
4554	/**
4555	* ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4556	* @ds: The dsa_switch structure.
4557	* @port: The port number.
4558	* @wol: Pointer to ethtool Wake-on-LAN settings structure.
4559	*
4560	* This function checks the device PME wakeup_source flag and chip_id.
4561	* If enabled and supported, it sets the supported and active WoL
4562	* flags.
4563	*/
4564	static void ksz_get_wol(struct dsa_switch *ds, int port,
4565	struct ethtool_wolinfo *wol)
4566	{
4567	struct ksz_device *dev = ds->priv;
4568	const u16 *regs = dev->info->regs;
4569	u8 pme_ctrl;
4570	int ret;
4571
4572	if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4573	return;
4574
4575	if (!dev->wakeup_source)
4576	return;
4577
4578	wol->supported = WAKE_PHY;
4579
4580	/* Check if the current MAC address on this port can be set
4581	* as global for WAKE_MAGIC support. The result may vary
4582	* dynamically based on other ports configurations.
4583	*/
4584	if (ksz_is_port_mac_global_usable(ds: dev->ds, port))
4585	wol->supported |= WAKE_MAGIC;
4586
4587	ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4588	&pme_ctrl);
4589	if (ret)
4590	return;
4591
4592	if (pme_ctrl & PME_WOL_MAGICPKT)
4593	wol->wolopts |= WAKE_MAGIC;
4594	if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4595	wol->wolopts |= WAKE_PHY;
4596	}
4597
4598	/**
4599	* ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4600	* @ds: The dsa_switch structure.
4601	* @port: The port number.
4602	* @wol: Pointer to ethtool Wake-on-LAN settings structure.
4603	*
4604	* This function configures Wake-on-LAN (WoL) settings for a specified
4605	* port. It validates the provided WoL options, checks if PME is
4606	* enabled and supported, clears any previous wake reasons, and sets
4607	* the Magic Packet flag in the port's PME control register if
4608	* specified.
4609	*
4610	* Return: 0 on success, or other error codes on failure.
4611	*/
4612	static int ksz_set_wol(struct dsa_switch *ds, int port,
4613	struct ethtool_wolinfo *wol)
4614	{
4615	u8 pme_ctrl = 0, pme_ctrl_old = 0;
4616	struct ksz_device *dev = ds->priv;
4617	const u16 *regs = dev->info->regs;
4618	bool magic_switched_off;
4619	bool magic_switched_on;
4620	int ret;
4621
4622	if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4623	return -EINVAL;
4624
4625	if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4626	return -EOPNOTSUPP;
4627
4628	if (!dev->wakeup_source)
4629	return -EOPNOTSUPP;
4630
4631	ret = ksz_handle_wake_reason(dev, port);
4632	if (ret)
4633	return ret;
4634
4635	if (wol->wolopts & WAKE_MAGIC)
4636	pme_ctrl |= PME_WOL_MAGICPKT;
4637	if (wol->wolopts & WAKE_PHY)
4638	pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4639
4640	ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4641	&pme_ctrl_old);
4642	if (ret)
4643	return ret;
4644
4645	if (pme_ctrl_old == pme_ctrl)
4646	return 0;
4647
4648	magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4649	!(pme_ctrl & PME_WOL_MAGICPKT);
4650	magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4651	(pme_ctrl & PME_WOL_MAGICPKT);
4652
4653	/* To keep reference count of MAC address, we should do this
4654	* operation only on change of WOL settings.
4655	*/
4656	if (magic_switched_on) {
4657	ret = ksz_switch_macaddr_get(ds: dev->ds, port, NULL);
4658	if (ret)
4659	return ret;
4660	} else if (magic_switched_off) {
4661	ksz_switch_macaddr_put(ds: dev->ds);
4662	}
4663
4664	ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4665	pme_ctrl);
4666	if (ret) {
4667	if (magic_switched_on)
4668	ksz_switch_macaddr_put(ds: dev->ds);
4669	return ret;
4670	}
4671
4672	return 0;
4673	}
4674
4675	/**
4676	* ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4677	* considering Wake-on-LAN (WoL) settings.
4678	* @dev: The switch device structure.
4679	* @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4680	* enabled on any port.
4681	*
4682	* This function prepares the switch device for a safe shutdown while taking
4683	* into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4684	* the wol_enabled flag accordingly to reflect whether WoL is active on any
4685	* port.
4686	*/
4687	static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4688	{
4689	const struct ksz_dev_ops *ops = dev->dev_ops;
4690	const u16 *regs = dev->info->regs;
4691	u8 pme_pin_en = PME_ENABLE;
4692	struct dsa_port *dp;
4693	int ret;
4694
4695	*wol_enabled = false;
4696
4697	if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4698	return;
4699
4700	if (!dev->wakeup_source)
4701	return;
4702
4703	dsa_switch_for_each_user_port(dp, dev->ds) {
4704	u8 pme_ctrl = 0;
4705
4706	ret = ops->pme_pread8(dev, dp->index,
4707	regs[REG_PORT_PME_CTRL], &pme_ctrl);
4708	if (!ret && pme_ctrl)
4709	*wol_enabled = true;
4710
4711	/* make sure there are no pending wake events which would
4712	* prevent the device from going to sleep/shutdown.
4713	*/
4714	ksz_handle_wake_reason(dev, port: dp->index);
4715	}
4716
4717	/* Now we are save to enable PME pin. */
4718	if (*wol_enabled) {
4719	if (dev->pme_active_high)
4720	pme_pin_en |= PME_POLARITY;
4721	ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4722	if (ksz_is_ksz87xx(dev))
4723	ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4724	}
4725	}
4726
4727	static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4728	const unsigned char *addr)
4729	{
4730	struct dsa_port *dp = dsa_to_port(ds, p: port);
4731	struct ethtool_wolinfo wol;
4732
4733	if (dp->hsr_dev) {
4734	dev_err(ds->dev,
4735	"Cannot change MAC address on port %d with active HSR offload\n",
4736	port);
4737	return -EBUSY;
4738	}
4739
4740	/* Need to initialize variable as the code to fill in settings may
4741	* not be executed.
4742	*/
4743	wol.wolopts = 0;
4744
4745	ksz_get_wol(ds, port: dp->index, wol: &wol);
4746	if (wol.wolopts & WAKE_MAGIC) {
4747	dev_err(ds->dev,
4748	"Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4749	port);
4750	return -EBUSY;
4751	}
4752
4753	return 0;
4754	}
4755
4756	/**
4757	* ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4758	* can be used as a global address.
4759	* @ds: Pointer to the DSA switch structure.
4760	* @port: The port number on which the MAC address is to be checked.
4761	*
4762	* This function examines the MAC address set on the specified port and
4763	* determines if it can be used as a global address for the switch.
4764	*
4765	* Return: true if the port's MAC address can be used as a global address, false
4766	* otherwise.
4767	*/
4768	bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4769	{
4770	struct net_device *user = dsa_to_port(ds, p: port)->user;
4771	const unsigned char *addr = user->dev_addr;
4772	struct ksz_switch_macaddr *switch_macaddr;
4773	struct ksz_device *dev = ds->priv;
4774
4775	ASSERT_RTNL();
4776
4777	switch_macaddr = dev->switch_macaddr;
4778	if (switch_macaddr && !ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr))
4779	return false;
4780
4781	return true;
4782	}
4783
4784	/**
4785	* ksz_switch_macaddr_get - Program the switch's MAC address register.
4786	* @ds: DSA switch instance.
4787	* @port: Port number.
4788	* @extack: Netlink extended acknowledgment.
4789	*
4790	* This function programs the switch's MAC address register with the MAC address
4791	* of the requesting user port. This single address is used by the switch for
4792	* multiple features like HSR self-address filtering and WoL. Other user ports
4793	* can share ownership of this address as long as their MAC address is the same.
4794	* The MAC addresses of user ports must not change while they have ownership of
4795	* the switch MAC address.
4796	*
4797	* Return: 0 on success, or other error codes on failure.
4798	*/
4799	int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4800	struct netlink_ext_ack *extack)
4801	{
4802	struct net_device *user = dsa_to_port(ds, p: port)->user;
4803	const unsigned char *addr = user->dev_addr;
4804	struct ksz_switch_macaddr *switch_macaddr;
4805	struct ksz_device *dev = ds->priv;
4806	const u16 *regs = dev->info->regs;
4807	int i, ret;
4808
4809	/* Make sure concurrent MAC address changes are blocked */
4810	ASSERT_RTNL();
4811
4812	switch_macaddr = dev->switch_macaddr;
4813	if (switch_macaddr) {
4814	if (!ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr)) {
4815	NL_SET_ERR_MSG_FMT_MOD(extack,
4816	"Switch already configured for MAC address %pM",
4817	switch_macaddr->addr);
4818	return -EBUSY;
4819	}
4820
4821	refcount_inc(r: &switch_macaddr->refcount);
4822	return 0;
4823	}
4824
4825	switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4826	if (!switch_macaddr)
4827	return -ENOMEM;
4828
4829	ether_addr_copy(dst: switch_macaddr->addr, src: addr);
4830	refcount_set(r: &switch_macaddr->refcount, n: 1);
4831	dev->switch_macaddr = switch_macaddr;
4832
4833	/* Program the switch MAC address to hardware */
4834	for (i = 0; i < ETH_ALEN; i++) {
4835	if (ksz_is_ksz8463(dev)) {
4836	u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1];
4837
4838	ret = ksz_write16(dev, reg: regs[REG_SW_MAC_ADDR] + i,
4839	value: addr16);
4840	i++;
4841	} else {
4842	ret = ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i,
4843	value: addr[i]);
4844	}
4845	if (ret)
4846	goto macaddr_drop;
4847	}
4848
4849	return 0;
4850
4851	macaddr_drop:
4852	dev->switch_macaddr = NULL;
4853	refcount_set(r: &switch_macaddr->refcount, n: 0);
4854	kfree(objp: switch_macaddr);
4855
4856	return ret;
4857	}
4858
4859	void ksz_switch_macaddr_put(struct dsa_switch *ds)
4860	{
4861	struct ksz_switch_macaddr *switch_macaddr;
4862	struct ksz_device *dev = ds->priv;
4863	const u16 *regs = dev->info->regs;
4864	int i;
4865
4866	/* Make sure concurrent MAC address changes are blocked */
4867	ASSERT_RTNL();
4868
4869	switch_macaddr = dev->switch_macaddr;
4870	if (!refcount_dec_and_test(r: &switch_macaddr->refcount))
4871	return;
4872
4873	for (i = 0; i < ETH_ALEN; i++)
4874	ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: 0);
4875
4876	dev->switch_macaddr = NULL;
4877	kfree(objp: switch_macaddr);
4878	}
4879
4880	static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4881	struct netlink_ext_ack *extack)
4882	{
4883	struct ksz_device *dev = ds->priv;
4884	enum hsr_version ver;
4885	int ret;
4886
4887	ret = hsr_get_version(dev: hsr, ver: &ver);
4888	if (ret)
4889	return ret;
4890
4891	if (dev->chip_id != KSZ9477_CHIP_ID) {
4892	NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4893	return -EOPNOTSUPP;
4894	}
4895
4896	/* KSZ9477 can support HW offloading of only 1 HSR device */
4897	if (dev->hsr_dev && hsr != dev->hsr_dev) {
4898	NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4899	return -EOPNOTSUPP;
4900	}
4901
4902	/* KSZ9477 only supports HSR v0 and v1 */
4903	if (!(ver == HSR_V0 || ver == HSR_V1)) {
4904	NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4905	return -EOPNOTSUPP;
4906	}
4907
4908	/* KSZ9477 can only perform HSR offloading for up to two ports */
4909	if (hweight8(dev->hsr_ports) >= 2) {
4910	NL_SET_ERR_MSG_MOD(extack,
4911	"Cannot offload more than two ports - using software HSR");
4912	return -EOPNOTSUPP;
4913	}
4914
4915	/* Self MAC address filtering, to avoid frames traversing
4916	* the HSR ring more than once.
4917	*/
4918	ret = ksz_switch_macaddr_get(ds, port, extack);
4919	if (ret)
4920	return ret;
4921
4922	ksz9477_hsr_join(ds, port, hsr);
4923	dev->hsr_dev = hsr;
4924	dev->hsr_ports |= BIT(port);
4925
4926	return 0;
4927	}
4928
4929	static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4930	struct net_device *hsr)
4931	{
4932	struct ksz_device *dev = ds->priv;
4933
4934	WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4935
4936	ksz9477_hsr_leave(ds, port, hsr);
4937	dev->hsr_ports &= ~BIT(port);
4938	if (!dev->hsr_ports)
4939	dev->hsr_dev = NULL;
4940
4941	ksz_switch_macaddr_put(ds);
4942
4943	return 0;
4944	}
4945
4946	static int ksz_suspend(struct dsa_switch *ds)
4947	{
4948	struct ksz_device *dev = ds->priv;
4949
4950	cancel_delayed_work_sync(dwork: &dev->mib_read);
4951	return 0;
4952	}
4953
4954	static int ksz_resume(struct dsa_switch *ds)
4955	{
4956	struct ksz_device *dev = ds->priv;
4957
4958	if (dev->mib_read_interval)
4959	schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval);
4960	return 0;
4961	}
4962
4963	static const struct dsa_switch_ops ksz_switch_ops = {
4964	.get_tag_protocol = ksz_get_tag_protocol,
4965	.connect_tag_protocol = ksz_connect_tag_protocol,
4966	.get_phy_flags = ksz_get_phy_flags,
4967	.setup = ksz_setup,
4968	.teardown = ksz_teardown,
4969	.phy_read = ksz_phy_read16,
4970	.phy_write = ksz_phy_write16,
4971	.phylink_get_caps = ksz_phylink_get_caps,
4972	.port_setup = ksz_port_setup,
4973	.set_ageing_time = ksz_set_ageing_time,
4974	.get_strings = ksz_get_strings,
4975	.get_ethtool_stats = ksz_get_ethtool_stats,
4976	.get_sset_count = ksz_sset_count,
4977	.port_bridge_join = ksz_port_bridge_join,
4978	.port_bridge_leave = ksz_port_bridge_leave,
4979	.port_hsr_join = ksz_hsr_join,
4980	.port_hsr_leave = ksz_hsr_leave,
4981	.port_set_mac_address = ksz_port_set_mac_address,
4982	.port_stp_state_set = ksz_port_stp_state_set,
4983	.port_teardown = ksz_port_teardown,
4984	.port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4985	.port_bridge_flags = ksz_port_bridge_flags,
4986	.port_fast_age = ksz_port_fast_age,
4987	.port_vlan_filtering = ksz_port_vlan_filtering,
4988	.port_vlan_add = ksz_port_vlan_add,
4989	.port_vlan_del = ksz_port_vlan_del,
4990	.port_fdb_dump = ksz_port_fdb_dump,
4991	.port_fdb_add = ksz_port_fdb_add,
4992	.port_fdb_del = ksz_port_fdb_del,
4993	.port_mdb_add = ksz_port_mdb_add,
4994	.port_mdb_del = ksz_port_mdb_del,
4995	.port_mirror_add = ksz_port_mirror_add,
4996	.port_mirror_del = ksz_port_mirror_del,
4997	.get_stats64 = ksz_get_stats64,
4998	.get_pause_stats = ksz_get_pause_stats,
4999	.port_change_mtu = ksz_change_mtu,
5000	.port_max_mtu = ksz_max_mtu,
5001	.get_wol = ksz_get_wol,
5002	.set_wol = ksz_set_wol,
5003	.suspend = ksz_suspend,
5004	.resume = ksz_resume,
5005	.get_ts_info = ksz_get_ts_info,
5006	.port_hwtstamp_get = ksz_hwtstamp_get,
5007	.port_hwtstamp_set = ksz_hwtstamp_set,
5008	.port_txtstamp = ksz_port_txtstamp,
5009	.port_rxtstamp = ksz_port_rxtstamp,
5010	.cls_flower_add = ksz_cls_flower_add,
5011	.cls_flower_del = ksz_cls_flower_del,
5012	.port_setup_tc = ksz_setup_tc,
5013	.support_eee = ksz_support_eee,
5014	.set_mac_eee = ksz_set_mac_eee,
5015	.port_get_default_prio = ksz_port_get_default_prio,
5016	.port_set_default_prio = ksz_port_set_default_prio,
5017	.port_get_dscp_prio = ksz_port_get_dscp_prio,
5018	.port_add_dscp_prio = ksz_port_add_dscp_prio,
5019	.port_del_dscp_prio = ksz_port_del_dscp_prio,
5020	.port_get_apptrust = ksz_port_get_apptrust,
5021	.port_set_apptrust = ksz_port_set_apptrust,
5022	};
5023
5024	struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
5025	{
5026	struct dsa_switch *ds;
5027	struct ksz_device *swdev;
5028
5029	ds = devm_kzalloc(dev: base, size: sizeof(*ds), GFP_KERNEL);
5030	if (!ds)
5031	return NULL;
5032
5033	ds->dev = base;
5034	ds->num_ports = DSA_MAX_PORTS;
5035	ds->ops = &ksz_switch_ops;
5036
5037	swdev = devm_kzalloc(dev: base, size: sizeof(*swdev), GFP_KERNEL);
5038	if (!swdev)
5039	return NULL;
5040
5041	ds->priv = swdev;
5042	swdev->dev = base;
5043
5044	swdev->ds = ds;
5045	swdev->priv = priv;
5046
5047	return swdev;
5048	}
5049	EXPORT_SYMBOL(ksz_switch_alloc);
5050
5051	/**
5052	* ksz_switch_shutdown - Shutdown routine for the switch device.
5053	* @dev: The switch device structure.
5054	*
5055	* This function is responsible for initiating a shutdown sequence for the
5056	* switch device. It invokes the reset operation defined in the device
5057	* operations, if available, to reset the switch. Subsequently, it calls the
5058	* DSA framework's shutdown function to ensure a proper shutdown of the DSA
5059	* switch.
5060	*/
5061	void ksz_switch_shutdown(struct ksz_device *dev)
5062	{
5063	bool wol_enabled = false;
5064
5065	ksz_wol_pre_shutdown(dev, wol_enabled: &wol_enabled);
5066
5067	if (dev->dev_ops->reset && !wol_enabled)
5068	dev->dev_ops->reset(dev);
5069
5070	dsa_switch_shutdown(ds: dev->ds);
5071	}
5072	EXPORT_SYMBOL(ksz_switch_shutdown);
5073
5074	static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
5075	struct device_node *port_dn)
5076	{
5077	phy_interface_t phy_mode = dev->ports[port_num].interface;
5078	int rx_delay = -1, tx_delay = -1;
5079
5080	if (!phy_interface_mode_is_rgmii(mode: phy_mode))
5081	return;
5082
5083	of_property_read_u32(np: port_dn, propname: "rx-internal-delay-ps", out_value: &rx_delay);
5084	of_property_read_u32(np: port_dn, propname: "tx-internal-delay-ps", out_value: &tx_delay);
5085
5086	if (rx_delay == -1 && tx_delay == -1) {
5087	dev_warn(dev->dev,
5088	"Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
5089	"please update device tree to specify \"rx-internal-delay-ps\" and "
5090	"\"tx-internal-delay-ps\"",
5091	port_num);
5092
5093	if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
5094	phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5095	rx_delay = 2000;
5096
5097	if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
5098	phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5099	tx_delay = 2000;
5100	}
5101
5102	if (rx_delay < 0)
5103	rx_delay = 0;
5104	if (tx_delay < 0)
5105	tx_delay = 0;
5106
5107	dev->ports[port_num].rgmii_rx_val = rx_delay;
5108	dev->ports[port_num].rgmii_tx_val = tx_delay;
5109	}
5110
5111	/**
5112	* ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
5113	* register value.
5114	* @array: The array of drive strength values to search.
5115	* @array_size: The size of the array.
5116	* @microamp: The drive strength value in microamp to be converted.
5117	*
5118	* This function searches the array of drive strength values for the given
5119	* microamp value and returns the corresponding register value for that drive.
5120	*
5121	* Returns: If found, the corresponding register value for that drive strength
5122	* is returned. Otherwise, -EINVAL is returned indicating an invalid value.
5123	*/
5124	static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
5125	size_t array_size, int microamp)
5126	{
5127	int i;
5128
5129	for (i = 0; i < array_size; i++) {
5130	if (array[i].microamp == microamp)
5131	return array[i].reg_val;
5132	}
5133
5134	return -EINVAL;
5135	}
5136
5137	/**
5138	* ksz_drive_strength_error() - Report invalid drive strength value
5139	* @dev: ksz device
5140	* @array: The array of drive strength values to search.
5141	* @array_size: The size of the array.
5142	* @microamp: Invalid drive strength value in microamp
5143	*
5144	* This function logs an error message when an unsupported drive strength value
5145	* is detected. It lists out all the supported drive strength values for
5146	* reference in the error message.
5147	*/
5148	static void ksz_drive_strength_error(struct ksz_device *dev,
5149	const struct ksz_drive_strength *array,
5150	size_t array_size, int microamp)
5151	{
5152	char supported_values[100];
5153	size_t remaining_size;
5154	int added_len;
5155	char *ptr;
5156	int i;
5157
5158	remaining_size = sizeof(supported_values);
5159	ptr = supported_values;
5160
5161	for (i = 0; i < array_size; i++) {
5162	added_len = snprintf(buf: ptr, size: remaining_size,
5163	fmt: i == 0 ? "%d" : ", %d", array[i].microamp);
5164
5165	if (added_len >= remaining_size)
5166	break;
5167
5168	ptr += added_len;
5169	remaining_size -= added_len;
5170	}
5171
5172	dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
5173	microamp, supported_values);
5174	}
5175
5176	/**
5177	* ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
5178	* chip variants.
5179	* @dev: ksz device
5180	* @props: Array of drive strength properties to be applied
5181	* @num_props: Number of properties in the array
5182	*
5183	* This function configures the drive strength for various KSZ9477 chip variants
5184	* based on the provided properties. It handles chip-specific nuances and
5185	* ensures only valid drive strengths are written to the respective chip.
5186	*
5187	* Return: 0 on successful configuration, a negative error code on failure.
5188	*/
5189	static int ksz9477_drive_strength_write(struct ksz_device *dev,
5190	struct ksz_driver_strength_prop *props,
5191	int num_props)
5192	{
5193	size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
5194	int i, ret, reg;
5195	u8 mask = 0;
5196	u8 val = 0;
5197
5198	if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
5199	dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5200	props[KSZ_DRIVER_STRENGTH_IO].name);
5201
5202	if (dev->chip_id == KSZ8795_CHIP_ID ||
5203	dev->chip_id == KSZ8794_CHIP_ID ||
5204	dev->chip_id == KSZ8765_CHIP_ID)
5205	reg = KSZ8795_REG_SW_CTRL_20;
5206	else
5207	reg = KSZ9477_REG_SW_IO_STRENGTH;
5208
5209	for (i = 0; i < num_props; i++) {
5210	if (props[i].value == -1)
5211	continue;
5212
5213	ret = ksz_drive_strength_to_reg(array: ksz9477_drive_strengths,
5214	array_size, microamp: props[i].value);
5215	if (ret < 0) {
5216	ksz_drive_strength_error(dev, array: ksz9477_drive_strengths,
5217	array_size, microamp: props[i].value);
5218	return ret;
5219	}
5220
5221	mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
5222	val |= ret << props[i].offset;
5223	}
5224
5225	return ksz_rmw8(dev, offset: reg, mask, val);
5226	}
5227
5228	/**
5229	* ksz88x3_drive_strength_write() - Set the drive strength configuration for
5230	* KSZ8863 compatible chip variants.
5231	* @dev: ksz device
5232	* @props: Array of drive strength properties to be set
5233	* @num_props: Number of properties in the array
5234	*
5235	* This function applies the specified drive strength settings to KSZ88X3 chip
5236	* variants (KSZ8873, KSZ8863).
5237	* It ensures the configurations align with what the chip variant supports and
5238	* warns or errors out on unsupported settings.
5239	*
5240	* Return: 0 on success, error code otherwise
5241	*/
5242	static int ksz88x3_drive_strength_write(struct ksz_device *dev,
5243	struct ksz_driver_strength_prop *props,
5244	int num_props)
5245	{
5246	size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
5247	int microamp;
5248	int i, ret;
5249
5250	for (i = 0; i < num_props; i++) {
5251	if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
5252	continue;
5253
5254	dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5255	props[i].name);
5256	}
5257
5258	microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
5259	ret = ksz_drive_strength_to_reg(array: ksz88x3_drive_strengths, array_size,
5260	microamp);
5261	if (ret < 0) {
5262	ksz_drive_strength_error(dev, array: ksz88x3_drive_strengths,
5263	array_size, microamp);
5264	return ret;
5265	}
5266
5267	return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
5268	KSZ8873_DRIVE_STRENGTH_16MA, val: ret);
5269	}
5270
5271	/**
5272	* ksz_parse_drive_strength() - Extract and apply drive strength configurations
5273	* from device tree properties.
5274	* @dev: ksz device
5275	*
5276	* This function reads the specified drive strength properties from the
5277	* device tree, validates against the supported chip variants, and sets
5278	* them accordingly. An error should be critical here, as the drive strength
5279	* settings are crucial for EMI compliance.
5280	*
5281	* Return: 0 on success, error code otherwise
5282	*/
5283	static int ksz_parse_drive_strength(struct ksz_device *dev)
5284	{
5285	struct ksz_driver_strength_prop of_props[] = {
5286	[KSZ_DRIVER_STRENGTH_HI] = {
5287	.name = "microchip,hi-drive-strength-microamp",
5288	.offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
5289	.value = -1,
5290	},
5291	[KSZ_DRIVER_STRENGTH_LO] = {
5292	.name = "microchip,lo-drive-strength-microamp",
5293	.offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
5294	.value = -1,
5295	},
5296	[KSZ_DRIVER_STRENGTH_IO] = {
5297	.name = "microchip,io-drive-strength-microamp",
5298	.offset = 0, /* don't care */
5299	.value = -1,
5300	},
5301	};
5302	struct device_node *np = dev->dev->of_node;
5303	bool have_any_prop = false;
5304	int i, ret;
5305
5306	for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5307	ret = of_property_read_u32(np, propname: of_props[i].name,
5308	out_value: &of_props[i].value);
5309	if (ret && ret != -EINVAL)
5310	dev_warn(dev->dev, "Failed to read %s\n",
5311	of_props[i].name);
5312	if (ret)
5313	continue;
5314
5315	have_any_prop = true;
5316	}
5317
5318	if (!have_any_prop)
5319	return 0;
5320
5321	switch (dev->chip_id) {
5322	case KSZ88X3_CHIP_ID:
5323	return ksz88x3_drive_strength_write(dev, props: of_props,
5324	ARRAY_SIZE(of_props));
5325	case KSZ8795_CHIP_ID:
5326	case KSZ8794_CHIP_ID:
5327	case KSZ8765_CHIP_ID:
5328	case KSZ8563_CHIP_ID:
5329	case KSZ8567_CHIP_ID:
5330	case KSZ9477_CHIP_ID:
5331	case KSZ9563_CHIP_ID:
5332	case KSZ9567_CHIP_ID:
5333	case KSZ9893_CHIP_ID:
5334	case KSZ9896_CHIP_ID:
5335	case KSZ9897_CHIP_ID:
5336	case LAN9646_CHIP_ID:
5337	return ksz9477_drive_strength_write(dev, props: of_props,
5338	ARRAY_SIZE(of_props));
5339	default:
5340	for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5341	if (of_props[i].value == -1)
5342	continue;
5343
5344	dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5345	of_props[i].name);
5346	}
5347	}
5348
5349	return 0;
5350	}
5351
5352	static int ksz8463_configure_straps_spi(struct ksz_device *dev)
5353	{
5354	struct pinctrl *pinctrl;
5355	struct gpio_desc *rxd0;
5356	struct gpio_desc *rxd1;
5357
5358	rxd0 = devm_gpiod_get_index_optional(dev: dev->dev, con_id: "straps-rxd", index: 0, flags: GPIOD_OUT_LOW);
5359	if (IS_ERR(ptr: rxd0))
5360	return PTR_ERR(ptr: rxd0);
5361
5362	rxd1 = devm_gpiod_get_index_optional(dev: dev->dev, con_id: "straps-rxd", index: 1, flags: GPIOD_OUT_HIGH);
5363	if (IS_ERR(ptr: rxd1))
5364	return PTR_ERR(ptr: rxd1);
5365
5366	if (!rxd0 && !rxd1)
5367	return 0;
5368
5369	if ((rxd0 && !rxd1) || (rxd1 && !rxd0))
5370	return -EINVAL;
5371
5372	pinctrl = devm_pinctrl_get_select(dev: dev->dev, name: "reset");
5373	if (IS_ERR(ptr: pinctrl))
5374	return PTR_ERR(ptr: pinctrl);
5375
5376	return 0;
5377	}
5378
5379	static int ksz8463_release_straps_spi(struct ksz_device *dev)
5380	{
5381	return pinctrl_select_default_state(dev: dev->dev);
5382	}
5383
5384	int ksz_switch_register(struct ksz_device *dev)
5385	{
5386	const struct ksz_chip_data *info;
5387	struct device_node *ports;
5388	phy_interface_t interface;
5389	unsigned int port_num;
5390	int ret;
5391	int i;
5392
5393	dev->reset_gpio = devm_gpiod_get_optional(dev: dev->dev, con_id: "reset",
5394	flags: GPIOD_OUT_LOW);
5395	if (IS_ERR(ptr: dev->reset_gpio))
5396	return PTR_ERR(ptr: dev->reset_gpio);
5397
5398	if (dev->reset_gpio) {
5399	if (of_device_is_compatible(device: dev->dev->of_node, "microchip,ksz8463")) {
5400	ret = ksz8463_configure_straps_spi(dev);
5401	if (ret)
5402	return ret;
5403	}
5404
5405	gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
5406	usleep_range(min: 10000, max: 12000);
5407	gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 0);
5408	msleep(msecs: 100);
5409
5410	if (of_device_is_compatible(device: dev->dev->of_node, "microchip,ksz8463")) {
5411	ret = ksz8463_release_straps_spi(dev);
5412	if (ret)
5413	return ret;
5414	}
5415	}
5416
5417	mutex_init(&dev->dev_mutex);
5418	mutex_init(&dev->regmap_mutex);
5419	mutex_init(&dev->alu_mutex);
5420	mutex_init(&dev->vlan_mutex);
5421
5422	ret = ksz_switch_detect(dev);
5423	if (ret)
5424	return ret;
5425
5426	info = ksz_lookup_info(prod_num: dev->chip_id);
5427	if (!info)
5428	return -ENODEV;
5429
5430	/* Update the compatible info with the probed one */
5431	dev->info = info;
5432
5433	dev_info(dev->dev, "found switch: %s, rev %i\n",
5434	dev->info->dev_name, dev->chip_rev);
5435
5436	ret = ksz_check_device_id(dev);
5437	if (ret)
5438	return ret;
5439
5440	dev->dev_ops = dev->info->ops;
5441
5442	ret = dev->dev_ops->init(dev);
5443	if (ret)
5444	return ret;
5445
5446	dev->ports = devm_kzalloc(dev: dev->dev,
5447	size: dev->info->port_cnt * sizeof(struct ksz_port),
5448	GFP_KERNEL);
5449	if (!dev->ports)
5450	return -ENOMEM;
5451
5452	for (i = 0; i < dev->info->port_cnt; i++) {
5453	spin_lock_init(&dev->ports[i].mib.stats64_lock);
5454	mutex_init(&dev->ports[i].mib.cnt_mutex);
5455	dev->ports[i].mib.counters =
5456	devm_kzalloc(dev: dev->dev,
5457	size: sizeof(u64) * (dev->info->mib_cnt + 1),
5458	GFP_KERNEL);
5459	if (!dev->ports[i].mib.counters)
5460	return -ENOMEM;
5461
5462	dev->ports[i].ksz_dev = dev;
5463	dev->ports[i].num = i;
5464	}
5465
5466	/* set the real number of ports */
5467	dev->ds->num_ports = dev->info->port_cnt;
5468
5469	/* set the phylink ops */
5470	dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5471
5472	/* Host port interface will be self detected, or specifically set in
5473	* device tree.
5474	*/
5475	for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5476	dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5477	if (dev->dev->of_node) {
5478	ret = of_get_phy_mode(np: dev->dev->of_node, interface: &interface);
5479	if (ret == 0)
5480	dev->compat_interface = interface;
5481	ports = of_get_child_by_name(node: dev->dev->of_node, name: "ethernet-ports");
5482	if (!ports)
5483	ports = of_get_child_by_name(node: dev->dev->of_node, name: "ports");
5484	if (ports) {
5485	for_each_available_child_of_node_scoped(ports, port) {
5486	if (of_property_read_u32(np: port, propname: "reg",
5487	out_value: &port_num))
5488	continue;
5489	if (!(dev->port_mask & BIT(port_num))) {
5490	of_node_put(node: ports);
5491	return -EINVAL;
5492	}
5493	of_get_phy_mode(np: port,
5494	interface: &dev->ports[port_num].interface);
5495
5496	ksz_parse_rgmii_delay(dev, port_num, port_dn: port);
5497	dev->ports[port_num].fiber =
5498	of_property_read_bool(np: port,
5499	propname: "micrel,fiber-mode");
5500	}
5501	of_node_put(node: ports);
5502	}
5503	dev->synclko_125 = of_property_read_bool(np: dev->dev->of_node,
5504	propname: "microchip,synclko-125");
5505	dev->synclko_disable = of_property_read_bool(np: dev->dev->of_node,
5506	propname: "microchip,synclko-disable");
5507	if (dev->synclko_125 && dev->synclko_disable) {
5508	dev_err(dev->dev, "inconsistent synclko settings\n");
5509	return -EINVAL;
5510	}
5511
5512	dev->wakeup_source = of_property_read_bool(np: dev->dev->of_node,
5513	propname: "wakeup-source");
5514	dev->pme_active_high = of_property_read_bool(np: dev->dev->of_node,
5515	propname: "microchip,pme-active-high");
5516	}
5517
5518	ret = dsa_register_switch(ds: dev->ds);
5519	if (ret) {
5520	dev->dev_ops->exit(dev);
5521	return ret;
5522	}
5523
5524	/* Read MIB counters every 30 seconds to avoid overflow. */
5525	dev->mib_read_interval = msecs_to_jiffies(m: 5000);
5526
5527	/* Start the MIB timer. */
5528	schedule_delayed_work(dwork: &dev->mib_read, delay: 0);
5529
5530	return ret;
5531	}
5532	EXPORT_SYMBOL(ksz_switch_register);
5533
5534	void ksz_switch_remove(struct ksz_device *dev)
5535	{
5536	/* timer started */
5537	if (dev->mib_read_interval) {
5538	dev->mib_read_interval = 0;
5539	cancel_delayed_work_sync(dwork: &dev->mib_read);
5540	}
5541
5542	dev->dev_ops->exit(dev);
5543	dsa_unregister_switch(ds: dev->ds);
5544
5545	if (dev->reset_gpio)
5546	gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1);
5547
5548	}
5549	EXPORT_SYMBOL(ksz_switch_remove);
5550
5551	#ifdef CONFIG_PM_SLEEP
5552	int ksz_switch_suspend(struct device *dev)
5553	{
5554	struct ksz_device *priv = dev_get_drvdata(dev);
5555
5556	return dsa_switch_suspend(ds: priv->ds);
5557	}
5558	EXPORT_SYMBOL(ksz_switch_suspend);
5559
5560	int ksz_switch_resume(struct device *dev)
5561	{
5562	struct ksz_device *priv = dev_get_drvdata(dev);
5563
5564	return dsa_switch_resume(ds: priv->ds);
5565	}
5566	EXPORT_SYMBOL(ksz_switch_resume);
5567	#endif
5568
5569	MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5570	MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5571	MODULE_LICENSE("GPL");
5572