1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
4 *
5 * Author: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 *
8 * Description:
9 * QE UCC Gigabit Ethernet Driver
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
26#include <linux/dma-mapping.h>
27#include <linux/mii.h>
28#include <linux/phy.h>
29#include <linux/phylink.h>
30#include <linux/workqueue.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_mdio.h>
35#include <linux/of_net.h>
36#include <linux/platform_device.h>
37#include <linux/rtnetlink.h>
38
39#include <linux/uaccess.h>
40#include <asm/irq.h>
41#include <asm/io.h>
42#include <soc/fsl/qe/immap_qe.h>
43#include <soc/fsl/qe/qe.h>
44#include <soc/fsl/qe/ucc.h>
45#include <soc/fsl/qe/ucc_fast.h>
46#include <asm/machdep.h>
47
48#include "ucc_geth.h"
49
50#undef DEBUG
51
52#define ugeth_printk(level, format, arg...) \
53 printk(level format "\n", ## arg)
54
55#define ugeth_dbg(format, arg...) \
56 ugeth_printk(KERN_DEBUG , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
64
65
66static DEFINE_SPINLOCK(ugeth_lock);
67
68static struct {
69 u32 msg_enable;
70} debug = { -1 };
71
72module_param_named(debug, debug.msg_enable, int, 0);
73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
75static int ucc_geth_thread_count(enum ucc_geth_num_of_threads idx)
76{
77 static const u8 count[] = {
78 [UCC_GETH_NUM_OF_THREADS_1] = 1,
79 [UCC_GETH_NUM_OF_THREADS_2] = 2,
80 [UCC_GETH_NUM_OF_THREADS_4] = 4,
81 [UCC_GETH_NUM_OF_THREADS_6] = 6,
82 [UCC_GETH_NUM_OF_THREADS_8] = 8,
83 };
84 if (idx >= ARRAY_SIZE(count))
85 return 0;
86 return count[idx];
87}
88
89static inline int ucc_geth_tx_queues(const struct ucc_geth_info *info)
90{
91 return 1;
92}
93
94static inline int ucc_geth_rx_queues(const struct ucc_geth_info *info)
95{
96 return 1;
97}
98
99static const struct ucc_geth_info ugeth_primary_info = {
100 .uf_info = {
101 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
102 .max_rx_buf_length = 1536,
103 /* adjusted at startup if max-speed 1000 */
104 .urfs = UCC_GETH_URFS_INIT,
105 .urfet = UCC_GETH_URFET_INIT,
106 .urfset = UCC_GETH_URFSET_INIT,
107 .utfs = UCC_GETH_UTFS_INIT,
108 .utfet = UCC_GETH_UTFET_INIT,
109 .utftt = UCC_GETH_UTFTT_INIT,
110 .ufpt = 256,
111 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
112 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
113 .tenc = UCC_FAST_TX_ENCODING_NRZ,
114 .renc = UCC_FAST_RX_ENCODING_NRZ,
115 .tcrc = UCC_FAST_16_BIT_CRC,
116 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
117 },
118 .extendedFilteringChainPointer = ((uint32_t) NULL),
119 .typeorlen = 3072 /*1536 */ ,
120 .nonBackToBackIfgPart1 = 0x40,
121 .nonBackToBackIfgPart2 = 0x60,
122 .miminumInterFrameGapEnforcement = 0x50,
123 .backToBackInterFrameGap = 0x60,
124 .mblinterval = 128,
125 .nortsrbytetime = 5,
126 .fracsiz = 1,
127 .strictpriorityq = 0xff,
128 .altBebTruncation = 0xa,
129 .excessDefer = 1,
130 .maxRetransmission = 0xf,
131 .collisionWindow = 0x37,
132 .receiveFlowControl = 1,
133 .transmitFlowControl = 1,
134 .maxGroupAddrInHash = 4,
135 .maxIndAddrInHash = 4,
136 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
137 .minFrameLength = 64,
138 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
139 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
140 .vlantype = 0x8100,
141 .ecamptr = ((uint32_t) NULL),
142 .eventRegMask = UCCE_OTHER,
143 .pausePeriod = 0xf000,
144 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
145 .bdRingLenTx = {
146 TX_BD_RING_LEN,
147 TX_BD_RING_LEN,
148 TX_BD_RING_LEN,
149 TX_BD_RING_LEN,
150 TX_BD_RING_LEN,
151 TX_BD_RING_LEN,
152 TX_BD_RING_LEN,
153 TX_BD_RING_LEN},
154
155 .bdRingLenRx = {
156 RX_BD_RING_LEN,
157 RX_BD_RING_LEN,
158 RX_BD_RING_LEN,
159 RX_BD_RING_LEN,
160 RX_BD_RING_LEN,
161 RX_BD_RING_LEN,
162 RX_BD_RING_LEN,
163 RX_BD_RING_LEN},
164
165 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
166 .largestexternallookupkeysize =
167 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
168 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
169 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
170 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
171 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
172 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
173 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
174 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
175 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
176 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
177 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
178 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
179 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
180};
181
182#ifdef DEBUG
183static void mem_disp(u8 *addr, int size)
184{
185 u8 *i;
186 int size16Aling = (size >> 4) << 4;
187 int size4Aling = (size >> 2) << 2;
188 int notAlign = 0;
189 if (size % 16)
190 notAlign = 1;
191
192 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
193 printk("0x%08x: %08x %08x %08x %08x\r\n",
194 (u32) i,
195 *((u32 *) (i)),
196 *((u32 *) (i + 4)),
197 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
198 if (notAlign == 1)
199 printk("0x%08x: ", (u32) i);
200 for (; (u32) i < (u32) addr + size4Aling; i += 4)
201 printk("%08x ", *((u32 *) (i)));
202 for (; (u32) i < (u32) addr + size; i++)
203 printk("%02x", *((i)));
204 if (notAlign == 1)
205 printk("\r\n");
206}
207#endif /* DEBUG */
208
209static struct list_head *dequeue(struct list_head *lh)
210{
211 unsigned long flags;
212
213 spin_lock_irqsave(&ugeth_lock, flags);
214 if (!list_empty(head: lh)) {
215 struct list_head *node = lh->next;
216 list_del(entry: node);
217 spin_unlock_irqrestore(lock: &ugeth_lock, flags);
218 return node;
219 } else {
220 spin_unlock_irqrestore(lock: &ugeth_lock, flags);
221 return NULL;
222 }
223}
224
225static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
226 u8 __iomem *bd)
227{
228 struct sk_buff *skb;
229
230 skb = netdev_alloc_skb(dev: ugeth->ndev,
231 length: ugeth->ug_info->uf_info.max_rx_buf_length +
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
233 if (!skb)
234 return NULL;
235
236 /* We need the data buffer to be aligned properly. We will reserve
237 * as many bytes as needed to align the data properly
238 */
239 skb_reserve(skb,
240 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
241 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
242 1)));
243
244 out_be32(&((struct qe_bd __iomem *)bd)->buf,
245 dma_map_single(ugeth->dev,
246 skb->data,
247 ugeth->ug_info->uf_info.max_rx_buf_length +
248 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
249 DMA_FROM_DEVICE));
250
251 out_be32((u32 __iomem *)bd,
252 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
253
254 return skb;
255}
256
257static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
258{
259 u8 __iomem *bd;
260 u32 bd_status;
261 struct sk_buff *skb;
262 int i;
263
264 bd = ugeth->p_rx_bd_ring[rxQ];
265 i = 0;
266
267 do {
268 bd_status = in_be32((u32 __iomem *)bd);
269 skb = get_new_skb(ugeth, bd);
270
271 if (!skb) /* If can not allocate data buffer,
272 abort. Cleanup will be elsewhere */
273 return -ENOMEM;
274
275 ugeth->rx_skbuff[rxQ][i] = skb;
276
277 /* advance the BD pointer */
278 bd += sizeof(struct qe_bd);
279 i++;
280 } while (!(bd_status & R_W));
281
282 return 0;
283}
284
285static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
286 u32 *p_start,
287 u8 num_entries,
288 u32 thread_size,
289 u32 thread_alignment,
290 unsigned int risc,
291 int skip_page_for_first_entry)
292{
293 u32 init_enet_offset;
294 u8 i;
295 int snum;
296
297 for (i = 0; i < num_entries; i++) {
298 if ((snum = qe_get_snum()) < 0) {
299 if (netif_msg_ifup(ugeth))
300 pr_err("Can not get SNUM\n");
301 return snum;
302 }
303 if ((i == 0) && skip_page_for_first_entry)
304 /* First entry of Rx does not have page */
305 init_enet_offset = 0;
306 else {
307 init_enet_offset =
308 qe_muram_alloc(size: thread_size, align: thread_alignment);
309 if (IS_ERR_VALUE(init_enet_offset)) {
310 if (netif_msg_ifup(ugeth))
311 pr_err("Can not allocate DPRAM memory\n");
312 qe_put_snum(snum: (u8) snum);
313 return -ENOMEM;
314 }
315 }
316 *(p_start++) =
317 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
318 | risc;
319 }
320
321 return 0;
322}
323
324static int return_init_enet_entries(struct ucc_geth_private *ugeth,
325 u32 *p_start,
326 u8 num_entries,
327 unsigned int risc,
328 int skip_page_for_first_entry)
329{
330 u32 init_enet_offset;
331 u8 i;
332 int snum;
333
334 for (i = 0; i < num_entries; i++) {
335 u32 val = *p_start;
336
337 /* Check that this entry was actually valid --
338 needed in case failed in allocations */
339 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
340 snum =
341 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
342 ENET_INIT_PARAM_SNUM_SHIFT;
343 qe_put_snum(snum: (u8) snum);
344 if (!((i == 0) && skip_page_for_first_entry)) {
345 /* First entry of Rx does not have page */
346 init_enet_offset =
347 (val & ENET_INIT_PARAM_PTR_MASK);
348 qe_muram_free(offset: init_enet_offset);
349 }
350 *p_start++ = 0;
351 }
352 }
353
354 return 0;
355}
356
357#ifdef DEBUG
358static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
359 u32 __iomem *p_start,
360 u8 num_entries,
361 u32 thread_size,
362 unsigned int risc,
363 int skip_page_for_first_entry)
364{
365 u32 init_enet_offset;
366 u8 i;
367 int snum;
368
369 for (i = 0; i < num_entries; i++) {
370 u32 val = in_be32(p_start);
371
372 /* Check that this entry was actually valid --
373 needed in case failed in allocations */
374 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
375 snum =
376 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
377 ENET_INIT_PARAM_SNUM_SHIFT;
378 qe_put_snum((u8) snum);
379 if (!((i == 0) && skip_page_for_first_entry)) {
380 /* First entry of Rx does not have page */
381 init_enet_offset =
382 (in_be32(p_start) &
383 ENET_INIT_PARAM_PTR_MASK);
384 pr_info("Init enet entry %d:\n", i);
385 pr_info("Base address: 0x%08x\n",
386 (u32)qe_muram_addr(init_enet_offset));
387 mem_disp(qe_muram_addr(init_enet_offset),
388 thread_size);
389 }
390 p_start++;
391 }
392 }
393
394 return 0;
395}
396#endif
397
398static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
399{
400 kfree(objp: enet_addr_cont);
401}
402
403static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
404{
405 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
406 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
407 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
408}
409
410static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
411{
412 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
413
414 if (paddr_num >= NUM_OF_PADDRS) {
415 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
416 return -EINVAL;
417 }
418
419 p_82xx_addr_filt =
420 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
421 addressfiltering;
422
423 /* Writing address ff.ff.ff.ff.ff.ff disables address
424 recognition for this register */
425 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
426 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
427 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
428
429 return 0;
430}
431
432static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
433 u8 *p_enet_addr)
434{
435 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
436 u32 cecr_subblock;
437
438 p_82xx_addr_filt =
439 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
440 addressfiltering;
441
442 cecr_subblock =
443 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.ucc_num);
444
445 /* Ethernet frames are defined in Little Endian mode,
446 therefore to insert */
447 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
448
449 set_mac_addr(reg: &p_82xx_addr_filt->taddr.h, mac: p_enet_addr);
450
451 qe_issue_cmd(QE_SET_GROUP_ADDRESS, device: cecr_subblock,
452 QE_CR_PROTOCOL_ETHERNET, cmd_input: 0);
453}
454
455#ifdef DEBUG
456static void get_statistics(struct ucc_geth_private *ugeth,
457 struct ucc_geth_tx_firmware_statistics *
458 tx_firmware_statistics,
459 struct ucc_geth_rx_firmware_statistics *
460 rx_firmware_statistics,
461 struct ucc_geth_hardware_statistics *hardware_statistics)
462{
463 struct ucc_fast __iomem *uf_regs;
464 struct ucc_geth __iomem *ug_regs;
465 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
466 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
467
468 ug_regs = ugeth->ug_regs;
469 uf_regs = (struct ucc_fast __iomem *) ug_regs;
470 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
471 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
472
473 /* Tx firmware only if user handed pointer and driver actually
474 gathers Tx firmware statistics */
475 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
476 tx_firmware_statistics->sicoltx =
477 in_be32(&p_tx_fw_statistics_pram->sicoltx);
478 tx_firmware_statistics->mulcoltx =
479 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
480 tx_firmware_statistics->latecoltxfr =
481 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
482 tx_firmware_statistics->frabortduecol =
483 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
484 tx_firmware_statistics->frlostinmactxer =
485 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
486 tx_firmware_statistics->carriersenseertx =
487 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
488 tx_firmware_statistics->frtxok =
489 in_be32(&p_tx_fw_statistics_pram->frtxok);
490 tx_firmware_statistics->txfrexcessivedefer =
491 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
492 tx_firmware_statistics->txpkts256 =
493 in_be32(&p_tx_fw_statistics_pram->txpkts256);
494 tx_firmware_statistics->txpkts512 =
495 in_be32(&p_tx_fw_statistics_pram->txpkts512);
496 tx_firmware_statistics->txpkts1024 =
497 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
498 tx_firmware_statistics->txpktsjumbo =
499 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
500 }
501
502 /* Rx firmware only if user handed pointer and driver actually
503 * gathers Rx firmware statistics */
504 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
505 int i;
506 rx_firmware_statistics->frrxfcser =
507 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
508 rx_firmware_statistics->fraligner =
509 in_be32(&p_rx_fw_statistics_pram->fraligner);
510 rx_firmware_statistics->inrangelenrxer =
511 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
512 rx_firmware_statistics->outrangelenrxer =
513 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
514 rx_firmware_statistics->frtoolong =
515 in_be32(&p_rx_fw_statistics_pram->frtoolong);
516 rx_firmware_statistics->runt =
517 in_be32(&p_rx_fw_statistics_pram->runt);
518 rx_firmware_statistics->verylongevent =
519 in_be32(&p_rx_fw_statistics_pram->verylongevent);
520 rx_firmware_statistics->symbolerror =
521 in_be32(&p_rx_fw_statistics_pram->symbolerror);
522 rx_firmware_statistics->dropbsy =
523 in_be32(&p_rx_fw_statistics_pram->dropbsy);
524 for (i = 0; i < 0x8; i++)
525 rx_firmware_statistics->res0[i] =
526 p_rx_fw_statistics_pram->res0[i];
527 rx_firmware_statistics->mismatchdrop =
528 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
529 rx_firmware_statistics->underpkts =
530 in_be32(&p_rx_fw_statistics_pram->underpkts);
531 rx_firmware_statistics->pkts256 =
532 in_be32(&p_rx_fw_statistics_pram->pkts256);
533 rx_firmware_statistics->pkts512 =
534 in_be32(&p_rx_fw_statistics_pram->pkts512);
535 rx_firmware_statistics->pkts1024 =
536 in_be32(&p_rx_fw_statistics_pram->pkts1024);
537 rx_firmware_statistics->pktsjumbo =
538 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
539 rx_firmware_statistics->frlossinmacer =
540 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
541 rx_firmware_statistics->pausefr =
542 in_be32(&p_rx_fw_statistics_pram->pausefr);
543 for (i = 0; i < 0x4; i++)
544 rx_firmware_statistics->res1[i] =
545 p_rx_fw_statistics_pram->res1[i];
546 rx_firmware_statistics->removevlan =
547 in_be32(&p_rx_fw_statistics_pram->removevlan);
548 rx_firmware_statistics->replacevlan =
549 in_be32(&p_rx_fw_statistics_pram->replacevlan);
550 rx_firmware_statistics->insertvlan =
551 in_be32(&p_rx_fw_statistics_pram->insertvlan);
552 }
553
554 /* Hardware only if user handed pointer and driver actually
555 gathers hardware statistics */
556 if (hardware_statistics &&
557 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
558 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
559 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
560 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
561 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
562 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
563 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
564 hardware_statistics->txok = in_be32(&ug_regs->txok);
565 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
566 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
567 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
568 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
569 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
570 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
571 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
572 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
573 }
574}
575
576static void dump_bds(struct ucc_geth_private *ugeth)
577{
578 int i;
579 int length;
580
581 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) {
582 if (ugeth->p_tx_bd_ring[i]) {
583 length =
584 (ugeth->ug_info->bdRingLenTx[i] *
585 sizeof(struct qe_bd));
586 pr_info("TX BDs[%d]\n", i);
587 mem_disp(ugeth->p_tx_bd_ring[i], length);
588 }
589 }
590 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
591 if (ugeth->p_rx_bd_ring[i]) {
592 length =
593 (ugeth->ug_info->bdRingLenRx[i] *
594 sizeof(struct qe_bd));
595 pr_info("RX BDs[%d]\n", i);
596 mem_disp(ugeth->p_rx_bd_ring[i], length);
597 }
598 }
599}
600
601static void dump_regs(struct ucc_geth_private *ugeth)
602{
603 int i;
604
605 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
606 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
607
608 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n",
609 (u32)&ugeth->ug_regs->maccfg1,
610 in_be32(&ugeth->ug_regs->maccfg1));
611 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n",
612 (u32)&ugeth->ug_regs->maccfg2,
613 in_be32(&ugeth->ug_regs->maccfg2));
614 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n",
615 (u32)&ugeth->ug_regs->ipgifg,
616 in_be32(&ugeth->ug_regs->ipgifg));
617 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n",
618 (u32)&ugeth->ug_regs->hafdup,
619 in_be32(&ugeth->ug_regs->hafdup));
620 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n",
621 (u32)&ugeth->ug_regs->ifctl,
622 in_be32(&ugeth->ug_regs->ifctl));
623 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n",
624 (u32)&ugeth->ug_regs->ifstat,
625 in_be32(&ugeth->ug_regs->ifstat));
626 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
627 (u32)&ugeth->ug_regs->macstnaddr1,
628 in_be32(&ugeth->ug_regs->macstnaddr1));
629 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
630 (u32)&ugeth->ug_regs->macstnaddr2,
631 in_be32(&ugeth->ug_regs->macstnaddr2));
632 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n",
633 (u32)&ugeth->ug_regs->uempr,
634 in_be32(&ugeth->ug_regs->uempr));
635 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n",
636 (u32)&ugeth->ug_regs->utbipar,
637 in_be32(&ugeth->ug_regs->utbipar));
638 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n",
639 (u32)&ugeth->ug_regs->uescr,
640 in_be16(&ugeth->ug_regs->uescr));
641 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n",
642 (u32)&ugeth->ug_regs->tx64,
643 in_be32(&ugeth->ug_regs->tx64));
644 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n",
645 (u32)&ugeth->ug_regs->tx127,
646 in_be32(&ugeth->ug_regs->tx127));
647 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n",
648 (u32)&ugeth->ug_regs->tx255,
649 in_be32(&ugeth->ug_regs->tx255));
650 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n",
651 (u32)&ugeth->ug_regs->rx64,
652 in_be32(&ugeth->ug_regs->rx64));
653 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n",
654 (u32)&ugeth->ug_regs->rx127,
655 in_be32(&ugeth->ug_regs->rx127));
656 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n",
657 (u32)&ugeth->ug_regs->rx255,
658 in_be32(&ugeth->ug_regs->rx255));
659 pr_info("txok : addr - 0x%08x, val - 0x%08x\n",
660 (u32)&ugeth->ug_regs->txok,
661 in_be32(&ugeth->ug_regs->txok));
662 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n",
663 (u32)&ugeth->ug_regs->txcf,
664 in_be16(&ugeth->ug_regs->txcf));
665 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n",
666 (u32)&ugeth->ug_regs->tmca,
667 in_be32(&ugeth->ug_regs->tmca));
668 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n",
669 (u32)&ugeth->ug_regs->tbca,
670 in_be32(&ugeth->ug_regs->tbca));
671 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n",
672 (u32)&ugeth->ug_regs->rxfok,
673 in_be32(&ugeth->ug_regs->rxfok));
674 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n",
675 (u32)&ugeth->ug_regs->rxbok,
676 in_be32(&ugeth->ug_regs->rxbok));
677 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n",
678 (u32)&ugeth->ug_regs->rbyt,
679 in_be32(&ugeth->ug_regs->rbyt));
680 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n",
681 (u32)&ugeth->ug_regs->rmca,
682 in_be32(&ugeth->ug_regs->rmca));
683 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n",
684 (u32)&ugeth->ug_regs->rbca,
685 in_be32(&ugeth->ug_regs->rbca));
686 pr_info("scar : addr - 0x%08x, val - 0x%08x\n",
687 (u32)&ugeth->ug_regs->scar,
688 in_be32(&ugeth->ug_regs->scar));
689 pr_info("scam : addr - 0x%08x, val - 0x%08x\n",
690 (u32)&ugeth->ug_regs->scam,
691 in_be32(&ugeth->ug_regs->scam));
692
693 if (ugeth->p_thread_data_tx) {
694 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsTx);
695
696 pr_info("Thread data TXs:\n");
697 pr_info("Base address: 0x%08x\n",
698 (u32)ugeth->p_thread_data_tx);
699 for (i = 0; i < count; i++) {
700 pr_info("Thread data TX[%d]:\n", i);
701 pr_info("Base address: 0x%08x\n",
702 (u32)&ugeth->p_thread_data_tx[i]);
703 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
704 sizeof(struct ucc_geth_thread_data_tx));
705 }
706 }
707 if (ugeth->p_thread_data_rx) {
708 int count = ucc_geth_thread_count(ugeth->ug_info->numThreadsRx);
709
710 pr_info("Thread data RX:\n");
711 pr_info("Base address: 0x%08x\n",
712 (u32)ugeth->p_thread_data_rx);
713 for (i = 0; i < count; i++) {
714 pr_info("Thread data RX[%d]:\n", i);
715 pr_info("Base address: 0x%08x\n",
716 (u32)&ugeth->p_thread_data_rx[i]);
717 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
718 sizeof(struct ucc_geth_thread_data_rx));
719 }
720 }
721 if (ugeth->p_exf_glbl_param) {
722 pr_info("EXF global param:\n");
723 pr_info("Base address: 0x%08x\n",
724 (u32)ugeth->p_exf_glbl_param);
725 mem_disp((u8 *) ugeth->p_exf_glbl_param,
726 sizeof(*ugeth->p_exf_glbl_param));
727 }
728 if (ugeth->p_tx_glbl_pram) {
729 pr_info("TX global param:\n");
730 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
731 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n",
732 (u32)&ugeth->p_tx_glbl_pram->temoder,
733 in_be16(&ugeth->p_tx_glbl_pram->temoder));
734 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n",
735 (u32)&ugeth->p_tx_glbl_pram->sqptr,
736 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
737 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
738 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
739 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
740 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
741 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
742 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
743 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n",
744 (u32)&ugeth->p_tx_glbl_pram->tstate,
745 in_be32(&ugeth->p_tx_glbl_pram->tstate));
746 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
747 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
748 ugeth->p_tx_glbl_pram->iphoffset[0]);
749 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
750 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
751 ugeth->p_tx_glbl_pram->iphoffset[1]);
752 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
753 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
754 ugeth->p_tx_glbl_pram->iphoffset[2]);
755 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
756 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
757 ugeth->p_tx_glbl_pram->iphoffset[3]);
758 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
759 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
760 ugeth->p_tx_glbl_pram->iphoffset[4]);
761 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
762 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
763 ugeth->p_tx_glbl_pram->iphoffset[5]);
764 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
765 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
766 ugeth->p_tx_glbl_pram->iphoffset[6]);
767 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
768 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
769 ugeth->p_tx_glbl_pram->iphoffset[7]);
770 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
771 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
772 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
773 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
774 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
775 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
776 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
777 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
778 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
779 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
780 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
781 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
782 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
783 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
784 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
785 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
786 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
787 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
788 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
789 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
790 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
791 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
792 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
793 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
794 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n",
795 (u32)&ugeth->p_tx_glbl_pram->tqptr,
796 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
797 }
798 if (ugeth->p_rx_glbl_pram) {
799 pr_info("RX global param:\n");
800 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
801 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n",
802 (u32)&ugeth->p_rx_glbl_pram->remoder,
803 in_be32(&ugeth->p_rx_glbl_pram->remoder));
804 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n",
805 (u32)&ugeth->p_rx_glbl_pram->rqptr,
806 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
807 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n",
808 (u32)&ugeth->p_rx_glbl_pram->typeorlen,
809 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
810 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n",
811 (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
812 ugeth->p_rx_glbl_pram->rxgstpack);
813 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n",
814 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
815 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
816 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
817 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
818 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
819 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n",
820 (u32)&ugeth->p_rx_glbl_pram->rstate,
821 ugeth->p_rx_glbl_pram->rstate);
822 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n",
823 (u32)&ugeth->p_rx_glbl_pram->mrblr,
824 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
825 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n",
826 (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
827 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
828 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n",
829 (u32)&ugeth->p_rx_glbl_pram->mflr,
830 in_be16(&ugeth->p_rx_glbl_pram->mflr));
831 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n",
832 (u32)&ugeth->p_rx_glbl_pram->minflr,
833 in_be16(&ugeth->p_rx_glbl_pram->minflr));
834 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n",
835 (u32)&ugeth->p_rx_glbl_pram->maxd1,
836 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
837 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n",
838 (u32)&ugeth->p_rx_glbl_pram->maxd2,
839 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
840 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n",
841 (u32)&ugeth->p_rx_glbl_pram->ecamptr,
842 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
843 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n",
844 (u32)&ugeth->p_rx_glbl_pram->l2qt,
845 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
846 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n",
847 (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
848 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
849 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n",
850 (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
851 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
852 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n",
853 (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
854 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
855 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n",
856 (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
857 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
858 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n",
859 (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
860 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
861 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n",
862 (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
863 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
864 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n",
865 (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
866 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
867 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n",
868 (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
869 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
870 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n",
871 (u32)&ugeth->p_rx_glbl_pram->vlantype,
872 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
873 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n",
874 (u32)&ugeth->p_rx_glbl_pram->vlantci,
875 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
876 for (i = 0; i < 64; i++)
877 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
878 i,
879 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
880 ugeth->p_rx_glbl_pram->addressfiltering[i]);
881 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n",
882 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
883 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
884 }
885 if (ugeth->p_send_q_mem_reg) {
886 pr_info("Send Q memory registers:\n");
887 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
888 for (i = 0; i < ucc_geth_tx_queues(ugeth->ug_info); i++) {
889 pr_info("SQQD[%d]:\n", i);
890 pr_info("Base address: 0x%08x\n",
891 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
892 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
893 sizeof(struct ucc_geth_send_queue_qd));
894 }
895 }
896 if (ugeth->p_scheduler) {
897 pr_info("Scheduler:\n");
898 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
899 mem_disp((u8 *) ugeth->p_scheduler,
900 sizeof(*ugeth->p_scheduler));
901 }
902 if (ugeth->p_tx_fw_statistics_pram) {
903 pr_info("TX FW statistics pram:\n");
904 pr_info("Base address: 0x%08x\n",
905 (u32)ugeth->p_tx_fw_statistics_pram);
906 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
907 sizeof(*ugeth->p_tx_fw_statistics_pram));
908 }
909 if (ugeth->p_rx_fw_statistics_pram) {
910 pr_info("RX FW statistics pram:\n");
911 pr_info("Base address: 0x%08x\n",
912 (u32)ugeth->p_rx_fw_statistics_pram);
913 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
914 sizeof(*ugeth->p_rx_fw_statistics_pram));
915 }
916 if (ugeth->p_rx_irq_coalescing_tbl) {
917 pr_info("RX IRQ coalescing tables:\n");
918 pr_info("Base address: 0x%08x\n",
919 (u32)ugeth->p_rx_irq_coalescing_tbl);
920 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
921 pr_info("RX IRQ coalescing table entry[%d]:\n", i);
922 pr_info("Base address: 0x%08x\n",
923 (u32)&ugeth->p_rx_irq_coalescing_tbl->
924 coalescingentry[i]);
925 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
926 (u32)&ugeth->p_rx_irq_coalescing_tbl->
927 coalescingentry[i].interruptcoalescingmaxvalue,
928 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
929 coalescingentry[i].
930 interruptcoalescingmaxvalue));
931 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
932 (u32)&ugeth->p_rx_irq_coalescing_tbl->
933 coalescingentry[i].interruptcoalescingcounter,
934 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
935 coalescingentry[i].
936 interruptcoalescingcounter));
937 }
938 }
939 if (ugeth->p_rx_bd_qs_tbl) {
940 pr_info("RX BD QS tables:\n");
941 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
942 for (i = 0; i < ucc_geth_rx_queues(ugeth->ug_info); i++) {
943 pr_info("RX BD QS table[%d]:\n", i);
944 pr_info("Base address: 0x%08x\n",
945 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
946 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n",
947 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
948 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
949 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n",
950 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
951 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
952 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
953 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
954 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
955 externalbdbaseptr));
956 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n",
957 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
958 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
959 pr_info("ucode RX Prefetched BDs:\n");
960 pr_info("Base address: 0x%08x\n",
961 (u32)qe_muram_addr(in_be32
962 (&ugeth->p_rx_bd_qs_tbl[i].
963 bdbaseptr)));
964 mem_disp((u8 *)
965 qe_muram_addr(in_be32
966 (&ugeth->p_rx_bd_qs_tbl[i].
967 bdbaseptr)),
968 sizeof(struct ucc_geth_rx_prefetched_bds));
969 }
970 }
971 if (ugeth->p_init_enet_param_shadow) {
972 int size;
973 pr_info("Init enet param shadow:\n");
974 pr_info("Base address: 0x%08x\n",
975 (u32) ugeth->p_init_enet_param_shadow);
976 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
977 sizeof(*ugeth->p_init_enet_param_shadow));
978
979 size = sizeof(struct ucc_geth_thread_rx_pram);
980 if (ugeth->ug_info->rxExtendedFiltering) {
981 size +=
982 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
983 if (ugeth->ug_info->largestexternallookupkeysize ==
984 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
985 size +=
986 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
987 if (ugeth->ug_info->largestexternallookupkeysize ==
988 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
989 size +=
990 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
991 }
992
993 dump_init_enet_entries(ugeth,
994 &(ugeth->p_init_enet_param_shadow->
995 txthread[0]),
996 ENET_INIT_PARAM_MAX_ENTRIES_TX,
997 sizeof(struct ucc_geth_thread_tx_pram),
998 ugeth->ug_info->riscTx, 0);
999 dump_init_enet_entries(ugeth,
1000 &(ugeth->p_init_enet_param_shadow->
1001 rxthread[0]),
1002 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1003 ugeth->ug_info->riscRx, 1);
1004 }
1005}
1006#endif /* DEBUG */
1007
1008static void init_default_reg_vals(u32 __iomem *upsmr_register,
1009 u32 __iomem *maccfg1_register,
1010 u32 __iomem *maccfg2_register)
1011{
1012 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1013 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1014 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1015}
1016
1017static int init_half_duplex_params(int alt_beb,
1018 int back_pressure_no_backoff,
1019 int no_backoff,
1020 int excess_defer,
1021 u8 alt_beb_truncation,
1022 u8 max_retransmissions,
1023 u8 collision_window,
1024 u32 __iomem *hafdup_register)
1025{
1026 u32 value = 0;
1027
1028 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1029 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1030 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1031 return -EINVAL;
1032
1033 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1034
1035 if (alt_beb)
1036 value |= HALFDUP_ALT_BEB;
1037 if (back_pressure_no_backoff)
1038 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1039 if (no_backoff)
1040 value |= HALFDUP_NO_BACKOFF;
1041 if (excess_defer)
1042 value |= HALFDUP_EXCESSIVE_DEFER;
1043
1044 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1045
1046 value |= collision_window;
1047
1048 out_be32(hafdup_register, value);
1049 return 0;
1050}
1051
1052static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1053 u8 non_btb_ipg,
1054 u8 min_ifg,
1055 u8 btb_ipg,
1056 u32 __iomem *ipgifg_register)
1057{
1058 u32 value = 0;
1059
1060 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1061 IPG part 2 */
1062 if (non_btb_cs_ipg > non_btb_ipg)
1063 return -EINVAL;
1064
1065 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1066 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1067 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1068 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1069 return -EINVAL;
1070
1071 value |=
1072 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1073 IPGIFG_NBTB_CS_IPG_MASK);
1074 value |=
1075 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1076 IPGIFG_NBTB_IPG_MASK);
1077 value |=
1078 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1079 IPGIFG_MIN_IFG_MASK);
1080 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1081
1082 out_be32(ipgifg_register, value);
1083 return 0;
1084}
1085
1086int init_flow_control_params(u32 automatic_flow_control_mode,
1087 int rx_flow_control_enable,
1088 int tx_flow_control_enable,
1089 u16 pause_period,
1090 u16 extension_field,
1091 u32 __iomem *upsmr_register,
1092 u32 __iomem *uempr_register,
1093 u32 __iomem *maccfg1_register)
1094{
1095 u32 value = 0;
1096
1097 /* Set UEMPR register */
1098 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1099 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1100 out_be32(uempr_register, value);
1101
1102 /* Set UPSMR register */
1103 setbits32(upsmr_register, automatic_flow_control_mode);
1104
1105 value = in_be32(maccfg1_register);
1106 if (rx_flow_control_enable)
1107 value |= MACCFG1_FLOW_RX;
1108 if (tx_flow_control_enable)
1109 value |= MACCFG1_FLOW_TX;
1110 out_be32(maccfg1_register, value);
1111
1112 return 0;
1113}
1114
1115static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1116 int auto_zero_hardware_statistics,
1117 u32 __iomem *upsmr_register,
1118 u16 __iomem *uescr_register)
1119{
1120 u16 uescr_value = 0;
1121
1122 /* Enable hardware statistics gathering if requested */
1123 if (enable_hardware_statistics)
1124 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1125
1126 /* Clear hardware statistics counters */
1127 uescr_value = in_be16(uescr_register);
1128 uescr_value |= UESCR_CLRCNT;
1129 /* Automatically zero hardware statistics counters on read,
1130 if requested */
1131 if (auto_zero_hardware_statistics)
1132 uescr_value |= UESCR_AUTOZ;
1133 out_be16(uescr_register, uescr_value);
1134
1135 return 0;
1136}
1137
1138static int init_firmware_statistics_gathering_mode(int
1139 enable_tx_firmware_statistics,
1140 int enable_rx_firmware_statistics,
1141 u32 __iomem *tx_rmon_base_ptr,
1142 u32 tx_firmware_statistics_structure_address,
1143 u32 __iomem *rx_rmon_base_ptr,
1144 u32 rx_firmware_statistics_structure_address,
1145 u16 __iomem *temoder_register,
1146 u32 __iomem *remoder_register)
1147{
1148 /* Note: this function does not check if */
1149 /* the parameters it receives are NULL */
1150
1151 if (enable_tx_firmware_statistics) {
1152 out_be32(tx_rmon_base_ptr,
1153 tx_firmware_statistics_structure_address);
1154 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1155 }
1156
1157 if (enable_rx_firmware_statistics) {
1158 out_be32(rx_rmon_base_ptr,
1159 rx_firmware_statistics_structure_address);
1160 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1161 }
1162
1163 return 0;
1164}
1165
1166static int init_mac_station_addr_regs(u8 address_byte_0,
1167 u8 address_byte_1,
1168 u8 address_byte_2,
1169 u8 address_byte_3,
1170 u8 address_byte_4,
1171 u8 address_byte_5,
1172 u32 __iomem *macstnaddr1_register,
1173 u32 __iomem *macstnaddr2_register)
1174{
1175 u32 value = 0;
1176
1177 /* Example: for a station address of 0x12345678ABCD, */
1178 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1179
1180 /* MACSTNADDR1 Register: */
1181
1182 /* 0 7 8 15 */
1183 /* station address byte 5 station address byte 4 */
1184 /* 16 23 24 31 */
1185 /* station address byte 3 station address byte 2 */
1186 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1187 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1188 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1189 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1190
1191 out_be32(macstnaddr1_register, value);
1192
1193 /* MACSTNADDR2 Register: */
1194
1195 /* 0 7 8 15 */
1196 /* station address byte 1 station address byte 0 */
1197 /* 16 23 24 31 */
1198 /* reserved reserved */
1199 value = 0;
1200 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1201 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1202
1203 out_be32(macstnaddr2_register, value);
1204
1205 return 0;
1206}
1207
1208static int init_rx_parameters(int reject_broadcast,
1209 int receive_short_frames,
1210 int promiscuous, u32 __iomem *upsmr_register)
1211{
1212 u32 value = 0;
1213
1214 value = in_be32(upsmr_register);
1215
1216 if (reject_broadcast)
1217 value |= UCC_GETH_UPSMR_BRO;
1218 else
1219 value &= ~UCC_GETH_UPSMR_BRO;
1220
1221 if (receive_short_frames)
1222 value |= UCC_GETH_UPSMR_RSH;
1223 else
1224 value &= ~UCC_GETH_UPSMR_RSH;
1225
1226 if (promiscuous)
1227 value |= UCC_GETH_UPSMR_PRO;
1228 else
1229 value &= ~UCC_GETH_UPSMR_PRO;
1230
1231 out_be32(upsmr_register, value);
1232
1233 return 0;
1234}
1235
1236static int init_max_rx_buff_len(u16 max_rx_buf_len,
1237 u16 __iomem *mrblr_register)
1238{
1239 /* max_rx_buf_len value must be a multiple of 128 */
1240 if ((max_rx_buf_len == 0) ||
1241 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1242 return -EINVAL;
1243
1244 out_be16(mrblr_register, max_rx_buf_len);
1245 return 0;
1246}
1247
1248static int init_min_frame_len(u16 min_frame_length,
1249 u16 __iomem *minflr_register,
1250 u16 __iomem *mrblr_register)
1251{
1252 u16 mrblr_value = 0;
1253
1254 mrblr_value = in_be16(mrblr_register);
1255 if (min_frame_length >= (mrblr_value - 4))
1256 return -EINVAL;
1257
1258 out_be16(minflr_register, min_frame_length);
1259 return 0;
1260}
1261
1262static bool phy_interface_mode_is_reduced(phy_interface_t interface)
1263{
1264 return phy_interface_mode_is_rgmii(mode: interface) ||
1265 interface == PHY_INTERFACE_MODE_RMII ||
1266 interface == PHY_INTERFACE_MODE_RTBI;
1267}
1268
1269static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1270{
1271 struct ucc_fast_private *uccf;
1272 u32 cecr_subblock;
1273 u32 temp;
1274 int i = 10;
1275
1276 uccf = ugeth->uccf;
1277
1278 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1279 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1280 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1281
1282 /* Issue host command */
1283 cecr_subblock =
1284 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.ucc_num);
1285 qe_issue_cmd(QE_GRACEFUL_STOP_TX, device: cecr_subblock,
1286 QE_CR_PROTOCOL_ETHERNET, cmd_input: 0);
1287
1288 /* Wait for command to complete */
1289 do {
1290 msleep(msecs: 10);
1291 temp = in_be32(uccf->p_ucce);
1292 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1293
1294 uccf->stopped_tx = 1;
1295
1296 return 0;
1297}
1298
1299static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1300{
1301 struct ucc_fast_private *uccf;
1302 u32 cecr_subblock;
1303 u8 temp;
1304 int i = 10;
1305
1306 uccf = ugeth->uccf;
1307
1308 /* Clear acknowledge bit */
1309 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1310 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1311 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1312
1313 /* Keep issuing command and checking acknowledge bit until
1314 it is asserted, according to spec */
1315 do {
1316 /* Issue host command */
1317 cecr_subblock =
1318 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.
1319 ucc_num);
1320 qe_issue_cmd(QE_GRACEFUL_STOP_RX, device: cecr_subblock,
1321 QE_CR_PROTOCOL_ETHERNET, cmd_input: 0);
1322 msleep(msecs: 10);
1323 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1324 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1325
1326 uccf->stopped_rx = 1;
1327
1328 return 0;
1329}
1330
1331static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1332{
1333 struct ucc_fast_private *uccf;
1334 u32 cecr_subblock;
1335
1336 uccf = ugeth->uccf;
1337
1338 cecr_subblock =
1339 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.ucc_num);
1340 qe_issue_cmd(QE_RESTART_TX, device: cecr_subblock, QE_CR_PROTOCOL_ETHERNET, cmd_input: 0);
1341 uccf->stopped_tx = 0;
1342
1343 return 0;
1344}
1345
1346static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1347{
1348 struct ucc_fast_private *uccf;
1349 u32 cecr_subblock;
1350
1351 uccf = ugeth->uccf;
1352
1353 cecr_subblock =
1354 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.ucc_num);
1355 qe_issue_cmd(QE_RESTART_RX, device: cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1356 cmd_input: 0);
1357 uccf->stopped_rx = 0;
1358
1359 return 0;
1360}
1361
1362static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1363{
1364 struct ucc_fast_private *uccf;
1365 int enabled_tx, enabled_rx;
1366
1367 uccf = ugeth->uccf;
1368
1369 /* check if the UCC number is in range. */
1370 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1371 if (netif_msg_probe(ugeth))
1372 pr_err("ucc_num out of range\n");
1373 return -EINVAL;
1374 }
1375
1376 enabled_tx = uccf->enabled_tx;
1377 enabled_rx = uccf->enabled_rx;
1378
1379 /* Get Tx and Rx going again, in case this channel was actively
1380 disabled. */
1381 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1382 ugeth_restart_tx(ugeth);
1383 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1384 ugeth_restart_rx(ugeth);
1385
1386 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1387
1388 return 0;
1389
1390}
1391
1392static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1393{
1394 struct ucc_fast_private *uccf;
1395
1396 uccf = ugeth->uccf;
1397
1398 /* check if the UCC number is in range. */
1399 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1400 if (netif_msg_probe(ugeth))
1401 pr_err("ucc_num out of range\n");
1402 return -EINVAL;
1403 }
1404
1405 /* Stop any transmissions */
1406 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1407 ugeth_graceful_stop_tx(ugeth);
1408
1409 /* Stop any receptions */
1410 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1411 ugeth_graceful_stop_rx(ugeth);
1412
1413 ucc_fast_disable(uccf: ugeth->uccf, mode); /* OK to do even if not enabled */
1414
1415 return 0;
1416}
1417
1418static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1419{
1420 /* Prevent any further xmits */
1421 netif_tx_stop_all_queues(dev: ugeth->ndev);
1422
1423 /* Disable the interrupt to avoid NAPI rescheduling. */
1424 disable_irq(irq: ugeth->ug_info->uf_info.irq);
1425
1426 /* Stop NAPI, and possibly wait for its completion. */
1427 napi_disable(n: &ugeth->napi);
1428}
1429
1430static void ugeth_activate(struct ucc_geth_private *ugeth)
1431{
1432 napi_enable(n: &ugeth->napi);
1433 enable_irq(irq: ugeth->ug_info->uf_info.irq);
1434
1435 /* allow to xmit again */
1436 netif_tx_wake_all_queues(dev: ugeth->ndev);
1437 netdev_watchdog_up(dev: ugeth->ndev);
1438}
1439
1440/* Initialize TBI PHY interface for communicating with the
1441 * SERDES lynx PHY on the chip. We communicate with this PHY
1442 * through the MDIO bus on each controller, treating it as a
1443 * "normal" PHY at the address found in the UTBIPA register. We assume
1444 * that the UTBIPA register is valid. Either the MDIO bus code will set
1445 * it to a value that doesn't conflict with other PHYs on the bus, or the
1446 * value doesn't matter, as there are no other PHYs on the bus.
1447 */
1448static void uec_configure_serdes(struct net_device *dev)
1449{
1450 struct ucc_geth_private *ugeth = netdev_priv(dev);
1451 struct ucc_geth_info *ug_info = ugeth->ug_info;
1452 struct phy_device *tbiphy;
1453
1454 if (!ug_info->tbi_node) {
1455 dev_warn(&dev->dev, "SGMII mode requires that the device tree specify a tbi-handle\n");
1456 return;
1457 }
1458
1459 tbiphy = of_phy_find_device(phy_np: ug_info->tbi_node);
1460 if (!tbiphy) {
1461 dev_err(&dev->dev, "error: Could not get TBI device\n");
1462 return;
1463 }
1464
1465 /*
1466 * If the link is already up, we must already be ok, and don't need to
1467 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1468 * everything for us? Resetting it takes the link down and requires
1469 * several seconds for it to come back.
1470 */
1471 if (phy_read(phydev: tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
1472 put_device(dev: &tbiphy->mdio.dev);
1473 return;
1474 }
1475
1476 /* Single clk mode, mii mode off(for serdes communication) */
1477 phy_write(phydev: tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1478
1479 phy_write(phydev: tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1480
1481 phy_write(phydev: tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1482
1483 put_device(dev: &tbiphy->mdio.dev);
1484}
1485
1486static void ugeth_mac_link_up(struct phylink_config *config, struct phy_device *phy,
1487 unsigned int mode, phy_interface_t interface,
1488 int speed, int duplex, bool tx_pause, bool rx_pause)
1489{
1490 struct net_device *ndev = to_net_dev(config->dev);
1491 struct ucc_geth_private *ugeth = netdev_priv(dev: ndev);
1492 struct ucc_geth_info *ug_info = ugeth->ug_info;
1493 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
1494 struct ucc_fast __iomem *uf_regs = ugeth->uccf->uf_regs;
1495 u32 old_maccfg2, maccfg2 = in_be32(&ug_regs->maccfg2);
1496 u32 old_upsmr, upsmr = in_be32(&uf_regs->upsmr);
1497
1498 old_maccfg2 = maccfg2;
1499 old_upsmr = upsmr;
1500
1501 /* No length check */
1502 maccfg2 &= ~MACCFG2_LC;
1503 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1504 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1505 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1506
1507 if (speed == SPEED_10 || speed == SPEED_100)
1508 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1509 else if (speed == SPEED_1000)
1510 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1511
1512 maccfg2 |= ug_info->padAndCrc;
1513
1514 if (phy_interface_mode_is_reduced(interface)) {
1515
1516 if (interface != PHY_INTERFACE_MODE_RMII)
1517 upsmr |= UCC_GETH_UPSMR_RPM;
1518
1519 switch (speed) {
1520 case SPEED_10:
1521 upsmr |= UCC_GETH_UPSMR_R10M;
1522 fallthrough;
1523 case SPEED_100:
1524 if (interface != PHY_INTERFACE_MODE_RTBI)
1525 upsmr |= UCC_GETH_UPSMR_RMM;
1526 }
1527 }
1528
1529 if (interface == PHY_INTERFACE_MODE_TBI ||
1530 interface == PHY_INTERFACE_MODE_RTBI)
1531 upsmr |= UCC_GETH_UPSMR_TBIM;
1532
1533 if (interface == PHY_INTERFACE_MODE_SGMII)
1534 upsmr |= UCC_GETH_UPSMR_SGMM;
1535
1536 if (duplex == DUPLEX_HALF)
1537 maccfg2 &= ~(MACCFG2_FDX);
1538 else
1539 maccfg2 |= MACCFG2_FDX;
1540
1541 if (maccfg2 != old_maccfg2 || upsmr != old_upsmr) {
1542 /*
1543 * To change the MAC configuration we need to disable
1544 * the controller. To do so, we have to either grab
1545 * ugeth->lock, which is a bad idea since 'graceful
1546 * stop' commands might take quite a while, or we can
1547 * quiesce driver's activity.
1548 */
1549 ugeth_quiesce(ugeth);
1550 ugeth_disable(ugeth, mode: COMM_DIR_RX_AND_TX);
1551
1552 out_be32(&ug_regs->maccfg2, maccfg2);
1553 out_be32(&uf_regs->upsmr, upsmr);
1554
1555 ugeth_enable(ugeth, mode: COMM_DIR_RX_AND_TX);
1556 ugeth_activate(ugeth);
1557 }
1558
1559 if (interface == PHY_INTERFACE_MODE_SGMII)
1560 uec_configure_serdes(dev: ndev);
1561
1562 if (!phylink_autoneg_inband(mode)) {
1563 ug_info->aufc = 0;
1564 ug_info->receiveFlowControl = rx_pause;
1565 ug_info->transmitFlowControl = tx_pause;
1566
1567 init_flow_control_params(automatic_flow_control_mode: ug_info->aufc,
1568 rx_flow_control_enable: ug_info->receiveFlowControl,
1569 tx_flow_control_enable: ug_info->transmitFlowControl,
1570 pause_period: ug_info->pausePeriod,
1571 extension_field: ug_info->extensionField,
1572 upsmr_register: &ugeth->uccf->uf_regs->upsmr,
1573 uempr_register: &ugeth->ug_regs->uempr,
1574 maccfg1_register: &ugeth->ug_regs->maccfg1);
1575 }
1576
1577 ugeth_enable(ugeth, mode: COMM_DIR_RX_AND_TX);
1578}
1579
1580static void ugeth_mac_link_down(struct phylink_config *config,
1581 unsigned int mode, phy_interface_t interface)
1582{
1583 struct net_device *ndev = to_net_dev(config->dev);
1584 struct ucc_geth_private *ugeth = netdev_priv(dev: ndev);
1585
1586 ugeth_disable(ugeth, mode: COMM_DIR_RX_AND_TX);
1587}
1588
1589static void ugeth_mac_config(struct phylink_config *config, unsigned int mode,
1590 const struct phylink_link_state *state)
1591{
1592 struct net_device *ndev = to_net_dev(config->dev);
1593 struct ucc_geth_private *ugeth = netdev_priv(dev: ndev);
1594 struct ucc_geth_info *ug_info = ugeth->ug_info;
1595 u16 value;
1596
1597 if (state->interface == PHY_INTERFACE_MODE_TBI ||
1598 state->interface == PHY_INTERFACE_MODE_RTBI) {
1599 struct phy_device *tbiphy;
1600
1601 if (!ug_info->tbi_node)
1602 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1603
1604 tbiphy = of_phy_find_device(phy_np: ug_info->tbi_node);
1605 if (!tbiphy)
1606 pr_warn("Could not get TBI device\n");
1607
1608 value = phy_read(phydev: tbiphy, ENET_TBI_MII_CR);
1609 value &= ~0x1000; /* Turn off autonegotiation */
1610 phy_write(phydev: tbiphy, ENET_TBI_MII_CR, val: value);
1611
1612 put_device(dev: &tbiphy->mdio.dev);
1613 }
1614
1615 if (phylink_autoneg_inband(mode)) {
1616 ug_info->aufc = 1;
1617
1618 init_flow_control_params(automatic_flow_control_mode: ug_info->aufc, rx_flow_control_enable: 1, tx_flow_control_enable: 1,
1619 pause_period: ug_info->pausePeriod,
1620 extension_field: ug_info->extensionField,
1621 upsmr_register: &ugeth->uccf->uf_regs->upsmr,
1622 uempr_register: &ugeth->ug_regs->uempr,
1623 maccfg1_register: &ugeth->ug_regs->maccfg1);
1624 }
1625}
1626
1627static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1628{
1629#ifdef DEBUG
1630 ucc_fast_dump_regs(ugeth->uccf);
1631 dump_regs(ugeth);
1632 dump_bds(ugeth);
1633#endif
1634}
1635
1636static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1637 ugeth,
1638 enum enet_addr_type
1639 enet_addr_type)
1640{
1641 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1642 struct ucc_fast_private *uccf;
1643 enum comm_dir comm_dir;
1644 struct list_head *p_lh;
1645 u16 i, num;
1646 u32 __iomem *addr_h;
1647 u32 __iomem *addr_l;
1648 u8 *p_counter;
1649
1650 uccf = ugeth->uccf;
1651
1652 p_82xx_addr_filt =
1653 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1654 ugeth->p_rx_glbl_pram->addressfiltering;
1655
1656 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1657 addr_h = &(p_82xx_addr_filt->gaddr_h);
1658 addr_l = &(p_82xx_addr_filt->gaddr_l);
1659 p_lh = &ugeth->group_hash_q;
1660 p_counter = &(ugeth->numGroupAddrInHash);
1661 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1662 addr_h = &(p_82xx_addr_filt->iaddr_h);
1663 addr_l = &(p_82xx_addr_filt->iaddr_l);
1664 p_lh = &ugeth->ind_hash_q;
1665 p_counter = &(ugeth->numIndAddrInHash);
1666 } else
1667 return -EINVAL;
1668
1669 comm_dir = 0;
1670 if (uccf->enabled_tx)
1671 comm_dir |= COMM_DIR_TX;
1672 if (uccf->enabled_rx)
1673 comm_dir |= COMM_DIR_RX;
1674 if (comm_dir)
1675 ugeth_disable(ugeth, mode: comm_dir);
1676
1677 /* Clear the hash table. */
1678 out_be32(addr_h, 0x00000000);
1679 out_be32(addr_l, 0x00000000);
1680
1681 if (!p_lh)
1682 return 0;
1683
1684 num = *p_counter;
1685
1686 /* Delete all remaining CQ elements */
1687 for (i = 0; i < num; i++)
1688 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1689
1690 *p_counter = 0;
1691
1692 if (comm_dir)
1693 ugeth_enable(ugeth, mode: comm_dir);
1694
1695 return 0;
1696}
1697
1698static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1699 u8 paddr_num)
1700{
1701 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1702 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1703}
1704
1705static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1706{
1707 struct ucc_geth_info *ug_info;
1708 struct ucc_fast_info *uf_info;
1709 u16 i, j;
1710 u8 __iomem *bd;
1711
1712
1713 ug_info = ugeth->ug_info;
1714 uf_info = &ug_info->uf_info;
1715
1716 for (i = 0; i < ucc_geth_rx_queues(info: ugeth->ug_info); i++) {
1717 if (ugeth->p_rx_bd_ring[i]) {
1718 /* Return existing data buffers in ring */
1719 bd = ugeth->p_rx_bd_ring[i];
1720 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1721 if (ugeth->rx_skbuff[i][j]) {
1722 dma_unmap_single(ugeth->dev,
1723 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1724 ugeth->ug_info->
1725 uf_info.max_rx_buf_length +
1726 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1727 DMA_FROM_DEVICE);
1728 dev_kfree_skb_any(
1729 skb: ugeth->rx_skbuff[i][j]);
1730 ugeth->rx_skbuff[i][j] = NULL;
1731 }
1732 bd += sizeof(struct qe_bd);
1733 }
1734
1735 kfree(objp: ugeth->rx_skbuff[i]);
1736
1737 kfree(objp: ugeth->p_rx_bd_ring[i]);
1738 ugeth->p_rx_bd_ring[i] = NULL;
1739 }
1740 }
1741
1742}
1743
1744static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1745{
1746 struct ucc_geth_info *ug_info;
1747 struct ucc_fast_info *uf_info;
1748 u16 i, j;
1749 u8 __iomem *bd;
1750
1751 netdev_reset_queue(dev_queue: ugeth->ndev);
1752
1753 ug_info = ugeth->ug_info;
1754 uf_info = &ug_info->uf_info;
1755
1756 for (i = 0; i < ucc_geth_tx_queues(info: ugeth->ug_info); i++) {
1757 bd = ugeth->p_tx_bd_ring[i];
1758 if (!bd)
1759 continue;
1760 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1761 if (ugeth->tx_skbuff[i][j]) {
1762 dma_unmap_single(ugeth->dev,
1763 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1764 (in_be32((u32 __iomem *)bd) &
1765 BD_LENGTH_MASK),
1766 DMA_TO_DEVICE);
1767 dev_kfree_skb_any(skb: ugeth->tx_skbuff[i][j]);
1768 ugeth->tx_skbuff[i][j] = NULL;
1769 }
1770 }
1771
1772 kfree(objp: ugeth->tx_skbuff[i]);
1773
1774 kfree(objp: ugeth->p_tx_bd_ring[i]);
1775 ugeth->p_tx_bd_ring[i] = NULL;
1776 }
1777
1778}
1779
1780static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1781{
1782 if (!ugeth)
1783 return;
1784
1785 if (ugeth->uccf) {
1786 ucc_fast_free(uccf: ugeth->uccf);
1787 ugeth->uccf = NULL;
1788 }
1789
1790 qe_muram_free_addr(addr: ugeth->p_thread_data_tx);
1791 ugeth->p_thread_data_tx = NULL;
1792
1793 qe_muram_free_addr(addr: ugeth->p_thread_data_rx);
1794 ugeth->p_thread_data_rx = NULL;
1795
1796 qe_muram_free_addr(addr: ugeth->p_exf_glbl_param);
1797 ugeth->p_exf_glbl_param = NULL;
1798
1799 qe_muram_free_addr(addr: ugeth->p_rx_glbl_pram);
1800 ugeth->p_rx_glbl_pram = NULL;
1801
1802 qe_muram_free_addr(addr: ugeth->p_tx_glbl_pram);
1803 ugeth->p_tx_glbl_pram = NULL;
1804
1805 qe_muram_free_addr(addr: ugeth->p_send_q_mem_reg);
1806 ugeth->p_send_q_mem_reg = NULL;
1807
1808 qe_muram_free_addr(addr: ugeth->p_scheduler);
1809 ugeth->p_scheduler = NULL;
1810
1811 qe_muram_free_addr(addr: ugeth->p_tx_fw_statistics_pram);
1812 ugeth->p_tx_fw_statistics_pram = NULL;
1813
1814 qe_muram_free_addr(addr: ugeth->p_rx_fw_statistics_pram);
1815 ugeth->p_rx_fw_statistics_pram = NULL;
1816
1817 qe_muram_free_addr(addr: ugeth->p_rx_irq_coalescing_tbl);
1818 ugeth->p_rx_irq_coalescing_tbl = NULL;
1819
1820 qe_muram_free_addr(addr: ugeth->p_rx_bd_qs_tbl);
1821 ugeth->p_rx_bd_qs_tbl = NULL;
1822
1823 if (ugeth->p_init_enet_param_shadow) {
1824 return_init_enet_entries(ugeth,
1825 p_start: &(ugeth->p_init_enet_param_shadow->
1826 rxthread[0]),
1827 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1828 risc: ugeth->ug_info->riscRx, skip_page_for_first_entry: 1);
1829 return_init_enet_entries(ugeth,
1830 p_start: &(ugeth->p_init_enet_param_shadow->
1831 txthread[0]),
1832 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1833 risc: ugeth->ug_info->riscTx, skip_page_for_first_entry: 0);
1834 kfree(objp: ugeth->p_init_enet_param_shadow);
1835 ugeth->p_init_enet_param_shadow = NULL;
1836 }
1837 ucc_geth_free_tx(ugeth);
1838 ucc_geth_free_rx(ugeth);
1839 while (!list_empty(head: &ugeth->group_hash_q))
1840 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1841 (dequeue(&ugeth->group_hash_q)));
1842 while (!list_empty(head: &ugeth->ind_hash_q))
1843 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1844 (dequeue(&ugeth->ind_hash_q)));
1845 if (ugeth->ug_regs) {
1846 iounmap(addr: ugeth->ug_regs);
1847 ugeth->ug_regs = NULL;
1848 }
1849}
1850
1851static void ucc_geth_set_multi(struct net_device *dev)
1852{
1853 struct ucc_geth_private *ugeth;
1854 struct netdev_hw_addr *ha;
1855 struct ucc_fast __iomem *uf_regs;
1856 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1857
1858 ugeth = netdev_priv(dev);
1859
1860 uf_regs = ugeth->uccf->uf_regs;
1861
1862 if (dev->flags & IFF_PROMISC) {
1863 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1864 } else {
1865 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1866
1867 p_82xx_addr_filt =
1868 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1869 p_rx_glbl_pram->addressfiltering;
1870
1871 if (dev->flags & IFF_ALLMULTI) {
1872 /* Catch all multicast addresses, so set the
1873 * filter to all 1's.
1874 */
1875 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1876 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1877 } else {
1878 /* Clear filter and add the addresses in the list.
1879 */
1880 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1881 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1882
1883 netdev_for_each_mc_addr(ha, dev) {
1884 /* Ask CPM to run CRC and set bit in
1885 * filter mask.
1886 */
1887 hw_add_addr_in_hash(ugeth, p_enet_addr: ha->addr);
1888 }
1889 }
1890 }
1891}
1892
1893static void ucc_geth_stop(struct ucc_geth_private *ugeth)
1894{
1895 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
1896
1897 ugeth_vdbg("%s: IN", __func__);
1898
1899 /*
1900 * Tell the kernel the link is down.
1901 * Must be done before disabling the controller
1902 * or deadlock may happen.
1903 */
1904 phylink_stop(ugeth->phylink);
1905
1906 /* Disable the controller */
1907 ugeth_disable(ugeth, mode: COMM_DIR_RX_AND_TX);
1908
1909 /* Mask all interrupts */
1910 out_be32(ugeth->uccf->p_uccm, 0x00000000);
1911
1912 /* Clear all interrupts */
1913 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
1914
1915 /* Disable Rx and Tx */
1916 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
1917
1918 ucc_geth_memclean(ugeth);
1919}
1920
1921static int ucc_struct_init(struct ucc_geth_private *ugeth)
1922{
1923 struct ucc_geth_info *ug_info;
1924 struct ucc_fast_info *uf_info;
1925 int i;
1926
1927 ug_info = ugeth->ug_info;
1928 uf_info = &ug_info->uf_info;
1929
1930 /* Rx BD lengths */
1931 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++) {
1932 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
1933 (ug_info->bdRingLenRx[i] %
1934 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
1935 if (netif_msg_probe(ugeth))
1936 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
1937 return -EINVAL;
1938 }
1939 }
1940
1941 /* Tx BD lengths */
1942 for (i = 0; i < ucc_geth_tx_queues(info: ug_info); i++) {
1943 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
1944 if (netif_msg_probe(ugeth))
1945 pr_err("Tx BD ring length must be no smaller than 2\n");
1946 return -EINVAL;
1947 }
1948 }
1949
1950 /* mrblr */
1951 if ((uf_info->max_rx_buf_length == 0) ||
1952 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
1953 if (netif_msg_probe(ugeth))
1954 pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
1955 return -EINVAL;
1956 }
1957
1958 /* num Tx queues */
1959 if (ucc_geth_tx_queues(info: ug_info) > NUM_TX_QUEUES) {
1960 if (netif_msg_probe(ugeth))
1961 pr_err("number of tx queues too large\n");
1962 return -EINVAL;
1963 }
1964
1965 /* num Rx queues */
1966 if (ucc_geth_rx_queues(info: ug_info) > NUM_RX_QUEUES) {
1967 if (netif_msg_probe(ugeth))
1968 pr_err("number of rx queues too large\n");
1969 return -EINVAL;
1970 }
1971
1972 /* l2qt */
1973 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
1974 if (ug_info->l2qt[i] >= ucc_geth_rx_queues(info: ug_info)) {
1975 if (netif_msg_probe(ugeth))
1976 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
1977 return -EINVAL;
1978 }
1979 }
1980
1981 /* l3qt */
1982 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
1983 if (ug_info->l3qt[i] >= ucc_geth_rx_queues(info: ug_info)) {
1984 if (netif_msg_probe(ugeth))
1985 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
1986 return -EINVAL;
1987 }
1988 }
1989
1990 if (ug_info->cam && !ug_info->ecamptr) {
1991 if (netif_msg_probe(ugeth))
1992 pr_err("If cam mode is chosen, must supply cam ptr\n");
1993 return -EINVAL;
1994 }
1995
1996 if ((ug_info->numStationAddresses !=
1997 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
1998 ug_info->rxExtendedFiltering) {
1999 if (netif_msg_probe(ugeth))
2000 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2001 return -EINVAL;
2002 }
2003
2004 /* Generate uccm_mask for receive */
2005 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2006 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++)
2007 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2008
2009 for (i = 0; i < ucc_geth_tx_queues(info: ug_info); i++)
2010 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2011 /* Initialize the general fast UCC block. */
2012 if (ucc_fast_init(uf_info, uccf_ret: &ugeth->uccf)) {
2013 if (netif_msg_probe(ugeth))
2014 pr_err("Failed to init uccf\n");
2015 return -ENOMEM;
2016 }
2017
2018 /* read the number of risc engines, update the riscTx and riscRx
2019 * if there are 4 riscs in QE
2020 */
2021 if (qe_get_num_of_risc() == 4) {
2022 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2023 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2024 }
2025
2026 ugeth->ug_regs = ioremap(offset: uf_info->regs, size: sizeof(*ugeth->ug_regs));
2027 if (!ugeth->ug_regs) {
2028 if (netif_msg_probe(ugeth))
2029 pr_err("Failed to ioremap regs\n");
2030 return -ENOMEM;
2031 }
2032
2033 return 0;
2034}
2035
2036static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2037{
2038 struct ucc_geth_info *ug_info;
2039 struct ucc_fast_info *uf_info;
2040 int length;
2041 u16 i, j;
2042 u8 __iomem *bd;
2043
2044 ug_info = ugeth->ug_info;
2045 uf_info = &ug_info->uf_info;
2046
2047 /* Allocate Tx bds */
2048 for (j = 0; j < ucc_geth_tx_queues(info: ug_info); j++) {
2049 u32 align = max(UCC_GETH_TX_BD_RING_ALIGNMENT,
2050 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT);
2051 u32 alloc;
2052
2053 length = ug_info->bdRingLenTx[j] * sizeof(struct qe_bd);
2054 alloc = round_up(length, align);
2055 alloc = roundup_pow_of_two(alloc);
2056
2057 ugeth->p_tx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL);
2058
2059 if (!ugeth->p_tx_bd_ring[j]) {
2060 if (netif_msg_ifup(ugeth))
2061 pr_err("Can not allocate memory for Tx bd rings\n");
2062 return -ENOMEM;
2063 }
2064 /* Zero unused end of bd ring, according to spec */
2065 memset(ugeth->p_tx_bd_ring[j] + length, 0, alloc - length);
2066 }
2067
2068 /* Init Tx bds */
2069 for (j = 0; j < ucc_geth_tx_queues(info: ug_info); j++) {
2070 /* Setup the skbuff rings */
2071 ugeth->tx_skbuff[j] =
2072 kcalloc(ugeth->ug_info->bdRingLenTx[j],
2073 sizeof(struct sk_buff *), GFP_KERNEL);
2074
2075 if (ugeth->tx_skbuff[j] == NULL) {
2076 if (netif_msg_ifup(ugeth))
2077 pr_err("Could not allocate tx_skbuff\n");
2078 return -ENOMEM;
2079 }
2080
2081 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2082 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2083 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2084 /* clear bd buffer */
2085 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2086 /* set bd status and length */
2087 out_be32((u32 __iomem *)bd, 0);
2088 bd += sizeof(struct qe_bd);
2089 }
2090 bd -= sizeof(struct qe_bd);
2091 /* set bd status and length */
2092 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2093 }
2094
2095 return 0;
2096}
2097
2098static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2099{
2100 struct ucc_geth_info *ug_info;
2101 struct ucc_fast_info *uf_info;
2102 int length;
2103 u16 i, j;
2104 u8 __iomem *bd;
2105
2106 ug_info = ugeth->ug_info;
2107 uf_info = &ug_info->uf_info;
2108
2109 /* Allocate Rx bds */
2110 for (j = 0; j < ucc_geth_rx_queues(info: ug_info); j++) {
2111 u32 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2112 u32 alloc;
2113
2114 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2115 alloc = round_up(length, align);
2116 alloc = roundup_pow_of_two(alloc);
2117
2118 ugeth->p_rx_bd_ring[j] = kmalloc(alloc, GFP_KERNEL);
2119 if (!ugeth->p_rx_bd_ring[j]) {
2120 if (netif_msg_ifup(ugeth))
2121 pr_err("Can not allocate memory for Rx bd rings\n");
2122 return -ENOMEM;
2123 }
2124 }
2125
2126 /* Init Rx bds */
2127 for (j = 0; j < ucc_geth_rx_queues(info: ug_info); j++) {
2128 /* Setup the skbuff rings */
2129 ugeth->rx_skbuff[j] =
2130 kcalloc(ugeth->ug_info->bdRingLenRx[j],
2131 sizeof(struct sk_buff *), GFP_KERNEL);
2132
2133 if (ugeth->rx_skbuff[j] == NULL) {
2134 if (netif_msg_ifup(ugeth))
2135 pr_err("Could not allocate rx_skbuff\n");
2136 return -ENOMEM;
2137 }
2138
2139 ugeth->skb_currx[j] = 0;
2140 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2141 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2142 /* set bd status and length */
2143 out_be32((u32 __iomem *)bd, R_I);
2144 /* clear bd buffer */
2145 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2146 bd += sizeof(struct qe_bd);
2147 }
2148 bd -= sizeof(struct qe_bd);
2149 /* set bd status and length */
2150 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2151 }
2152
2153 return 0;
2154}
2155
2156static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2157{
2158 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2159 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2160 struct ucc_fast_private *uccf;
2161 struct ucc_geth_info *ug_info;
2162 struct ucc_fast_info *uf_info;
2163 struct ucc_fast __iomem *uf_regs;
2164 struct ucc_geth __iomem *ug_regs;
2165 int ret_val = -EINVAL;
2166 u32 remoder = UCC_GETH_REMODER_INIT;
2167 u32 init_enet_pram_offset, cecr_subblock, command;
2168 u32 ifstat, i, j, size, l2qt, l3qt;
2169 u16 temoder = UCC_GETH_TEMODER_INIT;
2170 u8 function_code = 0;
2171 u8 __iomem *endOfRing;
2172 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2173 s32 rx_glbl_pram_offset, tx_glbl_pram_offset;
2174
2175 ugeth_vdbg("%s: IN", __func__);
2176 uccf = ugeth->uccf;
2177 ug_info = ugeth->ug_info;
2178 uf_info = &ug_info->uf_info;
2179 uf_regs = uccf->uf_regs;
2180 ug_regs = ugeth->ug_regs;
2181
2182 numThreadsRxNumerical = ucc_geth_thread_count(idx: ug_info->numThreadsRx);
2183 if (!numThreadsRxNumerical) {
2184 if (netif_msg_ifup(ugeth))
2185 pr_err("Bad number of Rx threads value\n");
2186 return -EINVAL;
2187 }
2188
2189 numThreadsTxNumerical = ucc_geth_thread_count(idx: ug_info->numThreadsTx);
2190 if (!numThreadsTxNumerical) {
2191 if (netif_msg_ifup(ugeth))
2192 pr_err("Bad number of Tx threads value\n");
2193 return -EINVAL;
2194 }
2195
2196 /* Calculate rx_extended_features */
2197 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2198 ug_info->ipAddressAlignment ||
2199 (ug_info->numStationAddresses !=
2200 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2201
2202 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2203 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2204 (ug_info->vlanOperationNonTagged !=
2205 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2206
2207 init_default_reg_vals(upsmr_register: &uf_regs->upsmr,
2208 maccfg1_register: &ug_regs->maccfg1, maccfg2_register: &ug_regs->maccfg2);
2209
2210 /* Set UPSMR */
2211 /* For more details see the hardware spec. */
2212 init_rx_parameters(reject_broadcast: ug_info->bro,
2213 receive_short_frames: ug_info->rsh, promiscuous: ug_info->pro, upsmr_register: &uf_regs->upsmr);
2214
2215 /* We're going to ignore other registers for now, */
2216 /* except as needed to get up and running */
2217
2218 /* Set MACCFG1 */
2219 /* For more details see the hardware spec. */
2220 init_flow_control_params(automatic_flow_control_mode: ug_info->aufc,
2221 rx_flow_control_enable: ug_info->receiveFlowControl,
2222 tx_flow_control_enable: ug_info->transmitFlowControl,
2223 pause_period: ug_info->pausePeriod,
2224 extension_field: ug_info->extensionField,
2225 upsmr_register: &uf_regs->upsmr,
2226 uempr_register: &ug_regs->uempr, maccfg1_register: &ug_regs->maccfg1);
2227
2228 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2229
2230 /* Set IPGIFG */
2231 /* For more details see the hardware spec. */
2232 ret_val = init_inter_frame_gap_params(non_btb_cs_ipg: ug_info->nonBackToBackIfgPart1,
2233 non_btb_ipg: ug_info->nonBackToBackIfgPart2,
2234 min_ifg: ug_info->
2235 miminumInterFrameGapEnforcement,
2236 btb_ipg: ug_info->backToBackInterFrameGap,
2237 ipgifg_register: &ug_regs->ipgifg);
2238 if (ret_val != 0) {
2239 if (netif_msg_ifup(ugeth))
2240 pr_err("IPGIFG initialization parameter too large\n");
2241 return ret_val;
2242 }
2243
2244 /* Set HAFDUP */
2245 /* For more details see the hardware spec. */
2246 ret_val = init_half_duplex_params(alt_beb: ug_info->altBeb,
2247 back_pressure_no_backoff: ug_info->backPressureNoBackoff,
2248 no_backoff: ug_info->noBackoff,
2249 excess_defer: ug_info->excessDefer,
2250 alt_beb_truncation: ug_info->altBebTruncation,
2251 max_retransmissions: ug_info->maxRetransmission,
2252 collision_window: ug_info->collisionWindow,
2253 hafdup_register: &ug_regs->hafdup);
2254 if (ret_val != 0) {
2255 if (netif_msg_ifup(ugeth))
2256 pr_err("Half Duplex initialization parameter too large\n");
2257 return ret_val;
2258 }
2259
2260 /* Set IFSTAT */
2261 /* For more details see the hardware spec. */
2262 /* Read only - resets upon read */
2263 ifstat = in_be32(&ug_regs->ifstat);
2264
2265 /* Clear UEMPR */
2266 /* For more details see the hardware spec. */
2267 out_be32(&ug_regs->uempr, 0);
2268
2269 /* Set UESCR */
2270 /* For more details see the hardware spec. */
2271 init_hw_statistics_gathering_mode(enable_hardware_statistics: (ug_info->statisticsMode &
2272 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2273 auto_zero_hardware_statistics: 0, upsmr_register: &uf_regs->upsmr, uescr_register: &ug_regs->uescr);
2274
2275 ret_val = ucc_geth_alloc_tx(ugeth);
2276 if (ret_val != 0)
2277 return ret_val;
2278
2279 ret_val = ucc_geth_alloc_rx(ugeth);
2280 if (ret_val != 0)
2281 return ret_val;
2282
2283 /*
2284 * Global PRAM
2285 */
2286 /* Tx global PRAM */
2287 /* Allocate global tx parameter RAM page */
2288 tx_glbl_pram_offset =
2289 qe_muram_alloc(size: sizeof(struct ucc_geth_tx_global_pram),
2290 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2291 if (tx_glbl_pram_offset < 0) {
2292 if (netif_msg_ifup(ugeth))
2293 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2294 return -ENOMEM;
2295 }
2296 ugeth->p_tx_glbl_pram = qe_muram_addr(offset: tx_glbl_pram_offset);
2297 /* Fill global PRAM */
2298
2299 /* TQPTR */
2300 /* Size varies with number of Tx threads */
2301 ugeth->thread_dat_tx_offset =
2302 qe_muram_alloc(size: numThreadsTxNumerical *
2303 sizeof(struct ucc_geth_thread_data_tx) +
2304 32 * (numThreadsTxNumerical == 1),
2305 UCC_GETH_THREAD_DATA_ALIGNMENT);
2306 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2307 if (netif_msg_ifup(ugeth))
2308 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2309 return -ENOMEM;
2310 }
2311
2312 ugeth->p_thread_data_tx =
2313 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(offset: ugeth->
2314 thread_dat_tx_offset);
2315 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2316
2317 /* vtagtable */
2318 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2319 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2320 ug_info->vtagtable[i]);
2321
2322 /* iphoffset */
2323 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2324 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2325 ug_info->iphoffset[i]);
2326
2327 /* SQPTR */
2328 /* Size varies with number of Tx queues */
2329 ugeth->send_q_mem_reg_offset =
2330 qe_muram_alloc(size: ucc_geth_tx_queues(info: ug_info) *
2331 sizeof(struct ucc_geth_send_queue_qd),
2332 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2333 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2334 if (netif_msg_ifup(ugeth))
2335 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2336 return -ENOMEM;
2337 }
2338
2339 ugeth->p_send_q_mem_reg =
2340 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(offset: ugeth->
2341 send_q_mem_reg_offset);
2342 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2343
2344 /* Setup the table */
2345 /* Assume BD rings are already established */
2346 for (i = 0; i < ucc_geth_tx_queues(info: ug_info); i++) {
2347 endOfRing =
2348 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2349 1) * sizeof(struct qe_bd);
2350 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2351 (u32) virt_to_phys(address: ugeth->p_tx_bd_ring[i]));
2352 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2353 last_bd_completed_address,
2354 (u32) virt_to_phys(address: endOfRing));
2355 }
2356
2357 /* schedulerbasepointer */
2358
2359 if (ucc_geth_tx_queues(info: ug_info) > 1) {
2360 /* scheduler exists only if more than 1 tx queue */
2361 ugeth->scheduler_offset =
2362 qe_muram_alloc(size: sizeof(struct ucc_geth_scheduler),
2363 UCC_GETH_SCHEDULER_ALIGNMENT);
2364 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2365 if (netif_msg_ifup(ugeth))
2366 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2367 return -ENOMEM;
2368 }
2369
2370 ugeth->p_scheduler =
2371 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(offset: ugeth->
2372 scheduler_offset);
2373 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2374 ugeth->scheduler_offset);
2375
2376 /* Set values in scheduler */
2377 out_be32(&ugeth->p_scheduler->mblinterval,
2378 ug_info->mblinterval);
2379 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2380 ug_info->nortsrbytetime);
2381 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2382 out_8(&ugeth->p_scheduler->strictpriorityq,
2383 ug_info->strictpriorityq);
2384 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2385 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2386 for (i = 0; i < NUM_TX_QUEUES; i++)
2387 out_8(&ugeth->p_scheduler->weightfactor[i],
2388 ug_info->weightfactor[i]);
2389
2390 /* Set pointers to cpucount registers in scheduler */
2391 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2392 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2393 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2394 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2395 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2396 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2397 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2398 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2399 }
2400
2401 /* schedulerbasepointer */
2402 /* TxRMON_PTR (statistics) */
2403 if (ug_info->
2404 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2405 ugeth->tx_fw_statistics_pram_offset =
2406 qe_muram_alloc(size: sizeof
2407 (struct ucc_geth_tx_firmware_statistics_pram),
2408 UCC_GETH_TX_STATISTICS_ALIGNMENT);
2409 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2410 if (netif_msg_ifup(ugeth))
2411 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2412 return -ENOMEM;
2413 }
2414 ugeth->p_tx_fw_statistics_pram =
2415 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2416 qe_muram_addr(offset: ugeth->tx_fw_statistics_pram_offset);
2417 }
2418
2419 /* temoder */
2420 /* Already has speed set */
2421
2422 if (ucc_geth_tx_queues(info: ug_info) > 1)
2423 temoder |= TEMODER_SCHEDULER_ENABLE;
2424 if (ug_info->ipCheckSumGenerate)
2425 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2426 temoder |= ((ucc_geth_tx_queues(info: ug_info) - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2427 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2428
2429 /* Function code register value to be used later */
2430 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2431 /* Required for QE */
2432
2433 /* function code register */
2434 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2435
2436 /* Rx global PRAM */
2437 /* Allocate global rx parameter RAM page */
2438 rx_glbl_pram_offset =
2439 qe_muram_alloc(size: sizeof(struct ucc_geth_rx_global_pram),
2440 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2441 if (rx_glbl_pram_offset < 0) {
2442 if (netif_msg_ifup(ugeth))
2443 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2444 return -ENOMEM;
2445 }
2446 ugeth->p_rx_glbl_pram = qe_muram_addr(offset: rx_glbl_pram_offset);
2447 /* Fill global PRAM */
2448
2449 /* RQPTR */
2450 /* Size varies with number of Rx threads */
2451 ugeth->thread_dat_rx_offset =
2452 qe_muram_alloc(size: numThreadsRxNumerical *
2453 sizeof(struct ucc_geth_thread_data_rx),
2454 UCC_GETH_THREAD_DATA_ALIGNMENT);
2455 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2456 if (netif_msg_ifup(ugeth))
2457 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2458 return -ENOMEM;
2459 }
2460
2461 ugeth->p_thread_data_rx =
2462 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(offset: ugeth->
2463 thread_dat_rx_offset);
2464 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2465
2466 /* typeorlen */
2467 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2468
2469 /* rxrmonbaseptr (statistics) */
2470 if (ug_info->
2471 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2472 ugeth->rx_fw_statistics_pram_offset =
2473 qe_muram_alloc(size: sizeof
2474 (struct ucc_geth_rx_firmware_statistics_pram),
2475 UCC_GETH_RX_STATISTICS_ALIGNMENT);
2476 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2477 if (netif_msg_ifup(ugeth))
2478 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2479 return -ENOMEM;
2480 }
2481 ugeth->p_rx_fw_statistics_pram =
2482 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2483 qe_muram_addr(offset: ugeth->rx_fw_statistics_pram_offset);
2484 }
2485
2486 /* intCoalescingPtr */
2487
2488 /* Size varies with number of Rx queues */
2489 ugeth->rx_irq_coalescing_tbl_offset =
2490 qe_muram_alloc(size: ucc_geth_rx_queues(info: ug_info) *
2491 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2492 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2493 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2494 if (netif_msg_ifup(ugeth))
2495 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2496 return -ENOMEM;
2497 }
2498
2499 ugeth->p_rx_irq_coalescing_tbl =
2500 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2501 qe_muram_addr(offset: ugeth->rx_irq_coalescing_tbl_offset);
2502 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2503 ugeth->rx_irq_coalescing_tbl_offset);
2504
2505 /* Fill interrupt coalescing table */
2506 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++) {
2507 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2508 interruptcoalescingmaxvalue,
2509 ug_info->interruptcoalescingmaxvalue[i]);
2510 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2511 interruptcoalescingcounter,
2512 ug_info->interruptcoalescingmaxvalue[i]);
2513 }
2514
2515 /* MRBLR */
2516 init_max_rx_buff_len(max_rx_buf_len: uf_info->max_rx_buf_length,
2517 mrblr_register: &ugeth->p_rx_glbl_pram->mrblr);
2518 /* MFLR */
2519 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2520 /* MINFLR */
2521 init_min_frame_len(min_frame_length: ug_info->minFrameLength,
2522 minflr_register: &ugeth->p_rx_glbl_pram->minflr,
2523 mrblr_register: &ugeth->p_rx_glbl_pram->mrblr);
2524 /* MAXD1 */
2525 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2526 /* MAXD2 */
2527 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2528
2529 /* l2qt */
2530 l2qt = 0;
2531 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2532 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2533 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2534
2535 /* l3qt */
2536 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2537 l3qt = 0;
2538 for (i = 0; i < 8; i++)
2539 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2540 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2541 }
2542
2543 /* vlantype */
2544 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2545
2546 /* vlantci */
2547 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2548
2549 /* ecamptr */
2550 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2551
2552 /* RBDQPTR */
2553 /* Size varies with number of Rx queues */
2554 ugeth->rx_bd_qs_tbl_offset =
2555 qe_muram_alloc(size: ucc_geth_rx_queues(info: ug_info) *
2556 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2557 sizeof(struct ucc_geth_rx_prefetched_bds)),
2558 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2559 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2560 if (netif_msg_ifup(ugeth))
2561 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2562 return -ENOMEM;
2563 }
2564
2565 ugeth->p_rx_bd_qs_tbl =
2566 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(offset: ugeth->
2567 rx_bd_qs_tbl_offset);
2568 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2569
2570 /* Setup the table */
2571 /* Assume BD rings are already established */
2572 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++) {
2573 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2574 (u32) virt_to_phys(address: ugeth->p_rx_bd_ring[i]));
2575 /* rest of fields handled by QE */
2576 }
2577
2578 /* remoder */
2579 /* Already has speed set */
2580
2581 if (ugeth->rx_extended_features)
2582 remoder |= REMODER_RX_EXTENDED_FEATURES;
2583 if (ug_info->rxExtendedFiltering)
2584 remoder |= REMODER_RX_EXTENDED_FILTERING;
2585 if (ug_info->dynamicMaxFrameLength)
2586 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2587 if (ug_info->dynamicMinFrameLength)
2588 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2589 remoder |=
2590 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2591 remoder |=
2592 ug_info->
2593 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2594 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2595 remoder |= ((ucc_geth_rx_queues(info: ug_info) - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2596 if (ug_info->ipCheckSumCheck)
2597 remoder |= REMODER_IP_CHECKSUM_CHECK;
2598 if (ug_info->ipAddressAlignment)
2599 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2600 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2601
2602 /* Note that this function must be called */
2603 /* ONLY AFTER p_tx_fw_statistics_pram */
2604 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2605 init_firmware_statistics_gathering_mode(enable_tx_firmware_statistics: (ug_info->
2606 statisticsMode &
2607 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2608 enable_rx_firmware_statistics: (ug_info->statisticsMode &
2609 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2610 tx_rmon_base_ptr: &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2611 tx_firmware_statistics_structure_address: ugeth->tx_fw_statistics_pram_offset,
2612 rx_rmon_base_ptr: &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2613 rx_firmware_statistics_structure_address: ugeth->rx_fw_statistics_pram_offset,
2614 temoder_register: &ugeth->p_tx_glbl_pram->temoder,
2615 remoder_register: &ugeth->p_rx_glbl_pram->remoder);
2616
2617 /* function code register */
2618 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2619
2620 /* initialize extended filtering */
2621 if (ug_info->rxExtendedFiltering) {
2622 if (!ug_info->extendedFilteringChainPointer) {
2623 if (netif_msg_ifup(ugeth))
2624 pr_err("Null Extended Filtering Chain Pointer\n");
2625 return -EINVAL;
2626 }
2627
2628 /* Allocate memory for extended filtering Mode Global
2629 Parameters */
2630 ugeth->exf_glbl_param_offset =
2631 qe_muram_alloc(size: sizeof(struct ucc_geth_exf_global_pram),
2632 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2633 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2634 if (netif_msg_ifup(ugeth))
2635 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2636 return -ENOMEM;
2637 }
2638
2639 ugeth->p_exf_glbl_param =
2640 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(offset: ugeth->
2641 exf_glbl_param_offset);
2642 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2643 ugeth->exf_glbl_param_offset);
2644 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2645 (u32) ug_info->extendedFilteringChainPointer);
2646
2647 } else { /* initialize 82xx style address filtering */
2648
2649 /* Init individual address recognition registers to disabled */
2650
2651 for (j = 0; j < NUM_OF_PADDRS; j++)
2652 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, paddr_num: (u8) j);
2653
2654 p_82xx_addr_filt =
2655 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2656 p_rx_glbl_pram->addressfiltering;
2657
2658 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2659 enet_addr_type: ENET_ADDR_TYPE_GROUP);
2660 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2661 enet_addr_type: ENET_ADDR_TYPE_INDIVIDUAL);
2662 }
2663
2664 /*
2665 * Initialize UCC at QE level
2666 */
2667
2668 command = QE_INIT_TX_RX;
2669
2670 /* Allocate shadow InitEnet command parameter structure.
2671 * This is needed because after the InitEnet command is executed,
2672 * the structure in DPRAM is released, because DPRAM is a premium
2673 * resource.
2674 * This shadow structure keeps a copy of what was done so that the
2675 * allocated resources can be released when the channel is freed.
2676 */
2677 if (!(ugeth->p_init_enet_param_shadow =
2678 kzalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2679 if (netif_msg_ifup(ugeth))
2680 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2681 return -ENOMEM;
2682 }
2683
2684 /* Fill shadow InitEnet command parameter structure */
2685
2686 ugeth->p_init_enet_param_shadow->resinit1 =
2687 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2688 ugeth->p_init_enet_param_shadow->resinit2 =
2689 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2690 ugeth->p_init_enet_param_shadow->resinit3 =
2691 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2692 ugeth->p_init_enet_param_shadow->resinit4 =
2693 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2694 ugeth->p_init_enet_param_shadow->resinit5 =
2695 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2696 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2697 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2698 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2699 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2700
2701 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2702 rx_glbl_pram_offset | ug_info->riscRx;
2703 if ((ug_info->largestexternallookupkeysize !=
2704 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2705 (ug_info->largestexternallookupkeysize !=
2706 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2707 (ug_info->largestexternallookupkeysize !=
2708 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2709 if (netif_msg_ifup(ugeth))
2710 pr_err("Invalid largest External Lookup Key Size\n");
2711 return -EINVAL;
2712 }
2713 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2714 ug_info->largestexternallookupkeysize;
2715 size = sizeof(struct ucc_geth_thread_rx_pram);
2716 if (ug_info->rxExtendedFiltering) {
2717 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2718 if (ug_info->largestexternallookupkeysize ==
2719 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2720 size +=
2721 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2722 if (ug_info->largestexternallookupkeysize ==
2723 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2724 size +=
2725 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2726 }
2727
2728 if ((ret_val = fill_init_enet_entries(ugeth, p_start: &(ugeth->
2729 p_init_enet_param_shadow->rxthread[0]),
2730 num_entries: (u8) (numThreadsRxNumerical + 1)
2731 /* Rx needs one extra for terminator */
2732 , thread_size: size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2733 risc: ug_info->riscRx, skip_page_for_first_entry: 1)) != 0) {
2734 if (netif_msg_ifup(ugeth))
2735 pr_err("Can not fill p_init_enet_param_shadow\n");
2736 return ret_val;
2737 }
2738
2739 ugeth->p_init_enet_param_shadow->txglobal =
2740 tx_glbl_pram_offset | ug_info->riscTx;
2741 if ((ret_val =
2742 fill_init_enet_entries(ugeth,
2743 p_start: &(ugeth->p_init_enet_param_shadow->
2744 txthread[0]), num_entries: numThreadsTxNumerical,
2745 thread_size: sizeof(struct ucc_geth_thread_tx_pram),
2746 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
2747 risc: ug_info->riscTx, skip_page_for_first_entry: 0)) != 0) {
2748 if (netif_msg_ifup(ugeth))
2749 pr_err("Can not fill p_init_enet_param_shadow\n");
2750 return ret_val;
2751 }
2752
2753 /* Load Rx bds with buffers */
2754 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++) {
2755 if ((ret_val = rx_bd_buffer_set(ugeth, rxQ: (u8) i)) != 0) {
2756 if (netif_msg_ifup(ugeth))
2757 pr_err("Can not fill Rx bds with buffers\n");
2758 return ret_val;
2759 }
2760 }
2761
2762 /* Allocate InitEnet command parameter structure */
2763 init_enet_pram_offset = qe_muram_alloc(size: sizeof(struct ucc_geth_init_pram), align: 4);
2764 if (IS_ERR_VALUE(init_enet_pram_offset)) {
2765 if (netif_msg_ifup(ugeth))
2766 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
2767 return -ENOMEM;
2768 }
2769 p_init_enet_pram =
2770 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(offset: init_enet_pram_offset);
2771
2772 /* Copy shadow InitEnet command parameter structure into PRAM */
2773 out_8(&p_init_enet_pram->resinit1,
2774 ugeth->p_init_enet_param_shadow->resinit1);
2775 out_8(&p_init_enet_pram->resinit2,
2776 ugeth->p_init_enet_param_shadow->resinit2);
2777 out_8(&p_init_enet_pram->resinit3,
2778 ugeth->p_init_enet_param_shadow->resinit3);
2779 out_8(&p_init_enet_pram->resinit4,
2780 ugeth->p_init_enet_param_shadow->resinit4);
2781 out_be16(&p_init_enet_pram->resinit5,
2782 ugeth->p_init_enet_param_shadow->resinit5);
2783 out_8(&p_init_enet_pram->largestexternallookupkeysize,
2784 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
2785 out_be32(&p_init_enet_pram->rgftgfrxglobal,
2786 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
2787 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
2788 out_be32(&p_init_enet_pram->rxthread[i],
2789 ugeth->p_init_enet_param_shadow->rxthread[i]);
2790 out_be32(&p_init_enet_pram->txglobal,
2791 ugeth->p_init_enet_param_shadow->txglobal);
2792 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
2793 out_be32(&p_init_enet_pram->txthread[i],
2794 ugeth->p_init_enet_param_shadow->txthread[i]);
2795
2796 /* Issue QE command */
2797 cecr_subblock =
2798 ucc_fast_get_qe_cr_subblock(uccf_num: ugeth->ug_info->uf_info.ucc_num);
2799 qe_issue_cmd(cmd: command, device: cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
2800 cmd_input: init_enet_pram_offset);
2801
2802 /* Free InitEnet command parameter */
2803 qe_muram_free(offset: init_enet_pram_offset);
2804
2805 return 0;
2806}
2807
2808/* This is called by the kernel when a frame is ready for transmission. */
2809/* It is pointed to by the dev->hard_start_xmit function pointer */
2810static netdev_tx_t
2811ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
2812{
2813 struct ucc_geth_private *ugeth = netdev_priv(dev);
2814#ifdef CONFIG_UGETH_TX_ON_DEMAND
2815 struct ucc_fast_private *uccf;
2816#endif
2817 u8 __iomem *bd; /* BD pointer */
2818 u32 bd_status;
2819 u8 txQ = 0;
2820 unsigned long flags;
2821
2822 ugeth_vdbg("%s: IN", __func__);
2823
2824 netdev_sent_queue(dev, bytes: skb->len);
2825 spin_lock_irqsave(&ugeth->lock, flags);
2826
2827 dev->stats.tx_bytes += skb->len;
2828
2829 /* Start from the next BD that should be filled */
2830 bd = ugeth->txBd[txQ];
2831 bd_status = in_be32((u32 __iomem *)bd);
2832 /* Save the skb pointer so we can free it later */
2833 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
2834
2835 /* Update the current skb pointer (wrapping if this was the last) */
2836 ugeth->skb_curtx[txQ] =
2837 (ugeth->skb_curtx[txQ] +
2838 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
2839
2840 /* set up the buffer descriptor */
2841 out_be32(&((struct qe_bd __iomem *)bd)->buf,
2842 dma_map_single(ugeth->dev, skb->data,
2843 skb->len, DMA_TO_DEVICE));
2844
2845 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
2846
2847 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
2848
2849 /* set bd status and length */
2850 out_be32((u32 __iomem *)bd, bd_status);
2851
2852 /* Move to next BD in the ring */
2853 if (!(bd_status & T_W))
2854 bd += sizeof(struct qe_bd);
2855 else
2856 bd = ugeth->p_tx_bd_ring[txQ];
2857
2858 /* If the next BD still needs to be cleaned up, then the bds
2859 are full. We need to tell the kernel to stop sending us stuff. */
2860 if (bd == ugeth->confBd[txQ]) {
2861 if (!netif_queue_stopped(dev))
2862 netif_stop_queue(dev);
2863 }
2864
2865 ugeth->txBd[txQ] = bd;
2866
2867 skb_tx_timestamp(skb);
2868
2869 if (ugeth->p_scheduler) {
2870 ugeth->cpucount[txQ]++;
2871 /* Indicate to QE that there are more Tx bds ready for
2872 transmission */
2873 /* This is done by writing a running counter of the bd
2874 count to the scheduler PRAM. */
2875 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
2876 }
2877
2878#ifdef CONFIG_UGETH_TX_ON_DEMAND
2879 uccf = ugeth->uccf;
2880 out_be16(uccf->p_utodr, UCC_FAST_TOD);
2881#endif
2882 spin_unlock_irqrestore(lock: &ugeth->lock, flags);
2883
2884 return NETDEV_TX_OK;
2885}
2886
2887static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
2888{
2889 struct sk_buff *skb;
2890 u8 __iomem *bd;
2891 u16 length, howmany = 0;
2892 u32 bd_status;
2893 u8 *bdBuffer;
2894 struct net_device *dev;
2895
2896 ugeth_vdbg("%s: IN", __func__);
2897
2898 dev = ugeth->ndev;
2899
2900 /* collect received buffers */
2901 bd = ugeth->rxBd[rxQ];
2902
2903 bd_status = in_be32((u32 __iomem *)bd);
2904
2905 /* while there are received buffers and BD is full (~R_E) */
2906 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
2907 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
2908 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
2909 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
2910
2911 /* determine whether buffer is first, last, first and last
2912 (single buffer frame) or middle (not first and not last) */
2913 if (!skb ||
2914 (!(bd_status & (R_F | R_L))) ||
2915 (bd_status & R_ERRORS_FATAL)) {
2916 if (netif_msg_rx_err(ugeth))
2917 pr_err("%d: ERROR!!! skb - 0x%08x\n",
2918 __LINE__, (u32)skb);
2919 dev_kfree_skb(skb);
2920
2921 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
2922 dev->stats.rx_dropped++;
2923 } else {
2924 dev->stats.rx_packets++;
2925 howmany++;
2926
2927 /* Prep the skb for the packet */
2928 skb_put(skb, len: length);
2929
2930 /* Tell the skb what kind of packet this is */
2931 skb->protocol = eth_type_trans(skb, dev: ugeth->ndev);
2932
2933 dev->stats.rx_bytes += length;
2934 /* Send the packet up the stack */
2935 netif_receive_skb(skb);
2936 }
2937
2938 skb = get_new_skb(ugeth, bd);
2939 if (!skb) {
2940 if (netif_msg_rx_err(ugeth))
2941 pr_warn("No Rx Data Buffer\n");
2942 dev->stats.rx_dropped++;
2943 break;
2944 }
2945
2946 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
2947
2948 /* update to point at the next skb */
2949 ugeth->skb_currx[rxQ] =
2950 (ugeth->skb_currx[rxQ] +
2951 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
2952
2953 if (bd_status & R_W)
2954 bd = ugeth->p_rx_bd_ring[rxQ];
2955 else
2956 bd += sizeof(struct qe_bd);
2957
2958 bd_status = in_be32((u32 __iomem *)bd);
2959 }
2960
2961 ugeth->rxBd[rxQ] = bd;
2962 return howmany;
2963}
2964
2965static int ucc_geth_tx(struct net_device *dev, u8 txQ)
2966{
2967 /* Start from the next BD that should be filled */
2968 struct ucc_geth_private *ugeth = netdev_priv(dev);
2969 unsigned int bytes_sent = 0;
2970 int howmany = 0;
2971 u8 __iomem *bd; /* BD pointer */
2972 u32 bd_status;
2973
2974 bd = ugeth->confBd[txQ];
2975 bd_status = in_be32((u32 __iomem *)bd);
2976
2977 /* Normal processing. */
2978 while ((bd_status & T_R) == 0) {
2979 struct sk_buff *skb;
2980
2981 /* BD contains already transmitted buffer. */
2982 /* Handle the transmitted buffer and release */
2983 /* the BD to be used with the current frame */
2984
2985 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
2986 if (!skb)
2987 break;
2988 howmany++;
2989 bytes_sent += skb->len;
2990 dev->stats.tx_packets++;
2991
2992 dev_consume_skb_any(skb);
2993
2994 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
2995 ugeth->skb_dirtytx[txQ] =
2996 (ugeth->skb_dirtytx[txQ] +
2997 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
2998
2999 /* We freed a buffer, so now we can restart transmission */
3000 if (netif_queue_stopped(dev))
3001 netif_wake_queue(dev);
3002
3003 /* Advance the confirmation BD pointer */
3004 if (!(bd_status & T_W))
3005 bd += sizeof(struct qe_bd);
3006 else
3007 bd = ugeth->p_tx_bd_ring[txQ];
3008 bd_status = in_be32((u32 __iomem *)bd);
3009 }
3010 ugeth->confBd[txQ] = bd;
3011 netdev_completed_queue(dev, pkts: howmany, bytes: bytes_sent);
3012 return 0;
3013}
3014
3015static int ucc_geth_poll(struct napi_struct *napi, int budget)
3016{
3017 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3018 struct ucc_geth_info *ug_info;
3019 int howmany, i;
3020
3021 ug_info = ugeth->ug_info;
3022
3023 /* Tx event processing */
3024 spin_lock(lock: &ugeth->lock);
3025 for (i = 0; i < ucc_geth_tx_queues(info: ug_info); i++)
3026 ucc_geth_tx(dev: ugeth->ndev, txQ: i);
3027 spin_unlock(lock: &ugeth->lock);
3028
3029 howmany = 0;
3030 for (i = 0; i < ucc_geth_rx_queues(info: ug_info); i++)
3031 howmany += ucc_geth_rx(ugeth, rxQ: i, rx_work_limit: budget - howmany);
3032
3033 if (howmany < budget) {
3034 napi_complete_done(n: napi, work_done: howmany);
3035 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3036 }
3037
3038 return howmany;
3039}
3040
3041static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3042{
3043 struct net_device *dev = info;
3044 struct ucc_geth_private *ugeth = netdev_priv(dev);
3045 struct ucc_fast_private *uccf;
3046 struct ucc_geth_info *ug_info;
3047 register u32 ucce;
3048 register u32 uccm;
3049
3050 ugeth_vdbg("%s: IN", __func__);
3051
3052 uccf = ugeth->uccf;
3053 ug_info = ugeth->ug_info;
3054
3055 /* read and clear events */
3056 ucce = (u32) in_be32(uccf->p_ucce);
3057 uccm = (u32) in_be32(uccf->p_uccm);
3058 ucce &= uccm;
3059 out_be32(uccf->p_ucce, ucce);
3060
3061 /* check for receive events that require processing */
3062 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3063 if (napi_schedule_prep(n: &ugeth->napi)) {
3064 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3065 out_be32(uccf->p_uccm, uccm);
3066 __napi_schedule(n: &ugeth->napi);
3067 }
3068 }
3069
3070 /* Errors and other events */
3071 if (ucce & UCCE_OTHER) {
3072 if (ucce & UCC_GETH_UCCE_BSY)
3073 dev->stats.rx_errors++;
3074 if (ucce & UCC_GETH_UCCE_TXE)
3075 dev->stats.tx_errors++;
3076 }
3077
3078 return IRQ_HANDLED;
3079}
3080
3081#ifdef CONFIG_NET_POLL_CONTROLLER
3082/*
3083 * Polling 'interrupt' - used by things like netconsole to send skbs
3084 * without having to re-enable interrupts. It's not called while
3085 * the interrupt routine is executing.
3086 */
3087static void ucc_netpoll(struct net_device *dev)
3088{
3089 struct ucc_geth_private *ugeth = netdev_priv(dev);
3090 int irq = ugeth->ug_info->uf_info.irq;
3091
3092 disable_irq(irq);
3093 ucc_geth_irq_handler(irq, info: dev);
3094 enable_irq(irq);
3095}
3096#endif /* CONFIG_NET_POLL_CONTROLLER */
3097
3098static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3099{
3100 struct ucc_geth_private *ugeth = netdev_priv(dev);
3101 struct sockaddr *addr = p;
3102
3103 if (!is_valid_ether_addr(addr: addr->sa_data))
3104 return -EADDRNOTAVAIL;
3105
3106 eth_hw_addr_set(dev, addr: addr->sa_data);
3107
3108 /*
3109 * If device is not running, we will set mac addr register
3110 * when opening the device.
3111 */
3112 if (!netif_running(dev))
3113 return 0;
3114
3115 spin_lock_irq(lock: &ugeth->lock);
3116 init_mac_station_addr_regs(address_byte_0: dev->dev_addr[0],
3117 address_byte_1: dev->dev_addr[1],
3118 address_byte_2: dev->dev_addr[2],
3119 address_byte_3: dev->dev_addr[3],
3120 address_byte_4: dev->dev_addr[4],
3121 address_byte_5: dev->dev_addr[5],
3122 macstnaddr1_register: &ugeth->ug_regs->macstnaddr1,
3123 macstnaddr2_register: &ugeth->ug_regs->macstnaddr2);
3124 spin_unlock_irq(lock: &ugeth->lock);
3125
3126 return 0;
3127}
3128
3129static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3130{
3131 struct net_device *dev = ugeth->ndev;
3132 int err;
3133
3134 err = ucc_struct_init(ugeth);
3135 if (err) {
3136 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3137 goto err;
3138 }
3139
3140 err = ucc_geth_startup(ugeth);
3141 if (err) {
3142 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3143 goto err;
3144 }
3145
3146 /* Set MACSTNADDR1, MACSTNADDR2 */
3147 /* For more details see the hardware spec. */
3148 init_mac_station_addr_regs(address_byte_0: dev->dev_addr[0],
3149 address_byte_1: dev->dev_addr[1],
3150 address_byte_2: dev->dev_addr[2],
3151 address_byte_3: dev->dev_addr[3],
3152 address_byte_4: dev->dev_addr[4],
3153 address_byte_5: dev->dev_addr[5],
3154 macstnaddr1_register: &ugeth->ug_regs->macstnaddr1,
3155 macstnaddr2_register: &ugeth->ug_regs->macstnaddr2);
3156
3157 return 0;
3158err:
3159 ucc_geth_stop(ugeth);
3160 return err;
3161}
3162
3163/* Called when something needs to use the ethernet device */
3164/* Returns 0 for success. */
3165static int ucc_geth_open(struct net_device *dev)
3166{
3167 struct ucc_geth_private *ugeth = netdev_priv(dev);
3168 int err;
3169
3170 ugeth_vdbg("%s: IN", __func__);
3171
3172 /* Test station address */
3173 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3174 netif_err(ugeth, ifup, dev,
3175 "Multicast address used for station address - is this what you wanted?\n");
3176 return -EINVAL;
3177 }
3178
3179 err = phylink_of_phy_connect(ugeth->phylink, ugeth->dev->of_node, flags: 0);
3180 if (err) {
3181 dev_err(&dev->dev, "Could not attach to PHY\n");
3182 return -ENODEV;
3183 }
3184
3185 err = ucc_geth_init_mac(ugeth);
3186 if (err) {
3187 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3188 goto err;
3189 }
3190
3191 err = request_irq(irq: ugeth->ug_info->uf_info.irq, handler: ucc_geth_irq_handler,
3192 flags: 0, name: "UCC Geth", dev);
3193 if (err) {
3194 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3195 goto err;
3196 }
3197
3198 phylink_start(ugeth->phylink);
3199 napi_enable(n: &ugeth->napi);
3200 netdev_reset_queue(dev_queue: dev);
3201 netif_start_queue(dev);
3202
3203 device_set_wakeup_capable(dev: &dev->dev,
3204 capable: qe_alive_during_sleep() || dev->phydev->irq);
3205 device_set_wakeup_enable(dev: &dev->dev, enable: ugeth->wol_en);
3206
3207 return err;
3208
3209err:
3210 ucc_geth_stop(ugeth);
3211 return err;
3212}
3213
3214/* Stops the kernel queue, and halts the controller */
3215static int ucc_geth_close(struct net_device *dev)
3216{
3217 struct ucc_geth_private *ugeth = netdev_priv(dev);
3218
3219 ugeth_vdbg("%s: IN", __func__);
3220
3221 napi_disable(n: &ugeth->napi);
3222
3223 cancel_work_sync(work: &ugeth->timeout_work);
3224 ucc_geth_stop(ugeth);
3225 phylink_disconnect_phy(ugeth->phylink);
3226
3227 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3228
3229 netif_stop_queue(dev);
3230 netdev_reset_queue(dev_queue: dev);
3231
3232 return 0;
3233}
3234
3235/* Reopen device. This will reset the MAC and PHY. */
3236static void ucc_geth_timeout_work(struct work_struct *work)
3237{
3238 struct ucc_geth_private *ugeth;
3239 struct net_device *dev;
3240
3241 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3242 dev = ugeth->ndev;
3243
3244 ugeth_vdbg("%s: IN", __func__);
3245
3246 dev->stats.tx_errors++;
3247
3248 ugeth_dump_regs(ugeth);
3249
3250 if (dev->flags & IFF_UP) {
3251 /*
3252 * Must reset MAC *and* PHY. This is done by reopening
3253 * the device.
3254 */
3255 netif_tx_stop_all_queues(dev);
3256 ucc_geth_stop(ugeth);
3257 ucc_geth_init_mac(ugeth);
3258 /* Must start PHY here */
3259 phylink_start(ugeth->phylink);
3260 netif_tx_start_all_queues(dev);
3261 }
3262
3263 netif_tx_schedule_all(dev);
3264}
3265
3266/*
3267 * ucc_geth_timeout gets called when a packet has not been
3268 * transmitted after a set amount of time.
3269 */
3270static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue)
3271{
3272 struct ucc_geth_private *ugeth = netdev_priv(dev);
3273
3274 schedule_work(work: &ugeth->timeout_work);
3275}
3276
3277
3278#ifdef CONFIG_PM
3279
3280static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3281{
3282 struct net_device *ndev = platform_get_drvdata(pdev: ofdev);
3283 struct ucc_geth_private *ugeth = netdev_priv(dev: ndev);
3284 bool mac_wol = false;
3285
3286 if (!netif_running(dev: ndev))
3287 return 0;
3288
3289 netif_device_detach(dev: ndev);
3290 napi_disable(n: &ugeth->napi);
3291
3292 /*
3293 * Disable the controller, otherwise we'll wakeup on any network
3294 * activity.
3295 */
3296 ugeth_disable(ugeth, mode: COMM_DIR_RX_AND_TX);
3297
3298 if (ugeth->wol_en & WAKE_MAGIC && !ugeth->phy_wol_en) {
3299 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3300 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3301 ucc_fast_enable(uccf: ugeth->uccf, mode: COMM_DIR_RX_AND_TX);
3302 mac_wol = true;
3303 }
3304
3305 rtnl_lock();
3306 phylink_suspend(pl: ugeth->phylink, mac_wol);
3307 rtnl_unlock();
3308
3309 return 0;
3310}
3311
3312static int ucc_geth_resume(struct platform_device *ofdev)
3313{
3314 struct net_device *ndev = platform_get_drvdata(pdev: ofdev);
3315 struct ucc_geth_private *ugeth = netdev_priv(dev: ndev);
3316 int err;
3317
3318 if (!netif_running(dev: ndev))
3319 return 0;
3320
3321 if (qe_alive_during_sleep()) {
3322 if (ugeth->wol_en & WAKE_MAGIC) {
3323 ucc_fast_disable(uccf: ugeth->uccf, mode: COMM_DIR_RX_AND_TX);
3324 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3325 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3326 }
3327 ugeth_enable(ugeth, mode: COMM_DIR_RX_AND_TX);
3328 } else {
3329 /*
3330 * Full reinitialization is required if QE shuts down
3331 * during sleep.
3332 */
3333 ucc_geth_memclean(ugeth);
3334
3335 err = ucc_geth_init_mac(ugeth);
3336 if (err) {
3337 netdev_err(dev: ndev, format: "Cannot initialize MAC, aborting\n");
3338 return err;
3339 }
3340 }
3341
3342 rtnl_lock();
3343 phylink_resume(pl: ugeth->phylink);
3344 rtnl_unlock();
3345
3346 napi_enable(n: &ugeth->napi);
3347 netif_device_attach(dev: ndev);
3348
3349 return 0;
3350}
3351
3352#else
3353#define ucc_geth_suspend NULL
3354#define ucc_geth_resume NULL
3355#endif
3356
3357static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3358{
3359 struct ucc_geth_private *ugeth = netdev_priv(dev);
3360
3361 if (!netif_running(dev))
3362 return -EINVAL;
3363
3364 return phylink_mii_ioctl(ugeth->phylink, rq, cmd);
3365}
3366
3367static const struct net_device_ops ucc_geth_netdev_ops = {
3368 .ndo_open = ucc_geth_open,
3369 .ndo_stop = ucc_geth_close,
3370 .ndo_start_xmit = ucc_geth_start_xmit,
3371 .ndo_validate_addr = eth_validate_addr,
3372 .ndo_set_mac_address = ucc_geth_set_mac_addr,
3373 .ndo_set_rx_mode = ucc_geth_set_multi,
3374 .ndo_tx_timeout = ucc_geth_timeout,
3375 .ndo_eth_ioctl = ucc_geth_ioctl,
3376#ifdef CONFIG_NET_POLL_CONTROLLER
3377 .ndo_poll_controller = ucc_netpoll,
3378#endif
3379};
3380
3381static int ucc_geth_parse_clock(struct device_node *np, const char *which,
3382 enum qe_clock *out)
3383{
3384 const char *sprop;
3385 char buf[24];
3386
3387 snprintf(buf, size: sizeof(buf), fmt: "%s-clock-name", which);
3388 sprop = of_get_property(node: np, name: buf, NULL);
3389 if (sprop) {
3390 *out = qe_clock_source(source: sprop);
3391 } else {
3392 u32 val;
3393
3394 snprintf(buf, size: sizeof(buf), fmt: "%s-clock", which);
3395 if (of_property_read_u32(np, propname: buf, out_value: &val)) {
3396 /* If both *-clock-name and *-clock are missing,
3397 * we want to tell people to use *-clock-name.
3398 */
3399 pr_err("missing %s-clock-name property\n", buf);
3400 return -EINVAL;
3401 }
3402 *out = val;
3403 }
3404 if (*out < QE_CLK_NONE || *out > QE_CLK24) {
3405 pr_err("invalid %s property\n", buf);
3406 return -EINVAL;
3407 }
3408 return 0;
3409}
3410
3411static const struct phylink_mac_ops ugeth_mac_ops = {
3412 .mac_link_up = ugeth_mac_link_up,
3413 .mac_link_down = ugeth_mac_link_down,
3414 .mac_config = ugeth_mac_config,
3415};
3416
3417static int ucc_geth_probe(struct platform_device* ofdev)
3418{
3419 struct device *device = &ofdev->dev;
3420 struct device_node *np = ofdev->dev.of_node;
3421 struct net_device *dev = NULL;
3422 struct ucc_geth_private *ugeth = NULL;
3423 struct ucc_geth_info *ug_info;
3424 struct device_node *phy_node;
3425 struct phylink *phylink;
3426 struct resource res;
3427 int err, ucc_num;
3428 const unsigned int *prop;
3429 phy_interface_t phy_interface;
3430
3431 ugeth_vdbg("%s: IN", __func__);
3432
3433 prop = of_get_property(node: np, name: "cell-index", NULL);
3434 if (!prop) {
3435 prop = of_get_property(node: np, name: "device-id", NULL);
3436 if (!prop)
3437 return -ENODEV;
3438 }
3439
3440 ucc_num = *prop - 1;
3441 if ((ucc_num < 0) || (ucc_num > 7))
3442 return -ENODEV;
3443
3444 ug_info = devm_kmemdup(dev: &ofdev->dev, src: &ugeth_primary_info,
3445 len: sizeof(*ug_info), GFP_KERNEL);
3446 if (!ug_info)
3447 return -ENOMEM;
3448
3449 ug_info->uf_info.ucc_num = ucc_num;
3450
3451 err = ucc_geth_parse_clock(np, which: "rx", out: &ug_info->uf_info.rx_clock);
3452 if (err)
3453 return err;
3454 err = ucc_geth_parse_clock(np, which: "tx", out: &ug_info->uf_info.tx_clock);
3455 if (err)
3456 return err;
3457
3458 err = of_address_to_resource(dev: np, index: 0, r: &res);
3459 if (err)
3460 return err;
3461
3462 ug_info->uf_info.regs = res.start;
3463 ug_info->uf_info.irq = irq_of_parse_and_map(node: np, index: 0);
3464
3465 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3466 ug_info->tbi_node = of_parse_phandle(np, phandle_name: "tbi-handle", index: 0);
3467
3468 phy_node = of_parse_phandle(np, phandle_name: "phy-handle", index: 0);
3469 if (phy_node) {
3470 prop = of_get_property(node: phy_node, name: "interface", NULL);
3471 if (prop) {
3472 dev_err(&ofdev->dev,
3473 "Device-tree property 'interface' is no longer supported. Please use 'phy-connection-type' instead.");
3474 of_node_put(node: phy_node);
3475 err = -EINVAL;
3476 goto err_put_tbi;
3477 }
3478 of_node_put(node: phy_node);
3479 }
3480
3481 err = of_get_phy_mode(np, interface: &phy_interface);
3482 if (err) {
3483 dev_err(&ofdev->dev, "Invalid phy-connection-type");
3484 goto err_put_tbi;
3485 }
3486
3487 if (phy_interface == PHY_INTERFACE_MODE_GMII ||
3488 phy_interface_mode_is_rgmii(mode: phy_interface) ||
3489 phy_interface == PHY_INTERFACE_MODE_TBI ||
3490 phy_interface == PHY_INTERFACE_MODE_RTBI ||
3491 phy_interface == PHY_INTERFACE_MODE_SGMII) {
3492 unsigned int snums = qe_get_num_of_snums();
3493
3494 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3495 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3496 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3497 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3498 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3499 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3500 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3501
3502 /* If QE's snum number is 46/76 which means we need to support
3503 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3504 * more Threads to Rx.
3505 */
3506 if ((snums == 76) || (snums == 46))
3507 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3508 else
3509 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3510 }
3511
3512 if (netif_msg_probe(&debug))
3513 pr_info("UCC%1d at 0x%8llx (irq = %d)\n",
3514 ug_info->uf_info.ucc_num + 1,
3515 (u64)ug_info->uf_info.regs,
3516 ug_info->uf_info.irq);
3517
3518 /* Create an ethernet device instance */
3519 dev = devm_alloc_etherdev(&ofdev->dev, sizeof(*ugeth));
3520 if (!dev) {
3521 err = -ENOMEM;
3522 goto err_put_tbi;
3523 }
3524
3525 ugeth = netdev_priv(dev);
3526 spin_lock_init(&ugeth->lock);
3527
3528 /* Create CQs for hash tables */
3529 INIT_LIST_HEAD(list: &ugeth->group_hash_q);
3530 INIT_LIST_HEAD(list: &ugeth->ind_hash_q);
3531
3532 dev_set_drvdata(dev: device, data: dev);
3533
3534 /* Set the dev->base_addr to the gfar reg region */
3535 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3536
3537 SET_NETDEV_DEV(dev, device);
3538
3539 /* Fill in the dev structure */
3540 uec_set_ethtool_ops(netdev: dev);
3541 dev->netdev_ops = &ucc_geth_netdev_ops;
3542 dev->watchdog_timeo = TX_TIMEOUT;
3543 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3544 netif_napi_add(dev, napi: &ugeth->napi, poll: ucc_geth_poll);
3545 dev->mtu = 1500;
3546 dev->max_mtu = 1518;
3547
3548 ugeth->msg_enable = netif_msg_init(debug_value: debug.msg_enable, UGETH_MSG_DEFAULT);
3549
3550 ugeth->phylink_config.dev = &dev->dev;
3551 ugeth->phylink_config.type = PHYLINK_NETDEV;
3552
3553 ugeth->phylink_config.mac_capabilities =
3554 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;
3555
3556 __set_bit(PHY_INTERFACE_MODE_MII,
3557 ugeth->phylink_config.supported_interfaces);
3558 __set_bit(PHY_INTERFACE_MODE_RMII,
3559 ugeth->phylink_config.supported_interfaces);
3560 __set_bit(PHY_INTERFACE_MODE_GMII,
3561 ugeth->phylink_config.supported_interfaces);
3562 phy_interface_set_rgmii(intf: ugeth->phylink_config.supported_interfaces);
3563
3564 if (ug_info->tbi_node) {
3565 __set_bit(PHY_INTERFACE_MODE_SGMII,
3566 ugeth->phylink_config.supported_interfaces);
3567 __set_bit(PHY_INTERFACE_MODE_TBI,
3568 ugeth->phylink_config.supported_interfaces);
3569 __set_bit(PHY_INTERFACE_MODE_RTBI,
3570 ugeth->phylink_config.supported_interfaces);
3571 }
3572
3573 phylink = phylink_create(&ugeth->phylink_config, dev_fwnode(&dev->dev),
3574 phy_interface, &ugeth_mac_ops);
3575 if (IS_ERR(ptr: phylink)) {
3576 err = PTR_ERR(ptr: phylink);
3577 goto err_put_tbi;
3578 }
3579
3580 ugeth->phylink = phylink;
3581
3582 err = devm_register_netdev(dev: &ofdev->dev, ndev: dev);
3583 if (err) {
3584 if (netif_msg_probe(ugeth))
3585 pr_err("%s: Cannot register net device, aborting\n",
3586 dev->name);
3587 goto err_destroy_phylink;
3588 }
3589
3590 err = of_get_ethdev_address(np, dev);
3591 if (err == -EPROBE_DEFER)
3592 goto err_destroy_phylink;
3593
3594 ugeth->ug_info = ug_info;
3595 ugeth->dev = device;
3596 ugeth->ndev = dev;
3597 ugeth->node = np;
3598
3599 return 0;
3600
3601err_destroy_phylink:
3602 phylink_destroy(phylink);
3603err_put_tbi:
3604 of_node_put(node: ug_info->tbi_node);
3605
3606 return err;
3607}
3608
3609static void ucc_geth_remove(struct platform_device* ofdev)
3610{
3611 struct net_device *dev = platform_get_drvdata(pdev: ofdev);
3612 struct ucc_geth_private *ugeth = netdev_priv(dev);
3613
3614 ucc_geth_memclean(ugeth);
3615 phylink_destroy(ugeth->phylink);
3616 of_node_put(node: ugeth->ug_info->tbi_node);
3617}
3618
3619static const struct of_device_id ucc_geth_match[] = {
3620 {
3621 .type = "network",
3622 .compatible = "ucc_geth",
3623 },
3624 {},
3625};
3626
3627MODULE_DEVICE_TABLE(of, ucc_geth_match);
3628
3629static struct platform_driver ucc_geth_driver = {
3630 .driver = {
3631 .name = DRV_NAME,
3632 .of_match_table = ucc_geth_match,
3633 },
3634 .probe = ucc_geth_probe,
3635 .remove = ucc_geth_remove,
3636 .suspend = ucc_geth_suspend,
3637 .resume = ucc_geth_resume,
3638};
3639
3640static int __init ucc_geth_init(void)
3641{
3642 if (netif_msg_drv(&debug))
3643 pr_info(DRV_DESC "\n");
3644
3645 return platform_driver_register(&ucc_geth_driver);
3646}
3647
3648static void __exit ucc_geth_exit(void)
3649{
3650 platform_driver_unregister(&ucc_geth_driver);
3651}
3652
3653module_init(ucc_geth_init);
3654module_exit(ucc_geth_exit);
3655
3656MODULE_AUTHOR("Freescale Semiconductor, Inc");
3657MODULE_DESCRIPTION(DRV_DESC);
3658MODULE_LICENSE("GPL");
3659

source code of linux/drivers/net/ethernet/freescale/ucc_geth.c