1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2019 Intel Corporation */
3
4#include "igc.h"
5
6#include <linux/module.h>
7#include <linux/device.h>
8#include <linux/pci.h>
9#include <linux/ptp_classify.h>
10#include <linux/clocksource.h>
11#include <linux/ktime.h>
12#include <linux/delay.h>
13#include <linux/iopoll.h>
14
15#define INCVALUE_MASK 0x7fffffff
16#define ISGN 0x80000000
17
18#define IGC_PTP_TX_TIMEOUT (HZ * 15)
19
20#define IGC_PTM_STAT_SLEEP 2
21#define IGC_PTM_STAT_TIMEOUT 100
22
23/* SYSTIM read access for I225 */
24void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
25{
26 struct igc_hw *hw = &adapter->hw;
27 u32 sec, nsec;
28
29 /* The timestamp is latched when SYSTIML is read. */
30 nsec = rd32(IGC_SYSTIML);
31 sec = rd32(IGC_SYSTIMH);
32
33 ts->tv_sec = sec;
34 ts->tv_nsec = nsec;
35}
36
37static void igc_ptp_write_i225(struct igc_adapter *adapter,
38 const struct timespec64 *ts)
39{
40 struct igc_hw *hw = &adapter->hw;
41
42 wr32(IGC_SYSTIML, ts->tv_nsec);
43 wr32(IGC_SYSTIMH, ts->tv_sec);
44}
45
46static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
47{
48 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
49 ptp_caps);
50 struct igc_hw *hw = &igc->hw;
51 int neg_adj = 0;
52 u64 rate;
53 u32 inca;
54
55 if (scaled_ppm < 0) {
56 neg_adj = 1;
57 scaled_ppm = -scaled_ppm;
58 }
59 rate = scaled_ppm;
60 rate <<= 14;
61 rate = div_u64(dividend: rate, divisor: 78125);
62
63 inca = rate & INCVALUE_MASK;
64 if (neg_adj)
65 inca |= ISGN;
66
67 wr32(IGC_TIMINCA, inca);
68
69 return 0;
70}
71
72static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
73{
74 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
75 ptp_caps);
76 struct timespec64 now, then = ns_to_timespec64(nsec: delta);
77 unsigned long flags;
78
79 spin_lock_irqsave(&igc->tmreg_lock, flags);
80
81 igc_ptp_read(adapter: igc, ts: &now);
82 now = timespec64_add(lhs: now, rhs: then);
83 igc_ptp_write_i225(adapter: igc, ts: (const struct timespec64 *)&now);
84
85 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
86
87 return 0;
88}
89
90static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
91 struct timespec64 *ts,
92 struct ptp_system_timestamp *sts)
93{
94 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
95 ptp_caps);
96 struct igc_hw *hw = &igc->hw;
97 unsigned long flags;
98
99 spin_lock_irqsave(&igc->tmreg_lock, flags);
100
101 ptp_read_system_prets(sts);
102 ts->tv_nsec = rd32(IGC_SYSTIML);
103 ts->tv_sec = rd32(IGC_SYSTIMH);
104 ptp_read_system_postts(sts);
105
106 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
107
108 return 0;
109}
110
111static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
112 const struct timespec64 *ts)
113{
114 struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
115 ptp_caps);
116 unsigned long flags;
117
118 spin_lock_irqsave(&igc->tmreg_lock, flags);
119
120 igc_ptp_write_i225(adapter: igc, ts);
121
122 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
123
124 return 0;
125}
126
127static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
128{
129 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
130 static const u32 mask[IGC_N_SDP] = {
131 IGC_CTRL_SDP0_DIR,
132 IGC_CTRL_SDP1_DIR,
133 IGC_CTRL_EXT_SDP2_DIR,
134 IGC_CTRL_EXT_SDP3_DIR,
135 };
136
137 if (input)
138 *ptr &= ~mask[pin];
139 else
140 *ptr |= mask[pin];
141}
142
143static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
144{
145 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
146 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
147 };
148 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
149 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
150 };
151 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
152 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
153 };
154 static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
155 IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
156 IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
157 };
158 static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
159 IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
160 IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
161 };
162 static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
163 IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
164 IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
165 };
166 static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
167 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
168 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
169 };
170 static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
171 IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
172 IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
173 };
174 struct igc_hw *hw = &igc->hw;
175 u32 ctrl, ctrl_ext, tssdp = 0;
176
177 ctrl = rd32(IGC_CTRL);
178 ctrl_ext = rd32(IGC_CTRL_EXT);
179 tssdp = rd32(IGC_TSSDP);
180
181 igc_pin_direction(pin, input: 0, ctrl: &ctrl, ctrl_ext: &ctrl_ext);
182
183 /* Make sure this pin is not enabled as an input. */
184 if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
185 tssdp &= ~IGC_AUX0_TS_SDP_EN;
186
187 if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
188 tssdp &= ~IGC_AUX1_TS_SDP_EN;
189
190 tssdp &= ~igc_ts_sdp_sel_clr[pin];
191 if (freq) {
192 if (chan == 1)
193 tssdp |= igc_ts_sdp_sel_fc1[pin];
194 else
195 tssdp |= igc_ts_sdp_sel_fc0[pin];
196 } else {
197 if (chan == 1)
198 tssdp |= igc_ts_sdp_sel_tt1[pin];
199 else
200 tssdp |= igc_ts_sdp_sel_tt0[pin];
201 }
202 tssdp |= igc_ts_sdp_en[pin];
203
204 wr32(IGC_TSSDP, tssdp);
205 wr32(IGC_CTRL, ctrl);
206 wr32(IGC_CTRL_EXT, ctrl_ext);
207}
208
209static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
210{
211 static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
212 IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
213 };
214 static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
215 IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
216 };
217 static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
218 IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
219 };
220 struct igc_hw *hw = &igc->hw;
221 u32 ctrl, ctrl_ext, tssdp = 0;
222
223 ctrl = rd32(IGC_CTRL);
224 ctrl_ext = rd32(IGC_CTRL_EXT);
225 tssdp = rd32(IGC_TSSDP);
226
227 igc_pin_direction(pin, input: 1, ctrl: &ctrl, ctrl_ext: &ctrl_ext);
228
229 /* Make sure this pin is not enabled as an output. */
230 tssdp &= ~igc_ts_sdp_en[pin];
231
232 if (chan == 1) {
233 tssdp &= ~IGC_AUX1_SEL_SDP3;
234 tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
235 } else {
236 tssdp &= ~IGC_AUX0_SEL_SDP3;
237 tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
238 }
239
240 wr32(IGC_TSSDP, tssdp);
241 wr32(IGC_CTRL, ctrl);
242 wr32(IGC_CTRL_EXT, ctrl_ext);
243}
244
245static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
246 struct ptp_clock_request *rq, int on)
247{
248 struct igc_adapter *igc =
249 container_of(ptp, struct igc_adapter, ptp_caps);
250 struct igc_hw *hw = &igc->hw;
251 unsigned long flags;
252 struct timespec64 ts;
253 int use_freq = 0, pin = -1;
254 u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
255 s64 ns;
256
257 switch (rq->type) {
258 case PTP_CLK_REQ_EXTTS:
259 /* Reject requests with unsupported flags */
260 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
261 PTP_RISING_EDGE |
262 PTP_FALLING_EDGE |
263 PTP_STRICT_FLAGS))
264 return -EOPNOTSUPP;
265
266 /* Reject requests failing to enable both edges. */
267 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
268 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
269 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
270 return -EOPNOTSUPP;
271
272 if (on) {
273 pin = ptp_find_pin(ptp: igc->ptp_clock, func: PTP_PF_EXTTS,
274 chan: rq->extts.index);
275 if (pin < 0)
276 return -EBUSY;
277 }
278 if (rq->extts.index == 1) {
279 tsauxc_mask = IGC_TSAUXC_EN_TS1;
280 tsim_mask = IGC_TSICR_AUTT1;
281 } else {
282 tsauxc_mask = IGC_TSAUXC_EN_TS0;
283 tsim_mask = IGC_TSICR_AUTT0;
284 }
285 spin_lock_irqsave(&igc->tmreg_lock, flags);
286 tsauxc = rd32(IGC_TSAUXC);
287 tsim = rd32(IGC_TSIM);
288 if (on) {
289 igc_pin_extts(igc, chan: rq->extts.index, pin);
290 tsauxc |= tsauxc_mask;
291 tsim |= tsim_mask;
292 } else {
293 tsauxc &= ~tsauxc_mask;
294 tsim &= ~tsim_mask;
295 }
296 wr32(IGC_TSAUXC, tsauxc);
297 wr32(IGC_TSIM, tsim);
298 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
299 return 0;
300
301 case PTP_CLK_REQ_PEROUT:
302 /* Reject requests with unsupported flags */
303 if (rq->perout.flags)
304 return -EOPNOTSUPP;
305
306 if (on) {
307 pin = ptp_find_pin(ptp: igc->ptp_clock, func: PTP_PF_PEROUT,
308 chan: rq->perout.index);
309 if (pin < 0)
310 return -EBUSY;
311 }
312 ts.tv_sec = rq->perout.period.sec;
313 ts.tv_nsec = rq->perout.period.nsec;
314 ns = timespec64_to_ns(ts: &ts);
315 ns = ns >> 1;
316 if (on && (ns <= 70000000LL || ns == 125000000LL ||
317 ns == 250000000LL || ns == 500000000LL)) {
318 if (ns < 8LL)
319 return -EINVAL;
320 use_freq = 1;
321 }
322 ts = ns_to_timespec64(nsec: ns);
323 if (rq->perout.index == 1) {
324 if (use_freq) {
325 tsauxc_mask = IGC_TSAUXC_EN_CLK1 | IGC_TSAUXC_ST1;
326 tsim_mask = 0;
327 } else {
328 tsauxc_mask = IGC_TSAUXC_EN_TT1;
329 tsim_mask = IGC_TSICR_TT1;
330 }
331 trgttiml = IGC_TRGTTIML1;
332 trgttimh = IGC_TRGTTIMH1;
333 freqout = IGC_FREQOUT1;
334 } else {
335 if (use_freq) {
336 tsauxc_mask = IGC_TSAUXC_EN_CLK0 | IGC_TSAUXC_ST0;
337 tsim_mask = 0;
338 } else {
339 tsauxc_mask = IGC_TSAUXC_EN_TT0;
340 tsim_mask = IGC_TSICR_TT0;
341 }
342 trgttiml = IGC_TRGTTIML0;
343 trgttimh = IGC_TRGTTIMH0;
344 freqout = IGC_FREQOUT0;
345 }
346 spin_lock_irqsave(&igc->tmreg_lock, flags);
347 tsauxc = rd32(IGC_TSAUXC);
348 tsim = rd32(IGC_TSIM);
349 if (rq->perout.index == 1) {
350 tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1 |
351 IGC_TSAUXC_ST1);
352 tsim &= ~IGC_TSICR_TT1;
353 } else {
354 tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0 |
355 IGC_TSAUXC_ST0);
356 tsim &= ~IGC_TSICR_TT0;
357 }
358 if (on) {
359 struct timespec64 safe_start;
360 int i = rq->perout.index;
361
362 igc_pin_perout(igc, chan: i, pin, freq: use_freq);
363 igc_ptp_read(adapter: igc, ts: &safe_start);
364
365 /* PPS output start time is triggered by Target time(TT)
366 * register. Programming any past time value into TT
367 * register will cause PPS to never start. Need to make
368 * sure we program the TT register a time ahead in
369 * future. There isn't a stringent need to fire PPS out
370 * right away. Adding +2 seconds should take care of
371 * corner cases. Let's say if the SYSTIML is close to
372 * wrap up and the timer keeps ticking as we program the
373 * register, adding +2seconds is safe bet.
374 */
375 safe_start.tv_sec += 2;
376
377 if (rq->perout.start.sec < safe_start.tv_sec)
378 igc->perout[i].start.tv_sec = safe_start.tv_sec;
379 else
380 igc->perout[i].start.tv_sec = rq->perout.start.sec;
381 igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
382 igc->perout[i].period.tv_sec = ts.tv_sec;
383 igc->perout[i].period.tv_nsec = ts.tv_nsec;
384 wr32(trgttimh, (u32)igc->perout[i].start.tv_sec);
385 /* For now, always select timer 0 as source. */
386 wr32(trgttiml, (u32)(igc->perout[i].start.tv_nsec |
387 IGC_TT_IO_TIMER_SEL_SYSTIM0));
388 if (use_freq)
389 wr32(freqout, ns);
390 tsauxc |= tsauxc_mask;
391 tsim |= tsim_mask;
392 }
393 wr32(IGC_TSAUXC, tsauxc);
394 wr32(IGC_TSIM, tsim);
395 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
396 return 0;
397
398 case PTP_CLK_REQ_PPS:
399 spin_lock_irqsave(&igc->tmreg_lock, flags);
400 tsim = rd32(IGC_TSIM);
401 if (on)
402 tsim |= IGC_TSICR_SYS_WRAP;
403 else
404 tsim &= ~IGC_TSICR_SYS_WRAP;
405 igc->pps_sys_wrap_on = on;
406 wr32(IGC_TSIM, tsim);
407 spin_unlock_irqrestore(lock: &igc->tmreg_lock, flags);
408 return 0;
409
410 default:
411 break;
412 }
413
414 return -EOPNOTSUPP;
415}
416
417static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
418 enum ptp_pin_function func, unsigned int chan)
419{
420 switch (func) {
421 case PTP_PF_NONE:
422 case PTP_PF_EXTTS:
423 case PTP_PF_PEROUT:
424 break;
425 case PTP_PF_PHYSYNC:
426 return -1;
427 }
428 return 0;
429}
430
431/**
432 * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
433 * @adapter: board private structure
434 * @hwtstamps: timestamp structure to update
435 * @systim: unsigned 64bit system time value
436 *
437 * We need to convert the system time value stored in the RX/TXSTMP registers
438 * into a hwtstamp which can be used by the upper level timestamping functions.
439 *
440 * Returns 0 on success.
441 **/
442static int igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
443 struct skb_shared_hwtstamps *hwtstamps,
444 u64 systim)
445{
446 switch (adapter->hw.mac.type) {
447 case igc_i225:
448 memset(hwtstamps, 0, sizeof(*hwtstamps));
449 /* Upper 32 bits contain s, lower 32 bits contain ns. */
450 hwtstamps->hwtstamp = ktime_set(secs: systim >> 32,
451 nsecs: systim & 0xFFFFFFFF);
452 break;
453 default:
454 return -EINVAL;
455 }
456 return 0;
457}
458
459/**
460 * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
461 * @adapter: Pointer to adapter the packet buffer belongs to
462 * @buf: Pointer to packet buffer
463 *
464 * This function retrieves the timestamp saved in the beginning of packet
465 * buffer. While two timestamps are available, one in timer0 reference and the
466 * other in timer1 reference, this function considers only the timestamp in
467 * timer0 reference.
468 *
469 * Returns timestamp value.
470 */
471ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
472{
473 ktime_t timestamp;
474 u32 secs, nsecs;
475 int adjust;
476
477 /* Timestamps are saved in little endian at the beginning of the packet
478 * buffer following the layout:
479 *
480 * DWORD: | 0 | 1 | 2 | 3 |
481 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
482 *
483 * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
484 * part of the timestamp.
485 */
486 nsecs = le32_to_cpu(buf[2]);
487 secs = le32_to_cpu(buf[3]);
488
489 timestamp = ktime_set(secs, nsecs);
490
491 /* Adjust timestamp for the RX latency based on link speed */
492 switch (adapter->link_speed) {
493 case SPEED_10:
494 adjust = IGC_I225_RX_LATENCY_10;
495 break;
496 case SPEED_100:
497 adjust = IGC_I225_RX_LATENCY_100;
498 break;
499 case SPEED_1000:
500 adjust = IGC_I225_RX_LATENCY_1000;
501 break;
502 case SPEED_2500:
503 adjust = IGC_I225_RX_LATENCY_2500;
504 break;
505 default:
506 adjust = 0;
507 netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
508 break;
509 }
510
511 return ktime_sub_ns(timestamp, adjust);
512}
513
514static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
515{
516 struct igc_hw *hw = &adapter->hw;
517 u32 val;
518 int i;
519
520 wr32(IGC_TSYNCRXCTL, 0);
521
522 for (i = 0; i < adapter->num_rx_queues; i++) {
523 val = rd32(IGC_SRRCTL(i));
524 val &= ~IGC_SRRCTL_TIMESTAMP;
525 wr32(IGC_SRRCTL(i), val);
526 }
527
528 val = rd32(IGC_RXPBS);
529 val &= ~IGC_RXPBS_CFG_TS_EN;
530 wr32(IGC_RXPBS, val);
531}
532
533static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
534{
535 struct igc_hw *hw = &adapter->hw;
536 u32 val;
537 int i;
538
539 val = rd32(IGC_RXPBS);
540 val |= IGC_RXPBS_CFG_TS_EN;
541 wr32(IGC_RXPBS, val);
542
543 for (i = 0; i < adapter->num_rx_queues; i++) {
544 val = rd32(IGC_SRRCTL(i));
545 /* FIXME: For now, only support retrieving RX timestamps from
546 * timer 0.
547 */
548 val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
549 IGC_SRRCTL_TIMESTAMP;
550 wr32(IGC_SRRCTL(i), val);
551 }
552
553 val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
554 IGC_TSYNCRXCTL_RXSYNSIG;
555 wr32(IGC_TSYNCRXCTL, val);
556}
557
558static void igc_ptp_clear_tx_tstamp(struct igc_adapter *adapter)
559{
560 unsigned long flags;
561 int i;
562
563 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
564
565 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
566 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
567
568 dev_kfree_skb_any(skb: tstamp->skb);
569 tstamp->skb = NULL;
570 }
571
572 spin_unlock_irqrestore(lock: &adapter->ptp_tx_lock, flags);
573}
574
575static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
576{
577 struct igc_hw *hw = &adapter->hw;
578 int i;
579
580 /* Clear the flags first to avoid new packets to be enqueued
581 * for TX timestamping.
582 */
583 for (i = 0; i < adapter->num_tx_queues; i++) {
584 struct igc_ring *tx_ring = adapter->tx_ring[i];
585
586 clear_bit(nr: IGC_RING_FLAG_TX_HWTSTAMP, addr: &tx_ring->flags);
587 }
588
589 /* Now we can clean the pending TX timestamp requests. */
590 igc_ptp_clear_tx_tstamp(adapter);
591
592 wr32(IGC_TSYNCTXCTL, 0);
593}
594
595static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
596{
597 struct igc_hw *hw = &adapter->hw;
598 int i;
599
600 wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
601
602 /* Read TXSTMP registers to discard any timestamp previously stored. */
603 rd32(IGC_TXSTMPL);
604 rd32(IGC_TXSTMPH);
605
606 /* The hardware is ready to accept TX timestamp requests,
607 * notify the transmit path.
608 */
609 for (i = 0; i < adapter->num_tx_queues; i++) {
610 struct igc_ring *tx_ring = adapter->tx_ring[i];
611
612 set_bit(nr: IGC_RING_FLAG_TX_HWTSTAMP, addr: &tx_ring->flags);
613 }
614
615}
616
617/**
618 * igc_ptp_set_timestamp_mode - setup hardware for timestamping
619 * @adapter: networking device structure
620 * @config: hwtstamp configuration
621 *
622 * Return: 0 in case of success, negative errno code otherwise.
623 */
624static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
625 struct hwtstamp_config *config)
626{
627 switch (config->tx_type) {
628 case HWTSTAMP_TX_OFF:
629 igc_ptp_disable_tx_timestamp(adapter);
630 break;
631 case HWTSTAMP_TX_ON:
632 igc_ptp_enable_tx_timestamp(adapter);
633 break;
634 default:
635 return -ERANGE;
636 }
637
638 switch (config->rx_filter) {
639 case HWTSTAMP_FILTER_NONE:
640 igc_ptp_disable_rx_timestamp(adapter);
641 break;
642 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
643 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
644 case HWTSTAMP_FILTER_PTP_V2_EVENT:
645 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
646 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
647 case HWTSTAMP_FILTER_PTP_V2_SYNC:
648 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
649 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
650 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
651 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
653 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
654 case HWTSTAMP_FILTER_NTP_ALL:
655 case HWTSTAMP_FILTER_ALL:
656 igc_ptp_enable_rx_timestamp(adapter);
657 config->rx_filter = HWTSTAMP_FILTER_ALL;
658 break;
659 default:
660 return -ERANGE;
661 }
662
663 return 0;
664}
665
666/* Requires adapter->ptp_tx_lock held by caller. */
667static void igc_ptp_tx_timeout(struct igc_adapter *adapter,
668 struct igc_tx_timestamp_request *tstamp)
669{
670 dev_kfree_skb_any(skb: tstamp->skb);
671 tstamp->skb = NULL;
672 adapter->tx_hwtstamp_timeouts++;
673
674 netdev_warn(dev: adapter->netdev, format: "Tx timestamp timeout\n");
675}
676
677void igc_ptp_tx_hang(struct igc_adapter *adapter)
678{
679 struct igc_tx_timestamp_request *tstamp;
680 struct igc_hw *hw = &adapter->hw;
681 unsigned long flags;
682 bool found = false;
683 int i;
684
685 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
686
687 for (i = 0; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
688 tstamp = &adapter->tx_tstamp[i];
689
690 if (!tstamp->skb)
691 continue;
692
693 if (time_is_after_jiffies(tstamp->start + IGC_PTP_TX_TIMEOUT))
694 continue;
695
696 igc_ptp_tx_timeout(adapter, tstamp);
697 found = true;
698 }
699
700 if (found) {
701 /* Reading the high register of the first set of timestamp registers
702 * clears all the equivalent bits in the TSYNCTXCTL register.
703 */
704 rd32(IGC_TXSTMPH_0);
705 }
706
707 spin_unlock_irqrestore(lock: &adapter->ptp_tx_lock, flags);
708}
709
710static void igc_ptp_tx_reg_to_stamp(struct igc_adapter *adapter,
711 struct igc_tx_timestamp_request *tstamp, u64 regval)
712{
713 struct skb_shared_hwtstamps shhwtstamps;
714 struct sk_buff *skb;
715 int adjust = 0;
716
717 skb = tstamp->skb;
718 if (!skb)
719 return;
720
721 if (igc_ptp_systim_to_hwtstamp(adapter, hwtstamps: &shhwtstamps, systim: regval))
722 return;
723
724 switch (adapter->link_speed) {
725 case SPEED_10:
726 adjust = IGC_I225_TX_LATENCY_10;
727 break;
728 case SPEED_100:
729 adjust = IGC_I225_TX_LATENCY_100;
730 break;
731 case SPEED_1000:
732 adjust = IGC_I225_TX_LATENCY_1000;
733 break;
734 case SPEED_2500:
735 adjust = IGC_I225_TX_LATENCY_2500;
736 break;
737 }
738
739 shhwtstamps.hwtstamp =
740 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
741
742 tstamp->skb = NULL;
743
744 skb_tstamp_tx(orig_skb: skb, hwtstamps: &shhwtstamps);
745 dev_kfree_skb_any(skb);
746}
747
748/**
749 * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
750 * @adapter: Board private structure
751 *
752 * Check against the ready mask for which of the timestamp register
753 * sets are ready to be retrieved, then retrieve that and notify the
754 * rest of the stack.
755 *
756 * Context: Expects adapter->ptp_tx_lock to be held by caller.
757 */
758static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
759{
760 struct igc_hw *hw = &adapter->hw;
761 u64 regval;
762 u32 mask;
763 int i;
764
765 mask = rd32(IGC_TSYNCTXCTL) & IGC_TSYNCTXCTL_TXTT_ANY;
766 if (mask & IGC_TSYNCTXCTL_TXTT_0) {
767 regval = rd32(IGC_TXSTMPL);
768 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
769 } else {
770 /* There's a bug in the hardware that could cause
771 * missing interrupts for TX timestamping. The issue
772 * is that for new interrupts to be triggered, the
773 * IGC_TXSTMPH_0 register must be read.
774 *
775 * To avoid discarding a valid timestamp that just
776 * happened at the "wrong" time, we need to confirm
777 * that there was no timestamp captured, we do that by
778 * assuming that no two timestamps in sequence have
779 * the same nanosecond value.
780 *
781 * So, we read the "low" register, read the "high"
782 * register (to latch a new timestamp) and read the
783 * "low" register again, if "old" and "new" versions
784 * of the "low" register are different, a valid
785 * timestamp was captured, we can read the "high"
786 * register again.
787 */
788 u32 txstmpl_old, txstmpl_new;
789
790 txstmpl_old = rd32(IGC_TXSTMPL);
791 rd32(IGC_TXSTMPH);
792 txstmpl_new = rd32(IGC_TXSTMPL);
793
794 if (txstmpl_old == txstmpl_new)
795 goto done;
796
797 regval = txstmpl_new;
798 regval |= (u64)rd32(IGC_TXSTMPH) << 32;
799 }
800
801 igc_ptp_tx_reg_to_stamp(adapter, tstamp: &adapter->tx_tstamp[0], regval);
802
803done:
804 /* Now that the problematic first register was handled, we can
805 * use retrieve the timestamps from the other registers
806 * (starting from '1') with less complications.
807 */
808 for (i = 1; i < IGC_MAX_TX_TSTAMP_REGS; i++) {
809 struct igc_tx_timestamp_request *tstamp = &adapter->tx_tstamp[i];
810
811 if (!(tstamp->mask & mask))
812 continue;
813
814 regval = rd32(tstamp->regl);
815 regval |= (u64)rd32(tstamp->regh) << 32;
816
817 igc_ptp_tx_reg_to_stamp(adapter, tstamp, regval);
818 }
819}
820
821/**
822 * igc_ptp_tx_tstamp_event
823 * @adapter: board private structure
824 *
825 * Called when a TX timestamp interrupt happens to retrieve the
826 * timestamp and send it up to the socket.
827 */
828void igc_ptp_tx_tstamp_event(struct igc_adapter *adapter)
829{
830 unsigned long flags;
831
832 spin_lock_irqsave(&adapter->ptp_tx_lock, flags);
833
834 igc_ptp_tx_hwtstamp(adapter);
835
836 spin_unlock_irqrestore(lock: &adapter->ptp_tx_lock, flags);
837}
838
839/**
840 * igc_ptp_set_ts_config - set hardware time stamping config
841 * @netdev: network interface device structure
842 * @ifr: interface request data
843 *
844 **/
845int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
846{
847 struct igc_adapter *adapter = netdev_priv(dev: netdev);
848 struct hwtstamp_config config;
849 int err;
850
851 if (copy_from_user(to: &config, from: ifr->ifr_data, n: sizeof(config)))
852 return -EFAULT;
853
854 err = igc_ptp_set_timestamp_mode(adapter, config: &config);
855 if (err)
856 return err;
857
858 /* save these settings for future reference */
859 memcpy(&adapter->tstamp_config, &config,
860 sizeof(adapter->tstamp_config));
861
862 return copy_to_user(to: ifr->ifr_data, from: &config, n: sizeof(config)) ?
863 -EFAULT : 0;
864}
865
866/**
867 * igc_ptp_get_ts_config - get hardware time stamping config
868 * @netdev: network interface device structure
869 * @ifr: interface request data
870 *
871 * Get the hwtstamp_config settings to return to the user. Rather than attempt
872 * to deconstruct the settings from the registers, just return a shadow copy
873 * of the last known settings.
874 **/
875int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
876{
877 struct igc_adapter *adapter = netdev_priv(dev: netdev);
878 struct hwtstamp_config *config = &adapter->tstamp_config;
879
880 return copy_to_user(to: ifr->ifr_data, from: config, n: sizeof(*config)) ?
881 -EFAULT : 0;
882}
883
884/* The two conditions below must be met for cross timestamping via
885 * PCIe PTM:
886 *
887 * 1. We have an way to convert the timestamps in the PTM messages
888 * to something related to the system clocks (right now, only
889 * X86 systems with support for the Always Running Timer allow that);
890 *
891 * 2. We have PTM enabled in the path from the device to the PCIe root port.
892 */
893static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
894{
895 if (!IS_ENABLED(CONFIG_X86_TSC))
896 return false;
897
898 /* FIXME: it was noticed that enabling support for PCIe PTM in
899 * some i225-V models could cause lockups when bringing the
900 * interface up/down. There should be no downsides to
901 * disabling crosstimestamping support for i225-V, as it
902 * doesn't have any PTP support. That way we gain some time
903 * while root causing the issue.
904 */
905 if (adapter->pdev->device == IGC_DEV_ID_I225_V)
906 return false;
907
908 return pcie_ptm_enabled(dev: adapter->pdev);
909}
910
911static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
912{
913#if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
914 return convert_art_ns_to_tsc(art_ns: tstamp);
915#else
916 return (struct system_counterval_t) { };
917#endif
918}
919
920static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
921{
922 struct net_device *netdev = adapter->netdev;
923
924 switch (ptm_stat) {
925 case IGC_PTM_STAT_RET_ERR:
926 netdev_err(dev: netdev, format: "PTM Error: Root port timeout\n");
927 break;
928 case IGC_PTM_STAT_BAD_PTM_RES:
929 netdev_err(dev: netdev, format: "PTM Error: Bad response, PTM Response Data expected\n");
930 break;
931 case IGC_PTM_STAT_T4M1_OVFL:
932 netdev_err(dev: netdev, format: "PTM Error: T4 minus T1 overflow\n");
933 break;
934 case IGC_PTM_STAT_ADJUST_1ST:
935 netdev_err(dev: netdev, format: "PTM Error: 1588 timer adjusted during first PTM cycle\n");
936 break;
937 case IGC_PTM_STAT_ADJUST_CYC:
938 netdev_err(dev: netdev, format: "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
939 break;
940 default:
941 netdev_err(dev: netdev, format: "PTM Error: Unknown error (%#x)\n", ptm_stat);
942 break;
943 }
944}
945
946static int igc_phc_get_syncdevicetime(ktime_t *device,
947 struct system_counterval_t *system,
948 void *ctx)
949{
950 u32 stat, t2_curr_h, t2_curr_l, ctrl;
951 struct igc_adapter *adapter = ctx;
952 struct igc_hw *hw = &adapter->hw;
953 int err, count = 100;
954 ktime_t t1, t2_curr;
955
956 /* Get a snapshot of system clocks to use as historic value. */
957 ktime_get_snapshot(systime_snapshot: &adapter->snapshot);
958
959 do {
960 /* Doing this in a loop because in the event of a
961 * badly timed (ha!) system clock adjustment, we may
962 * get PTM errors from the PCI root, but these errors
963 * are transitory. Repeating the process returns valid
964 * data eventually.
965 */
966
967 /* To "manually" start the PTM cycle we need to clear and
968 * then set again the TRIG bit.
969 */
970 ctrl = rd32(IGC_PTM_CTRL);
971 ctrl &= ~IGC_PTM_CTRL_TRIG;
972 wr32(IGC_PTM_CTRL, ctrl);
973 ctrl |= IGC_PTM_CTRL_TRIG;
974 wr32(IGC_PTM_CTRL, ctrl);
975
976 /* The cycle only starts "for real" when software notifies
977 * that it has read the registers, this is done by setting
978 * VALID bit.
979 */
980 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
981
982 err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
983 stat, IGC_PTM_STAT_SLEEP,
984 IGC_PTM_STAT_TIMEOUT);
985 if (err < 0) {
986 netdev_err(dev: adapter->netdev, format: "Timeout reading IGC_PTM_STAT register\n");
987 return err;
988 }
989
990 if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
991 break;
992
993 if (stat & ~IGC_PTM_STAT_VALID) {
994 /* An error occurred, log it. */
995 igc_ptm_log_error(adapter, ptm_stat: stat);
996 /* The STAT register is write-1-to-clear (W1C),
997 * so write the previous error status to clear it.
998 */
999 wr32(IGC_PTM_STAT, stat);
1000 continue;
1001 }
1002 } while (--count);
1003
1004 if (!count) {
1005 netdev_err(dev: adapter->netdev, format: "Exceeded number of tries for PTM cycle\n");
1006 return -ETIMEDOUT;
1007 }
1008
1009 t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
1010
1011 t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
1012 t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
1013
1014 /* FIXME: When the register that tells the endianness of the
1015 * PTM registers are implemented, check them here and add the
1016 * appropriate conversion.
1017 */
1018 t2_curr_h = swab32(t2_curr_h);
1019
1020 t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
1021
1022 *device = t1;
1023 *system = igc_device_tstamp_to_system(tstamp: t2_curr);
1024
1025 return 0;
1026}
1027
1028static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
1029 struct system_device_crosststamp *cts)
1030{
1031 struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
1032 ptp_caps);
1033
1034 return get_device_system_crosststamp(get_time_fn: igc_phc_get_syncdevicetime,
1035 ctx: adapter, history: &adapter->snapshot, xtstamp: cts);
1036}
1037
1038/**
1039 * igc_ptp_init - Initialize PTP functionality
1040 * @adapter: Board private structure
1041 *
1042 * This function is called at device probe to initialize the PTP
1043 * functionality.
1044 */
1045void igc_ptp_init(struct igc_adapter *adapter)
1046{
1047 struct net_device *netdev = adapter->netdev;
1048 struct igc_tx_timestamp_request *tstamp;
1049 struct igc_hw *hw = &adapter->hw;
1050 int i;
1051
1052 tstamp = &adapter->tx_tstamp[0];
1053 tstamp->mask = IGC_TSYNCTXCTL_TXTT_0;
1054 tstamp->regl = IGC_TXSTMPL_0;
1055 tstamp->regh = IGC_TXSTMPH_0;
1056 tstamp->flags = 0;
1057
1058 tstamp = &adapter->tx_tstamp[1];
1059 tstamp->mask = IGC_TSYNCTXCTL_TXTT_1;
1060 tstamp->regl = IGC_TXSTMPL_1;
1061 tstamp->regh = IGC_TXSTMPH_1;
1062 tstamp->flags = IGC_TX_FLAGS_TSTAMP_1;
1063
1064 tstamp = &adapter->tx_tstamp[2];
1065 tstamp->mask = IGC_TSYNCTXCTL_TXTT_2;
1066 tstamp->regl = IGC_TXSTMPL_2;
1067 tstamp->regh = IGC_TXSTMPH_2;
1068 tstamp->flags = IGC_TX_FLAGS_TSTAMP_2;
1069
1070 tstamp = &adapter->tx_tstamp[3];
1071 tstamp->mask = IGC_TSYNCTXCTL_TXTT_3;
1072 tstamp->regl = IGC_TXSTMPL_3;
1073 tstamp->regh = IGC_TXSTMPH_3;
1074 tstamp->flags = IGC_TX_FLAGS_TSTAMP_3;
1075
1076 switch (hw->mac.type) {
1077 case igc_i225:
1078 for (i = 0; i < IGC_N_SDP; i++) {
1079 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1080
1081 snprintf(buf: ppd->name, size: sizeof(ppd->name), fmt: "SDP%d", i);
1082 ppd->index = i;
1083 ppd->func = PTP_PF_NONE;
1084 }
1085 snprintf(buf: adapter->ptp_caps.name, size: 16, fmt: "%pm", netdev->dev_addr);
1086 adapter->ptp_caps.owner = THIS_MODULE;
1087 adapter->ptp_caps.max_adj = 62499999;
1088 adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
1089 adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
1090 adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
1091 adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
1092 adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
1093 adapter->ptp_caps.pps = 1;
1094 adapter->ptp_caps.pin_config = adapter->sdp_config;
1095 adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
1096 adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
1097 adapter->ptp_caps.n_pins = IGC_N_SDP;
1098 adapter->ptp_caps.verify = igc_ptp_verify_pin;
1099
1100 if (!igc_is_crosststamp_supported(adapter))
1101 break;
1102
1103 adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
1104 break;
1105 default:
1106 adapter->ptp_clock = NULL;
1107 return;
1108 }
1109
1110 spin_lock_init(&adapter->ptp_tx_lock);
1111 spin_lock_init(&adapter->tmreg_lock);
1112
1113 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1114 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1115
1116 adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
1117 adapter->ptp_reset_start = ktime_get();
1118
1119 adapter->ptp_clock = ptp_clock_register(info: &adapter->ptp_caps,
1120 parent: &adapter->pdev->dev);
1121 if (IS_ERR(ptr: adapter->ptp_clock)) {
1122 adapter->ptp_clock = NULL;
1123 netdev_err(dev: netdev, format: "ptp_clock_register failed\n");
1124 } else if (adapter->ptp_clock) {
1125 netdev_info(dev: netdev, format: "PHC added\n");
1126 adapter->ptp_flags |= IGC_PTP_ENABLED;
1127 }
1128}
1129
1130static void igc_ptp_time_save(struct igc_adapter *adapter)
1131{
1132 igc_ptp_read(adapter, ts: &adapter->prev_ptp_time);
1133 adapter->ptp_reset_start = ktime_get();
1134}
1135
1136static void igc_ptp_time_restore(struct igc_adapter *adapter)
1137{
1138 struct timespec64 ts = adapter->prev_ptp_time;
1139 ktime_t delta;
1140
1141 delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
1142
1143 timespec64_add_ns(a: &ts, ns: ktime_to_ns(kt: delta));
1144
1145 igc_ptp_write_i225(adapter, ts: &ts);
1146}
1147
1148static void igc_ptm_stop(struct igc_adapter *adapter)
1149{
1150 struct igc_hw *hw = &adapter->hw;
1151 u32 ctrl;
1152
1153 ctrl = rd32(IGC_PTM_CTRL);
1154 ctrl &= ~IGC_PTM_CTRL_EN;
1155
1156 wr32(IGC_PTM_CTRL, ctrl);
1157}
1158
1159/**
1160 * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1161 * @adapter: Board private structure
1162 *
1163 * This function stops the overflow check work and PTP Tx timestamp work, and
1164 * will prepare the device for OS suspend.
1165 */
1166void igc_ptp_suspend(struct igc_adapter *adapter)
1167{
1168 if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1169 return;
1170
1171 igc_ptp_clear_tx_tstamp(adapter);
1172
1173 if (pci_device_is_present(pdev: adapter->pdev)) {
1174 igc_ptp_time_save(adapter);
1175 igc_ptm_stop(adapter);
1176 }
1177}
1178
1179/**
1180 * igc_ptp_stop - Disable PTP device and stop the overflow check.
1181 * @adapter: Board private structure.
1182 *
1183 * This function stops the PTP support and cancels the delayed work.
1184 **/
1185void igc_ptp_stop(struct igc_adapter *adapter)
1186{
1187 igc_ptp_suspend(adapter);
1188
1189 if (adapter->ptp_clock) {
1190 ptp_clock_unregister(ptp: adapter->ptp_clock);
1191 netdev_info(dev: adapter->netdev, format: "PHC removed\n");
1192 adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1193 }
1194}
1195
1196/**
1197 * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1198 * @adapter: Board private structure.
1199 *
1200 * This function handles the reset work required to re-enable the PTP device.
1201 **/
1202void igc_ptp_reset(struct igc_adapter *adapter)
1203{
1204 struct igc_hw *hw = &adapter->hw;
1205 u32 cycle_ctrl, ctrl;
1206 unsigned long flags;
1207 u32 timadj;
1208
1209 /* reset the tstamp_config */
1210 igc_ptp_set_timestamp_mode(adapter, config: &adapter->tstamp_config);
1211
1212 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1213
1214 switch (adapter->hw.mac.type) {
1215 case igc_i225:
1216 timadj = rd32(IGC_TIMADJ);
1217 timadj |= IGC_TIMADJ_ADJUST_METH;
1218 wr32(IGC_TIMADJ, timadj);
1219
1220 wr32(IGC_TSAUXC, 0x0);
1221 wr32(IGC_TSSDP, 0x0);
1222 wr32(IGC_TSIM,
1223 IGC_TSICR_INTERRUPTS |
1224 (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1225 wr32(IGC_IMS, IGC_IMS_TS);
1226
1227 if (!igc_is_crosststamp_supported(adapter))
1228 break;
1229
1230 wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1231 wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1232
1233 cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1234
1235 wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1236
1237 ctrl = IGC_PTM_CTRL_EN |
1238 IGC_PTM_CTRL_START_NOW |
1239 IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1240 IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1241 IGC_PTM_CTRL_TRIG;
1242
1243 wr32(IGC_PTM_CTRL, ctrl);
1244
1245 /* Force the first cycle to run. */
1246 wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1247
1248 break;
1249 default:
1250 /* No work to do. */
1251 goto out;
1252 }
1253
1254 /* Re-initialize the timer. */
1255 if (hw->mac.type == igc_i225) {
1256 igc_ptp_time_restore(adapter);
1257 } else {
1258 timecounter_init(tc: &adapter->tc, cc: &adapter->cc,
1259 start_tstamp: ktime_to_ns(kt: ktime_get_real()));
1260 }
1261out:
1262 spin_unlock_irqrestore(lock: &adapter->tmreg_lock, flags);
1263
1264 wrfl();
1265}
1266

source code of linux/drivers/net/ethernet/intel/igc/igc_ptp.c