1	// SPDX-License-Identifier: GPL-2.0+
2	/*
3	* drivers/net/phy/micrel.c
4	*
5	* Driver for Micrel PHYs
6	*
7	* Author: David J. Choi
8	*
9	* Copyright (c) 2010-2013 Micrel, Inc.
10	* Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11	*
12	* Support : Micrel Phys:
13	* Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15	* ksz8021, ksz8031, ksz8051,
16	* ksz8081, ksz8091,
17	* ksz8061,
18	* Switch : ksz8873, ksz886x
19	* ksz9477, lan8804
20	*/
21
22	#include <linux/bitfield.h>
23	#include <linux/ethtool_netlink.h>
24	#include <linux/kernel.h>
25	#include <linux/module.h>
26	#include <linux/phy.h>
27	#include <linux/micrel_phy.h>
28	#include <linux/of.h>
29	#include <linux/clk.h>
30	#include <linux/delay.h>
31	#include <linux/ptp_clock_kernel.h>
32	#include <linux/ptp_clock.h>
33	#include <linux/ptp_classify.h>
34	#include <linux/net_tstamp.h>
35	#include <linux/gpio/consumer.h>
36
37	#include "phylib.h"
38
39	/* Operation Mode Strap Override */
40	#define MII_KSZPHY_OMSO 0x16
41	#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
42	#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
43	#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
44	#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
45	#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
46
47	/* general Interrupt control/status reg in vendor specific block. */
48	#define MII_KSZPHY_INTCS 0x1B
49	#define KSZPHY_INTCS_JABBER BIT(15)
50	#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
51	#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
52	#define KSZPHY_INTCS_PARELLEL BIT(12)
53	#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
54	#define KSZPHY_INTCS_LINK_DOWN BIT(10)
55	#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
56	#define KSZPHY_INTCS_LINK_UP BIT(8)
57	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
58	KSZPHY_INTCS_LINK_DOWN)
59	#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
60	#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
61	#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
62	KSZPHY_INTCS_LINK_UP_STATUS)
63
64	/* LinkMD Control/Status */
65	#define KSZ8081_LMD 0x1d
66	#define KSZ8081_LMD_ENABLE_TEST BIT(15)
67	#define KSZ8081_LMD_STAT_NORMAL 0
68	#define KSZ8081_LMD_STAT_OPEN 1
69	#define KSZ8081_LMD_STAT_SHORT 2
70	#define KSZ8081_LMD_STAT_FAIL 3
71	#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
72	/* Short cable (<10 meter) has been detected by LinkMD */
73	#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
74	#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
75
76	#define KSZ9x31_LMD 0x12
77	#define KSZ9x31_LMD_VCT_EN BIT(15)
78	#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
79	#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
80	#define KSZ9x31_LMD_VCT_SEL_RESULT 0
81	#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
82	#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
83	#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
84	#define KSZ9x31_LMD_VCT_ST_NORMAL 0
85	#define KSZ9x31_LMD_VCT_ST_OPEN 1
86	#define KSZ9x31_LMD_VCT_ST_SHORT 2
87	#define KSZ9x31_LMD_VCT_ST_FAIL 3
88	#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
89	#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
90	#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
91	#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
92	#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
93	#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
94	#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
95	#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
96
97	#define KSZPHY_WIRE_PAIR_MASK 0x3
98
99	#define LAN8814_CABLE_DIAG 0x12
100	#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
101	#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
102	#define LAN8814_PAIR_BIT_SHIFT 12
103
104	#define LAN8814_SKUS 0xB
105
106	#define LAN8814_WIRE_PAIR_MASK 0xF
107
108	/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
109	#define LAN8814_INTC 0x18
110	#define LAN8814_INTS 0x1B
111
112	#define LAN8814_INT_FLF BIT(15)
113	#define LAN8814_INT_LINK_DOWN BIT(2)
114	#define LAN8814_INT_LINK_UP BIT(0)
115	#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
116	LAN8814_INT_LINK_DOWN)
117
118	#define LAN8814_INTR_CTRL_REG 0x34
119	#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
120	#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
121
122	#define LAN8814_EEE_STATE 0x38
123	#define LAN8814_EEE_STATE_MASK2P5P BIT(10)
124
125	#define LAN8814_PD_CONTROLS 0x9d
126	#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)
127	#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb
128
129	/* Represents 1ppm adjustment in 2^32 format with
130	* each nsec contains 4 clock cycles.
131	* The value is calculated as following: (1/1000000)/((2^-32)/4)
132	*/
133	#define LAN8814_1PPM_FORMAT 17179
134
135	/* Represents 1ppm adjustment in 2^32 format with
136	* each nsec contains 8 clock cycles.
137	* The value is calculated as following: (1/1000000)/((2^-32)/8)
138	*/
139	#define LAN8841_1PPM_FORMAT 34360
140
141	#define PTP_RX_VERSION 0x0248
142	#define PTP_TX_VERSION 0x0288
143	#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
144	#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
145
146	#define PTP_RX_MOD 0x024F
147	#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
148	#define PTP_RX_TIMESTAMP_EN 0x024D
149	#define PTP_TX_TIMESTAMP_EN 0x028D
150
151	#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
152	#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
153	#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
154	#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
155
156	#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
157	#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
158
159	#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
160	#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
161	#define LTC_HARD_RESET 0x023F
162	#define LTC_HARD_RESET_ BIT(0)
163
164	#define TSU_HARD_RESET 0x02C1
165	#define TSU_HARD_RESET_ BIT(0)
166
167	#define PTP_CMD_CTL 0x0200
168	#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
169	#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
170	#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
171	#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
172	#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
173	#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
174
175	#define PTP_COMMON_INT_ENA 0x0204
176	#define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2)
177
178	#define PTP_CLOCK_SET_SEC_HI 0x0205
179	#define PTP_CLOCK_SET_SEC_MID 0x0206
180	#define PTP_CLOCK_SET_SEC_LO 0x0207
181	#define PTP_CLOCK_SET_NS_HI 0x0208
182	#define PTP_CLOCK_SET_NS_LO 0x0209
183
184	#define PTP_CLOCK_READ_SEC_HI 0x0229
185	#define PTP_CLOCK_READ_SEC_MID 0x022A
186	#define PTP_CLOCK_READ_SEC_LO 0x022B
187	#define PTP_CLOCK_READ_NS_HI 0x022C
188	#define PTP_CLOCK_READ_NS_LO 0x022D
189
190	#define PTP_GPIO_SEL 0x0230
191	#define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8)
192	#define PTP_GPIO_CAP_MAP_LO 0x0232
193
194	#define PTP_GPIO_CAP_EN 0x0233
195	#define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio)
196	#define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
197
198	#define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235
199	#define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236
200	#define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237
201	#define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238
202	#define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239
203	#define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A
204	#define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B
205	#define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C
206
207	#define PTP_GPIO_CAP_STS 0x023D
208	#define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio)
209	#define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8)
210
211	#define PTP_OPERATING_MODE 0x0241
212	#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
213
214	#define PTP_TX_MOD 0x028F
215	#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
216	#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
217
218	#define PTP_RX_PARSE_CONFIG 0x0242
219	#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
220	#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
221	#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
222
223	#define PTP_TX_PARSE_CONFIG 0x0282
224	#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
225	#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
226	#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
227
228	#define PTP_CLOCK_RATE_ADJ_HI 0x020C
229	#define PTP_CLOCK_RATE_ADJ_LO 0x020D
230	#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
231
232	#define PTP_LTC_STEP_ADJ_HI 0x0212
233	#define PTP_LTC_STEP_ADJ_LO 0x0213
234	#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
235
236	#define LAN8814_INTR_STS_REG 0x0033
237	#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
238	#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
239	#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
240	#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
241
242	#define PTP_CAP_INFO 0x022A
243	#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
244	#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
245
246	#define PTP_TX_EGRESS_SEC_HI 0x0296
247	#define PTP_TX_EGRESS_SEC_LO 0x0297
248	#define PTP_TX_EGRESS_NS_HI 0x0294
249	#define PTP_TX_EGRESS_NS_LO 0x0295
250	#define PTP_TX_MSG_HEADER2 0x0299
251
252	#define PTP_RX_INGRESS_SEC_HI 0x0256
253	#define PTP_RX_INGRESS_SEC_LO 0x0257
254	#define PTP_RX_INGRESS_NS_HI 0x0254
255	#define PTP_RX_INGRESS_NS_LO 0x0255
256	#define PTP_RX_MSG_HEADER2 0x0259
257
258	#define PTP_TSU_INT_EN 0x0200
259	#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
260	#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
261	#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
262	#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
263
264	#define PTP_TSU_INT_STS 0x0201
265	#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
266	#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
267	#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
268	#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
269
270	#define LAN8814_LED_CTRL_1 0x0
271	#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
272	#define LAN8814_LED_CTRL_2 0x1
273	#define LAN8814_LED_CTRL_2_LED1_COM_DIS BIT(8)
274
275	/* PHY Control 1 */
276	#define MII_KSZPHY_CTRL_1 0x1e
277	#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
278
279	/* PHY Control 2 / PHY Control (if no PHY Control 1) */
280	#define MII_KSZPHY_CTRL_2 0x1f
281	#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
282	/* bitmap of PHY register to set interrupt mode */
283	#define KSZ8081_CTRL2_HP_MDIX BIT(15)
284	#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
285	#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
286	#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
287	#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
288	#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
289	#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
290
291	/* Write/read to/from extended registers */
292	#define MII_KSZPHY_EXTREG 0x0b
293	#define KSZPHY_EXTREG_WRITE 0x8000
294
295	#define MII_KSZPHY_EXTREG_WRITE 0x0c
296	#define MII_KSZPHY_EXTREG_READ 0x0d
297
298	/* Extended registers */
299	#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
300	#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
301	#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
302
303	#define PS_TO_REG 200
304	#define FIFO_SIZE 8
305
306	#define LAN8814_PTP_GPIO_NUM 24
307	#define LAN8814_PTP_PEROUT_NUM 2
308	#define LAN8814_PTP_EXTTS_NUM 3
309
310	#define LAN8814_BUFFER_TIME 2
311
312	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
313	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
314	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
315	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
316	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
317	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
318	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
319	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
320	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
321	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
322	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
323	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
324	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
325	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
326
327	#define LAN8814_GPIO_EN1 0x20
328	#define LAN8814_GPIO_EN2 0x21
329	#define LAN8814_GPIO_DIR1 0x22
330	#define LAN8814_GPIO_DIR2 0x23
331	#define LAN8814_GPIO_BUF1 0x24
332	#define LAN8814_GPIO_BUF2 0x25
333
334	#define LAN8814_GPIO_EN_ADDR(pin) \
335	((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
336	#define LAN8814_GPIO_EN_BIT(pin) BIT(pin)
337	#define LAN8814_GPIO_DIR_ADDR(pin) \
338	((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
339	#define LAN8814_GPIO_DIR_BIT(pin) BIT(pin)
340	#define LAN8814_GPIO_BUF_ADDR(pin) \
341	((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)
342	#define LAN8814_GPIO_BUF_BIT(pin) BIT(pin)
343
344	#define LAN8814_EVENT_A 0
345	#define LAN8814_EVENT_B 1
346
347	#define LAN8814_PTP_GENERAL_CONFIG 0x0201
348	#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \
349	((event) ? GENMASK(11, 8) : GENMASK(7, 4))
350	#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \
351	(((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))
352	#define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \
353	((event) ? BIT(2) : BIT(0))
354	#define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \
355	((event) ? BIT(3) : BIT(1))
356
357	#define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215)
358	#define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216)
359	#define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217)
360	#define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218)
361
362	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219)
363	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A)
364	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B)
365	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C)
366
367	/* Delay used to get the second part from the LTC */
368	#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
369
370	#define LAN8842_REV_8832 0x8832
371
372	#define LAN8814_REV_LAN8814 0x8814
373	#define LAN8814_REV_LAN8818 0x8818
374
375	struct kszphy_hw_stat {
376	const char *string;
377	u8 reg;
378	u8 bits;
379	};
380
381	static struct kszphy_hw_stat kszphy_hw_stats[] = {
382	{ "phy_receive_errors", 21, 16},
383	{ "phy_idle_errors", 10, 8 },
384	};
385
386	struct kszphy_type {
387	u32 led_mode_reg;
388	u16 interrupt_level_mask;
389	u16 cable_diag_reg;
390	unsigned long pair_mask;
391	u16 disable_dll_tx_bit;
392	u16 disable_dll_rx_bit;
393	u16 disable_dll_mask;
394	bool has_broadcast_disable;
395	bool has_nand_tree_disable;
396	bool has_rmii_ref_clk_sel;
397	};
398
399	/* Shared structure between the PHYs of the same package. */
400	struct lan8814_shared_priv {
401	struct phy_device *phydev;
402	struct ptp_clock *ptp_clock;
403	struct ptp_clock_info ptp_clock_info;
404	struct ptp_pin_desc *pin_config;
405
406	/* Lock for ptp_clock */
407	struct mutex shared_lock;
408	};
409
410	struct lan8814_ptp_rx_ts {
411	struct list_head list;
412	u32 seconds;
413	u32 nsec;
414	u16 seq_id;
415	};
416
417	struct kszphy_ptp_priv {
418	struct mii_timestamper mii_ts;
419	struct phy_device *phydev;
420
421	struct sk_buff_head tx_queue;
422	struct sk_buff_head rx_queue;
423
424	struct list_head rx_ts_list;
425	/* Lock for Rx ts fifo */
426	spinlock_t rx_ts_lock;
427
428	int hwts_tx_type;
429	enum hwtstamp_rx_filters rx_filter;
430	int layer;
431	int version;
432
433	struct ptp_clock *ptp_clock;
434	struct ptp_clock_info ptp_clock_info;
435	/* Lock for ptp_clock */
436	struct mutex ptp_lock;
437	struct ptp_pin_desc *pin_config;
438
439	s64 seconds;
440	/* Lock for accessing seconds */
441	spinlock_t seconds_lock;
442	};
443
444	struct kszphy_phy_stats {
445	u64 rx_err_pkt_cnt;
446	};
447
448	struct kszphy_priv {
449	struct kszphy_ptp_priv ptp_priv;
450	const struct kszphy_type *type;
451	struct clk *clk;
452	int led_mode;
453	u16 vct_ctrl1000;
454	bool rmii_ref_clk_sel;
455	bool rmii_ref_clk_sel_val;
456	bool clk_enable;
457	bool is_ptp_available;
458	u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
459	struct kszphy_phy_stats phy_stats;
460	};
461
462	struct lan8842_phy_stats {
463	u64 rx_packets;
464	u64 rx_errors;
465	u64 tx_packets;
466	u64 tx_errors;
467	};
468
469	struct lan8842_priv {
470	struct lan8842_phy_stats phy_stats;
471	struct kszphy_ptp_priv ptp_priv;
472	u16 rev;
473	};
474
475	struct lanphy_reg_data {
476	int page;
477	u16 addr;
478	u16 val;
479	};
480
481	static const struct kszphy_type lan8814_type = {
482	.led_mode_reg = ~LAN8814_LED_CTRL_1,
483	.cable_diag_reg = LAN8814_CABLE_DIAG,
484	.pair_mask = LAN8814_WIRE_PAIR_MASK,
485	};
486
487	static const struct kszphy_type ksz886x_type = {
488	.cable_diag_reg = KSZ8081_LMD,
489	.pair_mask = KSZPHY_WIRE_PAIR_MASK,
490	};
491
492	static const struct kszphy_type ksz8021_type = {
493	.led_mode_reg = MII_KSZPHY_CTRL_2,
494	.has_broadcast_disable = true,
495	.has_nand_tree_disable = true,
496	.has_rmii_ref_clk_sel = true,
497	};
498
499	static const struct kszphy_type ksz8041_type = {
500	.led_mode_reg = MII_KSZPHY_CTRL_1,
501	};
502
503	static const struct kszphy_type ksz8051_type = {
504	.led_mode_reg = MII_KSZPHY_CTRL_2,
505	.has_nand_tree_disable = true,
506	};
507
508	static const struct kszphy_type ksz8081_type = {
509	.led_mode_reg = MII_KSZPHY_CTRL_2,
510	.cable_diag_reg = KSZ8081_LMD,
511	.pair_mask = KSZPHY_WIRE_PAIR_MASK,
512	.has_broadcast_disable = true,
513	.has_nand_tree_disable = true,
514	.has_rmii_ref_clk_sel = true,
515	};
516
517	static const struct kszphy_type ks8737_type = {
518	.interrupt_level_mask = BIT(14),
519	};
520
521	static const struct kszphy_type ksz9021_type = {
522	.interrupt_level_mask = BIT(14),
523	};
524
525	static const struct kszphy_type ksz9131_type = {
526	.interrupt_level_mask = BIT(14),
527	.disable_dll_tx_bit = BIT(12),
528	.disable_dll_rx_bit = BIT(12),
529	.disable_dll_mask = BIT_MASK(12),
530	};
531
532	static const struct kszphy_type lan8841_type = {
533	.disable_dll_tx_bit = BIT(14),
534	.disable_dll_rx_bit = BIT(14),
535	.disable_dll_mask = BIT_MASK(14),
536	.cable_diag_reg = LAN8814_CABLE_DIAG,
537	.pair_mask = LAN8814_WIRE_PAIR_MASK,
538	};
539
540	static int kszphy_extended_write(struct phy_device *phydev,
541	u32 regnum, u16 val)
542	{
543	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
544	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
545	}
546
547	static int kszphy_extended_read(struct phy_device *phydev,
548	u32 regnum)
549	{
550	phy_write(phydev, MII_KSZPHY_EXTREG, val: regnum);
551	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
552	}
553
554	static int kszphy_ack_interrupt(struct phy_device *phydev)
555	{
556	/* bit[7..0] int status, which is a read and clear register. */
557	int rc;
558
559	rc = phy_read(phydev, MII_KSZPHY_INTCS);
560
561	return (rc < 0) ? rc : 0;
562	}
563
564	static int kszphy_config_intr(struct phy_device *phydev)
565	{
566	const struct kszphy_type *type = phydev->drv->driver_data;
567	int temp, err;
568	u16 mask;
569
570	if (type && type->interrupt_level_mask)
571	mask = type->interrupt_level_mask;
572	else
573	mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
574
575	/* set the interrupt pin active low */
576	temp = phy_read(phydev, MII_KSZPHY_CTRL);
577	if (temp < 0)
578	return temp;
579	temp &= ~mask;
580	phy_write(phydev, MII_KSZPHY_CTRL, val: temp);
581
582	/* enable / disable interrupts */
583	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
584	err = kszphy_ack_interrupt(phydev);
585	if (err)
586	return err;
587
588	err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
589	} else {
590	err = phy_write(phydev, MII_KSZPHY_INTCS, val: 0);
591	if (err)
592	return err;
593
594	err = kszphy_ack_interrupt(phydev);
595	}
596
597	return err;
598	}
599
600	static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
601	{
602	int irq_status;
603
604	irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
605	if (irq_status < 0) {
606	phy_error(phydev);
607	return IRQ_NONE;
608	}
609
610	if (!(irq_status & KSZPHY_INTCS_STATUS))
611	return IRQ_NONE;
612
613	phy_trigger_machine(phydev);
614
615	return IRQ_HANDLED;
616	}
617
618	static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
619	{
620	int ctrl;
621
622	ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
623	if (ctrl < 0)
624	return ctrl;
625
626	if (val)
627	ctrl |= KSZPHY_RMII_REF_CLK_SEL;
628	else
629	ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
630
631	return phy_write(phydev, MII_KSZPHY_CTRL, val: ctrl);
632	}
633
634	static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
635	{
636	int rc, temp, shift;
637
638	switch (reg) {
639	case MII_KSZPHY_CTRL_1:
640	shift = 14;
641	break;
642	case MII_KSZPHY_CTRL_2:
643	shift = 4;
644	break;
645	default:
646	return -EINVAL;
647	}
648
649	temp = phy_read(phydev, regnum: reg);
650	if (temp < 0) {
651	rc = temp;
652	goto out;
653	}
654
655	temp &= ~(3 << shift);
656	temp |= val << shift;
657	rc = phy_write(phydev, regnum: reg, val: temp);
658	out:
659	if (rc < 0)
660	phydev_err(phydev, "failed to set led mode\n");
661
662	return rc;
663	}
664
665	/* Disable PHY address 0 as the broadcast address, so that it can be used as a
666	* unique (non-broadcast) address on a shared bus.
667	*/
668	static int kszphy_broadcast_disable(struct phy_device *phydev)
669	{
670	int ret;
671
672	ret = phy_read(phydev, MII_KSZPHY_OMSO);
673	if (ret < 0)
674	goto out;
675
676	ret = phy_write(phydev, MII_KSZPHY_OMSO, val: ret | KSZPHY_OMSO_B_CAST_OFF);
677	out:
678	if (ret)
679	phydev_err(phydev, "failed to disable broadcast address\n");
680
681	return ret;
682	}
683
684	static int kszphy_nand_tree_disable(struct phy_device *phydev)
685	{
686	int ret;
687
688	ret = phy_read(phydev, MII_KSZPHY_OMSO);
689	if (ret < 0)
690	goto out;
691
692	if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
693	return 0;
694
695	ret = phy_write(phydev, MII_KSZPHY_OMSO,
696	val: ret & ~KSZPHY_OMSO_NAND_TREE_ON);
697	out:
698	if (ret)
699	phydev_err(phydev, "failed to disable NAND tree mode\n");
700
701	return ret;
702	}
703
704	/* Some config bits need to be set again on resume, handle them here. */
705	static int kszphy_config_reset(struct phy_device *phydev)
706	{
707	struct kszphy_priv *priv = phydev->priv;
708	int ret;
709
710	if (priv->rmii_ref_clk_sel) {
711	ret = kszphy_rmii_clk_sel(phydev, val: priv->rmii_ref_clk_sel_val);
712	if (ret) {
713	phydev_err(phydev,
714	"failed to set rmii reference clock\n");
715	return ret;
716	}
717	}
718
719	if (priv->type && priv->led_mode >= 0)
720	kszphy_setup_led(phydev, reg: priv->type->led_mode_reg, val: priv->led_mode);
721
722	return 0;
723	}
724
725	static int kszphy_config_init(struct phy_device *phydev)
726	{
727	struct kszphy_priv *priv = phydev->priv;
728	const struct kszphy_type *type;
729
730	if (!priv)
731	return 0;
732
733	type = priv->type;
734
735	if (type && type->has_broadcast_disable)
736	kszphy_broadcast_disable(phydev);
737
738	if (type && type->has_nand_tree_disable)
739	kszphy_nand_tree_disable(phydev);
740
741	return kszphy_config_reset(phydev);
742	}
743
744	static int ksz8041_fiber_mode(struct phy_device *phydev)
745	{
746	struct device_node *of_node = phydev->mdio.dev.of_node;
747
748	return of_property_read_bool(np: of_node, propname: "micrel,fiber-mode");
749	}
750
751	static int ksz8041_config_init(struct phy_device *phydev)
752	{
753	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
754
755	/* Limit supported and advertised modes in fiber mode */
756	if (ksz8041_fiber_mode(phydev)) {
757	phydev->dev_flags |= MICREL_PHY_FXEN;
758	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
759	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
760
761	linkmode_and(dst: phydev->supported, a: phydev->supported, b: mask);
762	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
763	phydev->supported);
764	linkmode_and(dst: phydev->advertising, a: phydev->advertising, b: mask);
765	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
766	phydev->advertising);
767	phydev->autoneg = AUTONEG_DISABLE;
768	}
769
770	return kszphy_config_init(phydev);
771	}
772
773	static int ksz8041_config_aneg(struct phy_device *phydev)
774	{
775	/* Skip auto-negotiation in fiber mode */
776	if (phydev->dev_flags & MICREL_PHY_FXEN) {
777	phydev->speed = SPEED_100;
778	return 0;
779	}
780
781	return genphy_config_aneg(phydev);
782	}
783
784	static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
785	const bool ksz_8051)
786	{
787	int ret;
788
789	if (!phy_id_compare(id1: phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
790	return 0;
791
792	ret = phy_read(phydev, MII_BMSR);
793	if (ret < 0)
794	return ret;
795
796	/* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
797	* exact PHY ID. However, they can be told apart by the extended
798	* capability registers presence. The KSZ8051 PHY has them while
799	* the switch does not.
800	*/
801	ret &= BMSR_ERCAP;
802	if (ksz_8051)
803	return ret;
804	else
805	return !ret;
806	}
807
808	static int ksz8051_match_phy_device(struct phy_device *phydev,
809	const struct phy_driver *phydrv)
810	{
811	return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: true);
812	}
813
814	static int ksz8081_config_init(struct phy_device *phydev)
815	{
816	/* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
817	* based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
818	* pull-down is missing, the factory test mode should be cleared by
819	* manually writing a 0.
820	*/
821	phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
822
823	return kszphy_config_init(phydev);
824	}
825
826	static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
827	{
828	u16 val;
829
830	switch (ctrl) {
831	case ETH_TP_MDI:
832	val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
833	break;
834	case ETH_TP_MDI_X:
835	val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
836	KSZ8081_CTRL2_MDI_MDI_X_SELECT;
837	break;
838	case ETH_TP_MDI_AUTO:
839	val = 0;
840	break;
841	default:
842	return 0;
843	}
844
845	return phy_modify(phydev, MII_KSZPHY_CTRL_2,
846	KSZ8081_CTRL2_HP_MDIX |
847	KSZ8081_CTRL2_MDI_MDI_X_SELECT |
848	KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
849	KSZ8081_CTRL2_HP_MDIX | val);
850	}
851
852	static int ksz8081_config_aneg(struct phy_device *phydev)
853	{
854	int ret;
855
856	ret = genphy_config_aneg(phydev);
857	if (ret)
858	return ret;
859
860	/* The MDI-X configuration is automatically changed by the PHY after
861	* switching from autoneg off to on. So, take MDI-X configuration under
862	* own control and set it after autoneg configuration was done.
863	*/
864	return ksz8081_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
865	}
866
867	static int ksz8081_mdix_update(struct phy_device *phydev)
868	{
869	int ret;
870
871	ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
872	if (ret < 0)
873	return ret;
874
875	if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
876	if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
877	phydev->mdix_ctrl = ETH_TP_MDI_X;
878	else
879	phydev->mdix_ctrl = ETH_TP_MDI;
880	} else {
881	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
882	}
883
884	ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
885	if (ret < 0)
886	return ret;
887
888	if (ret & KSZ8081_CTRL1_MDIX_STAT)
889	phydev->mdix = ETH_TP_MDI;
890	else
891	phydev->mdix = ETH_TP_MDI_X;
892
893	return 0;
894	}
895
896	static int ksz8081_read_status(struct phy_device *phydev)
897	{
898	int ret;
899
900	ret = ksz8081_mdix_update(phydev);
901	if (ret < 0)
902	return ret;
903
904	return genphy_read_status(phydev);
905	}
906
907	static int ksz8061_config_init(struct phy_device *phydev)
908	{
909	int ret;
910
911	/* Chip can be powered down by the bootstrap code. */
912	ret = phy_read(phydev, MII_BMCR);
913	if (ret < 0)
914	return ret;
915	if (ret & BMCR_PDOWN) {
916	ret = phy_write(phydev, MII_BMCR, val: ret & ~BMCR_PDOWN);
917	if (ret < 0)
918	return ret;
919	usleep_range(min: 1000, max: 2000);
920	}
921
922	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, val: 0xB61A);
923	if (ret)
924	return ret;
925
926	return kszphy_config_init(phydev);
927	}
928
929	static int ksz8795_match_phy_device(struct phy_device *phydev,
930	const struct phy_driver *phydrv)
931	{
932	return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: false);
933	}
934
935	static int ksz9021_load_values_from_of(struct phy_device *phydev,
936	const struct device_node *of_node,
937	u16 reg,
938	const char *field1, const char *field2,
939	const char *field3, const char *field4)
940	{
941	int val1 = -1;
942	int val2 = -2;
943	int val3 = -3;
944	int val4 = -4;
945	int newval;
946	int matches = 0;
947
948	if (!of_property_read_u32(np: of_node, propname: field1, out_value: &val1))
949	matches++;
950
951	if (!of_property_read_u32(np: of_node, propname: field2, out_value: &val2))
952	matches++;
953
954	if (!of_property_read_u32(np: of_node, propname: field3, out_value: &val3))
955	matches++;
956
957	if (!of_property_read_u32(np: of_node, propname: field4, out_value: &val4))
958	matches++;
959
960	if (!matches)
961	return 0;
962
963	if (matches < 4)
964	newval = kszphy_extended_read(phydev, regnum: reg);
965	else
966	newval = 0;
967
968	if (val1 != -1)
969	newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
970
971	if (val2 != -2)
972	newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
973
974	if (val3 != -3)
975	newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
976
977	if (val4 != -4)
978	newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
979
980	return kszphy_extended_write(phydev, regnum: reg, val: newval);
981	}
982
983	static int ksz9021_config_init(struct phy_device *phydev)
984	{
985	const struct device_node *of_node;
986	const struct device *dev_walker;
987
988	/* The Micrel driver has a deprecated option to place phy OF
989	* properties in the MAC node. Walk up the tree of devices to
990	* find a device with an OF node.
991	*/
992	dev_walker = &phydev->mdio.dev;
993	do {
994	of_node = dev_walker->of_node;
995	dev_walker = dev_walker->parent;
996
997	} while (!of_node && dev_walker);
998
999	if (of_node) {
1000	ksz9021_load_values_from_of(phydev, of_node,
1001	MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
1002	field1: "txen-skew-ps", field2: "txc-skew-ps",
1003	field3: "rxdv-skew-ps", field4: "rxc-skew-ps");
1004	ksz9021_load_values_from_of(phydev, of_node,
1005	MII_KSZPHY_RX_DATA_PAD_SKEW,
1006	field1: "rxd0-skew-ps", field2: "rxd1-skew-ps",
1007	field3: "rxd2-skew-ps", field4: "rxd3-skew-ps");
1008	ksz9021_load_values_from_of(phydev, of_node,
1009	MII_KSZPHY_TX_DATA_PAD_SKEW,
1010	field1: "txd0-skew-ps", field2: "txd1-skew-ps",
1011	field3: "txd2-skew-ps", field4: "txd3-skew-ps");
1012	}
1013	return 0;
1014	}
1015
1016	#define KSZ9031_PS_TO_REG 60
1017
1018	/* Extended registers */
1019	/* MMD Address 0x0 */
1020	#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
1021	#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
1022
1023	/* MMD Address 0x2 */
1024	#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
1025	#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
1026	#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
1027
1028	#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
1029	#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
1030	#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
1031	#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
1032	#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
1033
1034	#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
1035	#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
1036	#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
1037	#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
1038	#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
1039
1040	#define MII_KSZ9031RN_CLK_PAD_SKEW 8
1041	#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
1042	#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
1043
1044	/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
1045	* provide different RGMII options we need to configure delay offset
1046	* for each pad relative to build in delay.
1047	*/
1048	/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
1049	* 1.80ns
1050	*/
1051	#define RX_ID 0x7
1052	#define RX_CLK_ID 0x19
1053
1054	/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
1055	* internal 1.2ns delay.
1056	*/
1057	#define RX_ND 0xc
1058	#define RX_CLK_ND 0x0
1059
1060	/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
1061	#define TX_ID 0x0
1062	#define TX_CLK_ID 0x1f
1063
1064	/* set tx and tx_clk to "No delay adjustment" to keep 0ns
1065	* delay
1066	*/
1067	#define TX_ND 0x7
1068	#define TX_CLK_ND 0xf
1069
1070	/* MMD Address 0x1C */
1071	#define MII_KSZ9031RN_EDPD 0x23
1072	#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
1073
1074	static int ksz9031_set_loopback(struct phy_device *phydev, bool enable,
1075	int speed)
1076	{
1077	u16 ctl = BMCR_LOOPBACK;
1078	int val;
1079
1080	if (!enable)
1081	return genphy_loopback(phydev, enable, speed: 0);
1082
1083	if (speed == SPEED_10 || speed == SPEED_100 || speed == SPEED_1000)
1084	phydev->speed = speed;
1085	else if (speed)
1086	return -EINVAL;
1087	phydev->duplex = DUPLEX_FULL;
1088
1089	ctl |= mii_bmcr_encode_fixed(speed: phydev->speed, duplex: phydev->duplex);
1090
1091	phy_write(phydev, MII_BMCR, val: ctl);
1092
1093	return phy_read_poll_timeout(phydev, MII_BMSR, val, val & BMSR_LSTATUS,
1094	5000, 500000, true);
1095	}
1096
1097	static int ksz9031_of_load_skew_values(struct phy_device *phydev,
1098	const struct device_node *of_node,
1099	u16 reg, size_t field_sz,
1100	const char *field[], u8 numfields,
1101	bool *update)
1102	{
1103	int val[4] = {-1, -2, -3, -4};
1104	int matches = 0;
1105	u16 mask;
1106	u16 maxval;
1107	u16 newval;
1108	int i;
1109
1110	for (i = 0; i < numfields; i++)
1111	if (!of_property_read_u32(np: of_node, propname: field[i], out_value: val + i))
1112	matches++;
1113
1114	if (!matches)
1115	return 0;
1116
1117	*update |= true;
1118
1119	if (matches < numfields)
1120	newval = phy_read_mmd(phydev, devad: 2, regnum: reg);
1121	else
1122	newval = 0;
1123
1124	maxval = (field_sz == 4) ? 0xf : 0x1f;
1125	for (i = 0; i < numfields; i++)
1126	if (val[i] != -(i + 1)) {
1127	mask = 0xffff;
1128	mask ^= maxval << (field_sz * i);
1129	newval = (newval & mask) |
1130	(((val[i] / KSZ9031_PS_TO_REG) & maxval)
1131	<< (field_sz * i));
1132	}
1133
1134	return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval);
1135	}
1136
1137	/* Center KSZ9031RNX FLP timing at 16ms. */
1138	static int ksz9031_center_flp_timing(struct phy_device *phydev)
1139	{
1140	int result;
1141
1142	result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
1143	val: 0x0006);
1144	if (result)
1145	return result;
1146
1147	result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
1148	val: 0x1A80);
1149	if (result)
1150	return result;
1151
1152	return genphy_restart_aneg(phydev);
1153	}
1154
1155	/* Enable energy-detect power-down mode */
1156	static int ksz9031_enable_edpd(struct phy_device *phydev)
1157	{
1158	int reg;
1159
1160	reg = phy_read_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD);
1161	if (reg < 0)
1162	return reg;
1163	return phy_write_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD,
1164	val: reg | MII_KSZ9031RN_EDPD_ENABLE);
1165	}
1166
1167	static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1168	{
1169	u16 rx, tx, rx_clk, tx_clk;
1170	int ret;
1171
1172	switch (phydev->interface) {
1173	case PHY_INTERFACE_MODE_RGMII:
1174	tx = TX_ND;
1175	tx_clk = TX_CLK_ND;
1176	rx = RX_ND;
1177	rx_clk = RX_CLK_ND;
1178	break;
1179	case PHY_INTERFACE_MODE_RGMII_ID:
1180	tx = TX_ID;
1181	tx_clk = TX_CLK_ID;
1182	rx = RX_ID;
1183	rx_clk = RX_CLK_ID;
1184	break;
1185	case PHY_INTERFACE_MODE_RGMII_RXID:
1186	tx = TX_ND;
1187	tx_clk = TX_CLK_ND;
1188	rx = RX_ID;
1189	rx_clk = RX_CLK_ID;
1190	break;
1191	case PHY_INTERFACE_MODE_RGMII_TXID:
1192	tx = TX_ID;
1193	tx_clk = TX_CLK_ID;
1194	rx = RX_ND;
1195	rx_clk = RX_CLK_ND;
1196	break;
1197	default:
1198	return 0;
1199	}
1200
1201	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1202	FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1203	FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1204	if (ret < 0)
1205	return ret;
1206
1207	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1208	FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1209	FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1210	FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1211	FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1212	if (ret < 0)
1213	return ret;
1214
1215	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1216	FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1217	FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1218	FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1219	FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1220	if (ret < 0)
1221	return ret;
1222
1223	return phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1224	FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1225	FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1226	}
1227
1228	static int ksz9031_config_init(struct phy_device *phydev)
1229	{
1230	const struct device_node *of_node;
1231	static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1232	static const char *rx_data_skews[4] = {
1233	"rxd0-skew-ps", "rxd1-skew-ps",
1234	"rxd2-skew-ps", "rxd3-skew-ps"
1235	};
1236	static const char *tx_data_skews[4] = {
1237	"txd0-skew-ps", "txd1-skew-ps",
1238	"txd2-skew-ps", "txd3-skew-ps"
1239	};
1240	static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1241	const struct device *dev_walker;
1242	int result;
1243
1244	result = ksz9031_enable_edpd(phydev);
1245	if (result < 0)
1246	return result;
1247
1248	/* The Micrel driver has a deprecated option to place phy OF
1249	* properties in the MAC node. Walk up the tree of devices to
1250	* find a device with an OF node.
1251	*/
1252	dev_walker = &phydev->mdio.dev;
1253	do {
1254	of_node = dev_walker->of_node;
1255	dev_walker = dev_walker->parent;
1256	} while (!of_node && dev_walker);
1257
1258	if (of_node) {
1259	bool update = false;
1260
1261	if (phy_interface_is_rgmii(phydev)) {
1262	result = ksz9031_config_rgmii_delay(phydev);
1263	if (result < 0)
1264	return result;
1265	}
1266
1267	ksz9031_of_load_skew_values(phydev, of_node,
1268	MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5,
1269	field: clk_skews, numfields: 2, update: &update);
1270
1271	ksz9031_of_load_skew_values(phydev, of_node,
1272	MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4,
1273	field: control_skews, numfields: 2, update: &update);
1274
1275	ksz9031_of_load_skew_values(phydev, of_node,
1276	MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4,
1277	field: rx_data_skews, numfields: 4, update: &update);
1278
1279	ksz9031_of_load_skew_values(phydev, of_node,
1280	MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4,
1281	field: tx_data_skews, numfields: 4, update: &update);
1282
1283	if (update && !phy_interface_is_rgmii(phydev))
1284	phydev_warn(phydev,
1285	"*-skew-ps values should be used only with RGMII PHY modes\n");
1286
1287	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
1288	* When the device links in the 1000BASE-T slave mode only,
1289	* the optional 125MHz reference output clock (CLK125_NDO)
1290	* has wide duty cycle variation.
1291	*
1292	* The optional CLK125_NDO clock does not meet the RGMII
1293	* 45/55 percent (min/max) duty cycle requirement and therefore
1294	* cannot be used directly by the MAC side for clocking
1295	* applications that have setup/hold time requirements on
1296	* rising and falling clock edges.
1297	*
1298	* Workaround:
1299	* Force the phy to be the master to receive a stable clock
1300	* which meets the duty cycle requirement.
1301	*/
1302	if (of_property_read_bool(np: of_node, propname: "micrel,force-master")) {
1303	result = phy_read(phydev, MII_CTRL1000);
1304	if (result < 0)
1305	goto err_force_master;
1306
1307	/* enable master mode, config & prefer master */
1308	result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1309	result = phy_write(phydev, MII_CTRL1000, val: result);
1310	if (result < 0)
1311	goto err_force_master;
1312	}
1313	}
1314
1315	return ksz9031_center_flp_timing(phydev);
1316
1317	err_force_master:
1318	phydev_err(phydev, "failed to force the phy to master mode\n");
1319	return result;
1320	}
1321
1322	#define KSZ9131_SKEW_5BIT_MAX 2400
1323	#define KSZ9131_SKEW_4BIT_MAX 800
1324	#define KSZ9131_OFFSET 700
1325	#define KSZ9131_STEP 100
1326
1327	static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1328	struct device_node *of_node,
1329	u16 reg, size_t field_sz,
1330	char *field[], u8 numfields)
1331	{
1332	int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1333	-(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1334	int skewval, skewmax = 0;
1335	int matches = 0;
1336	u16 maxval;
1337	u16 newval;
1338	u16 mask;
1339	int i;
1340
1341	/* psec properties in dts should mean x pico seconds */
1342	if (field_sz == 5)
1343	skewmax = KSZ9131_SKEW_5BIT_MAX;
1344	else
1345	skewmax = KSZ9131_SKEW_4BIT_MAX;
1346
1347	for (i = 0; i < numfields; i++)
1348	if (!of_property_read_s32(np: of_node, propname: field[i], out_value: &skewval)) {
1349	if (skewval < -KSZ9131_OFFSET)
1350	skewval = -KSZ9131_OFFSET;
1351	else if (skewval > skewmax)
1352	skewval = skewmax;
1353
1354	val[i] = skewval + KSZ9131_OFFSET;
1355	matches++;
1356	}
1357
1358	if (!matches)
1359	return 0;
1360
1361	if (matches < numfields)
1362	newval = phy_read_mmd(phydev, devad: 2, regnum: reg);
1363	else
1364	newval = 0;
1365
1366	maxval = (field_sz == 4) ? 0xf : 0x1f;
1367	for (i = 0; i < numfields; i++)
1368	if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1369	mask = 0xffff;
1370	mask ^= maxval << (field_sz * i);
1371	newval = (newval & mask) |
1372	(((val[i] / KSZ9131_STEP) & maxval)
1373	<< (field_sz * i));
1374	}
1375
1376	return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval);
1377	}
1378
1379	#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1380	#define KSZ9131RN_RXC_DLL_CTRL 76
1381	#define KSZ9131RN_TXC_DLL_CTRL 77
1382	#define KSZ9131RN_DLL_ENABLE_DELAY 0
1383
1384	static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1385	{
1386	const struct kszphy_type *type = phydev->drv->driver_data;
1387	u16 rxcdll_val, txcdll_val;
1388	int ret;
1389
1390	switch (phydev->interface) {
1391	case PHY_INTERFACE_MODE_RGMII:
1392	rxcdll_val = type->disable_dll_rx_bit;
1393	txcdll_val = type->disable_dll_tx_bit;
1394	break;
1395	case PHY_INTERFACE_MODE_RGMII_ID:
1396	rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1397	txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1398	break;
1399	case PHY_INTERFACE_MODE_RGMII_RXID:
1400	rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1401	txcdll_val = type->disable_dll_tx_bit;
1402	break;
1403	case PHY_INTERFACE_MODE_RGMII_TXID:
1404	rxcdll_val = type->disable_dll_rx_bit;
1405	txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1406	break;
1407	default:
1408	return 0;
1409	}
1410
1411	ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1412	KSZ9131RN_RXC_DLL_CTRL, mask: type->disable_dll_mask,
1413	set: rxcdll_val);
1414	if (ret < 0)
1415	return ret;
1416
1417	return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1418	KSZ9131RN_TXC_DLL_CTRL, mask: type->disable_dll_mask,
1419	set: txcdll_val);
1420	}
1421
1422	/* Silicon Errata DS80000693B
1423	*
1424	* When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1425	* condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1426	* according to the datasheet (off if there is no link).
1427	*/
1428	static int ksz9131_led_errata(struct phy_device *phydev)
1429	{
1430	int reg;
1431
1432	reg = phy_read_mmd(phydev, devad: 2, regnum: 0);
1433	if (reg < 0)
1434	return reg;
1435
1436	if (!(reg & BIT(4)))
1437	return 0;
1438
1439	return phy_set_bits(phydev, regnum: 0x1e, BIT(9));
1440	}
1441
1442	static int ksz9131_config_init(struct phy_device *phydev)
1443	{
1444	struct device_node *of_node;
1445	char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1446	char *rx_data_skews[4] = {
1447	"rxd0-skew-psec", "rxd1-skew-psec",
1448	"rxd2-skew-psec", "rxd3-skew-psec"
1449	};
1450	char *tx_data_skews[4] = {
1451	"txd0-skew-psec", "txd1-skew-psec",
1452	"txd2-skew-psec", "txd3-skew-psec"
1453	};
1454	char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1455	const struct device *dev_walker;
1456	int ret;
1457
1458	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1459
1460	dev_walker = &phydev->mdio.dev;
1461	do {
1462	of_node = dev_walker->of_node;
1463	dev_walker = dev_walker->parent;
1464	} while (!of_node && dev_walker);
1465
1466	if (!of_node)
1467	return 0;
1468
1469	if (phy_interface_is_rgmii(phydev)) {
1470	ret = ksz9131_config_rgmii_delay(phydev);
1471	if (ret < 0)
1472	return ret;
1473	}
1474
1475	ret = ksz9131_of_load_skew_values(phydev, of_node,
1476	MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5,
1477	field: clk_skews, numfields: 2);
1478	if (ret < 0)
1479	return ret;
1480
1481	ret = ksz9131_of_load_skew_values(phydev, of_node,
1482	MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4,
1483	field: control_skews, numfields: 2);
1484	if (ret < 0)
1485	return ret;
1486
1487	ret = ksz9131_of_load_skew_values(phydev, of_node,
1488	MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4,
1489	field: rx_data_skews, numfields: 4);
1490	if (ret < 0)
1491	return ret;
1492
1493	ret = ksz9131_of_load_skew_values(phydev, of_node,
1494	MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4,
1495	field: tx_data_skews, numfields: 4);
1496	if (ret < 0)
1497	return ret;
1498
1499	ret = ksz9131_led_errata(phydev);
1500	if (ret < 0)
1501	return ret;
1502
1503	return 0;
1504	}
1505
1506	#define MII_KSZ9131_AUTO_MDIX 0x1C
1507	#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1508	#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1509	#define MII_KSZ9131_DIG_AXAN_STS 0x14
1510	#define MII_KSZ9131_DIG_AXAN_STS_LINK_DET BIT(14)
1511	#define MII_KSZ9131_DIG_AXAN_STS_A_SELECT BIT(12)
1512
1513	static int ksz9131_mdix_update(struct phy_device *phydev)
1514	{
1515	int ret;
1516
1517	if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {
1518	phydev->mdix = phydev->mdix_ctrl;
1519	} else {
1520	ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);
1521	if (ret < 0)
1522	return ret;
1523
1524	if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {
1525	if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)
1526	phydev->mdix = ETH_TP_MDI;
1527	else
1528	phydev->mdix = ETH_TP_MDI_X;
1529	} else {
1530	phydev->mdix = ETH_TP_MDI_INVALID;
1531	}
1532	}
1533
1534	return 0;
1535	}
1536
1537	static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1538	{
1539	u16 val;
1540
1541	switch (ctrl) {
1542	case ETH_TP_MDI:
1543	val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1544	MII_KSZ9131_AUTO_MDI_SET;
1545	break;
1546	case ETH_TP_MDI_X:
1547	val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1548	break;
1549	case ETH_TP_MDI_AUTO:
1550	val = 0;
1551	break;
1552	default:
1553	return 0;
1554	}
1555
1556	return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1557	MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1558	MII_KSZ9131_AUTO_MDI_SET, set: val);
1559	}
1560
1561	static int ksz9131_read_status(struct phy_device *phydev)
1562	{
1563	int ret;
1564
1565	ret = ksz9131_mdix_update(phydev);
1566	if (ret < 0)
1567	return ret;
1568
1569	return genphy_read_status(phydev);
1570	}
1571
1572	static int ksz9131_config_aneg(struct phy_device *phydev)
1573	{
1574	int ret;
1575
1576	ret = ksz9131_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
1577	if (ret)
1578	return ret;
1579
1580	return genphy_config_aneg(phydev);
1581	}
1582
1583	static int ksz9477_get_features(struct phy_device *phydev)
1584	{
1585	int ret;
1586
1587	ret = genphy_read_abilities(phydev);
1588	if (ret)
1589	return ret;
1590
1591	/* The "EEE control and capability 1" (Register 3.20) seems to be
1592	* influenced by the "EEE advertisement 1" (Register 7.60). Changes
1593	* on the 7.60 will affect 3.20. So, we need to construct our own list
1594	* of caps.
1595	* KSZ8563R should have 100BaseTX/Full only.
1596	*/
1597	linkmode_and(dst: phydev->supported_eee, a: phydev->supported,
1598	PHY_EEE_CAP1_FEATURES);
1599
1600	return 0;
1601	}
1602
1603	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1604	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1605	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1606	static int ksz8873mll_read_status(struct phy_device *phydev)
1607	{
1608	int regval;
1609
1610	/* dummy read */
1611	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1612
1613	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1614
1615	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1616	phydev->duplex = DUPLEX_HALF;
1617	else
1618	phydev->duplex = DUPLEX_FULL;
1619
1620	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1621	phydev->speed = SPEED_10;
1622	else
1623	phydev->speed = SPEED_100;
1624
1625	phydev->link = 1;
1626	phydev->pause = phydev->asym_pause = 0;
1627
1628	return 0;
1629	}
1630
1631	static int ksz9031_get_features(struct phy_device *phydev)
1632	{
1633	int ret;
1634
1635	ret = genphy_read_abilities(phydev);
1636	if (ret < 0)
1637	return ret;
1638
1639	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
1640	* Whenever the device's Asymmetric Pause capability is set to 1,
1641	* link-up may fail after a link-up to link-down transition.
1642	*
1643	* The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1644	*
1645	* Workaround:
1646	* Do not enable the Asymmetric Pause capability bit.
1647	*/
1648	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1649
1650	/* We force setting the Pause capability as the core will force the
1651	* Asymmetric Pause capability to 1 otherwise.
1652	*/
1653	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1654
1655	return 0;
1656	}
1657
1658	static int ksz9031_read_status(struct phy_device *phydev)
1659	{
1660	int err;
1661	int regval;
1662
1663	err = genphy_read_status(phydev);
1664	if (err)
1665	return err;
1666
1667	/* Make sure the PHY is not broken. Read idle error count,
1668	* and reset the PHY if it is maxed out.
1669	*/
1670	regval = phy_read(phydev, MII_STAT1000);
1671	if ((regval & 0xFF) == 0xFF) {
1672	phy_init_hw(phydev);
1673	phydev->link = 0;
1674	if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1675	phydev->drv->config_intr(phydev);
1676	return genphy_config_aneg(phydev);
1677	}
1678
1679	return 0;
1680	}
1681
1682	static int ksz9x31_cable_test_start(struct phy_device *phydev)
1683	{
1684	struct kszphy_priv *priv = phydev->priv;
1685	int ret;
1686
1687	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1688	* Prior to running the cable diagnostics, Auto-negotiation should
1689	* be disabled, full duplex set and the link speed set to 1000Mbps
1690	* via the Basic Control Register.
1691	*/
1692	ret = phy_modify(phydev, MII_BMCR,
1693	BMCR_SPEED1000 | BMCR_FULLDPLX |
1694	BMCR_ANENABLE | BMCR_SPEED100,
1695	BMCR_SPEED1000 | BMCR_FULLDPLX);
1696	if (ret)
1697	return ret;
1698
1699	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1700	* The Master-Slave configuration should be set to Slave by writing
1701	* a value of 0x1000 to the Auto-Negotiation Master Slave Control
1702	* Register.
1703	*/
1704	ret = phy_read(phydev, MII_CTRL1000);
1705	if (ret < 0)
1706	return ret;
1707
1708	/* Cache these bits, they need to be restored once LinkMD finishes. */
1709	priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1710	ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1711	ret |= CTL1000_ENABLE_MASTER;
1712
1713	return phy_write(phydev, MII_CTRL1000, val: ret);
1714	}
1715
1716	static int ksz9x31_cable_test_result_trans(u16 status)
1717	{
1718	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1719	case KSZ9x31_LMD_VCT_ST_NORMAL:
1720	return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1721	case KSZ9x31_LMD_VCT_ST_OPEN:
1722	return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1723	case KSZ9x31_LMD_VCT_ST_SHORT:
1724	return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1725	case KSZ9x31_LMD_VCT_ST_FAIL:
1726	fallthrough;
1727	default:
1728	return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1729	}
1730	}
1731
1732	static bool ksz9x31_cable_test_failed(u16 status)
1733	{
1734	int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1735
1736	return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1737	}
1738
1739	static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1740	{
1741	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1742	case KSZ9x31_LMD_VCT_ST_OPEN:
1743	fallthrough;
1744	case KSZ9x31_LMD_VCT_ST_SHORT:
1745	return true;
1746	}
1747	return false;
1748	}
1749
1750	static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1751	{
1752	int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1753
1754	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1755	*
1756	* distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1757	*/
1758	if (phydev_id_compare(phydev, PHY_ID_KSZ9131) ||
1759	phydev_id_compare(phydev, PHY_ID_KSZ9477))
1760	dt = clamp(dt - 22, 0, 255);
1761
1762	return (dt * 400) / 10;
1763	}
1764
1765	static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1766	{
1767	int val, ret;
1768
1769	ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1770	!(val & KSZ9x31_LMD_VCT_EN),
1771	30000, 100000, true);
1772
1773	return ret < 0 ? ret : 0;
1774	}
1775
1776	static int ksz9x31_cable_test_get_pair(int pair)
1777	{
1778	static const int ethtool_pair[] = {
1779	ETHTOOL_A_CABLE_PAIR_A,
1780	ETHTOOL_A_CABLE_PAIR_B,
1781	ETHTOOL_A_CABLE_PAIR_C,
1782	ETHTOOL_A_CABLE_PAIR_D,
1783	};
1784
1785	return ethtool_pair[pair];
1786	}
1787
1788	static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1789	{
1790	int ret, val;
1791
1792	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1793	* To test each individual cable pair, set the cable pair in the Cable
1794	* Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1795	* Diagnostic Register, along with setting the Cable Diagnostics Test
1796	* Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1797	* will self clear when the test is concluded.
1798	*/
1799	ret = phy_write(phydev, KSZ9x31_LMD,
1800	KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1801	if (ret)
1802	return ret;
1803
1804	ret = ksz9x31_cable_test_wait_for_completion(phydev);
1805	if (ret)
1806	return ret;
1807
1808	val = phy_read(phydev, KSZ9x31_LMD);
1809	if (val < 0)
1810	return val;
1811
1812	if (ksz9x31_cable_test_failed(status: val))
1813	return -EAGAIN;
1814
1815	ret = ethnl_cable_test_result(phydev,
1816	pair: ksz9x31_cable_test_get_pair(pair),
1817	result: ksz9x31_cable_test_result_trans(status: val));
1818	if (ret)
1819	return ret;
1820
1821	if (!ksz9x31_cable_test_fault_length_valid(status: val))
1822	return 0;
1823
1824	return ethnl_cable_test_fault_length(phydev,
1825	pair: ksz9x31_cable_test_get_pair(pair),
1826	cm: ksz9x31_cable_test_fault_length(phydev, stat: val));
1827	}
1828
1829	static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1830	bool *finished)
1831	{
1832	struct kszphy_priv *priv = phydev->priv;
1833	unsigned long pair_mask;
1834	int retries = 20;
1835	int pair, ret, rv;
1836
1837	*finished = false;
1838
1839	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1840	phydev->supported) ||
1841	linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1842	phydev->supported))
1843	pair_mask = 0xf; /* All pairs */
1844	else
1845	pair_mask = 0x3; /* Pairs A and B only */
1846
1847	/* Try harder if link partner is active */
1848	while (pair_mask && retries--) {
1849	for_each_set_bit(pair, &pair_mask, 4) {
1850	ret = ksz9x31_cable_test_one_pair(phydev, pair);
1851	if (ret == -EAGAIN)
1852	continue;
1853	if (ret < 0)
1854	return ret;
1855	clear_bit(nr: pair, addr: &pair_mask);
1856	}
1857	/* If link partner is in autonegotiation mode it will send 2ms
1858	* of FLPs with at least 6ms of silence.
1859	* Add 2ms sleep to have better chances to hit this silence.
1860	*/
1861	if (pair_mask)
1862	usleep_range(min: 2000, max: 3000);
1863	}
1864
1865	/* Report remaining unfinished pair result as unknown. */
1866	for_each_set_bit(pair, &pair_mask, 4) {
1867	ret = ethnl_cable_test_result(phydev,
1868	pair: ksz9x31_cable_test_get_pair(pair),
1869	result: ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1870	}
1871
1872	*finished = true;
1873
1874	/* Restore cached bits from before LinkMD got started. */
1875	rv = phy_modify(phydev, MII_CTRL1000,
1876	CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1877	set: priv->vct_ctrl1000);
1878	if (rv)
1879	return rv;
1880
1881	return ret;
1882	}
1883
1884	static int ksz8873mll_config_aneg(struct phy_device *phydev)
1885	{
1886	return 0;
1887	}
1888
1889	static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1890	{
1891	u16 val;
1892
1893	switch (ctrl) {
1894	case ETH_TP_MDI:
1895	val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1896	break;
1897	case ETH_TP_MDI_X:
1898	/* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1899	* counter intuitive, the "-X" in "1 = Force MDI" in the data
1900	* sheet seems to be missing:
1901	* 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1902	* 0 = Normal operation (transmit on TX+/TX- pins)
1903	*/
1904	val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1905	break;
1906	case ETH_TP_MDI_AUTO:
1907	val = 0;
1908	break;
1909	default:
1910	return 0;
1911	}
1912
1913	return phy_modify(phydev, MII_BMCR,
1914	KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1915	KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1916	KSZ886X_BMCR_HP_MDIX | val);
1917	}
1918
1919	static int ksz886x_config_aneg(struct phy_device *phydev)
1920	{
1921	int ret;
1922
1923	ret = genphy_config_aneg(phydev);
1924	if (ret)
1925	return ret;
1926
1927	if (phydev->autoneg != AUTONEG_ENABLE) {
1928	/* When autonegotiation is disabled, we need to manually force
1929	* the link state. If we don't do this, the PHY will keep
1930	* sending Fast Link Pulses (FLPs) which are part of the
1931	* autonegotiation process. This is not desired when
1932	* autonegotiation is off.
1933	*/
1934	ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1935	KSZ886X_CTRL_FORCE_LINK);
1936	if (ret)
1937	return ret;
1938	} else {
1939	/* If we had previously forced the link state, we need to
1940	* clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1941	* will not perform autonegotiation.
1942	*/
1943	ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1944	KSZ886X_CTRL_FORCE_LINK);
1945	if (ret)
1946	return ret;
1947	}
1948
1949	/* The MDI-X configuration is automatically changed by the PHY after
1950	* switching from autoneg off to on. So, take MDI-X configuration under
1951	* own control and set it after autoneg configuration was done.
1952	*/
1953	return ksz886x_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
1954	}
1955
1956	static int ksz886x_mdix_update(struct phy_device *phydev)
1957	{
1958	int ret;
1959
1960	ret = phy_read(phydev, MII_BMCR);
1961	if (ret < 0)
1962	return ret;
1963
1964	if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1965	if (ret & KSZ886X_BMCR_FORCE_MDI)
1966	phydev->mdix_ctrl = ETH_TP_MDI_X;
1967	else
1968	phydev->mdix_ctrl = ETH_TP_MDI;
1969	} else {
1970	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1971	}
1972
1973	ret = phy_read(phydev, MII_KSZPHY_CTRL);
1974	if (ret < 0)
1975	return ret;
1976
1977	/* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1978	if (ret & KSZ886X_CTRL_MDIX_STAT)
1979	phydev->mdix = ETH_TP_MDI_X;
1980	else
1981	phydev->mdix = ETH_TP_MDI;
1982
1983	return 0;
1984	}
1985
1986	static int ksz886x_read_status(struct phy_device *phydev)
1987	{
1988	int ret;
1989
1990	ret = ksz886x_mdix_update(phydev);
1991	if (ret < 0)
1992	return ret;
1993
1994	return genphy_read_status(phydev);
1995	}
1996
1997	static int ksz9477_mdix_update(struct phy_device *phydev)
1998	{
1999	if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO)
2000	phydev->mdix = phydev->mdix_ctrl;
2001	else
2002	phydev->mdix = ETH_TP_MDI_INVALID;
2003
2004	return 0;
2005	}
2006
2007	static int ksz9477_read_mdix_ctrl(struct phy_device *phydev)
2008	{
2009	int val;
2010
2011	val = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
2012	if (val < 0)
2013	return val;
2014
2015	if (!(val & MII_KSZ9131_AUTO_MDIX_SWAP_OFF))
2016	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
2017	else if (val & MII_KSZ9131_AUTO_MDI_SET)
2018	phydev->mdix_ctrl = ETH_TP_MDI;
2019	else
2020	phydev->mdix_ctrl = ETH_TP_MDI_X;
2021
2022	return 0;
2023	}
2024
2025	static int ksz9477_read_status(struct phy_device *phydev)
2026	{
2027	int ret;
2028
2029	ret = ksz9477_mdix_update(phydev);
2030	if (ret)
2031	return ret;
2032
2033	return genphy_read_status(phydev);
2034	}
2035
2036	static int ksz9477_config_aneg(struct phy_device *phydev)
2037	{
2038	int ret;
2039
2040	ret = ksz9131_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
2041	if (ret)
2042	return ret;
2043
2044	return genphy_config_aneg(phydev);
2045	}
2046
2047	struct ksz9477_errata_write {
2048	u8 dev_addr;
2049	u8 reg_addr;
2050	u16 val;
2051	};
2052
2053	static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
2054	/* Register settings are needed to improve PHY receive performance */
2055	{0x01, 0x6f, 0xdd0b},
2056	{0x01, 0x8f, 0x6032},
2057	{0x01, 0x9d, 0x248c},
2058	{0x01, 0x75, 0x0060},
2059	{0x01, 0xd3, 0x7777},
2060	{0x1c, 0x06, 0x3008},
2061	{0x1c, 0x08, 0x2000},
2062
2063	/* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
2064	{0x1c, 0x04, 0x00d0},
2065
2066	/* Register settings are required to meet data sheet supply current specifications */
2067	{0x1c, 0x13, 0x6eff},
2068	{0x1c, 0x14, 0xe6ff},
2069	{0x1c, 0x15, 0x6eff},
2070	{0x1c, 0x16, 0xe6ff},
2071	{0x1c, 0x17, 0x00ff},
2072	{0x1c, 0x18, 0x43ff},
2073	{0x1c, 0x19, 0xc3ff},
2074	{0x1c, 0x1a, 0x6fff},
2075	{0x1c, 0x1b, 0x07ff},
2076	{0x1c, 0x1c, 0x0fff},
2077	{0x1c, 0x1d, 0xe7ff},
2078	{0x1c, 0x1e, 0xefff},
2079	{0x1c, 0x20, 0xeeee},
2080	};
2081
2082	static int ksz9477_phy_errata(struct phy_device *phydev)
2083	{
2084	int err;
2085	int i;
2086
2087	/* Apply PHY settings to address errata listed in
2088	* KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
2089	* Silicon Errata and Data Sheet Clarification documents.
2090	*
2091	* Document notes: Before configuring the PHY MMD registers, it is
2092	* necessary to set the PHY to 100 Mbps speed with auto-negotiation
2093	* disabled by writing to register 0xN100-0xN101. After writing the
2094	* MMD registers, and after all errata workarounds that involve PHY
2095	* register settings, write register 0xN100-0xN101 again to enable
2096	* and restart auto-negotiation.
2097	*/
2098	err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
2099	if (err)
2100	return err;
2101
2102	for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
2103	const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
2104
2105	err = phy_write_mmd(phydev, devad: errata->dev_addr, regnum: errata->reg_addr, val: errata->val);
2106	if (err)
2107	return err;
2108	}
2109
2110	return genphy_restart_aneg(phydev);
2111	}
2112
2113	static int ksz9477_config_init(struct phy_device *phydev)
2114	{
2115	int err;
2116
2117	/* Only KSZ9897 family of switches needs this fix. */
2118	if ((phydev->phy_id & 0xf) == 1) {
2119	err = ksz9477_phy_errata(phydev);
2120	if (err)
2121	return err;
2122	}
2123
2124	/* Read initial MDI-X config state. So, we do not need to poll it
2125	* later on.
2126	*/
2127	err = ksz9477_read_mdix_ctrl(phydev);
2128	if (err)
2129	return err;
2130
2131	return kszphy_config_init(phydev);
2132	}
2133
2134	static int kszphy_get_sset_count(struct phy_device *phydev)
2135	{
2136	return ARRAY_SIZE(kszphy_hw_stats);
2137	}
2138
2139	static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
2140	{
2141	int i;
2142
2143	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2144	ethtool_puts(data: &data, str: kszphy_hw_stats[i].string);
2145	}
2146
2147	static u64 kszphy_get_stat(struct phy_device *phydev, int i)
2148	{
2149	struct kszphy_hw_stat stat = kszphy_hw_stats[i];
2150	struct kszphy_priv *priv = phydev->priv;
2151	int val;
2152	u64 ret;
2153
2154	val = phy_read(phydev, regnum: stat.reg);
2155	if (val < 0) {
2156	ret = U64_MAX;
2157	} else {
2158	val = val & ((1 << stat.bits) - 1);
2159	priv->stats[i] += val;
2160	ret = priv->stats[i];
2161	}
2162
2163	return ret;
2164	}
2165
2166	static void kszphy_get_stats(struct phy_device *phydev,
2167	struct ethtool_stats *stats, u64 *data)
2168	{
2169	int i;
2170
2171	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2172	data[i] = kszphy_get_stat(phydev, i);
2173	}
2174
2175	/* KSZ9477 PHY RXER Counter. Probably supported by other PHYs like KSZ9313,
2176	* etc. The counter is incremented when the PHY receives a frame with one or
2177	* more symbol errors. The counter is cleared when the register is read.
2178	*/
2179	#define MII_KSZ9477_PHY_RXER_COUNTER 0x15
2180
2181	static int kszphy_update_stats(struct phy_device *phydev)
2182	{
2183	struct kszphy_priv *priv = phydev->priv;
2184	int ret;
2185
2186	ret = phy_read(phydev, MII_KSZ9477_PHY_RXER_COUNTER);
2187	if (ret < 0)
2188	return ret;
2189
2190	priv->phy_stats.rx_err_pkt_cnt += ret;
2191
2192	return 0;
2193	}
2194
2195	static void kszphy_get_phy_stats(struct phy_device *phydev,
2196	struct ethtool_eth_phy_stats *eth_stats,
2197	struct ethtool_phy_stats *stats)
2198	{
2199	struct kszphy_priv *priv = phydev->priv;
2200
2201	stats->rx_errors = priv->phy_stats.rx_err_pkt_cnt;
2202	}
2203
2204	/* Base register for Signal Quality Indicator (SQI) - Channel A
2205	*
2206	* MMD Address: MDIO_MMD_PMAPMD (0x01)
2207	* Register: 0xAC (Channel A)
2208	* Each channel (pair) has its own register:
2209	* Channel A: 0xAC
2210	* Channel B: 0xAD
2211	* Channel C: 0xAE
2212	* Channel D: 0xAF
2213	*/
2214	#define KSZ9477_MMD_SIGNAL_QUALITY_CHAN_A 0xac
2215
2216	/* SQI field mask for bits [14:8]
2217	*
2218	* SQI indicates relative quality of the signal.
2219	* A lower value indicates better signal quality.
2220	*/
2221	#define KSZ9477_MMD_SQI_MASK GENMASK(14, 8)
2222
2223	#define KSZ9477_MAX_CHANNELS 4
2224	#define KSZ9477_SQI_MAX 7
2225
2226	/* Number of SQI samples to average for a stable result.
2227	*
2228	* Reference: KSZ9477S Datasheet DS00002392C, Section 4.1.11 (page 26)
2229	* For noisy environments, a minimum of 30–50 readings is recommended.
2230	*/
2231	#define KSZ9477_SQI_SAMPLE_COUNT 40
2232
2233	/* The hardware SQI register provides a raw value from 0-127, where a lower
2234	* value indicates better signal quality. However, empirical testing has
2235	* shown that only the 0-7 range is relevant for a functional link. A raw
2236	* value of 8 or higher was measured directly before link drop. This aligns
2237	* with the OPEN Alliance recommendation that SQI=0 should represent the
2238	* pre-failure state.
2239	*
2240	* This table provides a non-linear mapping from the useful raw hardware
2241	* values (0-7) to the standard 0-7 SQI scale, where higher is better.
2242	*/
2243	static const u8 ksz_sqi_mapping[] = {
2244	7, /* raw 0 -> SQI 7 */
2245	7, /* raw 1 -> SQI 7 */
2246	6, /* raw 2 -> SQI 6 */
2247	5, /* raw 3 -> SQI 5 */
2248	4, /* raw 4 -> SQI 4 */
2249	3, /* raw 5 -> SQI 3 */
2250	2, /* raw 6 -> SQI 2 */
2251	1, /* raw 7 -> SQI 1 */
2252	};
2253
2254	/**
2255	* kszphy_get_sqi - Read, average, and map Signal Quality Index (SQI)
2256	* @phydev: the PHY device
2257	*
2258	* This function reads and processes the raw Signal Quality Index from the
2259	* PHY. Based on empirical testing, a raw value of 8 or higher indicates a
2260	* pre-failure state and is mapped to SQI 0. Raw values from 0-7 are
2261	* mapped to the standard 0-7 SQI scale via a lookup table.
2262	*
2263	* Return: SQI value (0–7), or a negative errno on failure.
2264	*/
2265	static int kszphy_get_sqi(struct phy_device *phydev)
2266	{
2267	int sum[KSZ9477_MAX_CHANNELS] = { 0 };
2268	int worst_sqi = KSZ9477_SQI_MAX;
2269	int i, val, raw_sqi, ch;
2270	u8 channels;
2271
2272	/* Determine applicable channels based on link speed */
2273	if (phydev->speed == SPEED_1000)
2274	channels = 4;
2275	else if (phydev->speed == SPEED_100)
2276	channels = 1;
2277	else
2278	return -EOPNOTSUPP;
2279
2280	/* Sample and accumulate SQI readings for each pair (currently only one).
2281	*
2282	* Reference: KSZ9477S Datasheet DS00002392C, Section 4.1.11 (page 26)
2283	* - The SQI register is updated every 2 µs.
2284	* - Values may fluctuate significantly, even in low-noise environments.
2285	* - For reliable estimation, average a minimum of 30–50 samples
2286	* (recommended for noisy environments)
2287	* - In noisy environments, individual readings are highly unreliable.
2288	*
2289	* We use 40 samples per pair with a delay of 3 µs between each
2290	* read to ensure new values are captured (2 µs update interval).
2291	*/
2292	for (i = 0; i < KSZ9477_SQI_SAMPLE_COUNT; i++) {
2293	for (ch = 0; ch < channels; ch++) {
2294	val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
2295	KSZ9477_MMD_SIGNAL_QUALITY_CHAN_A + ch);
2296	if (val < 0)
2297	return val;
2298
2299	raw_sqi = FIELD_GET(KSZ9477_MMD_SQI_MASK, val);
2300	sum[ch] += raw_sqi;
2301
2302	/* We communicate with the PHY via MDIO via SPI or
2303	* I2C, which is relatively slow. At least slower than
2304	* the update interval of the SQI register.
2305	* So, we can skip the delay between reads.
2306	*/
2307	}
2308	}
2309
2310	/* Calculate average for each channel and find the worst SQI */
2311	for (ch = 0; ch < channels; ch++) {
2312	int avg_raw_sqi = sum[ch] / KSZ9477_SQI_SAMPLE_COUNT;
2313	int mapped_sqi;
2314
2315	/* Handle the pre-fail/failed state first. */
2316	if (avg_raw_sqi >= ARRAY_SIZE(ksz_sqi_mapping))
2317	mapped_sqi = 0;
2318	else
2319	/* Use the lookup table for the good signal range. */
2320	mapped_sqi = ksz_sqi_mapping[avg_raw_sqi];
2321
2322	if (mapped_sqi < worst_sqi)
2323	worst_sqi = mapped_sqi;
2324	}
2325
2326	return worst_sqi;
2327	}
2328
2329	static int kszphy_get_sqi_max(struct phy_device *phydev)
2330	{
2331	return KSZ9477_SQI_MAX;
2332	}
2333
2334	static int kszphy_get_mse_capability(struct phy_device *phydev,
2335	struct phy_mse_capability *cap)
2336	{
2337	/* Capabilities depend on link mode:
2338	* - 1000BASE-T: per-pair SQI registers exist => expose A..D
2339	* and a WORST selector.
2340	* - 100BASE-TX: HW provides a single MSE/SQI reading in the "channel A"
2341	* register, but with auto MDI-X there is no MDI-X resolution bit,
2342	* so we cannot map that register to a specific wire pair reliably.
2343	* To avoid misleading per-channel data, advertise only LINK.
2344	* Other speeds: no MSE exposure via this driver.
2345	*
2346	* Note: WORST is *not* a hardware selector on this family.
2347	* We expose it because the driver computes it in software
2348	* by scanning per-channel readouts (A..D) and picking the
2349	* maximum average MSE.
2350	*/
2351	if (phydev->speed == SPEED_1000)
2352	cap->supported_caps = PHY_MSE_CAP_CHANNEL_A |
2353	PHY_MSE_CAP_CHANNEL_B |
2354	PHY_MSE_CAP_CHANNEL_C |
2355	PHY_MSE_CAP_CHANNEL_D |
2356	PHY_MSE_CAP_WORST_CHANNEL;
2357	else if (phydev->speed == SPEED_100)
2358	cap->supported_caps = PHY_MSE_CAP_LINK;
2359	else
2360	return -EOPNOTSUPP;
2361
2362	cap->max_average_mse = FIELD_MAX(KSZ9477_MMD_SQI_MASK);
2363	cap->refresh_rate_ps = 2000000; /* 2 us */
2364	/* Estimated from link modulation (125 MBd per channel) and documented
2365	* refresh rate of 2 us
2366	*/
2367	cap->num_symbols = 250;
2368
2369	cap->supported_caps |= PHY_MSE_CAP_AVG;
2370
2371	return 0;
2372	}
2373
2374	static int kszphy_get_mse_snapshot(struct phy_device *phydev,
2375	enum phy_mse_channel channel,
2376	struct phy_mse_snapshot *snapshot)
2377	{
2378	u8 num_channels;
2379	int ret;
2380
2381	if (phydev->speed == SPEED_1000)
2382	num_channels = 4;
2383	else if (phydev->speed == SPEED_100)
2384	num_channels = 1;
2385	else
2386	return -EOPNOTSUPP;
2387
2388	if (channel == PHY_MSE_CHANNEL_WORST) {
2389	u32 worst_val = 0;
2390	int i;
2391
2392	/* WORST is implemented in software: select the maximum
2393	* average MSE across the available per-channel registers.
2394	* Only defined when multiple channels exist (1000BASE-T).
2395	*/
2396	if (num_channels < 2)
2397	return -EOPNOTSUPP;
2398
2399	for (i = 0; i < num_channels; i++) {
2400	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
2401	KSZ9477_MMD_SIGNAL_QUALITY_CHAN_A + i);
2402	if (ret < 0)
2403	return ret;
2404
2405	ret = FIELD_GET(KSZ9477_MMD_SQI_MASK, ret);
2406	if (ret > worst_val)
2407	worst_val = ret;
2408	}
2409	snapshot->average_mse = worst_val;
2410	} else if (channel == PHY_MSE_CHANNEL_LINK && num_channels == 1) {
2411	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
2412	KSZ9477_MMD_SIGNAL_QUALITY_CHAN_A);
2413	if (ret < 0)
2414	return ret;
2415	snapshot->average_mse = FIELD_GET(KSZ9477_MMD_SQI_MASK, ret);
2416	} else if (channel >= PHY_MSE_CHANNEL_A &&
2417	channel <= PHY_MSE_CHANNEL_D) {
2418	/* Per-channel readouts are valid only for 1000BASE-T. */
2419	if (phydev->speed != SPEED_1000)
2420	return -EOPNOTSUPP;
2421
2422	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
2423	KSZ9477_MMD_SIGNAL_QUALITY_CHAN_A + channel);
2424	if (ret < 0)
2425	return ret;
2426	snapshot->average_mse = FIELD_GET(KSZ9477_MMD_SQI_MASK, ret);
2427	} else {
2428	return -EOPNOTSUPP;
2429	}
2430
2431	return 0;
2432	}
2433
2434	static void kszphy_enable_clk(struct phy_device *phydev)
2435	{
2436	struct kszphy_priv *priv = phydev->priv;
2437
2438	if (!priv->clk_enable && priv->clk) {
2439	clk_prepare_enable(clk: priv->clk);
2440	priv->clk_enable = true;
2441	}
2442	}
2443
2444	static void kszphy_disable_clk(struct phy_device *phydev)
2445	{
2446	struct kszphy_priv *priv = phydev->priv;
2447
2448	if (priv->clk_enable && priv->clk) {
2449	clk_disable_unprepare(clk: priv->clk);
2450	priv->clk_enable = false;
2451	}
2452	}
2453
2454	static int kszphy_generic_resume(struct phy_device *phydev)
2455	{
2456	kszphy_enable_clk(phydev);
2457
2458	return genphy_resume(phydev);
2459	}
2460
2461	static int kszphy_generic_suspend(struct phy_device *phydev)
2462	{
2463	int ret;
2464
2465	ret = genphy_suspend(phydev);
2466	if (ret)
2467	return ret;
2468
2469	kszphy_disable_clk(phydev);
2470
2471	return 0;
2472	}
2473
2474	static int kszphy_suspend(struct phy_device *phydev)
2475	{
2476	/* Disable PHY Interrupts */
2477	if (phy_interrupt_is_valid(phydev)) {
2478	phydev->interrupts = PHY_INTERRUPT_DISABLED;
2479	if (phydev->drv->config_intr)
2480	phydev->drv->config_intr(phydev);
2481	}
2482
2483	return kszphy_generic_suspend(phydev);
2484	}
2485
2486	static void kszphy_parse_led_mode(struct phy_device *phydev)
2487	{
2488	const struct kszphy_type *type = phydev->drv->driver_data;
2489	const struct device_node *np = phydev->mdio.dev.of_node;
2490	struct kszphy_priv *priv = phydev->priv;
2491	int ret;
2492
2493	if (type && type->led_mode_reg) {
2494	ret = of_property_read_u32(np, propname: "micrel,led-mode",
2495	out_value: &priv->led_mode);
2496
2497	if (ret)
2498	priv->led_mode = -1;
2499
2500	if (priv->led_mode > 3) {
2501	phydev_err(phydev, "invalid led mode: 0x%02x\n",
2502	priv->led_mode);
2503	priv->led_mode = -1;
2504	}
2505	} else {
2506	priv->led_mode = -1;
2507	}
2508	}
2509
2510	static int kszphy_resume(struct phy_device *phydev)
2511	{
2512	int ret;
2513
2514	ret = kszphy_generic_resume(phydev);
2515	if (ret)
2516	return ret;
2517
2518	/* After switching from power-down to normal mode, an internal global
2519	* reset is automatically generated. Wait a minimum of 1 ms before
2520	* read/write access to the PHY registers.
2521	*/
2522	usleep_range(min: 1000, max: 2000);
2523
2524	ret = kszphy_config_reset(phydev);
2525	if (ret)
2526	return ret;
2527
2528	/* Enable PHY Interrupts */
2529	if (phy_interrupt_is_valid(phydev)) {
2530	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2531	if (phydev->drv->config_intr)
2532	phydev->drv->config_intr(phydev);
2533	}
2534
2535	return 0;
2536	}
2537
2538	/* Because of errata DS80000700A, receiver error following software
2539	* power down. Suspend and resume callbacks only disable and enable
2540	* external rmii reference clock.
2541	*/
2542	static int ksz8041_resume(struct phy_device *phydev)
2543	{
2544	kszphy_enable_clk(phydev);
2545
2546	return 0;
2547	}
2548
2549	static int ksz8041_suspend(struct phy_device *phydev)
2550	{
2551	kszphy_disable_clk(phydev);
2552
2553	return 0;
2554	}
2555
2556	static int ksz9477_resume(struct phy_device *phydev)
2557	{
2558	int ret;
2559
2560	/* No need to initialize registers if not powered down. */
2561	ret = phy_read(phydev, MII_BMCR);
2562	if (ret < 0)
2563	return ret;
2564	if (!(ret & BMCR_PDOWN))
2565	return 0;
2566
2567	genphy_resume(phydev);
2568
2569	/* After switching from power-down to normal mode, an internal global
2570	* reset is automatically generated. Wait a minimum of 1 ms before
2571	* read/write access to the PHY registers.
2572	*/
2573	usleep_range(min: 1000, max: 2000);
2574
2575	/* Only KSZ9897 family of switches needs this fix. */
2576	if ((phydev->phy_id & 0xf) == 1) {
2577	ret = ksz9477_phy_errata(phydev);
2578	if (ret)
2579	return ret;
2580	}
2581
2582	/* Enable PHY Interrupts */
2583	if (phy_interrupt_is_valid(phydev)) {
2584	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2585	if (phydev->drv->config_intr)
2586	phydev->drv->config_intr(phydev);
2587	}
2588
2589	return 0;
2590	}
2591
2592	static int ksz8061_resume(struct phy_device *phydev)
2593	{
2594	int ret;
2595
2596	/* This function can be called twice when the Ethernet device is on. */
2597	ret = phy_read(phydev, MII_BMCR);
2598	if (ret < 0)
2599	return ret;
2600	if (!(ret & BMCR_PDOWN))
2601	return 0;
2602
2603	ret = kszphy_generic_resume(phydev);
2604	if (ret)
2605	return ret;
2606
2607	usleep_range(min: 1000, max: 2000);
2608
2609	/* Re-program the value after chip is reset. */
2610	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, val: 0xB61A);
2611	if (ret)
2612	return ret;
2613
2614	/* Enable PHY Interrupts */
2615	if (phy_interrupt_is_valid(phydev)) {
2616	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2617	if (phydev->drv->config_intr)
2618	phydev->drv->config_intr(phydev);
2619	}
2620
2621	return 0;
2622	}
2623
2624	static int ksz8061_suspend(struct phy_device *phydev)
2625	{
2626	return kszphy_suspend(phydev);
2627	}
2628
2629	static int kszphy_probe(struct phy_device *phydev)
2630	{
2631	const struct kszphy_type *type = phydev->drv->driver_data;
2632	const struct device_node *np = phydev->mdio.dev.of_node;
2633	struct kszphy_priv *priv;
2634	struct clk *clk;
2635
2636	priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL);
2637	if (!priv)
2638	return -ENOMEM;
2639
2640	phydev->priv = priv;
2641
2642	priv->type = type;
2643
2644	kszphy_parse_led_mode(phydev);
2645
2646	clk = devm_clk_get_optional(dev: &phydev->mdio.dev, id: "rmii-ref");
2647	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2648	if (!IS_ERR_OR_NULL(ptr: clk)) {
2649	bool rmii_ref_clk_sel_25_mhz;
2650	unsigned long rate;
2651	int err;
2652
2653	err = clk_prepare_enable(clk);
2654	if (err) {
2655	phydev_err(phydev, "Failed to enable rmii-ref clock\n");
2656	return err;
2657	}
2658
2659	rate = clk_get_rate(clk);
2660	clk_disable_unprepare(clk);
2661
2662	if (type)
2663	priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2664	rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2665	propname: "micrel,rmii-reference-clock-select-25-mhz");
2666
2667	if (rate > 24500000 && rate < 25500000) {
2668	priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2669	} else if (rate > 49500000 && rate < 50500000) {
2670	priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2671	} else {
2672	phydev_err(phydev, "Clock rate out of range: %ld\n",
2673	rate);
2674	return -EINVAL;
2675	}
2676	} else if (!clk) {
2677	/* unnamed clock from the generic ethernet-phy binding */
2678	clk = devm_clk_get_optional(dev: &phydev->mdio.dev, NULL);
2679	}
2680
2681	if (IS_ERR(ptr: clk))
2682	return PTR_ERR(ptr: clk);
2683
2684	priv->clk = clk;
2685
2686	if (ksz8041_fiber_mode(phydev))
2687	phydev->port = PORT_FIBRE;
2688
2689	/* Support legacy board-file configuration */
2690	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2691	priv->rmii_ref_clk_sel = true;
2692	priv->rmii_ref_clk_sel_val = true;
2693	}
2694
2695	return 0;
2696	}
2697
2698	static int lan8814_cable_test_start(struct phy_device *phydev)
2699	{
2700	/* If autoneg is enabled, we won't be able to test cross pair
2701	* short. In this case, the PHY will "detect" a link and
2702	* confuse the internal state machine - disable auto neg here.
2703	* Set the speed to 1000mbit and full duplex.
2704	*/
2705	return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2706	BMCR_SPEED1000 | BMCR_FULLDPLX);
2707	}
2708
2709	static int ksz886x_cable_test_start(struct phy_device *phydev)
2710	{
2711	if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2712	return -EOPNOTSUPP;
2713
2714	/* If autoneg is enabled, we won't be able to test cross pair
2715	* short. In this case, the PHY will "detect" a link and
2716	* confuse the internal state machine - disable auto neg here.
2717	* If autoneg is disabled, we should set the speed to 10mbit.
2718	*/
2719	return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2720	}
2721
2722	static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2723	{
2724	switch (FIELD_GET(mask, status)) {
2725	case KSZ8081_LMD_STAT_NORMAL:
2726	return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2727	case KSZ8081_LMD_STAT_SHORT:
2728	return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2729	case KSZ8081_LMD_STAT_OPEN:
2730	return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2731	case KSZ8081_LMD_STAT_FAIL:
2732	fallthrough;
2733	default:
2734	return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2735	}
2736	}
2737
2738	static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2739	{
2740	return FIELD_GET(mask, status) ==
2741	KSZ8081_LMD_STAT_FAIL;
2742	}
2743
2744	static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2745	{
2746	switch (FIELD_GET(mask, status)) {
2747	case KSZ8081_LMD_STAT_OPEN:
2748	fallthrough;
2749	case KSZ8081_LMD_STAT_SHORT:
2750	return true;
2751	}
2752	return false;
2753	}
2754
2755	static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2756	u16 status, u16 data_mask)
2757	{
2758	int dt;
2759
2760	/* According to the data sheet the distance to the fault is
2761	* DELTA_TIME * 0.4 meters for ksz phys.
2762	* (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2763	*/
2764	dt = FIELD_GET(data_mask, status);
2765
2766	if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2767	return ((dt - 22) * 800) / 10;
2768	else
2769	return (dt * 400) / 10;
2770	}
2771
2772	static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2773	{
2774	const struct kszphy_type *type = phydev->drv->driver_data;
2775	int val, ret;
2776
2777	ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2778	!(val & KSZ8081_LMD_ENABLE_TEST),
2779	30000, 100000, true);
2780
2781	return ret < 0 ? ret : 0;
2782	}
2783
2784	static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2785	{
2786	static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2787	ETHTOOL_A_CABLE_PAIR_B,
2788	ETHTOOL_A_CABLE_PAIR_C,
2789	ETHTOOL_A_CABLE_PAIR_D,
2790	};
2791	u32 fault_length;
2792	int ret;
2793	int val;
2794
2795	val = KSZ8081_LMD_ENABLE_TEST;
2796	val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2797
2798	ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2799	if (ret < 0)
2800	return ret;
2801
2802	ret = ksz886x_cable_test_wait_for_completion(phydev);
2803	if (ret)
2804	return ret;
2805
2806	val = phy_read(phydev, LAN8814_CABLE_DIAG);
2807	if (val < 0)
2808	return val;
2809
2810	if (ksz886x_cable_test_failed(status: val, LAN8814_CABLE_DIAG_STAT_MASK))
2811	return -EAGAIN;
2812
2813	ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
2814	result: ksz886x_cable_test_result_trans(status: val,
2815	LAN8814_CABLE_DIAG_STAT_MASK
2816	));
2817	if (ret)
2818	return ret;
2819
2820	if (!ksz886x_cable_test_fault_length_valid(status: val, LAN8814_CABLE_DIAG_STAT_MASK))
2821	return 0;
2822
2823	fault_length = ksz886x_cable_test_fault_length(phydev, status: val,
2824	LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2825
2826	return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length);
2827	}
2828
2829	static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2830	{
2831	static const int ethtool_pair[] = {
2832	ETHTOOL_A_CABLE_PAIR_A,
2833	ETHTOOL_A_CABLE_PAIR_B,
2834	};
2835	int ret, val, mdix;
2836	u32 fault_length;
2837
2838	/* There is no way to choice the pair, like we do one ksz9031.
2839	* We can workaround this limitation by using the MDI-X functionality.
2840	*/
2841	if (pair == 0)
2842	mdix = ETH_TP_MDI;
2843	else
2844	mdix = ETH_TP_MDI_X;
2845
2846	switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2847	case PHY_ID_KSZ8081:
2848	ret = ksz8081_config_mdix(phydev, ctrl: mdix);
2849	break;
2850	case PHY_ID_KSZ886X:
2851	ret = ksz886x_config_mdix(phydev, ctrl: mdix);
2852	break;
2853	default:
2854	ret = -ENODEV;
2855	}
2856
2857	if (ret)
2858	return ret;
2859
2860	/* Now we are ready to fire. This command will send a 100ns pulse
2861	* to the pair.
2862	*/
2863	ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2864	if (ret)
2865	return ret;
2866
2867	ret = ksz886x_cable_test_wait_for_completion(phydev);
2868	if (ret)
2869	return ret;
2870
2871	val = phy_read(phydev, KSZ8081_LMD);
2872	if (val < 0)
2873	return val;
2874
2875	if (ksz886x_cable_test_failed(status: val, KSZ8081_LMD_STAT_MASK))
2876	return -EAGAIN;
2877
2878	ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
2879	result: ksz886x_cable_test_result_trans(status: val, KSZ8081_LMD_STAT_MASK));
2880	if (ret)
2881	return ret;
2882
2883	if (!ksz886x_cable_test_fault_length_valid(status: val, KSZ8081_LMD_STAT_MASK))
2884	return 0;
2885
2886	fault_length = ksz886x_cable_test_fault_length(phydev, status: val, KSZ8081_LMD_DELTA_TIME_MASK);
2887
2888	return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length);
2889	}
2890
2891	static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2892	bool *finished)
2893	{
2894	const struct kszphy_type *type = phydev->drv->driver_data;
2895	unsigned long pair_mask = type->pair_mask;
2896	int retries = 20;
2897	int ret = 0;
2898	int pair;
2899
2900	*finished = false;
2901
2902	/* Try harder if link partner is active */
2903	while (pair_mask && retries--) {
2904	for_each_set_bit(pair, &pair_mask, 4) {
2905	if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2906	ret = lan8814_cable_test_one_pair(phydev, pair);
2907	else
2908	ret = ksz886x_cable_test_one_pair(phydev, pair);
2909	if (ret == -EAGAIN)
2910	continue;
2911	if (ret < 0)
2912	return ret;
2913	clear_bit(nr: pair, addr: &pair_mask);
2914	}
2915	/* If link partner is in autonegotiation mode it will send 2ms
2916	* of FLPs with at least 6ms of silence.
2917	* Add 2ms sleep to have better chances to hit this silence.
2918	*/
2919	if (pair_mask)
2920	msleep(msecs: 2);
2921	}
2922
2923	*finished = true;
2924
2925	return ret;
2926	}
2927
2928	/**
2929	* LAN8814_PAGE_PCS - Selects Extended Page 0.
2930	*
2931	* This page contains timers used for auto-negotiation, debug registers and
2932	* register to configure fast link failure.
2933	*/
2934	#define LAN8814_PAGE_PCS 0
2935
2936	/**
2937	* LAN8814_PAGE_AFE_PMA - Selects Extended Page 1.
2938	*
2939	* This page appears to control the Analog Front-End (AFE) and Physical
2940	* Medium Attachment (PMA) layers. It is used to access registers like
2941	* LAN8814_PD_CONTROLS and LAN8814_LINK_QUALITY.
2942	*/
2943	#define LAN8814_PAGE_AFE_PMA 1
2944
2945	/**
2946	* LAN8814_PAGE_PCS_DIGITAL - Selects Extended Page 2.
2947	*
2948	* This page seems dedicated to the Physical Coding Sublayer (PCS) and other
2949	* digital logic. It is used for MDI-X alignment (LAN8814_ALIGN_SWAP) and EEE
2950	* state (LAN8814_EEE_STATE) in the LAN8814, and is repurposed for statistics
2951	* and self-test counters in the LAN8842.
2952	*/
2953	#define LAN8814_PAGE_PCS_DIGITAL 2
2954
2955	/**
2956	* LAN8814_PAGE_EEE - Selects Extended Page 3.
2957	*
2958	* This page contains EEE registers
2959	*/
2960	#define LAN8814_PAGE_EEE 3
2961
2962	/**
2963	* LAN8814_PAGE_COMMON_REGS - Selects Extended Page 4.
2964	*
2965	* This page contains device-common registers that affect the entire chip.
2966	* It includes controls for chip-level resets, strap status, GPIO,
2967	* QSGMII, the shared 1588 PTP block, and the PVT monitor.
2968	*/
2969	#define LAN8814_PAGE_COMMON_REGS 4
2970
2971	/**
2972	* LAN8814_PAGE_PORT_REGS - Selects Extended Page 5.
2973	*
2974	* This page contains port-specific registers that must be accessed
2975	* on a per-port basis. It includes controls for port LEDs, QSGMII PCS,
2976	* rate adaptation FIFOs, and the per-port 1588 TSU block.
2977	*/
2978	#define LAN8814_PAGE_PORT_REGS 5
2979
2980	/**
2981	* LAN8814_PAGE_POWER_REGS - Selects Extended Page 28.
2982	*
2983	* This page contains analog control registers and power mode registers.
2984	*/
2985	#define LAN8814_PAGE_POWER_REGS 28
2986
2987	/**
2988	* LAN8814_PAGE_SYSTEM_CTRL - Selects Extended Page 31.
2989	*
2990	* This page appears to hold fundamental system or global controls. In the
2991	* driver, it is used by the related LAN8804 to access the
2992	* LAN8814_CLOCK_MANAGEMENT register.
2993	*/
2994	#define LAN8814_PAGE_SYSTEM_CTRL 31
2995
2996	#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2997	#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2998	#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2999
3000	#define LAN8814_QSGMII_TX_CONFIG 0x35
3001	#define LAN8814_QSGMII_TX_CONFIG_QSGMII BIT(3)
3002	#define LAN8814_QSGMII_SOFT_RESET 0x43
3003	#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
3004	#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
3005	#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
3006	#define LAN8814_ALIGN_SWAP 0x4a
3007	#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
3008	#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
3009
3010	#define LAN8804_ALIGN_SWAP 0x4a
3011	#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
3012	#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
3013	#define LAN8814_CLOCK_MANAGEMENT 0xd
3014	#define LAN8814_LINK_QUALITY 0x8e
3015
3016	static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
3017	{
3018	int data;
3019
3020	phy_lock_mdio_bus(phydev);
3021	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page);
3022	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr);
3023	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
3024	val: (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
3025	data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
3026	phy_unlock_mdio_bus(phydev);
3027
3028	return data;
3029	}
3030
3031	static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
3032	u16 val)
3033	{
3034	phy_lock_mdio_bus(phydev);
3035	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page);
3036	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr);
3037	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
3038	val: page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
3039
3040	val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
3041	if (val != 0)
3042	phydev_err(phydev, "Error: phy_write has returned error %d\n",
3043	val);
3044	phy_unlock_mdio_bus(phydev);
3045	return val;
3046	}
3047
3048	static int lanphy_modify_page_reg(struct phy_device *phydev, int page, u16 addr,
3049	u16 mask, u16 set)
3050	{
3051	int ret;
3052
3053	phy_lock_mdio_bus(phydev);
3054	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page);
3055	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr);
3056	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
3057	val: (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
3058	ret = __phy_modify_changed(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA,
3059	mask, set);
3060	phy_unlock_mdio_bus(phydev);
3061
3062	if (ret < 0)
3063	phydev_err(phydev, "__phy_modify_changed() failed: %pe\n",
3064	ERR_PTR(ret));
3065
3066	return ret;
3067	}
3068
3069	static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
3070	{
3071	u16 val = 0;
3072
3073	if (enable)
3074	val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
3075	PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
3076	PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
3077	PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
3078
3079	return lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3080	PTP_TSU_INT_EN, val);
3081	}
3082
3083	static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
3084	u32 *seconds, u32 *nano_seconds, u16 *seq_id)
3085	{
3086	*seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3087	PTP_RX_INGRESS_SEC_HI);
3088	*seconds = (*seconds << 16) |
3089	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3090	PTP_RX_INGRESS_SEC_LO);
3091
3092	*nano_seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3093	PTP_RX_INGRESS_NS_HI);
3094	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
3095	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3096	PTP_RX_INGRESS_NS_LO);
3097
3098	*seq_id = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3099	PTP_RX_MSG_HEADER2);
3100	}
3101
3102	static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
3103	u32 *seconds, u32 *nano_seconds, u16 *seq_id)
3104	{
3105	*seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3106	PTP_TX_EGRESS_SEC_HI);
3107	*seconds = *seconds << 16 |
3108	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3109	PTP_TX_EGRESS_SEC_LO);
3110
3111	*nano_seconds = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3112	PTP_TX_EGRESS_NS_HI);
3113	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
3114	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3115	PTP_TX_EGRESS_NS_LO);
3116
3117	*seq_id = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3118	PTP_TX_MSG_HEADER2);
3119	}
3120
3121	static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)
3122	{
3123	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3124	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev: ptp_priv->phydev);
3125
3126	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3127	SOF_TIMESTAMPING_RX_HARDWARE |
3128	SOF_TIMESTAMPING_RAW_HARDWARE;
3129
3130	info->phc_index = ptp_clock_index(ptp: shared->ptp_clock);
3131
3132	info->tx_types =
3133	(1 << HWTSTAMP_TX_OFF) |
3134	(1 << HWTSTAMP_TX_ON) |
3135	(1 << HWTSTAMP_TX_ONESTEP_SYNC);
3136
3137	info->rx_filters =
3138	(1 << HWTSTAMP_FILTER_NONE) |
3139	(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3140	(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3141	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3142	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3143
3144	return 0;
3145	}
3146
3147	static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
3148	{
3149	int i;
3150
3151	for (i = 0; i < FIFO_SIZE; ++i)
3152	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
3153	addr: egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
3154
3155	/* Read to clear overflow status bit */
3156	lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TSU_INT_STS);
3157	}
3158
3159	static int lan8814_hwtstamp_set(struct mii_timestamper *mii_ts,
3160	struct kernel_hwtstamp_config *config,
3161	struct netlink_ext_ack *extack)
3162	{
3163	struct kszphy_ptp_priv *ptp_priv =
3164	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3165	struct lan8814_ptp_rx_ts *rx_ts, *tmp;
3166	int txcfg = 0, rxcfg = 0;
3167	int pkt_ts_enable;
3168
3169	ptp_priv->hwts_tx_type = config->tx_type;
3170	ptp_priv->rx_filter = config->rx_filter;
3171
3172	switch (config->rx_filter) {
3173	case HWTSTAMP_FILTER_NONE:
3174	ptp_priv->layer = 0;
3175	ptp_priv->version = 0;
3176	break;
3177	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3178	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3179	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3180	ptp_priv->layer = PTP_CLASS_L4;
3181	ptp_priv->version = PTP_CLASS_V2;
3182	break;
3183	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3184	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3185	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3186	ptp_priv->layer = PTP_CLASS_L2;
3187	ptp_priv->version = PTP_CLASS_V2;
3188	break;
3189	case HWTSTAMP_FILTER_PTP_V2_EVENT:
3190	case HWTSTAMP_FILTER_PTP_V2_SYNC:
3191	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3192	ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3193	ptp_priv->version = PTP_CLASS_V2;
3194	break;
3195	default:
3196	return -ERANGE;
3197	}
3198
3199	if (ptp_priv->layer & PTP_CLASS_L2) {
3200	rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3201	txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3202	} else if (ptp_priv->layer & PTP_CLASS_L4) {
3203	rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3204	txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3205	}
3206	lanphy_write_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3207	PTP_RX_PARSE_CONFIG, val: rxcfg);
3208	lanphy_write_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3209	PTP_TX_PARSE_CONFIG, val: txcfg);
3210
3211	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3212	PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3213	lanphy_write_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3214	PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable);
3215	lanphy_write_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3216	PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable);
3217
3218	if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
3219	lanphy_modify_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3220	PTP_TX_MOD,
3221	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3222	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
3223	} else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
3224	lanphy_modify_page_reg(phydev: ptp_priv->phydev, LAN8814_PAGE_PORT_REGS,
3225	PTP_TX_MOD,
3226	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3227	set: 0);
3228	}
3229
3230	if (config->rx_filter != HWTSTAMP_FILTER_NONE)
3231	lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: true);
3232	else
3233	lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: false);
3234
3235	/* In case of multiple starts and stops, these needs to be cleared */
3236	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
3237	list_del(entry: &rx_ts->list);
3238	kfree(objp: rx_ts);
3239	}
3240	skb_queue_purge(list: &ptp_priv->rx_queue);
3241	skb_queue_purge(list: &ptp_priv->tx_queue);
3242
3243	lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: false);
3244	lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: true);
3245
3246	return 0;
3247	}
3248
3249	static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
3250	struct sk_buff *skb, int type)
3251	{
3252	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3253
3254	switch (ptp_priv->hwts_tx_type) {
3255	case HWTSTAMP_TX_ONESTEP_SYNC:
3256	if (ptp_msg_is_sync(skb, type)) {
3257	kfree_skb(skb);
3258	return;
3259	}
3260	fallthrough;
3261	case HWTSTAMP_TX_ON:
3262	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3263	skb_queue_tail(list: &ptp_priv->tx_queue, newsk: skb);
3264	break;
3265	case HWTSTAMP_TX_OFF:
3266	default:
3267	kfree_skb(skb);
3268	break;
3269	}
3270	}
3271
3272	static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
3273	{
3274	struct ptp_header *ptp_header;
3275	u32 type;
3276
3277	skb_push(skb, ETH_HLEN);
3278	type = ptp_classify_raw(skb);
3279	ptp_header = ptp_parse_header(skb, type);
3280	skb_pull_inline(skb, ETH_HLEN);
3281
3282	if (!ptp_header)
3283	return false;
3284
3285	*sig = (__force u16)(ntohs(ptp_header->sequence_id));
3286	return true;
3287	}
3288
3289	static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
3290	struct sk_buff *skb)
3291	{
3292	struct skb_shared_hwtstamps *shhwtstamps;
3293	struct lan8814_ptp_rx_ts *rx_ts, *tmp;
3294	unsigned long flags;
3295	bool ret = false;
3296	u16 skb_sig;
3297
3298	if (!lan8814_get_sig_rx(skb, sig: &skb_sig))
3299	return ret;
3300
3301	/* Iterate over all RX timestamps and match it with the received skbs */
3302	spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
3303	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
3304	/* Check if we found the signature we were looking for. */
3305	if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id)))
3306	continue;
3307
3308	shhwtstamps = skb_hwtstamps(skb);
3309	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3310	shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds,
3311	nsecs: rx_ts->nsec);
3312	list_del(entry: &rx_ts->list);
3313	kfree(objp: rx_ts);
3314
3315	ret = true;
3316	break;
3317	}
3318	spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags);
3319
3320	if (ret)
3321	netif_rx(skb);
3322	return ret;
3323	}
3324
3325	static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
3326	{
3327	struct kszphy_ptp_priv *ptp_priv =
3328	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3329
3330	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3331	type == PTP_CLASS_NONE)
3332	return false;
3333
3334	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3335	return false;
3336
3337	/* If we failed to match then add it to the queue for when the timestamp
3338	* will come
3339	*/
3340	if (!lan8814_match_rx_skb(ptp_priv, skb))
3341	skb_queue_tail(list: &ptp_priv->rx_queue, newsk: skb);
3342
3343	return true;
3344	}
3345
3346	static void lan8814_ptp_clock_set(struct phy_device *phydev,
3347	time64_t sec, u32 nsec)
3348	{
3349	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3350	PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
3351	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3352	PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
3353	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3354	PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
3355	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3356	PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
3357	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3358	PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
3359
3360	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3361	PTP_CMD_CTL_PTP_CLOCK_LOAD_);
3362	}
3363
3364	static void lan8814_ptp_clock_get(struct phy_device *phydev,
3365	time64_t *sec, u32 *nsec)
3366	{
3367	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3368	PTP_CMD_CTL_PTP_CLOCK_READ_);
3369
3370	*sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3371	PTP_CLOCK_READ_SEC_HI);
3372	*sec <<= 16;
3373	*sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3374	PTP_CLOCK_READ_SEC_MID);
3375	*sec <<= 16;
3376	*sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3377	PTP_CLOCK_READ_SEC_LO);
3378
3379	*nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3380	PTP_CLOCK_READ_NS_HI);
3381	*nsec <<= 16;
3382	*nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3383	PTP_CLOCK_READ_NS_LO);
3384	}
3385
3386	static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
3387	struct timespec64 *ts)
3388	{
3389	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3390	ptp_clock_info);
3391	struct phy_device *phydev = shared->phydev;
3392	u32 nano_seconds;
3393	time64_t seconds;
3394
3395	mutex_lock(&shared->shared_lock);
3396	lan8814_ptp_clock_get(phydev, sec: &seconds, nsec: &nano_seconds);
3397	mutex_unlock(lock: &shared->shared_lock);
3398	ts->tv_sec = seconds;
3399	ts->tv_nsec = nano_seconds;
3400
3401	return 0;
3402	}
3403
3404	static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
3405	const struct timespec64 *ts)
3406	{
3407	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3408	ptp_clock_info);
3409	struct phy_device *phydev = shared->phydev;
3410
3411	mutex_lock(&shared->shared_lock);
3412	lan8814_ptp_clock_set(phydev, sec: ts->tv_sec, nsec: ts->tv_nsec);
3413	mutex_unlock(lock: &shared->shared_lock);
3414
3415	return 0;
3416	}
3417
3418	static void lan8814_ptp_set_target(struct phy_device *phydev, int event,
3419	s64 start_sec, u32 start_nsec)
3420	{
3421	/* Set the start time */
3422	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3423	LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
3424	lower_16_bits(start_sec));
3425	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3426	LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
3427	upper_16_bits(start_sec));
3428
3429	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3430	LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
3431	lower_16_bits(start_nsec));
3432	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3433	LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
3434	upper_16_bits(start_nsec) & 0x3fff);
3435	}
3436
3437	static void lan8814_ptp_update_target(struct phy_device *phydev, time64_t sec)
3438	{
3439	lan8814_ptp_set_target(phydev, LAN8814_EVENT_A,
3440	start_sec: sec + LAN8814_BUFFER_TIME, start_nsec: 0);
3441	lan8814_ptp_set_target(phydev, LAN8814_EVENT_B,
3442	start_sec: sec + LAN8814_BUFFER_TIME, start_nsec: 0);
3443	}
3444
3445	static void lan8814_ptp_clock_step(struct phy_device *phydev,
3446	s64 time_step_ns)
3447	{
3448	u32 nano_seconds_step;
3449	u64 abs_time_step_ns;
3450	time64_t set_seconds;
3451	u32 nano_seconds;
3452	u32 remainder;
3453	s32 seconds;
3454
3455	if (time_step_ns > 15000000000LL) {
3456	/* convert to clock set */
3457	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nano_seconds);
3458	set_seconds += div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL,
3459	remainder: &remainder);
3460	nano_seconds += remainder;
3461	if (nano_seconds >= 1000000000) {
3462	set_seconds++;
3463	nano_seconds -= 1000000000;
3464	}
3465	lan8814_ptp_clock_set(phydev, sec: set_seconds, nsec: nano_seconds);
3466	lan8814_ptp_update_target(phydev, sec: set_seconds);
3467	return;
3468	} else if (time_step_ns < -15000000000LL) {
3469	/* convert to clock set */
3470	time_step_ns = -time_step_ns;
3471
3472	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nano_seconds);
3473	set_seconds -= div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL,
3474	remainder: &remainder);
3475	nano_seconds_step = remainder;
3476	if (nano_seconds < nano_seconds_step) {
3477	set_seconds--;
3478	nano_seconds += 1000000000;
3479	}
3480	nano_seconds -= nano_seconds_step;
3481	lan8814_ptp_clock_set(phydev, sec: set_seconds, nsec: nano_seconds);
3482	lan8814_ptp_update_target(phydev, sec: set_seconds);
3483	return;
3484	}
3485
3486	/* do clock step */
3487	if (time_step_ns >= 0) {
3488	abs_time_step_ns = (u64)time_step_ns;
3489	seconds = (s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000,
3490	remainder: &remainder);
3491	nano_seconds = remainder;
3492	} else {
3493	abs_time_step_ns = (u64)(-time_step_ns);
3494	seconds = -((s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000,
3495	remainder: &remainder));
3496	nano_seconds = remainder;
3497	if (nano_seconds > 0) {
3498	/* subtracting nano seconds is not allowed
3499	* convert to subtracting from seconds,
3500	* and adding to nanoseconds
3501	*/
3502	seconds--;
3503	nano_seconds = (1000000000 - nano_seconds);
3504	}
3505	}
3506
3507	if (nano_seconds > 0) {
3508	/* add 8 ns to cover the likely normal increment */
3509	nano_seconds += 8;
3510	}
3511
3512	if (nano_seconds >= 1000000000) {
3513	/* carry into seconds */
3514	seconds++;
3515	nano_seconds -= 1000000000;
3516	}
3517
3518	while (seconds) {
3519	u32 nsec;
3520
3521	if (seconds > 0) {
3522	u32 adjustment_value = (u32)seconds;
3523	u16 adjustment_value_lo, adjustment_value_hi;
3524
3525	if (adjustment_value > 0xF)
3526	adjustment_value = 0xF;
3527
3528	adjustment_value_lo = adjustment_value & 0xffff;
3529	adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3530
3531	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3532	PTP_LTC_STEP_ADJ_LO,
3533	val: adjustment_value_lo);
3534	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3535	PTP_LTC_STEP_ADJ_HI,
3536	PTP_LTC_STEP_ADJ_DIR_ |
3537	adjustment_value_hi);
3538	seconds -= ((s32)adjustment_value);
3539
3540	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nsec);
3541	set_seconds -= adjustment_value;
3542	lan8814_ptp_update_target(phydev, sec: set_seconds);
3543	} else {
3544	u32 adjustment_value = (u32)(-seconds);
3545	u16 adjustment_value_lo, adjustment_value_hi;
3546
3547	if (adjustment_value > 0xF)
3548	adjustment_value = 0xF;
3549
3550	adjustment_value_lo = adjustment_value & 0xffff;
3551	adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3552
3553	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3554	PTP_LTC_STEP_ADJ_LO,
3555	val: adjustment_value_lo);
3556	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3557	PTP_LTC_STEP_ADJ_HI,
3558	val: adjustment_value_hi);
3559	seconds += ((s32)adjustment_value);
3560
3561	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nsec);
3562	set_seconds += adjustment_value;
3563	lan8814_ptp_update_target(phydev, sec: set_seconds);
3564	}
3565	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3566	PTP_CMD_CTL, PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3567	}
3568	if (nano_seconds) {
3569	u16 nano_seconds_lo;
3570	u16 nano_seconds_hi;
3571
3572	nano_seconds_lo = nano_seconds & 0xffff;
3573	nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
3574
3575	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3576	PTP_LTC_STEP_ADJ_LO,
3577	val: nano_seconds_lo);
3578	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3579	PTP_LTC_STEP_ADJ_HI,
3580	PTP_LTC_STEP_ADJ_DIR_ |
3581	nano_seconds_hi);
3582	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
3583	PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
3584	}
3585	}
3586
3587	static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
3588	{
3589	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3590	ptp_clock_info);
3591	struct phy_device *phydev = shared->phydev;
3592
3593	mutex_lock(&shared->shared_lock);
3594	lan8814_ptp_clock_step(phydev, time_step_ns: delta);
3595	mutex_unlock(lock: &shared->shared_lock);
3596
3597	return 0;
3598	}
3599
3600	static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
3601	{
3602	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3603	ptp_clock_info);
3604	struct phy_device *phydev = shared->phydev;
3605	u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
3606	bool positive = true;
3607	u32 kszphy_rate_adj;
3608
3609	if (scaled_ppm < 0) {
3610	scaled_ppm = -scaled_ppm;
3611	positive = false;
3612	}
3613
3614	kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
3615	kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
3616
3617	kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
3618	kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
3619
3620	if (positive)
3621	kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
3622
3623	mutex_lock(&shared->shared_lock);
3624	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CLOCK_RATE_ADJ_HI,
3625	val: kszphy_rate_adj_hi);
3626	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CLOCK_RATE_ADJ_LO,
3627	val: kszphy_rate_adj_lo);
3628	mutex_unlock(lock: &shared->shared_lock);
3629
3630	return 0;
3631	}
3632
3633	static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,
3634	s64 period_sec, u32 period_nsec)
3635	{
3636	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3637	LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),
3638	lower_16_bits(period_sec));
3639	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3640	LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),
3641	upper_16_bits(period_sec));
3642
3643	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3644	LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),
3645	lower_16_bits(period_nsec));
3646	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3647	LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),
3648	upper_16_bits(period_nsec) & 0x3fff);
3649	}
3650
3651	static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,
3652	int pulse_width)
3653	{
3654	/* Set the pulse width of the event,
3655	* Make sure that the target clock will be incremented each time when
3656	* local time reaches or pass it
3657	* Set the polarity high
3658	*/
3659	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_PTP_GENERAL_CONFIG,
3660	LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) |
3661	LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) |
3662	LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) |
3663	LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event),
3664	LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width) |
3665	LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event));
3666	}
3667
3668	static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)
3669	{
3670	/* Set target to too far in the future, effectively disabling it */
3671	lan8814_ptp_set_target(phydev, event, start_sec: 0xFFFFFFFF, start_nsec: 0);
3672
3673	/* And then reload once it reaches the target */
3674	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_PTP_GENERAL_CONFIG,
3675	LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event),
3676	LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3677	}
3678
3679	static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)
3680	{
3681	/* Disable gpio alternate function,
3682	* 1: select as gpio,
3683	* 0: select alt func
3684	*/
3685	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3686	LAN8814_GPIO_EN_ADDR(pin),
3687	LAN8814_GPIO_EN_BIT(pin),
3688	LAN8814_GPIO_EN_BIT(pin));
3689
3690	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3691	LAN8814_GPIO_DIR_ADDR(pin),
3692	LAN8814_GPIO_DIR_BIT(pin),
3693	set: 0);
3694
3695	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3696	LAN8814_GPIO_BUF_ADDR(pin),
3697	LAN8814_GPIO_BUF_BIT(pin),
3698	set: 0);
3699	}
3700
3701	static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3702	{
3703	/* Set as gpio output */
3704	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3705	LAN8814_GPIO_DIR_ADDR(pin),
3706	LAN8814_GPIO_DIR_BIT(pin),
3707	LAN8814_GPIO_DIR_BIT(pin));
3708
3709	/* Enable gpio 0:for alternate function, 1:gpio */
3710	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3711	LAN8814_GPIO_EN_ADDR(pin),
3712	LAN8814_GPIO_EN_BIT(pin),
3713	set: 0);
3714
3715	/* Set buffer type to push pull */
3716	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3717	LAN8814_GPIO_BUF_ADDR(pin),
3718	LAN8814_GPIO_BUF_BIT(pin),
3719	LAN8814_GPIO_BUF_BIT(pin));
3720	}
3721
3722	static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,
3723	struct ptp_clock_request *rq, int on)
3724	{
3725	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3726	ptp_clock_info);
3727	struct phy_device *phydev = shared->phydev;
3728	struct timespec64 ts_on, ts_period;
3729	s64 on_nsec, period_nsec;
3730	int pulse_width;
3731	int pin, event;
3732
3733	mutex_lock(&shared->shared_lock);
3734	event = rq->perout.index;
3735	pin = ptp_find_pin(ptp: shared->ptp_clock, func: PTP_PF_PEROUT, chan: event);
3736	if (pin < 0 || pin >= LAN8814_PTP_PEROUT_NUM) {
3737	mutex_unlock(lock: &shared->shared_lock);
3738	return -EBUSY;
3739	}
3740
3741	if (!on) {
3742	lan8814_ptp_perout_off(phydev, pin);
3743	lan8814_ptp_disable_event(phydev, event);
3744	mutex_unlock(lock: &shared->shared_lock);
3745	return 0;
3746	}
3747
3748	ts_on.tv_sec = rq->perout.on.sec;
3749	ts_on.tv_nsec = rq->perout.on.nsec;
3750	on_nsec = timespec64_to_ns(ts: &ts_on);
3751
3752	ts_period.tv_sec = rq->perout.period.sec;
3753	ts_period.tv_nsec = rq->perout.period.nsec;
3754	period_nsec = timespec64_to_ns(ts: &ts_period);
3755
3756	if (period_nsec < 200) {
3757	pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
3758	phydev_name(phydev));
3759	mutex_unlock(lock: &shared->shared_lock);
3760	return -EOPNOTSUPP;
3761	}
3762
3763	if (on_nsec >= period_nsec) {
3764	pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
3765	phydev_name(phydev));
3766	mutex_unlock(lock: &shared->shared_lock);
3767	return -EINVAL;
3768	}
3769
3770	switch (on_nsec) {
3771	case 200000000:
3772	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
3773	break;
3774	case 100000000:
3775	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
3776	break;
3777	case 50000000:
3778	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
3779	break;
3780	case 10000000:
3781	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
3782	break;
3783	case 5000000:
3784	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
3785	break;
3786	case 1000000:
3787	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
3788	break;
3789	case 500000:
3790	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
3791	break;
3792	case 100000:
3793	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
3794	break;
3795	case 50000:
3796	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
3797	break;
3798	case 10000:
3799	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
3800	break;
3801	case 5000:
3802	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
3803	break;
3804	case 1000:
3805	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
3806	break;
3807	case 500:
3808	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
3809	break;
3810	case 100:
3811	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3812	break;
3813	default:
3814	pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
3815	phydev_name(phydev));
3816	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3817	break;
3818	}
3819
3820	/* Configure to pulse every period */
3821	lan8814_ptp_enable_event(phydev, event, pulse_width);
3822	lan8814_ptp_set_target(phydev, event, start_sec: rq->perout.start.sec,
3823	start_nsec: rq->perout.start.nsec);
3824	lan8814_ptp_set_reload(phydev, event, period_sec: rq->perout.period.sec,
3825	period_nsec: rq->perout.period.nsec);
3826	lan8814_ptp_perout_on(phydev, pin);
3827	mutex_unlock(lock: &shared->shared_lock);
3828
3829	return 0;
3830	}
3831
3832	static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3833	{
3834	/* Set as gpio input */
3835	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3836	LAN8814_GPIO_DIR_ADDR(pin),
3837	LAN8814_GPIO_DIR_BIT(pin),
3838	set: 0);
3839
3840	/* Map the pin to ltc pin 0 of the capture map registers */
3841	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3842	PTP_GPIO_CAP_MAP_LO, mask: pin, set: pin);
3843
3844	/* Enable capture on the edges of the ltc pin */
3845	if (flags & PTP_RISING_EDGE)
3846	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3847	PTP_GPIO_CAP_EN,
3848	PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0),
3849	PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0));
3850	if (flags & PTP_FALLING_EDGE)
3851	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3852	PTP_GPIO_CAP_EN,
3853	PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0),
3854	PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0));
3855
3856	/* Enable interrupt top interrupt */
3857	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_COMMON_INT_ENA,
3858	PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3859	PTP_COMMON_INT_ENA_GPIO_CAP_EN);
3860	}
3861
3862	static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3863	{
3864	/* Set as gpio out */
3865	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3866	LAN8814_GPIO_DIR_ADDR(pin),
3867	LAN8814_GPIO_DIR_BIT(pin),
3868	LAN8814_GPIO_DIR_BIT(pin));
3869
3870	/* Enable alternate, 0:for alternate function, 1:gpio */
3871	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3872	LAN8814_GPIO_EN_ADDR(pin),
3873	LAN8814_GPIO_EN_BIT(pin),
3874	set: 0);
3875
3876	/* Clear the mapping of pin to registers 0 of the capture registers */
3877	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
3878	PTP_GPIO_CAP_MAP_LO,
3879	GENMASK(3, 0),
3880	set: 0);
3881
3882	/* Disable capture on both of the edges */
3883	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_GPIO_CAP_EN,
3884	PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
3885	PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
3886	set: 0);
3887
3888	/* Disable interrupt top interrupt */
3889	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_COMMON_INT_ENA,
3890	PTP_COMMON_INT_ENA_GPIO_CAP_EN,
3891	set: 0);
3892	}
3893
3894	static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,
3895	struct ptp_clock_request *rq, int on)
3896	{
3897	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3898	ptp_clock_info);
3899	struct phy_device *phydev = shared->phydev;
3900	int pin;
3901
3902	pin = ptp_find_pin(ptp: shared->ptp_clock, func: PTP_PF_EXTTS,
3903	chan: rq->extts.index);
3904	if (pin == -1 || pin != LAN8814_PTP_EXTTS_NUM)
3905	return -EINVAL;
3906
3907	mutex_lock(&shared->shared_lock);
3908	if (on)
3909	lan8814_ptp_extts_on(phydev, pin, flags: rq->extts.flags);
3910	else
3911	lan8814_ptp_extts_off(phydev, pin);
3912
3913	mutex_unlock(lock: &shared->shared_lock);
3914
3915	return 0;
3916	}
3917
3918	static int lan8814_ptpci_enable(struct ptp_clock_info *ptpci,
3919	struct ptp_clock_request *rq, int on)
3920	{
3921	switch (rq->type) {
3922	case PTP_CLK_REQ_PEROUT:
3923	return lan8814_ptp_perout(ptpci, rq, on);
3924	case PTP_CLK_REQ_EXTTS:
3925	return lan8814_ptp_extts(ptpci, rq, on);
3926	default:
3927	return -EINVAL;
3928	}
3929	}
3930
3931	static int lan8814_ptpci_verify(struct ptp_clock_info *ptp, unsigned int pin,
3932	enum ptp_pin_function func, unsigned int chan)
3933	{
3934	switch (func) {
3935	case PTP_PF_NONE:
3936	case PTP_PF_PEROUT:
3937	/* Only pins 0 and 1 can generate perout signals. And for pin 0
3938	* there is only chan 0 (event A) and for pin 1 there is only
3939	* chan 1 (event B)
3940	*/
3941	if (pin >= LAN8814_PTP_PEROUT_NUM || pin != chan)
3942	return -1;
3943	break;
3944	case PTP_PF_EXTTS:
3945	if (pin != LAN8814_PTP_EXTTS_NUM)
3946	return -1;
3947	break;
3948	default:
3949	return -1;
3950	}
3951
3952	return 0;
3953	}
3954
3955	static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
3956	{
3957	struct ptp_header *ptp_header;
3958	u32 type;
3959
3960	type = ptp_classify_raw(skb);
3961	ptp_header = ptp_parse_header(skb, type);
3962
3963	if (!ptp_header)
3964	return false;
3965
3966	*sig = (__force u16)(ntohs(ptp_header->sequence_id));
3967	return true;
3968	}
3969
3970	static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
3971	u32 seconds, u32 nsec, u16 seq_id)
3972	{
3973	struct skb_shared_hwtstamps shhwtstamps;
3974	struct sk_buff *skb, *skb_tmp;
3975	unsigned long flags;
3976	bool ret = false;
3977	u16 skb_sig;
3978
3979	spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
3980	skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
3981	if (!lan8814_get_sig_tx(skb, sig: &skb_sig))
3982	continue;
3983
3984	if (memcmp(p: &skb_sig, q: &seq_id, size: sizeof(seq_id)))
3985	continue;
3986
3987	__skb_unlink(skb, list: &ptp_priv->tx_queue);
3988	ret = true;
3989	break;
3990	}
3991	spin_unlock_irqrestore(lock: &ptp_priv->tx_queue.lock, flags);
3992
3993	if (ret) {
3994	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3995	shhwtstamps.hwtstamp = ktime_set(secs: seconds, nsecs: nsec);
3996	skb_complete_tx_timestamp(skb, hwtstamps: &shhwtstamps);
3997	}
3998	}
3999
4000	static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
4001	{
4002	struct phy_device *phydev = ptp_priv->phydev;
4003	u32 seconds, nsec;
4004	u16 seq_id;
4005
4006	lan8814_ptp_tx_ts_get(phydev, seconds: &seconds, nano_seconds: &nsec, seq_id: &seq_id);
4007	lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
4008	}
4009
4010	static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
4011	{
4012	struct phy_device *phydev = ptp_priv->phydev;
4013	u32 reg;
4014
4015	do {
4016	lan8814_dequeue_tx_skb(ptp_priv);
4017
4018	/* If other timestamps are available in the FIFO,
4019	* process them.
4020	*/
4021	reg = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4022	PTP_CAP_INFO);
4023	} while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
4024	}
4025
4026	static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
4027	struct lan8814_ptp_rx_ts *rx_ts)
4028	{
4029	struct skb_shared_hwtstamps *shhwtstamps;
4030	struct sk_buff *skb, *skb_tmp;
4031	unsigned long flags;
4032	bool ret = false;
4033	u16 skb_sig;
4034
4035	spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
4036	skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
4037	if (!lan8814_get_sig_rx(skb, sig: &skb_sig))
4038	continue;
4039
4040	if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id)))
4041	continue;
4042
4043	__skb_unlink(skb, list: &ptp_priv->rx_queue);
4044
4045	ret = true;
4046	break;
4047	}
4048	spin_unlock_irqrestore(lock: &ptp_priv->rx_queue.lock, flags);
4049
4050	if (ret) {
4051	shhwtstamps = skb_hwtstamps(skb);
4052	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4053	shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds, nsecs: rx_ts->nsec);
4054	netif_rx(skb);
4055	}
4056
4057	return ret;
4058	}
4059
4060	static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
4061	struct lan8814_ptp_rx_ts *rx_ts)
4062	{
4063	unsigned long flags;
4064
4065	/* If we failed to match the skb add it to the queue for when
4066	* the frame will come
4067	*/
4068	if (!lan8814_match_skb(ptp_priv, rx_ts)) {
4069	spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
4070	list_add(new: &rx_ts->list, head: &ptp_priv->rx_ts_list);
4071	spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags);
4072	} else {
4073	kfree(objp: rx_ts);
4074	}
4075	}
4076
4077	static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
4078	{
4079	struct phy_device *phydev = ptp_priv->phydev;
4080	struct lan8814_ptp_rx_ts *rx_ts;
4081	u32 reg;
4082
4083	do {
4084	rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
4085	if (!rx_ts)
4086	return;
4087
4088	lan8814_ptp_rx_ts_get(phydev, seconds: &rx_ts->seconds, nano_seconds: &rx_ts->nsec,
4089	seq_id: &rx_ts->seq_id);
4090	lan8814_match_rx_ts(ptp_priv, rx_ts);
4091
4092	/* If other timestamps are available in the FIFO,
4093	* process them.
4094	*/
4095	reg = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4096	PTP_CAP_INFO);
4097	} while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
4098	}
4099
4100	static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
4101	{
4102	struct kszphy_priv *priv = phydev->priv;
4103	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4104
4105	if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
4106	lan8814_get_tx_ts(ptp_priv);
4107
4108	if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
4109	lan8814_get_rx_ts(ptp_priv);
4110
4111	if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
4112	lan8814_flush_fifo(phydev, egress: true);
4113	skb_queue_purge(list: &ptp_priv->tx_queue);
4114	}
4115
4116	if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
4117	lan8814_flush_fifo(phydev, egress: false);
4118	skb_queue_purge(list: &ptp_priv->rx_queue);
4119	}
4120	}
4121
4122	static int lan8814_gpio_process_cap(struct lan8814_shared_priv *shared)
4123	{
4124	struct phy_device *phydev = shared->phydev;
4125	struct ptp_clock_event ptp_event = {0};
4126	unsigned long nsec;
4127	s64 sec;
4128	u16 tmp;
4129
4130	/* This is 0 because whatever was the input pin it was mapped it to
4131	* ltc gpio pin 0
4132	*/
4133	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_GPIO_SEL,
4134	PTP_GPIO_SEL_GPIO_SEL(0),
4135	PTP_GPIO_SEL_GPIO_SEL(0));
4136
4137	tmp = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4138	PTP_GPIO_CAP_STS);
4139	if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
4140	!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))
4141	return -1;
4142
4143	if (tmp & BIT(0)) {
4144	sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4145	PTP_GPIO_RE_LTC_SEC_HI_CAP);
4146	sec <<= 16;
4147	sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4148	PTP_GPIO_RE_LTC_SEC_LO_CAP);
4149
4150	nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4151	PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
4152	nsec <<= 16;
4153	nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4154	PTP_GPIO_RE_LTC_NS_LO_CAP);
4155	} else {
4156	sec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4157	PTP_GPIO_FE_LTC_SEC_HI_CAP);
4158	sec <<= 16;
4159	sec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4160	PTP_GPIO_FE_LTC_SEC_LO_CAP);
4161
4162	nsec = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4163	PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
4164	nsec <<= 16;
4165	nsec |= lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4166	PTP_GPIO_RE_LTC_NS_LO_CAP);
4167	}
4168
4169	ptp_event.index = 0;
4170	ptp_event.timestamp = ktime_set(secs: sec, nsecs: nsec);
4171	ptp_event.type = PTP_CLOCK_EXTTS;
4172	ptp_clock_event(ptp: shared->ptp_clock, event: &ptp_event);
4173
4174	return 0;
4175	}
4176
4177	static int lan8814_handle_gpio_interrupt(struct phy_device *phydev, u16 status)
4178	{
4179	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
4180	int ret;
4181
4182	mutex_lock(&shared->shared_lock);
4183	ret = lan8814_gpio_process_cap(shared);
4184	mutex_unlock(lock: &shared->shared_lock);
4185
4186	return ret;
4187	}
4188
4189	static int lan8804_config_init(struct phy_device *phydev)
4190	{
4191	/* MDI-X setting for swap A,B transmit */
4192	lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8804_ALIGN_SWAP,
4193	LAN8804_ALIGN_TX_A_B_SWAP_MASK,
4194	LAN8804_ALIGN_TX_A_B_SWAP);
4195
4196	/* Make sure that the PHY will not stop generating the clock when the
4197	* link partner goes down
4198	*/
4199	lanphy_write_page_reg(phydev, LAN8814_PAGE_SYSTEM_CTRL,
4200	LAN8814_CLOCK_MANAGEMENT, val: 0x27e);
4201	lanphy_read_page_reg(phydev, LAN8814_PAGE_AFE_PMA, LAN8814_LINK_QUALITY);
4202
4203	return 0;
4204	}
4205
4206	static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
4207	{
4208	int status;
4209
4210	status = phy_read(phydev, LAN8814_INTS);
4211	if (status < 0) {
4212	phy_error(phydev);
4213	return IRQ_NONE;
4214	}
4215
4216	if (status > 0)
4217	phy_trigger_machine(phydev);
4218
4219	return IRQ_HANDLED;
4220	}
4221
4222	#define LAN8804_OUTPUT_CONTROL 25
4223	#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
4224	#define LAN8804_CONTROL 31
4225	#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
4226
4227	static int lan8804_config_intr(struct phy_device *phydev)
4228	{
4229	int err;
4230
4231	/* This is an internal PHY of lan966x and is not possible to change the
4232	* polarity on the GIC found in lan966x, therefore change the polarity
4233	* of the interrupt in the PHY from being active low instead of active
4234	* high.
4235	*/
4236	phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
4237
4238	/* By default interrupt buffer is open-drain in which case the interrupt
4239	* can be active only low. Therefore change the interrupt buffer to be
4240	* push-pull to be able to change interrupt polarity
4241	*/
4242	phy_write(phydev, LAN8804_OUTPUT_CONTROL,
4243	LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
4244
4245	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4246	err = phy_read(phydev, LAN8814_INTS);
4247	if (err < 0)
4248	return err;
4249
4250	err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
4251	if (err)
4252	return err;
4253	} else {
4254	err = phy_write(phydev, LAN8814_INTC, val: 0);
4255	if (err)
4256	return err;
4257
4258	err = phy_read(phydev, LAN8814_INTS);
4259	if (err < 0)
4260	return err;
4261	}
4262
4263	return 0;
4264	}
4265
4266	/* Check if the PHY has 1588 support. There are multiple skus of the PHY and
4267	* some of them support PTP while others don't support it. This function will
4268	* return true is the sku supports it, otherwise will return false.
4269	*/
4270	static bool lan8814_has_ptp(struct phy_device *phydev)
4271	{
4272	struct kszphy_priv *priv = phydev->priv;
4273
4274	return priv->is_ptp_available;
4275	}
4276
4277	static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
4278	{
4279	int ret = IRQ_NONE;
4280	int irq_status;
4281
4282	irq_status = phy_read(phydev, LAN8814_INTS);
4283	if (irq_status < 0) {
4284	phy_error(phydev);
4285	return IRQ_NONE;
4286	}
4287
4288	if (irq_status & LAN8814_INT_LINK) {
4289	phy_trigger_machine(phydev);
4290	ret = IRQ_HANDLED;
4291	}
4292
4293	if (!lan8814_has_ptp(phydev))
4294	return ret;
4295
4296	while (true) {
4297	irq_status = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4298	PTP_TSU_INT_STS);
4299	if (!irq_status)
4300	break;
4301
4302	lan8814_handle_ptp_interrupt(phydev, status: irq_status);
4303	ret = IRQ_HANDLED;
4304	}
4305
4306	if (!lan8814_handle_gpio_interrupt(phydev, status: irq_status))
4307	ret = IRQ_HANDLED;
4308
4309	return ret;
4310	}
4311
4312	static int lan8814_ack_interrupt(struct phy_device *phydev)
4313	{
4314	/* bit[12..0] int status, which is a read and clear register. */
4315	int rc;
4316
4317	rc = phy_read(phydev, LAN8814_INTS);
4318
4319	return (rc < 0) ? rc : 0;
4320	}
4321
4322	static int lan8814_config_intr(struct phy_device *phydev)
4323	{
4324	int err;
4325
4326	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, LAN8814_INTR_CTRL_REG,
4327	LAN8814_INTR_CTRL_REG_POLARITY |
4328	LAN8814_INTR_CTRL_REG_INTR_ENABLE);
4329
4330	/* enable / disable interrupts */
4331	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4332	err = lan8814_ack_interrupt(phydev);
4333	if (err)
4334	return err;
4335
4336	err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
4337	} else {
4338	err = phy_write(phydev, LAN8814_INTC, val: 0);
4339	if (err)
4340	return err;
4341
4342	err = lan8814_ack_interrupt(phydev);
4343	}
4344
4345	return err;
4346	}
4347
4348	static void lan8814_ptp_init(struct phy_device *phydev)
4349	{
4350	struct kszphy_priv *priv = phydev->priv;
4351	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4352
4353	if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
4354	!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4355	return;
4356
4357	if (!lan8814_has_ptp(phydev))
4358	return;
4359
4360	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4361	TSU_HARD_RESET, TSU_HARD_RESET_);
4362
4363	lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TX_MOD,
4364	PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4365	PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4366
4367	lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_RX_MOD,
4368	PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_,
4369	PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_);
4370
4371	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4372	PTP_RX_PARSE_CONFIG, val: 0);
4373	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4374	PTP_TX_PARSE_CONFIG, val: 0);
4375
4376	/* Removing default registers configs related to L2 and IP */
4377	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4378	PTP_TX_PARSE_L2_ADDR_EN, val: 0);
4379	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4380	PTP_RX_PARSE_L2_ADDR_EN, val: 0);
4381	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4382	PTP_TX_PARSE_IP_ADDR_EN, val: 0);
4383	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4384	PTP_RX_PARSE_IP_ADDR_EN, val: 0);
4385
4386	/* Disable checking for minorVersionPTP field */
4387	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_RX_VERSION,
4388	PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
4389	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS, PTP_TX_VERSION,
4390	PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
4391
4392	skb_queue_head_init(list: &ptp_priv->tx_queue);
4393	skb_queue_head_init(list: &ptp_priv->rx_queue);
4394	INIT_LIST_HEAD(list: &ptp_priv->rx_ts_list);
4395	spin_lock_init(&ptp_priv->rx_ts_lock);
4396
4397	ptp_priv->phydev = phydev;
4398
4399	ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
4400	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4401	ptp_priv->mii_ts.hwtstamp_set = lan8814_hwtstamp_set;
4402	ptp_priv->mii_ts.ts_info = lan8814_ts_info;
4403
4404	phydev->mii_ts = &ptp_priv->mii_ts;
4405
4406	/* Timestamp selected by default to keep legacy API */
4407	phydev->default_timestamp = true;
4408	}
4409
4410	static int __lan8814_ptp_probe_once(struct phy_device *phydev, char *pin_name,
4411	int gpios)
4412	{
4413	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
4414
4415	shared->phydev = phydev;
4416
4417	/* Initialise shared lock for clock*/
4418	mutex_init(&shared->shared_lock);
4419
4420	shared->pin_config = devm_kmalloc_array(dev: &phydev->mdio.dev,
4421	n: gpios,
4422	size: sizeof(*shared->pin_config),
4423	GFP_KERNEL);
4424	if (!shared->pin_config)
4425	return -ENOMEM;
4426
4427	for (int i = 0; i < gpios; i++) {
4428	struct ptp_pin_desc *ptp_pin = &shared->pin_config[i];
4429
4430	memset(ptp_pin, 0, sizeof(*ptp_pin));
4431	snprintf(buf: ptp_pin->name,
4432	size: sizeof(ptp_pin->name), fmt: "%s_%02d", pin_name, i);
4433	ptp_pin->index = i;
4434	ptp_pin->func = PTP_PF_NONE;
4435	}
4436
4437	shared->ptp_clock_info.owner = THIS_MODULE;
4438	snprintf(buf: shared->ptp_clock_info.name, size: 30, fmt: "%s", phydev->drv->name);
4439	shared->ptp_clock_info.max_adj = 31249999;
4440	shared->ptp_clock_info.n_alarm = 0;
4441	shared->ptp_clock_info.n_ext_ts = LAN8814_PTP_EXTTS_NUM;
4442	shared->ptp_clock_info.n_pins = gpios;
4443	shared->ptp_clock_info.pps = 0;
4444	shared->ptp_clock_info.supported_extts_flags = PTP_RISING_EDGE |
4445	PTP_FALLING_EDGE |
4446	PTP_STRICT_FLAGS;
4447	shared->ptp_clock_info.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE;
4448	shared->ptp_clock_info.pin_config = shared->pin_config;
4449	shared->ptp_clock_info.n_per_out = LAN8814_PTP_PEROUT_NUM;
4450	shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
4451	shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
4452	shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
4453	shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
4454	shared->ptp_clock_info.getcrosststamp = NULL;
4455	shared->ptp_clock_info.enable = lan8814_ptpci_enable;
4456	shared->ptp_clock_info.verify = lan8814_ptpci_verify;
4457
4458	shared->ptp_clock = ptp_clock_register(info: &shared->ptp_clock_info,
4459	parent: &phydev->mdio.dev);
4460	if (IS_ERR(ptr: shared->ptp_clock)) {
4461	phydev_err(phydev, "ptp_clock_register failed %pe\n",
4462	shared->ptp_clock);
4463	return -EINVAL;
4464	}
4465
4466	/* Check if PHC support is missing at the configuration level */
4467	if (!shared->ptp_clock)
4468	return 0;
4469
4470	phydev_dbg(phydev, "successfully registered ptp clock\n");
4471
4472	/* The EP.4 is shared between all the PHYs in the package and also it
4473	* can be accessed by any of the PHYs
4474	*/
4475	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4476	LTC_HARD_RESET, LTC_HARD_RESET_);
4477	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_OPERATING_MODE,
4478	PTP_OPERATING_MODE_STANDALONE_);
4479
4480	/* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */
4481	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, PTP_CMD_CTL,
4482	PTP_CMD_CTL_PTP_ENABLE_);
4483
4484	return 0;
4485	}
4486
4487	static int lan8814_ptp_probe_once(struct phy_device *phydev)
4488	{
4489	if (!lan8814_has_ptp(phydev))
4490	return 0;
4491
4492	return __lan8814_ptp_probe_once(phydev, pin_name: "lan8814_ptp_pin",
4493	LAN8814_PTP_GPIO_NUM);
4494	}
4495
4496	static void lan8814_setup_led(struct phy_device *phydev, int val)
4497	{
4498	int temp;
4499
4500	temp = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4501	LAN8814_LED_CTRL_1);
4502
4503	if (val)
4504	temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
4505	else
4506	temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
4507
4508	lanphy_write_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
4509	LAN8814_LED_CTRL_1, val: temp);
4510	}
4511
4512	static int lan8814_config_init(struct phy_device *phydev)
4513	{
4514	struct kszphy_priv *lan8814 = phydev->priv;
4515	int ret;
4516
4517	/* Based on the interface type select how the advertise ability is
4518	* encoded, to set as SGMII or as USGMII.
4519	*/
4520	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
4521	ret = lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4522	LAN8814_QSGMII_TX_CONFIG,
4523	LAN8814_QSGMII_TX_CONFIG_QSGMII,
4524	LAN8814_QSGMII_TX_CONFIG_QSGMII);
4525	else
4526	ret = lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4527	LAN8814_QSGMII_TX_CONFIG,
4528	LAN8814_QSGMII_TX_CONFIG_QSGMII,
4529	set: 0);
4530
4531	if (ret < 0)
4532	return ret;
4533
4534	/* MDI-X setting for swap A,B transmit */
4535	lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8814_ALIGN_SWAP,
4536	LAN8814_ALIGN_TX_A_B_SWAP_MASK,
4537	LAN8814_ALIGN_TX_A_B_SWAP);
4538
4539	if (lan8814->led_mode >= 0)
4540	lan8814_setup_led(phydev, val: lan8814->led_mode);
4541
4542	return 0;
4543	}
4544
4545	/* It is expected that there will not be any 'lan8814_take_coma_mode'
4546	* function called in suspend. Because the GPIO line can be shared, so if one of
4547	* the phys goes back in coma mode, then all the other PHYs will go, which is
4548	* wrong.
4549	*/
4550	static int lan8814_release_coma_mode(struct phy_device *phydev)
4551	{
4552	struct gpio_desc *gpiod;
4553
4554	gpiod = devm_gpiod_get_optional(dev: &phydev->mdio.dev, con_id: "coma-mode",
4555	flags: GPIOD_OUT_HIGH_OPEN_DRAIN |
4556	GPIOD_FLAGS_BIT_NONEXCLUSIVE);
4557	if (IS_ERR(ptr: gpiod))
4558	return PTR_ERR(ptr: gpiod);
4559
4560	gpiod_set_consumer_name(desc: gpiod, name: "LAN8814 coma mode");
4561	gpiod_set_value_cansleep(desc: gpiod, value: 0);
4562
4563	return 0;
4564	}
4565
4566	static void lan8814_clear_2psp_bit(struct phy_device *phydev)
4567	{
4568	/* It was noticed that when traffic is passing through the PHY and the
4569	* cable is removed then the LED was still on even though there is no
4570	* link
4571	*/
4572	lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL, LAN8814_EEE_STATE,
4573	LAN8814_EEE_STATE_MASK2P5P,
4574	set: 0);
4575	}
4576
4577	static void lan8814_update_meas_time(struct phy_device *phydev)
4578	{
4579	/* By setting the measure time to a value of 0xb this will allow cables
4580	* longer than 100m to be used. This configuration can be used
4581	* regardless of the mode of operation of the PHY
4582	*/
4583	lanphy_modify_page_reg(phydev, LAN8814_PAGE_AFE_PMA, LAN8814_PD_CONTROLS,
4584	LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK,
4585	LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL);
4586	}
4587
4588	static int lan8814_probe(struct phy_device *phydev)
4589	{
4590	const struct kszphy_type *type = phydev->drv->driver_data;
4591	struct kszphy_priv *priv;
4592	u16 addr;
4593	int err;
4594
4595	priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL);
4596	if (!priv)
4597	return -ENOMEM;
4598
4599	phydev->priv = priv;
4600
4601	priv->type = type;
4602
4603	kszphy_parse_led_mode(phydev);
4604
4605	/* Strap-in value for PHY address, below register read gives starting
4606	* phy address value
4607	*/
4608	addr = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS, addr: 0) & 0x1F;
4609	devm_phy_package_join(dev: &phydev->mdio.dev, phydev,
4610	base_addr: addr, priv_size: sizeof(struct lan8814_shared_priv));
4611
4612	/* There are lan8814 SKUs that don't support PTP. Make sure that for
4613	* those skus no PTP device is created. Here we check if the SKU
4614	* supports PTP.
4615	*/
4616	err = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4617	LAN8814_SKUS);
4618	if (err < 0)
4619	return err;
4620
4621	priv->is_ptp_available = err == LAN8814_REV_LAN8814 ||
4622	err == LAN8814_REV_LAN8818;
4623
4624	if (phy_package_init_once(phydev)) {
4625	/* Reset the PHY */
4626	lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
4627	LAN8814_QSGMII_SOFT_RESET,
4628	LAN8814_QSGMII_SOFT_RESET_BIT,
4629	LAN8814_QSGMII_SOFT_RESET_BIT);
4630
4631	err = lan8814_release_coma_mode(phydev);
4632	if (err)
4633	return err;
4634
4635	err = lan8814_ptp_probe_once(phydev);
4636	if (err)
4637	return err;
4638	}
4639
4640	lan8814_ptp_init(phydev);
4641
4642	/* Errata workarounds */
4643	lan8814_clear_2psp_bit(phydev);
4644	lan8814_update_meas_time(phydev);
4645
4646	return 0;
4647	}
4648
4649	#define LAN8841_MMD_TIMER_REG 0
4650	#define LAN8841_MMD0_REGISTER_17 17
4651	#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
4652	#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
4653	#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
4654	#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
4655	#define LAN8841_MMD_ANALOG_REG 28
4656	#define LAN8841_ANALOG_CONTROL_1 1
4657	#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
4658	#define LAN8841_ANALOG_CONTROL_10 13
4659	#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
4660	#define LAN8841_ANALOG_CONTROL_11 14
4661	#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
4662	#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
4663	#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
4664	#define LAN8841_BTRX_POWER_DOWN 70
4665	#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
4666	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
4667	#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
4668	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
4669	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
4670	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
4671	#define LAN8841_ADC_CHANNEL_MASK 198
4672	#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
4673	#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
4674	#define LAN8841_PTP_RX_VERSION 374
4675	#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
4676	#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
4677	#define LAN8841_PTP_TX_VERSION 438
4678	#define LAN8841_PTP_CMD_CTL 256
4679	#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
4680	#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
4681	#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
4682	#define LAN8841_PTP_RX_PARSE_CONFIG 368
4683	#define LAN8841_PTP_TX_PARSE_CONFIG 432
4684	#define LAN8841_PTP_RX_MODE 381
4685	#define LAN8841_PTP_INSERT_TS_EN BIT(0)
4686	#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
4687
4688	static int lan8841_config_init(struct phy_device *phydev)
4689	{
4690	int ret;
4691
4692	ret = ksz9131_config_init(phydev);
4693	if (ret)
4694	return ret;
4695
4696	/* Initialize the HW by resetting everything */
4697	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4698	LAN8841_PTP_CMD_CTL,
4699	LAN8841_PTP_CMD_CTL_PTP_RESET,
4700	LAN8841_PTP_CMD_CTL_PTP_RESET);
4701
4702	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4703	LAN8841_PTP_CMD_CTL,
4704	LAN8841_PTP_CMD_CTL_PTP_ENABLE,
4705	LAN8841_PTP_CMD_CTL_PTP_ENABLE);
4706
4707	/* Don't process any frames */
4708	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4709	LAN8841_PTP_RX_PARSE_CONFIG, val: 0);
4710	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4711	LAN8841_PTP_TX_PARSE_CONFIG, val: 0);
4712	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4713	LAN8841_PTP_TX_PARSE_L2_ADDR_EN, val: 0);
4714	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4715	LAN8841_PTP_RX_PARSE_L2_ADDR_EN, val: 0);
4716	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4717	LAN8841_PTP_TX_PARSE_IP_ADDR_EN, val: 0);
4718	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4719	LAN8841_PTP_RX_PARSE_IP_ADDR_EN, val: 0);
4720
4721	/* Disable checking for minorVersionPTP field */
4722	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4723	LAN8841_PTP_RX_VERSION, val: 0xff00);
4724	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4725	LAN8841_PTP_TX_VERSION, val: 0xff00);
4726
4727	/* 100BT Clause 40 improvement errata */
4728	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4729	LAN8841_ANALOG_CONTROL_1,
4730	LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
4731	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4732	LAN8841_ANALOG_CONTROL_10,
4733	LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
4734
4735	/* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
4736	* Magnetics
4737	*/
4738	ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4739	LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
4740	if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
4741	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4742	LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
4743	LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
4744	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4745	LAN8841_BTRX_POWER_DOWN,
4746	LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
4747	LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
4748	LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
4749	LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
4750	LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
4751	LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
4752	}
4753
4754	/* LDO Adjustment errata */
4755	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4756	LAN8841_ANALOG_CONTROL_11,
4757	LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
4758
4759	/* 100BT RGMII latency tuning errata */
4760	phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
4761	LAN8841_ADC_CHANNEL_MASK, val: 0x0);
4762	phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
4763	LAN8841_MMD0_REGISTER_17,
4764	LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
4765	LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
4766
4767	return 0;
4768	}
4769
4770	#define LAN8841_OUTPUT_CTRL 25
4771	#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
4772	#define LAN8841_INT_PTP BIT(9)
4773
4774	static int lan8841_config_intr(struct phy_device *phydev)
4775	{
4776	int err;
4777
4778	phy_modify(phydev, LAN8841_OUTPUT_CTRL,
4779	LAN8841_OUTPUT_CTRL_INT_BUFFER, set: 0);
4780
4781	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4782	err = phy_read(phydev, LAN8814_INTS);
4783	if (err < 0)
4784	return err;
4785
4786	/* Enable / disable interrupts. It is OK to enable PTP interrupt
4787	* even if it PTP is not enabled. Because the underneath blocks
4788	* will not enable the PTP so we will never get the PTP
4789	* interrupt.
4790	*/
4791	err = phy_write(phydev, LAN8814_INTC,
4792	LAN8814_INT_LINK | LAN8841_INT_PTP);
4793	} else {
4794	err = phy_write(phydev, LAN8814_INTC, val: 0);
4795	if (err)
4796	return err;
4797
4798	err = phy_read(phydev, LAN8814_INTS);
4799	if (err < 0)
4800	return err;
4801
4802	/* Getting a positive value doesn't mean that is an error, it
4803	* just indicates what was the status. Therefore make sure to
4804	* clear the value and say that there is no error.
4805	*/
4806	err = 0;
4807	}
4808
4809	return err;
4810	}
4811
4812	#define LAN8841_PTP_TX_EGRESS_SEC_LO 453
4813	#define LAN8841_PTP_TX_EGRESS_SEC_HI 452
4814	#define LAN8841_PTP_TX_EGRESS_NS_LO 451
4815	#define LAN8841_PTP_TX_EGRESS_NS_HI 450
4816	#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
4817	#define LAN8841_PTP_TX_MSG_HEADER2 455
4818
4819	static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
4820	u32 *sec, u32 *nsec, u16 *seq)
4821	{
4822	struct phy_device *phydev = ptp_priv->phydev;
4823
4824	*nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_HI);
4825	if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
4826	return false;
4827
4828	*nsec = ((*nsec & 0x3fff) << 16);
4829	*nsec = *nsec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_LO);
4830
4831	*sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
4832	*sec = *sec << 16;
4833	*sec = *sec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
4834
4835	*seq = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2);
4836
4837	return true;
4838	}
4839
4840	static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
4841	{
4842	u32 sec, nsec;
4843	u16 seq;
4844
4845	while (lan8841_ptp_get_tx_ts(ptp_priv, sec: &sec, nsec: &nsec, seq: &seq))
4846	lan8814_match_tx_skb(ptp_priv, seconds: sec, nsec, seq_id: seq);
4847	}
4848
4849	#define LAN8841_PTP_INT_STS 259
4850	#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
4851	#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
4852	#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
4853
4854	static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
4855	{
4856	struct phy_device *phydev = ptp_priv->phydev;
4857	int i;
4858
4859	for (i = 0; i < FIFO_SIZE; ++i)
4860	phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2);
4861
4862	phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS);
4863	}
4864
4865	#define LAN8841_PTP_GPIO_CAP_STS 506
4866	#define LAN8841_PTP_GPIO_SEL 327
4867	#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
4868	#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
4869	#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
4870	#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
4871	#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
4872	#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
4873	#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
4874	#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
4875	#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
4876
4877	static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
4878	{
4879	struct phy_device *phydev = ptp_priv->phydev;
4880	struct ptp_clock_event ptp_event = {0};
4881	int pin, ret, tmp;
4882	s32 sec, nsec;
4883
4884	pin = ptp_find_pin_unlocked(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: 0);
4885	if (pin == -1)
4886	return;
4887
4888	tmp = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_STS);
4889	if (tmp < 0)
4890	return;
4891
4892	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL,
4893	LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
4894	if (ret)
4895	return;
4896
4897	mutex_lock(&ptp_priv->ptp_lock);
4898	if (tmp & BIT(pin)) {
4899	sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
4900	sec <<= 16;
4901	sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
4902
4903	nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
4904	nsec <<= 16;
4905	nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
4906	} else {
4907	sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
4908	sec <<= 16;
4909	sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
4910
4911	nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
4912	nsec <<= 16;
4913	nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
4914	}
4915	mutex_unlock(lock: &ptp_priv->ptp_lock);
4916	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL, val: 0);
4917	if (ret)
4918	return;
4919
4920	ptp_event.index = 0;
4921	ptp_event.timestamp = ktime_set(secs: sec, nsecs: nsec);
4922	ptp_event.type = PTP_CLOCK_EXTTS;
4923	ptp_clock_event(ptp: ptp_priv->ptp_clock, event: &ptp_event);
4924	}
4925
4926	static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
4927	{
4928	struct kszphy_priv *priv = phydev->priv;
4929	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4930	u16 status;
4931
4932	do {
4933	status = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS);
4934
4935	if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
4936	lan8841_ptp_process_tx_ts(ptp_priv);
4937
4938	if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
4939	lan8841_gpio_process_cap(ptp_priv);
4940
4941	if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
4942	lan8841_ptp_flush_fifo(ptp_priv);
4943	skb_queue_purge(list: &ptp_priv->tx_queue);
4944	}
4945
4946	} while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
4947	LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
4948	LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
4949	}
4950
4951	#define LAN8841_INTS_PTP BIT(9)
4952
4953	static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
4954	{
4955	irqreturn_t ret = IRQ_NONE;
4956	int irq_status;
4957
4958	irq_status = phy_read(phydev, LAN8814_INTS);
4959	if (irq_status < 0) {
4960	phy_error(phydev);
4961	return IRQ_NONE;
4962	}
4963
4964	if (irq_status & LAN8814_INT_LINK) {
4965	phy_trigger_machine(phydev);
4966	ret = IRQ_HANDLED;
4967	}
4968
4969	if (irq_status & LAN8841_INTS_PTP) {
4970	lan8841_handle_ptp_interrupt(phydev);
4971	ret = IRQ_HANDLED;
4972	}
4973
4974	return ret;
4975	}
4976
4977	static int lan8841_ts_info(struct mii_timestamper *mii_ts,
4978	struct kernel_ethtool_ts_info *info)
4979	{
4980	struct kszphy_ptp_priv *ptp_priv;
4981
4982	ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4983
4984	info->phc_index = ptp_priv->ptp_clock ?
4985	ptp_clock_index(ptp: ptp_priv->ptp_clock) : -1;
4986	if (info->phc_index == -1)
4987	return 0;
4988
4989	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
4990	SOF_TIMESTAMPING_RX_HARDWARE |
4991	SOF_TIMESTAMPING_RAW_HARDWARE;
4992
4993	info->tx_types = (1 << HWTSTAMP_TX_OFF) |
4994	(1 << HWTSTAMP_TX_ON) |
4995	(1 << HWTSTAMP_TX_ONESTEP_SYNC);
4996
4997	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
4998	(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
4999	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5000	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
5001
5002	return 0;
5003	}
5004
5005	#define LAN8841_PTP_INT_EN 260
5006	#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
5007	#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
5008
5009	static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
5010	bool enable)
5011	{
5012	struct phy_device *phydev = ptp_priv->phydev;
5013
5014	if (enable) {
5015	/* Enable interrupts on the TX side */
5016	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5017	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
5018	LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
5019	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
5020	LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
5021
5022	/* Enable the modification of the frame on RX side,
5023	* this will add the ns and 2 bits of sec in the reserved field
5024	* of the PTP header
5025	*/
5026	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5027	LAN8841_PTP_RX_MODE,
5028	LAN8841_PTP_INSERT_TS_EN |
5029	LAN8841_PTP_INSERT_TS_32BIT,
5030	LAN8841_PTP_INSERT_TS_EN |
5031	LAN8841_PTP_INSERT_TS_32BIT);
5032
5033	ptp_schedule_worker(ptp: ptp_priv->ptp_clock, delay: 0);
5034	} else {
5035	/* Disable interrupts on the TX side */
5036	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5037	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
5038	LAN8841_PTP_INT_EN_PTP_TX_TS_EN, set: 0);
5039
5040	/* Disable modification of the RX frames */
5041	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5042	LAN8841_PTP_RX_MODE,
5043	LAN8841_PTP_INSERT_TS_EN |
5044	LAN8841_PTP_INSERT_TS_32BIT, set: 0);
5045
5046	ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock);
5047	}
5048	}
5049
5050	#define LAN8841_PTP_RX_TIMESTAMP_EN 379
5051	#define LAN8841_PTP_TX_TIMESTAMP_EN 443
5052	#define LAN8841_PTP_TX_MOD 445
5053
5054	static int lan8841_hwtstamp_set(struct mii_timestamper *mii_ts,
5055	struct kernel_hwtstamp_config *config,
5056	struct netlink_ext_ack *extack)
5057	{
5058	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
5059	struct phy_device *phydev = ptp_priv->phydev;
5060	int txcfg = 0, rxcfg = 0;
5061	int pkt_ts_enable;
5062
5063	ptp_priv->hwts_tx_type = config->tx_type;
5064	ptp_priv->rx_filter = config->rx_filter;
5065
5066	switch (config->rx_filter) {
5067	case HWTSTAMP_FILTER_NONE:
5068	ptp_priv->layer = 0;
5069	ptp_priv->version = 0;
5070	break;
5071	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5072	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5073	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5074	ptp_priv->layer = PTP_CLASS_L4;
5075	ptp_priv->version = PTP_CLASS_V2;
5076	break;
5077	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5078	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5079	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5080	ptp_priv->layer = PTP_CLASS_L2;
5081	ptp_priv->version = PTP_CLASS_V2;
5082	break;
5083	case HWTSTAMP_FILTER_PTP_V2_EVENT:
5084	case HWTSTAMP_FILTER_PTP_V2_SYNC:
5085	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5086	ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
5087	ptp_priv->version = PTP_CLASS_V2;
5088	break;
5089	default:
5090	return -ERANGE;
5091	}
5092
5093	/* Setup parsing of the frames and enable the timestamping for ptp
5094	* frames
5095	*/
5096	if (ptp_priv->layer & PTP_CLASS_L2) {
5097	rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
5098	txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
5099	} else if (ptp_priv->layer & PTP_CLASS_L4) {
5100	rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
5101	txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
5102	}
5103
5104	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_PARSE_CONFIG, val: rxcfg);
5105	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_PARSE_CONFIG, val: txcfg);
5106
5107	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
5108	PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
5109	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable);
5110	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable);
5111
5112	/* Enable / disable of the TX timestamp in the SYNC frames */
5113	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_TX_MOD,
5114	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
5115	set: ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
5116	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
5117
5118	/* Now enable/disable the timestamping */
5119	lan8841_ptp_enable_processing(ptp_priv,
5120	enable: config->rx_filter != HWTSTAMP_FILTER_NONE);
5121
5122	skb_queue_purge(list: &ptp_priv->tx_queue);
5123
5124	lan8841_ptp_flush_fifo(ptp_priv);
5125
5126	return 0;
5127	}
5128
5129	static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
5130	struct sk_buff *skb, int type)
5131	{
5132	struct kszphy_ptp_priv *ptp_priv =
5133	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
5134	struct ptp_header *header = ptp_parse_header(skb, type);
5135	struct skb_shared_hwtstamps *shhwtstamps;
5136	struct timespec64 ts;
5137	unsigned long flags;
5138	u32 ts_header;
5139
5140	if (!header)
5141	return false;
5142
5143	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
5144	type == PTP_CLASS_NONE)
5145	return false;
5146
5147	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
5148	return false;
5149
5150	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5151	ts.tv_sec = ptp_priv->seconds;
5152	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
5153	ts_header = __be32_to_cpu(header->reserved2);
5154
5155	shhwtstamps = skb_hwtstamps(skb);
5156	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
5157
5158	/* Check for any wrap arounds for the second part */
5159	if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
5160	ts.tv_sec -= GENMASK(1, 0) + 1;
5161	else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
5162	ts.tv_sec += 1;
5163
5164	shhwtstamps->hwtstamp =
5165	ktime_set(secs: (ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
5166	nsecs: ts_header & GENMASK(29, 0));
5167	header->reserved2 = 0;
5168
5169	netif_rx(skb);
5170
5171	return true;
5172	}
5173
5174	#define LAN8841_EVENT_A 0
5175	#define LAN8841_EVENT_B 1
5176	#define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
5177	#define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
5178	#define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
5179	#define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
5180
5181	static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
5182	s64 sec, u32 nsec)
5183	{
5184	struct phy_device *phydev = ptp_priv->phydev;
5185	int ret;
5186
5187	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
5188	upper_16_bits(sec));
5189	if (ret)
5190	return ret;
5191
5192	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
5193	lower_16_bits(sec));
5194	if (ret)
5195	return ret;
5196
5197	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
5198	upper_16_bits(nsec));
5199	if (ret)
5200	return ret;
5201
5202	return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
5203	lower_16_bits(nsec));
5204	}
5205
5206	#define LAN8841_BUFFER_TIME 2
5207
5208	static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
5209	const struct timespec64 *ts)
5210	{
5211	return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
5212	sec: ts->tv_sec + LAN8841_BUFFER_TIME, nsec: 0);
5213	}
5214
5215	#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
5216	#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
5217	#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
5218	#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
5219
5220	static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
5221	s64 sec, u32 nsec)
5222	{
5223	struct phy_device *phydev = ptp_priv->phydev;
5224	int ret;
5225
5226	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
5227	upper_16_bits(sec));
5228	if (ret)
5229	return ret;
5230
5231	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
5232	lower_16_bits(sec));
5233	if (ret)
5234	return ret;
5235
5236	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
5237	upper_16_bits(nsec));
5238	if (ret)
5239	return ret;
5240
5241	return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
5242	lower_16_bits(nsec));
5243	}
5244
5245	#define LAN8841_PTP_LTC_SET_SEC_HI 262
5246	#define LAN8841_PTP_LTC_SET_SEC_MID 263
5247	#define LAN8841_PTP_LTC_SET_SEC_LO 264
5248	#define LAN8841_PTP_LTC_SET_NS_HI 265
5249	#define LAN8841_PTP_LTC_SET_NS_LO 266
5250	#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
5251
5252	static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
5253	const struct timespec64 *ts)
5254	{
5255	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5256	ptp_clock_info);
5257	struct phy_device *phydev = ptp_priv->phydev;
5258	unsigned long flags;
5259	int ret;
5260
5261	/* Set the value to be stored */
5262	mutex_lock(&ptp_priv->ptp_lock);
5263	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
5264	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
5265	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
5266	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
5267	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
5268
5269	/* Set the command to load the LTC */
5270	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
5271	LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
5272	ret = lan8841_ptp_update_target(ptp_priv, ts);
5273	mutex_unlock(lock: &ptp_priv->ptp_lock);
5274
5275	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5276	ptp_priv->seconds = ts->tv_sec;
5277	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
5278
5279	return ret;
5280	}
5281
5282	#define LAN8841_PTP_LTC_RD_SEC_HI 358
5283	#define LAN8841_PTP_LTC_RD_SEC_MID 359
5284	#define LAN8841_PTP_LTC_RD_SEC_LO 360
5285	#define LAN8841_PTP_LTC_RD_NS_HI 361
5286	#define LAN8841_PTP_LTC_RD_NS_LO 362
5287	#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
5288
5289	static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
5290	struct timespec64 *ts)
5291	{
5292	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5293	ptp_clock_info);
5294	struct phy_device *phydev = ptp_priv->phydev;
5295	time64_t s;
5296	s64 ns;
5297
5298	mutex_lock(&ptp_priv->ptp_lock);
5299	/* Issue the command to read the LTC */
5300	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
5301	LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
5302
5303	/* Read the LTC */
5304	s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI);
5305	s <<= 16;
5306	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID);
5307	s <<= 16;
5308	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO);
5309
5310	ns = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
5311	ns <<= 16;
5312	ns |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_LO);
5313	mutex_unlock(lock: &ptp_priv->ptp_lock);
5314
5315	set_normalized_timespec64(ts, sec: s, nsec: ns);
5316	return 0;
5317	}
5318
5319	static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
5320	struct timespec64 *ts)
5321	{
5322	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5323	ptp_clock_info);
5324	struct phy_device *phydev = ptp_priv->phydev;
5325	time64_t s;
5326
5327	mutex_lock(&ptp_priv->ptp_lock);
5328	/* Issue the command to read the LTC */
5329	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
5330	LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
5331
5332	/* Read the LTC */
5333	s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI);
5334	s <<= 16;
5335	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID);
5336	s <<= 16;
5337	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO);
5338	mutex_unlock(lock: &ptp_priv->ptp_lock);
5339
5340	set_normalized_timespec64(ts, sec: s, nsec: 0);
5341	}
5342
5343	#define LAN8841_PTP_LTC_STEP_ADJ_LO 276
5344	#define LAN8841_PTP_LTC_STEP_ADJ_HI 275
5345	#define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
5346	#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
5347	#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
5348
5349	static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
5350	{
5351	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5352	ptp_clock_info);
5353	struct phy_device *phydev = ptp_priv->phydev;
5354	struct timespec64 ts;
5355	bool add = true;
5356	u32 nsec;
5357	s32 sec;
5358	int ret;
5359
5360	/* The HW allows up to 15 sec to adjust the time, but here we limit to
5361	* 10 sec the adjustment. The reason is, in case the adjustment is 14
5362	* sec and 999999999 nsec, then we add 8ns to compansate the actual
5363	* increment so the value can be bigger than 15 sec. Therefore limit the
5364	* possible adjustments so we will not have these corner cases
5365	*/
5366	if (delta > 10000000000LL || delta < -10000000000LL) {
5367	/* The timeadjustment is too big, so fall back using set time */
5368	u64 now;
5369
5370	ptp->gettime64(ptp, &ts);
5371
5372	now = ktime_to_ns(kt: timespec64_to_ktime(ts));
5373	ts = ns_to_timespec64(nsec: now + delta);
5374
5375	ptp->settime64(ptp, &ts);
5376	return 0;
5377	}
5378
5379	sec = div_u64_rem(dividend: delta < 0 ? -delta : delta, NSEC_PER_SEC, remainder: &nsec);
5380	if (delta < 0 && nsec != 0) {
5381	/* It is not allowed to adjust low the nsec part, therefore
5382	* subtract more from second part and add to nanosecond such
5383	* that would roll over, so the second part will increase
5384	*/
5385	sec--;
5386	nsec = NSEC_PER_SEC - nsec;
5387	}
5388
5389	/* Calculate the adjustments and the direction */
5390	if (delta < 0)
5391	add = false;
5392
5393	if (nsec > 0)
5394	/* add 8 ns to cover the likely normal increment */
5395	nsec += 8;
5396
5397	if (nsec >= NSEC_PER_SEC) {
5398	/* carry into seconds */
5399	sec++;
5400	nsec -= NSEC_PER_SEC;
5401	}
5402
5403	mutex_lock(&ptp_priv->ptp_lock);
5404	if (sec) {
5405	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO, val: sec);
5406	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
5407	val: add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
5408	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
5409	LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
5410	}
5411
5412	if (nsec) {
5413	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
5414	val: nsec & 0xffff);
5415	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
5416	val: (nsec >> 16) & 0x3fff);
5417	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
5418	LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
5419	}
5420	mutex_unlock(lock: &ptp_priv->ptp_lock);
5421
5422	/* Update the target clock */
5423	ptp->gettime64(ptp, &ts);
5424	mutex_lock(&ptp_priv->ptp_lock);
5425	ret = lan8841_ptp_update_target(ptp_priv, ts: &ts);
5426	mutex_unlock(lock: &ptp_priv->ptp_lock);
5427
5428	return ret;
5429	}
5430
5431	#define LAN8841_PTP_LTC_RATE_ADJ_HI 269
5432	#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
5433	#define LAN8841_PTP_LTC_RATE_ADJ_LO 270
5434
5435	static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
5436	{
5437	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5438	ptp_clock_info);
5439	struct phy_device *phydev = ptp_priv->phydev;
5440	bool faster = true;
5441	u32 rate;
5442
5443	if (!scaled_ppm)
5444	return 0;
5445
5446	if (scaled_ppm < 0) {
5447	scaled_ppm = -scaled_ppm;
5448	faster = false;
5449	}
5450
5451	rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
5452	rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
5453
5454	mutex_lock(&ptp_priv->ptp_lock);
5455	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
5456	val: faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
5457	: upper_16_bits(rate) & 0x3fff);
5458	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
5459	mutex_unlock(lock: &ptp_priv->ptp_lock);
5460
5461	return 0;
5462	}
5463
5464	static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
5465	enum ptp_pin_function func, unsigned int chan)
5466	{
5467	switch (func) {
5468	case PTP_PF_NONE:
5469	case PTP_PF_PEROUT:
5470	case PTP_PF_EXTTS:
5471	break;
5472	default:
5473	return -1;
5474	}
5475
5476	return 0;
5477	}
5478
5479	#define LAN8841_PTP_GPIO_NUM 10
5480	#define LAN8841_GPIO_EN 128
5481	#define LAN8841_GPIO_DIR 129
5482	#define LAN8841_GPIO_BUF 130
5483
5484	static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
5485	{
5486	struct phy_device *phydev = ptp_priv->phydev;
5487	int ret;
5488
5489	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5490	if (ret)
5491	return ret;
5492
5493	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin));
5494	if (ret)
5495	return ret;
5496
5497	return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5498	}
5499
5500	static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
5501	{
5502	struct phy_device *phydev = ptp_priv->phydev;
5503	int ret;
5504
5505	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5506	if (ret)
5507	return ret;
5508
5509	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin));
5510	if (ret)
5511	return ret;
5512
5513	return phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5514	}
5515
5516	#define LAN8841_GPIO_DATA_SEL1 131
5517	#define LAN8841_GPIO_DATA_SEL2 132
5518	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
5519	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
5520	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
5521	#define LAN8841_PTP_GENERAL_CONFIG 257
5522	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
5523	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
5524	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
5525	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
5526	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
5527	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
5528
5529	static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
5530	u8 event)
5531	{
5532	struct phy_device *phydev = ptp_priv->phydev;
5533	u16 tmp;
5534	int ret;
5535
5536	/* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
5537	* pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
5538	* depending on the pin, it requires to read a different register
5539	*/
5540	if (pin < 5) {
5541	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
5542	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1, val: tmp);
5543	} else {
5544	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
5545	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2, val: tmp);
5546	}
5547	if (ret)
5548	return ret;
5549
5550	/* Disable the event */
5551	if (event == LAN8841_EVENT_A)
5552	tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5553	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
5554	else
5555	tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5556	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
5557	return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, val: tmp);
5558	}
5559
5560	static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
5561	u8 event, int pulse_width)
5562	{
5563	struct phy_device *phydev = ptp_priv->phydev;
5564	u16 tmp;
5565	int ret;
5566
5567	/* Enable the event */
5568	if (event == LAN8841_EVENT_A)
5569	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG,
5570	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5571	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
5572	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5573	pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
5574	else
5575	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG,
5576	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5577	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
5578	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5579	pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
5580	if (ret)
5581	return ret;
5582
5583	/* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
5584	* pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
5585	* depending on the pin, it requires to read a different register
5586	*/
5587	if (event == LAN8841_EVENT_A)
5588	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
5589	else
5590	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
5591
5592	if (pin < 5)
5593	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1,
5594	val: tmp << (3 * pin));
5595	else
5596	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2,
5597	val: tmp << (3 * (pin - 5)));
5598
5599	return ret;
5600	}
5601
5602	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
5603	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
5604	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
5605	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
5606	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
5607	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
5608	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
5609	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
5610	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
5611	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
5612	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
5613	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
5614	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
5615	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
5616
5617	static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
5618	struct ptp_clock_request *rq, int on)
5619	{
5620	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5621	ptp_clock_info);
5622	struct phy_device *phydev = ptp_priv->phydev;
5623	struct timespec64 ts_on, ts_period;
5624	s64 on_nsec, period_nsec;
5625	int pulse_width;
5626	int pin;
5627	int ret;
5628
5629	pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_PEROUT, chan: rq->perout.index);
5630	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5631	return -EINVAL;
5632
5633	if (!on) {
5634	ret = lan8841_ptp_perout_off(ptp_priv, pin);
5635	if (ret)
5636	return ret;
5637
5638	return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, event: pin);
5639	}
5640
5641	ts_on.tv_sec = rq->perout.on.sec;
5642	ts_on.tv_nsec = rq->perout.on.nsec;
5643	on_nsec = timespec64_to_ns(ts: &ts_on);
5644
5645	ts_period.tv_sec = rq->perout.period.sec;
5646	ts_period.tv_nsec = rq->perout.period.nsec;
5647	period_nsec = timespec64_to_ns(ts: &ts_period);
5648
5649	if (period_nsec < 200) {
5650	pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
5651	phydev_name(phydev));
5652	return -EOPNOTSUPP;
5653	}
5654
5655	if (on_nsec >= period_nsec) {
5656	pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
5657	phydev_name(phydev));
5658	return -EINVAL;
5659	}
5660
5661	switch (on_nsec) {
5662	case 200000000:
5663	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
5664	break;
5665	case 100000000:
5666	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
5667	break;
5668	case 50000000:
5669	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
5670	break;
5671	case 10000000:
5672	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
5673	break;
5674	case 5000000:
5675	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
5676	break;
5677	case 1000000:
5678	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
5679	break;
5680	case 500000:
5681	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
5682	break;
5683	case 100000:
5684	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
5685	break;
5686	case 50000:
5687	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
5688	break;
5689	case 10000:
5690	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
5691	break;
5692	case 5000:
5693	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
5694	break;
5695	case 1000:
5696	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
5697	break;
5698	case 500:
5699	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
5700	break;
5701	case 100:
5702	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5703	break;
5704	default:
5705	pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
5706	phydev_name(phydev));
5707	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5708	break;
5709	}
5710
5711	mutex_lock(&ptp_priv->ptp_lock);
5712	ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.start.sec,
5713	nsec: rq->perout.start.nsec);
5714	mutex_unlock(lock: &ptp_priv->ptp_lock);
5715	if (ret)
5716	return ret;
5717
5718	ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.period.sec,
5719	nsec: rq->perout.period.nsec);
5720	if (ret)
5721	return ret;
5722
5723	ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
5724	pulse_width);
5725	if (ret)
5726	return ret;
5727
5728	ret = lan8841_ptp_perout_on(ptp_priv, pin);
5729	if (ret)
5730	lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
5731
5732	return ret;
5733	}
5734
5735	#define LAN8841_PTP_GPIO_CAP_EN 496
5736	#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
5737	#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
5738	#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
5739
5740	static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
5741	u32 flags)
5742	{
5743	struct phy_device *phydev = ptp_priv->phydev;
5744	u16 tmp = 0;
5745	int ret;
5746
5747	/* Set GPIO to be input */
5748	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5749	if (ret)
5750	return ret;
5751
5752	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5753	if (ret)
5754	return ret;
5755
5756	/* Enable capture on the edges of the pin */
5757	if (flags & PTP_RISING_EDGE)
5758	tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
5759	if (flags & PTP_FALLING_EDGE)
5760	tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
5761	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN, val: tmp);
5762	if (ret)
5763	return ret;
5764
5765	/* Enable interrupt */
5766	return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5767	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5768	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
5769	}
5770
5771	static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
5772	{
5773	struct phy_device *phydev = ptp_priv->phydev;
5774	int ret;
5775
5776	/* Set GPIO to be output */
5777	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5778	if (ret)
5779	return ret;
5780
5781	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5782	if (ret)
5783	return ret;
5784
5785	/* Disable capture on both of the edges */
5786	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN,
5787	LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
5788	LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
5789	set: 0);
5790	if (ret)
5791	return ret;
5792
5793	/* Disable interrupt */
5794	return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5795	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5796	set: 0);
5797	}
5798
5799	static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
5800	struct ptp_clock_request *rq, int on)
5801	{
5802	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5803	ptp_clock_info);
5804	int pin;
5805	int ret;
5806
5807	/* Reject requests with unsupported flags */
5808	if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
5809	PTP_EXTTS_EDGES |
5810	PTP_STRICT_FLAGS))
5811	return -EOPNOTSUPP;
5812
5813	pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: rq->extts.index);
5814	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5815	return -EINVAL;
5816
5817	mutex_lock(&ptp_priv->ptp_lock);
5818	if (on)
5819	ret = lan8841_ptp_extts_on(ptp_priv, pin, flags: rq->extts.flags);
5820	else
5821	ret = lan8841_ptp_extts_off(ptp_priv, pin);
5822	mutex_unlock(lock: &ptp_priv->ptp_lock);
5823
5824	return ret;
5825	}
5826
5827	static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
5828	struct ptp_clock_request *rq, int on)
5829	{
5830	switch (rq->type) {
5831	case PTP_CLK_REQ_EXTTS:
5832	return lan8841_ptp_extts(ptp, rq, on);
5833	case PTP_CLK_REQ_PEROUT:
5834	return lan8841_ptp_perout(ptp, rq, on);
5835	default:
5836	return -EOPNOTSUPP;
5837	}
5838
5839	return 0;
5840	}
5841
5842	static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
5843	{
5844	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5845	ptp_clock_info);
5846	struct timespec64 ts;
5847	unsigned long flags;
5848
5849	lan8841_ptp_getseconds(ptp: &ptp_priv->ptp_clock_info, ts: &ts);
5850
5851	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5852	ptp_priv->seconds = ts.tv_sec;
5853	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
5854
5855	return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
5856	}
5857
5858	static struct ptp_clock_info lan8841_ptp_clock_info = {
5859	.owner = THIS_MODULE,
5860	.name = "lan8841 ptp",
5861	.max_adj = 31249999,
5862	.gettime64 = lan8841_ptp_gettime64,
5863	.settime64 = lan8841_ptp_settime64,
5864	.adjtime = lan8841_ptp_adjtime,
5865	.adjfine = lan8841_ptp_adjfine,
5866	.verify = lan8841_ptp_verify,
5867	.enable = lan8841_ptp_enable,
5868	.do_aux_work = lan8841_ptp_do_aux_work,
5869	.n_per_out = LAN8841_PTP_GPIO_NUM,
5870	.n_ext_ts = LAN8841_PTP_GPIO_NUM,
5871	.n_pins = LAN8841_PTP_GPIO_NUM,
5872	.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE,
5873	};
5874
5875	#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
5876	#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
5877
5878	static int lan8841_probe(struct phy_device *phydev)
5879	{
5880	struct kszphy_ptp_priv *ptp_priv;
5881	struct kszphy_priv *priv;
5882	int err;
5883
5884	err = kszphy_probe(phydev);
5885	if (err)
5886	return err;
5887
5888	if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5889	LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
5890	LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
5891	phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
5892
5893	/* Register the clock */
5894	if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
5895	return 0;
5896
5897	priv = phydev->priv;
5898	ptp_priv = &priv->ptp_priv;
5899
5900	ptp_priv->pin_config = devm_kcalloc(dev: &phydev->mdio.dev,
5901	LAN8841_PTP_GPIO_NUM,
5902	size: sizeof(*ptp_priv->pin_config),
5903	GFP_KERNEL);
5904	if (!ptp_priv->pin_config)
5905	return -ENOMEM;
5906
5907	for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
5908	struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
5909
5910	snprintf(buf: p->name, size: sizeof(p->name), fmt: "pin%d", i);
5911	p->index = i;
5912	p->func = PTP_PF_NONE;
5913	}
5914
5915	ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
5916	ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
5917	ptp_priv->ptp_clock = ptp_clock_register(info: &ptp_priv->ptp_clock_info,
5918	parent: &phydev->mdio.dev);
5919	if (IS_ERR(ptr: ptp_priv->ptp_clock)) {
5920	phydev_err(phydev, "ptp_clock_register failed: %pe\n",
5921	ptp_priv->ptp_clock);
5922	return -EINVAL;
5923	}
5924
5925	if (!ptp_priv->ptp_clock)
5926	return 0;
5927
5928	/* Initialize the SW */
5929	skb_queue_head_init(list: &ptp_priv->tx_queue);
5930	ptp_priv->phydev = phydev;
5931	mutex_init(&ptp_priv->ptp_lock);
5932	spin_lock_init(&ptp_priv->seconds_lock);
5933
5934	ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
5935	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
5936	ptp_priv->mii_ts.hwtstamp_set = lan8841_hwtstamp_set;
5937	ptp_priv->mii_ts.ts_info = lan8841_ts_info;
5938
5939	phydev->mii_ts = &ptp_priv->mii_ts;
5940
5941	/* Timestamp selected by default to keep legacy API */
5942	phydev->default_timestamp = true;
5943
5944	return 0;
5945	}
5946
5947	static int lan8804_resume(struct phy_device *phydev)
5948	{
5949	return kszphy_resume(phydev);
5950	}
5951
5952	static int lan8804_suspend(struct phy_device *phydev)
5953	{
5954	return kszphy_generic_suspend(phydev);
5955	}
5956
5957	static int lan8841_resume(struct phy_device *phydev)
5958	{
5959	return kszphy_generic_resume(phydev);
5960	}
5961
5962	static int lan8841_suspend(struct phy_device *phydev)
5963	{
5964	struct kszphy_priv *priv = phydev->priv;
5965	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
5966
5967	if (ptp_priv->ptp_clock)
5968	ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock);
5969
5970	return kszphy_generic_suspend(phydev);
5971	}
5972
5973	static int ksz9131_resume(struct phy_device *phydev)
5974	{
5975	if (phydev->suspended && phy_interface_is_rgmii(phydev))
5976	ksz9131_config_rgmii_delay(phydev);
5977
5978	return kszphy_resume(phydev);
5979	}
5980
5981	#define LAN8842_PTP_GPIO_NUM 16
5982
5983	static int lan8842_ptp_probe_once(struct phy_device *phydev)
5984	{
5985	return __lan8814_ptp_probe_once(phydev, pin_name: "lan8842_ptp_pin",
5986	LAN8842_PTP_GPIO_NUM);
5987	}
5988
5989	#define LAN8842_STRAP_REG 0 /* 0x0 */
5990	#define LAN8842_STRAP_REG_PHYADDR_MASK GENMASK(4, 0)
5991	#define LAN8842_SKU_REG 11 /* 0x0b */
5992	#define LAN8842_SELF_TEST 14 /* 0x0e */
5993	#define LAN8842_SELF_TEST_RX_CNT_ENA BIT(8)
5994	#define LAN8842_SELF_TEST_TX_CNT_ENA BIT(4)
5995
5996	static int lan8842_probe(struct phy_device *phydev)
5997	{
5998	struct lan8842_priv *priv;
5999	int addr;
6000	int ret;
6001
6002	priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL);
6003	if (!priv)
6004	return -ENOMEM;
6005
6006	phydev->priv = priv;
6007
6008	/* Similar to lan8814 this PHY has a pin which needs to be pulled down
6009	* to enable to pass any traffic through it. Therefore use the same
6010	* function as lan8814
6011	*/
6012	ret = lan8814_release_coma_mode(phydev);
6013	if (ret)
6014	return ret;
6015
6016	/* Enable to count the RX and TX packets */
6017	ret = lanphy_write_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL,
6018	LAN8842_SELF_TEST,
6019	LAN8842_SELF_TEST_RX_CNT_ENA |
6020	LAN8842_SELF_TEST_TX_CNT_ENA);
6021	if (ret < 0)
6022	return ret;
6023
6024	/* Revision lan8832 doesn't have support for PTP, therefore don't add
6025	* any PTP clocks
6026	*/
6027	ret = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
6028	LAN8842_SKU_REG);
6029	if (ret < 0)
6030	return ret;
6031
6032	priv->rev = ret;
6033	if (priv->rev == LAN8842_REV_8832)
6034	return 0;
6035
6036	/* As the lan8814 and lan8842 has the same IP for the PTP block, the
6037	* only difference is the number of the GPIOs, then make sure that the
6038	* lan8842 initialized also the shared data pointer as this is used in
6039	* all the PTP functions for lan8814. The lan8842 doesn't have multiple
6040	* PHYs in the same package.
6041	*/
6042	addr = lanphy_read_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
6043	LAN8842_STRAP_REG);
6044	if (addr < 0)
6045	return addr;
6046	addr &= LAN8842_STRAP_REG_PHYADDR_MASK;
6047
6048	ret = devm_phy_package_join(dev: &phydev->mdio.dev, phydev, base_addr: addr,
6049	priv_size: sizeof(struct lan8814_shared_priv));
6050	if (ret)
6051	return ret;
6052
6053	if (phy_package_init_once(phydev)) {
6054	ret = lan8842_ptp_probe_once(phydev);
6055	if (ret)
6056	return ret;
6057	}
6058
6059	lan8814_ptp_init(phydev);
6060
6061	return 0;
6062	}
6063
6064	#define LAN8814_POWER_MGMT_MODE_3_ANEG_MDI 0x13
6065	#define LAN8814_POWER_MGMT_MODE_4_ANEG_MDIX 0x14
6066	#define LAN8814_POWER_MGMT_MODE_5_10BT_MDI 0x15
6067	#define LAN8814_POWER_MGMT_MODE_6_10BT_MDIX 0x16
6068	#define LAN8814_POWER_MGMT_MODE_7_100BT_TRAIN 0x17
6069	#define LAN8814_POWER_MGMT_MODE_8_100BT_MDI 0x18
6070	#define LAN8814_POWER_MGMT_MODE_9_100BT_EEE_MDI_TX 0x19
6071	#define LAN8814_POWER_MGMT_MODE_10_100BT_EEE_MDI_RX 0x1a
6072	#define LAN8814_POWER_MGMT_MODE_11_100BT_MDIX 0x1b
6073	#define LAN8814_POWER_MGMT_MODE_12_100BT_EEE_MDIX_TX 0x1c
6074	#define LAN8814_POWER_MGMT_MODE_13_100BT_EEE_MDIX_RX 0x1d
6075	#define LAN8814_POWER_MGMT_MODE_14_100BTX_EEE_TX_RX 0x1e
6076
6077	#define LAN8814_POWER_MGMT_DLLPD_D BIT(0)
6078	#define LAN8814_POWER_MGMT_ADCPD_D BIT(1)
6079	#define LAN8814_POWER_MGMT_PGAPD_D BIT(2)
6080	#define LAN8814_POWER_MGMT_TXPD_D BIT(3)
6081	#define LAN8814_POWER_MGMT_DLLPD_C BIT(4)
6082	#define LAN8814_POWER_MGMT_ADCPD_C BIT(5)
6083	#define LAN8814_POWER_MGMT_PGAPD_C BIT(6)
6084	#define LAN8814_POWER_MGMT_TXPD_C BIT(7)
6085	#define LAN8814_POWER_MGMT_DLLPD_B BIT(8)
6086	#define LAN8814_POWER_MGMT_ADCPD_B BIT(9)
6087	#define LAN8814_POWER_MGMT_PGAPD_B BIT(10)
6088	#define LAN8814_POWER_MGMT_TXPD_B BIT(11)
6089	#define LAN8814_POWER_MGMT_DLLPD_A BIT(12)
6090	#define LAN8814_POWER_MGMT_ADCPD_A BIT(13)
6091	#define LAN8814_POWER_MGMT_PGAPD_A BIT(14)
6092	#define LAN8814_POWER_MGMT_TXPD_A BIT(15)
6093
6094	#define LAN8814_POWER_MGMT_C_D (LAN8814_POWER_MGMT_DLLPD_D | \
6095	LAN8814_POWER_MGMT_ADCPD_D | \
6096	LAN8814_POWER_MGMT_PGAPD_D | \
6097	LAN8814_POWER_MGMT_DLLPD_C | \
6098	LAN8814_POWER_MGMT_ADCPD_C | \
6099	LAN8814_POWER_MGMT_PGAPD_C)
6100
6101	#define LAN8814_POWER_MGMT_B_C_D (LAN8814_POWER_MGMT_C_D | \
6102	LAN8814_POWER_MGMT_DLLPD_B | \
6103	LAN8814_POWER_MGMT_ADCPD_B | \
6104	LAN8814_POWER_MGMT_PGAPD_B)
6105
6106	#define LAN8814_POWER_MGMT_VAL1 (LAN8814_POWER_MGMT_C_D | \
6107	LAN8814_POWER_MGMT_ADCPD_B | \
6108	LAN8814_POWER_MGMT_PGAPD_B | \
6109	LAN8814_POWER_MGMT_ADCPD_A | \
6110	LAN8814_POWER_MGMT_PGAPD_A)
6111
6112	#define LAN8814_POWER_MGMT_VAL2 LAN8814_POWER_MGMT_C_D
6113
6114	#define LAN8814_POWER_MGMT_VAL3 (LAN8814_POWER_MGMT_C_D | \
6115	LAN8814_POWER_MGMT_DLLPD_B | \
6116	LAN8814_POWER_MGMT_ADCPD_B | \
6117	LAN8814_POWER_MGMT_PGAPD_A)
6118
6119	#define LAN8814_POWER_MGMT_VAL4 (LAN8814_POWER_MGMT_B_C_D | \
6120	LAN8814_POWER_MGMT_ADCPD_A | \
6121	LAN8814_POWER_MGMT_PGAPD_A)
6122
6123	#define LAN8814_POWER_MGMT_VAL5 LAN8814_POWER_MGMT_B_C_D
6124
6125	#define LAN8814_EEE_WAKE_TX_TIMER 0x0e
6126	#define LAN8814_EEE_WAKE_TX_TIMER_MAX_VAL 0x1f
6127
6128	static const struct lanphy_reg_data short_center_tap_errata[] = {
6129	{ LAN8814_PAGE_POWER_REGS,
6130	LAN8814_POWER_MGMT_MODE_3_ANEG_MDI,
6131	LAN8814_POWER_MGMT_VAL1 },
6132	{ LAN8814_PAGE_POWER_REGS,
6133	LAN8814_POWER_MGMT_MODE_4_ANEG_MDIX,
6134	LAN8814_POWER_MGMT_VAL1 },
6135	{ LAN8814_PAGE_POWER_REGS,
6136	LAN8814_POWER_MGMT_MODE_5_10BT_MDI,
6137	LAN8814_POWER_MGMT_VAL1 },
6138	{ LAN8814_PAGE_POWER_REGS,
6139	LAN8814_POWER_MGMT_MODE_6_10BT_MDIX,
6140	LAN8814_POWER_MGMT_VAL1 },
6141	{ LAN8814_PAGE_POWER_REGS,
6142	LAN8814_POWER_MGMT_MODE_7_100BT_TRAIN,
6143	LAN8814_POWER_MGMT_VAL2 },
6144	{ LAN8814_PAGE_POWER_REGS,
6145	LAN8814_POWER_MGMT_MODE_8_100BT_MDI,
6146	LAN8814_POWER_MGMT_VAL3 },
6147	{ LAN8814_PAGE_POWER_REGS,
6148	LAN8814_POWER_MGMT_MODE_9_100BT_EEE_MDI_TX,
6149	LAN8814_POWER_MGMT_VAL3 },
6150	{ LAN8814_PAGE_POWER_REGS,
6151	LAN8814_POWER_MGMT_MODE_10_100BT_EEE_MDI_RX,
6152	LAN8814_POWER_MGMT_VAL4 },
6153	{ LAN8814_PAGE_POWER_REGS,
6154	LAN8814_POWER_MGMT_MODE_11_100BT_MDIX,
6155	LAN8814_POWER_MGMT_VAL5 },
6156	{ LAN8814_PAGE_POWER_REGS,
6157	LAN8814_POWER_MGMT_MODE_12_100BT_EEE_MDIX_TX,
6158	LAN8814_POWER_MGMT_VAL5 },
6159	{ LAN8814_PAGE_POWER_REGS,
6160	LAN8814_POWER_MGMT_MODE_13_100BT_EEE_MDIX_RX,
6161	LAN8814_POWER_MGMT_VAL4 },
6162	{ LAN8814_PAGE_POWER_REGS,
6163	LAN8814_POWER_MGMT_MODE_14_100BTX_EEE_TX_RX,
6164	LAN8814_POWER_MGMT_VAL4 },
6165	};
6166
6167	static const struct lanphy_reg_data waketx_timer_errata[] = {
6168	{ LAN8814_PAGE_EEE,
6169	LAN8814_EEE_WAKE_TX_TIMER,
6170	LAN8814_EEE_WAKE_TX_TIMER_MAX_VAL },
6171	};
6172
6173	static int lanphy_write_reg_data(struct phy_device *phydev,
6174	const struct lanphy_reg_data *data,
6175	size_t num)
6176	{
6177	int ret = 0;
6178
6179	while (num--) {
6180	ret = lanphy_write_page_reg(phydev, page: data->page, addr: data->addr,
6181	val: data->val);
6182	if (ret)
6183	break;
6184	}
6185
6186	return ret;
6187	}
6188
6189	static int lan8842_erratas(struct phy_device *phydev)
6190	{
6191	int ret;
6192
6193	ret = lanphy_write_reg_data(phydev, data: short_center_tap_errata,
6194	ARRAY_SIZE(short_center_tap_errata));
6195	if (ret)
6196	return ret;
6197
6198	return lanphy_write_reg_data(phydev, data: waketx_timer_errata,
6199	ARRAY_SIZE(waketx_timer_errata));
6200	}
6201
6202	static int lan8842_config_init(struct phy_device *phydev)
6203	{
6204	int ret;
6205
6206	/* Reset the PHY */
6207	ret = lanphy_modify_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
6208	LAN8814_QSGMII_SOFT_RESET,
6209	LAN8814_QSGMII_SOFT_RESET_BIT,
6210	LAN8814_QSGMII_SOFT_RESET_BIT);
6211	if (ret < 0)
6212	return ret;
6213
6214	/* Apply the erratas for this device */
6215	ret = lan8842_erratas(phydev);
6216	if (ret < 0)
6217	return ret;
6218
6219	/* Even if the GPIOs are set to control the LEDs the behaviour of the
6220	* LEDs is wrong, they are not blinking when there is traffic.
6221	* To fix this it is required to set extended LED mode
6222	*/
6223	ret = lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
6224	LAN8814_LED_CTRL_1,
6225	LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_, set: 0);
6226	if (ret < 0)
6227	return ret;
6228
6229	ret = lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
6230	LAN8814_LED_CTRL_2,
6231	LAN8814_LED_CTRL_2_LED1_COM_DIS,
6232	LAN8814_LED_CTRL_2_LED1_COM_DIS);
6233	if (ret < 0)
6234	return ret;
6235
6236	/* To allow the PHY to control the LEDs the GPIOs of the PHY should have
6237	* a function mode and not the GPIO. Apparently by default the value is
6238	* GPIO and not function even though the datasheet it says that it is
6239	* function. Therefore set this value.
6240	*/
6241	return lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
6242	LAN8814_GPIO_EN2, val: 0);
6243	}
6244
6245	#define LAN8842_INTR_CTRL_REG 52 /* 0x34 */
6246
6247	static int lan8842_config_intr(struct phy_device *phydev)
6248	{
6249	int err;
6250
6251	lanphy_write_page_reg(phydev, LAN8814_PAGE_COMMON_REGS,
6252	LAN8842_INTR_CTRL_REG,
6253	LAN8814_INTR_CTRL_REG_INTR_ENABLE);
6254
6255	/* enable / disable interrupts */
6256	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
6257	err = lan8814_ack_interrupt(phydev);
6258	if (err)
6259	return err;
6260
6261	err = phy_write(phydev, LAN8814_INTC,
6262	LAN8814_INT_LINK | LAN8814_INT_FLF);
6263	} else {
6264	err = phy_write(phydev, LAN8814_INTC, val: 0);
6265	if (err)
6266	return err;
6267
6268	err = lan8814_ack_interrupt(phydev);
6269	}
6270
6271	return err;
6272	}
6273
6274	static unsigned int lan8842_inband_caps(struct phy_device *phydev,
6275	phy_interface_t interface)
6276	{
6277	/* Inband configuration can be enabled or disabled using the registers
6278	* PCS1G_ANEG_CONFIG.
6279	*/
6280	return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
6281	}
6282
6283	static int lan8842_config_inband(struct phy_device *phydev, unsigned int modes)
6284	{
6285	bool enable;
6286
6287	if (modes == LINK_INBAND_DISABLE)
6288	enable = false;
6289	else
6290	enable = true;
6291
6292	/* Disable or enable in-band autoneg with PCS Host side
6293	* It has the same address as lan8814
6294	*/
6295	return lanphy_modify_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
6296	LAN8814_QSGMII_PCS1G_ANEG_CONFIG,
6297	LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA,
6298	set: enable ? LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA : 0);
6299	}
6300
6301	static void lan8842_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
6302	{
6303	struct kszphy_ptp_priv *ptp_priv;
6304	struct lan8842_priv *priv;
6305
6306	priv = phydev->priv;
6307	ptp_priv = &priv->ptp_priv;
6308
6309	if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
6310	lan8814_get_tx_ts(ptp_priv);
6311
6312	if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
6313	lan8814_get_rx_ts(ptp_priv);
6314
6315	if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
6316	lan8814_flush_fifo(phydev, egress: true);
6317	skb_queue_purge(list: &ptp_priv->tx_queue);
6318	}
6319
6320	if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
6321	lan8814_flush_fifo(phydev, egress: false);
6322	skb_queue_purge(list: &ptp_priv->rx_queue);
6323	}
6324	}
6325
6326	static irqreturn_t lan8842_handle_interrupt(struct phy_device *phydev)
6327	{
6328	struct lan8842_priv *priv = phydev->priv;
6329	int ret = IRQ_NONE;
6330	int irq_status;
6331
6332	irq_status = phy_read(phydev, LAN8814_INTS);
6333	if (irq_status < 0) {
6334	phy_error(phydev);
6335	return IRQ_NONE;
6336	}
6337
6338	if (irq_status & (LAN8814_INT_LINK | LAN8814_INT_FLF)) {
6339	phy_trigger_machine(phydev);
6340	ret = IRQ_HANDLED;
6341	}
6342
6343	/* Phy revision lan8832 doesn't have support for PTP therefore there is
6344	* not need to check the PTP and GPIO interrupts
6345	*/
6346	if (priv->rev == LAN8842_REV_8832)
6347	goto out;
6348
6349	while (true) {
6350	irq_status = lanphy_read_page_reg(phydev, LAN8814_PAGE_PORT_REGS,
6351	PTP_TSU_INT_STS);
6352	if (!irq_status)
6353	break;
6354
6355	lan8842_handle_ptp_interrupt(phydev, status: irq_status);
6356	ret = IRQ_HANDLED;
6357	}
6358
6359	if (!lan8814_handle_gpio_interrupt(phydev, status: irq_status))
6360	ret = IRQ_HANDLED;
6361
6362	out:
6363	return ret;
6364	}
6365
6366	static u64 lan8842_get_stat(struct phy_device *phydev, int count, int *regs)
6367	{
6368	u64 ret = 0;
6369	int val;
6370
6371	for (int j = 0; j < count; ++j) {
6372	val = lanphy_read_page_reg(phydev, LAN8814_PAGE_PCS_DIGITAL,
6373	addr: regs[j]);
6374	if (val < 0)
6375	return U64_MAX;
6376
6377	ret <<= 16;
6378	ret += val;
6379	}
6380	return ret;
6381	}
6382
6383	static int lan8842_update_stats(struct phy_device *phydev)
6384	{
6385	struct lan8842_priv *priv = phydev->priv;
6386	int rx_packets_regs[] = {88, 61, 60};
6387	int rx_errors_regs[] = {63, 62};
6388	int tx_packets_regs[] = {89, 85, 84};
6389	int tx_errors_regs[] = {87, 86};
6390
6391	priv->phy_stats.rx_packets = lan8842_get_stat(phydev,
6392	ARRAY_SIZE(rx_packets_regs),
6393	regs: rx_packets_regs);
6394	priv->phy_stats.rx_errors = lan8842_get_stat(phydev,
6395	ARRAY_SIZE(rx_errors_regs),
6396	regs: rx_errors_regs);
6397	priv->phy_stats.tx_packets = lan8842_get_stat(phydev,
6398	ARRAY_SIZE(tx_packets_regs),
6399	regs: tx_packets_regs);
6400	priv->phy_stats.tx_errors = lan8842_get_stat(phydev,
6401	ARRAY_SIZE(tx_errors_regs),
6402	regs: tx_errors_regs);
6403
6404	return 0;
6405	}
6406
6407	#define LAN8842_FLF 15 /* 0x0e */
6408	#define LAN8842_FLF_ENA BIT(1)
6409	#define LAN8842_FLF_ENA_LINK_DOWN BIT(0)
6410
6411	static int lan8842_get_fast_down(struct phy_device *phydev, u8 *msecs)
6412	{
6413	int ret;
6414
6415	ret = lanphy_read_page_reg(phydev, LAN8814_PAGE_PCS, LAN8842_FLF);
6416	if (ret < 0)
6417	return ret;
6418
6419	if (ret & LAN8842_FLF_ENA)
6420	*msecs = ETHTOOL_PHY_FAST_LINK_DOWN_ON;
6421	else
6422	*msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
6423
6424	return 0;
6425	}
6426
6427	static int lan8842_set_fast_down(struct phy_device *phydev, const u8 *msecs)
6428	{
6429	u16 flf;
6430
6431	switch (*msecs) {
6432	case ETHTOOL_PHY_FAST_LINK_DOWN_OFF:
6433	flf = 0;
6434	break;
6435	case ETHTOOL_PHY_FAST_LINK_DOWN_ON:
6436	flf = LAN8842_FLF_ENA | LAN8842_FLF_ENA_LINK_DOWN;
6437	break;
6438	default:
6439	return -EINVAL;
6440	}
6441
6442	return lanphy_modify_page_reg(phydev, LAN8814_PAGE_PCS,
6443	LAN8842_FLF,
6444	LAN8842_FLF_ENA |
6445	LAN8842_FLF_ENA_LINK_DOWN, set: flf);
6446	}
6447
6448	static int lan8842_get_tunable(struct phy_device *phydev,
6449	struct ethtool_tunable *tuna, void *data)
6450	{
6451	switch (tuna->id) {
6452	case ETHTOOL_PHY_FAST_LINK_DOWN:
6453	return lan8842_get_fast_down(phydev, msecs: data);
6454	default:
6455	return -EOPNOTSUPP;
6456	}
6457	}
6458
6459	static int lan8842_set_tunable(struct phy_device *phydev,
6460	struct ethtool_tunable *tuna, const void *data)
6461	{
6462	switch (tuna->id) {
6463	case ETHTOOL_PHY_FAST_LINK_DOWN:
6464	return lan8842_set_fast_down(phydev, msecs: data);
6465	default:
6466	return -EOPNOTSUPP;
6467	}
6468	}
6469
6470	static void lan8842_get_phy_stats(struct phy_device *phydev,
6471	struct ethtool_eth_phy_stats *eth_stats,
6472	struct ethtool_phy_stats *stats)
6473	{
6474	struct lan8842_priv *priv = phydev->priv;
6475
6476	stats->rx_packets = priv->phy_stats.rx_packets;
6477	stats->rx_errors = priv->phy_stats.rx_errors;
6478	stats->tx_packets = priv->phy_stats.tx_packets;
6479	stats->tx_errors = priv->phy_stats.tx_errors;
6480	}
6481
6482	static struct phy_driver ksphy_driver[] = {
6483	{
6484	PHY_ID_MATCH_MODEL(PHY_ID_KS8737),
6485	.name = "Micrel KS8737",
6486	/* PHY_BASIC_FEATURES */
6487	.driver_data = &ks8737_type,
6488	.probe = kszphy_probe,
6489	.config_init = kszphy_config_init,
6490	.config_intr = kszphy_config_intr,
6491	.handle_interrupt = kszphy_handle_interrupt,
6492	.suspend = kszphy_suspend,
6493	.resume = kszphy_resume,
6494	}, {
6495	.phy_id = PHY_ID_KSZ8021,
6496	.phy_id_mask = 0x00ffffff,
6497	.name = "Micrel KSZ8021 or KSZ8031",
6498	/* PHY_BASIC_FEATURES */
6499	.driver_data = &ksz8021_type,
6500	.probe = kszphy_probe,
6501	.config_init = kszphy_config_init,
6502	.config_intr = kszphy_config_intr,
6503	.handle_interrupt = kszphy_handle_interrupt,
6504	.get_sset_count = kszphy_get_sset_count,
6505	.get_strings = kszphy_get_strings,
6506	.get_stats = kszphy_get_stats,
6507	.suspend = kszphy_suspend,
6508	.resume = kszphy_resume,
6509	}, {
6510	.phy_id = PHY_ID_KSZ8031,
6511	.phy_id_mask = 0x00ffffff,
6512	.name = "Micrel KSZ8031",
6513	/* PHY_BASIC_FEATURES */
6514	.driver_data = &ksz8021_type,
6515	.probe = kszphy_probe,
6516	.config_init = kszphy_config_init,
6517	.config_intr = kszphy_config_intr,
6518	.handle_interrupt = kszphy_handle_interrupt,
6519	.get_sset_count = kszphy_get_sset_count,
6520	.get_strings = kszphy_get_strings,
6521	.get_stats = kszphy_get_stats,
6522	.suspend = kszphy_suspend,
6523	.resume = kszphy_resume,
6524	}, {
6525	PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041),
6526	.name = "Micrel KSZ8041",
6527	/* PHY_BASIC_FEATURES */
6528	.driver_data = &ksz8041_type,
6529	.probe = kszphy_probe,
6530	.config_init = ksz8041_config_init,
6531	.config_aneg = ksz8041_config_aneg,
6532	.config_intr = kszphy_config_intr,
6533	.handle_interrupt = kszphy_handle_interrupt,
6534	.get_sset_count = kszphy_get_sset_count,
6535	.get_strings = kszphy_get_strings,
6536	.get_stats = kszphy_get_stats,
6537	.suspend = ksz8041_suspend,
6538	.resume = ksz8041_resume,
6539	}, {
6540	PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041RNLI),
6541	.name = "Micrel KSZ8041RNLI",
6542	/* PHY_BASIC_FEATURES */
6543	.driver_data = &ksz8041_type,
6544	.probe = kszphy_probe,
6545	.config_init = kszphy_config_init,
6546	.config_intr = kszphy_config_intr,
6547	.handle_interrupt = kszphy_handle_interrupt,
6548	.get_sset_count = kszphy_get_sset_count,
6549	.get_strings = kszphy_get_strings,
6550	.get_stats = kszphy_get_stats,
6551	.suspend = kszphy_suspend,
6552	.resume = kszphy_resume,
6553	}, {
6554	.name = "Micrel KSZ8051",
6555	/* PHY_BASIC_FEATURES */
6556	.driver_data = &ksz8051_type,
6557	.probe = kszphy_probe,
6558	.config_init = kszphy_config_init,
6559	.config_intr = kszphy_config_intr,
6560	.handle_interrupt = kszphy_handle_interrupt,
6561	.get_sset_count = kszphy_get_sset_count,
6562	.get_strings = kszphy_get_strings,
6563	.get_stats = kszphy_get_stats,
6564	.match_phy_device = ksz8051_match_phy_device,
6565	.suspend = kszphy_suspend,
6566	.resume = kszphy_resume,
6567	}, {
6568	.phy_id = PHY_ID_KSZ8001,
6569	.name = "Micrel KSZ8001 or KS8721",
6570	.phy_id_mask = 0x00fffffc,
6571	/* PHY_BASIC_FEATURES */
6572	.driver_data = &ksz8041_type,
6573	.probe = kszphy_probe,
6574	.config_init = kszphy_config_init,
6575	.config_intr = kszphy_config_intr,
6576	.handle_interrupt = kszphy_handle_interrupt,
6577	.get_sset_count = kszphy_get_sset_count,
6578	.get_strings = kszphy_get_strings,
6579	.get_stats = kszphy_get_stats,
6580	.suspend = kszphy_suspend,
6581	.resume = kszphy_resume,
6582	}, {
6583	PHY_ID_MATCH_MODEL(PHY_ID_KSZ8081),
6584	.name = "Micrel KSZ8081 or KSZ8091",
6585	.flags = PHY_POLL_CABLE_TEST,
6586	/* PHY_BASIC_FEATURES */
6587	.driver_data = &ksz8081_type,
6588	.probe = kszphy_probe,
6589	.config_init = ksz8081_config_init,
6590	.soft_reset = genphy_soft_reset,
6591	.config_aneg = ksz8081_config_aneg,
6592	.read_status = ksz8081_read_status,
6593	.config_intr = kszphy_config_intr,
6594	.handle_interrupt = kszphy_handle_interrupt,
6595	.get_sset_count = kszphy_get_sset_count,
6596	.get_strings = kszphy_get_strings,
6597	.get_stats = kszphy_get_stats,
6598	.suspend = kszphy_suspend,
6599	.resume = kszphy_resume,
6600	.cable_test_start = ksz886x_cable_test_start,
6601	.cable_test_get_status = ksz886x_cable_test_get_status,
6602	}, {
6603	PHY_ID_MATCH_MODEL(PHY_ID_KSZ8061),
6604	.name = "Micrel KSZ8061",
6605	/* PHY_BASIC_FEATURES */
6606	.probe = kszphy_probe,
6607	.config_init = ksz8061_config_init,
6608	.soft_reset = genphy_soft_reset,
6609	.config_intr = kszphy_config_intr,
6610	.handle_interrupt = kszphy_handle_interrupt,
6611	.suspend = ksz8061_suspend,
6612	.resume = ksz8061_resume,
6613	}, {
6614	.phy_id = PHY_ID_KSZ9021,
6615	.phy_id_mask = 0x000ffffe,
6616	.name = "Micrel KSZ9021 Gigabit PHY",
6617	/* PHY_GBIT_FEATURES */
6618	.driver_data = &ksz9021_type,
6619	.probe = kszphy_probe,
6620	.get_features = ksz9031_get_features,
6621	.config_init = ksz9021_config_init,
6622	.config_intr = kszphy_config_intr,
6623	.handle_interrupt = kszphy_handle_interrupt,
6624	.get_sset_count = kszphy_get_sset_count,
6625	.get_strings = kszphy_get_strings,
6626	.get_stats = kszphy_get_stats,
6627	.suspend = kszphy_suspend,
6628	.resume = kszphy_resume,
6629	.read_mmd = genphy_read_mmd_unsupported,
6630	.write_mmd = genphy_write_mmd_unsupported,
6631	}, {
6632	PHY_ID_MATCH_MODEL(PHY_ID_KSZ9031),
6633	.name = "Micrel KSZ9031 Gigabit PHY",
6634	.flags = PHY_POLL_CABLE_TEST,
6635	.driver_data = &ksz9021_type,
6636	.probe = kszphy_probe,
6637	.get_features = ksz9031_get_features,
6638	.config_init = ksz9031_config_init,
6639	.soft_reset = genphy_soft_reset,
6640	.read_status = ksz9031_read_status,
6641	.config_intr = kszphy_config_intr,
6642	.handle_interrupt = kszphy_handle_interrupt,
6643	.get_sset_count = kszphy_get_sset_count,
6644	.get_strings = kszphy_get_strings,
6645	.get_stats = kszphy_get_stats,
6646	.suspend = kszphy_suspend,
6647	.resume = kszphy_resume,
6648	.cable_test_start = ksz9x31_cable_test_start,
6649	.cable_test_get_status = ksz9x31_cable_test_get_status,
6650	.set_loopback = ksz9031_set_loopback,
6651	}, {
6652	PHY_ID_MATCH_MODEL(PHY_ID_LAN8814),
6653	.name = "Microchip INDY Gigabit Quad PHY",
6654	.flags = PHY_POLL_CABLE_TEST,
6655	.config_init = lan8814_config_init,
6656	.driver_data = &lan8814_type,
6657	.probe = lan8814_probe,
6658	.soft_reset = genphy_soft_reset,
6659	.read_status = ksz9031_read_status,
6660	.get_sset_count = kszphy_get_sset_count,
6661	.get_strings = kszphy_get_strings,
6662	.get_stats = kszphy_get_stats,
6663	.suspend = genphy_suspend,
6664	.resume = kszphy_resume,
6665	.config_intr = lan8814_config_intr,
6666	.inband_caps = lan8842_inband_caps,
6667	.config_inband = lan8842_config_inband,
6668	.handle_interrupt = lan8814_handle_interrupt,
6669	.cable_test_start = lan8814_cable_test_start,
6670	.cable_test_get_status = ksz886x_cable_test_get_status,
6671	}, {
6672	PHY_ID_MATCH_MODEL(PHY_ID_LAN8804),
6673	.name = "Microchip LAN966X Gigabit PHY",
6674	.config_init = lan8804_config_init,
6675	.driver_data = &ksz9021_type,
6676	.probe = kszphy_probe,
6677	.soft_reset = genphy_soft_reset,
6678	.read_status = ksz9031_read_status,
6679	.get_sset_count = kszphy_get_sset_count,
6680	.get_strings = kszphy_get_strings,
6681	.get_stats = kszphy_get_stats,
6682	.suspend = lan8804_suspend,
6683	.resume = lan8804_resume,
6684	.config_intr = lan8804_config_intr,
6685	.handle_interrupt = lan8804_handle_interrupt,
6686	}, {
6687	PHY_ID_MATCH_MODEL(PHY_ID_LAN8841),
6688	.name = "Microchip LAN8841 Gigabit PHY",
6689	.flags = PHY_POLL_CABLE_TEST,
6690	.driver_data = &lan8841_type,
6691	.config_init = lan8841_config_init,
6692	.probe = lan8841_probe,
6693	.soft_reset = genphy_soft_reset,
6694	.config_intr = lan8841_config_intr,
6695	.handle_interrupt = lan8841_handle_interrupt,
6696	.get_sset_count = kszphy_get_sset_count,
6697	.get_strings = kszphy_get_strings,
6698	.get_stats = kszphy_get_stats,
6699	.suspend = lan8841_suspend,
6700	.resume = lan8841_resume,
6701	.cable_test_start = lan8814_cable_test_start,
6702	.cable_test_get_status = ksz886x_cable_test_get_status,
6703	}, {
6704	PHY_ID_MATCH_MODEL(PHY_ID_LAN8842),
6705	.name = "Microchip LAN8842 Gigabit PHY",
6706	.flags = PHY_POLL_CABLE_TEST,
6707	.driver_data = &lan8814_type,
6708	.probe = lan8842_probe,
6709	.config_init = lan8842_config_init,
6710	.config_intr = lan8842_config_intr,
6711	.inband_caps = lan8842_inband_caps,
6712	.config_inband = lan8842_config_inband,
6713	.handle_interrupt = lan8842_handle_interrupt,
6714	.get_phy_stats = lan8842_get_phy_stats,
6715	.update_stats = lan8842_update_stats,
6716	.get_tunable = lan8842_get_tunable,
6717	.set_tunable = lan8842_set_tunable,
6718	.cable_test_start = lan8814_cable_test_start,
6719	.cable_test_get_status = ksz886x_cable_test_get_status,
6720	}, {
6721	PHY_ID_MATCH_MODEL(PHY_ID_KSZ9131),
6722	.name = "Microchip KSZ9131 Gigabit PHY",
6723	/* PHY_GBIT_FEATURES */
6724	.flags = PHY_POLL_CABLE_TEST,
6725	.driver_data = &ksz9131_type,
6726	.probe = kszphy_probe,
6727	.soft_reset = genphy_soft_reset,
6728	.config_init = ksz9131_config_init,
6729	.config_intr = kszphy_config_intr,
6730	.config_aneg = ksz9131_config_aneg,
6731	.read_status = ksz9131_read_status,
6732	.handle_interrupt = kszphy_handle_interrupt,
6733	.get_sset_count = kszphy_get_sset_count,
6734	.get_strings = kszphy_get_strings,
6735	.get_stats = kszphy_get_stats,
6736	.suspend = kszphy_suspend,
6737	.resume = ksz9131_resume,
6738	.cable_test_start = ksz9x31_cable_test_start,
6739	.cable_test_get_status = ksz9x31_cable_test_get_status,
6740	.get_features = ksz9477_get_features,
6741	}, {
6742	PHY_ID_MATCH_MODEL(PHY_ID_KSZ8873MLL),
6743	.name = "Micrel KSZ8873MLL Switch",
6744	/* PHY_BASIC_FEATURES */
6745	.config_init = kszphy_config_init,
6746	.config_aneg = ksz8873mll_config_aneg,
6747	.read_status = ksz8873mll_read_status,
6748	.suspend = genphy_suspend,
6749	.resume = genphy_resume,
6750	}, {
6751	PHY_ID_MATCH_MODEL(PHY_ID_KSZ886X),
6752	.name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
6753	.driver_data = &ksz886x_type,
6754	/* PHY_BASIC_FEATURES */
6755	.flags = PHY_POLL_CABLE_TEST,
6756	.config_init = kszphy_config_init,
6757	.config_aneg = ksz886x_config_aneg,
6758	.read_status = ksz886x_read_status,
6759	.suspend = genphy_suspend,
6760	.resume = genphy_resume,
6761	.cable_test_start = ksz886x_cable_test_start,
6762	.cable_test_get_status = ksz886x_cable_test_get_status,
6763	}, {
6764	.name = "Micrel KSZ87XX Switch",
6765	/* PHY_BASIC_FEATURES */
6766	.config_init = kszphy_config_init,
6767	.match_phy_device = ksz8795_match_phy_device,
6768	.suspend = genphy_suspend,
6769	.resume = genphy_resume,
6770	}, {
6771	PHY_ID_MATCH_MODEL(PHY_ID_KSZ9477),
6772	.name = "Microchip KSZ9477",
6773	.probe = kszphy_probe,
6774	/* PHY_GBIT_FEATURES */
6775	.config_init = ksz9477_config_init,
6776	.config_intr = kszphy_config_intr,
6777	.config_aneg = ksz9477_config_aneg,
6778	.read_status = ksz9477_read_status,
6779	.handle_interrupt = kszphy_handle_interrupt,
6780	.suspend = genphy_suspend,
6781	.resume = ksz9477_resume,
6782	.get_phy_stats = kszphy_get_phy_stats,
6783	.update_stats = kszphy_update_stats,
6784	.cable_test_start = ksz9x31_cable_test_start,
6785	.cable_test_get_status = ksz9x31_cable_test_get_status,
6786	.get_sqi = kszphy_get_sqi,
6787	.get_sqi_max = kszphy_get_sqi_max,
6788	.get_mse_capability = kszphy_get_mse_capability,
6789	.get_mse_snapshot = kszphy_get_mse_snapshot,
6790	} };
6791
6792	module_phy_driver(ksphy_driver);
6793
6794	MODULE_DESCRIPTION("Micrel PHY driver");
6795	MODULE_AUTHOR("David J. Choi");
6796	MODULE_LICENSE("GPL");
6797
6798	static const struct mdio_device_id __maybe_unused micrel_tbl[] = {
6799	{ PHY_ID_KSZ9021, 0x000ffffe },
6800	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ9031) },
6801	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ9131) },
6802	{ PHY_ID_KSZ8001, 0x00fffffc },
6803	{ PHY_ID_MATCH_MODEL(PHY_ID_KS8737) },
6804	{ PHY_ID_KSZ8021, 0x00ffffff },
6805	{ PHY_ID_KSZ8031, 0x00ffffff },
6806	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041) },
6807	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8041RNLI) },
6808	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8051) },
6809	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8061) },
6810	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8081) },
6811	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ8873MLL) },
6812	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ886X) },
6813	{ PHY_ID_MATCH_MODEL(PHY_ID_KSZ9477) },
6814	{ PHY_ID_MATCH_MODEL(PHY_ID_LAN8814) },
6815	{ PHY_ID_MATCH_MODEL(PHY_ID_LAN8804) },
6816	{ PHY_ID_MATCH_MODEL(PHY_ID_LAN8841) },
6817	{ PHY_ID_MATCH_MODEL(PHY_ID_LAN8842) },
6818	{ }
6819	};
6820
6821	MODULE_DEVICE_TABLE(mdio, micrel_tbl);
6822