1	// SPDX-License-Identifier: GPL-2.0+
2	/*
3	* drivers/net/phy/micrel.c
4	*
5	* Driver for Micrel PHYs
6	*
7	* Author: David J. Choi
8	*
9	* Copyright (c) 2010-2013 Micrel, Inc.
10	* Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11	*
12	* Support : Micrel Phys:
13	* Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15	* ksz8021, ksz8031, ksz8051,
16	* ksz8081, ksz8091,
17	* ksz8061,
18	* Switch : ksz8873, ksz886x
19	* ksz9477, lan8804
20	*/
21
22	#include <linux/bitfield.h>
23	#include <linux/ethtool_netlink.h>
24	#include <linux/kernel.h>
25	#include <linux/module.h>
26	#include <linux/phy.h>
27	#include <linux/micrel_phy.h>
28	#include <linux/of.h>
29	#include <linux/clk.h>
30	#include <linux/delay.h>
31	#include <linux/ptp_clock_kernel.h>
32	#include <linux/ptp_clock.h>
33	#include <linux/ptp_classify.h>
34	#include <linux/net_tstamp.h>
35	#include <linux/gpio/consumer.h>
36
37	#include "phylib.h"
38
39	/* Operation Mode Strap Override */
40	#define MII_KSZPHY_OMSO 0x16
41	#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
42	#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
43	#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
44	#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
45	#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
46
47	/* general Interrupt control/status reg in vendor specific block. */
48	#define MII_KSZPHY_INTCS 0x1B
49	#define KSZPHY_INTCS_JABBER BIT(15)
50	#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
51	#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
52	#define KSZPHY_INTCS_PARELLEL BIT(12)
53	#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
54	#define KSZPHY_INTCS_LINK_DOWN BIT(10)
55	#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
56	#define KSZPHY_INTCS_LINK_UP BIT(8)
57	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
58	KSZPHY_INTCS_LINK_DOWN)
59	#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
60	#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
61	#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
62	KSZPHY_INTCS_LINK_UP_STATUS)
63
64	/* LinkMD Control/Status */
65	#define KSZ8081_LMD 0x1d
66	#define KSZ8081_LMD_ENABLE_TEST BIT(15)
67	#define KSZ8081_LMD_STAT_NORMAL 0
68	#define KSZ8081_LMD_STAT_OPEN 1
69	#define KSZ8081_LMD_STAT_SHORT 2
70	#define KSZ8081_LMD_STAT_FAIL 3
71	#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
72	/* Short cable (<10 meter) has been detected by LinkMD */
73	#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
74	#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
75
76	#define KSZ9x31_LMD 0x12
77	#define KSZ9x31_LMD_VCT_EN BIT(15)
78	#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
79	#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
80	#define KSZ9x31_LMD_VCT_SEL_RESULT 0
81	#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
82	#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
83	#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
84	#define KSZ9x31_LMD_VCT_ST_NORMAL 0
85	#define KSZ9x31_LMD_VCT_ST_OPEN 1
86	#define KSZ9x31_LMD_VCT_ST_SHORT 2
87	#define KSZ9x31_LMD_VCT_ST_FAIL 3
88	#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
89	#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
90	#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
91	#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
92	#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
93	#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
94	#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
95	#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
96
97	#define KSZPHY_WIRE_PAIR_MASK 0x3
98
99	#define LAN8814_CABLE_DIAG 0x12
100	#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
101	#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
102	#define LAN8814_PAIR_BIT_SHIFT 12
103
104	#define LAN8814_WIRE_PAIR_MASK 0xF
105
106	/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
107	#define LAN8814_INTC 0x18
108	#define LAN8814_INTS 0x1B
109
110	#define LAN8814_INT_LINK_DOWN BIT(2)
111	#define LAN8814_INT_LINK_UP BIT(0)
112	#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
113	LAN8814_INT_LINK_DOWN)
114
115	#define LAN8814_INTR_CTRL_REG 0x34
116	#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
117	#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
118
119	#define LAN8814_EEE_STATE 0x38
120	#define LAN8814_EEE_STATE_MASK2P5P BIT(10)
121
122	#define LAN8814_PD_CONTROLS 0x9d
123	#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)
124	#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb
125
126	/* Represents 1ppm adjustment in 2^32 format with
127	* each nsec contains 4 clock cycles.
128	* The value is calculated as following: (1/1000000)/((2^-32)/4)
129	*/
130	#define LAN8814_1PPM_FORMAT 17179
131
132	/* Represents 1ppm adjustment in 2^32 format with
133	* each nsec contains 8 clock cycles.
134	* The value is calculated as following: (1/1000000)/((2^-32)/8)
135	*/
136	#define LAN8841_1PPM_FORMAT 34360
137
138	#define PTP_RX_VERSION 0x0248
139	#define PTP_TX_VERSION 0x0288
140	#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
141	#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
142
143	#define PTP_RX_MOD 0x024F
144	#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
145	#define PTP_RX_TIMESTAMP_EN 0x024D
146	#define PTP_TX_TIMESTAMP_EN 0x028D
147
148	#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
149	#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
150	#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
151	#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
152
153	#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
154	#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
155
156	#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
157	#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
158	#define LTC_HARD_RESET 0x023F
159	#define LTC_HARD_RESET_ BIT(0)
160
161	#define TSU_HARD_RESET 0x02C1
162	#define TSU_HARD_RESET_ BIT(0)
163
164	#define PTP_CMD_CTL 0x0200
165	#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
166	#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
167	#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
168	#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
169	#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
170	#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
171
172	#define PTP_COMMON_INT_ENA 0x0204
173	#define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2)
174
175	#define PTP_CLOCK_SET_SEC_HI 0x0205
176	#define PTP_CLOCK_SET_SEC_MID 0x0206
177	#define PTP_CLOCK_SET_SEC_LO 0x0207
178	#define PTP_CLOCK_SET_NS_HI 0x0208
179	#define PTP_CLOCK_SET_NS_LO 0x0209
180
181	#define PTP_CLOCK_READ_SEC_HI 0x0229
182	#define PTP_CLOCK_READ_SEC_MID 0x022A
183	#define PTP_CLOCK_READ_SEC_LO 0x022B
184	#define PTP_CLOCK_READ_NS_HI 0x022C
185	#define PTP_CLOCK_READ_NS_LO 0x022D
186
187	#define PTP_GPIO_SEL 0x0230
188	#define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8)
189	#define PTP_GPIO_CAP_MAP_LO 0x0232
190
191	#define PTP_GPIO_CAP_EN 0x0233
192	#define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio)
193	#define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
194
195	#define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235
196	#define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236
197	#define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237
198	#define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238
199	#define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239
200	#define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A
201	#define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B
202	#define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C
203
204	#define PTP_GPIO_CAP_STS 0x023D
205	#define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio)
206	#define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8)
207
208	#define PTP_OPERATING_MODE 0x0241
209	#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
210
211	#define PTP_TX_MOD 0x028F
212	#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
213	#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
214
215	#define PTP_RX_PARSE_CONFIG 0x0242
216	#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
217	#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
218	#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
219
220	#define PTP_TX_PARSE_CONFIG 0x0282
221	#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
222	#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
223	#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
224
225	#define PTP_CLOCK_RATE_ADJ_HI 0x020C
226	#define PTP_CLOCK_RATE_ADJ_LO 0x020D
227	#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
228
229	#define PTP_LTC_STEP_ADJ_HI 0x0212
230	#define PTP_LTC_STEP_ADJ_LO 0x0213
231	#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
232
233	#define LAN8814_INTR_STS_REG 0x0033
234	#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
235	#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
236	#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
237	#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
238
239	#define PTP_CAP_INFO 0x022A
240	#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
241	#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
242
243	#define PTP_TX_EGRESS_SEC_HI 0x0296
244	#define PTP_TX_EGRESS_SEC_LO 0x0297
245	#define PTP_TX_EGRESS_NS_HI 0x0294
246	#define PTP_TX_EGRESS_NS_LO 0x0295
247	#define PTP_TX_MSG_HEADER2 0x0299
248
249	#define PTP_RX_INGRESS_SEC_HI 0x0256
250	#define PTP_RX_INGRESS_SEC_LO 0x0257
251	#define PTP_RX_INGRESS_NS_HI 0x0254
252	#define PTP_RX_INGRESS_NS_LO 0x0255
253	#define PTP_RX_MSG_HEADER2 0x0259
254
255	#define PTP_TSU_INT_EN 0x0200
256	#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
257	#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
258	#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
259	#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
260
261	#define PTP_TSU_INT_STS 0x0201
262	#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
263	#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
264	#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
265	#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
266
267	#define LAN8814_LED_CTRL_1 0x0
268	#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
269
270	/* PHY Control 1 */
271	#define MII_KSZPHY_CTRL_1 0x1e
272	#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
273
274	/* PHY Control 2 / PHY Control (if no PHY Control 1) */
275	#define MII_KSZPHY_CTRL_2 0x1f
276	#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
277	/* bitmap of PHY register to set interrupt mode */
278	#define KSZ8081_CTRL2_HP_MDIX BIT(15)
279	#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
280	#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
281	#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
282	#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
283	#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
284	#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
285
286	/* Write/read to/from extended registers */
287	#define MII_KSZPHY_EXTREG 0x0b
288	#define KSZPHY_EXTREG_WRITE 0x8000
289
290	#define MII_KSZPHY_EXTREG_WRITE 0x0c
291	#define MII_KSZPHY_EXTREG_READ 0x0d
292
293	/* Extended registers */
294	#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
295	#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
296	#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
297
298	#define PS_TO_REG 200
299	#define FIFO_SIZE 8
300
301	#define LAN8814_PTP_GPIO_NUM 24
302	#define LAN8814_PTP_PEROUT_NUM 2
303	#define LAN8814_PTP_EXTTS_NUM 3
304
305	#define LAN8814_BUFFER_TIME 2
306
307	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
308	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
309	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
310	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
311	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
312	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
313	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
314	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
315	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
316	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
317	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
318	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
319	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
320	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
321
322	#define LAN8814_GPIO_EN1 0x20
323	#define LAN8814_GPIO_EN2 0x21
324	#define LAN8814_GPIO_DIR1 0x22
325	#define LAN8814_GPIO_DIR2 0x23
326	#define LAN8814_GPIO_BUF1 0x24
327	#define LAN8814_GPIO_BUF2 0x25
328
329	#define LAN8814_GPIO_EN_ADDR(pin) \
330	((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
331	#define LAN8814_GPIO_EN_BIT(pin) BIT(pin)
332	#define LAN8814_GPIO_DIR_ADDR(pin) \
333	((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
334	#define LAN8814_GPIO_DIR_BIT(pin) BIT(pin)
335	#define LAN8814_GPIO_BUF_ADDR(pin) \
336	((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)
337	#define LAN8814_GPIO_BUF_BIT(pin) BIT(pin)
338
339	#define LAN8814_EVENT_A 0
340	#define LAN8814_EVENT_B 1
341
342	#define LAN8814_PTP_GENERAL_CONFIG 0x0201
343	#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \
344	((event) ? GENMASK(11, 8) : GENMASK(7, 4))
345	#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \
346	(((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))
347	#define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \
348	((event) ? BIT(2) : BIT(0))
349	#define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \
350	((event) ? BIT(3) : BIT(1))
351
352	#define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215)
353	#define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216)
354	#define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217)
355	#define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218)
356
357	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219)
358	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A)
359	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B)
360	#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C)
361
362	/* Delay used to get the second part from the LTC */
363	#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
364
365	struct kszphy_hw_stat {
366	const char *string;
367	u8 reg;
368	u8 bits;
369	};
370
371	static struct kszphy_hw_stat kszphy_hw_stats[] = {
372	{ "phy_receive_errors", 21, 16},
373	{ "phy_idle_errors", 10, 8 },
374	};
375
376	struct kszphy_type {
377	u32 led_mode_reg;
378	u16 interrupt_level_mask;
379	u16 cable_diag_reg;
380	unsigned long pair_mask;
381	u16 disable_dll_tx_bit;
382	u16 disable_dll_rx_bit;
383	u16 disable_dll_mask;
384	bool has_broadcast_disable;
385	bool has_nand_tree_disable;
386	bool has_rmii_ref_clk_sel;
387	};
388
389	/* Shared structure between the PHYs of the same package. */
390	struct lan8814_shared_priv {
391	struct phy_device *phydev;
392	struct ptp_clock *ptp_clock;
393	struct ptp_clock_info ptp_clock_info;
394	struct ptp_pin_desc *pin_config;
395
396	/* Lock for ptp_clock */
397	struct mutex shared_lock;
398	};
399
400	struct lan8814_ptp_rx_ts {
401	struct list_head list;
402	u32 seconds;
403	u32 nsec;
404	u16 seq_id;
405	};
406
407	struct kszphy_ptp_priv {
408	struct mii_timestamper mii_ts;
409	struct phy_device *phydev;
410
411	struct sk_buff_head tx_queue;
412	struct sk_buff_head rx_queue;
413
414	struct list_head rx_ts_list;
415	/* Lock for Rx ts fifo */
416	spinlock_t rx_ts_lock;
417
418	int hwts_tx_type;
419	enum hwtstamp_rx_filters rx_filter;
420	int layer;
421	int version;
422
423	struct ptp_clock *ptp_clock;
424	struct ptp_clock_info ptp_clock_info;
425	/* Lock for ptp_clock */
426	struct mutex ptp_lock;
427	struct ptp_pin_desc *pin_config;
428
429	s64 seconds;
430	/* Lock for accessing seconds */
431	spinlock_t seconds_lock;
432	};
433
434	struct kszphy_priv {
435	struct kszphy_ptp_priv ptp_priv;
436	const struct kszphy_type *type;
437	struct clk *clk;
438	int led_mode;
439	u16 vct_ctrl1000;
440	bool rmii_ref_clk_sel;
441	bool rmii_ref_clk_sel_val;
442	bool clk_enable;
443	u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
444	};
445
446	static const struct kszphy_type lan8814_type = {
447	.led_mode_reg = ~LAN8814_LED_CTRL_1,
448	.cable_diag_reg = LAN8814_CABLE_DIAG,
449	.pair_mask = LAN8814_WIRE_PAIR_MASK,
450	};
451
452	static const struct kszphy_type ksz886x_type = {
453	.cable_diag_reg = KSZ8081_LMD,
454	.pair_mask = KSZPHY_WIRE_PAIR_MASK,
455	};
456
457	static const struct kszphy_type ksz8021_type = {
458	.led_mode_reg = MII_KSZPHY_CTRL_2,
459	.has_broadcast_disable = true,
460	.has_nand_tree_disable = true,
461	.has_rmii_ref_clk_sel = true,
462	};
463
464	static const struct kszphy_type ksz8041_type = {
465	.led_mode_reg = MII_KSZPHY_CTRL_1,
466	};
467
468	static const struct kszphy_type ksz8051_type = {
469	.led_mode_reg = MII_KSZPHY_CTRL_2,
470	.has_nand_tree_disable = true,
471	};
472
473	static const struct kszphy_type ksz8081_type = {
474	.led_mode_reg = MII_KSZPHY_CTRL_2,
475	.has_broadcast_disable = true,
476	.has_nand_tree_disable = true,
477	.has_rmii_ref_clk_sel = true,
478	};
479
480	static const struct kszphy_type ks8737_type = {
481	.interrupt_level_mask = BIT(14),
482	};
483
484	static const struct kszphy_type ksz9021_type = {
485	.interrupt_level_mask = BIT(14),
486	};
487
488	static const struct kszphy_type ksz9131_type = {
489	.interrupt_level_mask = BIT(14),
490	.disable_dll_tx_bit = BIT(12),
491	.disable_dll_rx_bit = BIT(12),
492	.disable_dll_mask = BIT_MASK(12),
493	};
494
495	static const struct kszphy_type lan8841_type = {
496	.disable_dll_tx_bit = BIT(14),
497	.disable_dll_rx_bit = BIT(14),
498	.disable_dll_mask = BIT_MASK(14),
499	.cable_diag_reg = LAN8814_CABLE_DIAG,
500	.pair_mask = LAN8814_WIRE_PAIR_MASK,
501	};
502
503	static int kszphy_extended_write(struct phy_device *phydev,
504	u32 regnum, u16 val)
505	{
506	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
507	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
508	}
509
510	static int kszphy_extended_read(struct phy_device *phydev,
511	u32 regnum)
512	{
513	phy_write(phydev, MII_KSZPHY_EXTREG, val: regnum);
514	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
515	}
516
517	static int kszphy_ack_interrupt(struct phy_device *phydev)
518	{
519	/* bit[7..0] int status, which is a read and clear register. */
520	int rc;
521
522	rc = phy_read(phydev, MII_KSZPHY_INTCS);
523
524	return (rc < 0) ? rc : 0;
525	}
526
527	static int kszphy_config_intr(struct phy_device *phydev)
528	{
529	const struct kszphy_type *type = phydev->drv->driver_data;
530	int temp, err;
531	u16 mask;
532
533	if (type && type->interrupt_level_mask)
534	mask = type->interrupt_level_mask;
535	else
536	mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
537
538	/* set the interrupt pin active low */
539	temp = phy_read(phydev, MII_KSZPHY_CTRL);
540	if (temp < 0)
541	return temp;
542	temp &= ~mask;
543	phy_write(phydev, MII_KSZPHY_CTRL, val: temp);
544
545	/* enable / disable interrupts */
546	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
547	err = kszphy_ack_interrupt(phydev);
548	if (err)
549	return err;
550
551	err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
552	} else {
553	err = phy_write(phydev, MII_KSZPHY_INTCS, val: 0);
554	if (err)
555	return err;
556
557	err = kszphy_ack_interrupt(phydev);
558	}
559
560	return err;
561	}
562
563	static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
564	{
565	int irq_status;
566
567	irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
568	if (irq_status < 0) {
569	phy_error(phydev);
570	return IRQ_NONE;
571	}
572
573	if (!(irq_status & KSZPHY_INTCS_STATUS))
574	return IRQ_NONE;
575
576	phy_trigger_machine(phydev);
577
578	return IRQ_HANDLED;
579	}
580
581	static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
582	{
583	int ctrl;
584
585	ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
586	if (ctrl < 0)
587	return ctrl;
588
589	if (val)
590	ctrl |= KSZPHY_RMII_REF_CLK_SEL;
591	else
592	ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
593
594	return phy_write(phydev, MII_KSZPHY_CTRL, val: ctrl);
595	}
596
597	static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
598	{
599	int rc, temp, shift;
600
601	switch (reg) {
602	case MII_KSZPHY_CTRL_1:
603	shift = 14;
604	break;
605	case MII_KSZPHY_CTRL_2:
606	shift = 4;
607	break;
608	default:
609	return -EINVAL;
610	}
611
612	temp = phy_read(phydev, regnum: reg);
613	if (temp < 0) {
614	rc = temp;
615	goto out;
616	}
617
618	temp &= ~(3 << shift);
619	temp |= val << shift;
620	rc = phy_write(phydev, regnum: reg, val: temp);
621	out:
622	if (rc < 0)
623	phydev_err(phydev, "failed to set led mode\n");
624
625	return rc;
626	}
627
628	/* Disable PHY address 0 as the broadcast address, so that it can be used as a
629	* unique (non-broadcast) address on a shared bus.
630	*/
631	static int kszphy_broadcast_disable(struct phy_device *phydev)
632	{
633	int ret;
634
635	ret = phy_read(phydev, MII_KSZPHY_OMSO);
636	if (ret < 0)
637	goto out;
638
639	ret = phy_write(phydev, MII_KSZPHY_OMSO, val: ret | KSZPHY_OMSO_B_CAST_OFF);
640	out:
641	if (ret)
642	phydev_err(phydev, "failed to disable broadcast address\n");
643
644	return ret;
645	}
646
647	static int kszphy_nand_tree_disable(struct phy_device *phydev)
648	{
649	int ret;
650
651	ret = phy_read(phydev, MII_KSZPHY_OMSO);
652	if (ret < 0)
653	goto out;
654
655	if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
656	return 0;
657
658	ret = phy_write(phydev, MII_KSZPHY_OMSO,
659	val: ret & ~KSZPHY_OMSO_NAND_TREE_ON);
660	out:
661	if (ret)
662	phydev_err(phydev, "failed to disable NAND tree mode\n");
663
664	return ret;
665	}
666
667	/* Some config bits need to be set again on resume, handle them here. */
668	static int kszphy_config_reset(struct phy_device *phydev)
669	{
670	struct kszphy_priv *priv = phydev->priv;
671	int ret;
672
673	if (priv->rmii_ref_clk_sel) {
674	ret = kszphy_rmii_clk_sel(phydev, val: priv->rmii_ref_clk_sel_val);
675	if (ret) {
676	phydev_err(phydev,
677	"failed to set rmii reference clock\n");
678	return ret;
679	}
680	}
681
682	if (priv->type && priv->led_mode >= 0)
683	kszphy_setup_led(phydev, reg: priv->type->led_mode_reg, val: priv->led_mode);
684
685	return 0;
686	}
687
688	static int kszphy_config_init(struct phy_device *phydev)
689	{
690	struct kszphy_priv *priv = phydev->priv;
691	const struct kszphy_type *type;
692
693	if (!priv)
694	return 0;
695
696	type = priv->type;
697
698	if (type && type->has_broadcast_disable)
699	kszphy_broadcast_disable(phydev);
700
701	if (type && type->has_nand_tree_disable)
702	kszphy_nand_tree_disable(phydev);
703
704	return kszphy_config_reset(phydev);
705	}
706
707	static int ksz8041_fiber_mode(struct phy_device *phydev)
708	{
709	struct device_node *of_node = phydev->mdio.dev.of_node;
710
711	return of_property_read_bool(np: of_node, propname: "micrel,fiber-mode");
712	}
713
714	static int ksz8041_config_init(struct phy_device *phydev)
715	{
716	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
717
718	/* Limit supported and advertised modes in fiber mode */
719	if (ksz8041_fiber_mode(phydev)) {
720	phydev->dev_flags |= MICREL_PHY_FXEN;
721	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
722	linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
723
724	linkmode_and(dst: phydev->supported, a: phydev->supported, b: mask);
725	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
726	phydev->supported);
727	linkmode_and(dst: phydev->advertising, a: phydev->advertising, b: mask);
728	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
729	phydev->advertising);
730	phydev->autoneg = AUTONEG_DISABLE;
731	}
732
733	return kszphy_config_init(phydev);
734	}
735
736	static int ksz8041_config_aneg(struct phy_device *phydev)
737	{
738	/* Skip auto-negotiation in fiber mode */
739	if (phydev->dev_flags & MICREL_PHY_FXEN) {
740	phydev->speed = SPEED_100;
741	return 0;
742	}
743
744	return genphy_config_aneg(phydev);
745	}
746
747	static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
748	const bool ksz_8051)
749	{
750	int ret;
751
752	if (!phy_id_compare(id1: phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
753	return 0;
754
755	ret = phy_read(phydev, MII_BMSR);
756	if (ret < 0)
757	return ret;
758
759	/* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
760	* exact PHY ID. However, they can be told apart by the extended
761	* capability registers presence. The KSZ8051 PHY has them while
762	* the switch does not.
763	*/
764	ret &= BMSR_ERCAP;
765	if (ksz_8051)
766	return ret;
767	else
768	return !ret;
769	}
770
771	static int ksz8051_match_phy_device(struct phy_device *phydev,
772	const struct phy_driver *phydrv)
773	{
774	return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: true);
775	}
776
777	static int ksz8081_config_init(struct phy_device *phydev)
778	{
779	/* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
780	* based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
781	* pull-down is missing, the factory test mode should be cleared by
782	* manually writing a 0.
783	*/
784	phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
785
786	return kszphy_config_init(phydev);
787	}
788
789	static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
790	{
791	u16 val;
792
793	switch (ctrl) {
794	case ETH_TP_MDI:
795	val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
796	break;
797	case ETH_TP_MDI_X:
798	val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
799	KSZ8081_CTRL2_MDI_MDI_X_SELECT;
800	break;
801	case ETH_TP_MDI_AUTO:
802	val = 0;
803	break;
804	default:
805	return 0;
806	}
807
808	return phy_modify(phydev, MII_KSZPHY_CTRL_2,
809	KSZ8081_CTRL2_HP_MDIX |
810	KSZ8081_CTRL2_MDI_MDI_X_SELECT |
811	KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
812	KSZ8081_CTRL2_HP_MDIX | val);
813	}
814
815	static int ksz8081_config_aneg(struct phy_device *phydev)
816	{
817	int ret;
818
819	ret = genphy_config_aneg(phydev);
820	if (ret)
821	return ret;
822
823	/* The MDI-X configuration is automatically changed by the PHY after
824	* switching from autoneg off to on. So, take MDI-X configuration under
825	* own control and set it after autoneg configuration was done.
826	*/
827	return ksz8081_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
828	}
829
830	static int ksz8081_mdix_update(struct phy_device *phydev)
831	{
832	int ret;
833
834	ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
835	if (ret < 0)
836	return ret;
837
838	if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
839	if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
840	phydev->mdix_ctrl = ETH_TP_MDI_X;
841	else
842	phydev->mdix_ctrl = ETH_TP_MDI;
843	} else {
844	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
845	}
846
847	ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
848	if (ret < 0)
849	return ret;
850
851	if (ret & KSZ8081_CTRL1_MDIX_STAT)
852	phydev->mdix = ETH_TP_MDI;
853	else
854	phydev->mdix = ETH_TP_MDI_X;
855
856	return 0;
857	}
858
859	static int ksz8081_read_status(struct phy_device *phydev)
860	{
861	int ret;
862
863	ret = ksz8081_mdix_update(phydev);
864	if (ret < 0)
865	return ret;
866
867	return genphy_read_status(phydev);
868	}
869
870	static int ksz8061_config_init(struct phy_device *phydev)
871	{
872	int ret;
873
874	/* Chip can be powered down by the bootstrap code. */
875	ret = phy_read(phydev, MII_BMCR);
876	if (ret < 0)
877	return ret;
878	if (ret & BMCR_PDOWN) {
879	ret = phy_write(phydev, MII_BMCR, val: ret & ~BMCR_PDOWN);
880	if (ret < 0)
881	return ret;
882	usleep_range(min: 1000, max: 2000);
883	}
884
885	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, val: 0xB61A);
886	if (ret)
887	return ret;
888
889	return kszphy_config_init(phydev);
890	}
891
892	static int ksz8795_match_phy_device(struct phy_device *phydev,
893	const struct phy_driver *phydrv)
894	{
895	return ksz8051_ksz8795_match_phy_device(phydev, ksz_8051: false);
896	}
897
898	static int ksz9021_load_values_from_of(struct phy_device *phydev,
899	const struct device_node *of_node,
900	u16 reg,
901	const char *field1, const char *field2,
902	const char *field3, const char *field4)
903	{
904	int val1 = -1;
905	int val2 = -2;
906	int val3 = -3;
907	int val4 = -4;
908	int newval;
909	int matches = 0;
910
911	if (!of_property_read_u32(np: of_node, propname: field1, out_value: &val1))
912	matches++;
913
914	if (!of_property_read_u32(np: of_node, propname: field2, out_value: &val2))
915	matches++;
916
917	if (!of_property_read_u32(np: of_node, propname: field3, out_value: &val3))
918	matches++;
919
920	if (!of_property_read_u32(np: of_node, propname: field4, out_value: &val4))
921	matches++;
922
923	if (!matches)
924	return 0;
925
926	if (matches < 4)
927	newval = kszphy_extended_read(phydev, regnum: reg);
928	else
929	newval = 0;
930
931	if (val1 != -1)
932	newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
933
934	if (val2 != -2)
935	newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
936
937	if (val3 != -3)
938	newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
939
940	if (val4 != -4)
941	newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
942
943	return kszphy_extended_write(phydev, regnum: reg, val: newval);
944	}
945
946	static int ksz9021_config_init(struct phy_device *phydev)
947	{
948	const struct device_node *of_node;
949	const struct device *dev_walker;
950
951	/* The Micrel driver has a deprecated option to place phy OF
952	* properties in the MAC node. Walk up the tree of devices to
953	* find a device with an OF node.
954	*/
955	dev_walker = &phydev->mdio.dev;
956	do {
957	of_node = dev_walker->of_node;
958	dev_walker = dev_walker->parent;
959
960	} while (!of_node && dev_walker);
961
962	if (of_node) {
963	ksz9021_load_values_from_of(phydev, of_node,
964	MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
965	field1: "txen-skew-ps", field2: "txc-skew-ps",
966	field3: "rxdv-skew-ps", field4: "rxc-skew-ps");
967	ksz9021_load_values_from_of(phydev, of_node,
968	MII_KSZPHY_RX_DATA_PAD_SKEW,
969	field1: "rxd0-skew-ps", field2: "rxd1-skew-ps",
970	field3: "rxd2-skew-ps", field4: "rxd3-skew-ps");
971	ksz9021_load_values_from_of(phydev, of_node,
972	MII_KSZPHY_TX_DATA_PAD_SKEW,
973	field1: "txd0-skew-ps", field2: "txd1-skew-ps",
974	field3: "txd2-skew-ps", field4: "txd3-skew-ps");
975	}
976	return 0;
977	}
978
979	#define KSZ9031_PS_TO_REG 60
980
981	/* Extended registers */
982	/* MMD Address 0x0 */
983	#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
984	#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
985
986	/* MMD Address 0x2 */
987	#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
988	#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
989	#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
990
991	#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
992	#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
993	#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
994	#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
995	#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
996
997	#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
998	#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
999	#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
1000	#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
1001	#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
1002
1003	#define MII_KSZ9031RN_CLK_PAD_SKEW 8
1004	#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
1005	#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
1006
1007	/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
1008	* provide different RGMII options we need to configure delay offset
1009	* for each pad relative to build in delay.
1010	*/
1011	/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
1012	* 1.80ns
1013	*/
1014	#define RX_ID 0x7
1015	#define RX_CLK_ID 0x19
1016
1017	/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
1018	* internal 1.2ns delay.
1019	*/
1020	#define RX_ND 0xc
1021	#define RX_CLK_ND 0x0
1022
1023	/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
1024	#define TX_ID 0x0
1025	#define TX_CLK_ID 0x1f
1026
1027	/* set tx and tx_clk to "No delay adjustment" to keep 0ns
1028	* dealy
1029	*/
1030	#define TX_ND 0x7
1031	#define TX_CLK_ND 0xf
1032
1033	/* MMD Address 0x1C */
1034	#define MII_KSZ9031RN_EDPD 0x23
1035	#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
1036
1037	static int ksz9031_set_loopback(struct phy_device *phydev, bool enable,
1038	int speed)
1039	{
1040	u16 ctl = BMCR_LOOPBACK;
1041	int val;
1042
1043	if (!enable)
1044	return genphy_loopback(phydev, enable, speed: 0);
1045
1046	if (speed == SPEED_10 || speed == SPEED_100 || speed == SPEED_1000)
1047	phydev->speed = speed;
1048	else if (speed)
1049	return -EINVAL;
1050	phydev->duplex = DUPLEX_FULL;
1051
1052	ctl |= mii_bmcr_encode_fixed(speed: phydev->speed, duplex: phydev->duplex);
1053
1054	phy_write(phydev, MII_BMCR, val: ctl);
1055
1056	return phy_read_poll_timeout(phydev, MII_BMSR, val, val & BMSR_LSTATUS,
1057	5000, 500000, true);
1058	}
1059
1060	static int ksz9031_of_load_skew_values(struct phy_device *phydev,
1061	const struct device_node *of_node,
1062	u16 reg, size_t field_sz,
1063	const char *field[], u8 numfields,
1064	bool *update)
1065	{
1066	int val[4] = {-1, -2, -3, -4};
1067	int matches = 0;
1068	u16 mask;
1069	u16 maxval;
1070	u16 newval;
1071	int i;
1072
1073	for (i = 0; i < numfields; i++)
1074	if (!of_property_read_u32(np: of_node, propname: field[i], out_value: val + i))
1075	matches++;
1076
1077	if (!matches)
1078	return 0;
1079
1080	*update |= true;
1081
1082	if (matches < numfields)
1083	newval = phy_read_mmd(phydev, devad: 2, regnum: reg);
1084	else
1085	newval = 0;
1086
1087	maxval = (field_sz == 4) ? 0xf : 0x1f;
1088	for (i = 0; i < numfields; i++)
1089	if (val[i] != -(i + 1)) {
1090	mask = 0xffff;
1091	mask ^= maxval << (field_sz * i);
1092	newval = (newval & mask) |
1093	(((val[i] / KSZ9031_PS_TO_REG) & maxval)
1094	<< (field_sz * i));
1095	}
1096
1097	return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval);
1098	}
1099
1100	/* Center KSZ9031RNX FLP timing at 16ms. */
1101	static int ksz9031_center_flp_timing(struct phy_device *phydev)
1102	{
1103	int result;
1104
1105	result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
1106	val: 0x0006);
1107	if (result)
1108	return result;
1109
1110	result = phy_write_mmd(phydev, devad: 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
1111	val: 0x1A80);
1112	if (result)
1113	return result;
1114
1115	return genphy_restart_aneg(phydev);
1116	}
1117
1118	/* Enable energy-detect power-down mode */
1119	static int ksz9031_enable_edpd(struct phy_device *phydev)
1120	{
1121	int reg;
1122
1123	reg = phy_read_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD);
1124	if (reg < 0)
1125	return reg;
1126	return phy_write_mmd(phydev, devad: 0x1C, MII_KSZ9031RN_EDPD,
1127	val: reg | MII_KSZ9031RN_EDPD_ENABLE);
1128	}
1129
1130	static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1131	{
1132	u16 rx, tx, rx_clk, tx_clk;
1133	int ret;
1134
1135	switch (phydev->interface) {
1136	case PHY_INTERFACE_MODE_RGMII:
1137	tx = TX_ND;
1138	tx_clk = TX_CLK_ND;
1139	rx = RX_ND;
1140	rx_clk = RX_CLK_ND;
1141	break;
1142	case PHY_INTERFACE_MODE_RGMII_ID:
1143	tx = TX_ID;
1144	tx_clk = TX_CLK_ID;
1145	rx = RX_ID;
1146	rx_clk = RX_CLK_ID;
1147	break;
1148	case PHY_INTERFACE_MODE_RGMII_RXID:
1149	tx = TX_ND;
1150	tx_clk = TX_CLK_ND;
1151	rx = RX_ID;
1152	rx_clk = RX_CLK_ID;
1153	break;
1154	case PHY_INTERFACE_MODE_RGMII_TXID:
1155	tx = TX_ID;
1156	tx_clk = TX_CLK_ID;
1157	rx = RX_ND;
1158	rx_clk = RX_CLK_ND;
1159	break;
1160	default:
1161	return 0;
1162	}
1163
1164	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1165	FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1166	FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1167	if (ret < 0)
1168	return ret;
1169
1170	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1171	FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1172	FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1173	FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1174	FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1175	if (ret < 0)
1176	return ret;
1177
1178	ret = phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1179	FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1180	FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1181	FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1182	FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1183	if (ret < 0)
1184	return ret;
1185
1186	return phy_write_mmd(phydev, devad: 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1187	FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1188	FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1189	}
1190
1191	static int ksz9031_config_init(struct phy_device *phydev)
1192	{
1193	const struct device_node *of_node;
1194	static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1195	static const char *rx_data_skews[4] = {
1196	"rxd0-skew-ps", "rxd1-skew-ps",
1197	"rxd2-skew-ps", "rxd3-skew-ps"
1198	};
1199	static const char *tx_data_skews[4] = {
1200	"txd0-skew-ps", "txd1-skew-ps",
1201	"txd2-skew-ps", "txd3-skew-ps"
1202	};
1203	static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1204	const struct device *dev_walker;
1205	int result;
1206
1207	result = ksz9031_enable_edpd(phydev);
1208	if (result < 0)
1209	return result;
1210
1211	/* The Micrel driver has a deprecated option to place phy OF
1212	* properties in the MAC node. Walk up the tree of devices to
1213	* find a device with an OF node.
1214	*/
1215	dev_walker = &phydev->mdio.dev;
1216	do {
1217	of_node = dev_walker->of_node;
1218	dev_walker = dev_walker->parent;
1219	} while (!of_node && dev_walker);
1220
1221	if (of_node) {
1222	bool update = false;
1223
1224	if (phy_interface_is_rgmii(phydev)) {
1225	result = ksz9031_config_rgmii_delay(phydev);
1226	if (result < 0)
1227	return result;
1228	}
1229
1230	ksz9031_of_load_skew_values(phydev, of_node,
1231	MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5,
1232	field: clk_skews, numfields: 2, update: &update);
1233
1234	ksz9031_of_load_skew_values(phydev, of_node,
1235	MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4,
1236	field: control_skews, numfields: 2, update: &update);
1237
1238	ksz9031_of_load_skew_values(phydev, of_node,
1239	MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4,
1240	field: rx_data_skews, numfields: 4, update: &update);
1241
1242	ksz9031_of_load_skew_values(phydev, of_node,
1243	MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4,
1244	field: tx_data_skews, numfields: 4, update: &update);
1245
1246	if (update && !phy_interface_is_rgmii(phydev))
1247	phydev_warn(phydev,
1248	"*-skew-ps values should be used only with RGMII PHY modes\n");
1249
1250	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
1251	* When the device links in the 1000BASE-T slave mode only,
1252	* the optional 125MHz reference output clock (CLK125_NDO)
1253	* has wide duty cycle variation.
1254	*
1255	* The optional CLK125_NDO clock does not meet the RGMII
1256	* 45/55 percent (min/max) duty cycle requirement and therefore
1257	* cannot be used directly by the MAC side for clocking
1258	* applications that have setup/hold time requirements on
1259	* rising and falling clock edges.
1260	*
1261	* Workaround:
1262	* Force the phy to be the master to receive a stable clock
1263	* which meets the duty cycle requirement.
1264	*/
1265	if (of_property_read_bool(np: of_node, propname: "micrel,force-master")) {
1266	result = phy_read(phydev, MII_CTRL1000);
1267	if (result < 0)
1268	goto err_force_master;
1269
1270	/* enable master mode, config & prefer master */
1271	result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1272	result = phy_write(phydev, MII_CTRL1000, val: result);
1273	if (result < 0)
1274	goto err_force_master;
1275	}
1276	}
1277
1278	return ksz9031_center_flp_timing(phydev);
1279
1280	err_force_master:
1281	phydev_err(phydev, "failed to force the phy to master mode\n");
1282	return result;
1283	}
1284
1285	#define KSZ9131_SKEW_5BIT_MAX 2400
1286	#define KSZ9131_SKEW_4BIT_MAX 800
1287	#define KSZ9131_OFFSET 700
1288	#define KSZ9131_STEP 100
1289
1290	static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1291	struct device_node *of_node,
1292	u16 reg, size_t field_sz,
1293	char *field[], u8 numfields)
1294	{
1295	int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1296	-(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1297	int skewval, skewmax = 0;
1298	int matches = 0;
1299	u16 maxval;
1300	u16 newval;
1301	u16 mask;
1302	int i;
1303
1304	/* psec properties in dts should mean x pico seconds */
1305	if (field_sz == 5)
1306	skewmax = KSZ9131_SKEW_5BIT_MAX;
1307	else
1308	skewmax = KSZ9131_SKEW_4BIT_MAX;
1309
1310	for (i = 0; i < numfields; i++)
1311	if (!of_property_read_s32(np: of_node, propname: field[i], out_value: &skewval)) {
1312	if (skewval < -KSZ9131_OFFSET)
1313	skewval = -KSZ9131_OFFSET;
1314	else if (skewval > skewmax)
1315	skewval = skewmax;
1316
1317	val[i] = skewval + KSZ9131_OFFSET;
1318	matches++;
1319	}
1320
1321	if (!matches)
1322	return 0;
1323
1324	if (matches < numfields)
1325	newval = phy_read_mmd(phydev, devad: 2, regnum: reg);
1326	else
1327	newval = 0;
1328
1329	maxval = (field_sz == 4) ? 0xf : 0x1f;
1330	for (i = 0; i < numfields; i++)
1331	if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1332	mask = 0xffff;
1333	mask ^= maxval << (field_sz * i);
1334	newval = (newval & mask) |
1335	(((val[i] / KSZ9131_STEP) & maxval)
1336	<< (field_sz * i));
1337	}
1338
1339	return phy_write_mmd(phydev, devad: 2, regnum: reg, val: newval);
1340	}
1341
1342	#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1343	#define KSZ9131RN_RXC_DLL_CTRL 76
1344	#define KSZ9131RN_TXC_DLL_CTRL 77
1345	#define KSZ9131RN_DLL_ENABLE_DELAY 0
1346
1347	static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1348	{
1349	const struct kszphy_type *type = phydev->drv->driver_data;
1350	u16 rxcdll_val, txcdll_val;
1351	int ret;
1352
1353	switch (phydev->interface) {
1354	case PHY_INTERFACE_MODE_RGMII:
1355	rxcdll_val = type->disable_dll_rx_bit;
1356	txcdll_val = type->disable_dll_tx_bit;
1357	break;
1358	case PHY_INTERFACE_MODE_RGMII_ID:
1359	rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1360	txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1361	break;
1362	case PHY_INTERFACE_MODE_RGMII_RXID:
1363	rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1364	txcdll_val = type->disable_dll_tx_bit;
1365	break;
1366	case PHY_INTERFACE_MODE_RGMII_TXID:
1367	rxcdll_val = type->disable_dll_rx_bit;
1368	txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1369	break;
1370	default:
1371	return 0;
1372	}
1373
1374	ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1375	KSZ9131RN_RXC_DLL_CTRL, mask: type->disable_dll_mask,
1376	set: rxcdll_val);
1377	if (ret < 0)
1378	return ret;
1379
1380	return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1381	KSZ9131RN_TXC_DLL_CTRL, mask: type->disable_dll_mask,
1382	set: txcdll_val);
1383	}
1384
1385	/* Silicon Errata DS80000693B
1386	*
1387	* When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1388	* condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1389	* according to the datasheet (off if there is no link).
1390	*/
1391	static int ksz9131_led_errata(struct phy_device *phydev)
1392	{
1393	int reg;
1394
1395	reg = phy_read_mmd(phydev, devad: 2, regnum: 0);
1396	if (reg < 0)
1397	return reg;
1398
1399	if (!(reg & BIT(4)))
1400	return 0;
1401
1402	return phy_set_bits(phydev, regnum: 0x1e, BIT(9));
1403	}
1404
1405	static int ksz9131_config_init(struct phy_device *phydev)
1406	{
1407	struct device_node *of_node;
1408	char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1409	char *rx_data_skews[4] = {
1410	"rxd0-skew-psec", "rxd1-skew-psec",
1411	"rxd2-skew-psec", "rxd3-skew-psec"
1412	};
1413	char *tx_data_skews[4] = {
1414	"txd0-skew-psec", "txd1-skew-psec",
1415	"txd2-skew-psec", "txd3-skew-psec"
1416	};
1417	char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1418	const struct device *dev_walker;
1419	int ret;
1420
1421	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1422
1423	dev_walker = &phydev->mdio.dev;
1424	do {
1425	of_node = dev_walker->of_node;
1426	dev_walker = dev_walker->parent;
1427	} while (!of_node && dev_walker);
1428
1429	if (!of_node)
1430	return 0;
1431
1432	if (phy_interface_is_rgmii(phydev)) {
1433	ret = ksz9131_config_rgmii_delay(phydev);
1434	if (ret < 0)
1435	return ret;
1436	}
1437
1438	ret = ksz9131_of_load_skew_values(phydev, of_node,
1439	MII_KSZ9031RN_CLK_PAD_SKEW, field_sz: 5,
1440	field: clk_skews, numfields: 2);
1441	if (ret < 0)
1442	return ret;
1443
1444	ret = ksz9131_of_load_skew_values(phydev, of_node,
1445	MII_KSZ9031RN_CONTROL_PAD_SKEW, field_sz: 4,
1446	field: control_skews, numfields: 2);
1447	if (ret < 0)
1448	return ret;
1449
1450	ret = ksz9131_of_load_skew_values(phydev, of_node,
1451	MII_KSZ9031RN_RX_DATA_PAD_SKEW, field_sz: 4,
1452	field: rx_data_skews, numfields: 4);
1453	if (ret < 0)
1454	return ret;
1455
1456	ret = ksz9131_of_load_skew_values(phydev, of_node,
1457	MII_KSZ9031RN_TX_DATA_PAD_SKEW, field_sz: 4,
1458	field: tx_data_skews, numfields: 4);
1459	if (ret < 0)
1460	return ret;
1461
1462	ret = ksz9131_led_errata(phydev);
1463	if (ret < 0)
1464	return ret;
1465
1466	return 0;
1467	}
1468
1469	#define MII_KSZ9131_AUTO_MDIX 0x1C
1470	#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1471	#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1472	#define MII_KSZ9131_DIG_AXAN_STS 0x14
1473	#define MII_KSZ9131_DIG_AXAN_STS_LINK_DET BIT(14)
1474	#define MII_KSZ9131_DIG_AXAN_STS_A_SELECT BIT(12)
1475
1476	static int ksz9131_mdix_update(struct phy_device *phydev)
1477	{
1478	int ret;
1479
1480	if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {
1481	phydev->mdix = phydev->mdix_ctrl;
1482	} else {
1483	ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);
1484	if (ret < 0)
1485	return ret;
1486
1487	if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {
1488	if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)
1489	phydev->mdix = ETH_TP_MDI;
1490	else
1491	phydev->mdix = ETH_TP_MDI_X;
1492	} else {
1493	phydev->mdix = ETH_TP_MDI_INVALID;
1494	}
1495	}
1496
1497	return 0;
1498	}
1499
1500	static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1501	{
1502	u16 val;
1503
1504	switch (ctrl) {
1505	case ETH_TP_MDI:
1506	val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1507	MII_KSZ9131_AUTO_MDI_SET;
1508	break;
1509	case ETH_TP_MDI_X:
1510	val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1511	break;
1512	case ETH_TP_MDI_AUTO:
1513	val = 0;
1514	break;
1515	default:
1516	return 0;
1517	}
1518
1519	return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1520	MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1521	MII_KSZ9131_AUTO_MDI_SET, set: val);
1522	}
1523
1524	static int ksz9131_read_status(struct phy_device *phydev)
1525	{
1526	int ret;
1527
1528	ret = ksz9131_mdix_update(phydev);
1529	if (ret < 0)
1530	return ret;
1531
1532	return genphy_read_status(phydev);
1533	}
1534
1535	static int ksz9131_config_aneg(struct phy_device *phydev)
1536	{
1537	int ret;
1538
1539	ret = ksz9131_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
1540	if (ret)
1541	return ret;
1542
1543	return genphy_config_aneg(phydev);
1544	}
1545
1546	static int ksz9477_get_features(struct phy_device *phydev)
1547	{
1548	int ret;
1549
1550	ret = genphy_read_abilities(phydev);
1551	if (ret)
1552	return ret;
1553
1554	/* The "EEE control and capability 1" (Register 3.20) seems to be
1555	* influenced by the "EEE advertisement 1" (Register 7.60). Changes
1556	* on the 7.60 will affect 3.20. So, we need to construct our own list
1557	* of caps.
1558	* KSZ8563R should have 100BaseTX/Full only.
1559	*/
1560	linkmode_and(dst: phydev->supported_eee, a: phydev->supported,
1561	PHY_EEE_CAP1_FEATURES);
1562
1563	return 0;
1564	}
1565
1566	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1567	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1568	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1569	static int ksz8873mll_read_status(struct phy_device *phydev)
1570	{
1571	int regval;
1572
1573	/* dummy read */
1574	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1575
1576	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1577
1578	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1579	phydev->duplex = DUPLEX_HALF;
1580	else
1581	phydev->duplex = DUPLEX_FULL;
1582
1583	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1584	phydev->speed = SPEED_10;
1585	else
1586	phydev->speed = SPEED_100;
1587
1588	phydev->link = 1;
1589	phydev->pause = phydev->asym_pause = 0;
1590
1591	return 0;
1592	}
1593
1594	static int ksz9031_get_features(struct phy_device *phydev)
1595	{
1596	int ret;
1597
1598	ret = genphy_read_abilities(phydev);
1599	if (ret < 0)
1600	return ret;
1601
1602	/* Silicon Errata Sheet (DS80000691D or DS80000692D):
1603	* Whenever the device's Asymmetric Pause capability is set to 1,
1604	* link-up may fail after a link-up to link-down transition.
1605	*
1606	* The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1607	*
1608	* Workaround:
1609	* Do not enable the Asymmetric Pause capability bit.
1610	*/
1611	linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1612
1613	/* We force setting the Pause capability as the core will force the
1614	* Asymmetric Pause capability to 1 otherwise.
1615	*/
1616	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1617
1618	return 0;
1619	}
1620
1621	static int ksz9031_read_status(struct phy_device *phydev)
1622	{
1623	int err;
1624	int regval;
1625
1626	err = genphy_read_status(phydev);
1627	if (err)
1628	return err;
1629
1630	/* Make sure the PHY is not broken. Read idle error count,
1631	* and reset the PHY if it is maxed out.
1632	*/
1633	regval = phy_read(phydev, MII_STAT1000);
1634	if ((regval & 0xFF) == 0xFF) {
1635	phy_init_hw(phydev);
1636	phydev->link = 0;
1637	if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1638	phydev->drv->config_intr(phydev);
1639	return genphy_config_aneg(phydev);
1640	}
1641
1642	return 0;
1643	}
1644
1645	static int ksz9x31_cable_test_start(struct phy_device *phydev)
1646	{
1647	struct kszphy_priv *priv = phydev->priv;
1648	int ret;
1649
1650	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1651	* Prior to running the cable diagnostics, Auto-negotiation should
1652	* be disabled, full duplex set and the link speed set to 1000Mbps
1653	* via the Basic Control Register.
1654	*/
1655	ret = phy_modify(phydev, MII_BMCR,
1656	BMCR_SPEED1000 | BMCR_FULLDPLX |
1657	BMCR_ANENABLE | BMCR_SPEED100,
1658	BMCR_SPEED1000 | BMCR_FULLDPLX);
1659	if (ret)
1660	return ret;
1661
1662	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1663	* The Master-Slave configuration should be set to Slave by writing
1664	* a value of 0x1000 to the Auto-Negotiation Master Slave Control
1665	* Register.
1666	*/
1667	ret = phy_read(phydev, MII_CTRL1000);
1668	if (ret < 0)
1669	return ret;
1670
1671	/* Cache these bits, they need to be restored once LinkMD finishes. */
1672	priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1673	ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1674	ret |= CTL1000_ENABLE_MASTER;
1675
1676	return phy_write(phydev, MII_CTRL1000, val: ret);
1677	}
1678
1679	static int ksz9x31_cable_test_result_trans(u16 status)
1680	{
1681	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1682	case KSZ9x31_LMD_VCT_ST_NORMAL:
1683	return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1684	case KSZ9x31_LMD_VCT_ST_OPEN:
1685	return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1686	case KSZ9x31_LMD_VCT_ST_SHORT:
1687	return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1688	case KSZ9x31_LMD_VCT_ST_FAIL:
1689	fallthrough;
1690	default:
1691	return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1692	}
1693	}
1694
1695	static bool ksz9x31_cable_test_failed(u16 status)
1696	{
1697	int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1698
1699	return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1700	}
1701
1702	static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1703	{
1704	switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1705	case KSZ9x31_LMD_VCT_ST_OPEN:
1706	fallthrough;
1707	case KSZ9x31_LMD_VCT_ST_SHORT:
1708	return true;
1709	}
1710	return false;
1711	}
1712
1713	static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1714	{
1715	int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1716
1717	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1718	*
1719	* distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1720	*/
1721	if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1722	dt = clamp(dt - 22, 0, 255);
1723
1724	return (dt * 400) / 10;
1725	}
1726
1727	static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1728	{
1729	int val, ret;
1730
1731	ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1732	!(val & KSZ9x31_LMD_VCT_EN),
1733	30000, 100000, true);
1734
1735	return ret < 0 ? ret : 0;
1736	}
1737
1738	static int ksz9x31_cable_test_get_pair(int pair)
1739	{
1740	static const int ethtool_pair[] = {
1741	ETHTOOL_A_CABLE_PAIR_A,
1742	ETHTOOL_A_CABLE_PAIR_B,
1743	ETHTOOL_A_CABLE_PAIR_C,
1744	ETHTOOL_A_CABLE_PAIR_D,
1745	};
1746
1747	return ethtool_pair[pair];
1748	}
1749
1750	static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1751	{
1752	int ret, val;
1753
1754	/* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1755	* To test each individual cable pair, set the cable pair in the Cable
1756	* Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1757	* Diagnostic Register, along with setting the Cable Diagnostics Test
1758	* Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1759	* will self clear when the test is concluded.
1760	*/
1761	ret = phy_write(phydev, KSZ9x31_LMD,
1762	KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1763	if (ret)
1764	return ret;
1765
1766	ret = ksz9x31_cable_test_wait_for_completion(phydev);
1767	if (ret)
1768	return ret;
1769
1770	val = phy_read(phydev, KSZ9x31_LMD);
1771	if (val < 0)
1772	return val;
1773
1774	if (ksz9x31_cable_test_failed(status: val))
1775	return -EAGAIN;
1776
1777	ret = ethnl_cable_test_result(phydev,
1778	pair: ksz9x31_cable_test_get_pair(pair),
1779	result: ksz9x31_cable_test_result_trans(status: val));
1780	if (ret)
1781	return ret;
1782
1783	if (!ksz9x31_cable_test_fault_length_valid(status: val))
1784	return 0;
1785
1786	return ethnl_cable_test_fault_length(phydev,
1787	pair: ksz9x31_cable_test_get_pair(pair),
1788	cm: ksz9x31_cable_test_fault_length(phydev, stat: val));
1789	}
1790
1791	static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1792	bool *finished)
1793	{
1794	struct kszphy_priv *priv = phydev->priv;
1795	unsigned long pair_mask = 0xf;
1796	int retries = 20;
1797	int pair, ret, rv;
1798
1799	*finished = false;
1800
1801	/* Try harder if link partner is active */
1802	while (pair_mask && retries--) {
1803	for_each_set_bit(pair, &pair_mask, 4) {
1804	ret = ksz9x31_cable_test_one_pair(phydev, pair);
1805	if (ret == -EAGAIN)
1806	continue;
1807	if (ret < 0)
1808	return ret;
1809	clear_bit(nr: pair, addr: &pair_mask);
1810	}
1811	/* If link partner is in autonegotiation mode it will send 2ms
1812	* of FLPs with at least 6ms of silence.
1813	* Add 2ms sleep to have better chances to hit this silence.
1814	*/
1815	if (pair_mask)
1816	usleep_range(min: 2000, max: 3000);
1817	}
1818
1819	/* Report remaining unfinished pair result as unknown. */
1820	for_each_set_bit(pair, &pair_mask, 4) {
1821	ret = ethnl_cable_test_result(phydev,
1822	pair: ksz9x31_cable_test_get_pair(pair),
1823	result: ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1824	}
1825
1826	*finished = true;
1827
1828	/* Restore cached bits from before LinkMD got started. */
1829	rv = phy_modify(phydev, MII_CTRL1000,
1830	CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1831	set: priv->vct_ctrl1000);
1832	if (rv)
1833	return rv;
1834
1835	return ret;
1836	}
1837
1838	static int ksz8873mll_config_aneg(struct phy_device *phydev)
1839	{
1840	return 0;
1841	}
1842
1843	static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1844	{
1845	u16 val;
1846
1847	switch (ctrl) {
1848	case ETH_TP_MDI:
1849	val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1850	break;
1851	case ETH_TP_MDI_X:
1852	/* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1853	* counter intuitive, the "-X" in "1 = Force MDI" in the data
1854	* sheet seems to be missing:
1855	* 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1856	* 0 = Normal operation (transmit on TX+/TX- pins)
1857	*/
1858	val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1859	break;
1860	case ETH_TP_MDI_AUTO:
1861	val = 0;
1862	break;
1863	default:
1864	return 0;
1865	}
1866
1867	return phy_modify(phydev, MII_BMCR,
1868	KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1869	KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1870	KSZ886X_BMCR_HP_MDIX | val);
1871	}
1872
1873	static int ksz886x_config_aneg(struct phy_device *phydev)
1874	{
1875	int ret;
1876
1877	ret = genphy_config_aneg(phydev);
1878	if (ret)
1879	return ret;
1880
1881	if (phydev->autoneg != AUTONEG_ENABLE) {
1882	/* When autonegotation is disabled, we need to manually force
1883	* the link state. If we don't do this, the PHY will keep
1884	* sending Fast Link Pulses (FLPs) which are part of the
1885	* autonegotiation process. This is not desired when
1886	* autonegotiation is off.
1887	*/
1888	ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1889	KSZ886X_CTRL_FORCE_LINK);
1890	if (ret)
1891	return ret;
1892	} else {
1893	/* If we had previously forced the link state, we need to
1894	* clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1895	* will not perform autonegotiation.
1896	*/
1897	ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1898	KSZ886X_CTRL_FORCE_LINK);
1899	if (ret)
1900	return ret;
1901	}
1902
1903	/* The MDI-X configuration is automatically changed by the PHY after
1904	* switching from autoneg off to on. So, take MDI-X configuration under
1905	* own control and set it after autoneg configuration was done.
1906	*/
1907	return ksz886x_config_mdix(phydev, ctrl: phydev->mdix_ctrl);
1908	}
1909
1910	static int ksz886x_mdix_update(struct phy_device *phydev)
1911	{
1912	int ret;
1913
1914	ret = phy_read(phydev, MII_BMCR);
1915	if (ret < 0)
1916	return ret;
1917
1918	if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1919	if (ret & KSZ886X_BMCR_FORCE_MDI)
1920	phydev->mdix_ctrl = ETH_TP_MDI_X;
1921	else
1922	phydev->mdix_ctrl = ETH_TP_MDI;
1923	} else {
1924	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1925	}
1926
1927	ret = phy_read(phydev, MII_KSZPHY_CTRL);
1928	if (ret < 0)
1929	return ret;
1930
1931	/* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1932	if (ret & KSZ886X_CTRL_MDIX_STAT)
1933	phydev->mdix = ETH_TP_MDI_X;
1934	else
1935	phydev->mdix = ETH_TP_MDI;
1936
1937	return 0;
1938	}
1939
1940	static int ksz886x_read_status(struct phy_device *phydev)
1941	{
1942	int ret;
1943
1944	ret = ksz886x_mdix_update(phydev);
1945	if (ret < 0)
1946	return ret;
1947
1948	return genphy_read_status(phydev);
1949	}
1950
1951	struct ksz9477_errata_write {
1952	u8 dev_addr;
1953	u8 reg_addr;
1954	u16 val;
1955	};
1956
1957	static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1958	/* Register settings are needed to improve PHY receive performance */
1959	{0x01, 0x6f, 0xdd0b},
1960	{0x01, 0x8f, 0x6032},
1961	{0x01, 0x9d, 0x248c},
1962	{0x01, 0x75, 0x0060},
1963	{0x01, 0xd3, 0x7777},
1964	{0x1c, 0x06, 0x3008},
1965	{0x1c, 0x08, 0x2000},
1966
1967	/* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1968	{0x1c, 0x04, 0x00d0},
1969
1970	/* Register settings are required to meet data sheet supply current specifications */
1971	{0x1c, 0x13, 0x6eff},
1972	{0x1c, 0x14, 0xe6ff},
1973	{0x1c, 0x15, 0x6eff},
1974	{0x1c, 0x16, 0xe6ff},
1975	{0x1c, 0x17, 0x00ff},
1976	{0x1c, 0x18, 0x43ff},
1977	{0x1c, 0x19, 0xc3ff},
1978	{0x1c, 0x1a, 0x6fff},
1979	{0x1c, 0x1b, 0x07ff},
1980	{0x1c, 0x1c, 0x0fff},
1981	{0x1c, 0x1d, 0xe7ff},
1982	{0x1c, 0x1e, 0xefff},
1983	{0x1c, 0x20, 0xeeee},
1984	};
1985
1986	static int ksz9477_phy_errata(struct phy_device *phydev)
1987	{
1988	int err;
1989	int i;
1990
1991	/* Apply PHY settings to address errata listed in
1992	* KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1993	* Silicon Errata and Data Sheet Clarification documents.
1994	*
1995	* Document notes: Before configuring the PHY MMD registers, it is
1996	* necessary to set the PHY to 100 Mbps speed with auto-negotiation
1997	* disabled by writing to register 0xN100-0xN101. After writing the
1998	* MMD registers, and after all errata workarounds that involve PHY
1999	* register settings, write register 0xN100-0xN101 again to enable
2000	* and restart auto-negotiation.
2001	*/
2002	err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
2003	if (err)
2004	return err;
2005
2006	for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
2007	const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
2008
2009	err = phy_write_mmd(phydev, devad: errata->dev_addr, regnum: errata->reg_addr, val: errata->val);
2010	if (err)
2011	return err;
2012	}
2013
2014	err = genphy_restart_aneg(phydev);
2015	if (err)
2016	return err;
2017
2018	return err;
2019	}
2020
2021	static int ksz9477_config_init(struct phy_device *phydev)
2022	{
2023	int err;
2024
2025	/* Only KSZ9897 family of switches needs this fix. */
2026	if ((phydev->phy_id & 0xf) == 1) {
2027	err = ksz9477_phy_errata(phydev);
2028	if (err)
2029	return err;
2030	}
2031
2032	return kszphy_config_init(phydev);
2033	}
2034
2035	static int kszphy_get_sset_count(struct phy_device *phydev)
2036	{
2037	return ARRAY_SIZE(kszphy_hw_stats);
2038	}
2039
2040	static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
2041	{
2042	int i;
2043
2044	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2045	ethtool_puts(data: &data, str: kszphy_hw_stats[i].string);
2046	}
2047
2048	static u64 kszphy_get_stat(struct phy_device *phydev, int i)
2049	{
2050	struct kszphy_hw_stat stat = kszphy_hw_stats[i];
2051	struct kszphy_priv *priv = phydev->priv;
2052	int val;
2053	u64 ret;
2054
2055	val = phy_read(phydev, regnum: stat.reg);
2056	if (val < 0) {
2057	ret = U64_MAX;
2058	} else {
2059	val = val & ((1 << stat.bits) - 1);
2060	priv->stats[i] += val;
2061	ret = priv->stats[i];
2062	}
2063
2064	return ret;
2065	}
2066
2067	static void kszphy_get_stats(struct phy_device *phydev,
2068	struct ethtool_stats *stats, u64 *data)
2069	{
2070	int i;
2071
2072	for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2073	data[i] = kszphy_get_stat(phydev, i);
2074	}
2075
2076	static void kszphy_enable_clk(struct phy_device *phydev)
2077	{
2078	struct kszphy_priv *priv = phydev->priv;
2079
2080	if (!priv->clk_enable && priv->clk) {
2081	clk_prepare_enable(clk: priv->clk);
2082	priv->clk_enable = true;
2083	}
2084	}
2085
2086	static void kszphy_disable_clk(struct phy_device *phydev)
2087	{
2088	struct kszphy_priv *priv = phydev->priv;
2089
2090	if (priv->clk_enable && priv->clk) {
2091	clk_disable_unprepare(clk: priv->clk);
2092	priv->clk_enable = false;
2093	}
2094	}
2095
2096	static int kszphy_generic_resume(struct phy_device *phydev)
2097	{
2098	kszphy_enable_clk(phydev);
2099
2100	return genphy_resume(phydev);
2101	}
2102
2103	static int kszphy_generic_suspend(struct phy_device *phydev)
2104	{
2105	int ret;
2106
2107	ret = genphy_suspend(phydev);
2108	if (ret)
2109	return ret;
2110
2111	kszphy_disable_clk(phydev);
2112
2113	return 0;
2114	}
2115
2116	static int kszphy_suspend(struct phy_device *phydev)
2117	{
2118	/* Disable PHY Interrupts */
2119	if (phy_interrupt_is_valid(phydev)) {
2120	phydev->interrupts = PHY_INTERRUPT_DISABLED;
2121	if (phydev->drv->config_intr)
2122	phydev->drv->config_intr(phydev);
2123	}
2124
2125	return kszphy_generic_suspend(phydev);
2126	}
2127
2128	static void kszphy_parse_led_mode(struct phy_device *phydev)
2129	{
2130	const struct kszphy_type *type = phydev->drv->driver_data;
2131	const struct device_node *np = phydev->mdio.dev.of_node;
2132	struct kszphy_priv *priv = phydev->priv;
2133	int ret;
2134
2135	if (type && type->led_mode_reg) {
2136	ret = of_property_read_u32(np, propname: "micrel,led-mode",
2137	out_value: &priv->led_mode);
2138
2139	if (ret)
2140	priv->led_mode = -1;
2141
2142	if (priv->led_mode > 3) {
2143	phydev_err(phydev, "invalid led mode: 0x%02x\n",
2144	priv->led_mode);
2145	priv->led_mode = -1;
2146	}
2147	} else {
2148	priv->led_mode = -1;
2149	}
2150	}
2151
2152	static int kszphy_resume(struct phy_device *phydev)
2153	{
2154	int ret;
2155
2156	ret = kszphy_generic_resume(phydev);
2157	if (ret)
2158	return ret;
2159
2160	/* After switching from power-down to normal mode, an internal global
2161	* reset is automatically generated. Wait a minimum of 1 ms before
2162	* read/write access to the PHY registers.
2163	*/
2164	usleep_range(min: 1000, max: 2000);
2165
2166	ret = kszphy_config_reset(phydev);
2167	if (ret)
2168	return ret;
2169
2170	/* Enable PHY Interrupts */
2171	if (phy_interrupt_is_valid(phydev)) {
2172	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2173	if (phydev->drv->config_intr)
2174	phydev->drv->config_intr(phydev);
2175	}
2176
2177	return 0;
2178	}
2179
2180	/* Because of errata DS80000700A, receiver error following software
2181	* power down. Suspend and resume callbacks only disable and enable
2182	* external rmii reference clock.
2183	*/
2184	static int ksz8041_resume(struct phy_device *phydev)
2185	{
2186	kszphy_enable_clk(phydev);
2187
2188	return 0;
2189	}
2190
2191	static int ksz8041_suspend(struct phy_device *phydev)
2192	{
2193	kszphy_disable_clk(phydev);
2194
2195	return 0;
2196	}
2197
2198	static int ksz9477_resume(struct phy_device *phydev)
2199	{
2200	int ret;
2201
2202	/* No need to initialize registers if not powered down. */
2203	ret = phy_read(phydev, MII_BMCR);
2204	if (ret < 0)
2205	return ret;
2206	if (!(ret & BMCR_PDOWN))
2207	return 0;
2208
2209	genphy_resume(phydev);
2210
2211	/* After switching from power-down to normal mode, an internal global
2212	* reset is automatically generated. Wait a minimum of 1 ms before
2213	* read/write access to the PHY registers.
2214	*/
2215	usleep_range(min: 1000, max: 2000);
2216
2217	/* Only KSZ9897 family of switches needs this fix. */
2218	if ((phydev->phy_id & 0xf) == 1) {
2219	ret = ksz9477_phy_errata(phydev);
2220	if (ret)
2221	return ret;
2222	}
2223
2224	/* Enable PHY Interrupts */
2225	if (phy_interrupt_is_valid(phydev)) {
2226	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2227	if (phydev->drv->config_intr)
2228	phydev->drv->config_intr(phydev);
2229	}
2230
2231	return 0;
2232	}
2233
2234	static int ksz8061_resume(struct phy_device *phydev)
2235	{
2236	int ret;
2237
2238	/* This function can be called twice when the Ethernet device is on. */
2239	ret = phy_read(phydev, MII_BMCR);
2240	if (ret < 0)
2241	return ret;
2242	if (!(ret & BMCR_PDOWN))
2243	return 0;
2244
2245	ret = kszphy_generic_resume(phydev);
2246	if (ret)
2247	return ret;
2248
2249	usleep_range(min: 1000, max: 2000);
2250
2251	/* Re-program the value after chip is reset. */
2252	ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, val: 0xB61A);
2253	if (ret)
2254	return ret;
2255
2256	/* Enable PHY Interrupts */
2257	if (phy_interrupt_is_valid(phydev)) {
2258	phydev->interrupts = PHY_INTERRUPT_ENABLED;
2259	if (phydev->drv->config_intr)
2260	phydev->drv->config_intr(phydev);
2261	}
2262
2263	return 0;
2264	}
2265
2266	static int ksz8061_suspend(struct phy_device *phydev)
2267	{
2268	return kszphy_suspend(phydev);
2269	}
2270
2271	static int kszphy_probe(struct phy_device *phydev)
2272	{
2273	const struct kszphy_type *type = phydev->drv->driver_data;
2274	const struct device_node *np = phydev->mdio.dev.of_node;
2275	struct kszphy_priv *priv;
2276	struct clk *clk;
2277
2278	priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL);
2279	if (!priv)
2280	return -ENOMEM;
2281
2282	phydev->priv = priv;
2283
2284	priv->type = type;
2285
2286	kszphy_parse_led_mode(phydev);
2287
2288	clk = devm_clk_get_optional_enabled(dev: &phydev->mdio.dev, id: "rmii-ref");
2289	/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2290	if (!IS_ERR_OR_NULL(ptr: clk)) {
2291	unsigned long rate = clk_get_rate(clk);
2292	bool rmii_ref_clk_sel_25_mhz;
2293
2294	if (type)
2295	priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2296	rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2297	propname: "micrel,rmii-reference-clock-select-25-mhz");
2298
2299	if (rate > 24500000 && rate < 25500000) {
2300	priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2301	} else if (rate > 49500000 && rate < 50500000) {
2302	priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2303	} else {
2304	phydev_err(phydev, "Clock rate out of range: %ld\n",
2305	rate);
2306	return -EINVAL;
2307	}
2308	} else if (!clk) {
2309	/* unnamed clock from the generic ethernet-phy binding */
2310	clk = devm_clk_get_optional_enabled(dev: &phydev->mdio.dev, NULL);
2311	}
2312
2313	if (IS_ERR(ptr: clk))
2314	return PTR_ERR(ptr: clk);
2315
2316	clk_disable_unprepare(clk);
2317	priv->clk = clk;
2318
2319	if (ksz8041_fiber_mode(phydev))
2320	phydev->port = PORT_FIBRE;
2321
2322	/* Support legacy board-file configuration */
2323	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2324	priv->rmii_ref_clk_sel = true;
2325	priv->rmii_ref_clk_sel_val = true;
2326	}
2327
2328	return 0;
2329	}
2330
2331	static int lan8814_cable_test_start(struct phy_device *phydev)
2332	{
2333	/* If autoneg is enabled, we won't be able to test cross pair
2334	* short. In this case, the PHY will "detect" a link and
2335	* confuse the internal state machine - disable auto neg here.
2336	* Set the speed to 1000mbit and full duplex.
2337	*/
2338	return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2339	BMCR_SPEED1000 | BMCR_FULLDPLX);
2340	}
2341
2342	static int ksz886x_cable_test_start(struct phy_device *phydev)
2343	{
2344	if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2345	return -EOPNOTSUPP;
2346
2347	/* If autoneg is enabled, we won't be able to test cross pair
2348	* short. In this case, the PHY will "detect" a link and
2349	* confuse the internal state machine - disable auto neg here.
2350	* If autoneg is disabled, we should set the speed to 10mbit.
2351	*/
2352	return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2353	}
2354
2355	static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2356	{
2357	switch (FIELD_GET(mask, status)) {
2358	case KSZ8081_LMD_STAT_NORMAL:
2359	return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2360	case KSZ8081_LMD_STAT_SHORT:
2361	return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2362	case KSZ8081_LMD_STAT_OPEN:
2363	return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2364	case KSZ8081_LMD_STAT_FAIL:
2365	fallthrough;
2366	default:
2367	return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2368	}
2369	}
2370
2371	static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2372	{
2373	return FIELD_GET(mask, status) ==
2374	KSZ8081_LMD_STAT_FAIL;
2375	}
2376
2377	static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2378	{
2379	switch (FIELD_GET(mask, status)) {
2380	case KSZ8081_LMD_STAT_OPEN:
2381	fallthrough;
2382	case KSZ8081_LMD_STAT_SHORT:
2383	return true;
2384	}
2385	return false;
2386	}
2387
2388	static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2389	u16 status, u16 data_mask)
2390	{
2391	int dt;
2392
2393	/* According to the data sheet the distance to the fault is
2394	* DELTA_TIME * 0.4 meters for ksz phys.
2395	* (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2396	*/
2397	dt = FIELD_GET(data_mask, status);
2398
2399	if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2400	return ((dt - 22) * 800) / 10;
2401	else
2402	return (dt * 400) / 10;
2403	}
2404
2405	static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2406	{
2407	const struct kszphy_type *type = phydev->drv->driver_data;
2408	int val, ret;
2409
2410	ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2411	!(val & KSZ8081_LMD_ENABLE_TEST),
2412	30000, 100000, true);
2413
2414	return ret < 0 ? ret : 0;
2415	}
2416
2417	static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2418	{
2419	static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2420	ETHTOOL_A_CABLE_PAIR_B,
2421	ETHTOOL_A_CABLE_PAIR_C,
2422	ETHTOOL_A_CABLE_PAIR_D,
2423	};
2424	u32 fault_length;
2425	int ret;
2426	int val;
2427
2428	val = KSZ8081_LMD_ENABLE_TEST;
2429	val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2430
2431	ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2432	if (ret < 0)
2433	return ret;
2434
2435	ret = ksz886x_cable_test_wait_for_completion(phydev);
2436	if (ret)
2437	return ret;
2438
2439	val = phy_read(phydev, LAN8814_CABLE_DIAG);
2440	if (val < 0)
2441	return val;
2442
2443	if (ksz886x_cable_test_failed(status: val, LAN8814_CABLE_DIAG_STAT_MASK))
2444	return -EAGAIN;
2445
2446	ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
2447	result: ksz886x_cable_test_result_trans(status: val,
2448	LAN8814_CABLE_DIAG_STAT_MASK
2449	));
2450	if (ret)
2451	return ret;
2452
2453	if (!ksz886x_cable_test_fault_length_valid(status: val, LAN8814_CABLE_DIAG_STAT_MASK))
2454	return 0;
2455
2456	fault_length = ksz886x_cable_test_fault_length(phydev, status: val,
2457	LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2458
2459	return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length);
2460	}
2461
2462	static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2463	{
2464	static const int ethtool_pair[] = {
2465	ETHTOOL_A_CABLE_PAIR_A,
2466	ETHTOOL_A_CABLE_PAIR_B,
2467	};
2468	int ret, val, mdix;
2469	u32 fault_length;
2470
2471	/* There is no way to choice the pair, like we do one ksz9031.
2472	* We can workaround this limitation by using the MDI-X functionality.
2473	*/
2474	if (pair == 0)
2475	mdix = ETH_TP_MDI;
2476	else
2477	mdix = ETH_TP_MDI_X;
2478
2479	switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2480	case PHY_ID_KSZ8081:
2481	ret = ksz8081_config_mdix(phydev, ctrl: mdix);
2482	break;
2483	case PHY_ID_KSZ886X:
2484	ret = ksz886x_config_mdix(phydev, ctrl: mdix);
2485	break;
2486	default:
2487	ret = -ENODEV;
2488	}
2489
2490	if (ret)
2491	return ret;
2492
2493	/* Now we are ready to fire. This command will send a 100ns pulse
2494	* to the pair.
2495	*/
2496	ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2497	if (ret)
2498	return ret;
2499
2500	ret = ksz886x_cable_test_wait_for_completion(phydev);
2501	if (ret)
2502	return ret;
2503
2504	val = phy_read(phydev, KSZ8081_LMD);
2505	if (val < 0)
2506	return val;
2507
2508	if (ksz886x_cable_test_failed(status: val, KSZ8081_LMD_STAT_MASK))
2509	return -EAGAIN;
2510
2511	ret = ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
2512	result: ksz886x_cable_test_result_trans(status: val, KSZ8081_LMD_STAT_MASK));
2513	if (ret)
2514	return ret;
2515
2516	if (!ksz886x_cable_test_fault_length_valid(status: val, KSZ8081_LMD_STAT_MASK))
2517	return 0;
2518
2519	fault_length = ksz886x_cable_test_fault_length(phydev, status: val, KSZ8081_LMD_DELTA_TIME_MASK);
2520
2521	return ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair], cm: fault_length);
2522	}
2523
2524	static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2525	bool *finished)
2526	{
2527	const struct kszphy_type *type = phydev->drv->driver_data;
2528	unsigned long pair_mask = type->pair_mask;
2529	int retries = 20;
2530	int ret = 0;
2531	int pair;
2532
2533	*finished = false;
2534
2535	/* Try harder if link partner is active */
2536	while (pair_mask && retries--) {
2537	for_each_set_bit(pair, &pair_mask, 4) {
2538	if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2539	ret = lan8814_cable_test_one_pair(phydev, pair);
2540	else
2541	ret = ksz886x_cable_test_one_pair(phydev, pair);
2542	if (ret == -EAGAIN)
2543	continue;
2544	if (ret < 0)
2545	return ret;
2546	clear_bit(nr: pair, addr: &pair_mask);
2547	}
2548	/* If link partner is in autonegotiation mode it will send 2ms
2549	* of FLPs with at least 6ms of silence.
2550	* Add 2ms sleep to have better chances to hit this silence.
2551	*/
2552	if (pair_mask)
2553	msleep(msecs: 2);
2554	}
2555
2556	*finished = true;
2557
2558	return ret;
2559	}
2560
2561	#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2562	#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2563	#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2564
2565	#define LAN8814_QSGMII_SOFT_RESET 0x43
2566	#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2567	#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2568	#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2569	#define LAN8814_ALIGN_SWAP 0x4a
2570	#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2571	#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2572
2573	#define LAN8804_ALIGN_SWAP 0x4a
2574	#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2575	#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2576	#define LAN8814_CLOCK_MANAGEMENT 0xd
2577	#define LAN8814_LINK_QUALITY 0x8e
2578
2579	static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2580	{
2581	int data;
2582
2583	phy_lock_mdio_bus(phydev);
2584	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page);
2585	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr);
2586	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2587	val: (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2588	data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2589	phy_unlock_mdio_bus(phydev);
2590
2591	return data;
2592	}
2593
2594	static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2595	u16 val)
2596	{
2597	phy_lock_mdio_bus(phydev);
2598	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, val: page);
2599	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val: addr);
2600	__phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2601	val: page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2602
2603	val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2604	if (val != 0)
2605	phydev_err(phydev, "Error: phy_write has returned error %d\n",
2606	val);
2607	phy_unlock_mdio_bus(phydev);
2608	return val;
2609	}
2610
2611	static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2612	{
2613	u16 val = 0;
2614
2615	if (enable)
2616	val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2617	PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2618	PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2619	PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2620
2621	return lanphy_write_page_reg(phydev, page: 5, PTP_TSU_INT_EN, val);
2622	}
2623
2624	static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2625	u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2626	{
2627	*seconds = lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_SEC_HI);
2628	*seconds = (*seconds << 16) |
2629	lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_SEC_LO);
2630
2631	*nano_seconds = lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_NS_HI);
2632	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2633	lanphy_read_page_reg(phydev, page: 5, PTP_RX_INGRESS_NS_LO);
2634
2635	*seq_id = lanphy_read_page_reg(phydev, page: 5, PTP_RX_MSG_HEADER2);
2636	}
2637
2638	static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2639	u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2640	{
2641	*seconds = lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_SEC_HI);
2642	*seconds = *seconds << 16 |
2643	lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_SEC_LO);
2644
2645	*nano_seconds = lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_NS_HI);
2646	*nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2647	lanphy_read_page_reg(phydev, page: 5, PTP_TX_EGRESS_NS_LO);
2648
2649	*seq_id = lanphy_read_page_reg(phydev, page: 5, PTP_TX_MSG_HEADER2);
2650	}
2651
2652	static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)
2653	{
2654	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2655	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev: ptp_priv->phydev);
2656
2657	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2658	SOF_TIMESTAMPING_RX_HARDWARE |
2659	SOF_TIMESTAMPING_RAW_HARDWARE;
2660
2661	info->phc_index = ptp_clock_index(ptp: shared->ptp_clock);
2662
2663	info->tx_types =
2664	(1 << HWTSTAMP_TX_OFF) |
2665	(1 << HWTSTAMP_TX_ON) |
2666	(1 << HWTSTAMP_TX_ONESTEP_SYNC);
2667
2668	info->rx_filters =
2669	(1 << HWTSTAMP_FILTER_NONE) |
2670	(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2671	(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2672	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2673	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2674
2675	return 0;
2676	}
2677
2678	static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2679	{
2680	int i;
2681
2682	for (i = 0; i < FIFO_SIZE; ++i)
2683	lanphy_read_page_reg(phydev, page: 5,
2684	addr: egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2685
2686	/* Read to clear overflow status bit */
2687	lanphy_read_page_reg(phydev, page: 5, PTP_TSU_INT_STS);
2688	}
2689
2690	static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2691	struct kernel_hwtstamp_config *config,
2692	struct netlink_ext_ack *extack)
2693	{
2694	struct kszphy_ptp_priv *ptp_priv =
2695	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2696	struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2697	int txcfg = 0, rxcfg = 0;
2698	int pkt_ts_enable;
2699	int tx_mod;
2700
2701	ptp_priv->hwts_tx_type = config->tx_type;
2702	ptp_priv->rx_filter = config->rx_filter;
2703
2704	switch (config->rx_filter) {
2705	case HWTSTAMP_FILTER_NONE:
2706	ptp_priv->layer = 0;
2707	ptp_priv->version = 0;
2708	break;
2709	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2710	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2711	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2712	ptp_priv->layer = PTP_CLASS_L4;
2713	ptp_priv->version = PTP_CLASS_V2;
2714	break;
2715	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2716	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2717	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2718	ptp_priv->layer = PTP_CLASS_L2;
2719	ptp_priv->version = PTP_CLASS_V2;
2720	break;
2721	case HWTSTAMP_FILTER_PTP_V2_EVENT:
2722	case HWTSTAMP_FILTER_PTP_V2_SYNC:
2723	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2724	ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2725	ptp_priv->version = PTP_CLASS_V2;
2726	break;
2727	default:
2728	return -ERANGE;
2729	}
2730
2731	if (ptp_priv->layer & PTP_CLASS_L2) {
2732	rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2733	txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2734	} else if (ptp_priv->layer & PTP_CLASS_L4) {
2735	rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2736	txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2737	}
2738	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_RX_PARSE_CONFIG, val: rxcfg);
2739	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_PARSE_CONFIG, val: txcfg);
2740
2741	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2742	PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2743	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable);
2744	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable);
2745
2746	tx_mod = lanphy_read_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_MOD);
2747	if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2748	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_MOD,
2749	val: tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2750	} else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2751	lanphy_write_page_reg(phydev: ptp_priv->phydev, page: 5, PTP_TX_MOD,
2752	val: tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2753	}
2754
2755	if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2756	lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: true);
2757	else
2758	lan8814_config_ts_intr(phydev: ptp_priv->phydev, enable: false);
2759
2760	/* In case of multiple starts and stops, these needs to be cleared */
2761	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2762	list_del(entry: &rx_ts->list);
2763	kfree(objp: rx_ts);
2764	}
2765	skb_queue_purge(list: &ptp_priv->rx_queue);
2766	skb_queue_purge(list: &ptp_priv->tx_queue);
2767
2768	lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: false);
2769	lan8814_flush_fifo(phydev: ptp_priv->phydev, egress: true);
2770
2771	return 0;
2772	}
2773
2774	static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2775	struct sk_buff *skb, int type)
2776	{
2777	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2778
2779	switch (ptp_priv->hwts_tx_type) {
2780	case HWTSTAMP_TX_ONESTEP_SYNC:
2781	if (ptp_msg_is_sync(skb, type)) {
2782	kfree_skb(skb);
2783	return;
2784	}
2785	fallthrough;
2786	case HWTSTAMP_TX_ON:
2787	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2788	skb_queue_tail(list: &ptp_priv->tx_queue, newsk: skb);
2789	break;
2790	case HWTSTAMP_TX_OFF:
2791	default:
2792	kfree_skb(skb);
2793	break;
2794	}
2795	}
2796
2797	static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2798	{
2799	struct ptp_header *ptp_header;
2800	u32 type;
2801
2802	skb_push(skb, ETH_HLEN);
2803	type = ptp_classify_raw(skb);
2804	ptp_header = ptp_parse_header(skb, type);
2805	skb_pull_inline(skb, ETH_HLEN);
2806
2807	if (!ptp_header)
2808	return false;
2809
2810	*sig = (__force u16)(ntohs(ptp_header->sequence_id));
2811	return true;
2812	}
2813
2814	static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2815	struct sk_buff *skb)
2816	{
2817	struct skb_shared_hwtstamps *shhwtstamps;
2818	struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2819	unsigned long flags;
2820	bool ret = false;
2821	u16 skb_sig;
2822
2823	if (!lan8814_get_sig_rx(skb, sig: &skb_sig))
2824	return ret;
2825
2826	/* Iterate over all RX timestamps and match it with the received skbs */
2827	spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2828	list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2829	/* Check if we found the signature we were looking for. */
2830	if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id)))
2831	continue;
2832
2833	shhwtstamps = skb_hwtstamps(skb);
2834	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2835	shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds,
2836	nsecs: rx_ts->nsec);
2837	list_del(entry: &rx_ts->list);
2838	kfree(objp: rx_ts);
2839
2840	ret = true;
2841	break;
2842	}
2843	spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags);
2844
2845	if (ret)
2846	netif_rx(skb);
2847	return ret;
2848	}
2849
2850	static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2851	{
2852	struct kszphy_ptp_priv *ptp_priv =
2853	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2854
2855	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2856	type == PTP_CLASS_NONE)
2857	return false;
2858
2859	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2860	return false;
2861
2862	/* If we failed to match then add it to the queue for when the timestamp
2863	* will come
2864	*/
2865	if (!lan8814_match_rx_skb(ptp_priv, skb))
2866	skb_queue_tail(list: &ptp_priv->rx_queue, newsk: skb);
2867
2868	return true;
2869	}
2870
2871	static void lan8814_ptp_clock_set(struct phy_device *phydev,
2872	time64_t sec, u32 nsec)
2873	{
2874	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
2875	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
2876	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
2877	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
2878	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
2879
2880	lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2881	}
2882
2883	static void lan8814_ptp_clock_get(struct phy_device *phydev,
2884	time64_t *sec, u32 *nsec)
2885	{
2886	lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2887
2888	*sec = lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_SEC_HI);
2889	*sec <<= 16;
2890	*sec |= lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_SEC_MID);
2891	*sec <<= 16;
2892	*sec |= lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_SEC_LO);
2893
2894	*nsec = lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_NS_HI);
2895	*nsec <<= 16;
2896	*nsec |= lanphy_read_page_reg(phydev, page: 4, PTP_CLOCK_READ_NS_LO);
2897	}
2898
2899	static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2900	struct timespec64 *ts)
2901	{
2902	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2903	ptp_clock_info);
2904	struct phy_device *phydev = shared->phydev;
2905	u32 nano_seconds;
2906	time64_t seconds;
2907
2908	mutex_lock(&shared->shared_lock);
2909	lan8814_ptp_clock_get(phydev, sec: &seconds, nsec: &nano_seconds);
2910	mutex_unlock(lock: &shared->shared_lock);
2911	ts->tv_sec = seconds;
2912	ts->tv_nsec = nano_seconds;
2913
2914	return 0;
2915	}
2916
2917	static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2918	const struct timespec64 *ts)
2919	{
2920	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2921	ptp_clock_info);
2922	struct phy_device *phydev = shared->phydev;
2923
2924	mutex_lock(&shared->shared_lock);
2925	lan8814_ptp_clock_set(phydev, sec: ts->tv_sec, nsec: ts->tv_nsec);
2926	mutex_unlock(lock: &shared->shared_lock);
2927
2928	return 0;
2929	}
2930
2931	static void lan8814_ptp_set_target(struct phy_device *phydev, int event,
2932	s64 start_sec, u32 start_nsec)
2933	{
2934	/* Set the start time */
2935	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
2936	lower_16_bits(start_sec));
2937	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
2938	upper_16_bits(start_sec));
2939
2940	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
2941	lower_16_bits(start_nsec));
2942	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
2943	upper_16_bits(start_nsec) & 0x3fff);
2944	}
2945
2946	static void lan8814_ptp_update_target(struct phy_device *phydev, time64_t sec)
2947	{
2948	lan8814_ptp_set_target(phydev, LAN8814_EVENT_A,
2949	start_sec: sec + LAN8814_BUFFER_TIME, start_nsec: 0);
2950	lan8814_ptp_set_target(phydev, LAN8814_EVENT_B,
2951	start_sec: sec + LAN8814_BUFFER_TIME, start_nsec: 0);
2952	}
2953
2954	static void lan8814_ptp_clock_step(struct phy_device *phydev,
2955	s64 time_step_ns)
2956	{
2957	u32 nano_seconds_step;
2958	u64 abs_time_step_ns;
2959	time64_t set_seconds;
2960	u32 nano_seconds;
2961	u32 remainder;
2962	s32 seconds;
2963
2964	if (time_step_ns > 15000000000LL) {
2965	/* convert to clock set */
2966	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nano_seconds);
2967	set_seconds += div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL,
2968	remainder: &remainder);
2969	nano_seconds += remainder;
2970	if (nano_seconds >= 1000000000) {
2971	set_seconds++;
2972	nano_seconds -= 1000000000;
2973	}
2974	lan8814_ptp_clock_set(phydev, sec: set_seconds, nsec: nano_seconds);
2975	lan8814_ptp_update_target(phydev, sec: set_seconds);
2976	return;
2977	} else if (time_step_ns < -15000000000LL) {
2978	/* convert to clock set */
2979	time_step_ns = -time_step_ns;
2980
2981	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nano_seconds);
2982	set_seconds -= div_u64_rem(dividend: time_step_ns, divisor: 1000000000LL,
2983	remainder: &remainder);
2984	nano_seconds_step = remainder;
2985	if (nano_seconds < nano_seconds_step) {
2986	set_seconds--;
2987	nano_seconds += 1000000000;
2988	}
2989	nano_seconds -= nano_seconds_step;
2990	lan8814_ptp_clock_set(phydev, sec: set_seconds, nsec: nano_seconds);
2991	lan8814_ptp_update_target(phydev, sec: set_seconds);
2992	return;
2993	}
2994
2995	/* do clock step */
2996	if (time_step_ns >= 0) {
2997	abs_time_step_ns = (u64)time_step_ns;
2998	seconds = (s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000,
2999	remainder: &remainder);
3000	nano_seconds = remainder;
3001	} else {
3002	abs_time_step_ns = (u64)(-time_step_ns);
3003	seconds = -((s32)div_u64_rem(dividend: abs_time_step_ns, divisor: 1000000000,
3004	remainder: &remainder));
3005	nano_seconds = remainder;
3006	if (nano_seconds > 0) {
3007	/* subtracting nano seconds is not allowed
3008	* convert to subtracting from seconds,
3009	* and adding to nanoseconds
3010	*/
3011	seconds--;
3012	nano_seconds = (1000000000 - nano_seconds);
3013	}
3014	}
3015
3016	if (nano_seconds > 0) {
3017	/* add 8 ns to cover the likely normal increment */
3018	nano_seconds += 8;
3019	}
3020
3021	if (nano_seconds >= 1000000000) {
3022	/* carry into seconds */
3023	seconds++;
3024	nano_seconds -= 1000000000;
3025	}
3026
3027	while (seconds) {
3028	u32 nsec;
3029
3030	if (seconds > 0) {
3031	u32 adjustment_value = (u32)seconds;
3032	u16 adjustment_value_lo, adjustment_value_hi;
3033
3034	if (adjustment_value > 0xF)
3035	adjustment_value = 0xF;
3036
3037	adjustment_value_lo = adjustment_value & 0xffff;
3038	adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3039
3040	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO,
3041	val: adjustment_value_lo);
3042	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI,
3043	PTP_LTC_STEP_ADJ_DIR_ |
3044	adjustment_value_hi);
3045	seconds -= ((s32)adjustment_value);
3046
3047	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nsec);
3048	set_seconds -= adjustment_value;
3049	lan8814_ptp_update_target(phydev, sec: set_seconds);
3050	} else {
3051	u32 adjustment_value = (u32)(-seconds);
3052	u16 adjustment_value_lo, adjustment_value_hi;
3053
3054	if (adjustment_value > 0xF)
3055	adjustment_value = 0xF;
3056
3057	adjustment_value_lo = adjustment_value & 0xffff;
3058	adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3059
3060	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO,
3061	val: adjustment_value_lo);
3062	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI,
3063	val: adjustment_value_hi);
3064	seconds += ((s32)adjustment_value);
3065
3066	lan8814_ptp_clock_get(phydev, sec: &set_seconds, nsec: &nsec);
3067	set_seconds += adjustment_value;
3068	lan8814_ptp_update_target(phydev, sec: set_seconds);
3069	}
3070	lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL,
3071	PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3072	}
3073	if (nano_seconds) {
3074	u16 nano_seconds_lo;
3075	u16 nano_seconds_hi;
3076
3077	nano_seconds_lo = nano_seconds & 0xffff;
3078	nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
3079
3080	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_LO,
3081	val: nano_seconds_lo);
3082	lanphy_write_page_reg(phydev, page: 4, PTP_LTC_STEP_ADJ_HI,
3083	PTP_LTC_STEP_ADJ_DIR_ |
3084	nano_seconds_hi);
3085	lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL,
3086	PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
3087	}
3088	}
3089
3090	static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
3091	{
3092	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3093	ptp_clock_info);
3094	struct phy_device *phydev = shared->phydev;
3095
3096	mutex_lock(&shared->shared_lock);
3097	lan8814_ptp_clock_step(phydev, time_step_ns: delta);
3098	mutex_unlock(lock: &shared->shared_lock);
3099
3100	return 0;
3101	}
3102
3103	static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
3104	{
3105	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3106	ptp_clock_info);
3107	struct phy_device *phydev = shared->phydev;
3108	u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
3109	bool positive = true;
3110	u32 kszphy_rate_adj;
3111
3112	if (scaled_ppm < 0) {
3113	scaled_ppm = -scaled_ppm;
3114	positive = false;
3115	}
3116
3117	kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
3118	kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
3119
3120	kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
3121	kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
3122
3123	if (positive)
3124	kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
3125
3126	mutex_lock(&shared->shared_lock);
3127	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_RATE_ADJ_HI, val: kszphy_rate_adj_hi);
3128	lanphy_write_page_reg(phydev, page: 4, PTP_CLOCK_RATE_ADJ_LO, val: kszphy_rate_adj_lo);
3129	mutex_unlock(lock: &shared->shared_lock);
3130
3131	return 0;
3132	}
3133
3134	static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,
3135	s64 period_sec, u32 period_nsec)
3136	{
3137	lanphy_write_page_reg(phydev, page: 4,
3138	LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),
3139	lower_16_bits(period_sec));
3140	lanphy_write_page_reg(phydev, page: 4,
3141	LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),
3142	upper_16_bits(period_sec));
3143
3144	lanphy_write_page_reg(phydev, page: 4,
3145	LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),
3146	lower_16_bits(period_nsec));
3147	lanphy_write_page_reg(phydev, page: 4,
3148	LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),
3149	upper_16_bits(period_nsec) & 0x3fff);
3150	}
3151
3152	static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,
3153	int pulse_width)
3154	{
3155	u16 val;
3156
3157	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_PTP_GENERAL_CONFIG);
3158	/* Set the pulse width of the event */
3159	val &= ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event));
3160	/* Make sure that the target clock will be incremented each time when
3161	* local time reaches or pass it
3162	*/
3163	val |= LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width);
3164	val &= ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3165	/* Set the polarity high */
3166	val |= LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event);
3167	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_GENERAL_CONFIG, val);
3168	}
3169
3170	static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)
3171	{
3172	u16 val;
3173
3174	/* Set target to too far in the future, effectively disabling it */
3175	lan8814_ptp_set_target(phydev, event, start_sec: 0xFFFFFFFF, start_nsec: 0);
3176
3177	/* And then reload once it recheas the target */
3178	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_PTP_GENERAL_CONFIG);
3179	val |= LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event);
3180	lanphy_write_page_reg(phydev, page: 4, LAN8814_PTP_GENERAL_CONFIG, val);
3181	}
3182
3183	static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)
3184	{
3185	u16 val;
3186
3187	/* Disable gpio alternate function,
3188	* 1: select as gpio,
3189	* 0: select alt func
3190	*/
3191	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin));
3192	val |= LAN8814_GPIO_EN_BIT(pin);
3193	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin), val);
3194
3195	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin));
3196	val &= ~LAN8814_GPIO_DIR_BIT(pin);
3197	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3198
3199	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_BUF_ADDR(pin));
3200	val &= ~LAN8814_GPIO_BUF_BIT(pin);
3201	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3202	}
3203
3204	static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3205	{
3206	int val;
3207
3208	/* Set as gpio output */
3209	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin));
3210	val |= LAN8814_GPIO_DIR_BIT(pin);
3211	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3212
3213	/* Enable gpio 0:for alternate function, 1:gpio */
3214	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin));
3215	val &= ~LAN8814_GPIO_EN_BIT(pin);
3216	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin), val);
3217
3218	/* Set buffer type to push pull */
3219	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_BUF_ADDR(pin));
3220	val |= LAN8814_GPIO_BUF_BIT(pin);
3221	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3222	}
3223
3224	static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,
3225	struct ptp_clock_request *rq, int on)
3226	{
3227	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3228	ptp_clock_info);
3229	struct phy_device *phydev = shared->phydev;
3230	struct timespec64 ts_on, ts_period;
3231	s64 on_nsec, period_nsec;
3232	int pulse_width;
3233	int pin, event;
3234
3235	mutex_lock(&shared->shared_lock);
3236	event = rq->perout.index;
3237	pin = ptp_find_pin(ptp: shared->ptp_clock, func: PTP_PF_PEROUT, chan: event);
3238	if (pin < 0 || pin >= LAN8814_PTP_PEROUT_NUM) {
3239	mutex_unlock(lock: &shared->shared_lock);
3240	return -EBUSY;
3241	}
3242
3243	if (!on) {
3244	lan8814_ptp_perout_off(phydev, pin);
3245	lan8814_ptp_disable_event(phydev, event);
3246	mutex_unlock(lock: &shared->shared_lock);
3247	return 0;
3248	}
3249
3250	ts_on.tv_sec = rq->perout.on.sec;
3251	ts_on.tv_nsec = rq->perout.on.nsec;
3252	on_nsec = timespec64_to_ns(ts: &ts_on);
3253
3254	ts_period.tv_sec = rq->perout.period.sec;
3255	ts_period.tv_nsec = rq->perout.period.nsec;
3256	period_nsec = timespec64_to_ns(ts: &ts_period);
3257
3258	if (period_nsec < 200) {
3259	pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
3260	phydev_name(phydev));
3261	mutex_unlock(lock: &shared->shared_lock);
3262	return -EOPNOTSUPP;
3263	}
3264
3265	if (on_nsec >= period_nsec) {
3266	pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
3267	phydev_name(phydev));
3268	mutex_unlock(lock: &shared->shared_lock);
3269	return -EINVAL;
3270	}
3271
3272	switch (on_nsec) {
3273	case 200000000:
3274	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
3275	break;
3276	case 100000000:
3277	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
3278	break;
3279	case 50000000:
3280	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
3281	break;
3282	case 10000000:
3283	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
3284	break;
3285	case 5000000:
3286	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
3287	break;
3288	case 1000000:
3289	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
3290	break;
3291	case 500000:
3292	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
3293	break;
3294	case 100000:
3295	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
3296	break;
3297	case 50000:
3298	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
3299	break;
3300	case 10000:
3301	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
3302	break;
3303	case 5000:
3304	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
3305	break;
3306	case 1000:
3307	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
3308	break;
3309	case 500:
3310	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
3311	break;
3312	case 100:
3313	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3314	break;
3315	default:
3316	pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
3317	phydev_name(phydev));
3318	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3319	break;
3320	}
3321
3322	/* Configure to pulse every period */
3323	lan8814_ptp_enable_event(phydev, event, pulse_width);
3324	lan8814_ptp_set_target(phydev, event, start_sec: rq->perout.start.sec,
3325	start_nsec: rq->perout.start.nsec);
3326	lan8814_ptp_set_reload(phydev, event, period_sec: rq->perout.period.sec,
3327	period_nsec: rq->perout.period.nsec);
3328	lan8814_ptp_perout_on(phydev, pin);
3329	mutex_unlock(lock: &shared->shared_lock);
3330
3331	return 0;
3332	}
3333
3334	static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3335	{
3336	u16 tmp;
3337
3338	/* Set as gpio input */
3339	tmp = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin));
3340	tmp &= ~LAN8814_GPIO_DIR_BIT(pin);
3341	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin), val: tmp);
3342
3343	/* Map the pin to ltc pin 0 of the capture map registers */
3344	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_CAP_MAP_LO);
3345	tmp |= pin;
3346	lanphy_write_page_reg(phydev, page: 4, PTP_GPIO_CAP_MAP_LO, val: tmp);
3347
3348	/* Enable capture on the edges of the ltc pin */
3349	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_CAP_EN);
3350	if (flags & PTP_RISING_EDGE)
3351	tmp |= PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0);
3352	if (flags & PTP_FALLING_EDGE)
3353	tmp |= PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0);
3354	lanphy_write_page_reg(phydev, page: 4, PTP_GPIO_CAP_EN, val: tmp);
3355
3356	/* Enable interrupt top interrupt */
3357	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_COMMON_INT_ENA);
3358	tmp |= PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3359	lanphy_write_page_reg(phydev, page: 4, PTP_COMMON_INT_ENA, val: tmp);
3360	}
3361
3362	static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3363	{
3364	u16 tmp;
3365
3366	/* Set as gpio out */
3367	tmp = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin));
3368	tmp |= LAN8814_GPIO_DIR_BIT(pin);
3369	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_DIR_ADDR(pin), val: tmp);
3370
3371	/* Enable alternate, 0:for alternate function, 1:gpio */
3372	tmp = lanphy_read_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin));
3373	tmp &= ~LAN8814_GPIO_EN_BIT(pin);
3374	lanphy_write_page_reg(phydev, page: 4, LAN8814_GPIO_EN_ADDR(pin), val: tmp);
3375
3376	/* Clear the mapping of pin to registers 0 of the capture registers */
3377	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_CAP_MAP_LO);
3378	tmp &= ~GENMASK(3, 0);
3379	lanphy_write_page_reg(phydev, page: 4, PTP_GPIO_CAP_MAP_LO, val: tmp);
3380
3381	/* Disable capture on both of the edges */
3382	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_CAP_EN);
3383	tmp &= ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
3384	tmp &= ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
3385	lanphy_write_page_reg(phydev, page: 4, PTP_GPIO_CAP_EN, val: tmp);
3386
3387	/* Disable interrupt top interrupt */
3388	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_COMMON_INT_ENA);
3389	tmp &= ~PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3390	lanphy_write_page_reg(phydev, page: 4, PTP_COMMON_INT_ENA, val: tmp);
3391	}
3392
3393	static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,
3394	struct ptp_clock_request *rq, int on)
3395	{
3396	struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3397	ptp_clock_info);
3398	struct phy_device *phydev = shared->phydev;
3399	int pin;
3400
3401	pin = ptp_find_pin(ptp: shared->ptp_clock, func: PTP_PF_EXTTS,
3402	chan: rq->extts.index);
3403	if (pin == -1 || pin != LAN8814_PTP_EXTTS_NUM)
3404	return -EINVAL;
3405
3406	mutex_lock(&shared->shared_lock);
3407	if (on)
3408	lan8814_ptp_extts_on(phydev, pin, flags: rq->extts.flags);
3409	else
3410	lan8814_ptp_extts_off(phydev, pin);
3411
3412	mutex_unlock(lock: &shared->shared_lock);
3413
3414	return 0;
3415	}
3416
3417	static int lan8814_ptpci_enable(struct ptp_clock_info *ptpci,
3418	struct ptp_clock_request *rq, int on)
3419	{
3420	switch (rq->type) {
3421	case PTP_CLK_REQ_PEROUT:
3422	return lan8814_ptp_perout(ptpci, rq, on);
3423	case PTP_CLK_REQ_EXTTS:
3424	return lan8814_ptp_extts(ptpci, rq, on);
3425	default:
3426	return -EINVAL;
3427	}
3428	}
3429
3430	static int lan8814_ptpci_verify(struct ptp_clock_info *ptp, unsigned int pin,
3431	enum ptp_pin_function func, unsigned int chan)
3432	{
3433	switch (func) {
3434	case PTP_PF_NONE:
3435	case PTP_PF_PEROUT:
3436	/* Only pins 0 and 1 can generate perout signals. And for pin 0
3437	* there is only chan 0 (event A) and for pin 1 there is only
3438	* chan 1 (event B)
3439	*/
3440	if (pin >= LAN8814_PTP_PEROUT_NUM || pin != chan)
3441	return -1;
3442	break;
3443	case PTP_PF_EXTTS:
3444	if (pin != LAN8814_PTP_EXTTS_NUM)
3445	return -1;
3446	break;
3447	default:
3448	return -1;
3449	}
3450
3451	return 0;
3452	}
3453
3454	static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
3455	{
3456	struct ptp_header *ptp_header;
3457	u32 type;
3458
3459	type = ptp_classify_raw(skb);
3460	ptp_header = ptp_parse_header(skb, type);
3461
3462	if (!ptp_header)
3463	return false;
3464
3465	*sig = (__force u16)(ntohs(ptp_header->sequence_id));
3466	return true;
3467	}
3468
3469	static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
3470	u32 seconds, u32 nsec, u16 seq_id)
3471	{
3472	struct skb_shared_hwtstamps shhwtstamps;
3473	struct sk_buff *skb, *skb_tmp;
3474	unsigned long flags;
3475	bool ret = false;
3476	u16 skb_sig;
3477
3478	spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
3479	skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
3480	if (!lan8814_get_sig_tx(skb, sig: &skb_sig))
3481	continue;
3482
3483	if (memcmp(p: &skb_sig, q: &seq_id, size: sizeof(seq_id)))
3484	continue;
3485
3486	__skb_unlink(skb, list: &ptp_priv->tx_queue);
3487	ret = true;
3488	break;
3489	}
3490	spin_unlock_irqrestore(lock: &ptp_priv->tx_queue.lock, flags);
3491
3492	if (ret) {
3493	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3494	shhwtstamps.hwtstamp = ktime_set(secs: seconds, nsecs: nsec);
3495	skb_complete_tx_timestamp(skb, hwtstamps: &shhwtstamps);
3496	}
3497	}
3498
3499	static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
3500	{
3501	struct phy_device *phydev = ptp_priv->phydev;
3502	u32 seconds, nsec;
3503	u16 seq_id;
3504
3505	lan8814_ptp_tx_ts_get(phydev, seconds: &seconds, nano_seconds: &nsec, seq_id: &seq_id);
3506	lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
3507	}
3508
3509	static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3510	{
3511	struct phy_device *phydev = ptp_priv->phydev;
3512	u32 reg;
3513
3514	do {
3515	lan8814_dequeue_tx_skb(ptp_priv);
3516
3517	/* If other timestamps are available in the FIFO,
3518	* process them.
3519	*/
3520	reg = lanphy_read_page_reg(phydev, page: 5, PTP_CAP_INFO);
3521	} while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
3522	}
3523
3524	static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
3525	struct lan8814_ptp_rx_ts *rx_ts)
3526	{
3527	struct skb_shared_hwtstamps *shhwtstamps;
3528	struct sk_buff *skb, *skb_tmp;
3529	unsigned long flags;
3530	bool ret = false;
3531	u16 skb_sig;
3532
3533	spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
3534	skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
3535	if (!lan8814_get_sig_rx(skb, sig: &skb_sig))
3536	continue;
3537
3538	if (memcmp(p: &skb_sig, q: &rx_ts->seq_id, size: sizeof(rx_ts->seq_id)))
3539	continue;
3540
3541	__skb_unlink(skb, list: &ptp_priv->rx_queue);
3542
3543	ret = true;
3544	break;
3545	}
3546	spin_unlock_irqrestore(lock: &ptp_priv->rx_queue.lock, flags);
3547
3548	if (ret) {
3549	shhwtstamps = skb_hwtstamps(skb);
3550	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3551	shhwtstamps->hwtstamp = ktime_set(secs: rx_ts->seconds, nsecs: rx_ts->nsec);
3552	netif_rx(skb);
3553	}
3554
3555	return ret;
3556	}
3557
3558	static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
3559	struct lan8814_ptp_rx_ts *rx_ts)
3560	{
3561	unsigned long flags;
3562
3563	/* If we failed to match the skb add it to the queue for when
3564	* the frame will come
3565	*/
3566	if (!lan8814_match_skb(ptp_priv, rx_ts)) {
3567	spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
3568	list_add(new: &rx_ts->list, head: &ptp_priv->rx_ts_list);
3569	spin_unlock_irqrestore(lock: &ptp_priv->rx_ts_lock, flags);
3570	} else {
3571	kfree(objp: rx_ts);
3572	}
3573	}
3574
3575	static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
3576	{
3577	struct phy_device *phydev = ptp_priv->phydev;
3578	struct lan8814_ptp_rx_ts *rx_ts;
3579	u32 reg;
3580
3581	do {
3582	rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
3583	if (!rx_ts)
3584	return;
3585
3586	lan8814_ptp_rx_ts_get(phydev, seconds: &rx_ts->seconds, nano_seconds: &rx_ts->nsec,
3587	seq_id: &rx_ts->seq_id);
3588	lan8814_match_rx_ts(ptp_priv, rx_ts);
3589
3590	/* If other timestamps are available in the FIFO,
3591	* process them.
3592	*/
3593	reg = lanphy_read_page_reg(phydev, page: 5, PTP_CAP_INFO);
3594	} while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
3595	}
3596
3597	static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
3598	{
3599	struct kszphy_priv *priv = phydev->priv;
3600	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3601
3602	if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
3603	lan8814_get_tx_ts(ptp_priv);
3604
3605	if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
3606	lan8814_get_rx_ts(ptp_priv);
3607
3608	if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
3609	lan8814_flush_fifo(phydev, egress: true);
3610	skb_queue_purge(list: &ptp_priv->tx_queue);
3611	}
3612
3613	if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
3614	lan8814_flush_fifo(phydev, egress: false);
3615	skb_queue_purge(list: &ptp_priv->rx_queue);
3616	}
3617	}
3618
3619	static int lan8814_gpio_process_cap(struct lan8814_shared_priv *shared)
3620	{
3621	struct phy_device *phydev = shared->phydev;
3622	struct ptp_clock_event ptp_event = {0};
3623	unsigned long nsec;
3624	s64 sec;
3625	u16 tmp;
3626
3627	/* This is 0 because whatever was the input pin it was mapped it to
3628	* ltc gpio pin 0
3629	*/
3630	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_SEL);
3631	tmp |= PTP_GPIO_SEL_GPIO_SEL(0);
3632	lanphy_write_page_reg(phydev, page: 4, PTP_GPIO_SEL, val: tmp);
3633
3634	tmp = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_CAP_STS);
3635	if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
3636	!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))
3637	return -1;
3638
3639	if (tmp & BIT(0)) {
3640	sec = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_RE_LTC_SEC_HI_CAP);
3641	sec <<= 16;
3642	sec |= lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_RE_LTC_SEC_LO_CAP);
3643
3644	nsec = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3645	nsec <<= 16;
3646	nsec |= lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3647	} else {
3648	sec = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_FE_LTC_SEC_HI_CAP);
3649	sec <<= 16;
3650	sec |= lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_FE_LTC_SEC_LO_CAP);
3651
3652	nsec = lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3653	nsec <<= 16;
3654	nsec |= lanphy_read_page_reg(phydev, page: 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3655	}
3656
3657	ptp_event.index = 0;
3658	ptp_event.timestamp = ktime_set(secs: sec, nsecs: nsec);
3659	ptp_event.type = PTP_CLOCK_EXTTS;
3660	ptp_clock_event(ptp: shared->ptp_clock, event: &ptp_event);
3661
3662	return 0;
3663	}
3664
3665	static int lan8814_handle_gpio_interrupt(struct phy_device *phydev, u16 status)
3666	{
3667	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
3668	int ret;
3669
3670	mutex_lock(&shared->shared_lock);
3671	ret = lan8814_gpio_process_cap(shared);
3672	mutex_unlock(lock: &shared->shared_lock);
3673
3674	return ret;
3675	}
3676
3677	static int lan8804_config_init(struct phy_device *phydev)
3678	{
3679	int val;
3680
3681	/* MDI-X setting for swap A,B transmit */
3682	val = lanphy_read_page_reg(phydev, page: 2, LAN8804_ALIGN_SWAP);
3683	val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3684	val |= LAN8804_ALIGN_TX_A_B_SWAP;
3685	lanphy_write_page_reg(phydev, page: 2, LAN8804_ALIGN_SWAP, val);
3686
3687	/* Make sure that the PHY will not stop generating the clock when the
3688	* link partner goes down
3689	*/
3690	lanphy_write_page_reg(phydev, page: 31, LAN8814_CLOCK_MANAGEMENT, val: 0x27e);
3691	lanphy_read_page_reg(phydev, page: 1, LAN8814_LINK_QUALITY);
3692
3693	return 0;
3694	}
3695
3696	static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3697	{
3698	int status;
3699
3700	status = phy_read(phydev, LAN8814_INTS);
3701	if (status < 0) {
3702	phy_error(phydev);
3703	return IRQ_NONE;
3704	}
3705
3706	if (status > 0)
3707	phy_trigger_machine(phydev);
3708
3709	return IRQ_HANDLED;
3710	}
3711
3712	#define LAN8804_OUTPUT_CONTROL 25
3713	#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3714	#define LAN8804_CONTROL 31
3715	#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3716
3717	static int lan8804_config_intr(struct phy_device *phydev)
3718	{
3719	int err;
3720
3721	/* This is an internal PHY of lan966x and is not possible to change the
3722	* polarity on the GIC found in lan966x, therefore change the polarity
3723	* of the interrupt in the PHY from being active low instead of active
3724	* high.
3725	*/
3726	phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3727
3728	/* By default interrupt buffer is open-drain in which case the interrupt
3729	* can be active only low. Therefore change the interrupt buffer to be
3730	* push-pull to be able to change interrupt polarity
3731	*/
3732	phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3733	LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3734
3735	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3736	err = phy_read(phydev, LAN8814_INTS);
3737	if (err < 0)
3738	return err;
3739
3740	err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3741	if (err)
3742	return err;
3743	} else {
3744	err = phy_write(phydev, LAN8814_INTC, val: 0);
3745	if (err)
3746	return err;
3747
3748	err = phy_read(phydev, LAN8814_INTS);
3749	if (err < 0)
3750	return err;
3751	}
3752
3753	return 0;
3754	}
3755
3756	static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3757	{
3758	int ret = IRQ_NONE;
3759	int irq_status;
3760
3761	irq_status = phy_read(phydev, LAN8814_INTS);
3762	if (irq_status < 0) {
3763	phy_error(phydev);
3764	return IRQ_NONE;
3765	}
3766
3767	if (irq_status & LAN8814_INT_LINK) {
3768	phy_trigger_machine(phydev);
3769	ret = IRQ_HANDLED;
3770	}
3771
3772	while (true) {
3773	irq_status = lanphy_read_page_reg(phydev, page: 5, PTP_TSU_INT_STS);
3774	if (!irq_status)
3775	break;
3776
3777	lan8814_handle_ptp_interrupt(phydev, status: irq_status);
3778	ret = IRQ_HANDLED;
3779	}
3780
3781	if (!lan8814_handle_gpio_interrupt(phydev, status: irq_status))
3782	ret = IRQ_HANDLED;
3783
3784	return ret;
3785	}
3786
3787	static int lan8814_ack_interrupt(struct phy_device *phydev)
3788	{
3789	/* bit[12..0] int status, which is a read and clear register. */
3790	int rc;
3791
3792	rc = phy_read(phydev, LAN8814_INTS);
3793
3794	return (rc < 0) ? rc : 0;
3795	}
3796
3797	static int lan8814_config_intr(struct phy_device *phydev)
3798	{
3799	int err;
3800
3801	lanphy_write_page_reg(phydev, page: 4, LAN8814_INTR_CTRL_REG,
3802	LAN8814_INTR_CTRL_REG_POLARITY |
3803	LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3804
3805	/* enable / disable interrupts */
3806	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3807	err = lan8814_ack_interrupt(phydev);
3808	if (err)
3809	return err;
3810
3811	err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3812	} else {
3813	err = phy_write(phydev, LAN8814_INTC, val: 0);
3814	if (err)
3815	return err;
3816
3817	err = lan8814_ack_interrupt(phydev);
3818	}
3819
3820	return err;
3821	}
3822
3823	static void lan8814_ptp_init(struct phy_device *phydev)
3824	{
3825	struct kszphy_priv *priv = phydev->priv;
3826	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3827	u32 temp;
3828
3829	if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3830	!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3831	return;
3832
3833	lanphy_write_page_reg(phydev, page: 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3834
3835	temp = lanphy_read_page_reg(phydev, page: 5, PTP_TX_MOD);
3836	temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3837	lanphy_write_page_reg(phydev, page: 5, PTP_TX_MOD, val: temp);
3838
3839	temp = lanphy_read_page_reg(phydev, page: 5, PTP_RX_MOD);
3840	temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3841	lanphy_write_page_reg(phydev, page: 5, PTP_RX_MOD, val: temp);
3842
3843	lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_CONFIG, val: 0);
3844	lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_CONFIG, val: 0);
3845
3846	/* Removing default registers configs related to L2 and IP */
3847	lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_L2_ADDR_EN, val: 0);
3848	lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_L2_ADDR_EN, val: 0);
3849	lanphy_write_page_reg(phydev, page: 5, PTP_TX_PARSE_IP_ADDR_EN, val: 0);
3850	lanphy_write_page_reg(phydev, page: 5, PTP_RX_PARSE_IP_ADDR_EN, val: 0);
3851
3852	/* Disable checking for minorVersionPTP field */
3853	lanphy_write_page_reg(phydev, page: 5, PTP_RX_VERSION,
3854	PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3855	lanphy_write_page_reg(phydev, page: 5, PTP_TX_VERSION,
3856	PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3857
3858	skb_queue_head_init(list: &ptp_priv->tx_queue);
3859	skb_queue_head_init(list: &ptp_priv->rx_queue);
3860	INIT_LIST_HEAD(list: &ptp_priv->rx_ts_list);
3861	spin_lock_init(&ptp_priv->rx_ts_lock);
3862
3863	ptp_priv->phydev = phydev;
3864
3865	ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3866	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3867	ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3868	ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3869
3870	phydev->mii_ts = &ptp_priv->mii_ts;
3871
3872	/* Timestamp selected by default to keep legacy API */
3873	phydev->default_timestamp = true;
3874	}
3875
3876	static int lan8814_ptp_probe_once(struct phy_device *phydev)
3877	{
3878	struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
3879
3880	/* Initialise shared lock for clock*/
3881	mutex_init(&shared->shared_lock);
3882
3883	shared->pin_config = devm_kmalloc_array(dev: &phydev->mdio.dev,
3884	LAN8814_PTP_GPIO_NUM,
3885	size: sizeof(*shared->pin_config),
3886	GFP_KERNEL);
3887	if (!shared->pin_config)
3888	return -ENOMEM;
3889
3890	for (int i = 0; i < LAN8814_PTP_GPIO_NUM; i++) {
3891	struct ptp_pin_desc *ptp_pin = &shared->pin_config[i];
3892
3893	memset(ptp_pin, 0, sizeof(*ptp_pin));
3894	snprintf(buf: ptp_pin->name,
3895	size: sizeof(ptp_pin->name), fmt: "lan8814_ptp_pin_%02d", i);
3896	ptp_pin->index = i;
3897	ptp_pin->func = PTP_PF_NONE;
3898	}
3899
3900	shared->ptp_clock_info.owner = THIS_MODULE;
3901	snprintf(buf: shared->ptp_clock_info.name, size: 30, fmt: "%s", phydev->drv->name);
3902	shared->ptp_clock_info.max_adj = 31249999;
3903	shared->ptp_clock_info.n_alarm = 0;
3904	shared->ptp_clock_info.n_ext_ts = LAN8814_PTP_EXTTS_NUM;
3905	shared->ptp_clock_info.n_pins = LAN8814_PTP_GPIO_NUM;
3906	shared->ptp_clock_info.pps = 0;
3907	shared->ptp_clock_info.supported_extts_flags = PTP_RISING_EDGE |
3908	PTP_FALLING_EDGE |
3909	PTP_STRICT_FLAGS;
3910	shared->ptp_clock_info.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE;
3911	shared->ptp_clock_info.pin_config = shared->pin_config;
3912	shared->ptp_clock_info.n_per_out = LAN8814_PTP_PEROUT_NUM;
3913	shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3914	shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3915	shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3916	shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3917	shared->ptp_clock_info.getcrosststamp = NULL;
3918	shared->ptp_clock_info.enable = lan8814_ptpci_enable;
3919	shared->ptp_clock_info.verify = lan8814_ptpci_verify;
3920
3921	shared->ptp_clock = ptp_clock_register(info: &shared->ptp_clock_info,
3922	parent: &phydev->mdio.dev);
3923	if (IS_ERR(ptr: shared->ptp_clock)) {
3924	phydev_err(phydev, "ptp_clock_register failed %lu\n",
3925	PTR_ERR(shared->ptp_clock));
3926	return -EINVAL;
3927	}
3928
3929	/* Check if PHC support is missing at the configuration level */
3930	if (!shared->ptp_clock)
3931	return 0;
3932
3933	phydev_dbg(phydev, "successfully registered ptp clock\n");
3934
3935	shared->phydev = phydev;
3936
3937	/* The EP.4 is shared between all the PHYs in the package and also it
3938	* can be accessed by any of the PHYs
3939	*/
3940	lanphy_write_page_reg(phydev, page: 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3941	lanphy_write_page_reg(phydev, page: 4, PTP_OPERATING_MODE,
3942	PTP_OPERATING_MODE_STANDALONE_);
3943
3944	/* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */
3945	lanphy_write_page_reg(phydev, page: 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_);
3946
3947	return 0;
3948	}
3949
3950	static void lan8814_setup_led(struct phy_device *phydev, int val)
3951	{
3952	int temp;
3953
3954	temp = lanphy_read_page_reg(phydev, page: 5, LAN8814_LED_CTRL_1);
3955
3956	if (val)
3957	temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3958	else
3959	temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3960
3961	lanphy_write_page_reg(phydev, page: 5, LAN8814_LED_CTRL_1, val: temp);
3962	}
3963
3964	static int lan8814_config_init(struct phy_device *phydev)
3965	{
3966	struct kszphy_priv *lan8814 = phydev->priv;
3967	int val;
3968
3969	/* Reset the PHY */
3970	val = lanphy_read_page_reg(phydev, page: 4, LAN8814_QSGMII_SOFT_RESET);
3971	val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3972	lanphy_write_page_reg(phydev, page: 4, LAN8814_QSGMII_SOFT_RESET, val);
3973
3974	/* Disable ANEG with QSGMII PCS Host side */
3975	val = lanphy_read_page_reg(phydev, page: 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3976	val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3977	lanphy_write_page_reg(phydev, page: 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3978
3979	/* MDI-X setting for swap A,B transmit */
3980	val = lanphy_read_page_reg(phydev, page: 2, LAN8814_ALIGN_SWAP);
3981	val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3982	val |= LAN8814_ALIGN_TX_A_B_SWAP;
3983	lanphy_write_page_reg(phydev, page: 2, LAN8814_ALIGN_SWAP, val);
3984
3985	if (lan8814->led_mode >= 0)
3986	lan8814_setup_led(phydev, val: lan8814->led_mode);
3987
3988	return 0;
3989	}
3990
3991	/* It is expected that there will not be any 'lan8814_take_coma_mode'
3992	* function called in suspend. Because the GPIO line can be shared, so if one of
3993	* the phys goes back in coma mode, then all the other PHYs will go, which is
3994	* wrong.
3995	*/
3996	static int lan8814_release_coma_mode(struct phy_device *phydev)
3997	{
3998	struct gpio_desc *gpiod;
3999
4000	gpiod = devm_gpiod_get_optional(dev: &phydev->mdio.dev, con_id: "coma-mode",
4001	flags: GPIOD_OUT_HIGH_OPEN_DRAIN |
4002	GPIOD_FLAGS_BIT_NONEXCLUSIVE);
4003	if (IS_ERR(ptr: gpiod))
4004	return PTR_ERR(ptr: gpiod);
4005
4006	gpiod_set_consumer_name(desc: gpiod, name: "LAN8814 coma mode");
4007	gpiod_set_value_cansleep(desc: gpiod, value: 0);
4008
4009	return 0;
4010	}
4011
4012	static void lan8814_clear_2psp_bit(struct phy_device *phydev)
4013	{
4014	u16 val;
4015
4016	/* It was noticed that when traffic is passing through the PHY and the
4017	* cable is removed then the LED was still one even though there is no
4018	* link
4019	*/
4020	val = lanphy_read_page_reg(phydev, page: 2, LAN8814_EEE_STATE);
4021	val &= ~LAN8814_EEE_STATE_MASK2P5P;
4022	lanphy_write_page_reg(phydev, page: 2, LAN8814_EEE_STATE, val);
4023	}
4024
4025	static void lan8814_update_meas_time(struct phy_device *phydev)
4026	{
4027	u16 val;
4028
4029	/* By setting the measure time to a value of 0xb this will allow cables
4030	* longer than 100m to be used. This configuration can be used
4031	* regardless of the mode of operation of the PHY
4032	*/
4033	val = lanphy_read_page_reg(phydev, page: 1, LAN8814_PD_CONTROLS);
4034	val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;
4035	val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;
4036	lanphy_write_page_reg(phydev, page: 1, LAN8814_PD_CONTROLS, val);
4037	}
4038
4039	static int lan8814_probe(struct phy_device *phydev)
4040	{
4041	const struct kszphy_type *type = phydev->drv->driver_data;
4042	struct kszphy_priv *priv;
4043	u16 addr;
4044	int err;
4045
4046	priv = devm_kzalloc(dev: &phydev->mdio.dev, size: sizeof(*priv), GFP_KERNEL);
4047	if (!priv)
4048	return -ENOMEM;
4049
4050	phydev->priv = priv;
4051
4052	priv->type = type;
4053
4054	kszphy_parse_led_mode(phydev);
4055
4056	/* Strap-in value for PHY address, below register read gives starting
4057	* phy address value
4058	*/
4059	addr = lanphy_read_page_reg(phydev, page: 4, addr: 0) & 0x1F;
4060	devm_phy_package_join(dev: &phydev->mdio.dev, phydev,
4061	base_addr: addr, priv_size: sizeof(struct lan8814_shared_priv));
4062
4063	if (phy_package_init_once(phydev)) {
4064	err = lan8814_release_coma_mode(phydev);
4065	if (err)
4066	return err;
4067
4068	err = lan8814_ptp_probe_once(phydev);
4069	if (err)
4070	return err;
4071	}
4072
4073	lan8814_ptp_init(phydev);
4074
4075	/* Errata workarounds */
4076	lan8814_clear_2psp_bit(phydev);
4077	lan8814_update_meas_time(phydev);
4078
4079	return 0;
4080	}
4081
4082	#define LAN8841_MMD_TIMER_REG 0
4083	#define LAN8841_MMD0_REGISTER_17 17
4084	#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
4085	#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
4086	#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
4087	#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
4088	#define LAN8841_MMD_ANALOG_REG 28
4089	#define LAN8841_ANALOG_CONTROL_1 1
4090	#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
4091	#define LAN8841_ANALOG_CONTROL_10 13
4092	#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
4093	#define LAN8841_ANALOG_CONTROL_11 14
4094	#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
4095	#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
4096	#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
4097	#define LAN8841_BTRX_POWER_DOWN 70
4098	#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
4099	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
4100	#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
4101	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
4102	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
4103	#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
4104	#define LAN8841_ADC_CHANNEL_MASK 198
4105	#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
4106	#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
4107	#define LAN8841_PTP_RX_VERSION 374
4108	#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
4109	#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
4110	#define LAN8841_PTP_TX_VERSION 438
4111	#define LAN8841_PTP_CMD_CTL 256
4112	#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
4113	#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
4114	#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
4115	#define LAN8841_PTP_RX_PARSE_CONFIG 368
4116	#define LAN8841_PTP_TX_PARSE_CONFIG 432
4117	#define LAN8841_PTP_RX_MODE 381
4118	#define LAN8841_PTP_INSERT_TS_EN BIT(0)
4119	#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
4120
4121	static int lan8841_config_init(struct phy_device *phydev)
4122	{
4123	int ret;
4124
4125	ret = ksz9131_config_init(phydev);
4126	if (ret)
4127	return ret;
4128
4129	/* Initialize the HW by resetting everything */
4130	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4131	LAN8841_PTP_CMD_CTL,
4132	LAN8841_PTP_CMD_CTL_PTP_RESET,
4133	LAN8841_PTP_CMD_CTL_PTP_RESET);
4134
4135	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4136	LAN8841_PTP_CMD_CTL,
4137	LAN8841_PTP_CMD_CTL_PTP_ENABLE,
4138	LAN8841_PTP_CMD_CTL_PTP_ENABLE);
4139
4140	/* Don't process any frames */
4141	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4142	LAN8841_PTP_RX_PARSE_CONFIG, val: 0);
4143	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4144	LAN8841_PTP_TX_PARSE_CONFIG, val: 0);
4145	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4146	LAN8841_PTP_TX_PARSE_L2_ADDR_EN, val: 0);
4147	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4148	LAN8841_PTP_RX_PARSE_L2_ADDR_EN, val: 0);
4149	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4150	LAN8841_PTP_TX_PARSE_IP_ADDR_EN, val: 0);
4151	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4152	LAN8841_PTP_RX_PARSE_IP_ADDR_EN, val: 0);
4153
4154	/* Disable checking for minorVersionPTP field */
4155	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4156	LAN8841_PTP_RX_VERSION, val: 0xff00);
4157	phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4158	LAN8841_PTP_TX_VERSION, val: 0xff00);
4159
4160	/* 100BT Clause 40 improvenent errata */
4161	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4162	LAN8841_ANALOG_CONTROL_1,
4163	LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
4164	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4165	LAN8841_ANALOG_CONTROL_10,
4166	LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
4167
4168	/* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
4169	* Magnetics
4170	*/
4171	ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4172	LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
4173	if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
4174	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4175	LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
4176	LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
4177	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4178	LAN8841_BTRX_POWER_DOWN,
4179	LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
4180	LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
4181	LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
4182	LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
4183	LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
4184	LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
4185	}
4186
4187	/* LDO Adjustment errata */
4188	phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4189	LAN8841_ANALOG_CONTROL_11,
4190	LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
4191
4192	/* 100BT RGMII latency tuning errata */
4193	phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
4194	LAN8841_ADC_CHANNEL_MASK, val: 0x0);
4195	phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
4196	LAN8841_MMD0_REGISTER_17,
4197	LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
4198	LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
4199
4200	return 0;
4201	}
4202
4203	#define LAN8841_OUTPUT_CTRL 25
4204	#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
4205	#define LAN8841_INT_PTP BIT(9)
4206
4207	static int lan8841_config_intr(struct phy_device *phydev)
4208	{
4209	int err;
4210
4211	phy_modify(phydev, LAN8841_OUTPUT_CTRL,
4212	LAN8841_OUTPUT_CTRL_INT_BUFFER, set: 0);
4213
4214	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4215	err = phy_read(phydev, LAN8814_INTS);
4216	if (err < 0)
4217	return err;
4218
4219	/* Enable / disable interrupts. It is OK to enable PTP interrupt
4220	* even if it PTP is not enabled. Because the underneath blocks
4221	* will not enable the PTP so we will never get the PTP
4222	* interrupt.
4223	*/
4224	err = phy_write(phydev, LAN8814_INTC,
4225	LAN8814_INT_LINK | LAN8841_INT_PTP);
4226	} else {
4227	err = phy_write(phydev, LAN8814_INTC, val: 0);
4228	if (err)
4229	return err;
4230
4231	err = phy_read(phydev, LAN8814_INTS);
4232	if (err < 0)
4233	return err;
4234
4235	/* Getting a positive value doesn't mean that is an error, it
4236	* just indicates what was the status. Therefore make sure to
4237	* clear the value and say that there is no error.
4238	*/
4239	err = 0;
4240	}
4241
4242	return err;
4243	}
4244
4245	#define LAN8841_PTP_TX_EGRESS_SEC_LO 453
4246	#define LAN8841_PTP_TX_EGRESS_SEC_HI 452
4247	#define LAN8841_PTP_TX_EGRESS_NS_LO 451
4248	#define LAN8841_PTP_TX_EGRESS_NS_HI 450
4249	#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
4250	#define LAN8841_PTP_TX_MSG_HEADER2 455
4251
4252	static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
4253	u32 *sec, u32 *nsec, u16 *seq)
4254	{
4255	struct phy_device *phydev = ptp_priv->phydev;
4256
4257	*nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_HI);
4258	if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
4259	return false;
4260
4261	*nsec = ((*nsec & 0x3fff) << 16);
4262	*nsec = *nsec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_NS_LO);
4263
4264	*sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
4265	*sec = *sec << 16;
4266	*sec = *sec | phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
4267
4268	*seq = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2);
4269
4270	return true;
4271	}
4272
4273	static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
4274	{
4275	u32 sec, nsec;
4276	u16 seq;
4277
4278	while (lan8841_ptp_get_tx_ts(ptp_priv, sec: &sec, nsec: &nsec, seq: &seq))
4279	lan8814_match_tx_skb(ptp_priv, seconds: sec, nsec, seq_id: seq);
4280	}
4281
4282	#define LAN8841_PTP_INT_STS 259
4283	#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
4284	#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
4285	#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
4286
4287	static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
4288	{
4289	struct phy_device *phydev = ptp_priv->phydev;
4290	int i;
4291
4292	for (i = 0; i < FIFO_SIZE; ++i)
4293	phy_read_mmd(phydev, devad: 2, LAN8841_PTP_TX_MSG_HEADER2);
4294
4295	phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS);
4296	}
4297
4298	#define LAN8841_PTP_GPIO_CAP_STS 506
4299	#define LAN8841_PTP_GPIO_SEL 327
4300	#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
4301	#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
4302	#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
4303	#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
4304	#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
4305	#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
4306	#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
4307	#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
4308	#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
4309
4310	static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
4311	{
4312	struct phy_device *phydev = ptp_priv->phydev;
4313	struct ptp_clock_event ptp_event = {0};
4314	int pin, ret, tmp;
4315	s32 sec, nsec;
4316
4317	pin = ptp_find_pin_unlocked(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: 0);
4318	if (pin == -1)
4319	return;
4320
4321	tmp = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_STS);
4322	if (tmp < 0)
4323	return;
4324
4325	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL,
4326	LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
4327	if (ret)
4328	return;
4329
4330	mutex_lock(&ptp_priv->ptp_lock);
4331	if (tmp & BIT(pin)) {
4332	sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
4333	sec <<= 16;
4334	sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
4335
4336	nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
4337	nsec <<= 16;
4338	nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
4339	} else {
4340	sec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
4341	sec <<= 16;
4342	sec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
4343
4344	nsec = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
4345	nsec <<= 16;
4346	nsec |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
4347	}
4348	mutex_unlock(lock: &ptp_priv->ptp_lock);
4349	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_SEL, val: 0);
4350	if (ret)
4351	return;
4352
4353	ptp_event.index = 0;
4354	ptp_event.timestamp = ktime_set(secs: sec, nsecs: nsec);
4355	ptp_event.type = PTP_CLOCK_EXTTS;
4356	ptp_clock_event(ptp: ptp_priv->ptp_clock, event: &ptp_event);
4357	}
4358
4359	static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
4360	{
4361	struct kszphy_priv *priv = phydev->priv;
4362	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4363	u16 status;
4364
4365	do {
4366	status = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_INT_STS);
4367
4368	if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
4369	lan8841_ptp_process_tx_ts(ptp_priv);
4370
4371	if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
4372	lan8841_gpio_process_cap(ptp_priv);
4373
4374	if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
4375	lan8841_ptp_flush_fifo(ptp_priv);
4376	skb_queue_purge(list: &ptp_priv->tx_queue);
4377	}
4378
4379	} while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
4380	LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
4381	LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
4382	}
4383
4384	#define LAN8841_INTS_PTP BIT(9)
4385
4386	static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
4387	{
4388	irqreturn_t ret = IRQ_NONE;
4389	int irq_status;
4390
4391	irq_status = phy_read(phydev, LAN8814_INTS);
4392	if (irq_status < 0) {
4393	phy_error(phydev);
4394	return IRQ_NONE;
4395	}
4396
4397	if (irq_status & LAN8814_INT_LINK) {
4398	phy_trigger_machine(phydev);
4399	ret = IRQ_HANDLED;
4400	}
4401
4402	if (irq_status & LAN8841_INTS_PTP) {
4403	lan8841_handle_ptp_interrupt(phydev);
4404	ret = IRQ_HANDLED;
4405	}
4406
4407	return ret;
4408	}
4409
4410	static int lan8841_ts_info(struct mii_timestamper *mii_ts,
4411	struct kernel_ethtool_ts_info *info)
4412	{
4413	struct kszphy_ptp_priv *ptp_priv;
4414
4415	ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4416
4417	info->phc_index = ptp_priv->ptp_clock ?
4418	ptp_clock_index(ptp: ptp_priv->ptp_clock) : -1;
4419	if (info->phc_index == -1)
4420	return 0;
4421
4422	info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
4423	SOF_TIMESTAMPING_RX_HARDWARE |
4424	SOF_TIMESTAMPING_RAW_HARDWARE;
4425
4426	info->tx_types = (1 << HWTSTAMP_TX_OFF) |
4427	(1 << HWTSTAMP_TX_ON) |
4428	(1 << HWTSTAMP_TX_ONESTEP_SYNC);
4429
4430	info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
4431	(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
4432	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
4433	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
4434
4435	return 0;
4436	}
4437
4438	#define LAN8841_PTP_INT_EN 260
4439	#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
4440	#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
4441
4442	static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
4443	bool enable)
4444	{
4445	struct phy_device *phydev = ptp_priv->phydev;
4446
4447	if (enable) {
4448	/* Enable interrupts on the TX side */
4449	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
4450	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4451	LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
4452	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4453	LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
4454
4455	/* Enable the modification of the frame on RX side,
4456	* this will add the ns and 2 bits of sec in the reserved field
4457	* of the PTP header
4458	*/
4459	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4460	LAN8841_PTP_RX_MODE,
4461	LAN8841_PTP_INSERT_TS_EN |
4462	LAN8841_PTP_INSERT_TS_32BIT,
4463	LAN8841_PTP_INSERT_TS_EN |
4464	LAN8841_PTP_INSERT_TS_32BIT);
4465
4466	ptp_schedule_worker(ptp: ptp_priv->ptp_clock, delay: 0);
4467	} else {
4468	/* Disable interrupts on the TX side */
4469	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
4470	LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4471	LAN8841_PTP_INT_EN_PTP_TX_TS_EN, set: 0);
4472
4473	/* Disable modification of the RX frames */
4474	phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4475	LAN8841_PTP_RX_MODE,
4476	LAN8841_PTP_INSERT_TS_EN |
4477	LAN8841_PTP_INSERT_TS_32BIT, set: 0);
4478
4479	ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock);
4480	}
4481	}
4482
4483	#define LAN8841_PTP_RX_TIMESTAMP_EN 379
4484	#define LAN8841_PTP_TX_TIMESTAMP_EN 443
4485	#define LAN8841_PTP_TX_MOD 445
4486
4487	static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
4488	struct kernel_hwtstamp_config *config,
4489	struct netlink_ext_ack *extack)
4490	{
4491	struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4492	struct phy_device *phydev = ptp_priv->phydev;
4493	int txcfg = 0, rxcfg = 0;
4494	int pkt_ts_enable;
4495
4496	ptp_priv->hwts_tx_type = config->tx_type;
4497	ptp_priv->rx_filter = config->rx_filter;
4498
4499	switch (config->rx_filter) {
4500	case HWTSTAMP_FILTER_NONE:
4501	ptp_priv->layer = 0;
4502	ptp_priv->version = 0;
4503	break;
4504	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4505	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4506	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4507	ptp_priv->layer = PTP_CLASS_L4;
4508	ptp_priv->version = PTP_CLASS_V2;
4509	break;
4510	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4511	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4512	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4513	ptp_priv->layer = PTP_CLASS_L2;
4514	ptp_priv->version = PTP_CLASS_V2;
4515	break;
4516	case HWTSTAMP_FILTER_PTP_V2_EVENT:
4517	case HWTSTAMP_FILTER_PTP_V2_SYNC:
4518	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4519	ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
4520	ptp_priv->version = PTP_CLASS_V2;
4521	break;
4522	default:
4523	return -ERANGE;
4524	}
4525
4526	/* Setup parsing of the frames and enable the timestamping for ptp
4527	* frames
4528	*/
4529	if (ptp_priv->layer & PTP_CLASS_L2) {
4530	rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
4531	txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
4532	} else if (ptp_priv->layer & PTP_CLASS_L4) {
4533	rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
4534	txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
4535	}
4536
4537	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_PARSE_CONFIG, val: rxcfg);
4538	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_PARSE_CONFIG, val: txcfg);
4539
4540	pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
4541	PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
4542	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_RX_TIMESTAMP_EN, val: pkt_ts_enable);
4543	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_TX_TIMESTAMP_EN, val: pkt_ts_enable);
4544
4545	/* Enable / disable of the TX timestamp in the SYNC frames */
4546	phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_TX_MOD,
4547	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
4548	set: ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
4549	PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
4550
4551	/* Now enable/disable the timestamping */
4552	lan8841_ptp_enable_processing(ptp_priv,
4553	enable: config->rx_filter != HWTSTAMP_FILTER_NONE);
4554
4555	skb_queue_purge(list: &ptp_priv->tx_queue);
4556
4557	lan8841_ptp_flush_fifo(ptp_priv);
4558
4559	return 0;
4560	}
4561
4562	static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
4563	struct sk_buff *skb, int type)
4564	{
4565	struct kszphy_ptp_priv *ptp_priv =
4566	container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4567	struct ptp_header *header = ptp_parse_header(skb, type);
4568	struct skb_shared_hwtstamps *shhwtstamps;
4569	struct timespec64 ts;
4570	unsigned long flags;
4571	u32 ts_header;
4572
4573	if (!header)
4574	return false;
4575
4576	if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
4577	type == PTP_CLASS_NONE)
4578	return false;
4579
4580	if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
4581	return false;
4582
4583	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4584	ts.tv_sec = ptp_priv->seconds;
4585	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
4586	ts_header = __be32_to_cpu(header->reserved2);
4587
4588	shhwtstamps = skb_hwtstamps(skb);
4589	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4590
4591	/* Check for any wrap arounds for the second part */
4592	if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
4593	ts.tv_sec -= GENMASK(1, 0) + 1;
4594	else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
4595	ts.tv_sec += 1;
4596
4597	shhwtstamps->hwtstamp =
4598	ktime_set(secs: (ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
4599	nsecs: ts_header & GENMASK(29, 0));
4600	header->reserved2 = 0;
4601
4602	netif_rx(skb);
4603
4604	return true;
4605	}
4606
4607	#define LAN8841_EVENT_A 0
4608	#define LAN8841_EVENT_B 1
4609	#define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
4610	#define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
4611	#define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
4612	#define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
4613
4614	static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
4615	s64 sec, u32 nsec)
4616	{
4617	struct phy_device *phydev = ptp_priv->phydev;
4618	int ret;
4619
4620	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
4621	upper_16_bits(sec));
4622	if (ret)
4623	return ret;
4624
4625	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
4626	lower_16_bits(sec));
4627	if (ret)
4628	return ret;
4629
4630	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
4631	upper_16_bits(nsec));
4632	if (ret)
4633	return ret;
4634
4635	return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
4636	lower_16_bits(nsec));
4637	}
4638
4639	#define LAN8841_BUFFER_TIME 2
4640
4641	static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
4642	const struct timespec64 *ts)
4643	{
4644	return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
4645	sec: ts->tv_sec + LAN8841_BUFFER_TIME, nsec: 0);
4646	}
4647
4648	#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
4649	#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
4650	#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
4651	#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
4652
4653	static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
4654	s64 sec, u32 nsec)
4655	{
4656	struct phy_device *phydev = ptp_priv->phydev;
4657	int ret;
4658
4659	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
4660	upper_16_bits(sec));
4661	if (ret)
4662	return ret;
4663
4664	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
4665	lower_16_bits(sec));
4666	if (ret)
4667	return ret;
4668
4669	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
4670	upper_16_bits(nsec));
4671	if (ret)
4672	return ret;
4673
4674	return phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
4675	lower_16_bits(nsec));
4676	}
4677
4678	#define LAN8841_PTP_LTC_SET_SEC_HI 262
4679	#define LAN8841_PTP_LTC_SET_SEC_MID 263
4680	#define LAN8841_PTP_LTC_SET_SEC_LO 264
4681	#define LAN8841_PTP_LTC_SET_NS_HI 265
4682	#define LAN8841_PTP_LTC_SET_NS_LO 266
4683	#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
4684
4685	static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
4686	const struct timespec64 *ts)
4687	{
4688	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4689	ptp_clock_info);
4690	struct phy_device *phydev = ptp_priv->phydev;
4691	unsigned long flags;
4692	int ret;
4693
4694	/* Set the value to be stored */
4695	mutex_lock(&ptp_priv->ptp_lock);
4696	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
4697	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
4698	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
4699	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
4700	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
4701
4702	/* Set the command to load the LTC */
4703	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
4704	LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
4705	ret = lan8841_ptp_update_target(ptp_priv, ts);
4706	mutex_unlock(lock: &ptp_priv->ptp_lock);
4707
4708	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4709	ptp_priv->seconds = ts->tv_sec;
4710	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
4711
4712	return ret;
4713	}
4714
4715	#define LAN8841_PTP_LTC_RD_SEC_HI 358
4716	#define LAN8841_PTP_LTC_RD_SEC_MID 359
4717	#define LAN8841_PTP_LTC_RD_SEC_LO 360
4718	#define LAN8841_PTP_LTC_RD_NS_HI 361
4719	#define LAN8841_PTP_LTC_RD_NS_LO 362
4720	#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
4721
4722	static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
4723	struct timespec64 *ts)
4724	{
4725	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4726	ptp_clock_info);
4727	struct phy_device *phydev = ptp_priv->phydev;
4728	time64_t s;
4729	s64 ns;
4730
4731	mutex_lock(&ptp_priv->ptp_lock);
4732	/* Issue the command to read the LTC */
4733	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
4734	LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4735
4736	/* Read the LTC */
4737	s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI);
4738	s <<= 16;
4739	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID);
4740	s <<= 16;
4741	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO);
4742
4743	ns = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
4744	ns <<= 16;
4745	ns |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_NS_LO);
4746	mutex_unlock(lock: &ptp_priv->ptp_lock);
4747
4748	set_normalized_timespec64(ts, sec: s, nsec: ns);
4749	return 0;
4750	}
4751
4752	static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4753	struct timespec64 *ts)
4754	{
4755	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4756	ptp_clock_info);
4757	struct phy_device *phydev = ptp_priv->phydev;
4758	time64_t s;
4759
4760	mutex_lock(&ptp_priv->ptp_lock);
4761	/* Issue the command to read the LTC */
4762	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
4763	LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4764
4765	/* Read the LTC */
4766	s = phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_HI);
4767	s <<= 16;
4768	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_MID);
4769	s <<= 16;
4770	s |= phy_read_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RD_SEC_LO);
4771	mutex_unlock(lock: &ptp_priv->ptp_lock);
4772
4773	set_normalized_timespec64(ts, sec: s, nsec: 0);
4774	}
4775
4776	#define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4777	#define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4778	#define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4779	#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4780	#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4781
4782	static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4783	{
4784	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4785	ptp_clock_info);
4786	struct phy_device *phydev = ptp_priv->phydev;
4787	struct timespec64 ts;
4788	bool add = true;
4789	u32 nsec;
4790	s32 sec;
4791	int ret;
4792
4793	/* The HW allows up to 15 sec to adjust the time, but here we limit to
4794	* 10 sec the adjustment. The reason is, in case the adjustment is 14
4795	* sec and 999999999 nsec, then we add 8ns to compansate the actual
4796	* increment so the value can be bigger than 15 sec. Therefore limit the
4797	* possible adjustments so we will not have these corner cases
4798	*/
4799	if (delta > 10000000000LL || delta < -10000000000LL) {
4800	/* The timeadjustment is too big, so fall back using set time */
4801	u64 now;
4802
4803	ptp->gettime64(ptp, &ts);
4804
4805	now = ktime_to_ns(kt: timespec64_to_ktime(ts));
4806	ts = ns_to_timespec64(nsec: now + delta);
4807
4808	ptp->settime64(ptp, &ts);
4809	return 0;
4810	}
4811
4812	sec = div_u64_rem(dividend: delta < 0 ? -delta : delta, NSEC_PER_SEC, remainder: &nsec);
4813	if (delta < 0 && nsec != 0) {
4814	/* It is not allowed to adjust low the nsec part, therefore
4815	* subtract more from second part and add to nanosecond such
4816	* that would roll over, so the second part will increase
4817	*/
4818	sec--;
4819	nsec = NSEC_PER_SEC - nsec;
4820	}
4821
4822	/* Calculate the adjustments and the direction */
4823	if (delta < 0)
4824	add = false;
4825
4826	if (nsec > 0)
4827	/* add 8 ns to cover the likely normal increment */
4828	nsec += 8;
4829
4830	if (nsec >= NSEC_PER_SEC) {
4831	/* carry into seconds */
4832	sec++;
4833	nsec -= NSEC_PER_SEC;
4834	}
4835
4836	mutex_lock(&ptp_priv->ptp_lock);
4837	if (sec) {
4838	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO, val: sec);
4839	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4840	val: add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4841	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
4842	LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4843	}
4844
4845	if (nsec) {
4846	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4847	val: nsec & 0xffff);
4848	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4849	val: (nsec >> 16) & 0x3fff);
4850	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_CMD_CTL,
4851	LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4852	}
4853	mutex_unlock(lock: &ptp_priv->ptp_lock);
4854
4855	/* Update the target clock */
4856	ptp->gettime64(ptp, &ts);
4857	mutex_lock(&ptp_priv->ptp_lock);
4858	ret = lan8841_ptp_update_target(ptp_priv, ts: &ts);
4859	mutex_unlock(lock: &ptp_priv->ptp_lock);
4860
4861	return ret;
4862	}
4863
4864	#define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4865	#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4866	#define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4867
4868	static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4869	{
4870	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4871	ptp_clock_info);
4872	struct phy_device *phydev = ptp_priv->phydev;
4873	bool faster = true;
4874	u32 rate;
4875
4876	if (!scaled_ppm)
4877	return 0;
4878
4879	if (scaled_ppm < 0) {
4880	scaled_ppm = -scaled_ppm;
4881	faster = false;
4882	}
4883
4884	rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4885	rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4886
4887	mutex_lock(&ptp_priv->ptp_lock);
4888	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4889	val: faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4890	: upper_16_bits(rate) & 0x3fff);
4891	phy_write_mmd(phydev, devad: 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4892	mutex_unlock(lock: &ptp_priv->ptp_lock);
4893
4894	return 0;
4895	}
4896
4897	static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4898	enum ptp_pin_function func, unsigned int chan)
4899	{
4900	switch (func) {
4901	case PTP_PF_NONE:
4902	case PTP_PF_PEROUT:
4903	case PTP_PF_EXTTS:
4904	break;
4905	default:
4906	return -1;
4907	}
4908
4909	return 0;
4910	}
4911
4912	#define LAN8841_PTP_GPIO_NUM 10
4913	#define LAN8841_GPIO_EN 128
4914	#define LAN8841_GPIO_DIR 129
4915	#define LAN8841_GPIO_BUF 130
4916
4917	static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4918	{
4919	struct phy_device *phydev = ptp_priv->phydev;
4920	int ret;
4921
4922	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
4923	if (ret)
4924	return ret;
4925
4926	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin));
4927	if (ret)
4928	return ret;
4929
4930	return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
4931	}
4932
4933	static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4934	{
4935	struct phy_device *phydev = ptp_priv->phydev;
4936	int ret;
4937
4938	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
4939	if (ret)
4940	return ret;
4941
4942	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DIR, BIT(pin));
4943	if (ret)
4944	return ret;
4945
4946	return phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
4947	}
4948
4949	#define LAN8841_GPIO_DATA_SEL1 131
4950	#define LAN8841_GPIO_DATA_SEL2 132
4951	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4952	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4953	#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4954	#define LAN8841_PTP_GENERAL_CONFIG 257
4955	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4956	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4957	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4958	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4959	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4960	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4961
4962	static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4963	u8 event)
4964	{
4965	struct phy_device *phydev = ptp_priv->phydev;
4966	u16 tmp;
4967	int ret;
4968
4969	/* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4970	* pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4971	* depending on the pin, it requires to read a different register
4972	*/
4973	if (pin < 5) {
4974	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4975	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1, val: tmp);
4976	} else {
4977	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4978	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2, val: tmp);
4979	}
4980	if (ret)
4981	return ret;
4982
4983	/* Disable the event */
4984	if (event == LAN8841_EVENT_A)
4985	tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4986	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4987	else
4988	tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4989	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4990	return phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, val: tmp);
4991	}
4992
4993	static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4994	u8 event, int pulse_width)
4995	{
4996	struct phy_device *phydev = ptp_priv->phydev;
4997	u16 tmp;
4998	int ret;
4999
5000	/* Enable the event */
5001	if (event == LAN8841_EVENT_A)
5002	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG,
5003	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5004	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
5005	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5006	pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
5007	else
5008	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GENERAL_CONFIG,
5009	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5010	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
5011	LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5012	pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
5013	if (ret)
5014	return ret;
5015
5016	/* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
5017	* pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
5018	* depending on the pin, it requires to read a different register
5019	*/
5020	if (event == LAN8841_EVENT_A)
5021	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
5022	else
5023	tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
5024
5025	if (pin < 5)
5026	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL1,
5027	val: tmp << (3 * pin));
5028	else
5029	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_DATA_SEL2,
5030	val: tmp << (3 * (pin - 5)));
5031
5032	return ret;
5033	}
5034
5035	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
5036	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
5037	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
5038	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
5039	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
5040	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
5041	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
5042	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
5043	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
5044	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
5045	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
5046	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
5047	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
5048	#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
5049
5050	static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
5051	struct ptp_clock_request *rq, int on)
5052	{
5053	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5054	ptp_clock_info);
5055	struct phy_device *phydev = ptp_priv->phydev;
5056	struct timespec64 ts_on, ts_period;
5057	s64 on_nsec, period_nsec;
5058	int pulse_width;
5059	int pin;
5060	int ret;
5061
5062	pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_PEROUT, chan: rq->perout.index);
5063	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5064	return -EINVAL;
5065
5066	if (!on) {
5067	ret = lan8841_ptp_perout_off(ptp_priv, pin);
5068	if (ret)
5069	return ret;
5070
5071	return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, event: pin);
5072	}
5073
5074	ts_on.tv_sec = rq->perout.on.sec;
5075	ts_on.tv_nsec = rq->perout.on.nsec;
5076	on_nsec = timespec64_to_ns(ts: &ts_on);
5077
5078	ts_period.tv_sec = rq->perout.period.sec;
5079	ts_period.tv_nsec = rq->perout.period.nsec;
5080	period_nsec = timespec64_to_ns(ts: &ts_period);
5081
5082	if (period_nsec < 200) {
5083	pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
5084	phydev_name(phydev));
5085	return -EOPNOTSUPP;
5086	}
5087
5088	if (on_nsec >= period_nsec) {
5089	pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
5090	phydev_name(phydev));
5091	return -EINVAL;
5092	}
5093
5094	switch (on_nsec) {
5095	case 200000000:
5096	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
5097	break;
5098	case 100000000:
5099	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
5100	break;
5101	case 50000000:
5102	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
5103	break;
5104	case 10000000:
5105	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
5106	break;
5107	case 5000000:
5108	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
5109	break;
5110	case 1000000:
5111	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
5112	break;
5113	case 500000:
5114	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
5115	break;
5116	case 100000:
5117	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
5118	break;
5119	case 50000:
5120	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
5121	break;
5122	case 10000:
5123	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
5124	break;
5125	case 5000:
5126	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
5127	break;
5128	case 1000:
5129	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
5130	break;
5131	case 500:
5132	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
5133	break;
5134	case 100:
5135	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5136	break;
5137	default:
5138	pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
5139	phydev_name(phydev));
5140	pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5141	break;
5142	}
5143
5144	mutex_lock(&ptp_priv->ptp_lock);
5145	ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.start.sec,
5146	nsec: rq->perout.start.nsec);
5147	mutex_unlock(lock: &ptp_priv->ptp_lock);
5148	if (ret)
5149	return ret;
5150
5151	ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, sec: rq->perout.period.sec,
5152	nsec: rq->perout.period.nsec);
5153	if (ret)
5154	return ret;
5155
5156	ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
5157	pulse_width);
5158	if (ret)
5159	return ret;
5160
5161	ret = lan8841_ptp_perout_on(ptp_priv, pin);
5162	if (ret)
5163	lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
5164
5165	return ret;
5166	}
5167
5168	#define LAN8841_PTP_GPIO_CAP_EN 496
5169	#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
5170	#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
5171	#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
5172
5173	static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
5174	u32 flags)
5175	{
5176	struct phy_device *phydev = ptp_priv->phydev;
5177	u16 tmp = 0;
5178	int ret;
5179
5180	/* Set GPIO to be intput */
5181	ret = phy_set_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5182	if (ret)
5183	return ret;
5184
5185	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5186	if (ret)
5187	return ret;
5188
5189	/* Enable capture on the edges of the pin */
5190	if (flags & PTP_RISING_EDGE)
5191	tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
5192	if (flags & PTP_FALLING_EDGE)
5193	tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
5194	ret = phy_write_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN, val: tmp);
5195	if (ret)
5196	return ret;
5197
5198	/* Enable interrupt */
5199	return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5200	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5201	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
5202	}
5203
5204	static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
5205	{
5206	struct phy_device *phydev = ptp_priv->phydev;
5207	int ret;
5208
5209	/* Set GPIO to be output */
5210	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_EN, BIT(pin));
5211	if (ret)
5212	return ret;
5213
5214	ret = phy_clear_bits_mmd(phydev, devad: 2, LAN8841_GPIO_BUF, BIT(pin));
5215	if (ret)
5216	return ret;
5217
5218	/* Disable capture on both of the edges */
5219	ret = phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_GPIO_CAP_EN,
5220	LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
5221	LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
5222	set: 0);
5223	if (ret)
5224	return ret;
5225
5226	/* Disable interrupt */
5227	return phy_modify_mmd(phydev, devad: 2, LAN8841_PTP_INT_EN,
5228	LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5229	set: 0);
5230	}
5231
5232	static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
5233	struct ptp_clock_request *rq, int on)
5234	{
5235	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5236	ptp_clock_info);
5237	int pin;
5238	int ret;
5239
5240	/* Reject requests with unsupported flags */
5241	if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
5242	PTP_EXTTS_EDGES |
5243	PTP_STRICT_FLAGS))
5244	return -EOPNOTSUPP;
5245
5246	pin = ptp_find_pin(ptp: ptp_priv->ptp_clock, func: PTP_PF_EXTTS, chan: rq->extts.index);
5247	if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5248	return -EINVAL;
5249
5250	mutex_lock(&ptp_priv->ptp_lock);
5251	if (on)
5252	ret = lan8841_ptp_extts_on(ptp_priv, pin, flags: rq->extts.flags);
5253	else
5254	ret = lan8841_ptp_extts_off(ptp_priv, pin);
5255	mutex_unlock(lock: &ptp_priv->ptp_lock);
5256
5257	return ret;
5258	}
5259
5260	static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
5261	struct ptp_clock_request *rq, int on)
5262	{
5263	switch (rq->type) {
5264	case PTP_CLK_REQ_EXTTS:
5265	return lan8841_ptp_extts(ptp, rq, on);
5266	case PTP_CLK_REQ_PEROUT:
5267	return lan8841_ptp_perout(ptp, rq, on);
5268	default:
5269	return -EOPNOTSUPP;
5270	}
5271
5272	return 0;
5273	}
5274
5275	static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
5276	{
5277	struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5278	ptp_clock_info);
5279	struct timespec64 ts;
5280	unsigned long flags;
5281
5282	lan8841_ptp_getseconds(ptp: &ptp_priv->ptp_clock_info, ts: &ts);
5283
5284	spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5285	ptp_priv->seconds = ts.tv_sec;
5286	spin_unlock_irqrestore(lock: &ptp_priv->seconds_lock, flags);
5287
5288	return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
5289	}
5290
5291	static struct ptp_clock_info lan8841_ptp_clock_info = {
5292	.owner = THIS_MODULE,
5293	.name = "lan8841 ptp",
5294	.max_adj = 31249999,
5295	.gettime64 = lan8841_ptp_gettime64,
5296	.settime64 = lan8841_ptp_settime64,
5297	.adjtime = lan8841_ptp_adjtime,
5298	.adjfine = lan8841_ptp_adjfine,
5299	.verify = lan8841_ptp_verify,
5300	.enable = lan8841_ptp_enable,
5301	.do_aux_work = lan8841_ptp_do_aux_work,
5302	.n_per_out = LAN8841_PTP_GPIO_NUM,
5303	.n_ext_ts = LAN8841_PTP_GPIO_NUM,
5304	.n_pins = LAN8841_PTP_GPIO_NUM,
5305	.supported_perout_flags = PTP_PEROUT_DUTY_CYCLE,
5306	};
5307
5308	#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
5309	#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
5310
5311	static int lan8841_probe(struct phy_device *phydev)
5312	{
5313	struct kszphy_ptp_priv *ptp_priv;
5314	struct kszphy_priv *priv;
5315	int err;
5316
5317	err = kszphy_probe(phydev);
5318	if (err)
5319	return err;
5320
5321	if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5322	LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
5323	LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
5324	phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
5325
5326	/* Register the clock */
5327	if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
5328	return 0;
5329
5330	priv = phydev->priv;
5331	ptp_priv = &priv->ptp_priv;
5332
5333	ptp_priv->pin_config = devm_kcalloc(dev: &phydev->mdio.dev,
5334	LAN8841_PTP_GPIO_NUM,
5335	size: sizeof(*ptp_priv->pin_config),
5336	GFP_KERNEL);
5337	if (!ptp_priv->pin_config)
5338	return -ENOMEM;
5339
5340	for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
5341	struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
5342
5343	snprintf(buf: p->name, size: sizeof(p->name), fmt: "pin%d", i);
5344	p->index = i;
5345	p->func = PTP_PF_NONE;
5346	}
5347
5348	ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
5349	ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
5350	ptp_priv->ptp_clock = ptp_clock_register(info: &ptp_priv->ptp_clock_info,
5351	parent: &phydev->mdio.dev);
5352	if (IS_ERR(ptr: ptp_priv->ptp_clock)) {
5353	phydev_err(phydev, "ptp_clock_register failed: %lu\n",
5354	PTR_ERR(ptp_priv->ptp_clock));
5355	return -EINVAL;
5356	}
5357
5358	if (!ptp_priv->ptp_clock)
5359	return 0;
5360
5361	/* Initialize the SW */
5362	skb_queue_head_init(list: &ptp_priv->tx_queue);
5363	ptp_priv->phydev = phydev;
5364	mutex_init(&ptp_priv->ptp_lock);
5365	spin_lock_init(&ptp_priv->seconds_lock);
5366
5367	ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
5368	ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
5369	ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
5370	ptp_priv->mii_ts.ts_info = lan8841_ts_info;
5371
5372	phydev->mii_ts = &ptp_priv->mii_ts;
5373
5374	/* Timestamp selected by default to keep legacy API */
5375	phydev->default_timestamp = true;
5376
5377	return 0;
5378	}
5379
5380	static int lan8804_resume(struct phy_device *phydev)
5381	{
5382	return kszphy_resume(phydev);
5383	}
5384
5385	static int lan8804_suspend(struct phy_device *phydev)
5386	{
5387	return kszphy_generic_suspend(phydev);
5388	}
5389
5390	static int lan8841_resume(struct phy_device *phydev)
5391	{
5392	return kszphy_generic_resume(phydev);
5393	}
5394
5395	static int lan8841_suspend(struct phy_device *phydev)
5396	{
5397	struct kszphy_priv *priv = phydev->priv;
5398	struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
5399
5400	if (ptp_priv->ptp_clock)
5401	ptp_cancel_worker_sync(ptp: ptp_priv->ptp_clock);
5402
5403	return kszphy_generic_suspend(phydev);
5404	}
5405
5406	static struct phy_driver ksphy_driver[] = {
5407	{
5408	.phy_id = PHY_ID_KS8737,
5409	.phy_id_mask = MICREL_PHY_ID_MASK,
5410	.name = "Micrel KS8737",
5411	/* PHY_BASIC_FEATURES */
5412	.driver_data = &ks8737_type,
5413	.probe = kszphy_probe,
5414	.config_init = kszphy_config_init,
5415	.config_intr = kszphy_config_intr,
5416	.handle_interrupt = kszphy_handle_interrupt,
5417	.suspend = kszphy_suspend,
5418	.resume = kszphy_resume,
5419	}, {
5420	.phy_id = PHY_ID_KSZ8021,
5421	.phy_id_mask = 0x00ffffff,
5422	.name = "Micrel KSZ8021 or KSZ8031",
5423	/* PHY_BASIC_FEATURES */
5424	.driver_data = &ksz8021_type,
5425	.probe = kszphy_probe,
5426	.config_init = kszphy_config_init,
5427	.config_intr = kszphy_config_intr,
5428	.handle_interrupt = kszphy_handle_interrupt,
5429	.get_sset_count = kszphy_get_sset_count,
5430	.get_strings = kszphy_get_strings,
5431	.get_stats = kszphy_get_stats,
5432	.suspend = kszphy_suspend,
5433	.resume = kszphy_resume,
5434	}, {
5435	.phy_id = PHY_ID_KSZ8031,
5436	.phy_id_mask = 0x00ffffff,
5437	.name = "Micrel KSZ8031",
5438	/* PHY_BASIC_FEATURES */
5439	.driver_data = &ksz8021_type,
5440	.probe = kszphy_probe,
5441	.config_init = kszphy_config_init,
5442	.config_intr = kszphy_config_intr,
5443	.handle_interrupt = kszphy_handle_interrupt,
5444	.get_sset_count = kszphy_get_sset_count,
5445	.get_strings = kszphy_get_strings,
5446	.get_stats = kszphy_get_stats,
5447	.suspend = kszphy_suspend,
5448	.resume = kszphy_resume,
5449	}, {
5450	.phy_id = PHY_ID_KSZ8041,
5451	.phy_id_mask = MICREL_PHY_ID_MASK,
5452	.name = "Micrel KSZ8041",
5453	/* PHY_BASIC_FEATURES */
5454	.driver_data = &ksz8041_type,
5455	.probe = kszphy_probe,
5456	.config_init = ksz8041_config_init,
5457	.config_aneg = ksz8041_config_aneg,
5458	.config_intr = kszphy_config_intr,
5459	.handle_interrupt = kszphy_handle_interrupt,
5460	.get_sset_count = kszphy_get_sset_count,
5461	.get_strings = kszphy_get_strings,
5462	.get_stats = kszphy_get_stats,
5463	.suspend = ksz8041_suspend,
5464	.resume = ksz8041_resume,
5465	}, {
5466	.phy_id = PHY_ID_KSZ8041RNLI,
5467	.phy_id_mask = MICREL_PHY_ID_MASK,
5468	.name = "Micrel KSZ8041RNLI",
5469	/* PHY_BASIC_FEATURES */
5470	.driver_data = &ksz8041_type,
5471	.probe = kszphy_probe,
5472	.config_init = kszphy_config_init,
5473	.config_intr = kszphy_config_intr,
5474	.handle_interrupt = kszphy_handle_interrupt,
5475	.get_sset_count = kszphy_get_sset_count,
5476	.get_strings = kszphy_get_strings,
5477	.get_stats = kszphy_get_stats,
5478	.suspend = kszphy_suspend,
5479	.resume = kszphy_resume,
5480	}, {
5481	.name = "Micrel KSZ8051",
5482	/* PHY_BASIC_FEATURES */
5483	.driver_data = &ksz8051_type,
5484	.probe = kszphy_probe,
5485	.config_init = kszphy_config_init,
5486	.config_intr = kszphy_config_intr,
5487	.handle_interrupt = kszphy_handle_interrupt,
5488	.get_sset_count = kszphy_get_sset_count,
5489	.get_strings = kszphy_get_strings,
5490	.get_stats = kszphy_get_stats,
5491	.match_phy_device = ksz8051_match_phy_device,
5492	.suspend = kszphy_suspend,
5493	.resume = kszphy_resume,
5494	}, {
5495	.phy_id = PHY_ID_KSZ8001,
5496	.name = "Micrel KSZ8001 or KS8721",
5497	.phy_id_mask = 0x00fffffc,
5498	/* PHY_BASIC_FEATURES */
5499	.driver_data = &ksz8041_type,
5500	.probe = kszphy_probe,
5501	.config_init = kszphy_config_init,
5502	.config_intr = kszphy_config_intr,
5503	.handle_interrupt = kszphy_handle_interrupt,
5504	.get_sset_count = kszphy_get_sset_count,
5505	.get_strings = kszphy_get_strings,
5506	.get_stats = kszphy_get_stats,
5507	.suspend = kszphy_suspend,
5508	.resume = kszphy_resume,
5509	}, {
5510	.phy_id = PHY_ID_KSZ8081,
5511	.name = "Micrel KSZ8081 or KSZ8091",
5512	.phy_id_mask = MICREL_PHY_ID_MASK,
5513	.flags = PHY_POLL_CABLE_TEST,
5514	/* PHY_BASIC_FEATURES */
5515	.driver_data = &ksz8081_type,
5516	.probe = kszphy_probe,
5517	.config_init = ksz8081_config_init,
5518	.soft_reset = genphy_soft_reset,
5519	.config_aneg = ksz8081_config_aneg,
5520	.read_status = ksz8081_read_status,
5521	.config_intr = kszphy_config_intr,
5522	.handle_interrupt = kszphy_handle_interrupt,
5523	.get_sset_count = kszphy_get_sset_count,
5524	.get_strings = kszphy_get_strings,
5525	.get_stats = kszphy_get_stats,
5526	.suspend = kszphy_suspend,
5527	.resume = kszphy_resume,
5528	.cable_test_start = ksz886x_cable_test_start,
5529	.cable_test_get_status = ksz886x_cable_test_get_status,
5530	}, {
5531	.phy_id = PHY_ID_KSZ8061,
5532	.name = "Micrel KSZ8061",
5533	.phy_id_mask = MICREL_PHY_ID_MASK,
5534	/* PHY_BASIC_FEATURES */
5535	.probe = kszphy_probe,
5536	.config_init = ksz8061_config_init,
5537	.soft_reset = genphy_soft_reset,
5538	.config_intr = kszphy_config_intr,
5539	.handle_interrupt = kszphy_handle_interrupt,
5540	.suspend = ksz8061_suspend,
5541	.resume = ksz8061_resume,
5542	}, {
5543	.phy_id = PHY_ID_KSZ9021,
5544	.phy_id_mask = 0x000ffffe,
5545	.name = "Micrel KSZ9021 Gigabit PHY",
5546	/* PHY_GBIT_FEATURES */
5547	.driver_data = &ksz9021_type,
5548	.probe = kszphy_probe,
5549	.get_features = ksz9031_get_features,
5550	.config_init = ksz9021_config_init,
5551	.config_intr = kszphy_config_intr,
5552	.handle_interrupt = kszphy_handle_interrupt,
5553	.get_sset_count = kszphy_get_sset_count,
5554	.get_strings = kszphy_get_strings,
5555	.get_stats = kszphy_get_stats,
5556	.suspend = kszphy_suspend,
5557	.resume = kszphy_resume,
5558	.read_mmd = genphy_read_mmd_unsupported,
5559	.write_mmd = genphy_write_mmd_unsupported,
5560	}, {
5561	.phy_id = PHY_ID_KSZ9031,
5562	.phy_id_mask = MICREL_PHY_ID_MASK,
5563	.name = "Micrel KSZ9031 Gigabit PHY",
5564	.flags = PHY_POLL_CABLE_TEST,
5565	.driver_data = &ksz9021_type,
5566	.probe = kszphy_probe,
5567	.get_features = ksz9031_get_features,
5568	.config_init = ksz9031_config_init,
5569	.soft_reset = genphy_soft_reset,
5570	.read_status = ksz9031_read_status,
5571	.config_intr = kszphy_config_intr,
5572	.handle_interrupt = kszphy_handle_interrupt,
5573	.get_sset_count = kszphy_get_sset_count,
5574	.get_strings = kszphy_get_strings,
5575	.get_stats = kszphy_get_stats,
5576	.suspend = kszphy_suspend,
5577	.resume = kszphy_resume,
5578	.cable_test_start = ksz9x31_cable_test_start,
5579	.cable_test_get_status = ksz9x31_cable_test_get_status,
5580	.set_loopback = ksz9031_set_loopback,
5581	}, {
5582	.phy_id = PHY_ID_LAN8814,
5583	.phy_id_mask = MICREL_PHY_ID_MASK,
5584	.name = "Microchip INDY Gigabit Quad PHY",
5585	.flags = PHY_POLL_CABLE_TEST,
5586	.config_init = lan8814_config_init,
5587	.driver_data = &lan8814_type,
5588	.probe = lan8814_probe,
5589	.soft_reset = genphy_soft_reset,
5590	.read_status = ksz9031_read_status,
5591	.get_sset_count = kszphy_get_sset_count,
5592	.get_strings = kszphy_get_strings,
5593	.get_stats = kszphy_get_stats,
5594	.suspend = genphy_suspend,
5595	.resume = kszphy_resume,
5596	.config_intr = lan8814_config_intr,
5597	.handle_interrupt = lan8814_handle_interrupt,
5598	.cable_test_start = lan8814_cable_test_start,
5599	.cable_test_get_status = ksz886x_cable_test_get_status,
5600	}, {
5601	.phy_id = PHY_ID_LAN8804,
5602	.phy_id_mask = MICREL_PHY_ID_MASK,
5603	.name = "Microchip LAN966X Gigabit PHY",
5604	.config_init = lan8804_config_init,
5605	.driver_data = &ksz9021_type,
5606	.probe = kszphy_probe,
5607	.soft_reset = genphy_soft_reset,
5608	.read_status = ksz9031_read_status,
5609	.get_sset_count = kszphy_get_sset_count,
5610	.get_strings = kszphy_get_strings,
5611	.get_stats = kszphy_get_stats,
5612	.suspend = lan8804_suspend,
5613	.resume = lan8804_resume,
5614	.config_intr = lan8804_config_intr,
5615	.handle_interrupt = lan8804_handle_interrupt,
5616	}, {
5617	.phy_id = PHY_ID_LAN8841,
5618	.phy_id_mask = MICREL_PHY_ID_MASK,
5619	.name = "Microchip LAN8841 Gigabit PHY",
5620	.flags = PHY_POLL_CABLE_TEST,
5621	.driver_data = &lan8841_type,
5622	.config_init = lan8841_config_init,
5623	.probe = lan8841_probe,
5624	.soft_reset = genphy_soft_reset,
5625	.config_intr = lan8841_config_intr,
5626	.handle_interrupt = lan8841_handle_interrupt,
5627	.get_sset_count = kszphy_get_sset_count,
5628	.get_strings = kszphy_get_strings,
5629	.get_stats = kszphy_get_stats,
5630	.suspend = lan8841_suspend,
5631	.resume = lan8841_resume,
5632	.cable_test_start = lan8814_cable_test_start,
5633	.cable_test_get_status = ksz886x_cable_test_get_status,
5634	}, {
5635	.phy_id = PHY_ID_KSZ9131,
5636	.phy_id_mask = MICREL_PHY_ID_MASK,
5637	.name = "Microchip KSZ9131 Gigabit PHY",
5638	/* PHY_GBIT_FEATURES */
5639	.flags = PHY_POLL_CABLE_TEST,
5640	.driver_data = &ksz9131_type,
5641	.probe = kszphy_probe,
5642	.soft_reset = genphy_soft_reset,
5643	.config_init = ksz9131_config_init,
5644	.config_intr = kszphy_config_intr,
5645	.config_aneg = ksz9131_config_aneg,
5646	.read_status = ksz9131_read_status,
5647	.handle_interrupt = kszphy_handle_interrupt,
5648	.get_sset_count = kszphy_get_sset_count,
5649	.get_strings = kszphy_get_strings,
5650	.get_stats = kszphy_get_stats,
5651	.suspend = kszphy_suspend,
5652	.resume = kszphy_resume,
5653	.cable_test_start = ksz9x31_cable_test_start,
5654	.cable_test_get_status = ksz9x31_cable_test_get_status,
5655	.get_features = ksz9477_get_features,
5656	}, {
5657	.phy_id = PHY_ID_KSZ8873MLL,
5658	.phy_id_mask = MICREL_PHY_ID_MASK,
5659	.name = "Micrel KSZ8873MLL Switch",
5660	/* PHY_BASIC_FEATURES */
5661	.config_init = kszphy_config_init,
5662	.config_aneg = ksz8873mll_config_aneg,
5663	.read_status = ksz8873mll_read_status,
5664	.suspend = genphy_suspend,
5665	.resume = genphy_resume,
5666	}, {
5667	.phy_id = PHY_ID_KSZ886X,
5668	.phy_id_mask = MICREL_PHY_ID_MASK,
5669	.name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
5670	.driver_data = &ksz886x_type,
5671	/* PHY_BASIC_FEATURES */
5672	.flags = PHY_POLL_CABLE_TEST,
5673	.config_init = kszphy_config_init,
5674	.config_aneg = ksz886x_config_aneg,
5675	.read_status = ksz886x_read_status,
5676	.suspend = genphy_suspend,
5677	.resume = genphy_resume,
5678	.cable_test_start = ksz886x_cable_test_start,
5679	.cable_test_get_status = ksz886x_cable_test_get_status,
5680	}, {
5681	.name = "Micrel KSZ87XX Switch",
5682	/* PHY_BASIC_FEATURES */
5683	.config_init = kszphy_config_init,
5684	.match_phy_device = ksz8795_match_phy_device,
5685	.suspend = genphy_suspend,
5686	.resume = genphy_resume,
5687	}, {
5688	.phy_id = PHY_ID_KSZ9477,
5689	.phy_id_mask = MICREL_PHY_ID_MASK,
5690	.name = "Microchip KSZ9477",
5691	/* PHY_GBIT_FEATURES */
5692	.config_init = ksz9477_config_init,
5693	.config_intr = kszphy_config_intr,
5694	.handle_interrupt = kszphy_handle_interrupt,
5695	.suspend = genphy_suspend,
5696	.resume = ksz9477_resume,
5697	} };
5698
5699	module_phy_driver(ksphy_driver);
5700
5701	MODULE_DESCRIPTION("Micrel PHY driver");
5702	MODULE_AUTHOR("David J. Choi");
5703	MODULE_LICENSE("GPL");
5704
5705	static const struct mdio_device_id __maybe_unused micrel_tbl[] = {
5706	{ PHY_ID_KSZ9021, 0x000ffffe },
5707	{ PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
5708	{ PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
5709	{ PHY_ID_KSZ8001, 0x00fffffc },
5710	{ PHY_ID_KS8737, MICREL_PHY_ID_MASK },
5711	{ PHY_ID_KSZ8021, 0x00ffffff },
5712	{ PHY_ID_KSZ8031, 0x00ffffff },
5713	{ PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
5714	{ PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
5715	{ PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
5716	{ PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
5717	{ PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
5718	{ PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
5719	{ PHY_ID_KSZ9477, MICREL_PHY_ID_MASK },
5720	{ PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
5721	{ PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
5722	{ PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
5723	{ }
5724	};
5725
5726	MODULE_DEVICE_TABLE(mdio, micrel_tbl);
5727